Skip to content

Commit 1455e9a

Browse files
authored
Fix warnings due to TimeConverter change (sstsimulator#2596)
1 parent 6654316 commit 1455e9a

8 files changed

Lines changed: 9 additions & 9 deletions

File tree

src/sst/elements/balar/balarMMIO.cc

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ BalarMMIO::BalarMMIO(ComponentId_t id, Params &params) : SST::Component(id) {
6161
TimeConverter* tc = getTimeConverter(clockfreq);
6262

6363
// Bind tick function
64-
registerClock(tc, new Clock::Handler2<BalarMMIO,&BalarMMIO::clockTic>(this));
64+
registerClock(*tc, new Clock::Handler2<BalarMMIO,&BalarMMIO::clockTic>(this));
6565

6666
// Link names
6767
char* link_buffer = (char*) malloc(sizeof(char) * 256);
@@ -1732,4 +1732,4 @@ extern void SST_callback_cudaEventSynchronize_done(cudaEvent_t event) {
17321732
extern void SST_callback_kernel_done(cudaStream_t stream) {
17331733
assert(g_balarmmio_component);
17341734
g_balarmmio_component->SST_callback_event_done("Kernel_done", stream, NULL, 0);
1735-
}
1735+
}

src/sst/elements/balar/dmaEngine.cc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ DMAEngine::DMAEngine(ComponentId_t id, Params &params) : SST::Component(id) {
3838
TimeConverter* tc = getTimeConverter(clockfreq);
3939

4040
// Bind tick function
41-
registerClock(tc, new Clock::Handler2<DMAEngine,&DMAEngine::tick>(this));
41+
registerClock(*tc, new Clock::Handler2<DMAEngine,&DMAEngine::tick>(this));
4242

4343
// MMIO Memory address and size
4444
mmio_addr = params.find<uint64_t>("mmio_addr", 0);

src/sst/elements/golem/array/crossSimComputeArray.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ class CrossSimComputeArray : public ComputeArray {
5353
// Configure selfLink
5454
selfLink = configureSelfLink("Self", tc,
5555
new Event::Handler2<CrossSimComputeArray,&CrossSimComputeArray::handleSelfEvent>(this));
56-
selfLink->setDefaultTimeBase(latencyTC);
56+
selfLink->setDefaultTimeBase(*latencyTC);
5757

5858
// Allocate arrays to hold Python objects
5959
pyMatrix = new PyObject*[numArrays];

src/sst/elements/memHierarchy/coherencemgr/MESI_Directory.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ class DirectoryController : public Component {
148148
/* Turn clocks off when idle */
149149
bool clockOn;
150150
Clock::Handler<DirectoryController>* clockHandler;
151-
TimeConverter* defaultTimeBase;
151+
TimeConverter defaultTimeBase;
152152
SimTime_t lastActiveClockCycle;
153153

154154
/* Statistics counters for profiling DC */

src/sst/elements/memHierarchy/membackend/HBMpagedMultiBackend.cc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -107,7 +107,7 @@ HBMpagedMultiMemory::HBMpagedMultiMemory(ComponentId_t id, Params &params)
107107
nanoConv = getTimeConverter("1ns");
108108

109109
minAccTime = self_link->getDefaultTimeBase()->getFactor() /
110-
nanoConv->getFactor();
110+
nanoConv.getFactor();
111111

112112
const uint32_t seed = params.find<uint32_t>("seed", 1447);
113113

src/sst/elements/memHierarchy/membackend/HBMpagedMultiBackend.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -292,7 +292,7 @@ class HBMpagedMultiMemory : public HBMDRAMSimMemory {
292292
SimTime_t transferDelay;
293293
SimTime_t minAccTime;
294294
bool collectStats;
295-
TimeConverter* nanoConv;
295+
TimeConverter nanoConv;
296296

297297
void handleSelfEvent(SST::Event *event);
298298
bool quantaClock(SST::Cycle_t _cycle);

src/sst/elements/memHierarchy/membackend/pagedMultiBackend.cc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,7 @@ pagedMultiMemory::pagedMultiMemory(ComponentId_t id, Params &params) : DRAMSimMe
102102
nanoConv = getTimeConverter("1ns");
103103

104104
minAccTime = self_link->getDefaultTimeBase()->getFactor() /
105-
nanoConv->getFactor();
105+
nanoConv.getFactor();
106106

107107
const uint32_t seed = params.find<uint32_t>("seed", 1447);
108108

src/sst/elements/memHierarchy/membackend/pagedMultiBackend.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -292,7 +292,7 @@ class pagedMultiMemory : public DRAMSimMemory {
292292
SimTime_t transferDelay;
293293
SimTime_t minAccTime;
294294
bool collectStats;
295-
TimeConverter* nanoConv;
295+
TimeConverter nanoConv;
296296

297297
void handleSelfEvent(SST::Event *event);
298298
bool quantaClock(SST::Cycle_t _cycle);

0 commit comments

Comments
 (0)