From c693a46a4e2e1148807eef4dbfa28ece091601a5 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Tue, 9 Dec 2025 11:32:35 -0700 Subject: [PATCH 1/2] Move arch init from common to SoC Since the architecture is very much SoC-specific, have it perform any needed configurations. Signed-off-by: Tim Crawford --- src/app/main/main.c | 3 --- src/ec/ite/ec.c | 25 ++++++++++++++----------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/app/main/main.c b/src/app/main/main.c index d5aaf4fd9..9e48e3d57 100644 --- a/src/app/main/main.c +++ b/src/app/main/main.c @@ -17,8 +17,6 @@ #include #include #include -#include -#include #include #include #include @@ -57,7 +55,6 @@ uint8_t main_cycle = 0; void init(void) { // Must happen first - arch_init(); ec_init(); gctrl_init(); gpio_init(); diff --git a/src/ec/ite/ec.c b/src/ec/ite/ec.c index 4553e97b4..caf52ba60 100644 --- a/src/ec/ite/ec.c +++ b/src/ec/ite/ec.c @@ -1,21 +1,11 @@ // SPDX-License-Identifier: GPL-3.0-only #include +#include #include #include #include -void ec_init(void) { -#if CONFIG_EC_ITE_IT8587E - RSTS = (0b10U << 6) | BIT(2); -#else - RSTS = (0b01U << 6) | BIT(2); - - // Enable POST codes - SPCTRL1 |= BIT(7) | BIT(6) | BIT(3); -#endif -} - void ec_read_post_codes(void) { #if CONFIG_EC_ITE_IT5570E || CONFIG_EC_ITE_IT5571E while (P80H81HS & 1) { @@ -27,3 +17,16 @@ void ec_read_post_codes(void) { } #endif } + +void ec_init(void) { + arch_init(); + +#if CONFIG_EC_ITE_IT8587E + RSTS = (0b10U << 6) | BIT(2); +#else + RSTS = (0b01U << 6) | BIT(2); + + // Enable POST codes + SPCTRL1 |= BIT(7) | BIT(6) | BIT(3); +#endif +} From 90afad889fee7e2e23bd5105337be636dd390139 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Tue, 9 Dec 2025 11:17:40 -0700 Subject: [PATCH 2/2] Move GCTRL,ECPM init from common to SoC code GCTRL and ECPM are ITE system blocks. Move them out of common code. Signed-off-by: Tim Crawford --- src/app/main/Makefile.mk | 2 -- src/app/main/ecpm.c | 13 ------------- src/app/main/espi.c | 1 - src/app/main/gctrl.c | 10 ---------- src/app/main/include/app/ecpm.h | 10 ---------- src/app/main/include/app/gctrl.h | 10 ---------- src/app/main/main.c | 4 ---- src/ec/ite/ec.c | 20 ++++++++++++++++++++ 8 files changed, 20 insertions(+), 50 deletions(-) delete mode 100644 src/app/main/ecpm.c delete mode 100644 src/app/main/gctrl.c delete mode 100644 src/app/main/include/app/ecpm.h delete mode 100644 src/app/main/include/app/gctrl.h diff --git a/src/app/main/Makefile.mk b/src/app/main/Makefile.mk index 4a328311f..375cf6176 100644 --- a/src/app/main/Makefile.mk +++ b/src/app/main/Makefile.mk @@ -4,10 +4,8 @@ app-y += acpi.c app-y += battery.c app-y += config.c app-$(CONFIG_HAVE_DGPU) += dgpu.c -app-y += ecpm.c app-$(CONFIG_BUS_ESPI) += espi.c app-y += fan.c -app-y += gctrl.c app-y += kbc.c app-y += kbscan.c app-y += keymap.c diff --git a/src/app/main/ecpm.c b/src/app/main/ecpm.c deleted file mode 100644 index 165741a0f..000000000 --- a/src/app/main/ecpm.c +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-3.0-only - -#include -#include - -void ecpm_init(void) { - // Clock gate EGPC, CIR, and SWUC - CGCTRL2 |= BIT(6) | BIT(5) | BIT(4); - // Clock gate UART, SSPI, and DBGR - CGCTRL3 |= BIT(2) | BIT(1) | BIT(0); - // Clock gate CEC - CGCTRL4 |= BIT(0); -} diff --git a/src/app/main/espi.c b/src/app/main/espi.c index 70351c4a1..bd60d34c8 100644 --- a/src/app/main/espi.c +++ b/src/app/main/espi.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include <8051.h> diff --git a/src/app/main/gctrl.c b/src/app/main/gctrl.c deleted file mode 100644 index e721a4df6..000000000 --- a/src/app/main/gctrl.c +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-3.0-only - -#include - -void gctrl_init(void) { - // Set I2EC as R/W - SPCTRL1 |= 0x03; - // Set PNPCFG base address - BADRSEL = 0; -} diff --git a/src/app/main/include/app/ecpm.h b/src/app/main/include/app/ecpm.h deleted file mode 100644 index 7a1e99534..000000000 --- a/src/app/main/include/app/ecpm.h +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-3.0-only - -#ifndef _APP_ECPM_H -#define _APP_ECPM_H - -#include - -void ecpm_init(void); - -#endif // _APP_ECPM_H diff --git a/src/app/main/include/app/gctrl.h b/src/app/main/include/app/gctrl.h deleted file mode 100644 index 98f457135..000000000 --- a/src/app/main/include/app/gctrl.h +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-3.0-only - -#ifndef _APP_GCTRL_H -#define _APP_GCTRL_H - -#include - -void gctrl_init(void); - -#endif // _APP_GCTRL_H diff --git a/src/app/main/main.c b/src/app/main/main.c index 9e48e3d57..b566b34bb 100644 --- a/src/app/main/main.c +++ b/src/app/main/main.c @@ -3,9 +3,7 @@ #include #include #include -#include #include -#include #include #include #include @@ -56,14 +54,12 @@ uint8_t main_cycle = 0; void init(void) { // Must happen first ec_init(); - gctrl_init(); gpio_init(); // Can happen in any order #if CONFIG_HAVE_DGPU dgpu_init(); #endif - ecpm_init(); kbc_init(); kbled_init(); #ifdef PARALLEL_DEBUG diff --git a/src/ec/ite/ec.c b/src/ec/ite/ec.c index caf52ba60..9870378ab 100644 --- a/src/ec/ite/ec.c +++ b/src/ec/ite/ec.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -18,6 +19,22 @@ void ec_read_post_codes(void) { #endif } +static void gctrl_init(void) { + // Set I2EC as R/W + SPCTRL1 |= 0x03; + // Set PNPCFG base address + BADRSEL = 0; +} + +static void ecpm_init(void) { + // Clock gate EGPC, CIR, and SWUC + CGCTRL2 |= BIT(6) | BIT(5) | BIT(4); + // Clock gate UART, SSPI, and DBGR + CGCTRL3 |= BIT(2) | BIT(1) | BIT(0); + // Clock gate CEC + CGCTRL4 |= BIT(0); +} + void ec_init(void) { arch_init(); @@ -29,4 +46,7 @@ void ec_init(void) { // Enable POST codes SPCTRL1 |= BIT(7) | BIT(6) | BIT(3); #endif + + gctrl_init(); + ecpm_init(); }