Add decode for RISC-V "V" Vector extension

Add decode stage for RISC-V "V" Vector extension instructions from
version 1.0, excluding VXUNARY0, VRFUNARY0, VWFUNARY0, VFUNARY1,
vmv<nr>r, and VFUNARY0.

This commit focuses on the decode stage to ensure correct instructions
parsing before proceeding to the execution stage. Verification is
currently done through hand-written code.

Modify Makefile to support VLEN configuration, via make ENABLE_EXT_V=1
VLEN=<value>. The default value for VLEN is set to 128. The current
implementation only supports VLEN=128. Enabling ENABLE_EXT_V=1 will also
enable ENABLE_EXT_F=1, as vector load/ store instruction shares the same
opcode with load_fp and store_fp.

Author: vestata

Makefile

@@ -142,6 +142,16 @@ $(call set-feature, EXT_C)
 ENABLE_RV32E ?= 0
 $(call set-feature, RV32E)
 
+# Vector extension instructions
+ENABLE_EXT_V ?= 0
+$(call set-feature, EXT_V)
+VLEN ?= 128 # Default VLEN is 128
+ifeq ($(call has, EXT_V), 1)
+CFLAGS += -DVLEN=$(VLEN)
+ENABLE_EXT_F ?= 1
+$(call set-feature, EXT_F)
+endif
+
 # Control and Status Register (CSR)
 ENABLE_Zicsr ?= 1
 $(call set-feature, Zicsr)