Commit 4f05096
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Propagate location from destination alloca in
`salvageDebugInfo` is called during SIL Mem2Reg and could produce misleading debug info in the following case:
```
%a = alloc_stack $MyModel.TangentVector, var, name "self", argno 1, implicit, loc "debug2.swift":37:17 ...
...
store %b to %a : $*MyModel.TangentVector
```
Such SIL could be created as a result of inlining (where store comes from the inlined function).
Before this patch we'd end with `debug_value` instruction with variable information, but without or incorrect location.
This caused LLVM IR debug info verifier assertions when there might be another instruction with complete debug info (including location) for the same argument.
After this patch we always reuse it from destination alloca
Fixes #58660salvageDebugInfo(). (#58763)1 parent 6ac87ba commit 4f05096
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- SILOptimizer/Utils
- SIL/IR
- test/AutoDiff/compiler_crashers_fixed
3 files changed
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