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MitkoDyakovfpistm
MitkoDyakov
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fpistm
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variant: L4: add generic L433C(B-C)(T-U) and L443CC(T-U)
Note: SRAM split into 2 blocks. Anyway SRAM2 is also mapped at the end of SRAM1 offering a contiguous address space with the SRAM1. Signed-off-by: Frederic Pillon <frederic.pillon@st.com> Co-authored-by: MitkoDyakov <mitko.dqkov@gmail.com>
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‎README.md‎

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@@ -374,6 +374,9 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :----: | :-------: | ---- | :-----: | :---- |
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| :green_heart: | STM32L412K8<br>STM32L412KB<br>STM32L422KB | Generic Board | *2.0.0* | |
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| :green_heart: | STM32L432KB<br>STM32L432KC<br>STM32L442KC | Generic Board | *2.0.0* | |
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| :yellow_heart: | STM32L433CBT<br>STM32L433CCT | Generic Board | **2.1.0** | |
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| :yellow_heart: | STM32L433CBU<br>STM32L433CCU | Generic Board | **2.1.0** | |
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| :yellow_heart: | STM32L443CC<br>STM32L443CC | Generic Board | **2.1.0** | |
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| :green_heart: | STM32L433RC-P | Generic Board | *2.0.0* | |
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| :green_heart: | STM32L452RC<br>STM32L452RE<br>STM32L462RE | Generic Board | *2.0.0* | |
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| :green_heart: | STM32L452RE-P | Generic Board | *2.0.0* | |

‎boards.txt‎

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@@ -4589,6 +4589,38 @@ GenL4.menu.pnum.GENERIC_L442KCUX.build.board=GENERIC_L442KCUX
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GenL4.menu.pnum.GENERIC_L442KCUX.build.product_line=STM32L442xx
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GenL4.menu.pnum.GENERIC_L442KCUX.build.variant=STM32L4xx/L432K(B-C)U_L442KCU
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# Generic L433CBTx
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GenL4.menu.pnum.GENERIC_L433CBTX=Generic L433CBTx
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GenL4.menu.pnum.GENERIC_L433CBTX.upload.maximum_size=131072
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GenL4.menu.pnum.GENERIC_L433CBTX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L433CBTX.build.board=GENERIC_L433CBTX
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GenL4.menu.pnum.GENERIC_L433CBTX.build.product_line=STM32L433xx
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GenL4.menu.pnum.GENERIC_L433CBTX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
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# Generic L433CCTx
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GenL4.menu.pnum.GENERIC_L433CCTX=Generic L433CCTx
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GenL4.menu.pnum.GENERIC_L433CCTX.upload.maximum_size=262144
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GenL4.menu.pnum.GENERIC_L433CCTX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L433CCTX.build.board=GENERIC_L433CCTX
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GenL4.menu.pnum.GENERIC_L433CCTX.build.product_line=STM32L433xx
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GenL4.menu.pnum.GENERIC_L433CCTX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
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# Generic L433CBUx
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GenL4.menu.pnum.GENERIC_L433CBUX=Generic L433CBUx
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GenL4.menu.pnum.GENERIC_L433CBUX.upload.maximum_size=131072
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GenL4.menu.pnum.GENERIC_L433CBUX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L433CBUX.build.board=GENERIC_L433CBUX
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GenL4.menu.pnum.GENERIC_L433CBUX.build.product_line=STM32L433xx
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GenL4.menu.pnum.GENERIC_L433CBUX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
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# Generic L433CCUx
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GenL4.menu.pnum.GENERIC_L433CCUX=Generic L433CCUx
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GenL4.menu.pnum.GENERIC_L433CCUX.upload.maximum_size=262144
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GenL4.menu.pnum.GENERIC_L433CCUX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L433CCUX.build.board=GENERIC_L433CCUX
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GenL4.menu.pnum.GENERIC_L433CCUX.build.product_line=STM32L433xx
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GenL4.menu.pnum.GENERIC_L433CCUX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
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# Generic L433RCTxP
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GenL4.menu.pnum.GENERIC_L433RCTXP=Generic L433RCTxP
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GenL4.menu.pnum.GENERIC_L433RCTXP.upload.maximum_size=262144
@@ -4597,6 +4629,22 @@ GenL4.menu.pnum.GENERIC_L433RCTXP.build.board=GENERIC_L433RCTXP
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GenL4.menu.pnum.GENERIC_L433RCTXP.build.product_line=STM32L433xx
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GenL4.menu.pnum.GENERIC_L433RCTXP.build.variant=STM32L4xx/L433RCTxP
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# Generic L443CCTx
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GenL4.menu.pnum.GENERIC_L443CCTX=Generic L443CCTx
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GenL4.menu.pnum.GENERIC_L443CCTX.upload.maximum_size=262144
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GenL4.menu.pnum.GENERIC_L443CCTX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L443CCTX.build.board=GENERIC_L443CCTX
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GenL4.menu.pnum.GENERIC_L443CCTX.build.product_line=STM32L443xx
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GenL4.menu.pnum.GENERIC_L443CCTX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
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# Generic L443CCUx
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GenL4.menu.pnum.GENERIC_L443CCUX=Generic L443CCUx
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GenL4.menu.pnum.GENERIC_L443CCUX.upload.maximum_size=262144
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GenL4.menu.pnum.GENERIC_L443CCUX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L443CCUX.build.board=GENERIC_L443CCUX
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GenL4.menu.pnum.GENERIC_L443CCUX.build.product_line=STM32L443xx
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GenL4.menu.pnum.GENERIC_L443CCUX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
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# Generic L452RCIx
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GenL4.menu.pnum.GENERIC_L452RCIX=Generic L452RCIx
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GenL4.menu.pnum.GENERIC_L452RCIX.upload.maximum_size=262144

‎variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/generic_clock.c‎

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@@ -22,8 +22,57 @@
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*/
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WEAK void SystemClock_Config(void)
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{
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/* SystemClock_Config can be generated by STM32CubeMX */
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#warning "SystemClock_Config() is empty. Default clock at reset is used."
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RCC_OscInitTypeDef RCC_OscInitStruct = {};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
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/** Configure the main internal regulator output voltage
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*/
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if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
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Error_Handler();
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}
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.MSIState = RCC_MSI_ON;
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RCC_OscInitStruct.MSICalibrationValue = 0;
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RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
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RCC_OscInitStruct.PLL.PLLM = 1;
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RCC_OscInitStruct.PLL.PLLN = 40;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
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Error_Handler();
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}
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
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PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
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PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
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PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
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PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
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PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
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PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
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PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
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PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
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Error_Handler();
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}
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}
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#endif /* ARDUINO_GENERIC_* */

‎variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/ldscript.ld‎

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/*
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******************************************************************************
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**
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** @file : ldscript.ld
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**
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** @author : Auto-generated by STM32CubeIDE
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**
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** @brief : Linker script for STM32L433CCUx Device from STM32L4 series
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** 256Kbytes FLASH
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** 48Kbytes RAM
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** 16Kbytes RAM2
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**
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** Set heap size, stack size and stack location according
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** to application requirements.
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**
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** Set memory bank area and size if external memory is used
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**
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** Target : STMicroelectronics STM32
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**
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** Distribution: The file is distributed as is, without any warranty
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** of any kind.
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**
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******************************************************************************
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** @attention
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**
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** <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
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** All rights reserved.</center></h2>
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**
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** This software component is licensed by ST under BSD 3-Clause license,
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** the "License"; You may not use this file except in compliance with the
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** License. You may obtain a copy of the License at:
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** opensource.org/licenses/BSD-3-Clause
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**
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******************************************************************************
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
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_Min_Heap_Size = 0x200; /* required amount of heap */
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_Min_Stack_Size = 0x400; /* required amount of stack */
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/* Memories definition */
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MEMORY
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{
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
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FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
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}
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/* Sections */
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SECTIONS
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{
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/* The startup code into "FLASH" Rom type memory */
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.isr_vector :
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{
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. = ALIGN(4);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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} >FLASH
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/* The program code and other data into "FLASH" Rom type memory */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
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_etext = .; /* define a global symbols at end of code */
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} >FLASH
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/* Constant data into "FLASH" Rom type memory */
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.rodata :
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{
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. = ALIGN(4);
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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. = ALIGN(4);
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} >FLASH
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.ARM.extab : {
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. = ALIGN(4);
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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. = ALIGN(4);
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} >FLASH
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.ARM : {
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. = ALIGN(4);
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__exidx_start = .;
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*(.ARM.exidx*)
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__exidx_end = .;
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. = ALIGN(4);
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} >FLASH
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.preinit_array :
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{
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. = ALIGN(4);
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array*))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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} >FLASH
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.init_array :
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{
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. = ALIGN(4);
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array*))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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} >FLASH
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.fini_array :
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{
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. = ALIGN(4);
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(SORT(.fini_array.*)))
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KEEP (*(.fini_array*))
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PROVIDE_HIDDEN (__fini_array_end = .);
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. = ALIGN(4);
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} >FLASH
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/* Used by the startup to initialize data */
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_sidata = LOADADDR(.data);
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/* Initialized data sections into "RAM" Ram type memory */
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.data :
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{
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. = ALIGN(4);
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_sdata = .; /* create a global symbol at data start */
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*(.data) /* .data sections */
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*(.data*) /* .data* sections */
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*(.RamFunc) /* .RamFunc sections */
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*(.RamFunc*) /* .RamFunc* sections */
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. = ALIGN(4);
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_edata = .; /* define a global symbol at data end */
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} >RAM AT> FLASH
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/* Uninitialized data section into "RAM" Ram type memory */
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. = ALIGN(4);
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.bss :
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{
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/* This is used by the startup in order to initialize the .bss section */
156+
_sbss = .; /* define a global symbol at bss start */
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__bss_start__ = _sbss;
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*(.bss)
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .; /* define a global symbol at bss end */
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__bss_end__ = _ebss;
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} >RAM
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/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
168+
._user_heap_stack :
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{
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. = ALIGN(8);
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PROVIDE ( end = . );
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PROVIDE ( _end = . );
173+
. = . + _Min_Heap_Size;
174+
. = . + _Min_Stack_Size;
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. = ALIGN(8);
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} >RAM
177+
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/* Remove information from the compiler libraries */
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/DISCARD/ :
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{
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libc.a ( * )
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libm.a ( * )
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libgcc.a ( * )
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}
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.ARM.attributes 0 : { *(.ARM.attributes) }
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}

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