system(wl3): update STM32WL3x CMSIS Drivers to v1.3.1

fpistm · fpistm · commit a60b18f55d55 · 2025-12-05T18:11:11.000+01:00
Included in STM32CubeWL3 FW v1.3.1

Signed-off-by: Frederic Pillon &lt;frederic.pillon@st.com&gt;
diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3rx.h b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3rx.h
@@ -4042,6 +4042,7 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure  */
 /* ============================================================================================================================*/
 /*=====================                                        SPI                                        =====================*/
 /* ============================================================================================================================*/
+#define SPI_I2S_SUPPORT                       /*!< I2S support */
 
 /* =====================================================    CR1    =====================================================*/
 #define SPI_CR1_BIDIMODE_Pos                                               (15UL)        /*!<SPI CR1: BIDIMODE (Bit 15) */
@@ -4255,6 +4256,59 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure  */
 #define SPI_TXCRCR_TXCRC_14                                                (0x4000U << SPI_TXCRCR_TXCRC_Pos)
 #define SPI_TXCRCR_TXCRC_15                                                (0x8000U << SPI_TXCRCR_TXCRC_Pos)
 
+/* =====================================================    I2SCFGR    =====================================================*/
+#define SPI_I2SCFGR_ASTRTEN_Pos                                            (12UL)        /*!<SPI I2SCFGR: ASTRTEN (Bit 12) */
+#define SPI_I2SCFGR_ASTRTEN_Msk                                            (0x1000UL)        /*!< SPI I2SCFGR: ASTRTEN (Bitfield-Mask: 0x01) */
+#define SPI_I2SCFGR_ASTRTEN                                                SPI_I2SCFGR_ASTRTEN_Msk
+#define SPI_I2SCFGR_I2SMOD_Pos                                             (11UL)        /*!<SPI I2SCFGR: I2SMOD (Bit 11) */
+#define SPI_I2SCFGR_I2SMOD_Msk                                             (0x800UL)        /*!< SPI I2SCFGR: I2SMOD (Bitfield-Mask: 0x01) */
+#define SPI_I2SCFGR_I2SMOD                                                 SPI_I2SCFGR_I2SMOD_Msk
+#define SPI_I2SCFGR_I2SE_Pos                                               (10UL)        /*!<SPI I2SCFGR: I2SE (Bit 10) */
+#define SPI_I2SCFGR_I2SE_Msk                                               (0x400UL)        /*!< SPI I2SCFGR: I2SE (Bitfield-Mask: 0x01) */
+#define SPI_I2SCFGR_I2SE                                                   SPI_I2SCFGR_I2SE_Msk
+#define SPI_I2SCFGR_I2SCFG_Pos                                             (8UL)        /*!<SPI I2SCFGR: I2SCFG (Bit 8) */
+#define SPI_I2SCFGR_I2SCFG_Msk                                             (0x300UL)        /*!< SPI I2SCFGR: I2SCFG (Bitfield-Mask: 0x03) */
+#define SPI_I2SCFGR_I2SCFG                                                 SPI_I2SCFGR_I2SCFG_Msk
+#define SPI_I2SCFGR_I2SCFG_0                                               (0x1U << SPI_I2SCFGR_I2SCFG_Pos)
+#define SPI_I2SCFGR_I2SCFG_1                                               (0x2U << SPI_I2SCFGR_I2SCFG_Pos)
+#define SPI_I2SCFGR_PCMSYNC_Pos                                            (7UL)        /*!<SPI I2SCFGR: PCMSYNC (Bit 7) */
+#define SPI_I2SCFGR_PCMSYNC_Msk                                            (0x80UL)        /*!< SPI I2SCFGR: PCMSYNC (Bitfield-Mask: 0x01) */
+#define SPI_I2SCFGR_PCMSYNC                                                SPI_I2SCFGR_PCMSYNC_Msk
+#define SPI_I2SCFGR_I2SSTD_Pos                                             (4UL)        /*!<SPI I2SCFGR: I2SSTD (Bit 4) */
+#define SPI_I2SCFGR_I2SSTD_Msk                                             (0x30UL)        /*!< SPI I2SCFGR: I2SSTD (Bitfield-Mask: 0x03) */
+#define SPI_I2SCFGR_I2SSTD                                                 SPI_I2SCFGR_I2SSTD_Msk
+#define SPI_I2SCFGR_I2SSTD_0                                               (0x1U << SPI_I2SCFGR_I2SSTD_Pos)
+#define SPI_I2SCFGR_I2SSTD_1                                               (0x2U << SPI_I2SCFGR_I2SSTD_Pos)
+#define SPI_I2SCFGR_CKPOL_Pos                                              (3UL)        /*!<SPI I2SCFGR: CKPOL (Bit 3) */
+#define SPI_I2SCFGR_CKPOL_Msk                                              (0x8UL)        /*!< SPI I2SCFGR: CKPOL (Bitfield-Mask: 0x01) */
+#define SPI_I2SCFGR_CKPOL                                                  SPI_I2SCFGR_CKPOL_Msk
+#define SPI_I2SCFGR_DATLEN_Pos                                             (1UL)        /*!<SPI I2SCFGR: DATLEN (Bit 1) */
+#define SPI_I2SCFGR_DATLEN_Msk                                             (0x6UL)        /*!< SPI I2SCFGR: DATLEN (Bitfield-Mask: 0x03) */
+#define SPI_I2SCFGR_DATLEN                                                 SPI_I2SCFGR_DATLEN_Msk
+#define SPI_I2SCFGR_DATLEN_0                                               (0x1U << SPI_I2SCFGR_DATLEN_Pos)
+#define SPI_I2SCFGR_DATLEN_1                                               (0x2U << SPI_I2SCFGR_DATLEN_Pos)
+#define SPI_I2SCFGR_CHLEN_Pos                                              (0UL)        /*!<SPI I2SCFGR: CHLEN (Bit 0) */
+#define SPI_I2SCFGR_CHLEN_Msk                                              (0x1UL)        /*!< SPI I2SCFGR: CHLEN (Bitfield-Mask: 0x01) */
+#define SPI_I2SCFGR_CHLEN                                                  SPI_I2SCFGR_CHLEN_Msk
+
+/* =====================================================    I2SPR    =====================================================*/
+#define SPI_I2SPR_MCKOE_Pos                                                (9UL)        /*!<SPI I2SPR: MCKOE (Bit 9) */
+#define SPI_I2SPR_MCKOE_Msk                                                (0x200UL)        /*!< SPI I2SPR: MCKOE (Bitfield-Mask: 0x01) */
+#define SPI_I2SPR_MCKOE                                                    SPI_I2SPR_MCKOE_Msk
+#define SPI_I2SPR_ODD_Pos                                                  (8UL)        /*!<SPI I2SPR: ODD (Bit 8) */
+#define SPI_I2SPR_ODD_Msk                                                  (0x100UL)        /*!< SPI I2SPR: ODD (Bitfield-Mask: 0x01) */
+#define SPI_I2SPR_ODD                                                      SPI_I2SPR_ODD_Msk
+#define SPI_I2SPR_I2SDIV_Pos                                               (0UL)        /*!<SPI I2SPR: I2SDIV (Bit 0) */
+#define SPI_I2SPR_I2SDIV_Msk                                               (0xffUL)        /*!< SPI I2SPR: I2SDIV (Bitfield-Mask: 0xff) */
+#define SPI_I2SPR_I2SDIV                                                   SPI_I2SPR_I2SDIV_Msk
+#define SPI_I2SPR_I2SDIV_0                                                 (0x1U << SPI_I2SPR_I2SDIV_Pos)
+#define SPI_I2SPR_I2SDIV_1                                                 (0x2U << SPI_I2SPR_I2SDIV_Pos)
+#define SPI_I2SPR_I2SDIV_2                                                 (0x4U << SPI_I2SPR_I2SDIV_Pos)
+#define SPI_I2SPR_I2SDIV_3                                                 (0x8U << SPI_I2SPR_I2SDIV_Pos)
+#define SPI_I2SPR_I2SDIV_4                                                 (0x10U << SPI_I2SPR_I2SDIV_Pos)
+#define SPI_I2SPR_I2SDIV_5                                                 (0x20U << SPI_I2SPR_I2SDIV_Pos)
+#define SPI_I2SPR_I2SDIV_6                                                 (0x40U << SPI_I2SPR_I2SDIV_Pos)
+#define SPI_I2SPR_I2SDIV_7                                                 (0x80U << SPI_I2SPR_I2SDIV_Pos)
 
 
 /* ============================================================================================================================*/
@@ -11373,6 +11427,8 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure  */
 /******************************** SPI Instances *******************************/
 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI3)
 
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI3))
 
 /****************************** IWDG Instances ********************************/
 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3x.h b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3x.h
@@ -89,7 +89,7 @@
   */
 #define __STM32WL3x_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
 #define __STM32WL3x_CMSIS_VERSION_SUB1   (0x03U) /*!< [23:16] sub1 version */
-#define __STM32WL3x_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32WL3x_CMSIS_VERSION_SUB2   (0x01U) /*!< [15:8]  sub2 version */
 #define __STM32WL3x_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32WL3x_CMSIS_VERSION       ((__STM32WL3x_CMSIS_VERSION_MAIN << 24U)\
                                        |(__STM32WL3x_CMSIS_VERSION_SUB1 << 16U)\
diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Release_Notes.html
@@ -60,11 +60,35 @@ <h1 id="purpose">Purpose</h1>
 <section id="update-history" class="col-sm-12 col-lg-8">
 <h1>Update history</h1>
 <div class="collapse">
-<input type="checkbox" id="collapse-section5" checked aria-hidden="true">
+<input type="checkbox" id="collapse-section6" checked aria-hidden="true">
+<label for="collapse-section6" aria-hidden="true"> <strong>V1.3.1 /
+20-November-2025</strong> </label>
+<div>
+<h2 id="main-changes">Main Changes</h2>
+<ul>
+<li>Added missing I2S support on WL3Rx devices (stm32wl3rx.h)</li>
+</ul>
+<h2 id="known-limitations">Known Limitations</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="development-toolchains-and-compilers">Development Toolchains and
+Compilers</h2>
+<ul>
+<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
+</ul>
+<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<ul>
+<li>STM32WL3xx devices</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section5" aria-hidden="true">
 <label for="collapse-section5" aria-hidden="true"> <strong>V1.3.0 /
 29-October-2025</strong> </label>
 <div>
-<h2 id="main-changes">Main Changes</h2>
+<h2 id="main-changes-1">Main Changes</h2>
 <ul>
 <li>Added support to STM32WL3Rx product line.</li>
 <li>[LCSC] LCSC_VER register removed from the accessible register list,
@@ -74,16 +98,17 @@ <h2 id="main-changes">Main Changes</h2>
 <li>[MRSUBG] RSSI_FLT bit #3 renamed to
 <code>FREEZE_SYNC_ON_SYNC_OOK_PEAK_DECAY</code></li>
 </ul>
-<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="known-limitations-1">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="development-toolchains-and-compilers">Development Toolchains and
-Compilers</h2>
+<h2 id="development-toolchains-and-compilers-1">Development Toolchains
+and Compilers</h2>
 <ul>
 <li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
 </ul>
-<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-1">Supported Devices and
+boards</h2>
 <ul>
 <li>STM32WL3xx devices</li>
 </ul>
@@ -94,7 +119,7 @@ <h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
 <label for="collapse-section3" aria-hidden="true"> <strong>V1.2.0 /
 04-June-2025</strong> </label>
 <div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
 <ul>
 <li>Documentation based on jQuery 1.7.1 removed</li>
 </ul>
@@ -104,17 +129,17 @@ <h2 id="contents">Contents</h2>
 <li>Renamed some interrupt to improve clarity and consistency</li>
 <li>Added FQCY_BAND_ID bits definition for RF_INFO_OUT register</li>
 </ul>
-<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
 <ul>
 <li>CMSIS devices files are delivered “as is” and have not been fully
 validated</li>
 </ul>
-<h2 id="development-toolchains-and-compilers-1">Development Toolchains
+<h2 id="development-toolchains-and-compilers-2">Development Toolchains
 and Compilers</h2>
 <ul>
 <li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
 </ul>
-<h2 id="supported-devices-and-boards-1">Supported Devices and
+<h2 id="supported-devices-and-boards-2">Supported Devices and
 boards</h2>
 <ul>
 <li>STM32WL3xx devices</li>
@@ -126,7 +151,7 @@ <h2 id="supported-devices-and-boards-1">Supported Devices and
 <label for="collapse-section2" aria-hidden="true"> <strong>V1.1.0 /
 05-February-2025</strong> </label>
 <div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
 <h3 id="release">Release</h3>
 <ul>
 <li>Release of CMSIS for STM32WL3xx devices</li>
@@ -135,17 +160,17 @@ <h2 id="contents-1">Contents</h2>
 <ul>
 <li>CMSIS devices files for STM32WL3xx</li>
 </ul>
-<h2 id="known-limitations-2">Known Limitations</h2>
+<h2 id="known-limitations-3">Known Limitations</h2>
 <ul>
 <li>CMSIS devices files are delivered “as is” and have not been fully
 validated</li>
 </ul>
-<h2 id="development-toolchains-and-compilers-2">Development Toolchains
+<h2 id="development-toolchains-and-compilers-3">Development Toolchains
 and Compilers</h2>
 <ul>
 <li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
 </ul>
-<h2 id="supported-devices-and-boards-2">Supported Devices and
+<h2 id="supported-devices-and-boards-3">Supported Devices and
 boards</h2>
 <ul>
 <li>STM32WL3xx devices</li>
@@ -157,7 +182,7 @@ <h2 id="supported-devices-and-boards-2">Supported Devices and
 <label for="collapse-section1" aria-hidden="true"> <strong>V1.0.0 /
 30-October-2024</strong> </label>
 <div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
 <h3 id="first-release">First Release</h3>
 <ul>
 <li>First Official Release of CMSIS for STM32WL33x devices</li>
@@ -166,17 +191,17 @@ <h2 id="contents-2">Contents</h2>
 <ul>
 <li>CMSIS devices files for STM32WL33x</li>
 </ul>
-<h2 id="known-limitations-3">Known Limitations</h2>
+<h2 id="known-limitations-4">Known Limitations</h2>
 <ul>
 <li>CMSIS devices files are delivered “as is” and have not been fully
 validated</li>
 </ul>
-<h2 id="development-toolchains-and-compilers-3">Development Toolchains
+<h2 id="development-toolchains-and-compilers-4">Development Toolchains
 and Compilers</h2>
 <ul>
 <li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
 </ul>
-<h2 id="supported-devices-and-boards-3">Supported Devices and
+<h2 id="supported-devices-and-boards-4">Supported Devices and
 boards</h2>
 <ul>
 <li>STM32WL33x devices</li>
diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s
@@ -83,8 +83,6 @@ LoopFillZerobss:
   cmp  r2, r3
   bcc  FillZerobss
 
-/* Call static constructors */
-  bl __libc_init_array
 /* Call the application's entry point.*/
   bl  main
 
diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
@@ -23,7 +23,7 @@
   * STM32WB0: 1.4.0
   * STM32WBA: 1.8.0
   * STM32WL: 1.3.0
-  * STM32WL3: 1.3.0
+  * STM32WL3: 1.3.1
 
 Release notes of each STM32YYxx CMSIS available here:
 
