From 80d02a0790ad7571eb228b734d649c84c08a8e69 Mon Sep 17 00:00:00 2001 From: Vijay Anand R Date: Wed, 3 Jun 2026 16:29:27 +0000 Subject: [PATCH 1/4] update sai bcm modules Signed-off-by: Vijay Anand R --- include/ibde.h | 2 +- include/kcom.h | 4 +- include/sal/types.h | 2 +- include/sdk_config.h | 2 +- include/shared/bitop.h | 82 + include/shared/error.h | 103 + include/soc/devids.h | 43 +- make/Make.clang | 2 +- make/Make.config | 26 +- make/Make.depend | 2 +- make/Make.elfutils | 81 + make/Make.kernlib | 2 +- make/Make.kpmd | 120 + make/Make.lib | 4 +- make/Make.linux | 2 +- make/Make.lkm | 89 + make/Make.subdirs | 2 +- make/Make.tools | 2 +- make/Makefile.linux-gts | 2 +- make/Makefile.linux-iproc | 12 +- make/Makefile.linux-iproc-3_14 | 2 +- make/Makefile.linux-iproc-4_4 | 2 +- make/Makefile.linux-iproc_64 | 24 +- make/Makefile.linux-kernel | 2 +- make/Makefile.linux-kernel-2_6 | 2 +- make/Makefile.linux-kernel-3_6 | 2 +- make/Makefile.linux-kernel-4_18 | 2 +- make/Makefile.linux-kernel-4_4 | 2 +- make/Makefile.linux-kmodule | 2 +- make/Makefile.linux-slk | 2 +- make/Makefile.linux-x86-5_10 | 2 +- make/Makefile.linux-x86-64-fc28 | 2 +- make/Makefile.linux-x86-6_10 | 242 + make/Makefile.linux-x86-common-2_6 | 2 +- make/Makefile.linux-x86-generic-common-2_6 | 2 +- make/Makefile.linux-x86-smp_generic_64-2_6 | 21 +- make/Makefile.linux-xlr | 2 +- .../hmi/cmicr/bcmcnet_cmicr2_pdma_rxtx.c | 384 + .../bcmcnet/hmi/cmicr/bcmcnet_cmicr_pdma_hw.c | 720 + .../hmi/cmicr/bcmcnet_cmicr_pdma_rxtx.c | 1204 ++ .../bcmcnet/hmi/cmicx/bcmcnet_cmicx_pdma_hw.c | 601 + .../hmi/cmicx/bcmcnet_cmicx_pdma_rxtx.c | 1171 ++ .../bcmcnet/include/bcmcnet/bcmcnet_cmicr.h | 212 + .../bcmcnet/include/bcmcnet/bcmcnet_cmicr2.h | 63 + .../include/bcmcnet/bcmcnet_cmicr_acc.h | 810 ++ .../bcmcnet/include/bcmcnet/bcmcnet_cmicx.h | 397 + .../bcmcnet/include/bcmcnet/bcmcnet_core.h | 1376 ++ .../bcmcnet/include/bcmcnet/bcmcnet_dev.h | 570 + .../include/bcmcnet/bcmcnet_internal.h | 322 + .../bcmcnet/include/bcmcnet/bcmcnet_rxtx.h | 539 + .../bcmcnet/include/bcmcnet/bcmcnet_types.h | 282 + .../common/pktio/bcmcnet/main/bcmcnet_core.c | 799 ++ .../common/pktio/bcmcnet/main/bcmcnet_dev.c | 1135 ++ .../common/pktio/bcmcnet/main/bcmcnet_rxtx.c | 752 ++ .../pktio/bcmdrd/include/bcmdrd/bcmdrd.h | 370 + .../pktio/bcmdrd/include/bcmdrd/bcmdrd_chip.h | 852 ++ .../pktio/bcmdrd/include/bcmdrd/bcmdrd_dev.h | 1369 ++ .../bcmdrd/include/bcmdrd/bcmdrd_devlist.h | 266 + .../bcmdrd/include/bcmdrd/bcmdrd_feature.h | 116 + .../include/bcmdrd/bcmdrd_feature_enum.h | 236 + .../pktio/bcmdrd/include/bcmdrd/bcmdrd_hal.h | 1153 ++ .../bcmdrd/include/bcmdrd/bcmdrd_internal.h | 141 + .../include/bcmdrd/bcmdrd_symbol_types.h | 227 + .../bcmdrd/include/bcmdrd/bcmdrd_symbols.h | 1152 ++ .../bcmdrd/include/bcmdrd/bcmdrd_types.h | 694 + .../pktio/bcmdrd/include/bcmdrd_config.h | 202 + .../bcmdrd/include/bcmdrd_config_chips.h | 550 + .../pktio/bcmlrd/include/bcmlrd/bcmlrd_conf.h | 180 + .../bcmlrd/include/bcmlrd/bcmlrd_id_types.h | 57 + .../include/bcmlrd/bcmlrd_match_id_db.h | 387 + .../bcmlrd/include/bcmlrd/bcmlrd_variant.h | 53 + .../include/bcmlrd/chip/bcmlrd_chip_variant.h | 60 + .../include/bcmlrd/chip/bcmlrd_variant_defs.h | 53 + .../bcmltd/include/bcmltd/bcmltd_id_types.h | 72 + .../bcmltd/include/bcmltd/bcmltd_variant.h | 77 + .../include/bcmltd/chip/bcmltd_chip_variant.h | 54 + .../bcmltd/chip/bcmltd_config_variant.h | 91 + .../include/bcmltd/chip/bcmltd_variant_defs.h | 48 + .../bcmltd/chip/bcmltd_variant_entry.h | 63 + .../pktio/bcmpkt/include/bcmpkt/bcmpkt_buf.h | 568 + .../pktio/bcmpkt/include/bcmpkt/bcmpkt_dev.h | 1063 ++ .../pktio/bcmpkt/include/bcmpkt/bcmpkt_dump.h | 309 + .../bcmpkt/include/bcmpkt/bcmpkt_flexhdr.h | 409 + .../include/bcmpkt/bcmpkt_flexhdr_field.h | 113 + .../include/bcmpkt/bcmpkt_flexhdr_internal.h | 177 + .../pktio/bcmpkt/include/bcmpkt/bcmpkt_hg3.h | 62 + .../bcmpkt/include/bcmpkt/bcmpkt_higig_defs.h | 359 + .../bcmpkt/include/bcmpkt/bcmpkt_internal.h | 244 + .../pktio/bcmpkt/include/bcmpkt/bcmpkt_knet.h | 929 ++ .../bcmpkt/include/bcmpkt/bcmpkt_lbhdr.h | 156 + .../bcmpkt/include/bcmpkt/bcmpkt_lbhdr_defs.h | 381 + .../include/bcmpkt/bcmpkt_lbhdr_field.h | 72 + .../include/bcmpkt/bcmpkt_lbhdr_internal.h | 80 + .../bcmpkt/include/bcmpkt/bcmpkt_mhdr_defs.h | 184 + .../pktio/bcmpkt/include/bcmpkt/bcmpkt_net.h | 367 + .../bcmpkt/include/bcmpkt/bcmpkt_packet.h | 182 + .../pktio/bcmpkt/include/bcmpkt/bcmpkt_pmd.h | 66 + .../include/bcmpkt/bcmpkt_pmd_internal.h | 78 + .../bcmpkt/include/bcmpkt/bcmpkt_rcpu_hdr.h | 146 + .../bcmpkt/include/bcmpkt/bcmpkt_rxpmd.h | 284 + .../bcmpkt/include/bcmpkt/bcmpkt_rxpmd_defs.h | 1325 ++ .../bcmpkt/include/bcmpkt/bcmpkt_rxpmd_fid.h | 100 + .../include/bcmpkt/bcmpkt_rxpmd_field.h | 93 + .../include/bcmpkt/bcmpkt_rxpmd_internal.h | 99 + .../include/bcmpkt/bcmpkt_rxpmd_match_id.h | 192 + .../bcmpkt/include/bcmpkt/bcmpkt_socket.h | 339 + .../bcmpkt/include/bcmpkt/bcmpkt_trace_defs.h | 11062 ++++++++++++++++ .../bcmpkt/include/bcmpkt/bcmpkt_txpmd.h | 174 + .../bcmpkt/include/bcmpkt/bcmpkt_txpmd_defs.h | 823 ++ .../include/bcmpkt/bcmpkt_txpmd_field.h | 72 + .../include/bcmpkt/bcmpkt_txpmd_internal.h | 79 + .../pktio/bcmpkt/include/bcmpkt/bcmpkt_util.h | 90 + .../common/pktio/bcmpkt/rxpmd/bcmpkt_rxpmd.c | 432 + .../common/pktio/bcmpkt/txpmd/bcmpkt_txpmd.c | 273 + .../bcm88690_a0/bcm88690_a0_pdma_attach.c | 84 + .../chip/bcm88690_a0/bcm88690_a0_pkt_rxpmd.c | 439 + .../bcm88690_a0_pkt_rxpmd_dev_field.c | 42 + .../chip/bcm88690_a0/bcm88690_a0_pkt_txpmd.c | 405 + .../bcm88860_a0/bcm88860_a0_pdma_attach.c | 84 + .../chip/bcm88860_a0/bcm88860_a0_pkt_rxpmd.c | 439 + .../bcm88860_a0_pkt_rxpmd_dev_field.c | 41 + .../chip/bcm88860_a0/bcm88860_a0_pkt_txpmd.c | 405 + .../bcm88920_a0/bcm88920_a0_pdma_attach.c | 84 + .../chip/bcm88920_a0/bcm88920_a0_pkt_rxpmd.c | 367 + .../bcm88920_a0_pkt_rxpmd_dev_field.c | 41 + .../chip/bcm88920_a0/bcm88920_a0_pkt_txpmd.c | 405 + .../bcm99450_a0/bcm99450_a0_pdma_attach.c | 83 + .../chip/bcm99450_a0/bcm99450_a0_pkt_rxpmd.c | 439 + .../bcm99450_a0_pkt_rxpmd_dev_field.c | 41 + .../chip/bcm99450_a0/bcm99450_a0_pkt_txpmd.c | 405 + .../bcm99470_a0/bcm99470_a0_pdma_attach.c | 83 + .../chip/bcm99470_a0/bcm99470_a0_pkt_rxpmd.c | 367 + .../bcm99470_a0_pkt_rxpmd_dev_field.c | 41 + .../chip/bcm99470_a0/bcm99470_a0_pkt_txpmd.c | 405 + src/bcm/common/pktio/pktio_dep.h | 401 + systems/bde/linux/include/linux-bde.h | 7 +- systems/bde/linux/include/linux_dma.h | 2 +- systems/bde/linux/include/mpool.h | 2 +- systems/bde/linux/kernel/Makefile | 2 +- systems/bde/linux/kernel/linux-kernel-bde.c | 300 +- systems/bde/linux/kernel/linux_dma.c | 15 +- systems/bde/linux/kernel/linux_shbde.c | 2 +- systems/bde/linux/kernel/linux_shbde.h | 2 +- systems/bde/linux/shared/mpool.c | 2 +- systems/bde/linux/user/kernel/Makefile | 2 +- .../bde/linux/user/kernel/linux-user-bde.c | 41 +- .../bde/linux/user/kernel/linux-user-bde.h | 3 +- systems/bde/shared/include/shbde.h | 2 +- systems/bde/shared/include/shbde_iproc.h | 2 +- systems/bde/shared/include/shbde_mdio.h | 2 +- systems/bde/shared/include/shbde_pci.h | 2 +- systems/bde/shared/shbde_iproc.c | 2 +- systems/bde/shared/shbde_mdio.c | 2 +- systems/bde/shared/shbde_pci.c | 2 +- systems/linux/kernel/modules/Makefile | 2 +- .../linux/kernel/modules/bcm-genl/Makefile | 2 +- .../kernel/modules/bcm-genl/bcm-genl-dev.c | 2 +- .../kernel/modules/bcm-genl/bcm-genl-dev.h | 2 +- .../kernel/modules/bcm-genl/bcm-genl-netif.c | 2 +- .../kernel/modules/bcm-genl/bcm-genl-netif.h | 2 +- .../kernel/modules/bcm-genl/bcm-genl-packet.c | 2 +- .../kernel/modules/bcm-genl/bcm-genl-packet.h | 2 +- .../modules/bcm-genl/bcm-genl-psample.c | 4 +- .../modules/bcm-genl/bcm-genl-psample.h | 2 +- .../linux/kernel/modules/bcm-genl/bcm-genl.c | 2 +- .../linux/kernel/modules/bcm-knet/Makefile | 4 +- .../linux/kernel/modules/bcm-knet/bcm-knet.c | 17 +- .../linux/kernel/modules/bcm-ngknet/Kbuild | 67 + .../linux/kernel/modules/bcm-ngknet/Makefile | 184 + .../modules/bcm-ngknet/include/lkm/lkm.h | 214 + .../bcm-ngknet/include/lkm/ngbde_ioctl.h | 448 + .../bcm-ngknet/include/lkm/ngbde_kapi.h | 326 + .../bcm-ngknet/include/lkm/ngedk_ioctl.h | 214 + .../bcm-ngknet/include/lkm/ngedk_kapi.h | 52 + .../bcm-ngknet/include/lkm/ngknet_dev.h | 480 + .../bcm-ngknet/include/lkm/ngknet_ioctl.h | 126 + .../bcm-ngknet/include/lkm/ngknet_kapi.h | 436 + .../bcm-ngknet/include/lkm/ngknet_msg.h | 83 + .../bcm-ngknet/include/lkm/ngptpclock_ioctl.h | 56 + .../modules/bcm-ngknet/ngknet_adapter.c | 1096 ++ .../modules/bcm-ngknet/ngknet_adapter.h | 305 + .../kernel/modules/bcm-ngknet/ngknet_buff.c | 364 + .../kernel/modules/bcm-ngknet/ngknet_buff.h | 94 + .../modules/bcm-ngknet/ngknet_callback.c | 626 + .../modules/bcm-ngknet/ngknet_callback.h | 145 + .../kernel/modules/bcm-ngknet/ngknet_dep.h | 72 + .../kernel/modules/bcm-ngknet/ngknet_extra.c | 732 + .../kernel/modules/bcm-ngknet/ngknet_extra.h | 233 + .../kernel/modules/bcm-ngknet/ngknet_linux.c | 182 + .../kernel/modules/bcm-ngknet/ngknet_linux.h | 326 + .../kernel/modules/bcm-ngknet/ngknet_main.c | 3457 +++++ .../kernel/modules/bcm-ngknet/ngknet_main.h | 289 + .../kernel/modules/bcm-ngknet/ngknet_parser.c | 1231 ++ .../kernel/modules/bcm-ngknet/ngknet_parser.h | 53 + .../kernel/modules/bcm-ngknet/ngknet_procfs.c | 687 + .../kernel/modules/bcm-ngknet/ngknet_procfs.h | 60 + .../kernel/modules/bcm-ngknet/ngknet_ptp.c | 226 + .../kernel/modules/bcm-ngknet/ngknet_ptp.h | 140 + .../modules/bcm-ptp-clock/bcm-ptp-clock.c | 22 +- .../linux/kernel/modules/genl-packet/Makefile | 2 +- .../linux/kernel/modules/include/bcm-knet.h | 2 +- .../linux/kernel/modules/include/gmodule.h | 2 +- systems/linux/kernel/modules/include/lkm.h | 2 +- systems/linux/kernel/modules/knet-cb/Makefile | 2 +- .../linux/kernel/modules/knet-cb/knet-cb.c | 3 +- systems/linux/kernel/modules/ngknetcb/Kbuild | 53 + .../linux/kernel/modules/ngknetcb/Makefile | 121 + .../kernel/modules/ngknetcb/ngknetcb_main.c | 672 + systems/linux/kernel/modules/shared/Makefile | 2 +- systems/linux/kernel/modules/shared/gmodule.c | 2 +- systems/linux/user/common/Makefile | 88 +- systems/linux/user/gts/Makefile | 2 +- systems/linux/user/iproc-3_14/Makefile | 2 +- systems/linux/user/iproc-4_4/Makefile | 2 +- systems/linux/user/iproc/Makefile | 4 +- systems/linux/user/iproc_64/Makefile | 4 +- systems/linux/user/slk/Makefile | 2 +- systems/linux/user/x86-5_10/Makefile | 2 +- systems/linux/user/x86-64-fc28/Makefile | 2 +- systems/linux/user/x86-6_10/Makefile | 82 + .../user/x86-smp_generic_64-2_6/Makefile | 2 +- systems/linux/user/xlr/Makefile | 2 +- tools/mktool.pl | 2 +- 223 files changed, 61592 insertions(+), 174 deletions(-) create mode 100644 include/shared/bitop.h create mode 100644 include/shared/error.h create mode 100644 make/Make.elfutils create mode 100644 make/Make.kpmd create mode 100644 make/Make.lkm create mode 100644 make/Makefile.linux-x86-6_10 create mode 100644 src/bcm/common/pktio/bcmcnet/hmi/cmicr/bcmcnet_cmicr2_pdma_rxtx.c create mode 100644 src/bcm/common/pktio/bcmcnet/hmi/cmicr/bcmcnet_cmicr_pdma_hw.c create mode 100644 src/bcm/common/pktio/bcmcnet/hmi/cmicr/bcmcnet_cmicr_pdma_rxtx.c create mode 100644 src/bcm/common/pktio/bcmcnet/hmi/cmicx/bcmcnet_cmicx_pdma_hw.c create mode 100644 src/bcm/common/pktio/bcmcnet/hmi/cmicx/bcmcnet_cmicx_pdma_rxtx.c create mode 100644 src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicr.h create mode 100644 src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicr2.h create mode 100644 src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicr_acc.h create mode 100644 src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicx.h create mode 100644 src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_core.h create mode 100644 src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_dev.h create mode 100644 src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_internal.h create mode 100644 src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_rxtx.h create mode 100644 src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_types.h create mode 100644 src/bcm/common/pktio/bcmcnet/main/bcmcnet_core.c create mode 100644 src/bcm/common/pktio/bcmcnet/main/bcmcnet_dev.c create mode 100644 src/bcm/common/pktio/bcmcnet/main/bcmcnet_rxtx.c create mode 100644 src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd.h create mode 100644 src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_chip.h create mode 100644 src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_dev.h create mode 100644 src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_devlist.h create mode 100644 src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_feature.h create mode 100644 src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_feature_enum.h create mode 100644 src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_hal.h create mode 100644 src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_internal.h create mode 100644 src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_symbol_types.h create mode 100644 src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_symbols.h create mode 100644 src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_types.h create mode 100644 src/bcm/common/pktio/bcmdrd/include/bcmdrd_config.h create mode 100644 src/bcm/common/pktio/bcmdrd/include/bcmdrd_config_chips.h create mode 100644 src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_conf.h create mode 100644 src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_id_types.h create mode 100644 src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_match_id_db.h create mode 100644 src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_variant.h create mode 100644 src/bcm/common/pktio/bcmlrd/include/bcmlrd/chip/bcmlrd_chip_variant.h create mode 100644 src/bcm/common/pktio/bcmlrd/include/bcmlrd/chip/bcmlrd_variant_defs.h create mode 100644 src/bcm/common/pktio/bcmltd/include/bcmltd/bcmltd_id_types.h create mode 100644 src/bcm/common/pktio/bcmltd/include/bcmltd/bcmltd_variant.h create mode 100644 src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_chip_variant.h create mode 100644 src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_config_variant.h create mode 100644 src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_variant_defs.h create mode 100644 src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_variant_entry.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_buf.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_dev.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_dump.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_flexhdr.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_flexhdr_field.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_flexhdr_internal.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_hg3.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_higig_defs.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_internal.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_knet.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr_defs.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr_field.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr_internal.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_mhdr_defs.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_net.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_packet.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_pmd.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_pmd_internal.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rcpu_hdr.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_defs.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_fid.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_field.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_internal.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_match_id.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_socket.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_trace_defs.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd_defs.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd_field.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd_internal.h create mode 100644 src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_util.h create mode 100644 src/bcm/common/pktio/bcmpkt/rxpmd/bcmpkt_rxpmd.c create mode 100644 src/bcm/common/pktio/bcmpkt/txpmd/bcmpkt_txpmd.c create mode 100644 src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pdma_attach.c create mode 100644 src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pkt_rxpmd.c create mode 100644 src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pkt_rxpmd_dev_field.c create mode 100644 src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pkt_txpmd.c create mode 100644 src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pdma_attach.c create mode 100644 src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pkt_rxpmd.c create mode 100644 src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pkt_rxpmd_dev_field.c create mode 100644 src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pkt_txpmd.c create mode 100644 src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pdma_attach.c create mode 100644 src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pkt_rxpmd.c create mode 100644 src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pkt_rxpmd_dev_field.c create mode 100644 src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pkt_txpmd.c create mode 100644 src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pdma_attach.c create mode 100644 src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pkt_rxpmd.c create mode 100644 src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pkt_rxpmd_dev_field.c create mode 100644 src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pkt_txpmd.c create mode 100644 src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pdma_attach.c create mode 100644 src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pkt_rxpmd.c create mode 100644 src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pkt_rxpmd_dev_field.c create mode 100644 src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pkt_txpmd.c create mode 100644 src/bcm/common/pktio/pktio_dep.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/Kbuild create mode 100644 systems/linux/kernel/modules/bcm-ngknet/Makefile create mode 100644 systems/linux/kernel/modules/bcm-ngknet/include/lkm/lkm.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngbde_ioctl.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngbde_kapi.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngedk_ioctl.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngedk_kapi.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_dev.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_ioctl.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_kapi.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_msg.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngptpclock_ioctl.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_adapter.c create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_adapter.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_buff.c create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_buff.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_callback.c create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_callback.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_dep.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_extra.c create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_extra.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_linux.c create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_linux.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_main.c create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_main.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_parser.c create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_parser.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_procfs.c create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_procfs.h create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_ptp.c create mode 100644 systems/linux/kernel/modules/bcm-ngknet/ngknet_ptp.h create mode 100644 systems/linux/kernel/modules/ngknetcb/Kbuild create mode 100644 systems/linux/kernel/modules/ngknetcb/Makefile create mode 100644 systems/linux/kernel/modules/ngknetcb/ngknetcb_main.c create mode 100644 systems/linux/user/x86-6_10/Makefile diff --git a/include/ibde.h b/include/ibde.h index 67e9f8b..b5038de 100644 --- a/include/ibde.h +++ b/include/ibde.h @@ -1,7 +1,7 @@ /* * $Id: ibde.h,v 1.27 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/include/kcom.h b/include/kcom.h index 36a430e..3f64e01 100644 --- a/include/kcom.h +++ b/include/kcom.h @@ -1,6 +1,7 @@ /* * $Id: kcom.h,v 1.9 Broadcom SDK $ - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. @@ -209,6 +210,7 @@ typedef struct kcom_netif_s { #define KCOM_FILTER_F_ANY_DATA (1U << 0) #define KCOM_FILTER_F_STRIP_TAG (1U << 1) +#define KCOM_FILTER_F_OOB_RAW (1U << 2) #define KCOM_FILTER_DESC_MAX 32 diff --git a/include/sal/types.h b/include/sal/types.h index e4f17a2..4586e9f 100644 --- a/include/sal/types.h +++ b/include/sal/types.h @@ -1,7 +1,7 @@ /* * $Id: types.h,v 1.3 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/include/sdk_config.h b/include/sdk_config.h index 6cb0ce1..dcad8bc 100644 --- a/include/sdk_config.h +++ b/include/sdk_config.h @@ -1,7 +1,7 @@ /* * $Id: sdk_config.h,v 1.5 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/include/shared/bitop.h b/include/shared/bitop.h new file mode 100644 index 0000000..8fbd9c9 --- /dev/null +++ b/include/shared/bitop.h @@ -0,0 +1,82 @@ +/* + * $Id: bitop.h,v 1.16 Broadcom SDK $ + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * Bit Array Operations + */ + +#ifndef _SHR_BITOP_H +#define _SHR_BITOP_H + +#include + +/* Base type for declarations */ +#define SHR_BITDCL uint32 +#define SHR_BITWID 32 + +/* (internal) Number of SHR_BITDCLs needed to contain _max bits */ +#define _SHR_BITDCLSIZE(_max) (((_max) + SHR_BITWID - 1) / SHR_BITWID) +#define SHRi_BITDCLSIZE(_max) (((_max) + SHR_BITWID - 1) / SHR_BITWID) + +/* Size for giving to malloc and memset to handle _max bits */ +#define SHR_BITALLOCSIZE(_max) (_SHR_BITDCLSIZE(_max) * sizeof (SHR_BITDCL)) + + +/* (internal) Number of SHR_BITDCLs needed to contain from start bit to start bit + range */ +#define _SHR_BITDCLSIZE_FROM_START_BIT(_start_bit, _range) (_range + _start_bit -1)/SHR_BITWID - _start_bit/SHR_BITWID + 1 + +/* Size of SHR_BITDCLs needed to contain from start bit to start bit + range. + Needed when you want to do autosync */ +#define SHR_BITALLOCSIZE_FROM_START_BIT(_start_bit, _range) (_SHR_BITDCLSIZE_FROM_START_BIT(_start_bit, _range) * sizeof (SHR_BITDCL)) + + + +/* Declare bit array _n of size _max bits */ +#define SHR_BITDCLNAME(_n, _max) SHR_BITDCL _n[_SHR_BITDCLSIZE(_max)] +/* Declare bit array _n of size _max bits, and clear it */ +#define SHR_BIT_DCL_CLR_NAME(_n, _max) SHR_BITDCL _n[_SHR_BITDCLSIZE(_max)] = {0} + +/* (internal) Generic operation macro on bit array _a, with bit _b */ +#define _SHR_BITOP(_a, _b, _op) \ + (((_a)[(_b) / SHR_BITWID]) _op (1U << ((_b) % SHR_BITWID))) + +/* Specific operations */ +#define SHR_BITGET(_a, _b) _SHR_BITOP(_a, _b, &) +#define SHR_BITSET(_a, _b) _SHR_BITOP(_a, _b, |=) +#define SHR_BITCLR(_a, _b) _SHR_BITOP(_a, _b, &= ~) +#define SHR_BITWRITE(_a, _b, _val) ((_val) ? SHR_BITSET(_a, _b) : SHR_BITCLR(_a, _b)) +#define SHR_BIT_ITER(_a, _max, _b) \ + for ((_b) = 0; (_b) < (_max); (_b)++) \ + if ((_a)[(_b) / SHR_BITWID] == 0) \ + (_b) += (SHR_BITWID - 1); \ + else if (SHR_BITGET((_a), (_b))) + +#define SHR_IS_BITSET(_a, _b) (_SHR_BITOP(_a, _b, &) ? TRUE : FALSE) + +#endif /* !_SHR_BITOP_H */ diff --git a/include/shared/error.h b/include/shared/error.h new file mode 100644 index 0000000..f2c8b68 --- /dev/null +++ b/include/shared/error.h @@ -0,0 +1,103 @@ +/* + * $Id: error.h,v 1.23 Broadcom SDK $ + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file defines common error codes to be shared between API layers. + * + * Its contents are not used directly by applications; it is used only + * by header files of parent APIs which need to define error codes. + */ + +#ifndef _SHR_ERROR_H +#define _SHR_ERROR_H + +typedef enum { + _SHR_E_NONE = 0, + _SHR_E_INTERNAL = -1, + _SHR_E_MEMORY = -2, + _SHR_E_UNIT = -3, + _SHR_E_PARAM = -4, + _SHR_E_EMPTY = -5, + _SHR_E_FULL = -6, + _SHR_E_NOT_FOUND = -7, + _SHR_E_EXISTS = -8, + _SHR_E_TIMEOUT = -9, + _SHR_E_BUSY = -10, + _SHR_E_FAIL = -11, + _SHR_E_DISABLED = -12, + _SHR_E_BADID = -13, + _SHR_E_RESOURCE = -14, + _SHR_E_CONFIG = -15, + _SHR_E_UNAVAIL = -16, + _SHR_E_INIT = -17, + _SHR_E_PORT = -18, + _SHR_E_IO = -19, + _SHR_E_ACCESS = -20, + _SHR_E_NO_HANDLER = -21, + _SHR_E_PARTIAL = -22, + + _SHR_E_LIMIT = -23 /* Must come last */ +} _shr_error_t; + +#define _SHR_ERRMSG_INIT { \ + "Ok", /* E_NONE */ \ + "Internal error", /* E_INTERNAL */ \ + "Out of memory", /* E_MEMORY */ \ + "Invalid unit", /* E_UNIT */ \ + "Invalid parameter", /* E_PARAM */ \ + "Table empty", /* E_EMPTY */ \ + "Table full", /* E_FULL */ \ + "Entry not found", /* E_NOT_FOUND */ \ + "Entry exists", /* E_EXISTS */ \ + "Operation timed out", /* E_TIMEOUT */ \ + "Operation still running", /* E_BUSY */ \ + "Operation failed", /* E_FAIL */ \ + "Operation disabled", /* E_DISABLED */ \ + "Invalid identifier", /* E_BADID */ \ + "No resources for operation", /* E_RESOURCE */ \ + "Invalid configuration", /* E_CONFIG */ \ + "Feature unavailable", /* E_UNAVAIL */ \ + "Feature not initialized", /* E_INIT */ \ + "Invalid port", /* E_PORT */ \ + "I/O error", /* E_IO */ \ + "Access error", /* E_ACCESS */ \ + "No handler", /* E_NO_HANDLER */ \ + "Partial success", /* E_PARTIAL */ \ + "Unknown error" /* E_LIMIT */ \ + } + +extern char *_shr_errmsg[]; + +#define _SHR_ERRMSG(r) \ + _shr_errmsg[(((int)r) <= 0 && ((int)r) > _SHR_E_LIMIT) ? -(r) : -_SHR_E_LIMIT] + +#define _SHR_E_SUCCESS(rv) ((rv) >= 0) +#define _SHR_E_FAILURE(rv) ((rv) < 0) + +#endif /* !_SHR_ERROR_H */ diff --git a/include/soc/devids.h b/include/soc/devids.h index f9ce2ee..d4fc9ce 100644 --- a/include/soc/devids.h +++ b/include/soc/devids.h @@ -1,7 +1,7 @@ /* * $Id: devids.h,v 1.309 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. @@ -1767,17 +1767,14 @@ #define BCM8879C_DEVICE_ID 0x879C #define BCM8879D_DEVICE_ID 0x879D #define BCM8879E_DEVICE_ID 0x879E -#define BCM8879F_DEVICE_ID 0x879F +#define BCM8879F_DEVICE_ID 0x879F #ifdef BCM_DNXF3_SUPPORT #define RAMON2_DEVICE_ID 0x8910 #define BCM8891F_DEVICE_ID 0x891F #define RAMON3_DEVICE_ID 0x8920 #endif -#ifdef BCM_DNXFE_SUPPORT -#ifdef BCM_RAMON_4_SUPPORT #define RAMON4_DEVICE_ID 0x9470 -#endif -#endif + #define ARADPLUS_DEVICE_ID 0x8660 #define ARADPLUS_A0_REV_ID 0x0001 #define BCM88660_DEVICE_ID ARADPLUS_DEVICE_ID @@ -2086,24 +2083,24 @@ #define Q3U_ORIG_DEVICE_ID 0x8400 #define Q3N_ORIG_DEVICE_ID 0x8405 #endif -#ifdef BCM_JERICHO_4_SUPPORT -#define JERICHO4_DEVICE_ID 0x9450 -#define Q4_DEVICE_ID 0x9420 -#endif -#ifdef BCM_Q4D_SUPPORT -#define Q4D_DEVICE_ID 0x9430 -#define Q4D_PT200_START_DEVICE_ID 0x9436 -#define Q4D_PT200_END_DEVICE_ID 0x9439 -#endif -#ifdef BCM_J4L_SUPPORT -#define J4L_DEVICE_ID 0x9410 -#endif -#endif +#endif /* BCM_DNX3_SUPPORT */ + + +#define JERICHO4_DEVICE_ID 0x9450 +#define Q4_DEVICE_ID 0x9420 +#define Q4D_DEVICE_ID 0x9430 +#define Q4D_200G_START_DEVICE_ID 0x9436 +#define Q4D_200G_END_DEVICE_ID 0x9439 +#define J4L_DEVICE_ID 0x9410 +#define Q4DL_DEVICE_ID 0x94E0 +#define Q4DL_200G_START_DEVICE_ID 0x94E6 +#define Q4DL_200G_END_DEVICE_ID 0x94E9 + #define Q2A_DEVICE_ID 0x8480 #define Q2A_A0_REV_ID DNXC_A0_REV_ID #define Q2A_B0_REV_ID DNXC_B0_REV_ID @@ -2243,7 +2240,7 @@ #define PLX9056_DEVICE_ID 0x9056 /* needed for DNX_TEST_BOARD */ -/* Tomahawk F1 */ +/* Tomahawk Ultra */ #define BCM78920_DEVICE_ID 0xf920 #define BCM78920_A0_REV_ID 0x0001 #define BCM78923_DEVICE_ID 0xf923 @@ -2253,6 +2250,12 @@ #define BCM78928_DEVICE_ID 0xf928 #define BCM78928_A0_REV_ID 0x0001 +/* Tomahawk Ultra */ +#define BCM78920_B0_REV_ID 0x0011 +#define BCM78923_B0_REV_ID 0x0011 +#define BCM78924_B0_REV_ID 0x0011 +#define BCM78928_B0_REV_ID 0x0011 + /* Trident4 X11c */ #define BCM56890_DEVICE_ID 0xb890 #define BCM56890_A0_REV_ID 0x0001 diff --git a/make/Make.clang b/make/Make.clang index 0f27927..f0745af 100644 --- a/make/Make.clang +++ b/make/Make.clang @@ -1,6 +1,6 @@ # $Id: Make.clang # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Make.config b/make/Make.config index 4db6b99..55f9da3 100644 --- a/make/Make.config +++ b/make/Make.config @@ -1,6 +1,6 @@ # $Id: Make.config,v 1.3 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. @@ -83,25 +83,33 @@ endif # ALL_CHIPS ifdef ALL_DNX2_CHIPS CFGFLAGS += -DBCM_DNX_SUPPORT - CFGFLAGS += -DBCM_INSTANCE_SUPPORT endif ifdef ALL_DNX3_CHIPS CFGFLAGS += -DBCM_DNX3_SUPPORT - CFGFLAGS += -DBCM_INSTANCE_SUPPORT endif ifdef ALL_DNXF1_CHIPS CFGFLAGS += -DBCM_DNXF_SUPPORT - CFGFLAGS += -DBCM_INSTANCE_SUPPORT endif ifdef ALL_DNXF3_CHIPS CFGFLAGS += -DBCM_DNXF3_SUPPORT - CFGFLAGS += -DBCM_INSTANCE_SUPPORT endif +ifdef ALL_DNXGEN4_CHIPS + CFGFLAGS += -DBCM_JERICHO_4_SUPPORT + CFGFLAGS += -DBCM_J4L_SUPPORT + CFGFLAGS += -DBCM_Q4D_SUPPORT + CFGFLAGS += -DBCM_Q4DL_SUPPORT +endif + +CFGFLAGS += -DBCM_INSTANCE_SUPPORT +# For PKTIO implementation files +ifdef PKTIO_IMPL + CFGFLAGS += -DPKTIO_IMPL=1 +endif # PKTIO_IMPL # # By default, turn off the "changing directory" message. @@ -212,14 +220,6 @@ CFLAGS += ${INCFLAGS} CXXFLAGS += ${INCFLAGS} CPPFLAGS += ${INCFLAGS} -CFLAGS += -DSAI_FIXUP -UKCOM_FILTER_MAX -DKCOM_FILTER_MAX=1025 -UKCOM_NETIF_MAX -DKCOM_NETIF_MAX=1056 - -# Flags for DNX ASIC family -CFLAGS += -DBCM_DNX_SUPPORT -DBCM_DNX2_SUPPORT -DBCM_DNXF_SUPPORT -DBCM_DNX3_SUPPORT -# -# # Flag to enable multi instance support -CFLAGS += -DBCM_INSTANCE_SUPPORT - # # Debug #ifdef control # diff --git a/make/Make.depend b/make/Make.depend index 5efd74b..631cd79 100644 --- a/make/Make.depend +++ b/make/Make.depend @@ -1,6 +1,6 @@ # $Id: Make.depend,v 1.14 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Make.elfutils b/make/Make.elfutils new file mode 100644 index 0000000..1afe8a1 --- /dev/null +++ b/make/Make.elfutils @@ -0,0 +1,81 @@ +# +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. +# +# Permission is granted to use, copy, modify and/or distribute this +# software under either one of the licenses below. +# +# License Option 1: GPL +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License, version 2, as +# published by the Free Software Foundation (the "GPL"). +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License version 2 (GPLv2) for more details. +# +# You should have received a copy of the GNU General Public License +# version 2 (GPLv2) along with this source code. +# +# +# License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license +# +# This software is governed by the Broadcom Open Network Switch APIs license: +# https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ +# +# +# +# Version checker target for elfutils. +# +# The parent makefile should set ELFUTILS_MIN to enforce a minimum +# version of the elfutils library, e.g. ELFUTILS_MIN=158 to enforce +# version 0.158 (or newer). +# +# The parent makefile can optionally supply ELFUTILS_DIR, which must +# be a path to an elfutils library that meets the minimum version +# requirement. +# + +ELFUTILS_MIN ?= 158 +ELFUTILS_DIR ?= /projects/ntsw-tools/lib + +# Get elfutils version of host system +ELFUTILS_SYS := $(shell ldconfig -v 2>/dev/null | \ + grep libelf | uniq | \ + sed 's/.*libelf-0.\([0-9]*\).*/\1/g') +ELFUTILS_VER := $(ELFUTILS_SYS) + +# Check elfutils version against minimum requirement +OVERRIDE_LIBELF := $(shell if [ 0$(ELFUTILS_VER) -lt 0$(ELFUTILS_MIN) ]; then echo 1; fi) + +ifeq ($(OVERRIDE_LIBELF),1) +# Override elfutils library if path was provided +ifdef ELFUTILS_DIR +ELFUTILS_OVR := $(shell ls $(ELFUTILS_DIR)/libelf-* 2>/dev/null | \ + sed 's/.*libelf-0.\([0-9]*\).*/\1/g') +ELFUTILS_VER := $(ELFUTILS_OVR) +override LD_LIBRARY_PATH := $(ELFUTILS_DIR):$(LD_LIBRARY_PATH) +export LD_LIBRARY_PATH +endif +endif + +elfutils:: +ifdef ELFUTILS_MIN +ifdef ELFUTILS_OVR + @echo "Overriding default elfutils library" +endif +ifdef ELFUTILS_VERBOSE + @echo "elfutils version: 0.$(ELFUTILS_VER)" +ifdef ELFUTILS_DEBUG + @echo "elfutils version: 0.$(ELFUTILS_SYS)" + @echo "LD_LIBRARY_PATH: $(LD_LIBRARY_PATH)" +endif +endif + if [ 0$(ELFUTILS_VER) -lt 0$(ELFUTILS_MIN) ]; then \ + echo "*** Error: elfutils version must be 0.$(ELFUTILS_MIN) or higher"; \ + exit 1; \ + fi +endif + +.PHONY: elfutils diff --git a/make/Make.kernlib b/make/Make.kernlib index 49e7f75..71294b9 100644 --- a/make/Make.kernlib +++ b/make/Make.kernlib @@ -1,6 +1,6 @@ # $Id: Make.kernlib,v 1.7 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Make.kpmd b/make/Make.kpmd new file mode 100644 index 0000000..1a29882 --- /dev/null +++ b/make/Make.kpmd @@ -0,0 +1,120 @@ +# +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. +# +# Permission is granted to use, copy, modify and/or distribute this +# software under either one of the licenses below. +# +# License Option 1: GPL +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License, version 2, as +# published by the Free Software Foundation (the "GPL"). +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License version 2 (GPLv2) for more details. +# +# You should have received a copy of the GNU General Public License +# version 2 (GPLv2) along with this source code. +# +# +# License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license +# +# This software is governed by the Broadcom Open Network Switch APIs license: +# https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ +# +# +# +# Helper makefile for building Linux kernel module that depends on the +# SDK Packet Meta Data (PMD) library. +# +# The makefile provides a make target named 'kpmd', which the main +# kernel module makefile should depend on. +# +# The 'kpmd' make target will create symbolic links from the relevant +# SDK source files into the module source directory, which must be +# specified via either one of $(KMODDIR) or $(GENDIR). +# +# The 'kpmd' make target also exports two make variables, of which +# $(SDK_PMD_KFLAGS) should be added to the kernel module build flags, +# and $(SDK_PMD_KOBJS) should be added to the list of kernel module +# object files. +# +# For example usage, please refer to $SDK/linux/bcmgenl/Makefile. +# + +ifndef SDK +$(error The $$SDK environment variable is not set) +endif + +ifeq (,$(PKTIODIR)) +PKTIODIR = $(SDK)/src/bcm/common/pktio +endif + +# SDK make utilities +include $(SDK)/make/Make.elfutils + +# SDK source directories +SHRDIR = $(SDK)/src/shared +BCMPKTDIR = $(PKTIODIR)/bcmpkt +BCMPKTIDIR = $(BCMPKTDIR)/include/bcmpkt + +# Create links locally if no GENDIR was specified +ifeq (,$(GENDIR)) +GENDIR = $(KMODDIR) +endif + +# +# Suppress symlink error messages. +# +# Note that we do not use "ln -f" as this may cause failures if +# multiple builds are done in parallel on the same source tree. +# +R = 2>/dev/null + +mklinks: config + mkdir -p $(GENDIR) + -ln -s $(PKTIODIR)/pktio_dep.h $(GENDIR) $(R) + -ln -s $(PKTIODIR)/chip/*/*rxpmd.c $(GENDIR) $(R) + -ln -s $(PKTIODIR)/chip/*/*rxpmd_dev_field.c $(GENDIR) $(R) + -ln -s $(PKTIODIR)/chip/*/*txpmd.c $(GENDIR) $(R) + -ln -s $(BCMPKTDIR)/rxpmd/bcmpkt_rxpmd.c $(GENDIR) $(R) + -ln -s $(BCMPKTDIR)/txpmd/bcmpkt_txpmd.c $(GENDIR) $(R) + -ln -s $(KMODDIR)/*.[ch] $(GENDIR) $(R) + -ln -s $(KMODDIR)/Makefile $(GENDIR) $(R) + -ln -s $(KMODDIR)/Kbuild $(GENDIR) $(R) + +rmlinks: + -rm -f $(GENDIR)/bcm* + -rm -f $(GENDIR)/shr* + +kpmd: mklinks + +distclean:: rmlinks + +.PHONY: mklinks rmlinks config kpmd distclean + +ALL_CHIPS := $(subst $(PKTIODIR)/chip/,,$(wildcard $(PKTIODIR)/chip/bcm*)) + +# Set PMD_CHIPS +ifdef SDK_CHIPS +PMD_CHIPS := $(SDK_CHIPS) +else +PMD_CHIPS := $(ALL_CHIPS) +endif # SDK_CHIPS + +CHIP_SRCS += $(addsuffix _pkt_rxpmd.c,$(PMD_CHIPS)) +CHIP_SRCS += $(addsuffix _pkt_rxpmd_dev_field.c,$(PMD_CHIPS)) +CHIP_SRCS += $(addsuffix _pkt_txpmd.c,$(PMD_CHIPS)) + +CHIP_OBJS ?= $(patsubst %.c, %.o, $(CHIP_SRCS)) + +SDK_PMD_KFLAGS := -DSAL_LINUX -DKPMD $(SDK_CPPFLAGS) +export SDK_PMD_KFLAGS + +COMMON_SRCS += bcmpkt_rxpmd.c +COMMON_SRCS += bcmpkt_txpmd.c + +SDK_PMD_KOBJS ?= $(patsubst %.c, %.o, $(COMMON_SRCS) $(CHIP_SRCS)) +export SDK_PMD_KOBJS diff --git a/make/Make.lib b/make/Make.lib index a77683d..ae82d9f 100644 --- a/make/Make.lib +++ b/make/Make.lib @@ -1,6 +1,6 @@ # $Id: Make.lib,v 1.14 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. @@ -75,4 +75,4 @@ distclean:: clean ifeq ($(DNX_FAST_MODE),1) -include $(SDK)/tools/dnx/make/lib.mk -endif +endif \ No newline at end of file diff --git a/make/Make.linux b/make/Make.linux index c47bf56..ec2e28e 100644 --- a/make/Make.linux +++ b/make/Make.linux @@ -1,7 +1,7 @@ # # $Id: Make.linux,v 1.18 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Make.lkm b/make/Make.lkm new file mode 100644 index 0000000..1e3a06c --- /dev/null +++ b/make/Make.lkm @@ -0,0 +1,89 @@ +# +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. +# +# Permission is granted to use, copy, modify and/or distribute this +# software under either one of the licenses below. +# +# License Option 1: GPL +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License, version 2, as +# published by the Free Software Foundation (the "GPL"). +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License version 2 (GPLv2) for more details. +# +# You should have received a copy of the GNU General Public License +# version 2 (GPLv2) along with this source code. +# +# +# License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license +# +# This software is governed by the Broadcom Open Network Switch APIs license: +# https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ +# +# +# +# Shared makefile include for building Linux kernel modules. +# + +# KDIR must point to the Linux kernel sources +ifndef KDIR +nokdir:; @echo 'The $$KDIR variable is not set'; exit 1 +endif + +# Required for older kernels +export EXTRA_CFLAGS = $(ccflags-y) + +PWD := $(shell pwd) + +ifneq ($(LKM_BLDDIR),) +# +# If a build directory has been specified, then we symlink all sources +# to this directory and redirect the module build path. +# +# Note that the KBUILD_OUTPUT variable cannot be used to redirect the +# output as we want it. +# +MDIR := $(LKM_BLDDIR) +MOBJS := $($(MOD_NAME)-y) +ifeq (,$(MOBJS)) +MOBJS := $(obj-m) +endif +MSRCS := $(patsubst %.o,%.c,$(MOBJS)) +MSRCS += Makefile Kbuild +BSRCS := $(addprefix $(PWD)/,$(MSRCS)) +else +# +# Build in current directory by default. +# +MDIR := $(PWD) +endif + +all: mlinks + $(Q)echo Building kernel module $(MOD_NAME) + $(MAKE) -C $(KDIR) M=$(MDIR) + +clean:: mlinks + $(Q)echo Cleaning kernel module $(MOD_NAME) + $(MAKE) -C $(KDIR) M=$(MDIR) clean +ifneq ($(MDIR),$(PWD)) + rm -rf $(MDIR) +endif + +mlinks: +ifneq ($(MDIR),$(PWD)) + $(Q)mkdir -p $(MDIR) + (cd $(MDIR); \ + rm -rf $(MSRCS); \ + for f in $(BSRCS); do \ + ln -s $$f; \ + done) +endif + +.PHONY: all mlinks clean + +# Standard documentation targets +-include $(SDK)/make/doc.mk diff --git a/make/Make.subdirs b/make/Make.subdirs index 9f89fa7..49b97f1 100644 --- a/make/Make.subdirs +++ b/make/Make.subdirs @@ -1,6 +1,6 @@ # $Id: Make.subdirs,v 1.8 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Make.tools b/make/Make.tools index 32a1a8a..4872d29 100644 --- a/make/Make.tools +++ b/make/Make.tools @@ -1,6 +1,6 @@ # $Id: Make.tools,v 1.2 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-gts b/make/Makefile.linux-gts index 6d2adc3..6ce0f95 100644 --- a/make/Makefile.linux-gts +++ b/make/Makefile.linux-gts @@ -1,6 +1,6 @@ # $Id: Makefile.linux-xlr-4_19,v 0.1 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-iproc b/make/Makefile.linux-iproc index fe2501e..6369947 100644 --- a/make/Makefile.linux-iproc +++ b/make/Makefile.linux-iproc @@ -1,6 +1,6 @@ # $Id: Makefile.linux-iproc Exp $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. @@ -33,6 +33,10 @@ ifeq (,$(BUILD_PLATFORM)) BUILD_PLATFORM=ARM_LINUX endif +# Upgrade TCL version from default 8.3 to 8.4 +# Because the incompatible-pointer-types warnings will be treated as errors in new toolchain. +export TCL840 := 1 + # TOOLCHAIN_BASE_DIR Toolchain base directory for iPROC-CMICd devices # TARGET_ARCHITECTURE Compiler for target architecture # KERNDIR Kernel directory for iPROC-CMICd devices @@ -40,12 +44,12 @@ ifeq (BE,$(ENDIAN_MODE)) #While BE mode is supported, it's use is very limited. We had a specific customer #request for BE support but don't currently mainstream it. So a 5.1.0 version #has not been built. Continue using 5.0.3 for any BE support -TOOLCHAIN_BASE_DIR ?= /projects/ntsw-tools/linux/iproc_ldks/xldk63-be/XLDK32 +TOOLCHAIN_BASE_DIR ?= /projects/ntsw-tools/linux/iproc_ldks/xldk64-be/XLDK32 KERN_BASE_DIR ?= $(TOOLCHAIN_BASE_DIR) TARGET_ARCHITECTURE:=armeb-broadcom-linux-uclibcgnueabi KERNDIR ?= $(TOOLCHAIN_BASE_DIR)/kernel/linux else -TOOLCHAIN_BASE_DIR ?= /projects/ntsw-tools/linux/iproc_ldks/xldk63/XLDK32 +TOOLCHAIN_BASE_DIR ?= /projects/ntsw-tools/linux/iproc_ldks/xldk64/XLDK32 KERN_BASE_DIR ?= $(TOOLCHAIN_BASE_DIR) TARGET_ARCHITECTURE:= arm-broadcom-linux-uclibcgnueabi KERNDIR ?= $(KERN_BASE_DIR)/kernel/linux @@ -116,7 +120,7 @@ modname_flags = $(if $(filter 1,$(words $(modname))),\ KFLAG_INCLD ?= $(LD_LIBRARY_PATH)/gcc/$(TARGET_ARCHITECTURE)/$(CROSS_GCC_VER)/include ifeq (,$(KFLAGS)) -KFLAGS := -D__LINUX_ARM_ARCH__=7 -D__KERNEL__ -nostdinc -isystem $(KFLAG_INCLD) -I$(LINUX_INCLUDE) -include $(LINUX_INCLUDE)/generated/autoconf.h -I$(KERNDIR)/arch/arm/include -I$(KERNDIR)/arch/arm/include/generated -I$(KERNDIR)/arch/arm/mach-iproc/include -Wall -Wstrict-prototypes -Wno-trigraphs -Os -fno-strict-aliasing -fno-common -marm -mabi=aapcs-linux -fno-pic -pipe -msoft-float -ffreestanding -march=armv7-a -mfloat-abi=softfp -fomit-frame-pointer -g -fno-stack-protector -Wdeclaration-after-statement -Wno-pointer-sign -mlong-calls +KFLAGS := -D__LINUX_ARM_ARCH__=7 -D__KERNEL__ -nostdinc -isystem $(KFLAG_INCLD) -I$(LINUX_INCLUDE) -include $(LINUX_INCLUDE)/generated/autoconf.h -I$(KERNDIR)/arch/arm/include -I$(KERNDIR)/arch/arm/include/generated -I$(KERNDIR)/arch/arm/mach-iproc/include -Wall -Wstrict-prototypes -Wno-trigraphs -Os -fno-strict-aliasing -fno-common -marm -mabi=aapcs-linux -fno-pic -pipe -msoft-float -ffreestanding -march=armv7-a -mfloat-abi=softfp -fomit-frame-pointer -g -fno-stack-protector -Wno-frame-address -Wno-address-of-packed-member -Wno-pointer-sign -mlong-calls KFLAGS += -I$(LINUX_INCLUDE)/uapi -I$(LINUX_INCLUDE)/generated/uapi -I$(KERNDIR)/arch/arm/include/uapi -I$(KERNDIR)/arch/arm/include/generated/uapi ifeq "$(shell expr $(CROSS_GCC_VER_MAJOR) \== 10)" "1" diff --git a/make/Makefile.linux-iproc-3_14 b/make/Makefile.linux-iproc-3_14 index f0b6ab0..ed42aa7 100644 --- a/make/Makefile.linux-iproc-3_14 +++ b/make/Makefile.linux-iproc-3_14 @@ -1,6 +1,6 @@ # $Id: Makefile.linux-iproc-3_6,v 1.1 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-iproc-4_4 b/make/Makefile.linux-iproc-4_4 index 0d23f79..cfb2890 100644 --- a/make/Makefile.linux-iproc-4_4 +++ b/make/Makefile.linux-iproc-4_4 @@ -1,6 +1,6 @@ # $Id: Makefile.linux-iproc Exp $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-iproc_64 b/make/Makefile.linux-iproc_64 index 7115a21..0b8e3d9 100644 --- a/make/Makefile.linux-iproc_64 +++ b/make/Makefile.linux-iproc_64 @@ -1,6 +1,6 @@ # $Id: Makefile.linux-iproc Exp $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. @@ -34,9 +34,8 @@ BUILD_PLATFORM=ARM_LINUX endif # Upgrade TCL version from default 8.3 to 8.4 -ifneq ($(ESW_CHIPS)$(LTSW_CHIPS),) +# Because the incompatible-pointer-types warnings will be treated as errors in new toolchain. export TCL840 := 1 -endif # TOOLCHAIN_BASE_DIR Toolchain base directory for iPROC-CMICd devices # TARGET_ARCHITECTURE Compiler for target architecture @@ -44,12 +43,12 @@ endif ifeq (BE,$(ENDIAN_MODE)) #We've never actually built a 64 BE executable. Just here for any future #customer requirements. -TOOLCHAIN_BASE_DIR ?= /projects/ntsw-tools/linux/iproc_ldks/xldk63-be/XLDK64 +TOOLCHAIN_BASE_DIR ?= /projects/ntsw-tools/linux/iproc_ldks/xldk64-be/XLDK64 KERN_BASE_DIR ?= $(TOOLCHAIN_BASE_DIR) TARGET_ARCHITECTURE ?= aarch64_be-broadcom-linux-uclibc KERNDIR ?= $(KERN_BASE_DIR)/kernel/linux else -TOOLCHAIN_BASE_DIR ?= /projects/ntsw-tools/linux/iproc_ldks/xldk63/XLDK64 +TOOLCHAIN_BASE_DIR ?= /projects/ntsw-tools/linux/iproc_ldks/xldk64/XLDK64 KERN_BASE_DIR ?= $(TOOLCHAIN_BASE_DIR) TARGET_ARCHITECTURE ?= aarch64-broadcom-linux-uclibc KERNDIR ?= $(KERN_BASE_DIR)/kernel/linux @@ -88,6 +87,7 @@ endif ifeq ($(LOCALDIR),src/soc/phy/fcmap/src) OPT_CFLAGS += -Wno-address-of-packed-member endif + CFGFLAGS += -DPTRS_ARE_64BITS -DLONGS_ARE_64BITS CFGFLAGS += -DPHYS_ADDRS_ARE_64BITS CFLAGS += -fno-aggressive-loop-optimizations -fno-strict-overflow @@ -99,7 +99,15 @@ ifeq "$(shell expr $(CROSS_GCC_VER_MAJOR) \>= 12)" "1" CFLAGS += -flarge-source-files endif -CFGFLAGS += -D$(ENDIAN) -DIPROC_CMICD +CFGFLAGS += -D$(ENDIAN) +# IPROC_CMICD enables iproc platform driver which requires iproc_platform_* symbols +# from the Broadcom BSP kernel. Omit when building against generic kernel (e.g. Debian). +# Set BUILD_WITH_IPROC_BSP=1 only when building with a BSP kernel that provides those symbols. +BUILD_WITH_IPROC_BSP ?= 0 +ifeq ($(BUILD_WITH_IPROC_BSP),1) +CFGFLAGS += -DIPROC_CMICD +endif + CFGFLAGS += -DBCM_PLATFORM_STRING=\"IPROC_CMICD\" #CFGFLAGS += -DSAL_BDE_DMA_MEM_DEFAULT=16 @@ -121,10 +129,10 @@ basename_flags = -D"KBUILD_BASENAME=KBUILD_STR($(call name-fix,$(basetarget)))" modname_flags = $(if $(filter 1,$(words $(modname))),\ -D"KBUILD_MODNAME=KBUILD_STR($(call name-fix,$(modname)))") -KFLAG_INCLD ?= $(LD_LIBRARY_PATH)/../gcc/$(TARGET_ARCHITECTURE)/$(CROSS_GCC_VER)/include +KFLAG_INCLD ?= $(LD_LIBRARY_PATH)/gcc/$(TARGET_ARCHITECTURE)/$(CROSS_GCC_VER)/include ifeq (,$(KFLAGS)) -KFLAGS := -D__LINUX_ARM_ARCH__=8 -D__KERNEL__ -DPTRS_ARE_64BITS -DLONGS_ARE_64BITS -nostdinc -isystem $(KFLAG_INCLD) -I$(LINUX_INCLUDE) -include $(LINUX_INCLUDE)/generated/autoconf.h -I$(KERNDIR)/arch/arm64/include -I$(KERNDIR)/arch/arm64/include/generated -I$(KERNDIR)/arch/arm64/include/generated/uapi -I$(KERNDIR)/arch/arm64/include/generated/asm -I$(KERNDIR)/include/uapi -I$(KERNDIR)/include/generated/uapi -I$(KERNDIR)/arch/arm64/include/uapi -Wall -Wstrict-prototypes -Wno-trigraphs -O2 -fno-strict-aliasing -fno-common -fno-pic -pipe -ffreestanding -fomit-frame-pointer -g -fno-stack-protector -Wdeclaration-after-statement -Wno-pointer-sign -mcmodel=large +KFLAGS := -D__LINUX_ARM_ARCH__=8 -D__KERNEL__ -DPTRS_ARE_64BITS -DLONGS_ARE_64BITS -nostdinc -isystem $(KFLAG_INCLD) -I$(LINUX_INCLUDE) -include $(LINUX_INCLUDE)/generated/autoconf.h -I$(KERNDIR)/arch/arm64/include -I$(KERNDIR)/arch/arm64/include/generated -I$(KERNDIR)/arch/arm64/include/generated/uapi -I$(KERNDIR)/arch/arm64/include/generated/asm -I$(KERNDIR)/include/uapi -I$(KERNDIR)/include/generated/uapi -I$(KERNDIR)/arch/arm64/include/uapi -Wall -Wstrict-prototypes -Wno-trigraphs -O2 -fno-strict-aliasing -fno-common -fno-pic -pipe -ffreestanding -fomit-frame-pointer -g -fno-stack-protector -Wno-frame-address -Wno-address-of-packed-member -Wno-pointer-sign -mcmodel=large endif ifneq ($(targetplat),user) diff --git a/make/Makefile.linux-kernel b/make/Makefile.linux-kernel index a9b5b25..15cf73c 100644 --- a/make/Makefile.linux-kernel +++ b/make/Makefile.linux-kernel @@ -1,6 +1,6 @@ # $Id: Makefile.linux-kernel,v 1.27 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-kernel-2_6 b/make/Makefile.linux-kernel-2_6 index f203da1..10d5ce2 100644 --- a/make/Makefile.linux-kernel-2_6 +++ b/make/Makefile.linux-kernel-2_6 @@ -1,6 +1,6 @@ # $Id: Makefile.linux-kernel-2_6,v 1.40 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-kernel-3_6 b/make/Makefile.linux-kernel-3_6 index b3df440..357fd0a 100644 --- a/make/Makefile.linux-kernel-3_6 +++ b/make/Makefile.linux-kernel-3_6 @@ -1,6 +1,6 @@ # $Id: Makefile.linux-kernel-3_6,v 1.2 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-kernel-4_18 b/make/Makefile.linux-kernel-4_18 index 82b09cd..2adf6d1 100644 --- a/make/Makefile.linux-kernel-4_18 +++ b/make/Makefile.linux-kernel-4_18 @@ -1,6 +1,6 @@ # $Id: Makefile.linux-kernel-4_18,v 1.00 $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-kernel-4_4 b/make/Makefile.linux-kernel-4_4 index 2ad61c6..bedadf7 100644 --- a/make/Makefile.linux-kernel-4_4 +++ b/make/Makefile.linux-kernel-4_4 @@ -1,6 +1,6 @@ # $Id: Makefile.linux-kernel-2_6,v 1.40 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-kmodule b/make/Makefile.linux-kmodule index 422407f..b71e5e1 100644 --- a/make/Makefile.linux-kmodule +++ b/make/Makefile.linux-kmodule @@ -1,6 +1,6 @@ # $Id: Makefile.linux-kmodule-3_6,v 1.2 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-slk b/make/Makefile.linux-slk index 2badfe3..d381d57 100644 --- a/make/Makefile.linux-slk +++ b/make/Makefile.linux-slk @@ -1,6 +1,6 @@ # $Id: Makefile.linux-slk Exp $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-x86-5_10 b/make/Makefile.linux-x86-5_10 index 099e24e..ced4c17 100644 --- a/make/Makefile.linux-x86-5_10 +++ b/make/Makefile.linux-x86-5_10 @@ -1,6 +1,6 @@ # $Id: Makefile.linux-gts,v 0.1 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-x86-64-fc28 b/make/Makefile.linux-x86-64-fc28 index 05ebf9c..a9b2b7f 100644 --- a/make/Makefile.linux-x86-64-fc28 +++ b/make/Makefile.linux-x86-64-fc28 @@ -1,6 +1,6 @@ # $Id: Makefile.linux-gts,v 0.1 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-x86-6_10 b/make/Makefile.linux-x86-6_10 new file mode 100644 index 0000000..22c7b84 --- /dev/null +++ b/make/Makefile.linux-x86-6_10 @@ -0,0 +1,242 @@ +# $Id: Makefile.linux-gts,v 0.1 Broadcom SDK $ +# +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. +# +# Permission is granted to use, copy, modify and/or distribute this +# software under either one of the licenses below. +# +# License Option 1: GPL +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License, version 2, as +# published by the Free Software Foundation (the "GPL"). +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License version 2 (GPLv2) for more details. +# +# You should have received a copy of the GNU General Public License +# version 2 (GPLv2) along with this source code. +# +# +# License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license +# +# This software is governed by the Broadcom Open Network Switch APIs license: +# https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ +# +# + +# +# x86_64 build for Fedora 28 - system make file. +# +# + + +############################################################################# +# this segment is custom and not sourced from any existing makefile # +# (base thanks to http:confluence.broadcom.com/display/NTSWSW/X86+System) # +############################################################################# + +# set up a basic feature list. tcl, etc. # +#ifeq (,$(FEATURE_LIST)) +#FEATURE_LIST = TCL BFD PTP CINT L3 I2C MEM_SCAN EDITLINE BCM_SAL_PROFILE CUSTOMER TEST CHASSIS MSTP RCPU +#endif + +# some basic path variables for tools and kernel source, etc # + +export BINUTILSVER := 2.41 +RHEL_VERSION=$(shell sed -n 's/.*release *\([0-9]\+\)\..*/\1/p' /etc/redhat-release) + +# +# For ESW compilation, suppress 'stringop-overflow' +# +ifeq ($(BCM_ESW_SUPPORT),1) + OPT_CFLAGS += -Wno-error=stringop-overflow +endif + +export GCCVER := 14.1.0 +TOOLCHAIN_DIR = /projects/ntsw-tools/linux/gcc/$(GCCVER) +ifneq ($(DEBUG_OPTIMIZE),FALSE) +# { + # These flags are required for -O2 'optimized' compilation + # We leave the suppression of array-bounds since, currently, + # GCC emits many 'false positive' errors of this kind (among a + # few that are justified) + OPT_CFLAGS += -Wno-error=array-bounds= +# } +endif + +#Valgrind does not have symbolic traceback on newer gcc versions +ifeq (1,$(VALGRIND_SUPPORT)) + use_gcc_8_1_0 = 1 +endif + +ifeq (1,$(use_gcc_8_1_0)) + ifeq ($(targetplat),user) + # GCC 8.1 does not work with binutils 2.41 and newer + export BINUTILSVER := 2.38 + export GCCVER := 8.1.0 + TOOLCHAIN_DIR = /tools/oss/packages/x86_64-rhel$(RHEL_VERSION)/gcc/$(GCCVER) + endif +endif + +BINUTILS_DIR = /tools/oss/packages/x86_64-rhel$(RHEL_VERSION)/binutils/$(BINUTILSVER)/bin +export TCL860 := 1 +$(info INFO from make/Makefile.linux-x86-6_10. GCCVER is $(GCCVER). BINUTILSVER is $(BINUTILSVER). TOOLCHAIN_DIR is $(TOOLCHAIN_DIR)) + +# For GCC versions >= 4.7 +USE_GCC_TOOLS := 1 +#enables executables > 2GB +#CFLAGS += -mcmodel=medium + +TARGET_MACHINE ?= x86_64 +KERNDIR ?= /projects/ntsw-tools/linux/linux-6.10.7 + +# set up cross compile prefix, tools dir variables. # +#export CROSS_COMPILE := x86_64-fedora-linux-gnu- +export TOOLS_DIR := $(TOOLCHAIN_DIR)/bin + +# architecture. # +ARCH = x86_64 +#TARGET_ARCHITECTURE = x86_64-fedora-linux-gnu +TARGET_ARCHITECTURE := x86_64-pc-linux-gnu +TOOLCHAIN_BASE_DIR := $(TOOLCHAIN_DIR) + +ifeq (,$(BUILD_32BITS_EXEC)) +TOOLCHAIN_LIB_DIR:= $(TOOLCHAIN_DIR)/lib64 +else +TOOLCHAIN_LIB_DIR:= $(TOOLCHAIN_DIR)/lib +endif +# set up paths. # +#export LIBRARY_PATH := $(TOOLCHAIN_LIB_DIR):$(LIBRARY_PATH) +export PATH := $(TOOLS_DIR):$(BINUTILS_DIR):$(KERNDIR):$(PATH) + +# set up SYSINC path # +export SYSINC := $(TOOLCHAIN_DIR)/lib/gcc/$(TARGET_ARCHITECTURE)/$(GCCVER)/include + +# CFLAGS/CFGFLAGS # +ifdef SAND_CHIPS +CFGFLAGS += -D__DUNE_GTS_BCM_CPU__ +endif +CFGFLAGS += -DUSE_LINUX_BDE_MMAP=1 +#CFGFLAGS += -DBDE_LINUX_USE_MSI_INTERRUPT +# +#Flags to prevent gcc 8.1.0 new warnings to appear as errors. +#(All these flags have been removed so as to activate the maximal types of +#warning) +# +#OPT_CFLAGS += -Wno-error=unused-value +#OPT_CFLAGS += -Wno-error=unused-but-set-variable +#OPT_CFLAGS += -Wno-error=maybe-uninitialized +#OPT_CFLAGS += -Wno-error=aggressive-loop-optimizations +#OPT_CFLAGS += -Wno-error=array-bounds + +# set up KFLAGS appropriately. # +# -fno-builtin needed for using kernel's version of memcpy instead of the gcc inline version +ifeq (,$(KFLAGS)) +# { + KFLAGS := -I$(KERNDIR) -nostdinc -isystem $(SYSINC) -Iinclude -I$(KERNDIR)/arch/x86/include -I$(KERNDIR)/arch/x86/include/asm -I$(KERNDIR)/arch/x86/include/generated -I$(KERNDIR)/arch/x86/include/generated/uapi -I$(KERNDIR)/arch/x86/include/uapi -I$(KERNDIR)/include -I$(KERNDIR)/include/generated -I$(KERNDIR)/include/uapi -include $(KERNDIR)/include/generated/autoconf.h -D__KERNEL__ -DNDEBUG -Wundef -Wno-error=unused-value -Wno-error=cpp -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Wno-format-security -O2 -m64 -mtune=generic -mno-red-zone -mcmodel=kernel -funit-at-a-time -fstack-protector -DCONFIG_AS_CFI=1 -DCONFIG_AS_CFI_SIGNAL_FRAME=1 -pipe -Wno-sign-compare -fno-asynchronous-unwind-tables -Wframe-larger-than=1024 -fno-omit-frame-pointer -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fno-dwarf2-cfi-asm -fno-builtin + # + # Current version of CLANG seems to not recognize some of the options of kernel FLAGS. + # +ifneq (1,$(USE_CLANG)) +# { + KFLAGS += -Wno-error=maybe-uninitialized -lc -fno-delete-null-pointer-checks -maccumulate-outgoing-args -fconserve-stack -mpreferred-stack-boundary=3 +# } +else +# { + KFLAGS += -Wno-error=address-of-packed-member +# } +endif +ifeq (1,$(NO_PRECOMPILED_MODULE)) +# { + KFLAGS += -DNO_PRECOMPILED_MODULE=1 + export KFLAGS +# } +else +# { + KFLAGS += -DNO_PRECOMPILED_MODULE=0 +# } +endif + +# } +endif + +export LIBNSL_DEPRECATED := 1 + +###################################################################### +# this segment comes from make/Makefile.linux-x86-smp_generic_64-2_6 # +###################################################################### +CFGFLAGS += -DSAL_SPL_LOCK_ON_IRQ + +ifeq (,$(BUILD_32BITS_EXEC)) +CFGFLAGS += -DPTRS_ARE_64BITS -DLONGS_ARE_64BITS +else +CFLAGS += -m32 +EXTRA_USER_LDFLAGS += -m32 +CFGFLAGS += -DSAL_BDE_32BIT_USER_64BIT_KERNEL +endif +CFGFLAGS += -DPHYS_ADDRS_ARE_64BITS +CFLAGS += -fcf-protection + + +########################################################################################### +# This segment comes from make/Makefile.linux-x86-generic-common-2_6 (with modifications) # +########################################################################################### + +# Default architecture +ifeq (,$(ARCH)) +ARCH = x86_64 +endif + +# Noisy kernel build +KBUILD_VERBOSE = 1 + +export ARCH KBUILD_VERBOSE KERNDIR + +# Default Linux include directory +ifeq (,$(LINUX_INCLUDE)) +LINUX_INCLUDE := $(KERNDIR)/include +endif + +# autoconf.h was moved in later kernels +AUTOCONF = $(KERNDIR)/include/generated/autoconf.h +ifeq (,$(shell ls $(AUTOCONF) 2>/dev/null)) +AUTOCONF = $(KERNDIR)/include/linux/autoconf.h +endif + +# gcc system include path +#SYSINC = $(shell gcc -print-search-dirs | grep install | cut -c 10-)include + + +############################################################## +# This segment comes from make/Makefile.linux-x86-common-2_6 # +############################################################## +CFGFLAGS += -DSYS_BE_PIO=0 -DSYS_BE_PACKET=0 -DSYS_BE_OTHER=0 +ENDIAN = LE_HOST=1 +CFGFLAGS += -D$(ENDIAN) +CFGFLAGS += -DBCM_PLATFORM_STRING=\"X86\" +CFGFLAGS += -DSAL_BDE_DMA_MEM_DEFAULT=192 + +HASH := \# +# Extra variables. +EXTRA_CFLAGS = -D"KBUILD_STR(s)=$(HASH)s" $(basename_flags) $(modname_flags) + +comma = , +basetarget = $(basename $(notdir $@)) +modname = $(basetarget) + +name-fix = $(subst $(comma),_,$(subst -,_,$1)) +basename_flags = -D"KBUILD_BASENAME=KBUILD_STR($(call name-fix,$(basetarget)))" +modname_flags = $(if $(filter 1,$(words $(modname))),\ +-D"KBUILD_MODNAME=KBUILD_STR($(call name-fix,$(modname)))") + +# Default open source target build +OPENSRC_BUILD ?= fed21-x86_64 + +ifneq ($(targetplat),user) +# By default we exclude -Werror from x86 kernel builds +BCM_CFLAGS = -Wall +include ${SDK}/make/Makefile.linux-kernel-4_18 +endif diff --git a/make/Makefile.linux-x86-common-2_6 b/make/Makefile.linux-x86-common-2_6 index c3661c1..f9c78bd 100644 --- a/make/Makefile.linux-x86-common-2_6 +++ b/make/Makefile.linux-x86-common-2_6 @@ -1,6 +1,6 @@ # $Id: Makefile.linux-x86-common-2_6,v 1.13 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-x86-generic-common-2_6 b/make/Makefile.linux-x86-generic-common-2_6 index d3db429..9ddcdf9 100644 --- a/make/Makefile.linux-x86-generic-common-2_6 +++ b/make/Makefile.linux-x86-generic-common-2_6 @@ -1,6 +1,6 @@ # $Id: Makefile.linux-x86-generic-common-2_6,v 1.2 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/make/Makefile.linux-x86-smp_generic_64-2_6 b/make/Makefile.linux-x86-smp_generic_64-2_6 index 243e32a..c8fe7fa 100644 --- a/make/Makefile.linux-x86-smp_generic_64-2_6 +++ b/make/Makefile.linux-x86-smp_generic_64-2_6 @@ -1,6 +1,6 @@ # $Id: Makefile.linux-x86-smp_generic_64-2_6,v 1.5 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. @@ -32,10 +32,22 @@ CFGFLAGS += -DPTRS_ARE_64BITS CFGFLAGS += -DPHYS_ADDRS_ARE_64BITS CFGFLAGS += -DSAL_SPL_LOCK_ON_IRQ +ifneq ($(ESW_CHIPS)$(LTSW_CHIPS),) +# Glibc 2.27 or later version doesn't support SVID libm error handling. +# Building tcl 8.3.3 with the new toolchain will occur errors. +export TCL840 := 1 +endif + include ${SDK}/make/Makefile.linux-x86-generic-common-2_6 +GCC_VER_MAJOR := $(shell $(CC) -dumpversion 2>/dev/null | cut -f1 -d.) + ifeq (,$(KFLAGS)) KFLAGS := -nostdinc -isystem $(SYSINC) -I$(KERNDIR)/include -I$(KERNDIR)/arch/x86/include -include $(AUTOCONF) -D__KERNEL__ -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Werror-implicit-function-declaration -Wno-format-security -fno-delete-null-pointer-checks -Os -m64 -mtune=generic -mno-red-zone -fno-pie -mcmodel=kernel -DCONFIG_AS_CFI=1 -DCONFIG_AS_CFI_SIGNAL_FRAME=1 -pipe -Wno-sign-compare -fno-asynchronous-unwind-tables -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -fno-stack-protector -fomit-frame-pointer -g -Wdeclaration-after-statement -Wno-pointer-sign +ifeq "$(shell expr $(GCC_VER_MAJOR) \>= 12)" "1" +KFLAGS += -std=gnu11 -Wno-error=attributes -Wno-error=declaration-after-statement +KFLAGS += -Wno-attributes -Wno-declaration-after-statement +endif ifneq (1,$(USE_CLANG)) KFLAGS += -funit-at-a-time -maccumulate-outgoing-args endif @@ -46,6 +58,13 @@ ifneq (,$(shell ls $(LINUX_UAPI) 2>/dev/null)) KFLAGS += -I$(LINUX_INCLUDE)/uapi -I$(LINUX_INCLUDE)/generated/uapi -I$(KERNDIR)/arch/x86/include/generated -I$(KERNDIR)/arch/x86/include/uapi -I$(KERNDIR)/arch/x86/include/generated/uapi endif +ifeq "$(shell expr $(GCC_VER_MAJOR) \>= 12)" "1" +KFLAGS += -mfunction-return=thunk-extern -fpatchable-function-entry=16,16 +KFLAGS += -mindirect-branch=thunk-extern -mindirect-branch-cs-prefix +# IBT: emit ENDBR so objtool "relocation to !ENDBR" warnings are resolved +KFLAGS += -fcf-protection=branch +endif + ifdef LTSW_CHIPS # Hardware interface (see $SDKLT/bcma/sys/probe directory) SYSTEM_INTERFACE ?= ngbde diff --git a/make/Makefile.linux-xlr b/make/Makefile.linux-xlr index 6d2adc3..6ce0f95 100644 --- a/make/Makefile.linux-xlr +++ b/make/Makefile.linux-xlr @@ -1,6 +1,6 @@ # $Id: Makefile.linux-xlr-4_19,v 0.1 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/src/bcm/common/pktio/bcmcnet/hmi/cmicr/bcmcnet_cmicr2_pdma_rxtx.c b/src/bcm/common/pktio/bcmcnet/hmi/cmicr/bcmcnet_cmicr2_pdma_rxtx.c new file mode 100644 index 0000000..9cf1c7d --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/hmi/cmicr/bcmcnet_cmicr2_pdma_rxtx.c @@ -0,0 +1,384 @@ +/*! \file bcmcnet_cmicr2_pdma_rxtx.c + * + * Utility routines for BCMCNET hardware (CMICr2) specific Tx. + * All others leverage CMICr stuffs. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include +#include + +#define TX_DCB_STAT_SET(r, f) TX_DCB_SET(r, 3, f) +#define TX_DCB_CTRL_HGf_SET(r) TX_DCB_HGf_SET(r, 1) +#define TX_DCB_CTRL_HGf_CLR(r) TX_DCB_HGf_SET(r, 0) +#define TX_DCB_CTRL_PURGEf_SET(r) (r).tx_dcb[2] |= 1 << 23 +#define TX_DCB_CTRL_PURGEf_CLR(r) (r).tx_dcb[2] &= ~(1 << 23) +#define TX_DCB_CTRL_PROFf_SET(r, f) (r).tx_dcb[2] = ((r).tx_dcb[2] & ~(0x7 << 20)) | (((f) & 0x7) << 20) + +/*! + * Configure Tx descriptor + */ +static inline void +cmicr2_tx_desc_config(volatile TX_DCB_t *td, uint64_t addr, uint32_t len, + uint32_t prof, uint16_t flags) +{ + TX_DCB_ADDR_LOf_SET(*td, addr); + TX_DCB_ADDR_HIf_SET(*td, DMA_TO_BUS_HI(addr >> 32)); + TX_DCB_STAT_SET(*td, 0); + + if (flags & PDMA_TX_HIGIG_PKT) { + TX_DCB_CTRL_HGf_SET(*td); + } else { + TX_DCB_CTRL_HGf_CLR(*td); + } + if (flags & PDMA_TX_PURGE_PKT) { + TX_DCB_CTRL_PURGEf_SET(*td); + } else { + TX_DCB_CTRL_PURGEf_CLR(*td); + } + TX_DCB_CTRL_PROFf_SET(*td, prof); + TX_DCB_BYTE_COUNTf_SET(*td, len); + + MEMORY_BARRIER; +} + +/*! + * Chain Tx descriptor + */ +static inline void +cmicr2_tx_desc_chain(volatile TX_DCB_t *td, int chain) +{ + if (chain) { + TX_DCB_CHAINf_SET(*td, 1); + } else { + TX_DCB_CHAINf_SET(*td, 0); + } + + MEMORY_BARRIER; +} + +/*! + * Get unused descriptors in a Tx ring + */ +static inline int +cmicr2_pdma_tx_ring_unused(struct pdma_tx_queue *txq) +{ + /* Leave one descriptor unused so as not to halt */ + return (txq->nb_desc + txq->dirt - txq->curr - 1) % txq->nb_desc; +} + +/*! + * Fetch Tx vring + */ +static int +cmicr2_pdma_tx_vring_fetch(struct pdma_hw *hw, struct pdma_tx_queue *txq, + struct pdma_tx_buf *pbuf) +{ + struct pdma_dev *dev = hw->dev; + volatile TX_DCB_t *ring = (volatile TX_DCB_t *)txq->ring; + struct pdma_tx_queue *vtxq = NULL; + volatile TX_DCB_t *vring = NULL; + uint32_t rm; + + vtxq = (struct pdma_tx_queue *)dev->ctrl.vnet_txq[txq->queue_id]; + vring = (volatile TX_DCB_t *)vtxq->ring; + if (!vring || !TX_DCB_BYTE_COUNTf_GET(vring[vtxq->curr])) { + return SHR_E_UNAVAIL; + } + + /* Fetch vring descriptor */ + rm = TX_DCB_DESC_REMAINf_GET(ring[txq->curr]); + TX_DCB_SET(ring[txq->curr], 0, TX_DCB_GET(vring[vtxq->curr], 0)); + TX_DCB_SET(ring[txq->curr], 1, TX_DCB_GET(vring[vtxq->curr], 1)); + TX_DCB_SET(ring[txq->curr], 2, TX_DCB_GET(vring[vtxq->curr], 2)); + TX_DCB_SET(ring[txq->curr], 3, TX_DCB_GET(vring[vtxq->curr], 3)); + TX_DCB_DESC_REMAINf_SET(ring[txq->curr], rm); + TX_DCB_BYTE_COUNTf_SET(vring[vtxq->curr], 0); + + MEMORY_BARRIER; + + pbuf->dma = TX_DCB_ADDR_LOf_GET(vring[vtxq->curr]); + pbuf->len = TX_DCB_BYTE_COUNTf_GET(ring[txq->curr]); + vtxq->curr = (vtxq->curr + 1) % vtxq->nb_desc; + + return SHR_E_NONE; +} + +/*! + * Check Tx ring + */ +static inline int +cmicr2_pdma_tx_ring_check(struct pdma_hw *hw, struct pdma_tx_queue *txq) +{ + struct pdma_dev *dev = hw->dev; + + if (dev->suspended) { + txq->stats.xoffs++; + if (dev->tx_suspend) { + dev->tx_suspend(dev, txq->queue_id); + return SHR_E_BUSY; + } + if (!(txq->state & PDMA_TX_QUEUE_POLL)) { + return SHR_E_BUSY; + } + } + + if (cmicr2_pdma_tx_ring_unused(txq)) { + return SHR_E_NONE; + } + + sal_spinlock_lock(txq->lock); + if (!cmicr2_pdma_tx_ring_unused(txq)) { + txq->status |= PDMA_TX_QUEUE_XOFF; + txq->stats.xoffs++; + if (dev->tx_suspend) { + dev->tx_suspend(dev, txq->queue_id); + } + sal_spinlock_unlock(txq->lock); + return SHR_E_BUSY; + } + sal_spinlock_unlock(txq->lock); + + return SHR_E_NONE; +} + +/*! + * \brief Start packet transmission + * + * \param [in] hw HW structure point. + * \param [in] txq Tx queue structure point. + * \param [in] buf Tx packet buffer. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +cmicr2_pdma_pkt_xmit(struct pdma_hw *hw, struct pdma_tx_queue *txq, void *buf) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + volatile TX_DCB_t *ring = (volatile TX_DCB_t *)txq->ring; + struct pdma_tx_buf *pbuf = NULL; + struct pkt_hdr *pkh = NULL; + dma_addr_t addr; + uint32_t curr; + int retry = 5000000; + int rv; + + if (dev->tx_suspend) { + sal_spinlock_lock(txq->mutex); + } else { + rv = sal_sem_take(txq->sem, BCMCNET_TX_RSRC_WAIT_USEC); + if (rv == -1) { + CNET_ERROR(hw->unit, "Timeout waiting for Tx resources\n"); + return SHR_E_TIMEOUT; + } + } + + /* Check Tx resource */ + if (dev->tx_suspend) { + /* Suspend Tx if no resource */ + rv = cmicr2_pdma_tx_ring_check(hw, txq); + if (SHR_FAILURE(rv)) { + sal_spinlock_unlock(txq->mutex); + return rv; + } + } else { + /* Abort Tx if a fatal error happened */ + if (txq->status & PDMA_TX_QUEUE_XOFF) { + sal_sem_give(txq->sem); + return SHR_E_RESOURCE; + } + } + + /* Setup the new descriptor */ + curr = txq->curr; + pbuf = &txq->pbuf[curr]; + if (dev->mode == DEV_MODE_HNET && !buf) { + rv = cmicr2_pdma_tx_vring_fetch(hw, txq, pbuf); + if (SHR_FAILURE(rv)) { + sal_spinlock_unlock(txq->mutex); + return SHR_E_EMPTY; + } + txq->state |= PDMA_TX_QUEUE_BUSY; + } else { + pbuf->adj = 1; + pkh = bm->tx_buf_get(dev, txq, pbuf, buf); + if (!pkh) { + txq->stats.dropped++; + if (dev->tx_suspend) { + sal_spinlock_unlock(txq->mutex); + } else { + sal_sem_give(txq->sem); + } + return SHR_E_RESOURCE; + } + bm->tx_buf_dma(dev, txq, pbuf, &addr); + cmicr2_tx_desc_config(&ring[curr], addr, pbuf->len, pkh->hdr_prof, pkh->attrs); + } + + /* Notify HNET to process if needed */ + if (dev->mode == DEV_MODE_VNET) { + if (!TX_DCB_BYTE_COUNTf_GET(ring[(curr + txq->nb_desc - 1) % txq->nb_desc])) { + dev->xnet_wake(dev); + } + } + + /* Update the indicators */ + curr = (curr + 1) % txq->nb_desc; + txq->curr = curr; + + /* Start DMA if in chain mode */ + if (dev->flags & PDMA_CHAIN_MODE) { + if (txq->state & PDMA_TX_QUEUE_POLL) { + do { + rv = hw->dops.tx_ring_clean(hw, txq, txq->nb_desc - 1); + if (rv != (int)txq->nb_desc - 1) { + break; + } + sal_usleep(1); + } while (retry--); + if (retry < 0) { + CNET_ERROR(hw->unit, "Last Tx could not get done in given time\n"); + } + } + sal_spinlock_lock(txq->lock); + if (txq->dirt == txq->halt && txq->dirt != curr) { + hw->hdls.chan_stop(hw, txq->chan_id); + cmicr2_tx_desc_chain(&ring[(curr + txq->nb_desc - 1) % txq->nb_desc], 0); + hw->hdls.chan_setup(hw, txq->chan_id, + txq->ring_addr + sizeof(TX_DCB_t) * txq->halt); + hw->hdls.chan_start(hw, txq->chan_id); + txq->halt = curr; + } + sal_spinlock_unlock(txq->lock); + } + + /* Kick off DMA */ + txq->halt_addr = txq->ring_addr + sizeof(TX_DCB_t) * curr; + hw->hdls.chan_goto(hw, txq->chan_id, txq->halt_addr); + + /* Count the packets/bytes */ + txq->stats.packets++; + txq->stats.bytes += pbuf->len; + + /* Clean up ring if in polling mode */ + if (txq->state & PDMA_TX_QUEUE_POLL && + cmicr2_pdma_tx_ring_unused(txq) <= (int)txq->free_thresh) { + hw->dops.tx_ring_clean(hw, txq, dev->ctrl.budget); + } + + /* Suspend Tx if no resource */ + rv = cmicr2_pdma_tx_ring_check(hw, txq); + if (SHR_FAILURE(rv)) { + if (dev->mode == DEV_MODE_VNET) { + dev->xnet_wake(dev); + } + + if (txq->state & PDMA_TX_QUEUE_POLL) { + /* In polling mode, must wait till the ring is available */ + do { + hw->dops.tx_ring_clean(hw, txq, dev->ctrl.budget); + if (!(txq->status & PDMA_TX_QUEUE_XOFF) || + !(txq->state & PDMA_TX_QUEUE_ACTIVE)) { + break; + } + sal_usleep(1); + } while (retry--); + if (retry < 0) { + CNET_ERROR(hw->unit, "Fatal error: Tx ring is full, packets can not been transmitted\n"); + if (!dev->tx_suspend) { + sal_sem_give(txq->sem); + return SHR_E_RESOURCE; + } + } + } else { + /* In interrupt mode, the handle thread will wake up Tx */ + if (!dev->tx_suspend) { + return SHR_E_NONE; + } + } + } + + if (dev->tx_suspend) { + sal_spinlock_unlock(txq->mutex); + } else { + sal_sem_give(txq->sem); + } + + return SHR_E_NONE; +} + +/*! + * Attach device driver + */ +int +bcmcnet_cmicr2_pdma_driver_attach(struct pdma_dev *dev) +{ + struct pdma_hw *hw = NULL; + + /* Allocate memory for HW data */ + hw = sal_alloc(sizeof(*hw), "bcmcnetPdmaHw"); + if (!hw) { + return SHR_E_MEMORY; + } + sal_memset(hw, 0, sizeof(*hw)); + hw->unit = dev->unit; + hw->dev = dev; + dev->ctrl.hw = hw; + + bcmcnet_cmicr_pdma_hw_hdls_init(hw); + bcmcnet_cmicr_pdma_desc_ops_init(hw); + + hw->dops.pkt_xmit = cmicr2_pdma_pkt_xmit; + + dev->flags |= PDMA_NO_FCS; + + return SHR_E_NONE; +} + +/*! + * Detach device driver + */ +int +bcmcnet_cmicr2_pdma_driver_detach(struct pdma_dev *dev) +{ + if (dev->ctrl.hw) { + sal_free(dev->ctrl.hw); + } + dev->ctrl.hw = NULL; + + return SHR_E_NONE; +} diff --git a/src/bcm/common/pktio/bcmcnet/hmi/cmicr/bcmcnet_cmicr_pdma_hw.c b/src/bcm/common/pktio/bcmcnet/hmi/cmicr/bcmcnet_cmicr_pdma_hw.c new file mode 100644 index 0000000..c177e83 --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/hmi/cmicr/bcmcnet_cmicr_pdma_hw.c @@ -0,0 +1,720 @@ +/*! \file bcmcnet_cmicr_pdma_hw.c + * + * Utility routines for handling BCMCNET hardware (CMICr). + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include + +/*! + * Read 32-bit register + */ +static inline void +cmicr_pdma_reg_read32(struct pdma_hw *hw, uint32_t addr, uint32_t *data) +{ + if (hw->dev->dev_read32) { + hw->dev->dev_read32(hw->dev, addr, data); + } else { + DEV_READ32(&hw->dev->ctrl, addr, data); + } +} + +/*! + * Write 32-bit register + */ +static inline void +cmicr_pdma_reg_write32(struct pdma_hw *hw, uint32_t addr, uint32_t data) +{ + if (hw->dev->dev_write32) { + hw->dev->dev_write32(hw->dev, addr, data); + } else { + DEV_WRITE32(&hw->dev->ctrl, addr, data); + } +} + +/*! + * Enable interrupt for a channel + */ +static inline void +cmicr_pdma_intr_enable(struct pdma_hw *hw, int cmc, int chan) +{ + uint32_t reg, val; + + if (hw->dev->mode == DEV_MODE_UNET || hw->dev->mode == DEV_MODE_VNET) { + hw->dev->intr_unmask(hw->dev, cmc, chan, 0, 0); + return; + } + + if ((cmc == 0) || (cmc == 1 && chan < 8)) { + reg = PAXB_PDMA_IRQ_ENAB_SET0; + } else { + reg = PAXB_PDMA_IRQ_ENAB_SET1; + } + + val = 1 << chan; + if (cmc == 0) { + val <<= CMICR_IRQ_MASK_SHIFT; + } else if (cmc == 1 && chan < 8) { + val <<= CMICR_IRQ_MASK_SHIFT + CMICR_PDMA_CMC_CHAN; + } else { + val >>= CMICR_IRQ_MASK_SHIFT; + } + + hw->dev->intr_unmask(hw->dev, cmc, chan, reg & 0xfff, val); +} + +/*! + * Disable interrupt for a channel + */ +static inline void +cmicr_pdma_intr_disable(struct pdma_hw *hw, int cmc, int chan) +{ + uint32_t reg, val; + + if (hw->dev->mode == DEV_MODE_UNET || hw->dev->mode == DEV_MODE_VNET) { + hw->dev->intr_mask(hw->dev, cmc, chan, 0, 0); + return; + } + + if ((cmc == 0) || (cmc == 1 && chan < 8)) { + reg = PAXB_PDMA_IRQ_ENAB_CLR0; + } else { + reg = PAXB_PDMA_IRQ_ENAB_CLR1; + } + + val = 1 << chan; + if (cmc == 0) { + val <<= CMICR_IRQ_MASK_SHIFT; + } else if (cmc == 1 && chan < 8) { + val <<= CMICR_IRQ_MASK_SHIFT + CMICR_PDMA_CMC_CHAN; + } else { + val >>= CMICR_IRQ_MASK_SHIFT; + } + + hw->dev->intr_mask(hw->dev, cmc, chan, reg & 0xfff, val); +} + +/*! + * Initialize HW + */ +static int +cmicr_pdma_hw_init(struct pdma_hw *hw) +{ + dev_mode_t mode = DEV_MODE_MAX; + CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_t val_header_size; + + /* Temporarily upgrade work mode to get HW information in VNET mode. */ + if (hw->dev->mode == DEV_MODE_VNET) { + mode = DEV_MODE_VNET; + hw->dev->mode = DEV_MODE_UNET; + } + + hw->info.name = CMICR_DEV_NAME; + hw->info.dev_id = hw->dev->dev_id; + hw->info.num_cmcs = CMICR_PDMA_CMC_MAX; + hw->info.cmc_chans = CMICR_PDMA_CMC_CHAN; + hw->info.num_chans = CMICR_PDMA_CMC_MAX * CMICR_PDMA_CMC_CHAN; + hw->info.rx_dcb_size = CMICR_PDMA_DCB_SIZE; + hw->info.tx_dcb_size = CMICR_PDMA_DCB_SIZE; + hw->hdls.reg_rd32(hw, CMICR_EP_TO_CPU_HEADER_SIZE, + &CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_GET(val_header_size)); + hw->info.rx_ph_size = CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_EP_TO_CPU_HEADER_SIZEf_GET(val_header_size) * 8; + hw->info.tx_ph_size = CMICR_TX_PKT_HDR_SIZE; + + /* Restore work mode to VNET. */ + if (mode == DEV_MODE_VNET) { + hw->dev->mode = DEV_MODE_VNET; + } + + return SHR_E_NONE; +} + +/*! + * Configure HW + */ +static int +cmicr_pdma_hw_config(struct pdma_hw *hw) +{ + struct dev_ctrl *ctrl = &hw->dev->ctrl; + struct pdma_rx_queue *rxq = NULL; + struct pdma_tx_queue *txq = NULL; + uint32_t que_ctrl; + int grp, que; + uint32_t qi; + int ip_if_hdr_endian = 0; + int pipe; + CMIC_CMC_PKTDMA_CTRLr_t pktdma_ctrl; + CMIC_CMC_PKTDMA_INTR_ENABLEr_t pktdma_intr_enable; + CMIC_CMC_PKTDMA_INTR_CLRr_t pktdma_intr_clr; + CMIC_TOP_CONFIGr_t cmic_config; + CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_t pktdma_rxbuf_thresh; + + CMIC_CMC_PKTDMA_INTR_ENABLEr_CLR(pktdma_intr_enable); + CMIC_CMC_PKTDMA_INTR_ENABLEr_DESC_CONTROLLED_INTR_ENABLEf_SET(pktdma_intr_enable, 1); + + CMIC_CMC_PKTDMA_INTR_CLRr_CLR(pktdma_intr_clr); + CMIC_CMC_PKTDMA_INTR_CLRr_DESC_DONE_INTR_CLRf_SET(pktdma_intr_clr, 1); + CMIC_CMC_PKTDMA_INTR_CLRr_DESC_CONTROLLED_INTR_CLRf_SET(pktdma_intr_clr, 1); + CMIC_CMC_PKTDMA_INTR_CLRr_INTR_COALESCING_INTR_CLRf_SET(pktdma_intr_clr, 1); + CMIC_CMC_PKTDMA_INTR_CLRr_DYN_RCNFG_ERR_CLRf_SET(pktdma_intr_clr, 1); + + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[qi]; + grp = rxq->group_id; + que = rxq->chan_id % CMICR_PDMA_CMC_CHAN; + que_ctrl = ctrl->grp[grp].que_ctrl[que]; + pipe = ctrl->grp[grp].pipe[que]; + + hw->hdls.reg_rd32(hw, CMICR_PDMA_RBUF_THRE(grp, que), + &CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_GET(pktdma_rxbuf_thresh)); + CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_ENABLEf_SET(pktdma_rxbuf_thresh, 1); + hw->hdls.reg_wr32(hw, CMICR_PDMA_RBUF_THRE(grp, que), + CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_GET(pktdma_rxbuf_thresh)); + hw->hdls.reg_wr32(hw, CMICR_PDMA_INTR_CLR(grp, que), + CMIC_CMC_PKTDMA_INTR_CLRr_GET(pktdma_intr_clr)); + CMIC_CMC_PKTDMA_CTRLr_CLR(pktdma_ctrl); + if (que_ctrl & PDMA_PKT_BYTE_SWAP) { + CMIC_CMC_PKTDMA_CTRLr_PKTDMA_ENDIANESSf_SET(pktdma_ctrl, 1); + } + if (que_ctrl & PDMA_OTH_BYTE_SWAP) { + CMIC_CMC_PKTDMA_CTRLr_DESC_ENDIANESSf_SET(pktdma_ctrl, 1); + } + if (que_ctrl & PDMA_HDR_BYTE_SWAP) { + CMIC_CMC_PKTDMA_CTRLr_HEADER_ENDIANESSf_SET(pktdma_ctrl, 1); + } + if (!(hw->dev->flags & PDMA_CHAIN_MODE)) { + CMIC_CMC_PKTDMA_CTRLr_ENABLE_CONTINUOUS_DMAf_SET(pktdma_ctrl, 1); + } + CMIC_CMC_PKTDMA_CTRLr_CONTIGUOUS_DESCRIPTORSf_SET(pktdma_ctrl, 1); + CMIC_CMC_PKTDMA_CTRLr_DESC_DONE_INTR_MODEf_SET(pktdma_ctrl, 1); + if (pipe == 1) { + CMIC_CMC_PKTDMA_CTRLr_PIPE_MAPf_SET(pktdma_ctrl, 1); + } else if (pipe != 0) { + return SHR_E_CONFIG; + } + + hw->hdls.reg_wr32(hw, CMICR_PDMA_CTRL(grp, que), + CMIC_CMC_PKTDMA_CTRLr_GET(pktdma_ctrl)); + hw->hdls.reg_wr32(hw, CMICR_PDMA_INTR_ENAB(grp, que), + CMIC_CMC_PKTDMA_INTR_ENABLEr_GET(pktdma_intr_enable)); + } + + for (qi = 0; qi < ctrl->nb_txq; qi++) { + txq = (struct pdma_tx_queue *)ctrl->tx_queue[qi]; + grp = txq->group_id; + que = txq->chan_id % CMICR_PDMA_CMC_CHAN; + que_ctrl = ctrl->grp[grp].que_ctrl[que]; + pipe = ctrl->grp[grp].pipe[que]; + + hw->hdls.reg_wr32(hw, CMICR_PDMA_INTR_CLR(grp, que), + CMIC_CMC_PKTDMA_INTR_CLRr_GET(pktdma_intr_clr)); + CMIC_CMC_PKTDMA_CTRLr_CLR(pktdma_ctrl); + if (que_ctrl & PDMA_PKT_BYTE_SWAP) { + CMIC_CMC_PKTDMA_CTRLr_PKTDMA_ENDIANESSf_SET(pktdma_ctrl, 1); + CMIC_CMC_PKTDMA_CTRLr_HEADER_ENDIANESSf_SET(pktdma_ctrl, 1); + ip_if_hdr_endian = 1; + } + if (que_ctrl & PDMA_OTH_BYTE_SWAP) { + CMIC_CMC_PKTDMA_CTRLr_DESC_ENDIANESSf_SET(pktdma_ctrl, 1); + } + if (que_ctrl & PDMA_HDR_BYTE_SWAP) { + ip_if_hdr_endian = 1; + } + if (!(hw->dev->flags & PDMA_CHAIN_MODE)) { + CMIC_CMC_PKTDMA_CTRLr_ENABLE_CONTINUOUS_DMAf_SET(pktdma_ctrl, 1); + } + CMIC_CMC_PKTDMA_CTRLr_CONTIGUOUS_DESCRIPTORSf_SET(pktdma_ctrl, 1); + CMIC_CMC_PKTDMA_CTRLr_DESC_DONE_INTR_MODEf_SET(pktdma_ctrl, 1); + CMIC_CMC_PKTDMA_CTRLr_DIRECTIONf_SET(pktdma_ctrl, 1); + if (pipe == 1) { + CMIC_CMC_PKTDMA_CTRLr_PIPE_MAPf_SET(pktdma_ctrl, 1); + } else if (pipe != 0) { + return SHR_E_CONFIG; + } + + hw->hdls.reg_wr32(hw, CMICR_PDMA_CTRL(grp, que), + CMIC_CMC_PKTDMA_CTRLr_GET(pktdma_ctrl)); + hw->hdls.reg_wr32(hw, CMICR_PDMA_INTR_ENAB(grp, que), + CMIC_CMC_PKTDMA_INTR_ENABLEr_GET(pktdma_intr_enable)); + } + + hw->hdls.reg_rd32(hw, + CMICR_TOP_CONFIG, &CMIC_TOP_CONFIGr_GET(cmic_config)); + CMIC_TOP_CONFIGr_IP_INTERFACE_HEADER_ENDIANESSf_SET(cmic_config, + ip_if_hdr_endian); + hw->hdls.reg_wr32(hw, + CMICR_TOP_CONFIG, CMIC_TOP_CONFIGr_GET(cmic_config)); + + return SHR_E_NONE; +} + +/*! + * Reset HW + */ +static int +cmicr_pdma_hw_reset(struct pdma_hw *hw) +{ + int gi, qi; + + for (gi = 0; gi < hw->dev->num_groups; gi++) { + if (!hw->dev->ctrl.grp[gi].attached) { + continue; + } + for (qi = 0; qi < CMICR_PDMA_CMC_CHAN; qi++) { + if (1 << qi & hw->dev->ctrl.grp[gi].bm_rxq || + 1 << qi & hw->dev->ctrl.grp[gi].bm_txq) { + hw->hdls.reg_wr32(hw, CMICR_PDMA_CTRL(gi, qi), 0); + } + } + } + + return SHR_E_NONE; +} + +/*! + * Start a channel + */ +static int +cmicr_pdma_chan_start(struct pdma_hw *hw, int chan) +{ + CMIC_CMC_PKTDMA_CTRLr_t pktdma_ctrl; + int grp, que; + + grp = chan / CMICR_PDMA_CMC_CHAN; + que = chan % CMICR_PDMA_CMC_CHAN; + + hw->hdls.reg_rd32(hw, CMICR_PDMA_CTRL(grp, que), + &CMIC_CMC_PKTDMA_CTRLr_GET(pktdma_ctrl)); + CMIC_CMC_PKTDMA_CTRLr_DMA_ENf_SET(pktdma_ctrl, 1); + hw->hdls.reg_wr32(hw, CMICR_PDMA_CTRL(grp, que), + CMIC_CMC_PKTDMA_CTRLr_GET(pktdma_ctrl)); + + MEMORY_BARRIER; + + return SHR_E_NONE; +} + +/*! + * Stop a channel + */ +static int +cmicr_pdma_chan_stop(struct pdma_hw *hw, int chan) +{ + CMIC_CMC_PKTDMA_CTRLr_t pktdma_ctrl; + CMIC_CMC_PKTDMA_INTR_ENABLEr_t pktdma_intr_enable; + CMIC_CMC_PKTDMA_INTR_CLRr_t pktdma_intr_clr; + CMIC_CMC_PKTDMA_STATr_t pktdma_stat; + int grp, que; + int retry = CMICR_HW_RETRY_TIMES; + + grp = chan / CMICR_PDMA_CMC_CHAN; + que = chan % CMICR_PDMA_CMC_CHAN; + + hw->hdls.reg_rd32(hw, CMICR_PDMA_STAT(grp, que), + &CMIC_CMC_PKTDMA_STATr_GET(pktdma_stat)); + + if (CMIC_CMC_PKTDMA_STATr_CHAIN_DONEf_GET(pktdma_stat)) { + hw->hdls.reg_rd32(hw, CMICR_PDMA_CTRL(grp, que), + &CMIC_CMC_PKTDMA_CTRLr_GET(pktdma_ctrl)); + CMIC_CMC_PKTDMA_CTRLr_DMA_ENf_SET(pktdma_ctrl, 0); + hw->hdls.reg_wr32(hw, CMICR_PDMA_CTRL(grp, que), + CMIC_CMC_PKTDMA_CTRLr_GET(pktdma_ctrl)); + return SHR_E_NONE; + } + + /* if chain done is 0, abort */ + hw->hdls.reg_rd32(hw, CMICR_PDMA_CTRL(grp, que), + &CMIC_CMC_PKTDMA_CTRLr_GET(pktdma_ctrl)); + CMIC_CMC_PKTDMA_CTRLr_DMA_ENf_SET(pktdma_ctrl, 1); + CMIC_CMC_PKTDMA_CTRLr_ABORT_DMAf_SET(pktdma_ctrl, 1); + hw->hdls.reg_wr32(hw, CMICR_PDMA_CTRL(grp, que), + CMIC_CMC_PKTDMA_CTRLr_GET(pktdma_ctrl)); + + MEMORY_BARRIER; + + do { + hw->hdls.reg_rd32(hw, CMICR_PDMA_STAT(grp, que), + &CMIC_CMC_PKTDMA_STATr_GET(pktdma_stat)); + } while (!CMIC_CMC_PKTDMA_STATr_CHAIN_DONEf_GET(pktdma_stat) && (--retry > 0)); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_CTRL(grp, que), + &CMIC_CMC_PKTDMA_CTRLr_GET(pktdma_ctrl)); + CMIC_CMC_PKTDMA_CTRLr_DMA_ENf_SET(pktdma_ctrl, 0); + CMIC_CMC_PKTDMA_CTRLr_ABORT_DMAf_SET(pktdma_ctrl, 0); + hw->hdls.reg_wr32(hw, CMICR_PDMA_CTRL(grp, que), + CMIC_CMC_PKTDMA_CTRLr_GET(pktdma_ctrl)); + + MEMORY_BARRIER; + + CMIC_CMC_PKTDMA_INTR_ENABLEr_CLR(pktdma_intr_enable); + hw->hdls.reg_wr32(hw, CMICR_PDMA_INTR_ENAB(grp, que), + CMIC_CMC_PKTDMA_INTR_ENABLEr_GET(pktdma_intr_enable)); + + MEMORY_BARRIER; + + CMIC_CMC_PKTDMA_INTR_CLRr_CLR(pktdma_intr_clr); + CMIC_CMC_PKTDMA_INTR_CLRr_DESC_DONE_INTR_CLRf_SET(pktdma_intr_clr, 1); + CMIC_CMC_PKTDMA_INTR_CLRr_DESC_CONTROLLED_INTR_CLRf_SET(pktdma_intr_clr, 1); + CMIC_CMC_PKTDMA_INTR_CLRr_INTR_COALESCING_INTR_CLRf_SET(pktdma_intr_clr, 1); + CMIC_CMC_PKTDMA_INTR_CLRr_DYN_RCNFG_ERR_CLRf_SET(pktdma_intr_clr, 1); + hw->hdls.reg_wr32(hw, CMICR_PDMA_INTR_CLR(grp, que), + CMIC_CMC_PKTDMA_INTR_CLRr_GET(pktdma_intr_clr)); + + MEMORY_BARRIER; + + return SHR_E_NONE; +} + +/*! + * Setup a channel + */ +static int +cmicr_pdma_chan_setup(struct pdma_hw *hw, int chan, uint64_t addr) +{ + int grp, que; + + grp = chan / CMICR_PDMA_CMC_CHAN; + que = chan % CMICR_PDMA_CMC_CHAN; + + hw->hdls.reg_wr32(hw, CMICR_PDMA_DESC_LO(grp, que), addr); + hw->hdls.reg_wr32(hw, CMICR_PDMA_DESC_HI(grp, que), DMA_TO_BUS_HI(addr >> 32)); + + MEMORY_BARRIER; + + return SHR_E_NONE; +} + +/*! + * Set halt point for a channel + */ +static int +cmicr_pdma_chan_goto(struct pdma_hw *hw, int chan, uint64_t addr) +{ + int grp, que; + + grp = chan / CMICR_PDMA_CMC_CHAN; + que = chan % CMICR_PDMA_CMC_CHAN; + + hw->hdls.reg_wr32(hw, CMICR_PDMA_DESC_HALT_LO(grp, que), addr); + hw->hdls.reg_wr32(hw, CMICR_PDMA_DESC_HALT_HI(grp, que), DMA_TO_BUS_HI(addr >> 32)); + + MEMORY_BARRIER; + + return SHR_E_NONE; +} + +/*! + * Clear a channel + */ +static int +cmicr_pdma_chan_clear(struct pdma_hw *hw, int chan) +{ + CMIC_CMC_PKTDMA_INTR_CLRr_t pktdma_intr_clr; + int grp, que; + + grp = chan / CMICR_PDMA_CMC_CHAN; + que = chan % CMICR_PDMA_CMC_CHAN; + + CMIC_CMC_PKTDMA_INTR_CLRr_CLR(pktdma_intr_clr); + CMIC_CMC_PKTDMA_INTR_CLRr_DESC_CONTROLLED_INTR_CLRf_SET(pktdma_intr_clr, 1); + hw->hdls.reg_wr32(hw, CMICR_PDMA_INTR_CLR(grp, que), + CMIC_CMC_PKTDMA_INTR_CLRr_GET(pktdma_intr_clr)); + + MEMORY_BARRIER; + + return SHR_E_NONE; +} + +/*! + * Check a channel + */ +static int +cmicr_pdma_chan_check(struct pdma_hw *hw, int chan) +{ + CMIC_CMC_PKTDMA_STATr_t pktdma_stat; + int grp, que; + + grp = chan / CMICR_PDMA_CMC_CHAN; + que = chan % CMICR_PDMA_CMC_CHAN; + + MEMORY_BARRIER; + + hw->hdls.reg_rd32(hw, CMICR_PDMA_STAT(grp, que), + &CMIC_CMC_PKTDMA_STATr_GET(pktdma_stat)); + + return CMIC_CMC_PKTDMA_STATr_DESC_CONTROLLEDf_GET(pktdma_stat); +} + +/*! + * Get interrupt number for a channel + */ +static int +cmicr_pdma_chan_intr_num_get(struct pdma_hw *hw, int chan) +{ + int grp, que; + const int irq_map[CMICR_PDMA_CMC_MAX][CMICR_PDMA_CMC_CHAN] = + {{CMICR_IRQ_CMC0_PKTDMA_CH0_INTR, CMICR_IRQ_CMC0_PKTDMA_CH1_INTR, + CMICR_IRQ_CMC0_PKTDMA_CH2_INTR, CMICR_IRQ_CMC0_PKTDMA_CH3_INTR, + CMICR_IRQ_CMC0_PKTDMA_CH4_INTR, CMICR_IRQ_CMC0_PKTDMA_CH5_INTR, + CMICR_IRQ_CMC0_PKTDMA_CH6_INTR, CMICR_IRQ_CMC0_PKTDMA_CH7_INTR, + CMICR_IRQ_CMC0_PKTDMA_CH8_INTR, CMICR_IRQ_CMC0_PKTDMA_CH9_INTR, + CMICR_IRQ_CMC0_PKTDMA_CH10_INTR, CMICR_IRQ_CMC0_PKTDMA_CH11_INTR, + CMICR_IRQ_CMC0_PKTDMA_CH12_INTR, CMICR_IRQ_CMC0_PKTDMA_CH13_INTR, + CMICR_IRQ_CMC0_PKTDMA_CH14_INTR, CMICR_IRQ_CMC0_PKTDMA_CH15_INTR}, + {CMICR_IRQ_CMC1_PKTDMA_CH0_INTR, CMICR_IRQ_CMC1_PKTDMA_CH1_INTR, + CMICR_IRQ_CMC1_PKTDMA_CH2_INTR, CMICR_IRQ_CMC1_PKTDMA_CH3_INTR, + CMICR_IRQ_CMC1_PKTDMA_CH4_INTR, CMICR_IRQ_CMC1_PKTDMA_CH5_INTR, + CMICR_IRQ_CMC1_PKTDMA_CH6_INTR, CMICR_IRQ_CMC1_PKTDMA_CH7_INTR, + CMICR_IRQ_CMC1_PKTDMA_CH8_INTR, CMICR_IRQ_CMC1_PKTDMA_CH9_INTR, + CMICR_IRQ_CMC1_PKTDMA_CH10_INTR, CMICR_IRQ_CMC1_PKTDMA_CH11_INTR, + CMICR_IRQ_CMC1_PKTDMA_CH12_INTR, CMICR_IRQ_CMC1_PKTDMA_CH13_INTR, + CMICR_IRQ_CMC1_PKTDMA_CH14_INTR, CMICR_IRQ_CMC1_PKTDMA_CH15_INTR}}; + + grp = chan / CMICR_PDMA_CMC_CHAN; + que = chan % CMICR_PDMA_CMC_CHAN; + + if (grp < 0 || grp >= CMICR_PDMA_CMC_MAX) { + return -1; + } + + return irq_map[grp][que]; +} + +/*! + * Enable interrupt for a channel + */ +static int +cmicr_pdma_chan_intr_enable(struct pdma_hw *hw, int chan) +{ + int grp, que; + + grp = chan / CMICR_PDMA_CMC_CHAN; + que = chan % CMICR_PDMA_CMC_CHAN; + + hw->dev->ctrl.grp[grp].irq_mask |= (1 << que); + cmicr_pdma_intr_enable(hw, grp, que); + + return SHR_E_NONE; +} + +/*! + * Disable interrupt for a channel + */ +static int +cmicr_pdma_chan_intr_disable(struct pdma_hw *hw, int chan) +{ + int grp, que; + + grp = chan / CMICR_PDMA_CMC_CHAN; + que = chan % CMICR_PDMA_CMC_CHAN; + + hw->dev->ctrl.grp[grp].irq_mask &= ~(1 << que); + cmicr_pdma_intr_disable(hw, grp, que); + + return SHR_E_NONE; +} + +/*! + * Query interrupt status for a channel + * + * In group mode (interrupt processing per CMC), need to query each channel's + * interrupt status. + * + */ +static int +cmicr_pdma_chan_intr_query(struct pdma_hw *hw, int chan) +{ + CMIC_CMC_PKTDMA_INTRr_t pktdma_intr; + int grp, que; + + grp = chan / CMICR_PDMA_CMC_CHAN; + que = chan % CMICR_PDMA_CMC_CHAN; + + hw->hdls.reg_rd32(hw, CMICR_PDMA_INTR_STAT(grp, que), + &CMIC_CMC_PKTDMA_INTRr_GET(pktdma_intr)); + + return CMIC_CMC_PKTDMA_INTRr_DESC_CONTROLLED_INTRf_GET(pktdma_intr); +} + +/*! + * Check interrupt validity for a channel + * + * In group mode (interrupt processing per CMC), need to check each channel's + * interrupt validity based on its interrupt mask. + * + */ +static int +cmicr_pdma_chan_intr_check(struct pdma_hw *hw, int chan) +{ + int grp, que; + + grp = chan / CMICR_PDMA_CMC_CHAN; + que = chan % CMICR_PDMA_CMC_CHAN; + + if (!(hw->dev->ctrl.grp[grp].irq_mask & (1 << que))) { + return 0; + } + + return cmicr_pdma_chan_intr_query(hw, chan); +} + +/*! + * Coalesce interrupt for a channel + */ +static int +cmicr_pdma_chan_intr_coalesce(struct pdma_hw *hw, int chan, int count, int timer) +{ + CMIC_CMC_PKTDMA_INTR_COALr_t pktdma_intr_col; + int grp, que; + + grp = chan / CMICR_PDMA_CMC_CHAN; + que = chan % CMICR_PDMA_CMC_CHAN; + + CMIC_CMC_PKTDMA_INTR_COALr_CLR(pktdma_intr_col); + CMIC_CMC_PKTDMA_INTR_COALr_ENABLEf_SET(pktdma_intr_col, 1); + CMIC_CMC_PKTDMA_INTR_COALr_COUNTf_SET(pktdma_intr_col, count); + CMIC_CMC_PKTDMA_INTR_COALr_TIMERf_SET(pktdma_intr_col, timer); + hw->hdls.reg_wr32(hw, CMICR_PDMA_INTR_COAL(grp, que), + CMIC_CMC_PKTDMA_INTR_COALr_GET(pktdma_intr_col)); + + return SHR_E_NONE; +} + +/*! + * Dump registers for a channel + */ +static int +cmicr_pdma_chan_reg_dump(struct pdma_hw *hw, int chan) +{ + uint32_t val; + int grp, que; + + grp = chan / CMICR_PDMA_CMC_CHAN; + que = chan % CMICR_PDMA_CMC_CHAN; + + hw->hdls.reg_rd32(hw, CMICR_PDMA_CTRL(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_CTRL: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_DESC_LO(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_DESC_LO: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_DESC_HI(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_DESC_HI: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_CURR_DESC_LO(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_CURR_DESC_LO: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_CURR_DESC_HI(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_CURR_DESC_HI: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_DESC_HALT_LO(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_DESC_HALT_ADDR_LO: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_DESC_HALT_HI(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_DESC_HALT_ADDR_HI: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_COS_CTRL_RX0(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_COS_CTRL_RX_0: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_COS_CTRL_RX1(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_COS_CTRL_RX_1: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_INTR_COAL(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_INTR_COAL: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_RBUF_THRE(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_RXBUF_THRESHOLD_CONFIG: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_STAT(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_STAT: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_COUNT_RX(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_PKT_COUNT_RXPKT: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_COUNT_TX(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_PKT_COUNT_TXPKT: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_COUNT_RX_DROP(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_PKT_COUNT_RXPKT_DROP: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_INTR_ENAB(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_INTR_ENAB: 0x%08x\n", grp, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_INTR_STAT(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_INTR_STAT: 0x%08x\n", grp, val); + + hw->hdls.reg_rd32(hw, CMICR_PDMA_INTR_CLR(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_INTR_CLR: 0x%08x\n", grp, val); + + val = hw->dev->ctrl.grp[grp].irq_mask; + CNET_INFO(hw->unit, "CMIC_CMC%d_IRQ_ENAB: 0x%08x\n", grp, val); + + hw->hdls.reg_rd32(hw, CMICR_EP_TO_CPU_HEADER_SIZE, &val); + CNET_INFO(hw->unit, "CMIC_EP_TO_CPU_HEADER_SIZE: 0x%08x\n", val); + + return SHR_E_NONE; +} + +/*! + * Initialize function pointers + */ +int +bcmcnet_cmicr_pdma_hw_hdls_init(struct pdma_hw *hw) +{ + if (!hw) { + return SHR_E_PARAM; + } + + hw->hdls.reg_rd32 = cmicr_pdma_reg_read32; + hw->hdls.reg_wr32 = cmicr_pdma_reg_write32; + hw->hdls.hw_init = cmicr_pdma_hw_init; + hw->hdls.hw_config = cmicr_pdma_hw_config; + hw->hdls.hw_reset = cmicr_pdma_hw_reset; + hw->hdls.chan_start = cmicr_pdma_chan_start; + hw->hdls.chan_stop = cmicr_pdma_chan_stop; + hw->hdls.chan_setup = cmicr_pdma_chan_setup; + hw->hdls.chan_goto = cmicr_pdma_chan_goto; + hw->hdls.chan_clear = cmicr_pdma_chan_clear; + hw->hdls.chan_check = cmicr_pdma_chan_check; + hw->hdls.chan_intr_num_get = cmicr_pdma_chan_intr_num_get; + hw->hdls.chan_intr_enable = cmicr_pdma_chan_intr_enable; + hw->hdls.chan_intr_disable = cmicr_pdma_chan_intr_disable; + hw->hdls.chan_intr_query = cmicr_pdma_chan_intr_query; + hw->hdls.chan_intr_check = cmicr_pdma_chan_intr_check; + hw->hdls.chan_intr_coalesce = cmicr_pdma_chan_intr_coalesce; + hw->hdls.chan_reg_dump = cmicr_pdma_chan_reg_dump; + + return SHR_E_NONE; +} diff --git a/src/bcm/common/pktio/bcmcnet/hmi/cmicr/bcmcnet_cmicr_pdma_rxtx.c b/src/bcm/common/pktio/bcmcnet/hmi/cmicr/bcmcnet_cmicr_pdma_rxtx.c new file mode 100644 index 0000000..79c2346 --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/hmi/cmicr/bcmcnet_cmicr_pdma_rxtx.c @@ -0,0 +1,1204 @@ +/*! \file bcmcnet_cmicr_pdma_rxtx.c + * + * Utility routines for BCMCNET hardware (CMICr) specific Rx/Tx. + * + * Here are the CMIC specific Rx/Tx routines including DCBs resource allocation + * and clean up, DCBs configuration, Rx buffers allocation, Tx buffers release, + * Rx/Tx packets processing, etc. + * They are shared among all the modes (UNET, KNET, VNET, HNET) and in both of + * user space and kernel space. + * + * The driver uses a ring of DCBs per DMA channel based on Continuous DMA mode. + * The beginning is written to register pointing to the physical address of the + * start of the ring. The ring size is maintained by the driver. A HALT DCB + * physical address is written to DMA register timely to indicate how many DCBs + * can be handled by HW. + * + * When a packet is received, an interrupt is triggered. The handler will go + * through the Rx DCB ring to process the current completed DCB and every + * subsequent DCBs until no one is left. The received packet is processed and + * passed up to the high level SW. After that, a new buffer is allocated and + * the DCB is updated for receiving a new packet. A new HALT DCB is selected + * and its physical address is written to DMA register. + * + * When a packet is transmitted, the driver starts where it left off last time + * in the Tx DCB ring, updates the DCB and writes its physical address to DMA + * register so as to start DMA. Once the transmitting is finished, the handler + * is informed to clean up the buffer based on the work mode. In KNET or HNET + * mode, an interrupt will be triggered. Polling mode is used in CNET or VNET + * mode, the buffers will be cleaned up when the number of dirty DCBs reaches + * a pre-defined threshold. + * + * In VNET and HNET modes, DCB updating between virtual ring and real ring and + * a IOCTL based notification mechanism are involved. The hypervisor in kernel + * emulates the DMA HW behaviors to update DCBs in virtual network and inform + * the handler something happened. Likewise, the hypervisor updates itself real + * DCB ring from the virtual ring to start DMA for transmitting a packet once a + * notification is received from the virtual network. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include +#include + +#define RX_DCB_CTRL_WORD (2) +#define RX_DCB_STATUS_WORD (3) +#define RX_DCB_STATUS_GET(_rd_) (RX_DCB_GET((_rd_), RX_DCB_STATUS_WORD)) +#define RX_DCB_STATUS_SET(_rd_, _val_) (RX_DCB_SET((_rd_), RX_DCB_STATUS_WORD, (_val_))) +#define RX_DCB_CTRL_SET(_rd_, _val_) (RX_DCB_SET((_rd_), RX_DCB_CTRL_WORD, (_val_))) + +#define TX_DCB_CTRL_WORD (2) +#define TX_DCB_STATUS_WORD (3) +#define TX_DCB_STATUS_GET(_td_) (TX_DCB_GET((_td_), TX_DCB_STATUS_WORD)) +#define TX_DCB_STATUS_SET(_td_, _val_) (TX_DCB_SET((_td_), TX_DCB_STATUS_WORD, (_val_))) +#define TX_DCB_CTRL_SET(_td_, _val_) (TX_DCB_SET((_td_), TX_DCB_CTRL_WORD, (_val_))) + +/*! + * Configure Rx descriptor + */ +static inline void +cmicr_rx_desc_config(volatile RX_DCB_t *rd, uint64_t addr, uint32_t len) +{ + uint32_t remain; + + /* word 0, 1 : addr */ + RX_DCB_ADDR_LOf_SET(*rd, addr); + RX_DCB_ADDR_HIf_SET(*rd, DMA_TO_BUS_HI(addr >> 32)); + + /* word 2: ctrl */ + remain = RX_DCB_DESC_REMAINf_GET(*rd); + RX_DCB_CTRL_SET(*rd, 0); + RX_DCB_DESC_REMAINf_SET(*rd, remain); + RX_DCB_DESC_CTRL_INTRf_SET(*rd, 1); + RX_DCB_CHAINf_SET(*rd, 1); + RX_DCB_BYTE_COUNTf_SET(*rd, len); + + /* word 3: status */ + RX_DCB_STATUS_SET(*rd, 0); + + MEMORY_BARRIER; +} + +/*! + * Configure Tx descriptor + */ +static inline void +cmicr_tx_desc_config(volatile TX_DCB_t *td, uint64_t addr, uint32_t len, uint16_t flags) +{ + uint32_t remain; + + /* word 0,1 : addr */ + TX_DCB_ADDR_LOf_SET(*td, addr); + TX_DCB_ADDR_HIf_SET(*td, DMA_TO_BUS_HI(addr >> 32)); + + /* word 2: ctrl */ + remain = TX_DCB_DESC_REMAINf_GET(*td); + TX_DCB_CTRL_SET(*td, 0); + TX_DCB_DESC_REMAINf_SET(*td, remain); + TX_DCB_DESC_CTRL_INTRf_SET(*td, 1); + TX_DCB_CHAINf_SET(*td, 1); + TX_DCB_BYTE_COUNTf_SET(*td, len); + if (flags & PDMA_TX_HIGIG_PKT) { + TX_DCB_HGf_SET(*td, 1); + } + if (flags & PDMA_TX_PURGE_PKT) { + TX_DCB_PURGEf_SET(*td, 1); + } + + /* word 3: status */ + TX_DCB_STATUS_SET(*td, 0); + + MEMORY_BARRIER; +} + +/*! + * Configure Rx reload descriptor + */ +static inline void +cmicr_rx_rldesc_config(volatile RX_DCB_t *rd, uint64_t addr) +{ + /* word 0,1 : addr */ + RX_DCB_ADDR_LOf_SET(*rd, addr); + RX_DCB_ADDR_HIf_SET(*rd, DMA_TO_BUS_HI(addr >> 32)); + + /* word 2: ctrl */ + RX_DCB_CTRL_SET(*rd, 0); + RX_DCB_DESC_CTRL_INTRf_SET(*rd, 1); + RX_DCB_CHAINf_SET(*rd, 1); + RX_DCB_RELOADf_SET(*rd, 1); + + /* word 3: status */ + RX_DCB_STATUS_SET(*rd, 0); + + MEMORY_BARRIER; +} + +/*! + * Configure Tx reload descriptor + */ +static inline void +cmicr_tx_rldesc_config(volatile TX_DCB_t *td, uint64_t addr) +{ + /* word 0, 1 : addr */ + TX_DCB_ADDR_LOf_SET(*td, addr); + TX_DCB_ADDR_HIf_SET(*td, DMA_TO_BUS_HI(addr >> 32)); + + /* word 2: ctrl */ + TX_DCB_CTRL_SET(*td, 0); + TX_DCB_DESC_CTRL_INTRf_SET(*td, 1); + TX_DCB_CHAINf_SET(*td, 1); + TX_DCB_RELOADf_SET(*td, 1); + + /* word 3: status */ + TX_DCB_STATUS_SET(*td, 0); + + MEMORY_BARRIER; +} + +/*! + * Chain Rx descriptor + */ +static inline void +cmicr_rx_desc_chain(volatile RX_DCB_t *rd, int chain) +{ + if (chain) { + RX_DCB_CHAINf_SET(*rd, 1); + } else { + RX_DCB_CHAINf_SET(*rd, 0); + } + + MEMORY_BARRIER; +} + +/*! + * Chain Tx descriptor + */ +static inline void +cmicr_tx_desc_chain(volatile TX_DCB_t *td, int chain) +{ + if (chain) { + TX_DCB_CHAINf_SET(*td, 1); + } else { + TX_DCB_CHAINf_SET(*td, 0); + } + + MEMORY_BARRIER; +} + +/*! + * Set Rx descriptor remain + */ +static inline void +cmicr_rx_desc_remain(volatile RX_DCB_t *rd, uint32_t rm) +{ + RX_DCB_DESC_REMAINf_SET(*rd, rm); + + MEMORY_BARRIER; +} + +/*! + * Set Tx descriptor remain + */ +static inline void +cmicr_tx_desc_remain(volatile TX_DCB_t *td, uint32_t rm) +{ + TX_DCB_DESC_REMAINf_SET(*td, rm); + + MEMORY_BARRIER; +} + +/*! + * Get unused descriptors in a Rx ring + */ +static inline int +cmicr_pdma_rx_ring_unused(struct pdma_rx_queue *rxq) +{ + /* Leave one descriptor unused so as not to halt */ + return (rxq->nb_desc + rxq->curr - rxq->halt - 1) % rxq->nb_desc; +} + +/*! + * Get unused descriptors in a Tx ring + */ +static inline int +cmicr_pdma_tx_ring_unused(struct pdma_tx_queue *txq) +{ + /* Leave one descriptor unused so as not to halt */ + return (txq->nb_desc + txq->dirt - txq->curr - 1) % txq->nb_desc; +} + +/*! + * Initialize Rx descriptors + */ +static int +cmicr_pdma_rx_desc_init(struct pdma_hw *hw, struct pdma_rx_queue *rxq) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + volatile RX_DCB_t *ring = (volatile RX_DCB_t *)rxq->ring; + dma_addr_t addr; + uint32_t di, rm; + int rv; + + for (di = 0; di < rxq->nb_desc; di++) { + if (!rxq->pbuf[di].dma) { + /* Allocate pktbuf for ring entry */ + rv = bm->rx_buf_alloc(dev, rxq, &rxq->pbuf[di]); + if (SHR_FAILURE(rv)) { + goto cleanup; + } + } + /* Config receive descriptor ring */ + bm->rx_buf_dma(dev, rxq, &rxq->pbuf[di], &addr); + cmicr_rx_desc_config(&ring[di], addr, rxq->buf_size); + rm = (rxq->nb_desc - di) >= CMICR_DESC_REMAIN_MAX ? + CMICR_DESC_REMAIN_MAX : rxq->nb_desc - di; + cmicr_rx_desc_remain(&ring[di], rm); + if (hw->dev->flags & PDMA_CHAIN_MODE && di == rxq->nb_desc - 1) { + cmicr_rx_desc_chain(&ring[di], 0); + } + } + /* Config the last descriptor in the ring as reload descriptor */ + cmicr_rx_rldesc_config(&ring[di], rxq->ring_addr); + + rxq->curr = 0; + rxq->halt = rxq->nb_desc - 1; + + rxq->halt_addr = rxq->ring_addr + sizeof(RX_DCB_t) * rxq->halt; + hw->hdls.chan_goto(hw, rxq->chan_id, rxq->halt_addr); + hw->hdls.chan_setup(hw, rxq->chan_id, rxq->ring_addr); + + return SHR_E_NONE; + +cleanup: + for (di = 0; di < rxq->nb_desc; di++) { + if (rxq->pbuf[di].dma) { + bm->rx_buf_free(dev, rxq, &rxq->pbuf[di]); + } + cmicr_rx_desc_config(&ring[di], 0, 0); + } + + CNET_ERROR(hw->unit, "RX: Failed to allocate memory\n"); + + return SHR_E_MEMORY; +} + +/*! + * Cleanup Rx descriptors + */ +static int +cmicr_pdma_rx_desc_clean(struct pdma_hw *hw, struct pdma_rx_queue *rxq) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + volatile RX_DCB_t *ring = (volatile RX_DCB_t *)rxq->ring; + uint32_t di; + + /* Go through all the descriptors and free pktbuf */ + for (di = 0; di < rxq->nb_desc; di++) { + if (rxq->pbuf[di].dma) { + bm->rx_buf_free(dev, rxq, &rxq->pbuf[di]); + } + cmicr_rx_desc_config(&ring[di], 0, 0); + } + + rxq->curr = 0; + rxq->halt = 0; + + return SHR_E_NONE; +} + +/*! + * Initialize Tx descriptors + */ +static int +cmicr_pdma_tx_desc_init(struct pdma_hw *hw, struct pdma_tx_queue *txq) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + volatile TX_DCB_t *ring = (volatile TX_DCB_t *)txq->ring; + uint32_t di, rm; + + for (di = 0; di < txq->nb_desc; di++) { + if (txq->pbuf[di].dma) { + bm->tx_buf_free(dev, txq, &txq->pbuf[di]); + } + /* Config transmit descriptor ring */ + cmicr_tx_desc_config(&ring[di], 0, 0, 0); + rm = (txq->nb_desc - di) >= CMICR_DESC_REMAIN_MAX ? + CMICR_DESC_REMAIN_MAX : txq->nb_desc - di; + cmicr_tx_desc_remain(&ring[di], rm); + if (hw->dev->flags & PDMA_CHAIN_MODE) { + cmicr_tx_desc_chain(&ring[di], 0); + } + } + /* Config the last descriptor in the ring as reload descriptor */ + cmicr_tx_rldesc_config(&ring[di], txq->ring_addr); + + txq->curr = 0; + txq->dirt = 0; + txq->halt = 0; + + txq->halt_addr = txq->ring_addr; + hw->hdls.chan_goto(hw, txq->chan_id, txq->halt_addr); + hw->hdls.chan_setup(hw, txq->chan_id, txq->ring_addr); + + return SHR_E_NONE; +} + +/*! + * Cleanup Tx descriptors + */ +static int +cmicr_pdma_tx_desc_clean(struct pdma_hw *hw, struct pdma_tx_queue *txq) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + volatile TX_DCB_t *ring = (volatile TX_DCB_t *)txq->ring; + uint32_t di; + + /* Go through all the descriptors and free pktbuf */ + for (di = 0; di < txq->nb_desc; di++) { + if (txq->pbuf[di].dma) { + bm->tx_buf_free(dev, txq, &txq->pbuf[di]); + } + cmicr_tx_desc_config(&ring[di], 0, 0, 0); + } + + txq->curr = 0; + txq->dirt = 0; + txq->halt = 0; + + return SHR_E_NONE; +} + +/*! + * Process Rx vring + */ +static int +cmicr_pdma_rx_vring_process(struct pdma_hw *hw, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf) +{ + struct pdma_dev *dev = hw->dev; + volatile RX_DCB_t *ring = (volatile RX_DCB_t *)rxq->ring; + struct pdma_rx_queue *vrxq = NULL; + volatile RX_DCB_t *vring = NULL; + struct pkt_hdr *pkh = &pbuf->pkb->pkh; + uint64_t buf_addr; + + vrxq = (struct pdma_rx_queue *)dev->ctrl.vnet_rxq[rxq->queue_id]; + vring = (volatile RX_DCB_t *)vrxq->ring; + if (!vring) { + rxq->stats.dropped++; + return SHR_E_UNAVAIL; + } + + if (RX_DCB_DONEf_GET(vring[vrxq->curr])) { + dev->xnet_wake(dev); + return SHR_E_BUSY; + } + + /* Copy descriptor and packet to vring */ + buf_addr = BUS_TO_DMA_HI(RX_DCB_ADDR_HIf_GET(vring[vrxq->curr])); + buf_addr = buf_addr << 32 | RX_DCB_ADDR_LOf_GET(vring[vrxq->curr]); + sal_memcpy(dev->sys_p2v(dev, buf_addr), &pbuf->pkb->data, + pkh->meta_len + pkh->data_len); + RX_DCB_STATUS_SET(vring[vrxq->curr], RX_DCB_STATUS_GET(ring[rxq->curr])); + + MEMORY_BARRIER; + + /* Notify VNET to process if needed */ + if (!RX_DCB_STATUS_GET(vring[(vrxq->curr + vrxq->nb_desc - 1) % vrxq->nb_desc])) { + dev->xnet_wake(dev); + } + vrxq->curr = (vrxq->curr + 1) % vrxq->nb_desc; + + return SHR_E_NONE; +} + +/*! + * Refill Rx ring + */ +static int +cmicr_pdma_rx_ring_refill(struct pdma_hw *hw, struct pdma_rx_queue *rxq) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + volatile RX_DCB_t *ring = (volatile RX_DCB_t *)rxq->ring; + struct pdma_rx_buf *pbuf = NULL; + int unused = cmicr_pdma_rx_ring_unused(rxq); + dma_addr_t addr; + uint32_t halt; + int rv; + + for (halt = rxq->halt; halt < rxq->halt + unused; halt++) { + if (RX_DCB_ADDR_LOf_GET(ring[halt % rxq->nb_desc])) { + continue; + } + pbuf = &rxq->pbuf[halt % rxq->nb_desc]; + /* Allocate a new pktbuf */ + if (!bm->rx_buf_avail(dev, rxq, pbuf)) { + rv = bm->rx_buf_alloc(dev, rxq, pbuf); + if (SHR_FAILURE(rv)) { + rxq->stats.nomems++; + rxq->halt = halt % rxq->nb_desc; + CNET_ERROR(hw->unit, "Can not alloc RX buffer, %d DCBs not filled\n", + cmicr_pdma_rx_ring_unused(rxq)); + break; + } + } + /* Setup the new descriptor */ + bm->rx_buf_dma(dev, rxq, pbuf, &addr); + cmicr_rx_desc_config(&ring[halt % rxq->nb_desc], addr, rxq->buf_size); + if (dev->flags & PDMA_CHAIN_MODE && halt % rxq->nb_desc == rxq->nb_desc - 1) { + cmicr_rx_desc_chain(&ring[halt % rxq->nb_desc], 0); + } + } + rxq->halt = halt % rxq->nb_desc; + + /* Move forward */ + sal_spinlock_lock(rxq->lock); + if (!(rxq->status & PDMA_RX_QUEUE_XOFF)) { + /* Descriptor cherry pick */ + rxq->halt_addr = rxq->ring_addr + sizeof(RX_DCB_t) * rxq->halt; + hw->hdls.chan_goto(hw, rxq->chan_id, rxq->halt_addr); + } + sal_spinlock_unlock(rxq->lock); + + return SHR_E_NONE; +} + +/*! + * \brief Clean Rx ring + * + * \param [in] hw HW structure point. + * \param [in] rxq Rx queue structure point. + * \param [in] budget Polling budget. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +cmicr_pdma_rx_ring_clean(struct pdma_hw *hw, struct pdma_rx_queue *rxq, int budget) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + volatile RX_DCB_t *ring = (volatile RX_DCB_t *)rxq->ring; + struct pdma_rx_buf *pbuf = NULL; + struct pkt_hdr *pkh = NULL; + dma_addr_t addr; + uint32_t curr; + int len, done = 0; + int retry; + int rv; + + curr = rxq->curr; + while (RX_DCB_DONEf_GET(ring[curr])) { + if (done == budget) { + break; + } + + /* Move forward */ + if (!(rxq->state & PDMA_RX_BATCH_REFILL)) { + /* coverity[double_lock : FALSE] */ + sal_spinlock_lock(rxq->lock); + if (!(rxq->status & PDMA_RX_QUEUE_XOFF)) { + /* Descriptor cherry pick */ + rxq->halt_addr = rxq->ring_addr + sizeof(RX_DCB_t) * curr; + hw->hdls.chan_goto(hw, rxq->chan_id, rxq->halt_addr); + rxq->halt = curr; + } + sal_spinlock_unlock(rxq->lock); + } + + /* Get the current pktbuf to process */ + pbuf = &rxq->pbuf[curr]; + len = RX_DCB_BYTES_TRANSFERREDf_GET(ring[curr]); + pkh = bm->rx_buf_get(dev, rxq, pbuf, len); + if (!pkh) { + CNET_ERROR(hw->unit, "RX buffer build failed, retry ...\n"); + rxq->stats.nomems++; + /* Set busy state to retry */ + rxq->state |= PDMA_RX_QUEUE_BUSY; + return budget; + } + + /* Setup packet header */ + pkh->data_len = len - hw->info.rx_ph_size; + pkh->meta_len = hw->info.rx_ph_size; + pkh->queue_id = rxq->queue_id; + + /* Send up the packet */ + rv = dev->pkt_recv(dev, rxq->queue_id, (void *)pbuf->skb); + if (SHR_FAILURE(rv)) { + if (dev->mode == DEV_MODE_HNET && pkh->attrs & PDMA_RX_TO_VNET) { + rv = cmicr_pdma_rx_vring_process(hw, rxq, pbuf); + if (SHR_FAILURE(rv) && rv == SHR_E_BUSY) { + rxq->state |= PDMA_RX_QUEUE_BUSY; + return done; + } + } else { + rxq->stats.dropped++; + } + bm->rx_buf_put(dev, rxq, pbuf, len); + } + + /* Count the packets/bytes */ + rxq->stats.packets++; + rxq->stats.bytes += len; + + /* Count the errors if any */ + if (RX_DCB_CELL_ERRORf_GET(ring[curr]) || + RX_DCB_ECC_ERRORf_GET(ring[curr])) { + rxq->stats.errors++; + } + + /* Setup the new descriptor */ + if (!(rxq->state & PDMA_RX_BATCH_REFILL)) { + if (!bm->rx_buf_avail(dev, rxq, pbuf)) { + retry = 0; + while (1) { + rv = bm->rx_buf_alloc(dev, rxq, pbuf); + if (SHR_SUCCESS(rv)) { + break; + } + rxq->stats.nomems++; + if (dev->mode == DEV_MODE_UNET || dev->mode == DEV_MODE_VNET) { + if (retry++ < 5000000) { + sal_usleep(1); + continue; + } + CNET_ERROR(hw->unit, "Fatal error: can not alloc RX buffer\n"); + } + rxq->state |= PDMA_RX_BATCH_REFILL; + rxq->free_thresh = 1; + cmicr_rx_desc_config(&ring[curr], 0, 0); + CNET_ERROR(hw->unit, "RX buffer alloc failed, try batch refilling later\n"); + break; + } + } + if (pbuf->dma) { + bm->rx_buf_dma(dev, rxq, pbuf, &addr); + cmicr_rx_desc_config(&ring[curr], addr, rxq->buf_size); + if (dev->flags & PDMA_CHAIN_MODE && curr == rxq->nb_desc - 1) { + cmicr_rx_desc_chain(&ring[curr], 0); + } + } + } else { + cmicr_rx_desc_config(&ring[curr], 0, 0); + } + + /* Notify HNET to process if needed */ + if (dev->mode == DEV_MODE_VNET) { + if (RX_DCB_STATUS_GET(ring[(curr + rxq->nb_desc - 1) % rxq->nb_desc])) { + dev->xnet_wake(dev); + } + } + + /* Update the indicators */ + if (!(rxq->state & PDMA_RX_BATCH_REFILL) && rxq->halt != curr) { + sal_spinlock_lock(rxq->lock); + if (!(rxq->status & PDMA_RX_QUEUE_XOFF)) { + /* Descriptor cherry pick */ + rxq->halt_addr = rxq->ring_addr + sizeof(RX_DCB_t) * curr; + hw->hdls.chan_goto(hw, rxq->chan_id, rxq->halt_addr); + rxq->halt = curr; + } + curr = (curr + 1) % rxq->nb_desc; + sal_spinlock_unlock(rxq->lock); + } else { + curr = (curr + 1) % rxq->nb_desc; + } + rxq->curr = curr; + done++; + + /* Restart DMA if in chain mode */ + if (dev->flags & PDMA_CHAIN_MODE) { + /* coverity[double_lock : FALSE] */ + sal_spinlock_lock(rxq->lock); + if (curr == 0 && !(rxq->status & PDMA_RX_QUEUE_XOFF)) { + hw->hdls.chan_stop(hw, rxq->chan_id); + hw->hdls.chan_start(hw, rxq->chan_id); + } + sal_spinlock_unlock(rxq->lock); + } + } + + /* One more poll for chain done in chain mode */ + if (dev->flags & PDMA_CHAIN_MODE) { + if (curr == rxq->nb_desc - 1 && done) { + done = budget; + } + } + + /* In batching mode, replenish all the unused descriptors */ + if (rxq->state & PDMA_RX_BATCH_REFILL && + cmicr_pdma_rx_ring_unused(rxq) >= (int)rxq->free_thresh) { + cmicr_pdma_rx_ring_refill(hw, rxq); + /* If no one filled, return budget and keep polling */ + if (cmicr_pdma_rx_ring_unused(rxq) == (int)(rxq->nb_desc - 1)) { + rxq->state |= PDMA_RX_QUEUE_BUSY; + return budget; + } + } + + return done; +} + +/*! + * Process Tx vring + */ +static int +cmicr_pdma_tx_vring_process(struct pdma_hw *hw, struct pdma_tx_queue *txq, + struct pdma_tx_buf *pbuf) +{ + struct pdma_dev *dev = hw->dev; + volatile TX_DCB_t *ring = (volatile TX_DCB_t *)txq->ring; + struct pdma_tx_queue *vtxq = NULL; + volatile TX_DCB_t *vring = NULL; + + vtxq = (struct pdma_tx_queue *)dev->ctrl.vnet_txq[txq->queue_id]; + vring = (volatile TX_DCB_t *)vtxq->ring; + if (!vring) { + return SHR_E_UNAVAIL; + } + + /* Update vring descriptor */ + TX_DCB_STATUS_SET(vring[vtxq->dirt], TX_DCB_STATUS_GET(ring[txq->dirt])); + pbuf->dma = 0; + + MEMORY_BARRIER; + + /* Notify VNET to process if needed */ + if (!TX_DCB_STATUS_GET(vring[(vtxq->dirt + vtxq->nb_desc - 1) % vtxq->nb_desc])) { + dev->xnet_wake(dev); + } + vtxq->dirt = (vtxq->dirt + 1) % vtxq->nb_desc; + + return SHR_E_NONE; +} + +/*! + * \brief Clean Tx ring + * + * \param [in] hw HW structure point. + * \param [in] txq Tx queue structure point. + * \param [in] budget Polling budget. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +cmicr_pdma_tx_ring_clean(struct pdma_hw *hw, struct pdma_tx_queue *txq, int budget) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + volatile TX_DCB_t *ring = (volatile TX_DCB_t *)txq->ring; + uint32_t dirt, curr; + int done = 0; + + dirt = txq->dirt; + while (txq->pbuf[dirt].dma) { + if (!TX_DCB_STATUS_GET(ring[dirt])) { + break; + } + if (done == budget) { + break; + } + + if (dev->mode == DEV_MODE_HNET && !txq->pbuf[dirt].skb) { + cmicr_pdma_tx_vring_process(hw, txq, &txq->pbuf[dirt]); + } else { + /* Free the done pktbuf */ + bm->tx_buf_free(dev, txq, &txq->pbuf[dirt]); + } + + cmicr_tx_desc_config(&ring[dirt], 0, 0, 0); + + /* Update the indicators */ + dirt = (dirt + 1) % txq->nb_desc; + txq->dirt = dirt; + done++; + + /* Restart DMA if in chain mode */ + if (dev->flags & PDMA_CHAIN_MODE) { + sal_spinlock_lock(txq->lock); + curr = txq->curr; + if (dirt == txq->halt && dirt != curr) { + hw->hdls.chan_stop(hw, txq->chan_id); + cmicr_tx_desc_chain(&ring[(curr + txq->nb_desc - 1) % txq->nb_desc], 0); + hw->hdls.chan_setup(hw, txq->chan_id, + txq->ring_addr + sizeof(TX_DCB_t) * txq->halt); + hw->hdls.chan_start(hw, txq->chan_id); + txq->halt = curr; + } + sal_spinlock_unlock(txq->lock); + } + } + + /* One more poll for chain done in chain mode */ + if (dev->flags & PDMA_CHAIN_MODE) { + /* coverity[double_lock : FALSE] */ + sal_spinlock_lock(txq->lock); + if (dirt != txq->halt) { + done = budget; + } + sal_spinlock_unlock(txq->lock); + } + + /* Set busy state to avoid HW checking */ + if (done == budget) { + txq->state |= PDMA_TX_QUEUE_BUSY; + } + + /* Resume Tx if any */ + sal_spinlock_lock(txq->lock); + if (txq->status & PDMA_TX_QUEUE_XOFF && cmicr_pdma_tx_ring_unused(txq)) { + txq->status &= ~PDMA_TX_QUEUE_XOFF; + if (dev->suspended) { + sal_spinlock_unlock(txq->lock); + return done; + } + if (dev->tx_resume) { + dev->tx_resume(dev, txq->queue_id); + } + sal_spinlock_unlock(txq->lock); + if (!dev->tx_resume && !(txq->state & PDMA_TX_QUEUE_POLL)) { + sal_sem_give(txq->sem); + } + return done; + } + sal_spinlock_unlock(txq->lock); + + return done; +} + +/*! + * Dump Rx ring + */ +static int +cmicr_pdma_rx_ring_dump(struct pdma_hw *hw, struct pdma_rx_queue *rxq) +{ + volatile RX_DCB_t *ring = (volatile RX_DCB_t *)rxq->ring; + volatile RX_DCB_t *rd; + uint32_t di; + + CNET_INFO(hw->unit, "RX: queue=%d, chan=%d, curr=%d, halt=%d, halt@%p\n", + rxq->queue_id, rxq->chan_id, rxq->curr, rxq->halt, (void *)&ring[rxq->halt]); + CNET_INFO(hw->unit, "----------------------------------------------------------------\n"); + for (di = 0; di < rxq->nb_desc + 1; di++) { + rd = &ring[di]; + CNET_INFO(hw->unit, "DESC[%03d]: (%p)->%08x %08x %08x %08x\n", + di, (void *)(unsigned long)(rxq->ring_addr + di * CMICR_PDMA_DCB_SIZE), + RX_DCB_GET(*rd, 0), RX_DCB_GET(*rd, 1), + RX_DCB_GET(*rd, 2), RX_DCB_GET(*rd, 3)); + } + + return SHR_E_NONE; +} + +/*! + * Dump Tx ring + */ +static int +cmicr_pdma_tx_ring_dump(struct pdma_hw *hw, struct pdma_tx_queue *txq) +{ + volatile TX_DCB_t *ring = (volatile TX_DCB_t *)txq->ring; + volatile TX_DCB_t *td; + uint32_t di; + + CNET_INFO(hw->unit, "TX: queue=%d, chan=%d, curr=%d, dirt=%d, halt@%p\n", + txq->queue_id, txq->chan_id, txq->curr, txq->dirt, (void *)&ring[txq->curr]); + CNET_INFO(hw->unit, "----------------------------------------------------------------\n"); + for (di = 0; di < txq->nb_desc + 1; di++) { + td = &ring[di]; + CNET_INFO(hw->unit, "DESC[%03d]: (%p)->%08x %08x %08x %08x\n", + di, (void *)(unsigned long)(txq->ring_addr + di * CMICR_PDMA_DCB_SIZE), + TX_DCB_GET(*td, 0), TX_DCB_GET(*td, 1), + TX_DCB_GET(*td, 2), TX_DCB_GET(*td, 3)); + } + + return SHR_E_NONE; +} + +/*! + * Fetch Tx vring + */ +static int +cmicr_pdma_tx_vring_fetch(struct pdma_hw *hw, struct pdma_tx_queue *txq, + struct pdma_tx_buf *pbuf) +{ + struct pdma_dev *dev = hw->dev; + volatile TX_DCB_t *ring = (volatile TX_DCB_t *)txq->ring; + struct pdma_tx_queue *vtxq = NULL; + volatile TX_DCB_t *vring = NULL; + uint32_t rm; + + vtxq = (struct pdma_tx_queue *)dev->ctrl.vnet_txq[txq->queue_id]; + vring = (volatile TX_DCB_t *)vtxq->ring; + if (!vring || !TX_DCB_BYTE_COUNTf_GET(vring[vtxq->curr])) { + return SHR_E_UNAVAIL; + } + + /* Fetch vring descriptor */ + rm = TX_DCB_DESC_REMAINf_GET(ring[txq->curr]); + TX_DCB_SET(ring[txq->curr], 0, TX_DCB_GET(vring[vtxq->curr], 0)); + TX_DCB_SET(ring[txq->curr], 1, TX_DCB_GET(vring[vtxq->curr], 1)); + TX_DCB_SET(ring[txq->curr], 2, TX_DCB_GET(vring[vtxq->curr], 2)); + TX_DCB_SET(ring[txq->curr], 3, TX_DCB_GET(vring[vtxq->curr], 3)); + TX_DCB_DESC_REMAINf_SET(ring[txq->curr], rm); + TX_DCB_BYTE_COUNTf_SET(vring[vtxq->curr], 0); + + MEMORY_BARRIER; + + pbuf->dma = TX_DCB_ADDR_LOf_GET(vring[vtxq->curr]); + pbuf->len = TX_DCB_BYTE_COUNTf_GET(ring[txq->curr]); + vtxq->curr = (vtxq->curr + 1) % vtxq->nb_desc; + + return SHR_E_NONE; +} + +/*! + * Check Tx ring + */ +static inline int +cmicr_pdma_tx_ring_check(struct pdma_hw *hw, struct pdma_tx_queue *txq) +{ + struct pdma_dev *dev = hw->dev; + + if (dev->suspended) { + txq->stats.xoffs++; + if (dev->tx_suspend) { + dev->tx_suspend(dev, txq->queue_id); + return SHR_E_BUSY; + } + if (!(txq->state & PDMA_TX_QUEUE_POLL)) { + return SHR_E_BUSY; + } + } + + if (cmicr_pdma_tx_ring_unused(txq)) { + return SHR_E_NONE; + } + + sal_spinlock_lock(txq->lock); + if (!cmicr_pdma_tx_ring_unused(txq)) { + txq->status |= PDMA_TX_QUEUE_XOFF; + txq->stats.xoffs++; + if (dev->tx_suspend) { + dev->tx_suspend(dev, txq->queue_id); + } + sal_spinlock_unlock(txq->lock); + return SHR_E_BUSY; + } + sal_spinlock_unlock(txq->lock); + + return SHR_E_NONE; +} + +/*! + * \brief Start packet transmission + * + * \param [in] hw HW structure point. + * \param [in] txq Tx queue structure point. + * \param [in] buf Tx packet buffer. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +cmicr_pdma_pkt_xmit(struct pdma_hw *hw, struct pdma_tx_queue *txq, void *buf) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + volatile TX_DCB_t *ring = (volatile TX_DCB_t *)txq->ring; + struct pdma_tx_buf *pbuf = NULL; + struct pkt_hdr *pkh = NULL; + dma_addr_t addr; + uint32_t curr; + int retry = 5000000; + int rv; + + if (dev->tx_suspend) { + sal_spinlock_lock(txq->mutex); + } else { + rv = sal_sem_take(txq->sem, BCMCNET_TX_RSRC_WAIT_USEC); + if (rv == -1) { + CNET_ERROR(hw->unit, "Timeout waiting for Tx resources\n"); + return SHR_E_TIMEOUT; + } + } + + /* Check Tx resource */ + if (dev->tx_suspend) { + /* Suspend Tx if no resource */ + rv = cmicr_pdma_tx_ring_check(hw, txq); + if (SHR_FAILURE(rv)) { + sal_spinlock_unlock(txq->mutex); + return rv; + } + } else { + /* Abort Tx if a fatal error happened */ + if (txq->status & PDMA_TX_QUEUE_XOFF) { + sal_sem_give(txq->sem); + return SHR_E_RESOURCE; + } + } + + /* Setup the new descriptor */ + curr = txq->curr; + pbuf = &txq->pbuf[curr]; + if (dev->mode == DEV_MODE_HNET && !buf) { + rv = cmicr_pdma_tx_vring_fetch(hw, txq, pbuf); + if (SHR_FAILURE(rv)) { + sal_spinlock_unlock(txq->mutex); + return SHR_E_EMPTY; + } + txq->state |= PDMA_TX_QUEUE_BUSY; + } else { + pbuf->adj = 1; + pkh = bm->tx_buf_get(dev, txq, pbuf, buf); + if (!pkh) { + txq->stats.dropped++; + if (dev->tx_suspend) { + sal_spinlock_unlock(txq->mutex); + } else { + sal_sem_give(txq->sem); + } + return SHR_E_RESOURCE; + } + bm->tx_buf_dma(dev, txq, pbuf, &addr); + cmicr_tx_desc_config(&ring[curr], addr, pbuf->len, pkh->attrs); + } + + /* Notify HNET to process if needed */ + if (dev->mode == DEV_MODE_VNET) { + if (!TX_DCB_BYTE_COUNTf_GET(ring[(curr + txq->nb_desc - 1) % txq->nb_desc])) { + dev->xnet_wake(dev); + } + } + + /* Update the indicators */ + curr = (curr + 1) % txq->nb_desc; + txq->curr = curr; + + /* Start DMA if in chain mode */ + if (dev->flags & PDMA_CHAIN_MODE) { + if (txq->state & PDMA_TX_QUEUE_POLL) { + do { + rv = cmicr_pdma_tx_ring_clean(hw, txq, txq->nb_desc - 1); + if (rv != (int)txq->nb_desc - 1) { + break; + } + sal_usleep(1); + } while (retry--); + if (retry < 0) { + CNET_ERROR(hw->unit, "Last Tx could not get done in given time\n"); + } + } + sal_spinlock_lock(txq->lock); + if (txq->dirt == txq->halt && txq->dirt != curr) { + hw->hdls.chan_stop(hw, txq->chan_id); + cmicr_tx_desc_chain(&ring[(curr + txq->nb_desc - 1) % txq->nb_desc], 0); + hw->hdls.chan_setup(hw, txq->chan_id, + txq->ring_addr + sizeof(TX_DCB_t) * txq->halt); + hw->hdls.chan_start(hw, txq->chan_id); + txq->halt = curr; + } + sal_spinlock_unlock(txq->lock); + } + + /* Kick off DMA */ + txq->halt_addr = txq->ring_addr + sizeof(TX_DCB_t) * curr; + hw->hdls.chan_goto(hw, txq->chan_id, txq->halt_addr); + + /* Count the packets/bytes */ + txq->stats.packets++; + txq->stats.bytes += pbuf->len; + + /* Clean up ring if in polling mode */ + if (txq->state & PDMA_TX_QUEUE_POLL && + cmicr_pdma_tx_ring_unused(txq) <= (int)txq->free_thresh) { + cmicr_pdma_tx_ring_clean(hw, txq, dev->ctrl.budget); + } + + /* Suspend Tx if no resource */ + rv = cmicr_pdma_tx_ring_check(hw, txq); + if (SHR_FAILURE(rv)) { + if (dev->mode == DEV_MODE_VNET) { + dev->xnet_wake(dev); + } + + if (txq->state & PDMA_TX_QUEUE_POLL) { + /* In polling mode, must wait till the ring is available */ + do { + cmicr_pdma_tx_ring_clean(hw, txq, dev->ctrl.budget); + if (!(txq->status & PDMA_TX_QUEUE_XOFF) || + !(txq->state & PDMA_TX_QUEUE_ACTIVE)) { + break; + } + sal_usleep(1); + } while (retry--); + if (retry < 0) { + CNET_ERROR(hw->unit, "Fatal error: Tx ring is full, packets can not been transmitted\n"); + if (!dev->tx_suspend) { + sal_sem_give(txq->sem); + return SHR_E_RESOURCE; + } + } + } else { + /* In interrupt mode, the handle thread will wake up Tx */ + if (!dev->tx_suspend) { + return SHR_E_NONE; + } + } + } + + if (dev->tx_suspend) { + sal_spinlock_unlock(txq->mutex); + } else { + sal_sem_give(txq->sem); + } + + return SHR_E_NONE; +} + +/*! + * Suspend Rx queue + */ +static int +cmicr_pdma_rx_suspend(struct pdma_hw *hw, struct pdma_rx_queue *rxq) +{ + sal_spinlock_lock(rxq->lock); + rxq->status |= PDMA_RX_QUEUE_XOFF; + if (hw->dev->flags & PDMA_CHAIN_MODE) { + hw->hdls.chan_stop(hw, rxq->chan_id); + } + sal_spinlock_unlock(rxq->lock); + + return SHR_E_NONE; +} + +/*! + * Resume Rx queue + */ +static int +cmicr_pdma_rx_resume(struct pdma_hw *hw, struct pdma_rx_queue *rxq) +{ + sal_spinlock_lock(rxq->lock); + if (!(rxq->status & PDMA_RX_QUEUE_XOFF)) { + sal_spinlock_unlock(rxq->lock); + return SHR_E_NONE; + } + if (rxq->state & PDMA_RX_BATCH_REFILL) { + rxq->halt_addr = rxq->ring_addr + sizeof(RX_DCB_t) * rxq->halt; + hw->hdls.chan_goto(hw, rxq->chan_id, rxq->halt_addr); + } else if (rxq->halt == rxq->curr || (rxq->halt == rxq->nb_desc && rxq->curr == 0)) { + rxq->halt = (rxq->curr + 1) % rxq->nb_desc; + rxq->halt_addr = rxq->ring_addr + sizeof(RX_DCB_t) * rxq->halt; + hw->hdls.chan_goto(hw, rxq->chan_id, rxq->halt_addr); + } + if (hw->dev->flags & PDMA_CHAIN_MODE) { + rxq->curr = 0; + hw->hdls.chan_start(hw, rxq->chan_id); + } + rxq->status &= ~PDMA_RX_QUEUE_XOFF; + sal_spinlock_unlock(rxq->lock); + + return SHR_E_NONE; +} + +/*! + * Initialize function pointers + */ +int +bcmcnet_cmicr_pdma_desc_ops_init(struct pdma_hw *hw) +{ + if (!hw) { + return SHR_E_PARAM; + } + + hw->dops.rx_desc_init = cmicr_pdma_rx_desc_init; + hw->dops.rx_desc_clean = cmicr_pdma_rx_desc_clean; + hw->dops.rx_ring_clean = cmicr_pdma_rx_ring_clean; + hw->dops.rx_ring_dump = cmicr_pdma_rx_ring_dump; + hw->dops.rx_suspend = cmicr_pdma_rx_suspend; + hw->dops.rx_resume = cmicr_pdma_rx_resume; + hw->dops.tx_desc_init = cmicr_pdma_tx_desc_init; + hw->dops.tx_desc_clean = cmicr_pdma_tx_desc_clean; + hw->dops.tx_ring_clean = cmicr_pdma_tx_ring_clean; + hw->dops.tx_ring_dump = cmicr_pdma_tx_ring_dump; + hw->dops.pkt_xmit = cmicr_pdma_pkt_xmit; + + return SHR_E_NONE; +} + +/*! + * Attach device driver + */ +int +bcmcnet_cmicr_pdma_driver_attach(struct pdma_dev *dev) +{ + struct pdma_hw *hw = NULL; + + /* Allocate memory for HW data */ + hw = sal_alloc(sizeof(*hw), "bcmcnetPdmaHw"); + if (!hw) { + return SHR_E_MEMORY; + } + sal_memset(hw, 0, sizeof(*hw)); + hw->unit = dev->unit; + hw->dev = dev; + dev->ctrl.hw = hw; + + bcmcnet_cmicr_pdma_hw_hdls_init(hw); + bcmcnet_cmicr_pdma_desc_ops_init(hw); + + return SHR_E_NONE; +} + +/*! + * Detach device driver + */ +int +bcmcnet_cmicr_pdma_driver_detach(struct pdma_dev *dev) +{ + if (dev->ctrl.hw) { + sal_free(dev->ctrl.hw); + } + dev->ctrl.hw = NULL; + + return SHR_E_NONE; +} diff --git a/src/bcm/common/pktio/bcmcnet/hmi/cmicx/bcmcnet_cmicx_pdma_hw.c b/src/bcm/common/pktio/bcmcnet/hmi/cmicx/bcmcnet_cmicx_pdma_hw.c new file mode 100644 index 0000000..d955f96 --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/hmi/cmicx/bcmcnet_cmicx_pdma_hw.c @@ -0,0 +1,601 @@ +/*! \file bcmcnet_cmicx_pdma_hw.c + * + * Utility routines for handling BCMCNET hardware (CMICx). + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include + +#ifdef IPROC_CMICD +#undef MEMORY_BARRIER +#define dmb(opt) asm volatile("dmb " #opt : : : "memory") +#define MEMORY_BARRIER dmb(oshst) +#endif + +/*! + * Read 32-bit register + */ +static inline void +cmicx_pdma_reg_read32(struct pdma_hw *hw, uint32_t addr, uint32_t *data) +{ + if (hw->dev->dev_read32) { + hw->dev->dev_read32(hw->dev, addr, data); + } else { + DEV_READ32(&hw->dev->ctrl, addr, data); + } +} + +/*! + * Write 32-bit register + */ +static inline void +cmicx_pdma_reg_write32(struct pdma_hw *hw, uint32_t addr, uint32_t data) +{ + if (hw->dev->dev_write32) { + hw->dev->dev_write32(hw->dev, addr, data); + } else { + DEV_WRITE32(&hw->dev->ctrl, addr, data); + } +} + +/*! + * Enable interrupt for a channel + */ +static inline void +cmicx_pdma_intr_enable(struct pdma_hw *hw, int cmc, int chan, uint32_t mask) +{ + uint32_t reg, irq_mask; + + if (hw->dev->mode == DEV_MODE_UNET || hw->dev->mode == DEV_MODE_VNET) { + hw->dev->intr_unmask(hw->dev, cmc, chan, 0, 0); + return; + } + + hw->dev->ctrl.grp[cmc].irq_mask |= mask; + irq_mask = hw->dev->ctrl.grp[cmc].irq_mask; + if (cmc == 0) { + reg = CMICX_PDMA_IRQ_RAW_STAT0; + } else { + if (chan < 4) { + reg = CMICX_PDMA_IRQ_RAW_STAT1; + hw->dev->ctrl.grp[cmc].irq_mask <<= CMICX_IRQ_MASK_SHIFT; + } else { + reg = CMICX_PDMA_IRQ_RAW_STAT2; + hw->dev->ctrl.grp[cmc].irq_mask >>= 32 - CMICX_IRQ_MASK_SHIFT; + } + } + + hw->dev->intr_unmask(hw->dev, cmc, chan, reg & 0xfff, 0); + hw->dev->ctrl.grp[cmc].irq_mask = irq_mask; +} + +/*! + * Disable interrupt for a channel + */ +static inline void +cmicx_pdma_intr_disable(struct pdma_hw *hw, int cmc, int chan, uint32_t mask) +{ + uint32_t reg, irq_mask; + + if (hw->dev->mode == DEV_MODE_UNET || hw->dev->mode == DEV_MODE_VNET) { + hw->dev->intr_mask(hw->dev, cmc, chan, 0, 0); + return; + } + + hw->dev->ctrl.grp[cmc].irq_mask &= ~mask; + irq_mask = hw->dev->ctrl.grp[cmc].irq_mask; + if (cmc == 0) { + reg = CMICX_PDMA_IRQ_RAW_STAT0; + } else { + if (chan < 4) { + reg = CMICX_PDMA_IRQ_RAW_STAT1; + hw->dev->ctrl.grp[cmc].irq_mask <<= CMICX_IRQ_MASK_SHIFT; + } else { + reg = CMICX_PDMA_IRQ_RAW_STAT2; + hw->dev->ctrl.grp[cmc].irq_mask >>= 32 - CMICX_IRQ_MASK_SHIFT; + } + } + + hw->dev->intr_mask(hw->dev, cmc, chan, reg & 0xfff, 0); + hw->dev->ctrl.grp[cmc].irq_mask = irq_mask; +} + +/*! + * Initialize HW + */ +static int +cmicx_pdma_hw_init(struct pdma_hw *hw) +{ + dev_mode_t mode = DEV_MODE_MAX; + uint32_t val; + + /* Temporarily upgrade work mode to get HW information in VNET mode. */ + if (hw->dev->mode == DEV_MODE_VNET) { + mode = DEV_MODE_VNET; + hw->dev->mode = DEV_MODE_UNET; + } + + hw->info.name = CMICX_DEV_NAME; + hw->info.dev_id = hw->dev->dev_id; + hw->info.num_cmcs = CMICX_PDMA_CMC_MAX; + hw->info.cmc_chans = CMICX_PDMA_CMC_CHAN; + hw->info.num_chans = CMICX_PDMA_CMC_MAX * CMICX_PDMA_CMC_CHAN; + hw->info.rx_dcb_size = CMICX_PDMA_DCB_SIZE; + hw->info.tx_dcb_size = CMICX_PDMA_DCB_SIZE; + hw->hdls.reg_rd32(hw, CMICX_EP_TO_CPU_HEADER_SIZE, &val); + hw->info.rx_ph_size = (val & 0xf) * 8; + hw->info.tx_ph_size = CMICX_TX_PKT_HDR_SIZE; + + /* Restore work mode to VNET. */ + if (mode == DEV_MODE_VNET) { + hw->dev->mode = DEV_MODE_VNET; + } + + return SHR_E_NONE; +} + +/*! + * Configure HW + */ +static int +cmicx_pdma_hw_config(struct pdma_hw *hw) +{ + struct dev_ctrl *ctrl = &hw->dev->ctrl; + struct pdma_rx_queue *rxq = NULL; + struct pdma_tx_queue *txq = NULL; + uint32_t val, que_ctrl; + int grp, que; + uint32_t qi; + int ip_if_hdr_endian = 0; + + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[qi]; + grp = rxq->group_id; + que = rxq->chan_id % CMICX_PDMA_CMC_CHAN; + que_ctrl = ctrl->grp[grp].que_ctrl[que]; + + hw->hdls.reg_wr32(hw, CMICX_PDMA_IRQ_STAT_CLR(grp), CMICX_PDMA_IRQ_MASK(que)); + val = 0; + if (que_ctrl & PDMA_PKT_BYTE_SWAP) { + val |= CMICX_PDMA_PKT_BIG_ENDIAN; + } + if (que_ctrl & PDMA_OTH_BYTE_SWAP) { + val |= CMICX_PDMA_DESC_BIG_ENDIAN; + } + if (que_ctrl & PDMA_HDR_BYTE_SWAP) { + val |= CMICX_PDMA_HDR_BIG_ENDIAN; + } + if (!(hw->dev->flags & PDMA_CHAIN_MODE)) { + val |= CMICX_PDMA_CONTINUOUS; + } + if (hw->dev->flags & PDMA_DESC_PREFETCH) { + val |= CMICX_PDMA_CONTINUOUS_DESC; + } + val |= CMICX_PDMA_INTR_ON_DESC; + hw->hdls.reg_wr32(hw, CMICX_PDMA_CTRL(grp, que), val); + } + + for (qi = 0; qi < ctrl->nb_txq; qi++) { + txq = (struct pdma_tx_queue *)ctrl->tx_queue[qi]; + grp = txq->group_id; + que = txq->chan_id % CMICX_PDMA_CMC_CHAN; + que_ctrl = ctrl->grp[grp].que_ctrl[que]; + + hw->hdls.reg_wr32(hw, CMICX_PDMA_IRQ_STAT_CLR(grp), CMICX_PDMA_IRQ_MASK(que)); + val = 0; + if (que_ctrl & PDMA_PKT_BYTE_SWAP) { + val |= CMICX_PDMA_PKT_BIG_ENDIAN; + val |= CMICX_PDMA_HDR_BIG_ENDIAN; + ip_if_hdr_endian = 1; + } + if (que_ctrl & PDMA_OTH_BYTE_SWAP) { + val |= CMICX_PDMA_DESC_BIG_ENDIAN; + } + if (que_ctrl & PDMA_HDR_BYTE_SWAP) { + ip_if_hdr_endian = 1; + } + if (!(hw->dev->flags & PDMA_CHAIN_MODE)) { + val |= CMICX_PDMA_CONTINUOUS; + } + if (hw->dev->flags & PDMA_DESC_PREFETCH) { + val |= CMICX_PDMA_CONTINUOUS_DESC; + } + val |= CMICX_PDMA_INTR_ON_DESC | CMICX_PDMA_DIR; + hw->hdls.reg_wr32(hw, CMICX_PDMA_CTRL(grp, que), val); + } + + hw->hdls.reg_rd32(hw, CMICX_TOP_CONFIG, &val); + if (ip_if_hdr_endian == 1) { + val |= 0x80; + } else { + val &= ~0x80; + } + hw->hdls.reg_wr32(hw, CMICX_TOP_CONFIG, val); + return SHR_E_NONE; +} + +/*! + * Reset HW + */ +static int +cmicx_pdma_hw_reset(struct pdma_hw *hw) +{ + int gi, qi; + + for (gi = 0; gi < hw->dev->num_groups; gi++) { + if (!hw->dev->ctrl.grp[gi].attached) { + continue; + } + for (qi = 0; qi < CMICX_PDMA_CMC_CHAN; qi++) { + if (1 << qi & hw->dev->ctrl.grp[gi].bm_rxq || + 1 << qi & hw->dev->ctrl.grp[gi].bm_txq) { + hw->hdls.reg_wr32(hw, CMICX_PDMA_CTRL(gi, qi), 0); + } + } + } + + return SHR_E_NONE; +} + +/*! + * Start a channel + */ +static int +cmicx_pdma_chan_start(struct pdma_hw *hw, int chan) +{ + uint32_t val; + int grp, que; + + grp = chan / CMICX_PDMA_CMC_CHAN; + que = chan % CMICX_PDMA_CMC_CHAN; + + hw->hdls.reg_rd32(hw, CMICX_PDMA_CTRL(grp, que), &val); + val |= CMICX_PDMA_ENABLE; + hw->hdls.reg_wr32(hw, CMICX_PDMA_CTRL(grp, que), val); + + MEMORY_BARRIER; + + return SHR_E_NONE; +} + +/*! + * Stop a channel + */ +static int +cmicx_pdma_chan_stop(struct pdma_hw *hw, int chan) +{ + uint32_t val; + int grp, que; + int retry = CMICX_HW_RETRY_TIMES; + + grp = chan / CMICX_PDMA_CMC_CHAN; + que = chan % CMICX_PDMA_CMC_CHAN; + + hw->hdls.reg_rd32(hw, CMICX_PDMA_CTRL(grp, que), &val); + val |= CMICX_PDMA_ENABLE | CMICX_PDMA_ABORT; + hw->hdls.reg_wr32(hw, CMICX_PDMA_CTRL(grp, que), val); + + MEMORY_BARRIER; + + do { + val = ~CMICX_PDMA_IS_ACTIVE; + hw->hdls.reg_rd32(hw, CMICX_PDMA_STAT(grp, que), &val); + } while ((val & CMICX_PDMA_IS_ACTIVE) && (--retry > 0)); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_CTRL(grp, que), &val); + val &= ~(CMICX_PDMA_ENABLE | CMICX_PDMA_ABORT); + hw->hdls.reg_wr32(hw, CMICX_PDMA_CTRL(grp, que), val); + + hw->hdls.reg_wr32(hw, CMICX_PDMA_IRQ_STAT_CLR(grp), CMICX_PDMA_IRQ_MASK(que)); + + MEMORY_BARRIER; + + return SHR_E_NONE; +} + +/*! + * Setup a channel + */ +static int +cmicx_pdma_chan_setup(struct pdma_hw *hw, int chan, uint64_t addr) +{ + int grp, que; + + grp = chan / CMICX_PDMA_CMC_CHAN; + que = chan % CMICX_PDMA_CMC_CHAN; + + hw->hdls.reg_wr32(hw, CMICX_PDMA_DESC_LO(grp, que), addr); + hw->hdls.reg_wr32(hw, CMICX_PDMA_DESC_HI(grp, que), DMA_TO_BUS_HI(addr >> 32)); + + MEMORY_BARRIER; + + return SHR_E_NONE; +} + +/*! + * Set halt point for a channel + */ +static int +cmicx_pdma_chan_goto(struct pdma_hw *hw, int chan, uint64_t addr) +{ + int grp, que; + + grp = chan / CMICX_PDMA_CMC_CHAN; + que = chan % CMICX_PDMA_CMC_CHAN; + + hw->hdls.reg_wr32(hw, CMICX_PDMA_DESC_HALT_LO(grp, que), addr); + hw->hdls.reg_wr32(hw, CMICX_PDMA_DESC_HALT_HI(grp, que), DMA_TO_BUS_HI(addr >> 32)); + + MEMORY_BARRIER; + + return SHR_E_NONE; +} + +/*! + * Clear a channel + */ +static int +cmicx_pdma_chan_clear(struct pdma_hw *hw, int chan) +{ + int grp, que; + + grp = chan / CMICX_PDMA_CMC_CHAN; + que = chan % CMICX_PDMA_CMC_CHAN; + + hw->hdls.reg_wr32(hw, CMICX_PDMA_IRQ_STAT_CLR(grp), CMICX_PDMA_IRQ_CTRLD_INTR(que)); + + MEMORY_BARRIER; + + return SHR_E_NONE; +} + +/*! + * Get interrupt number for a channel + */ +static int +cmicx_pdma_chan_intr_num_get(struct pdma_hw *hw, int chan) +{ + int grp, que, start_num, mask_shift; + + grp = chan / CMICX_PDMA_CMC_CHAN; + que = chan % CMICX_PDMA_CMC_CHAN; + + mask_shift = 0; + if (grp > 0) { + mask_shift = CMICX_IRQ_MASK_SHIFT + grp * 32; + } + start_num = CMICX_IRQ_START_NUM + mask_shift; + + return start_num + (que * CMICX_IRQ_NUM_OFFSET); +} + +/*! + * Enable interrupt for a channel + */ +static int +cmicx_pdma_chan_intr_enable(struct pdma_hw *hw, int chan) +{ + int grp, que; + + grp = chan / CMICX_PDMA_CMC_CHAN; + que = chan % CMICX_PDMA_CMC_CHAN; + + cmicx_pdma_intr_enable(hw, grp, que, CMICX_PDMA_IRQ_CTRLD_INTR(que)); + + return SHR_E_NONE; +} + +/*! + * Disable interrupt for a channel + */ +static int +cmicx_pdma_chan_intr_disable(struct pdma_hw *hw, int chan) +{ + int grp, que; + + grp = chan / CMICX_PDMA_CMC_CHAN; + que = chan % CMICX_PDMA_CMC_CHAN; + + cmicx_pdma_intr_disable(hw, grp, que, CMICX_PDMA_IRQ_CTRLD_INTR(que)); + + return SHR_E_NONE; +} + +/*! + * Query interrupt status for a channel + * + * In group mode (interrupt processing per CMC), need to query each channel's + * interrupt status. + * + */ +static int +cmicx_pdma_chan_intr_query(struct pdma_hw *hw, int chan) +{ + uint32_t val; + int grp, que; + + grp = chan / CMICX_PDMA_CMC_CHAN; + que = chan % CMICX_PDMA_CMC_CHAN; + + hw->hdls.reg_rd32(hw, CMICX_PDMA_IRQ_STAT(grp), &val); + + return val & CMICX_PDMA_IRQ_CTRLD_INTR(que); +} + +/*! + * Check interrupt validity for a channel + * + * In group mode (interrupt processing per CMC), need to check each channel's + * interrupt validity based on its interrupt mask. + * + */ +static int +cmicx_pdma_chan_intr_check(struct pdma_hw *hw, int chan) +{ + int grp, que; + + grp = chan / CMICX_PDMA_CMC_CHAN; + que = chan % CMICX_PDMA_CMC_CHAN; + + if (!(hw->dev->ctrl.grp[grp].irq_mask & CMICX_PDMA_IRQ_CTRLD_INTR(que))) { + return 0; + } + + return cmicx_pdma_chan_intr_query(hw, chan); +} + +/*! + * Coalesce interrupt for a channel + */ +static int +cmicx_pdma_chan_intr_coalesce(struct pdma_hw *hw, int chan, int count, int timer) +{ + uint32_t val; + int grp, que; + + grp = chan / CMICX_PDMA_CMC_CHAN; + que = chan % CMICX_PDMA_CMC_CHAN; + + val = CMICX_PDMA_INTR_COAL_ENA | + CMICX_PDMA_INTR_THRESH(count) | + CMICX_PDMA_INTR_TIMER(timer); + hw->hdls.reg_wr32(hw, CMICX_PDMA_INTR_COAL(grp, que), val); + + return SHR_E_NONE; +} + +/*! + * Dump registers for a channel + */ +static int +cmicx_pdma_chan_reg_dump(struct pdma_hw *hw, int chan) +{ + uint32_t val; + int grp, que; + + grp = chan / CMICX_PDMA_CMC_CHAN; + que = chan % CMICX_PDMA_CMC_CHAN; + + hw->hdls.reg_rd32(hw, CMICX_PDMA_CTRL(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_CTRL: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_DESC_LO(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_DESC_LO: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_DESC_HI(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_DESC_HI: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_CURR_DESC_LO(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_CURR_DESC_LO: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_CURR_DESC_HI(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_CURR_DESC_HI: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_DESC_HALT_LO(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_DESC_HALT_ADDR_LO: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_DESC_HALT_HI(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_DESC_HALT_ADDR_HI: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_COS_CTRL_RX0(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_COS_CTRL_RX_0: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_COS_CTRL_RX1(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_COS_CTRL_RX_1: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_INTR_COAL(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_INTR_COAL: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_RBUF_THRE(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_RXBUF_THRESHOLD_CONFIG: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_STAT(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_STAT: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_COUNT_RX(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_PKT_COUNT_RXPKT: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_COUNT_TX(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_PKT_COUNT_TXPKT: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_COUNT_RX_DROP(grp, que), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_DMA_CH%d_PKT_COUNT_RXPKT_DROP: 0x%08x\n", grp, que, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_IRQ_STAT(grp), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_IRQ_STAT: 0x%08x\n", grp, val); + + hw->hdls.reg_rd32(hw, CMICX_PDMA_IRQ_STAT_CLR(grp), &val); + CNET_INFO(hw->unit, "CMIC_CMC%d_IRQ_STAT_CLR: 0x%08x\n", grp, val); + + val = hw->dev->ctrl.grp[grp].irq_mask; + CNET_INFO(hw->unit, "CMIC_CMC%d_IRQ_ENAB: 0x%08x\n", grp, val); + + hw->hdls.reg_rd32(hw, CMICX_EP_TO_CPU_HEADER_SIZE, &val); + CNET_INFO(hw->unit, "CMIC_EP_TO_CPU_HEADER_SIZE: 0x%08x\n", val); + + return SHR_E_NONE; +} + +/*! + * Initialize function pointers + */ +int +bcmcnet_cmicx_pdma_hw_hdls_init(struct pdma_hw *hw) +{ + if (!hw) { + return SHR_E_PARAM; + } + + hw->hdls.reg_rd32 = cmicx_pdma_reg_read32; + hw->hdls.reg_wr32 = cmicx_pdma_reg_write32; + hw->hdls.hw_init = cmicx_pdma_hw_init; + hw->hdls.hw_config = cmicx_pdma_hw_config; + hw->hdls.hw_reset = cmicx_pdma_hw_reset; + hw->hdls.chan_start = cmicx_pdma_chan_start; + hw->hdls.chan_stop = cmicx_pdma_chan_stop; + hw->hdls.chan_setup = cmicx_pdma_chan_setup; + hw->hdls.chan_goto = cmicx_pdma_chan_goto; + hw->hdls.chan_clear = cmicx_pdma_chan_clear; + hw->hdls.chan_intr_num_get = cmicx_pdma_chan_intr_num_get; + hw->hdls.chan_intr_enable = cmicx_pdma_chan_intr_enable; + hw->hdls.chan_intr_disable = cmicx_pdma_chan_intr_disable; + hw->hdls.chan_intr_query = cmicx_pdma_chan_intr_query; + hw->hdls.chan_intr_check = cmicx_pdma_chan_intr_check; + hw->hdls.chan_intr_coalesce = cmicx_pdma_chan_intr_coalesce; + hw->hdls.chan_reg_dump = cmicx_pdma_chan_reg_dump; + + return SHR_E_NONE; +} + diff --git a/src/bcm/common/pktio/bcmcnet/hmi/cmicx/bcmcnet_cmicx_pdma_rxtx.c b/src/bcm/common/pktio/bcmcnet/hmi/cmicx/bcmcnet_cmicx_pdma_rxtx.c new file mode 100644 index 0000000..307cf4d --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/hmi/cmicx/bcmcnet_cmicx_pdma_rxtx.c @@ -0,0 +1,1171 @@ +/*! \file bcmcnet_cmicx_pdma_rxtx.c + * + * Utility routines for BCMCNET hardware (CMICx) specific Rx/Tx. + * + * Here are the CMIC specific Rx/Tx routines including DCBs resource allocation + * and clean up, DCBs configuration, Rx buffers allocation, Tx buffers release, + * Rx/Tx packets processing, etc. + * They are shared among all the modes (UNET, KNET, VNET, HNET) and in both of + * user space and kernel space. + * + * The driver uses a ring of DCBs per DMA channel based on Continuous DMA mode. + * The beginning is written to register pointing to the physical address of the + * start of the ring. The ring size is maintained by the driver. A HALT DCB + * physical address is written to DMA register timely to indicate how many DCBs + * can be handled by HW. + * + * When a packet is received, an interrupt is triggered. The handler will go + * through the Rx DCB ring to process the current completed DCB and every + * subsequent DCBs until no one is left. The received packet is processed and + * passed up to the high level SW. After that, a new buffer is allocated and + * the DCB is updated for receiving a new packet. A new HALT DCB is selected + * and its physical address is written to DMA register. + * + * When a packet is transmitted, the driver starts where it left off last time + * in the Tx DCB ring, updates the DCB and writes its physical address to DMA + * register so as to start DMA. Once the transmitting is finished, the handler + * is informed to clean up the buffer based on the work mode. In KNET or HNET + * mode, an interrupt will be triggered. Polling mode is used in CNET or VNET + * mode, the buffers will be cleaned up when the number of dirty DCBs reaches + * a pre-defined threshold. + * + * In VNET and HNET modes, DCB updating between virtual ring and real ring and + * a IOCTL based notification mechanism are involved. The hypervisor in kernel + * emulates the DMA HW behaviors to update DCBs in virtual network and inform + * the handler something happened. Likewise, the hypervisor updates itself real + * DCB ring from the virtual ring to start DMA for transmitting a packet once a + * notification is received from the virtual network. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include +#include + +#ifdef IPROC_CMICD +#undef MEMORY_BARRIER +#define dmb(opt) asm volatile("dmb " #opt : : : "memory") +#define MEMORY_BARRIER dmb(oshst) +#endif + +/*! + * Configure Rx descriptor + */ +static inline void +cmicx_rx_desc_config(struct cmicx_rx_desc *rd, uint64_t addr, uint32_t len) +{ + uint32_t ctrl; + + rd->addr_lo = addr; + rd->addr_hi = DMA_TO_BUS_HI(addr >> 32); + rd->status = 0; + ctrl = rd->ctrl; + ctrl &= CMICX_DESC_CTRL_REMAIN(0xf); + ctrl |= CMICX_DESC_CTRL_CNTLD_INTR | CMICX_DESC_CTRL_CHAIN | + CMICX_DESC_CTRL_LEN(len); + rd->ctrl = ctrl; + + MEMORY_BARRIER; +} + +/*! + * Configure Tx descriptor + */ +static inline void +cmicx_tx_desc_config(struct cmicx_tx_desc *td, uint64_t addr, uint32_t len, uint32_t flags) +{ + uint32_t ctrl; + + td->addr_lo = addr; + td->addr_hi = DMA_TO_BUS_HI(addr >> 32); + td->status = 0; + ctrl = td->ctrl; + ctrl &= CMICX_DESC_CTRL_REMAIN(0xf); + ctrl |= CMICX_DESC_CTRL_CNTLD_INTR | CMICX_DESC_CTRL_CHAIN | + CMICX_DESC_CTRL_FLAGS(flags) | CMICX_DESC_CTRL_LEN(len); + td->ctrl = ctrl; + + MEMORY_BARRIER; +} + +/*! + * Configure Rx reload descriptor + */ +static inline void +cmicx_rx_rldesc_config(struct cmicx_rx_desc *rd, uint64_t addr) +{ + rd->addr_lo = addr; + rd->addr_hi = DMA_TO_BUS_HI(addr >> 32); + rd->status = 0; + rd->ctrl = CMICX_DESC_CTRL_CNTLD_INTR | CMICX_DESC_CTRL_CHAIN | + CMICX_DESC_CTRL_RELOAD; + + MEMORY_BARRIER; +} + +/*! + * Configure Tx reload descriptor + */ +static inline void +cmicx_tx_rldesc_config(struct cmicx_tx_desc *td, uint64_t addr) +{ + td->addr_lo = addr; + td->addr_hi = DMA_TO_BUS_HI(addr >> 32); + td->status = 0; + td->ctrl = CMICX_DESC_CTRL_CNTLD_INTR | CMICX_DESC_CTRL_CHAIN | + CMICX_DESC_CTRL_RELOAD; + + MEMORY_BARRIER; +} + +/*! + * Chain Rx descriptor + */ +static inline void +cmicx_rx_desc_chain(struct cmicx_rx_desc *rd, int chain) +{ + if (chain) { + rd->ctrl |= CMICX_DESC_CTRL_CHAIN; + } else { + rd->ctrl &= ~CMICX_DESC_CTRL_CHAIN; + } + + MEMORY_BARRIER; +} + +/*! + * Chain Tx descriptor + */ +static inline void +cmicx_tx_desc_chain(struct cmicx_tx_desc *td, int chain) +{ + if (chain) { + td->ctrl |= CMICX_DESC_CTRL_CHAIN; + } else { + td->ctrl &= ~CMICX_DESC_CTRL_CHAIN; + } + + MEMORY_BARRIER; +} + +/*! + * Set Rx descriptor remain + */ +static inline void +cmicx_rx_desc_remain(struct cmicx_rx_desc *rd, uint32_t rm) +{ + rd->ctrl &= ~CMICX_DESC_CTRL_REMAIN(0xf); + rd->ctrl |= CMICX_DESC_CTRL_REMAIN(rm); + + MEMORY_BARRIER; +} + +/*! + * Set Tx descriptor remain + */ +static inline void +cmicx_tx_desc_remain(struct cmicx_tx_desc *td, uint32_t rm) +{ + td->ctrl &= ~CMICX_DESC_CTRL_REMAIN(0xf); + td->ctrl |= CMICX_DESC_CTRL_REMAIN(rm); + + MEMORY_BARRIER; +} + +/*! + * Get unused descriptors in a Rx ring + */ +static inline int +cmicx_pdma_rx_ring_unused(struct pdma_rx_queue *rxq) +{ + /* Leave one descriptor unused so as not to halt */ + return (rxq->nb_desc + rxq->curr - rxq->halt - 1) % rxq->nb_desc; +} + +/*! + * Get unused descriptors in a Tx ring + */ +static inline int +cmicx_pdma_tx_ring_unused(struct pdma_tx_queue *txq) +{ + /* Leave one descriptor unused so as not to halt */ + return (txq->nb_desc + txq->dirt - txq->curr - 1) % txq->nb_desc; +} + +/*! + * Initialize Rx descriptors + */ +static int +cmicx_pdma_rx_desc_init(struct pdma_hw *hw, struct pdma_rx_queue *rxq) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + struct cmicx_rx_desc *ring = (struct cmicx_rx_desc *)rxq->ring; + dma_addr_t addr; + uint32_t di, rm; + int rv; + + for (di = 0; di < rxq->nb_desc; di++) { + if (!rxq->pbuf[di].dma) { + /* Allocate pktbuf for ring entry */ + rv = bm->rx_buf_alloc(dev, rxq, &rxq->pbuf[di]); + if (SHR_FAILURE(rv)) { + goto cleanup; + } + } + /* Config receive descriptor ring */ + bm->rx_buf_dma(dev, rxq, &rxq->pbuf[di], &addr); + cmicx_rx_desc_config(&ring[di], addr, rxq->buf_size); + rm = (rxq->nb_desc - di) >= CMICX_DESC_REMAIN_MAX ? + CMICX_DESC_REMAIN_MAX : rxq->nb_desc - di; + cmicx_rx_desc_remain(&ring[di], rm); + if (hw->dev->flags & PDMA_CHAIN_MODE && di == rxq->nb_desc - 1) { + cmicx_rx_desc_chain(&ring[di], 0); + } + } + /* Config the last descriptor in the ring as reload descriptor */ + cmicx_rx_rldesc_config(&ring[di], rxq->ring_addr); + + rxq->curr = 0; + rxq->halt = rxq->nb_desc - 1; + + rxq->halt_addr = rxq->ring_addr + sizeof(struct cmicx_rx_desc) * rxq->halt; + hw->hdls.chan_goto(hw, rxq->chan_id, rxq->halt_addr); + hw->hdls.chan_setup(hw, rxq->chan_id, rxq->ring_addr); + + return SHR_E_NONE; + +cleanup: + for (di = 0; di < rxq->nb_desc; di++) { + if (rxq->pbuf[di].dma) { + bm->rx_buf_free(dev, rxq, &rxq->pbuf[di]); + } + cmicx_rx_desc_config(&ring[di], 0, 0); + } + + CNET_ERROR(hw->unit, "RX: Failed to allocate memory\n"); + + return SHR_E_MEMORY; +} + +/*! + * Cleanup Rx descriptors + */ +static int +cmicx_pdma_rx_desc_clean(struct pdma_hw *hw, struct pdma_rx_queue *rxq) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + struct cmicx_rx_desc *ring = (struct cmicx_rx_desc *)rxq->ring; + uint32_t di; + + /* Go through all the descriptors and free pktbuf */ + for (di = 0; di < rxq->nb_desc; di++) { + if (rxq->pbuf[di].dma) { + bm->rx_buf_free(dev, rxq, &rxq->pbuf[di]); + } + cmicx_rx_desc_config(&ring[di], 0, 0); + } + + rxq->curr = 0; + rxq->halt = 0; + + return SHR_E_NONE; +} + +/*! + * Initialize Tx descriptors + */ +static int +cmicx_pdma_tx_desc_init(struct pdma_hw *hw, struct pdma_tx_queue *txq) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + struct cmicx_tx_desc *ring = (struct cmicx_tx_desc *)txq->ring; + uint32_t di, rm; + + for (di = 0; di < txq->nb_desc; di++) { + if (txq->pbuf[di].dma) { + bm->tx_buf_free(dev, txq, &txq->pbuf[di]); + } + /* Config transmit descriptor ring */ + cmicx_tx_desc_config(&ring[di], 0, 0, 0); + rm = (txq->nb_desc - di) >= CMICX_DESC_REMAIN_MAX ? + CMICX_DESC_REMAIN_MAX : txq->nb_desc - di; + cmicx_tx_desc_remain(&ring[di], rm); + if (hw->dev->flags & PDMA_CHAIN_MODE) { + cmicx_tx_desc_chain(&ring[di], 0); + } + } + /* Config the last descriptor in the ring as reload descriptor */ + cmicx_tx_rldesc_config(&ring[di], txq->ring_addr); + + txq->curr = 0; + txq->dirt = 0; + txq->halt = 0; + + txq->halt_addr = txq->ring_addr; + hw->hdls.chan_goto(hw, txq->chan_id, txq->halt_addr); + hw->hdls.chan_setup(hw, txq->chan_id, txq->ring_addr); + + return SHR_E_NONE; +} + +/*! + * Cleanup Tx descriptors + */ +static int +cmicx_pdma_tx_desc_clean(struct pdma_hw *hw, struct pdma_tx_queue *txq) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + struct cmicx_tx_desc *ring = (struct cmicx_tx_desc *)txq->ring; + uint32_t di; + + /* Go through all the descriptors and free pktbuf */ + for (di = 0; di < txq->nb_desc; di++) { + if (txq->pbuf[di].dma) { + bm->tx_buf_free(dev, txq, &txq->pbuf[di]); + } + cmicx_tx_desc_config(&ring[di], 0, 0, 0); + } + + txq->curr = 0; + txq->dirt = 0; + txq->halt = 0; + + return SHR_E_NONE; +} + +/*! + * Process Rx vring + */ +static int +cmicx_pdma_rx_vring_process(struct pdma_hw *hw, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf) +{ + struct pdma_dev *dev = hw->dev; + struct cmicx_rx_desc *ring = (struct cmicx_rx_desc *)rxq->ring; + struct pdma_rx_queue *vrxq = NULL; + struct cmicx_rx_desc *vring = NULL; + struct pkt_hdr *pkh = &pbuf->pkb->pkh; + uint64_t buf_addr; + + vrxq = (struct pdma_rx_queue *)dev->ctrl.vnet_rxq[rxq->queue_id]; + vring = (struct cmicx_rx_desc *)vrxq->ring; + if (!vring) { + rxq->stats.dropped++; + return SHR_E_UNAVAIL; + } + + if (vring[vrxq->curr].status & CMICX_DESC_STAT_RTX_DONE) { + dev->xnet_wake(dev); + return SHR_E_BUSY; + } + + /* Copy descriptor and packet to vring */ + buf_addr = BUS_TO_DMA_HI(vring[vrxq->curr].addr_hi); + buf_addr = buf_addr << 32 | vring[vrxq->curr].addr_lo; + sal_memcpy(dev->sys_p2v(dev, buf_addr), &pbuf->pkb->data, + pkh->meta_len + pkh->data_len); + vring[vrxq->curr].status = ring[rxq->curr].status; + + MEMORY_BARRIER; + + /* Notify VNET to process if needed */ + if (!vring[(vrxq->curr + vrxq->nb_desc - 1) % vrxq->nb_desc].status) { + dev->xnet_wake(dev); + } + vrxq->curr = (vrxq->curr + 1) % vrxq->nb_desc; + + return SHR_E_NONE; +} + +/*! + * Refill Rx ring + */ +static int +cmicx_pdma_rx_ring_refill(struct pdma_hw *hw, struct pdma_rx_queue *rxq) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + struct cmicx_rx_desc *ring = (struct cmicx_rx_desc *)rxq->ring; + struct pdma_rx_buf *pbuf = NULL; + int unused = cmicx_pdma_rx_ring_unused(rxq); + dma_addr_t addr; + uint32_t halt; + int rv; + + for (halt = rxq->halt; halt < rxq->halt + unused; halt++) { + if (ring[halt % rxq->nb_desc].addr_lo) { + continue; + } + pbuf = &rxq->pbuf[halt % rxq->nb_desc]; + /* Allocate a new pktbuf */ + if (!bm->rx_buf_avail(dev, rxq, pbuf)) { + rv = bm->rx_buf_alloc(dev, rxq, pbuf); + if (SHR_FAILURE(rv)) { + rxq->stats.nomems++; + rxq->halt = halt % rxq->nb_desc; + CNET_ERROR(hw->unit, "Can not alloc RX buffer, %d DCBs not filled\n", + cmicx_pdma_rx_ring_unused(rxq)); + break; + } + } + /* Setup the new descriptor */ + bm->rx_buf_dma(dev, rxq, pbuf, &addr); + cmicx_rx_desc_config(&ring[halt % rxq->nb_desc], addr, rxq->buf_size); + if (dev->flags & PDMA_CHAIN_MODE && halt % rxq->nb_desc == rxq->nb_desc - 1) { + cmicx_rx_desc_chain(&ring[halt % rxq->nb_desc], 0); + } + } + rxq->halt = halt % rxq->nb_desc; + + /* Move forward */ + sal_spinlock_lock(rxq->lock); + if (!(rxq->status & PDMA_RX_QUEUE_XOFF)) { + /* Descriptor cherry pick */ + rxq->halt_addr = rxq->ring_addr + sizeof(struct cmicx_rx_desc) * rxq->halt; + hw->hdls.chan_goto(hw, rxq->chan_id, rxq->halt_addr); + } + sal_spinlock_unlock(rxq->lock); + + return SHR_E_NONE; +} + +/*! + * \brief Clean Rx ring + * + * \param [in] hw HW structure point. + * \param [in] rxq Rx queue structure point. + * \param [in] budget Polling budget. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +cmicx_pdma_rx_ring_clean(struct pdma_hw *hw, struct pdma_rx_queue *rxq, int budget) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + struct cmicx_rx_desc *ring = (struct cmicx_rx_desc *)rxq->ring; + struct pdma_rx_buf *pbuf = NULL; + struct pkt_hdr *pkh = NULL; + dma_addr_t addr; + uint32_t stat, curr; + int len, done = 0; + int retry; + int rv; + + curr = rxq->curr; + while (CMICX_DESC_STAT_DONE(ring[curr].status)) { + if (done == budget) { + break; + } + + /* Move forward */ + if (!(rxq->state & PDMA_RX_BATCH_REFILL)) { + sal_spinlock_lock(rxq->lock); + if (!(rxq->status & PDMA_RX_QUEUE_XOFF)) { + /* Descriptor cherry pick */ + rxq->halt_addr = rxq->ring_addr + sizeof(struct cmicx_rx_desc) * curr; + hw->hdls.chan_goto(hw, rxq->chan_id, rxq->halt_addr); + rxq->halt = curr; + } + sal_spinlock_unlock(rxq->lock); + } + + /* Get the current pktbuf to process */ + pbuf = &rxq->pbuf[curr]; + stat = ring[curr].status; + len = CMICX_DESC_STAT_LEN(stat); + pkh = bm->rx_buf_get(dev, rxq, pbuf, len); + if (!pkh) { + CNET_ERROR(hw->unit, "RX buffer build failed, retry ...\n"); + rxq->stats.nomems++; + /* Set busy state to retry */ + rxq->state |= PDMA_RX_QUEUE_BUSY; + return budget; + } + + /* Setup packet header */ + pkh->data_len = len - hw->info.rx_ph_size; + pkh->meta_len = hw->info.rx_ph_size; + pkh->queue_id = rxq->queue_id; + pkh->attrs = CMICX_DESC_STAT_FLAGS(stat); + + /* Send up the packet */ + rv = dev->pkt_recv(dev, rxq->queue_id, (void *)pbuf->skb); + if (SHR_FAILURE(rv)) { + if (dev->mode == DEV_MODE_HNET && pkh->attrs & PDMA_RX_TO_VNET) { + rv = cmicx_pdma_rx_vring_process(hw, rxq, pbuf); + if (SHR_FAILURE(rv) && rv == SHR_E_BUSY) { + rxq->state |= PDMA_RX_QUEUE_BUSY; + return done; + } + } else { + rxq->stats.dropped++; + } + bm->rx_buf_put(dev, rxq, pbuf, len); + } + + /* Count the packets/bytes */ + rxq->stats.packets++; + rxq->stats.bytes += len; + + /* Count the errors if any */ + if (stat & CMICX_DESC_STAT_ERR_MASK) { + rxq->stats.errors++; + if (stat & CMICX_DESC_STAT_DATA_ERR) { + rxq->stats.data_errors++; + } + if (stat & CMICX_DESC_STAT_CELL_ERR) { + rxq->stats.cell_errors++; + } + } + + /* Setup the new descriptor */ + if (!(rxq->state & PDMA_RX_BATCH_REFILL)) { + if (!bm->rx_buf_avail(dev, rxq, pbuf)) { + retry = 0; + while (1) { + rv = bm->rx_buf_alloc(dev, rxq, pbuf); + if (SHR_SUCCESS(rv)) { + break; + } + rxq->stats.nomems++; + if (dev->mode == DEV_MODE_UNET || dev->mode == DEV_MODE_VNET) { + if (retry++ < 5000000) { + sal_usleep(1); + continue; + } + CNET_ERROR(hw->unit, "Fatal error: can not alloc RX buffer\n"); + } + rxq->state |= PDMA_RX_BATCH_REFILL; + rxq->free_thresh = 1; + cmicx_rx_desc_config(&ring[curr], 0, 0); + CNET_ERROR(hw->unit, "RX buffer alloc failed, try batch refilling later\n"); + break; + } + } + if (pbuf->dma) { + bm->rx_buf_dma(dev, rxq, pbuf, &addr); + cmicx_rx_desc_config(&ring[curr], addr, rxq->buf_size); + if (dev->flags & PDMA_CHAIN_MODE && curr == rxq->nb_desc - 1) { + cmicx_rx_desc_chain(&ring[curr], 0); + } + } + } else { + cmicx_rx_desc_config(&ring[curr], 0, 0); + } + + /* Notify HNET to process if needed */ + if (dev->mode == DEV_MODE_VNET) { + if (ring[(curr + rxq->nb_desc - 1) % rxq->nb_desc].status) { + dev->xnet_wake(dev); + } + } + + /* Update the indicators */ + if (!(rxq->state & PDMA_RX_BATCH_REFILL) && rxq->halt != curr) { + sal_spinlock_lock(rxq->lock); + if (!(rxq->status & PDMA_RX_QUEUE_XOFF)) { + /* Descriptor cherry pick */ + rxq->halt_addr = rxq->ring_addr + sizeof(struct cmicx_rx_desc) * curr; + hw->hdls.chan_goto(hw, rxq->chan_id, rxq->halt_addr); + rxq->halt = curr; + } + curr = (curr + 1) % rxq->nb_desc; + sal_spinlock_unlock(rxq->lock); + } else { + curr = (curr + 1) % rxq->nb_desc; + } + rxq->curr = curr; + done++; + + /* Restart DMA if in chain mode */ + if (dev->flags & PDMA_CHAIN_MODE) { + sal_spinlock_lock(rxq->lock); + if (curr == 0 && !(rxq->status & PDMA_RX_QUEUE_XOFF)) { + hw->hdls.chan_stop(hw, rxq->chan_id); + hw->hdls.chan_start(hw, rxq->chan_id); + } + sal_spinlock_unlock(rxq->lock); + } + } + + /* One more poll for chain done in chain mode */ + if (dev->flags & PDMA_CHAIN_MODE) { + if (curr == rxq->nb_desc - 1 && done) { + done = budget; + } + } + + /* In batching mode, replenish all the unused descriptors */ + if (rxq->state & PDMA_RX_BATCH_REFILL && + cmicx_pdma_rx_ring_unused(rxq) >= (int)rxq->free_thresh) { + cmicx_pdma_rx_ring_refill(hw, rxq); + /* If no one filled, return budget and keep polling */ + if (cmicx_pdma_rx_ring_unused(rxq) == (int)(rxq->nb_desc - 1)) { + rxq->state |= PDMA_RX_QUEUE_BUSY; + return budget; + } + } + + return done; +} + +/*! + * Process Tx vring + */ +static int +cmicx_pdma_tx_vring_process(struct pdma_hw *hw, struct pdma_tx_queue *txq, + struct pdma_tx_buf *pbuf) +{ + struct pdma_dev *dev = hw->dev; + struct cmicx_tx_desc *ring = (struct cmicx_tx_desc *)txq->ring; + struct pdma_tx_queue *vtxq = NULL; + struct cmicx_tx_desc *vring = NULL; + + vtxq = (struct pdma_tx_queue *)dev->ctrl.vnet_txq[txq->queue_id]; + vring = (struct cmicx_tx_desc *)vtxq->ring; + if (!vring) { + return SHR_E_UNAVAIL; + } + + /* Update vring descriptor */ + vring[vtxq->dirt].status = ring[txq->dirt].status; + pbuf->dma = 0; + + MEMORY_BARRIER; + + /* Notify VNET to process if needed */ + if (!vring[(vtxq->dirt + vtxq->nb_desc - 1) % vtxq->nb_desc].status) { + dev->xnet_wake(dev); + } + vtxq->dirt = (vtxq->dirt + 1) % vtxq->nb_desc; + + return SHR_E_NONE; +} + +/*! + * \brief Clean Tx ring + * + * \param [in] hw HW structure point. + * \param [in] txq Tx queue structure point. + * \param [in] budget Polling budget. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +cmicx_pdma_tx_ring_clean(struct pdma_hw *hw, struct pdma_tx_queue *txq, int budget) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + struct cmicx_tx_desc *ring = (struct cmicx_tx_desc *)txq->ring; + uint32_t dirt, curr; + int done = 0; + + dirt = txq->dirt; + while (txq->pbuf[dirt].dma) { + if (!CMICX_DESC_STAT_DONE(ring[dirt].status)) { + break; + } + if (done == budget) { + break; + } + + if (dev->mode == DEV_MODE_HNET && !txq->pbuf[dirt].skb) { + cmicx_pdma_tx_vring_process(hw, txq, &txq->pbuf[dirt]); + } else { + /* Free the done pktbuf */ + bm->tx_buf_free(dev, txq, &txq->pbuf[dirt]); + } + + cmicx_tx_desc_config(&ring[dirt], 0, 0, 0); + + /* Update the indicators */ + dirt = (dirt + 1) % txq->nb_desc; + txq->dirt = dirt; + done++; + + /* Restart DMA if in chain mode */ + if (dev->flags & PDMA_CHAIN_MODE) { + sal_spinlock_lock(txq->lock); + curr = txq->curr; + if (dirt == txq->halt && dirt != curr) { + hw->hdls.chan_stop(hw, txq->chan_id); + cmicx_tx_desc_chain(&ring[(curr + txq->nb_desc - 1) % txq->nb_desc], 0); + hw->hdls.chan_setup(hw, txq->chan_id, + txq->ring_addr + sizeof(struct cmicx_tx_desc) * txq->halt); + hw->hdls.chan_start(hw, txq->chan_id); + txq->halt = curr; + } + sal_spinlock_unlock(txq->lock); + } + } + + /* One more poll for chain done in chain mode */ + if (dev->flags & PDMA_CHAIN_MODE) { + sal_spinlock_lock(txq->lock); + if (dirt != txq->halt) { + done = budget; + } + sal_spinlock_unlock(txq->lock); + } + + /* Set busy state to avoid HW checking */ + if (done == budget) { + txq->state |= PDMA_TX_QUEUE_BUSY; + } + + /* Resume Tx if any */ + sal_spinlock_lock(txq->lock); + if (txq->status & PDMA_TX_QUEUE_XOFF && cmicx_pdma_tx_ring_unused(txq)) { + txq->status &= ~PDMA_TX_QUEUE_XOFF; + if (dev->suspended) { + sal_spinlock_unlock(txq->lock); + return done; + } + if (dev->tx_resume) { + dev->tx_resume(dev, txq->queue_id); + } + sal_spinlock_unlock(txq->lock); + if (!dev->tx_resume && !(txq->state & PDMA_TX_QUEUE_POLL)) { + sal_sem_give(txq->sem); + } + return done; + } + sal_spinlock_unlock(txq->lock); + + return done; +} + +/*! + * Dump Rx ring + */ +static int +cmicx_pdma_rx_ring_dump(struct pdma_hw *hw, struct pdma_rx_queue *rxq) +{ + struct cmicx_rx_desc *ring = (struct cmicx_rx_desc *)rxq->ring; + struct cmicx_rx_desc *rd; + uint32_t di; + + CNET_INFO(hw->unit, "RX: queue=%d, chan=%d, curr=%d, halt=%d, halt@%p\n", + rxq->queue_id, rxq->chan_id, rxq->curr, rxq->halt, (void *)&ring[rxq->halt]); + CNET_INFO(hw->unit, "----------------------------------------------------------------\n"); + for (di = 0; di < rxq->nb_desc + 1; di++) { + rd = &ring[di]; + CNET_INFO(hw->unit, "DESC[%03d]: (%p)->%08x %08x %08x %08x\n", + di, (void *)(unsigned long)(rxq->ring_addr + di * CMICX_PDMA_DCB_SIZE), + rd->addr_lo, rd->addr_hi, rd->ctrl, rd->status); + } + + return SHR_E_NONE; +} + +/*! + * Dump Tx ring + */ +static int +cmicx_pdma_tx_ring_dump(struct pdma_hw *hw, struct pdma_tx_queue *txq) +{ + struct cmicx_tx_desc *ring = (struct cmicx_tx_desc *)txq->ring; + struct cmicx_tx_desc *td; + uint32_t di; + + CNET_INFO(hw->unit, "TX: queue=%d, chan=%d, curr=%d, dirt=%d, halt@%p\n", + txq->queue_id, txq->chan_id, txq->curr, txq->dirt, (void *)&ring[txq->curr]); + CNET_INFO(hw->unit, "----------------------------------------------------------------\n"); + for (di = 0; di < txq->nb_desc + 1; di++) { + td = &ring[di]; + CNET_INFO(hw->unit, "DESC[%03d]: (%p)->%08x %08x %08x %08x\n", + di, (void *)(unsigned long)(txq->ring_addr + di * CMICX_PDMA_DCB_SIZE), + td->addr_lo, td->addr_hi, td->ctrl, td->status); + } + + return SHR_E_NONE; +} + +/*! + * Fetch Tx vring + */ +static int +cmicx_pdma_tx_vring_fetch(struct pdma_hw *hw, struct pdma_tx_queue *txq, + struct pdma_tx_buf *pbuf) +{ + struct pdma_dev *dev = hw->dev; + struct cmicx_tx_desc *ring = (struct cmicx_tx_desc *)txq->ring; + struct pdma_tx_queue *vtxq = NULL; + struct cmicx_tx_desc *vring = NULL; + uint32_t rm; + + vtxq = (struct pdma_tx_queue *)dev->ctrl.vnet_txq[txq->queue_id]; + vring = (struct cmicx_tx_desc *)vtxq->ring; + if (!vring || !CMICX_DESC_CTRL_LEN(vring[vtxq->curr].ctrl)) { + return SHR_E_UNAVAIL; + } + + /* Fetch vring descriptor */ + rm = ring[txq->curr].ctrl & CMICX_DESC_CTRL_REMAIN(0xf); + sal_memcpy(&ring[txq->curr], &vring[vtxq->curr], sizeof(struct cmicx_tx_desc)); + ring[txq->curr].ctrl &= ~CMICX_DESC_CTRL_REMAIN(0xf); + ring[txq->curr].ctrl |= rm; + vring[vtxq->curr].ctrl &= ~CMICX_DESC_CTRL_LEN(-1); + + MEMORY_BARRIER; + + pbuf->dma = vring[vtxq->curr].addr_lo; + pbuf->len = CMICX_DESC_CTRL_LEN(ring[txq->curr].ctrl); + vtxq->curr = (vtxq->curr + 1) % vtxq->nb_desc; + + return SHR_E_NONE; +} + +/*! + * Check Tx ring + */ +static inline int +cmicx_pdma_tx_ring_check(struct pdma_hw *hw, struct pdma_tx_queue *txq) +{ + struct pdma_dev *dev = hw->dev; + + if (dev->suspended) { + txq->stats.xoffs++; + if (dev->tx_suspend) { + dev->tx_suspend(dev, txq->queue_id); + return SHR_E_BUSY; + } + if (!(txq->state & PDMA_TX_QUEUE_POLL)) { + return SHR_E_BUSY; + } + } + + if (cmicx_pdma_tx_ring_unused(txq)) { + return SHR_E_NONE; + } + + sal_spinlock_lock(txq->lock); + if (!cmicx_pdma_tx_ring_unused(txq)) { + txq->status |= PDMA_TX_QUEUE_XOFF; + txq->stats.xoffs++; + if (dev->tx_suspend) { + dev->tx_suspend(dev, txq->queue_id); + } + sal_spinlock_unlock(txq->lock); + return SHR_E_BUSY; + } + sal_spinlock_unlock(txq->lock); + + return SHR_E_NONE; +} + +/*! + * \brief Start packet transmission + * + * \param [in] hw HW structure point. + * \param [in] txq Tx queue structure point. + * \param [in] buf Tx packet buffer. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +cmicx_pdma_pkt_xmit(struct pdma_hw *hw, struct pdma_tx_queue *txq, void *buf) +{ + struct pdma_dev *dev = hw->dev; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)dev->ctrl.buf_mngr; + struct cmicx_tx_desc *ring = (struct cmicx_tx_desc *)txq->ring; + struct pdma_tx_buf *pbuf = NULL; + struct pkt_hdr *pkh = NULL; + dma_addr_t addr; + uint32_t curr, flags = 0; + int retry = 5000000; + int rv; + + if (dev->tx_suspend) { + sal_spinlock_lock(txq->mutex); + } else { + rv = sal_sem_take(txq->sem, BCMCNET_TX_RSRC_WAIT_USEC); + if (rv == -1) { + CNET_ERROR(hw->unit, "Timeout waiting for Tx resources\n"); + return SHR_E_TIMEOUT; + } + } + + /* Check Tx resource */ + if (dev->tx_suspend) { + /* Suspend Tx if no resource */ + rv = cmicx_pdma_tx_ring_check(hw, txq); + if (SHR_FAILURE(rv)) { + sal_spinlock_unlock(txq->mutex); + return rv; + } + } else { + /* Abort Tx if a fatal error happened */ + if (txq->status & PDMA_TX_QUEUE_XOFF) { + sal_sem_give(txq->sem); + return SHR_E_RESOURCE; + } + } + + /* Setup the new descriptor */ + curr = txq->curr; + pbuf = &txq->pbuf[curr]; + if (dev->mode == DEV_MODE_HNET && !buf) { + rv = cmicx_pdma_tx_vring_fetch(hw, txq, pbuf); + if (SHR_FAILURE(rv)) { + sal_spinlock_unlock(txq->mutex); + return SHR_E_EMPTY; + } + txq->state |= PDMA_TX_QUEUE_BUSY; + } else { + pbuf->adj = 1; + pkh = bm->tx_buf_get(dev, txq, pbuf, buf); + if (!pkh) { + txq->stats.dropped++; + if (dev->tx_suspend) { + sal_spinlock_unlock(txq->mutex); + } else { + sal_sem_give(txq->sem); + } + return SHR_E_RESOURCE; + } + bm->tx_buf_dma(dev, txq, pbuf, &addr); + flags |= pkh->attrs & PDMA_TX_HIGIG_PKT ? CMICX_DESC_TX_HIGIG_PKT : 0; + flags |= pkh->attrs & PDMA_TX_PURGE_PKT ? CMICX_DESC_TX_PURGE_PKT : 0; + cmicx_tx_desc_config(&ring[curr], addr, pbuf->len, flags); + } + + /* Notify HNET to process if needed */ + if (dev->mode == DEV_MODE_VNET) { + if (!CMICX_DESC_CTRL_LEN(ring[(curr + txq->nb_desc - 1) % txq->nb_desc].ctrl)) { + dev->xnet_wake(dev); + } + } + + /* Update the indicators */ + curr = (curr + 1) % txq->nb_desc; + txq->curr = curr; + + /* Start DMA if in chain mode */ + if (dev->flags & PDMA_CHAIN_MODE) { + if (txq->state & PDMA_TX_QUEUE_POLL) { + do { + rv = cmicx_pdma_tx_ring_clean(hw, txq, txq->nb_desc - 1); + if (rv != (int)txq->nb_desc - 1) { + break; + } + sal_usleep(1); + } while (retry--); + if (retry < 0) { + CNET_ERROR(hw->unit, "Last Tx could not get done in given time\n"); + } + } + sal_spinlock_lock(txq->lock); + if (txq->dirt == txq->halt && txq->dirt != curr) { + hw->hdls.chan_stop(hw, txq->chan_id); + cmicx_tx_desc_chain(&ring[(curr + txq->nb_desc - 1) % txq->nb_desc], 0); + hw->hdls.chan_setup(hw, txq->chan_id, + txq->ring_addr + sizeof(struct cmicx_tx_desc) * txq->halt); + hw->hdls.chan_start(hw, txq->chan_id); + txq->halt = curr; + } + sal_spinlock_unlock(txq->lock); + } + + /* Kick off DMA */ + txq->halt_addr = txq->ring_addr + sizeof(struct cmicx_tx_desc) * curr; + hw->hdls.chan_goto(hw, txq->chan_id, txq->halt_addr); + + /* Count the packets/bytes */ + txq->stats.packets++; + txq->stats.bytes += pbuf->len; + + /* Clean up ring if in polling mode */ + if (txq->state & PDMA_TX_QUEUE_POLL && + cmicx_pdma_tx_ring_unused(txq) <= (int)txq->free_thresh) { + cmicx_pdma_tx_ring_clean(hw, txq, dev->ctrl.budget); + } + + /* Suspend Tx if no resource */ + rv = cmicx_pdma_tx_ring_check(hw, txq); + if (SHR_FAILURE(rv)) { + if (dev->mode == DEV_MODE_VNET) { + dev->xnet_wake(dev); + } + + if (txq->state & PDMA_TX_QUEUE_POLL) { + /* In polling mode, must wait till the ring is available */ + do { + cmicx_pdma_tx_ring_clean(hw, txq, dev->ctrl.budget); + if (!(txq->status & PDMA_TX_QUEUE_XOFF) || + !(txq->state & PDMA_TX_QUEUE_ACTIVE)) { + break; + } + sal_usleep(1); + } while (retry--); + if (retry < 0) { + CNET_ERROR(hw->unit, "Fatal error: Tx ring is full, packets can not been transmitted\n"); + if (!dev->tx_suspend) { + sal_sem_give(txq->sem); + return SHR_E_RESOURCE; + } + } + } else { + /* In interrupt mode, the handle thread will wake up Tx */ + if (!dev->tx_suspend) { + return SHR_E_NONE; + } + } + } + + if (dev->tx_suspend) { + sal_spinlock_unlock(txq->mutex); + } else { + sal_sem_give(txq->sem); + } + + return SHR_E_NONE; +} + +/*! + * Suspend Rx queue + */ +static int +cmicx_pdma_rx_suspend(struct pdma_hw *hw, struct pdma_rx_queue *rxq) +{ + sal_spinlock_lock(rxq->lock); + rxq->status |= PDMA_RX_QUEUE_XOFF; + if (hw->dev->flags & PDMA_CHAIN_MODE) { + hw->hdls.chan_stop(hw, rxq->chan_id); + } + sal_spinlock_unlock(rxq->lock); + + return SHR_E_NONE; +} + +/*! + * Resume Rx queue + */ +static int +cmicx_pdma_rx_resume(struct pdma_hw *hw, struct pdma_rx_queue *rxq) +{ + sal_spinlock_lock(rxq->lock); + if (!(rxq->status & PDMA_RX_QUEUE_XOFF)) { + sal_spinlock_unlock(rxq->lock); + return SHR_E_NONE; + } + if (rxq->state & PDMA_RX_BATCH_REFILL) { + rxq->halt_addr = rxq->ring_addr + sizeof(struct cmicx_rx_desc) * rxq->halt; + hw->hdls.chan_goto(hw, rxq->chan_id, rxq->halt_addr); + } else if (rxq->halt == rxq->curr || (rxq->halt == rxq->nb_desc && rxq->curr == 0)) { + rxq->halt = (rxq->curr + 1) % rxq->nb_desc; + rxq->halt_addr = rxq->ring_addr + sizeof(struct cmicx_rx_desc) * rxq->halt; + hw->hdls.chan_goto(hw, rxq->chan_id, rxq->halt_addr); + } + if (hw->dev->flags & PDMA_CHAIN_MODE) { + rxq->curr = 0; + hw->hdls.chan_start(hw, rxq->chan_id); + } + rxq->status &= ~PDMA_RX_QUEUE_XOFF; + sal_spinlock_unlock(rxq->lock); + + return SHR_E_NONE; +} + +/*! + * Initialize function pointers + */ +int +bcmcnet_cmicx_pdma_desc_ops_init(struct pdma_hw *hw) +{ + if (!hw) { + return SHR_E_PARAM; + } + + hw->dops.rx_desc_init = cmicx_pdma_rx_desc_init; + hw->dops.rx_desc_clean = cmicx_pdma_rx_desc_clean; + hw->dops.rx_ring_clean = cmicx_pdma_rx_ring_clean; + hw->dops.rx_ring_dump = cmicx_pdma_rx_ring_dump; + hw->dops.rx_suspend = cmicx_pdma_rx_suspend; + hw->dops.rx_resume = cmicx_pdma_rx_resume; + hw->dops.tx_desc_init = cmicx_pdma_tx_desc_init; + hw->dops.tx_desc_clean = cmicx_pdma_tx_desc_clean; + hw->dops.tx_ring_clean = cmicx_pdma_tx_ring_clean; + hw->dops.tx_ring_dump = cmicx_pdma_tx_ring_dump; + hw->dops.pkt_xmit = cmicx_pdma_pkt_xmit; + + return SHR_E_NONE; +} + +/*! + * Attach device driver + */ +int +bcmcnet_cmicx_pdma_driver_attach(struct pdma_dev *dev) +{ + struct pdma_hw *hw = NULL; + + /* Allocate memory for HW data */ + hw = sal_alloc(sizeof(*hw), "bcmcnetPdmaHw"); + if (!hw) { + return SHR_E_MEMORY; + } + sal_memset(hw, 0, sizeof(*hw)); + hw->unit = dev->unit; + hw->dev = dev; + dev->ctrl.hw = hw; + + bcmcnet_cmicx_pdma_hw_hdls_init(hw); + bcmcnet_cmicx_pdma_desc_ops_init(hw); + + return SHR_E_NONE; +} + +/*! + * Detach device driver + */ +int +bcmcnet_cmicx_pdma_driver_detach(struct pdma_dev *dev) +{ + if (dev->ctrl.hw) { + sal_free(dev->ctrl.hw); + } + dev->ctrl.hw = NULL; + + return SHR_E_NONE; +} + diff --git a/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicr.h b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicr.h new file mode 100644 index 0000000..b0f18f2 --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicr.h @@ -0,0 +1,212 @@ +/*! \file bcmcnet_cmicr.h + * + * CMICr registers and descriptors definitions. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMCNET_CMICR_H +#define BCMCNET_CMICR_H + +#include + +/*! + * \name CMICR PDMA HW definitions + */ +/*! \{ */ +/*! CMICR CMC number */ +#define CMICR_PDMA_CMC_MAX 2 +/*! CMICR CMC PDMA channels */ +#define CMICR_PDMA_CMC_CHAN 16 +/*! CMICR PDMA DCB size */ +#define CMICR_PDMA_DCB_SIZE RX_DCB_SIZE +/*! \} */ + +/*! + * \name CMICR PCIe device address definitions + */ +/*! \{ */ +/*! CMICR PCIE offset */ +#define CMICR_PCIE_SO_OFFSET 0x10000000 +/*! Higher DMA address to bus address */ +#define DMA_TO_BUS_HI(dma) ((dma) | CMICR_PCIE_SO_OFFSET) +/*! Higher bus address to DMA address */ +#define BUS_TO_DMA_HI(bus) ((bus) & ~CMICR_PCIE_SO_OFFSET) +/*! \} */ + + +/*! \} */ +/*! + * \name CMICR PDMA register address + */ +/*! \{ */ +/*! Base address */ +#define CMICR_GRP_BASE(g) (0x00000000 + 0x2000 * g) +/*! Control register address */ +#define CMICR_PDMA_CTRL(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_CTRLr_OFFSET + q * 0x80) +/*! Descriptor Address Lower register address */ +#define CMICR_PDMA_DESC_LO(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_DESC_ADDR_LOr_OFFSET + q * 0x80) +/*! Descriptor Address Higher register address */ +#define CMICR_PDMA_DESC_HI(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_DESC_ADDR_HIr_OFFSET + q * 0x80) +/*! Descriptor Halt Address Lower register address */ +#define CMICR_PDMA_DESC_HALT_LO(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LOr_OFFSET + q * 0x80) +/*! Descriptor Halt Address Higher register address */ +#define CMICR_PDMA_DESC_HALT_HI(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HIr_OFFSET + q * 0x80) +/*! Status register address */ +#define CMICR_PDMA_STAT(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_STATr_OFFSET + q * 0x80) +/*! Interrupt status register address */ +#define CMICR_PDMA_INTR_STAT(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_INTRr_OFFSET + q * 0x80) +/*! Interrupt enable register address */ +#define CMICR_PDMA_INTR_ENAB(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_INTR_ENABLEr_OFFSET + q * 0x80) +/*! Interrupt clear register address */ +#define CMICR_PDMA_INTR_CLR(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_INTR_CLRr_OFFSET + q * 0x80) +/*! COS Control Rx0 register address */ +#define CMICR_PDMA_COS_CTRL_RX0(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_COS_CTRL_RX_0r_OFFSET + q * 0x80) +/*! COS Control Rx1 register address */ +#define CMICR_PDMA_COS_CTRL_RX1(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_COS_CTRL_RX_1r_OFFSET + q * 0x80) +/*! Interrupt Coalesce register address */ +#define CMICR_PDMA_INTR_COAL(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_INTR_COALr_OFFSET + q * 0x80) +/*! Current Descriptor Address Lower register address */ +#define CMICR_PDMA_CURR_DESC_LO(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_CURR_DESC_LOr_OFFSET + q * 0x80) +/*! Current Descriptor Address Higher register address */ +#define CMICR_PDMA_CURR_DESC_HI(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_CURR_DESC_HIr_OFFSET + q * 0x80) +/*! Rx Buffer Threshhold register address */ +#define CMICR_PDMA_RBUF_THRE(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_OFFSET + q * 0x80) +/*! Debug Control register address */ +#define CMICR_PDMA_DEBUG_CTRL(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_DEBUG_CONTROLr_OFFSET + q * 0x80) +/*! Debug State Machine Status register address */ +#define CMICR_PDMA_DEBUG_SM_STAT(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_DEBUG_SM_STATUSr_OFFSET + q * 0x80) +/*! Debug Status register address */ +#define CMICR_PDMA_DEBUG_STAT(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_DEBUG_STATUSr_OFFSET + q * 0x80) +/*! Rx Packet Count register address */ +#define CMICR_PDMA_COUNT_RX(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_PKT_COUNT_RXPKTr_OFFSET + q * 0x80) +/*! Tx Packet Count register address */ +#define CMICR_PDMA_COUNT_TX(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_PKT_COUNT_TXPKTr_OFFSET + q * 0x80) +/*! Dropped Rx Packet Count register address */ +#define CMICR_PDMA_COUNT_RX_DROP(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROPr_OFFSET + q * 0x80) +/*! Requested Descriptor Count register address */ +#define CMICR_PDMA_DESC_CNT_REQ(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_DESC_COUNT_REQr_OFFSET + q * 0x80) +/*! Received Descriptor Count register address */ +#define CMICR_PDMA_DESC_CNT_RX(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_DESC_COUNT_RXr_OFFSET + q * 0x80) +/*! Updated Descriptor Count register address */ +#define CMICR_PDMA_DESC_CNT_STAT(g, q) (CMICR_GRP_BASE(g) + CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WRr_OFFSET + q * 0x80) +/*! EP_TO_CPU Header Size register address */ +#define CMICR_EP_TO_CPU_HEADER_SIZE CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_OFFSET +/*! Top config register address */ +#define CMICR_TOP_CONFIG CMIC_TOP_CONFIGr_OFFSET +/*! iProc interrupt enable set register address0 */ +#define PAXB_PDMA_IRQ_ENAB_SET0 PAXB_0_INTC_SET_INTR_ENABLE_REG5r_OFFSET +/*! iProc interrupt enable set register address1 */ +#define PAXB_PDMA_IRQ_ENAB_SET1 PAXB_0_INTC_SET_INTR_ENABLE_REG6r_OFFSET +/*! iProc interrupt enable clear register address0 */ +#define PAXB_PDMA_IRQ_ENAB_CLR0 PAXB_0_INTC_CLEAR_INTR_ENABLE_REG5r_OFFSET +/*! iProc interrupt enable clear register address1 */ +#define PAXB_PDMA_IRQ_ENAB_CLR1 PAXB_0_INTC_CLEAR_INTR_ENABLE_REG6r_OFFSET +/*! \} */ + +/*! + * \name Interrupt status & clear register definitions + */ +/*! \{ */ +/*! Interrupt mask shift */ +#define CMICR_IRQ_MASK_SHIFT 8 +/*! \} */ + +/*! 32-bit register read */ +#define DEV_READ32(_c, _a, _p) \ + do { \ + if ((_c)->dev->mode != DEV_MODE_VNET) { \ + *(_p) = ((volatile uint32_t *)(_c)->hw_addr)[(_a) / 4]; \ + } \ + } while (0) + +/*! 32-bit register write */ +#define DEV_WRITE32(_c, _a, _v) \ + do { \ + if ((_c)->dev->mode != DEV_MODE_VNET) { \ + ((volatile uint32_t *)(_c)->hw_addr)[(_a) / 4] = (_v); \ + } \ + } while (0) + +/*! Tx packet header size */ +#define CMICR_TX_PKT_HDR_SIZE 16 + +/*! HW access retry times */ +#define CMICR_HW_RETRY_TIMES 100000 + +/*! Max remaining descriptors */ +#define CMICR_DESC_REMAIN_MAX 63 + +/*! + * \brief Initialize HW handles. + * + * \param [in] hw HW structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_cmicr_pdma_hw_hdls_init(struct pdma_hw *hw); + +/*! + * \brief Initialize descriptor operations. + * + * \param [in] hw HW structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_cmicr_pdma_desc_ops_init(struct pdma_hw *hw); + +/*! + * \brief Attach device driver. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_cmicr_pdma_driver_attach(struct pdma_dev *dev); + +/*! + * \brief Detach device driver. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_cmicr_pdma_driver_detach(struct pdma_dev *dev); + +#endif /* BCMCNET_CMICR_H */ diff --git a/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicr2.h b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicr2.h new file mode 100644 index 0000000..4f4c351 --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicr2.h @@ -0,0 +1,63 @@ +/*! \file bcmcnet_cmicr2.h + * + * BCMCNET CMICr2 specific definitions and declarations. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMCNET_CMICR2_H +#define BCMCNET_CMICR2_H + +#include + +/*! + * \brief Attach device driver. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_cmicr2_pdma_driver_attach(struct pdma_dev *dev); + +/*! + * \brief Detach device driver. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_cmicr2_pdma_driver_detach(struct pdma_dev *dev); + +#endif /* BCMCNET_CMICR2_H */ diff --git a/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicr_acc.h b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicr_acc.h new file mode 100644 index 0000000..91775fa --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicr_acc.h @@ -0,0 +1,810 @@ +/*! \file bcmcnet_cmicr_acc.h + * + * CMICr PDMA registers and descriptors access macros extracted from: + * bcmbd/include/bcmbd/bcmbd_cmicr_acc.h + * bcmbd/include/bcmbd/bcmbd_cmicr_intr.h + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMCNET_CMICR_ACC_H +#define BCMCNET_CMICR_ACC_H + +#define IPROC_IRQ_BASE5 (5 * 32) +#define IPROC_IRQ_BASE6 (6 * 32) +#define CMICR_IRQ_CMC0_PKTDMA_CH0_INTR (IPROC_IRQ_BASE5 + 8) +#define CMICR_IRQ_CMC0_PKTDMA_CH1_INTR (IPROC_IRQ_BASE5 + 9) +#define CMICR_IRQ_CMC0_PKTDMA_CH2_INTR (IPROC_IRQ_BASE5 + 10) +#define CMICR_IRQ_CMC0_PKTDMA_CH3_INTR (IPROC_IRQ_BASE5 + 11) +#define CMICR_IRQ_CMC0_PKTDMA_CH4_INTR (IPROC_IRQ_BASE5 + 12) +#define CMICR_IRQ_CMC0_PKTDMA_CH5_INTR (IPROC_IRQ_BASE5 + 13) +#define CMICR_IRQ_CMC0_PKTDMA_CH6_INTR (IPROC_IRQ_BASE5 + 14) +#define CMICR_IRQ_CMC0_PKTDMA_CH7_INTR (IPROC_IRQ_BASE5 + 15) +#define CMICR_IRQ_CMC0_PKTDMA_CH8_INTR (IPROC_IRQ_BASE5 + 16) +#define CMICR_IRQ_CMC0_PKTDMA_CH9_INTR (IPROC_IRQ_BASE5 + 17) +#define CMICR_IRQ_CMC0_PKTDMA_CH10_INTR (IPROC_IRQ_BASE5 + 18) +#define CMICR_IRQ_CMC0_PKTDMA_CH11_INTR (IPROC_IRQ_BASE5 + 19) +#define CMICR_IRQ_CMC0_PKTDMA_CH12_INTR (IPROC_IRQ_BASE5 + 20) +#define CMICR_IRQ_CMC0_PKTDMA_CH13_INTR (IPROC_IRQ_BASE5 + 21) +#define CMICR_IRQ_CMC0_PKTDMA_CH14_INTR (IPROC_IRQ_BASE5 + 22) +#define CMICR_IRQ_CMC0_PKTDMA_CH15_INTR (IPROC_IRQ_BASE5 + 23) +#define CMICR_IRQ_CMC1_PKTDMA_CH0_INTR (IPROC_IRQ_BASE5 + 24) +#define CMICR_IRQ_CMC1_PKTDMA_CH1_INTR (IPROC_IRQ_BASE5 + 25) +#define CMICR_IRQ_CMC1_PKTDMA_CH2_INTR (IPROC_IRQ_BASE5 + 26) +#define CMICR_IRQ_CMC1_PKTDMA_CH3_INTR (IPROC_IRQ_BASE5 + 27) +#define CMICR_IRQ_CMC1_PKTDMA_CH4_INTR (IPROC_IRQ_BASE5 + 28) +#define CMICR_IRQ_CMC1_PKTDMA_CH5_INTR (IPROC_IRQ_BASE5 + 29) +#define CMICR_IRQ_CMC1_PKTDMA_CH6_INTR (IPROC_IRQ_BASE5 + 30) +#define CMICR_IRQ_CMC1_PKTDMA_CH7_INTR (IPROC_IRQ_BASE5 + 31) +#define CMICR_IRQ_CMC1_PKTDMA_CH8_INTR (IPROC_IRQ_BASE6 + 0) +#define CMICR_IRQ_CMC1_PKTDMA_CH9_INTR (IPROC_IRQ_BASE6 + 1) +#define CMICR_IRQ_CMC1_PKTDMA_CH10_INTR (IPROC_IRQ_BASE6 + 2) +#define CMICR_IRQ_CMC1_PKTDMA_CH11_INTR (IPROC_IRQ_BASE6 + 3) +#define CMICR_IRQ_CMC1_PKTDMA_CH12_INTR (IPROC_IRQ_BASE6 + 4) +#define CMICR_IRQ_CMC1_PKTDMA_CH13_INTR (IPROC_IRQ_BASE6 + 5) +#define CMICR_IRQ_CMC1_PKTDMA_CH14_INTR (IPROC_IRQ_BASE6 + 6) +#define CMICR_IRQ_CMC1_PKTDMA_CH15_INTR (IPROC_IRQ_BASE6 + 7) + +#define PAXB_0_INTC_SET_INTR_ENABLE_REG5r_OFFSET 0x0292d114 +#define PAXB_0_INTC_SET_INTR_ENABLE_REG6r_OFFSET 0x0292d118 +#define PAXB_0_INTC_CLEAR_INTR_ENABLE_REG5r_OFFSET 0x0292d13c +#define PAXB_0_INTC_CLEAR_INTR_ENABLE_REG6r_OFFSET 0x0292d140 + +/* + * This structure should be used to declare and program CMIC_TOP_CONFIG. + * + */ +typedef union CMIC_TOP_CONFIGr_s { + uint32_t v[1]; + uint32_t cmic_top_config[1]; + uint32_t _cmic_top_config; +} CMIC_TOP_CONFIGr_t; + +#define CMIC_TOP_CONFIGr_CLR(r) (r).cmic_top_config[0] = 0 +#define CMIC_TOP_CONFIGr_SET(r,d) (r).cmic_top_config[0] = d +#define CMIC_TOP_CONFIGr_GET(r) (r).cmic_top_config[0] +#define CMIC_TOP_CONFIGr_OFFSET 0x0000000c +#define CMIC_TOP_CONFIGr_IP_2_EP_LOOPBACK_ENABLEf_GET(r) ((((r).cmic_top_config[0]) >> 1) & 0x1) +#define CMIC_TOP_CONFIGr_IP_2_EP_LOOPBACK_ENABLEf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) +#define CMIC_TOP_CONFIGr_CMC0_CLK_ENf_GET(r) ((((r).cmic_top_config[0]) >> 2) & 0x1) +#define CMIC_TOP_CONFIGr_CMC0_CLK_ENf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) +#define CMIC_TOP_CONFIGr_CMC1_CLK_ENf_GET(r) ((((r).cmic_top_config[0]) >> 3) & 0x1) +#define CMIC_TOP_CONFIGr_CMC1_CLK_ENf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) +#define CMIC_TOP_CONFIGr_COMMON_POOL_CLK_ENf_GET(r) ((((r).cmic_top_config[0]) >> 4) & 0x1) +#define CMIC_TOP_CONFIGr_COMMON_POOL_CLK_ENf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) +#define CMIC_TOP_CONFIGr_RPE_CLK_ENf_GET(r) ((((r).cmic_top_config[0]) >> 5) & 0x1) +#define CMIC_TOP_CONFIGr_RPE_CLK_ENf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 5)) | ((((uint32_t)f) & 0x1) << 5)) +#define CMIC_TOP_CONFIGr_IP_INTERFACE_PAYLOAD_ENDIANESSf_GET(r) ((((r).cmic_top_config[0]) >> 6) & 0x1) +#define CMIC_TOP_CONFIGr_IP_INTERFACE_PAYLOAD_ENDIANESSf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 6)) | ((((uint32_t)f) & 0x1) << 6)) +#define CMIC_TOP_CONFIGr_IP_INTERFACE_HEADER_ENDIANESSf_GET(r) ((((r).cmic_top_config[0]) >> 7) & 0x1) +#define CMIC_TOP_CONFIGr_IP_INTERFACE_HEADER_ENDIANESSf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 7)) | ((((uint32_t)f) & 0x1) << 7)) +#define CMIC_TOP_CONFIGr_EP_INTERFACE_PAYLOAD_ENDIANESSf_GET(r) ((((r).cmic_top_config[0]) >> 8) & 0x1) +#define CMIC_TOP_CONFIGr_EP_INTERFACE_PAYLOAD_ENDIANESSf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) +#define CMIC_TOP_CONFIGr_EP_INTERFACE_HEADER_ENDIANESSf_GET(r) ((((r).cmic_top_config[0]) >> 9) & 0x1) +#define CMIC_TOP_CONFIGr_EP_INTERFACE_HEADER_ENDIANESSf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) +#define CMIC_TOP_CONFIGr_CLEAR_ON_READ_ENABLEf_GET(r) ((((r).cmic_top_config[0]) >> 10) & 0x1) +#define CMIC_TOP_CONFIGr_CLEAR_ON_READ_ENABLEf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) +#define CMIC_TOP_CONFIGr_SATURATE_ENABLEf_GET(r) ((((r).cmic_top_config[0]) >> 11) & 0x1) +#define CMIC_TOP_CONFIGr_SATURATE_ENABLEf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 11)) | ((((uint32_t)f) & 0x1) << 11)) +#define CMIC_TOP_CONFIGr_CLEAR_CMC0_COUNTERSf_GET(r) ((((r).cmic_top_config[0]) >> 12) & 0x1) +#define CMIC_TOP_CONFIGr_CLEAR_CMC0_COUNTERSf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) +#define CMIC_TOP_CONFIGr_CLEAR_CMC1_COUNTERSf_GET(r) ((((r).cmic_top_config[0]) >> 13) & 0x1) +#define CMIC_TOP_CONFIGr_CLEAR_CMC1_COUNTERSf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 13)) | ((((uint32_t)f) & 0x1) << 13)) +#define CMIC_TOP_CONFIGr_CLEAR_RPE_COUNTERSf_GET(r) ((((r).cmic_top_config[0]) >> 14) & 0x1) +#define CMIC_TOP_CONFIGr_CLEAR_RPE_COUNTERSf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 14)) | ((((uint32_t)f) & 0x1) << 14)) +#define CMIC_TOP_CONFIGr_CLEAR_TOP_COUNTERSf_GET(r) ((((r).cmic_top_config[0]) >> 15) & 0x1) +#define CMIC_TOP_CONFIGr_CLEAR_TOP_COUNTERSf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 15)) | ((((uint32_t)f) & 0x1) << 15)) +#define CMIC_TOP_CONFIGr_RPE_PIPE_MAPf_GET(r) ((((r).cmic_top_config[0]) >> 16) & 0x1) +#define CMIC_TOP_CONFIGr_RPE_PIPE_MAPf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 16)) | ((((uint32_t)f) & 0x1) << 16)) +#define CMIC_TOP_CONFIGr_SBUS_RING_ARB_CUT_THROUGH_MODE_ENABLEf_GET(r) ((((r).cmic_top_config[0]) >> 17) & 0x1) +#define CMIC_TOP_CONFIGr_SBUS_RING_ARB_CUT_THROUGH_MODE_ENABLEf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 17)) | ((((uint32_t)f) & 0x1) << 17)) +#define CMIC_TOP_CONFIGr_IP_ARB_QUANTA_SELf_GET(r) ((((r).cmic_top_config[0]) >> 18) & 0x3) +#define CMIC_TOP_CONFIGr_IP_ARB_QUANTA_SELf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x3 << 18)) | ((((uint32_t)f) & 0x3) << 18)) +#define CMIC_TOP_CONFIGr_ENABLE_CMIC_RST_AFTER_SW_IF_PURGEf_GET(r) ((((r).cmic_top_config[0]) >> 20) & 0x1) +#define CMIC_TOP_CONFIGr_ENABLE_CMIC_RST_AFTER_SW_IF_PURGEf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 20)) | ((((uint32_t)f) & 0x1) << 20)) +#define CMIC_TOP_CONFIGr_COS_MASK_OVERRIDEf_GET(r) ((((r).cmic_top_config[0]) >> 21) & 0x1) +#define CMIC_TOP_CONFIGr_COS_MASK_OVERRIDEf_SET(r,f) (r).cmic_top_config[0]=(((r).cmic_top_config[0] & ~((uint32_t)0x1 << 21)) | ((((uint32_t)f) & 0x1) << 21)) +#define READ_CMIC_TOP_CONFIGr(u,r) BCMDRD_DEV_READ32(u,CMIC_TOP_CONFIGr_OFFSET,r._cmic_top_config) +#define WRITE_CMIC_TOP_CONFIGr(u,r) BCMDRD_DEV_WRITE32(u,CMIC_TOP_CONFIGr_OFFSET,r._cmic_top_config) + +/* + * This structure should be used to declare and program CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZE. + * + */ +typedef union CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_s { + uint32_t v[1]; + uint32_t cmic_top_status_ep_to_cpu_header_size[1]; + uint32_t _cmic_top_status_ep_to_cpu_header_size; +} CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_t; + +#define CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_CLR(r) (r).cmic_top_status_ep_to_cpu_header_size[0] = 0 +#define CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_SET(r,d) (r).cmic_top_status_ep_to_cpu_header_size[0] = d +#define CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_GET(r) (r).cmic_top_status_ep_to_cpu_header_size[0] +#define CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_OFFSET 0x00000004 +#define CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_EP_TO_CPU_HEADER_SIZEf_GET(r) (((r).cmic_top_status_ep_to_cpu_header_size[0]) & 0xf) +#define CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_EP_TO_CPU_HEADER_SIZEf_SET(r,f) (r).cmic_top_status_ep_to_cpu_header_size[0]=(((r).cmic_top_status_ep_to_cpu_header_size[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) +#define READ_CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr(u,r) BCMDRD_DEV_READ32(u,CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_OFFSET,r._cmic_top_status_ep_to_cpu_header_size) +#define WRITE_CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr(u,r) BCMDRD_DEV_WRITE32(u,CMIC_TOP_STATUS_EP_TO_CPU_HEADER_SIZEr_OFFSET,r._cmic_top_status_ep_to_cpu_header_size) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_COS_CTRL_RX_0. + * + */ +typedef union CMIC_CMC_PKTDMA_COS_CTRL_RX_0r_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_cos_ctrl_rx_0[1]; + uint32_t _cmic_cmc_pktdma_cos_ctrl_rx_0; +} CMIC_CMC_PKTDMA_COS_CTRL_RX_0r_t; + +#define CMIC_CMC_PKTDMA_COS_CTRL_RX_0r_CLR(r) (r).cmic_cmc_pktdma_cos_ctrl_rx_0[0] = 0 +#define CMIC_CMC_PKTDMA_COS_CTRL_RX_0r_SET(r,d) (r).cmic_cmc_pktdma_cos_ctrl_rx_0[0] = d +#define CMIC_CMC_PKTDMA_COS_CTRL_RX_0r_GET(r) (r).cmic_cmc_pktdma_cos_ctrl_rx_0[0] +#define CMIC_CMC_PKTDMA_COS_CTRL_RX_0r_OFFSET 0x00003124 +#define CMIC_CMC_PKTDMA_COS_CTRL_RX_0r_COS_BMPf_GET(r) ((r).cmic_cmc_pktdma_cos_ctrl_rx_0[0]) +#define CMIC_CMC_PKTDMA_COS_CTRL_RX_0r_COS_BMPf_SET(r,f) (r).cmic_cmc_pktdma_cos_ctrl_rx_0[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_COS_CTRL_RX_0r(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_COS_CTRL_RX_0r_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_cos_ctrl_rx_0) +#define WRITE_CMIC_CMC_PKTDMA_COS_CTRL_RX_0r(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_COS_CTRL_RX_0r_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_cos_ctrl_rx_0) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_COS_CTRL_RX_1. + * + */ +typedef union CMIC_CMC_PKTDMA_COS_CTRL_RX_1r_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_cos_ctrl_rx_1[1]; + uint32_t _cmic_cmc_pktdma_cos_ctrl_rx_1; +} CMIC_CMC_PKTDMA_COS_CTRL_RX_1r_t; + +#define CMIC_CMC_PKTDMA_COS_CTRL_RX_1r_CLR(r) (r).cmic_cmc_pktdma_cos_ctrl_rx_1[0] = 0 +#define CMIC_CMC_PKTDMA_COS_CTRL_RX_1r_SET(r,d) (r).cmic_cmc_pktdma_cos_ctrl_rx_1[0] = d +#define CMIC_CMC_PKTDMA_COS_CTRL_RX_1r_GET(r) (r).cmic_cmc_pktdma_cos_ctrl_rx_1[0] +#define CMIC_CMC_PKTDMA_COS_CTRL_RX_1r_OFFSET 0x00003128 +#define CMIC_CMC_PKTDMA_COS_CTRL_RX_1r_COS_BMPf_GET(r) ((r).cmic_cmc_pktdma_cos_ctrl_rx_1[0]) +#define CMIC_CMC_PKTDMA_COS_CTRL_RX_1r_COS_BMPf_SET(r,f) (r).cmic_cmc_pktdma_cos_ctrl_rx_1[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_COS_CTRL_RX_1r(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_COS_CTRL_RX_1r_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_cos_ctrl_rx_1) +#define WRITE_CMIC_CMC_PKTDMA_COS_CTRL_RX_1r(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_COS_CTRL_RX_1r_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_cos_ctrl_rx_1) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_CTRL. + * + */ +typedef union CMIC_CMC_PKTDMA_CTRLr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_ctrl[1]; + uint32_t _cmic_cmc_pktdma_ctrl; +} CMIC_CMC_PKTDMA_CTRLr_t; + +#define CMIC_CMC_PKTDMA_CTRLr_CLR(r) (r).cmic_cmc_pktdma_ctrl[0] = 0 +#define CMIC_CMC_PKTDMA_CTRLr_SET(r,d) (r).cmic_cmc_pktdma_ctrl[0] = d +#define CMIC_CMC_PKTDMA_CTRLr_GET(r) (r).cmic_cmc_pktdma_ctrl[0] +#define CMIC_CMC_PKTDMA_CTRLr_OFFSET 0x00003100 +#define CMIC_CMC_PKTDMA_CTRLr_DIRECTIONf_GET(r) (((r).cmic_cmc_pktdma_ctrl[0]) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_DIRECTIONf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) +#define CMIC_CMC_PKTDMA_CTRLr_DMA_ENf_GET(r) ((((r).cmic_cmc_pktdma_ctrl[0]) >> 1) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_DMA_ENf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) +#define CMIC_CMC_PKTDMA_CTRLr_ABORT_DMAf_GET(r) ((((r).cmic_cmc_pktdma_ctrl[0]) >> 2) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_ABORT_DMAf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) +#define CMIC_CMC_PKTDMA_CTRLr_PKTDMA_ENDIANESSf_GET(r) ((((r).cmic_cmc_pktdma_ctrl[0]) >> 3) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_PKTDMA_ENDIANESSf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) +#define CMIC_CMC_PKTDMA_CTRLr_DESC_ENDIANESSf_GET(r) ((((r).cmic_cmc_pktdma_ctrl[0]) >> 4) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_DESC_ENDIANESSf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) +#define CMIC_CMC_PKTDMA_CTRLr_DROP_RX_PKT_ON_CHAIN_ENDf_GET(r) ((((r).cmic_cmc_pktdma_ctrl[0]) >> 5) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_DROP_RX_PKT_ON_CHAIN_ENDf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1 << 5)) | ((((uint32_t)f) & 0x1) << 5)) +#define CMIC_CMC_PKTDMA_CTRLr_RLD_STS_UPD_DISf_GET(r) ((((r).cmic_cmc_pktdma_ctrl[0]) >> 6) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_RLD_STS_UPD_DISf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1 << 6)) | ((((uint32_t)f) & 0x1) << 6)) +#define CMIC_CMC_PKTDMA_CTRLr_DESC_DONE_INTR_MODEf_GET(r) ((((r).cmic_cmc_pktdma_ctrl[0]) >> 7) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_DESC_DONE_INTR_MODEf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1 << 7)) | ((((uint32_t)f) & 0x1) << 7)) +#define CMIC_CMC_PKTDMA_CTRLr_ENABLE_CONTINUOUS_DMAf_GET(r) ((((r).cmic_cmc_pktdma_ctrl[0]) >> 8) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_ENABLE_CONTINUOUS_DMAf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) +#define CMIC_CMC_PKTDMA_CTRLr_CONTIGUOUS_DESCRIPTORSf_GET(r) ((((r).cmic_cmc_pktdma_ctrl[0]) >> 9) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_CONTIGUOUS_DESCRIPTORSf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) +#define CMIC_CMC_PKTDMA_CTRLr_HEADER_ENDIANESSf_GET(r) ((((r).cmic_cmc_pktdma_ctrl[0]) >> 12) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_HEADER_ENDIANESSf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) +#define CMIC_CMC_PKTDMA_CTRLr_DISABLE_ABORT_ON_ERRORf_GET(r) ((((r).cmic_cmc_pktdma_ctrl[0]) >> 13) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_DISABLE_ABORT_ON_ERRORf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1 << 13)) | ((((uint32_t)f) & 0x1) << 13)) +#define CMIC_CMC_PKTDMA_CTRLr_PIPE_MAPf_GET(r) ((((r).cmic_cmc_pktdma_ctrl[0]) >> 14) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_PIPE_MAPf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1 << 14)) | ((((uint32_t)f) & 0x1) << 14)) +#define CMIC_CMC_PKTDMA_CTRLr_DISABLE_DESC_OTDSTD_READf_GET(r) ((((r).cmic_cmc_pktdma_ctrl[0]) >> 15) & 0x1) +#define CMIC_CMC_PKTDMA_CTRLr_DISABLE_DESC_OTDSTD_READf_SET(r,f) (r).cmic_cmc_pktdma_ctrl[0]=(((r).cmic_cmc_pktdma_ctrl[0] & ~((uint32_t)0x1 << 15)) | ((((uint32_t)f) & 0x1) << 15)) +#define READ_CMIC_CMC_PKTDMA_CTRLr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_CTRLr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_ctrl) +#define WRITE_CMIC_CMC_PKTDMA_CTRLr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_CTRLr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_ctrl) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_CURR_DESC_HI. + * + */ +typedef union CMIC_CMC_PKTDMA_CURR_DESC_HIr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_curr_desc_hi[1]; + uint32_t _cmic_cmc_pktdma_curr_desc_hi; +} CMIC_CMC_PKTDMA_CURR_DESC_HIr_t; + +#define CMIC_CMC_PKTDMA_CURR_DESC_HIr_CLR(r) (r).cmic_cmc_pktdma_curr_desc_hi[0] = 0 +#define CMIC_CMC_PKTDMA_CURR_DESC_HIr_SET(r,d) (r).cmic_cmc_pktdma_curr_desc_hi[0] = d +#define CMIC_CMC_PKTDMA_CURR_DESC_HIr_GET(r) (r).cmic_cmc_pktdma_curr_desc_hi[0] +#define CMIC_CMC_PKTDMA_CURR_DESC_HIr_OFFSET 0x00003134 +#define CMIC_CMC_PKTDMA_CURR_DESC_HIr_ADDRf_GET(r) ((r).cmic_cmc_pktdma_curr_desc_hi[0]) +#define CMIC_CMC_PKTDMA_CURR_DESC_HIr_ADDRf_SET(r,f) (r).cmic_cmc_pktdma_curr_desc_hi[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_CURR_DESC_HIr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_CURR_DESC_HIr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_curr_desc_hi) +#define WRITE_CMIC_CMC_PKTDMA_CURR_DESC_HIr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_CURR_DESC_HIr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_curr_desc_hi) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_CURR_DESC_LO. + * + */ +typedef union CMIC_CMC_PKTDMA_CURR_DESC_LOr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_curr_desc_lo[1]; + uint32_t _cmic_cmc_pktdma_curr_desc_lo; +} CMIC_CMC_PKTDMA_CURR_DESC_LOr_t; + +#define CMIC_CMC_PKTDMA_CURR_DESC_LOr_CLR(r) (r).cmic_cmc_pktdma_curr_desc_lo[0] = 0 +#define CMIC_CMC_PKTDMA_CURR_DESC_LOr_SET(r,d) (r).cmic_cmc_pktdma_curr_desc_lo[0] = d +#define CMIC_CMC_PKTDMA_CURR_DESC_LOr_GET(r) (r).cmic_cmc_pktdma_curr_desc_lo[0] +#define CMIC_CMC_PKTDMA_CURR_DESC_LOr_OFFSET 0x00003130 +#define CMIC_CMC_PKTDMA_CURR_DESC_LOr_ADDRf_GET(r) ((r).cmic_cmc_pktdma_curr_desc_lo[0]) +#define CMIC_CMC_PKTDMA_CURR_DESC_LOr_ADDRf_SET(r,f) (r).cmic_cmc_pktdma_curr_desc_lo[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_CURR_DESC_LOr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_CURR_DESC_LOr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_curr_desc_lo) +#define WRITE_CMIC_CMC_PKTDMA_CURR_DESC_LOr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_CURR_DESC_LOr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_curr_desc_lo) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_DEBUG_CONTROL. + * + */ +typedef union CMIC_CMC_PKTDMA_DEBUG_CONTROLr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_debug_control[1]; + uint32_t _cmic_cmc_pktdma_debug_control; +} CMIC_CMC_PKTDMA_DEBUG_CONTROLr_t; + +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_CLR(r) (r).cmic_cmc_pktdma_debug_control[0] = 0 +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_SET(r,d) (r).cmic_cmc_pktdma_debug_control[0] = d +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_GET(r) (r).cmic_cmc_pktdma_debug_control[0] +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_OFFSET 0x0000313c +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_DESC_PENDING_SER_Q_SIZEf_GET(r) (((r).cmic_cmc_pktdma_debug_control[0]) & 0x7) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_DESC_PENDING_SER_Q_SIZEf_SET(r,f) (r).cmic_cmc_pktdma_debug_control[0]=(((r).cmic_cmc_pktdma_debug_control[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_DESC_PENDING_WRITE_Q_SIZEf_GET(r) ((((r).cmic_cmc_pktdma_debug_control[0]) >> 3) & 0x7) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_DESC_PENDING_WRITE_Q_SIZEf_SET(r,f) (r).cmic_cmc_pktdma_debug_control[0]=(((r).cmic_cmc_pktdma_debug_control[0] & ~((uint32_t)0x7 << 3)) | ((((uint32_t)f) & 0x7) << 3)) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_FLUSH_DESC_Qf_GET(r) ((((r).cmic_cmc_pktdma_debug_control[0]) >> 6) & 0x1) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_FLUSH_DESC_Qf_SET(r,f) (r).cmic_cmc_pktdma_debug_control[0]=(((r).cmic_cmc_pktdma_debug_control[0] & ~((uint32_t)0x1 << 6)) | ((((uint32_t)f) & 0x1) << 6)) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_RESET_OUTSTANDING_CNTf_GET(r) ((((r).cmic_cmc_pktdma_debug_control[0]) >> 7) & 0x1) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_RESET_OUTSTANDING_CNTf_SET(r,f) (r).cmic_cmc_pktdma_debug_control[0]=(((r).cmic_cmc_pktdma_debug_control[0] & ~((uint32_t)0x1 << 7)) | ((((uint32_t)f) & 0x1) << 7)) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_SM_SELECTf_GET(r) ((((r).cmic_cmc_pktdma_debug_control[0]) >> 8) & 0x3) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_SM_SELECTf_SET(r,f) (r).cmic_cmc_pktdma_debug_control[0]=(((r).cmic_cmc_pktdma_debug_control[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_RESET_DESC_READ_SM_IDLEf_GET(r) ((((r).cmic_cmc_pktdma_debug_control[0]) >> 10) & 0x1) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_RESET_DESC_READ_SM_IDLEf_SET(r,f) (r).cmic_cmc_pktdma_debug_control[0]=(((r).cmic_cmc_pktdma_debug_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_RESET_MEM_RDWR_SM_IDLEf_GET(r) ((((r).cmic_cmc_pktdma_debug_control[0]) >> 11) & 0x1) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_RESET_MEM_RDWR_SM_IDLEf_SET(r,f) (r).cmic_cmc_pktdma_debug_control[0]=(((r).cmic_cmc_pktdma_debug_control[0] & ~((uint32_t)0x1 << 11)) | ((((uint32_t)f) & 0x1) << 11)) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_RESET_DESC_STATUS_WR_SM_IDLEf_GET(r) ((((r).cmic_cmc_pktdma_debug_control[0]) >> 12) & 0x1) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_RESET_DESC_STATUS_WR_SM_IDLEf_SET(r,f) (r).cmic_cmc_pktdma_debug_control[0]=(((r).cmic_cmc_pktdma_debug_control[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_RESET_DYN_RCNFG_SM_IDLEf_GET(r) ((((r).cmic_cmc_pktdma_debug_control[0]) >> 13) & 0x1) +#define CMIC_CMC_PKTDMA_DEBUG_CONTROLr_RESET_DYN_RCNFG_SM_IDLEf_SET(r,f) (r).cmic_cmc_pktdma_debug_control[0]=(((r).cmic_cmc_pktdma_debug_control[0] & ~((uint32_t)0x1 << 13)) | ((((uint32_t)f) & 0x1) << 13)) +#define READ_CMIC_CMC_PKTDMA_DEBUG_CONTROLr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_DEBUG_CONTROLr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_debug_control) +#define WRITE_CMIC_CMC_PKTDMA_DEBUG_CONTROLr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_DEBUG_CONTROLr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_debug_control) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_DEBUG_SM_STATUS. + * + */ +typedef union CMIC_CMC_PKTDMA_DEBUG_SM_STATUSr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_debug_sm_status[1]; + uint32_t _cmic_cmc_pktdma_debug_sm_status; +} CMIC_CMC_PKTDMA_DEBUG_SM_STATUSr_t; + +#define CMIC_CMC_PKTDMA_DEBUG_SM_STATUSr_CLR(r) (r).cmic_cmc_pktdma_debug_sm_status[0] = 0 +#define CMIC_CMC_PKTDMA_DEBUG_SM_STATUSr_SET(r,d) (r).cmic_cmc_pktdma_debug_sm_status[0] = d +#define CMIC_CMC_PKTDMA_DEBUG_SM_STATUSr_GET(r) (r).cmic_cmc_pktdma_debug_sm_status[0] +#define CMIC_CMC_PKTDMA_DEBUG_SM_STATUSr_OFFSET 0x00003140 +#define CMIC_CMC_PKTDMA_DEBUG_SM_STATUSr_STATEf_GET(r) ((r).cmic_cmc_pktdma_debug_sm_status[0]) +#define CMIC_CMC_PKTDMA_DEBUG_SM_STATUSr_STATEf_SET(r,f) (r).cmic_cmc_pktdma_debug_sm_status[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_DEBUG_SM_STATUSr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_DEBUG_SM_STATUSr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_debug_sm_status) +#define WRITE_CMIC_CMC_PKTDMA_DEBUG_SM_STATUSr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_DEBUG_SM_STATUSr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_debug_sm_status) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_DEBUG_STATUS. + * + */ +typedef union CMIC_CMC_PKTDMA_DEBUG_STATUSr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_debug_status[1]; + uint32_t _cmic_cmc_pktdma_debug_status; +} CMIC_CMC_PKTDMA_DEBUG_STATUSr_t; + +#define CMIC_CMC_PKTDMA_DEBUG_STATUSr_CLR(r) (r).cmic_cmc_pktdma_debug_status[0] = 0 +#define CMIC_CMC_PKTDMA_DEBUG_STATUSr_SET(r,d) (r).cmic_cmc_pktdma_debug_status[0] = d +#define CMIC_CMC_PKTDMA_DEBUG_STATUSr_GET(r) (r).cmic_cmc_pktdma_debug_status[0] +#define CMIC_CMC_PKTDMA_DEBUG_STATUSr_OFFSET 0x00003144 +#define CMIC_CMC_PKTDMA_DEBUG_STATUSr_DESC_PENDING_SER_Q_SIZE_NUM_ENTRIESf_GET(r) (((r).cmic_cmc_pktdma_debug_status[0]) & 0x3f) +#define CMIC_CMC_PKTDMA_DEBUG_STATUSr_DESC_PENDING_SER_Q_SIZE_NUM_ENTRIESf_SET(r,f) (r).cmic_cmc_pktdma_debug_status[0]=(((r).cmic_cmc_pktdma_debug_status[0] & ~((uint32_t)0x3f)) | (((uint32_t)f) & 0x3f)) +#define CMIC_CMC_PKTDMA_DEBUG_STATUSr_DESC_PENDING_WRITE_Q_NUM_ENTRIESf_GET(r) ((((r).cmic_cmc_pktdma_debug_status[0]) >> 6) & 0x7f) +#define CMIC_CMC_PKTDMA_DEBUG_STATUSr_DESC_PENDING_WRITE_Q_NUM_ENTRIESf_SET(r,f) (r).cmic_cmc_pktdma_debug_status[0]=(((r).cmic_cmc_pktdma_debug_status[0] & ~((uint32_t)0x7f << 6)) | ((((uint32_t)f) & 0x7f) << 6)) +#define CMIC_CMC_PKTDMA_DEBUG_STATUSr_NUM_TXPKTBUF_CELL_USEDf_GET(r) ((((r).cmic_cmc_pktdma_debug_status[0]) >> 13) & 0x7f) +#define CMIC_CMC_PKTDMA_DEBUG_STATUSr_NUM_TXPKTBUF_CELL_USEDf_SET(r,f) (r).cmic_cmc_pktdma_debug_status[0]=(((r).cmic_cmc_pktdma_debug_status[0] & ~((uint32_t)0x7f << 13)) | ((((uint32_t)f) & 0x7f) << 13)) +#define CMIC_CMC_PKTDMA_DEBUG_STATUSr_DESC_READ_OUTSTD_CNTf_GET(r) ((((r).cmic_cmc_pktdma_debug_status[0]) >> 20) & 0x1f) +#define CMIC_CMC_PKTDMA_DEBUG_STATUSr_DESC_READ_OUTSTD_CNTf_SET(r,f) (r).cmic_cmc_pktdma_debug_status[0]=(((r).cmic_cmc_pktdma_debug_status[0] & ~((uint32_t)0x1f << 20)) | ((((uint32_t)f) & 0x1f) << 20)) +#define READ_CMIC_CMC_PKTDMA_DEBUG_STATUSr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_DEBUG_STATUSr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_debug_status) +#define WRITE_CMIC_CMC_PKTDMA_DEBUG_STATUSr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_DEBUG_STATUSr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_debug_status) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_DESC_ADDR_HI. + * + */ +typedef union CMIC_CMC_PKTDMA_DESC_ADDR_HIr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_desc_addr_hi[1]; + uint32_t _cmic_cmc_pktdma_desc_addr_hi; +} CMIC_CMC_PKTDMA_DESC_ADDR_HIr_t; + +#define CMIC_CMC_PKTDMA_DESC_ADDR_HIr_CLR(r) (r).cmic_cmc_pktdma_desc_addr_hi[0] = 0 +#define CMIC_CMC_PKTDMA_DESC_ADDR_HIr_SET(r,d) (r).cmic_cmc_pktdma_desc_addr_hi[0] = d +#define CMIC_CMC_PKTDMA_DESC_ADDR_HIr_GET(r) (r).cmic_cmc_pktdma_desc_addr_hi[0] +#define CMIC_CMC_PKTDMA_DESC_ADDR_HIr_OFFSET 0x00003108 +#define CMIC_CMC_PKTDMA_DESC_ADDR_HIr_ADDRf_GET(r) ((r).cmic_cmc_pktdma_desc_addr_hi[0]) +#define CMIC_CMC_PKTDMA_DESC_ADDR_HIr_ADDRf_SET(r,f) (r).cmic_cmc_pktdma_desc_addr_hi[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_DESC_ADDR_HIr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_DESC_ADDR_HIr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_addr_hi) +#define WRITE_CMIC_CMC_PKTDMA_DESC_ADDR_HIr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_DESC_ADDR_HIr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_addr_hi) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_DESC_ADDR_LO. + * + */ +typedef union CMIC_CMC_PKTDMA_DESC_ADDR_LOr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_desc_addr_lo[1]; + uint32_t _cmic_cmc_pktdma_desc_addr_lo; +} CMIC_CMC_PKTDMA_DESC_ADDR_LOr_t; + +#define CMIC_CMC_PKTDMA_DESC_ADDR_LOr_CLR(r) (r).cmic_cmc_pktdma_desc_addr_lo[0] = 0 +#define CMIC_CMC_PKTDMA_DESC_ADDR_LOr_SET(r,d) (r).cmic_cmc_pktdma_desc_addr_lo[0] = d +#define CMIC_CMC_PKTDMA_DESC_ADDR_LOr_GET(r) (r).cmic_cmc_pktdma_desc_addr_lo[0] +#define CMIC_CMC_PKTDMA_DESC_ADDR_LOr_OFFSET 0x00003104 +#define CMIC_CMC_PKTDMA_DESC_ADDR_LOr_ADDRf_GET(r) ((r).cmic_cmc_pktdma_desc_addr_lo[0]) +#define CMIC_CMC_PKTDMA_DESC_ADDR_LOr_ADDRf_SET(r,f) (r).cmic_cmc_pktdma_desc_addr_lo[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_DESC_ADDR_LOr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_DESC_ADDR_LOr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_addr_lo) +#define WRITE_CMIC_CMC_PKTDMA_DESC_ADDR_LOr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_DESC_ADDR_LOr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_addr_lo) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_DESC_COUNT_REQ. + * + */ +typedef union CMIC_CMC_PKTDMA_DESC_COUNT_REQr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_desc_count_req[1]; + uint32_t _cmic_cmc_pktdma_desc_count_req; +} CMIC_CMC_PKTDMA_DESC_COUNT_REQr_t; + +#define CMIC_CMC_PKTDMA_DESC_COUNT_REQr_CLR(r) (r).cmic_cmc_pktdma_desc_count_req[0] = 0 +#define CMIC_CMC_PKTDMA_DESC_COUNT_REQr_SET(r,d) (r).cmic_cmc_pktdma_desc_count_req[0] = d +#define CMIC_CMC_PKTDMA_DESC_COUNT_REQr_GET(r) (r).cmic_cmc_pktdma_desc_count_req[0] +#define CMIC_CMC_PKTDMA_DESC_COUNT_REQr_OFFSET 0x00003154 +#define CMIC_CMC_PKTDMA_DESC_COUNT_REQr_COUNTf_GET(r) ((r).cmic_cmc_pktdma_desc_count_req[0]) +#define CMIC_CMC_PKTDMA_DESC_COUNT_REQr_COUNTf_SET(r,f) (r).cmic_cmc_pktdma_desc_count_req[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_DESC_COUNT_REQr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_DESC_COUNT_REQr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_count_req) +#define WRITE_CMIC_CMC_PKTDMA_DESC_COUNT_REQr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_DESC_COUNT_REQr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_count_req) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_DESC_COUNT_RX. + * + */ +typedef union CMIC_CMC_PKTDMA_DESC_COUNT_RXr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_desc_count_rx[1]; + uint32_t _cmic_cmc_pktdma_desc_count_rx; +} CMIC_CMC_PKTDMA_DESC_COUNT_RXr_t; + +#define CMIC_CMC_PKTDMA_DESC_COUNT_RXr_CLR(r) (r).cmic_cmc_pktdma_desc_count_rx[0] = 0 +#define CMIC_CMC_PKTDMA_DESC_COUNT_RXr_SET(r,d) (r).cmic_cmc_pktdma_desc_count_rx[0] = d +#define CMIC_CMC_PKTDMA_DESC_COUNT_RXr_GET(r) (r).cmic_cmc_pktdma_desc_count_rx[0] +#define CMIC_CMC_PKTDMA_DESC_COUNT_RXr_OFFSET 0x00003158 +#define CMIC_CMC_PKTDMA_DESC_COUNT_RXr_COUNTf_GET(r) ((r).cmic_cmc_pktdma_desc_count_rx[0]) +#define CMIC_CMC_PKTDMA_DESC_COUNT_RXr_COUNTf_SET(r,f) (r).cmic_cmc_pktdma_desc_count_rx[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_DESC_COUNT_RXr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_DESC_COUNT_RXr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_count_rx) +#define WRITE_CMIC_CMC_PKTDMA_DESC_COUNT_RXr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_DESC_COUNT_RXr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_count_rx) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WR. + * + */ +typedef union CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WRr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_desc_count_status_wr[1]; + uint32_t _cmic_cmc_pktdma_desc_count_status_wr; +} CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WRr_t; + +#define CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WRr_CLR(r) (r).cmic_cmc_pktdma_desc_count_status_wr[0] = 0 +#define CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WRr_SET(r,d) (r).cmic_cmc_pktdma_desc_count_status_wr[0] = d +#define CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WRr_GET(r) (r).cmic_cmc_pktdma_desc_count_status_wr[0] +#define CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WRr_OFFSET 0x0000315c +#define CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WRr_COUNTf_GET(r) ((r).cmic_cmc_pktdma_desc_count_status_wr[0]) +#define CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WRr_COUNTf_SET(r,f) (r).cmic_cmc_pktdma_desc_count_status_wr[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WRr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WRr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_count_status_wr) +#define WRITE_CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WRr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_DESC_COUNT_STATUS_WRr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_count_status_wr) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HI. + * + */ +typedef union CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HIr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_desc_halt_addr_hi[1]; + uint32_t _cmic_cmc_pktdma_desc_halt_addr_hi; +} CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HIr_t; + +#define CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HIr_CLR(r) (r).cmic_cmc_pktdma_desc_halt_addr_hi[0] = 0 +#define CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HIr_SET(r,d) (r).cmic_cmc_pktdma_desc_halt_addr_hi[0] = d +#define CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HIr_GET(r) (r).cmic_cmc_pktdma_desc_halt_addr_hi[0] +#define CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HIr_OFFSET 0x00003110 +#define CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HIr_ADDRf_GET(r) ((r).cmic_cmc_pktdma_desc_halt_addr_hi[0]) +#define CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HIr_ADDRf_SET(r,f) (r).cmic_cmc_pktdma_desc_halt_addr_hi[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HIr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HIr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_halt_addr_hi) +#define WRITE_CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HIr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_DESC_HALT_ADDR_HIr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_halt_addr_hi) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LO. + * + */ +typedef union CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LOr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_desc_halt_addr_lo[1]; + uint32_t _cmic_cmc_pktdma_desc_halt_addr_lo; +} CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LOr_t; + +#define CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LOr_CLR(r) (r).cmic_cmc_pktdma_desc_halt_addr_lo[0] = 0 +#define CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LOr_SET(r,d) (r).cmic_cmc_pktdma_desc_halt_addr_lo[0] = d +#define CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LOr_GET(r) (r).cmic_cmc_pktdma_desc_halt_addr_lo[0] +#define CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LOr_OFFSET 0x0000310c +#define CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LOr_ADDRf_GET(r) ((r).cmic_cmc_pktdma_desc_halt_addr_lo[0]) +#define CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LOr_ADDRf_SET(r,f) (r).cmic_cmc_pktdma_desc_halt_addr_lo[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LOr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LOr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_halt_addr_lo) +#define WRITE_CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LOr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_DESC_HALT_ADDR_LOr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_desc_halt_addr_lo) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_INTR. + * + */ +typedef union CMIC_CMC_PKTDMA_INTRr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_intr[1]; + uint32_t _cmic_cmc_pktdma_intr; +} CMIC_CMC_PKTDMA_INTRr_t; + +#define CMIC_CMC_PKTDMA_INTRr_CLR(r) (r).cmic_cmc_pktdma_intr[0] = 0 +#define CMIC_CMC_PKTDMA_INTRr_SET(r,d) (r).cmic_cmc_pktdma_intr[0] = d +#define CMIC_CMC_PKTDMA_INTRr_GET(r) (r).cmic_cmc_pktdma_intr[0] +#define CMIC_CMC_PKTDMA_INTRr_OFFSET 0x00003118 +#define CMIC_CMC_PKTDMA_INTRr_CHAIN_DONE_INTRf_GET(r) (((r).cmic_cmc_pktdma_intr[0]) & 0x1) +#define CMIC_CMC_PKTDMA_INTRr_CHAIN_DONE_INTRf_SET(r,f) (r).cmic_cmc_pktdma_intr[0]=(((r).cmic_cmc_pktdma_intr[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) +#define CMIC_CMC_PKTDMA_INTRr_DESC_DONE_INTRf_GET(r) ((((r).cmic_cmc_pktdma_intr[0]) >> 1) & 0x1) +#define CMIC_CMC_PKTDMA_INTRr_DESC_DONE_INTRf_SET(r,f) (r).cmic_cmc_pktdma_intr[0]=(((r).cmic_cmc_pktdma_intr[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) +#define CMIC_CMC_PKTDMA_INTRr_DESC_CONTROLLED_INTRf_GET(r) ((((r).cmic_cmc_pktdma_intr[0]) >> 2) & 0x1) +#define CMIC_CMC_PKTDMA_INTRr_DESC_CONTROLLED_INTRf_SET(r,f) (r).cmic_cmc_pktdma_intr[0]=(((r).cmic_cmc_pktdma_intr[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) +#define CMIC_CMC_PKTDMA_INTRr_INTR_COALESCING_INTRf_GET(r) ((((r).cmic_cmc_pktdma_intr[0]) >> 3) & 0x1) +#define CMIC_CMC_PKTDMA_INTRr_INTR_COALESCING_INTRf_SET(r,f) (r).cmic_cmc_pktdma_intr[0]=(((r).cmic_cmc_pktdma_intr[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) +#define READ_CMIC_CMC_PKTDMA_INTRr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_INTRr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_intr) +#define WRITE_CMIC_CMC_PKTDMA_INTRr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_INTRr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_intr) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_INTR_CLR. + * + */ +typedef union CMIC_CMC_PKTDMA_INTR_CLRr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_intr_clr[1]; + uint32_t _cmic_cmc_pktdma_intr_clr; +} CMIC_CMC_PKTDMA_INTR_CLRr_t; + +#define CMIC_CMC_PKTDMA_INTR_CLRr_CLR(r) (r).cmic_cmc_pktdma_intr_clr[0] = 0 +#define CMIC_CMC_PKTDMA_INTR_CLRr_SET(r,d) (r).cmic_cmc_pktdma_intr_clr[0] = d +#define CMIC_CMC_PKTDMA_INTR_CLRr_GET(r) (r).cmic_cmc_pktdma_intr_clr[0] +#define CMIC_CMC_PKTDMA_INTR_CLRr_OFFSET 0x00003120 +#define CMIC_CMC_PKTDMA_INTR_CLRr_DESC_DONE_INTR_CLRf_GET(r) ((((r).cmic_cmc_pktdma_intr_clr[0]) >> 1) & 0x1) +#define CMIC_CMC_PKTDMA_INTR_CLRr_DESC_DONE_INTR_CLRf_SET(r,f) (r).cmic_cmc_pktdma_intr_clr[0]=(((r).cmic_cmc_pktdma_intr_clr[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) +#define CMIC_CMC_PKTDMA_INTR_CLRr_DESC_CONTROLLED_INTR_CLRf_GET(r) ((((r).cmic_cmc_pktdma_intr_clr[0]) >> 2) & 0x1) +#define CMIC_CMC_PKTDMA_INTR_CLRr_DESC_CONTROLLED_INTR_CLRf_SET(r,f) (r).cmic_cmc_pktdma_intr_clr[0]=(((r).cmic_cmc_pktdma_intr_clr[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) +#define CMIC_CMC_PKTDMA_INTR_CLRr_INTR_COALESCING_INTR_CLRf_GET(r) ((((r).cmic_cmc_pktdma_intr_clr[0]) >> 3) & 0x1) +#define CMIC_CMC_PKTDMA_INTR_CLRr_INTR_COALESCING_INTR_CLRf_SET(r,f) (r).cmic_cmc_pktdma_intr_clr[0]=(((r).cmic_cmc_pktdma_intr_clr[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) +#define CMIC_CMC_PKTDMA_INTR_CLRr_DYN_RCNFG_ERR_CLRf_GET(r) ((((r).cmic_cmc_pktdma_intr_clr[0]) >> 4) & 0x1) +#define CMIC_CMC_PKTDMA_INTR_CLRr_DYN_RCNFG_ERR_CLRf_SET(r,f) (r).cmic_cmc_pktdma_intr_clr[0]=(((r).cmic_cmc_pktdma_intr_clr[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) +#define READ_CMIC_CMC_PKTDMA_INTR_CLRr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_INTR_CLRr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_intr_clr) +#define WRITE_CMIC_CMC_PKTDMA_INTR_CLRr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_INTR_CLRr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_intr_clr) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_INTR_COAL. + * + */ +typedef union CMIC_CMC_PKTDMA_INTR_COALr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_intr_coal[1]; + uint32_t _cmic_cmc_pktdma_intr_coal; +} CMIC_CMC_PKTDMA_INTR_COALr_t; + +#define CMIC_CMC_PKTDMA_INTR_COALr_CLR(r) (r).cmic_cmc_pktdma_intr_coal[0] = 0 +#define CMIC_CMC_PKTDMA_INTR_COALr_SET(r,d) (r).cmic_cmc_pktdma_intr_coal[0] = d +#define CMIC_CMC_PKTDMA_INTR_COALr_GET(r) (r).cmic_cmc_pktdma_intr_coal[0] +#define CMIC_CMC_PKTDMA_INTR_COALr_OFFSET 0x0000312c +#define CMIC_CMC_PKTDMA_INTR_COALr_TIMERf_GET(r) (((r).cmic_cmc_pktdma_intr_coal[0]) & 0xffff) +#define CMIC_CMC_PKTDMA_INTR_COALr_TIMERf_SET(r,f) (r).cmic_cmc_pktdma_intr_coal[0]=(((r).cmic_cmc_pktdma_intr_coal[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) +#define CMIC_CMC_PKTDMA_INTR_COALr_COUNTf_GET(r) ((((r).cmic_cmc_pktdma_intr_coal[0]) >> 16) & 0x7fff) +#define CMIC_CMC_PKTDMA_INTR_COALr_COUNTf_SET(r,f) (r).cmic_cmc_pktdma_intr_coal[0]=(((r).cmic_cmc_pktdma_intr_coal[0] & ~((uint32_t)0x7fff << 16)) | ((((uint32_t)f) & 0x7fff) << 16)) +#define CMIC_CMC_PKTDMA_INTR_COALr_ENABLEf_GET(r) ((((r).cmic_cmc_pktdma_intr_coal[0]) >> 31) & 0x1) +#define CMIC_CMC_PKTDMA_INTR_COALr_ENABLEf_SET(r,f) (r).cmic_cmc_pktdma_intr_coal[0]=(((r).cmic_cmc_pktdma_intr_coal[0] & ~((uint32_t)0x1 << 31)) | ((((uint32_t)f) & 0x1) << 31)) +#define READ_CMIC_CMC_PKTDMA_INTR_COALr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_INTR_COALr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_intr_coal) +#define WRITE_CMIC_CMC_PKTDMA_INTR_COALr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_INTR_COALr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_intr_coal) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_INTR_ENABLE. + * + */ +typedef union CMIC_CMC_PKTDMA_INTR_ENABLEr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_intr_enable[1]; + uint32_t _cmic_cmc_pktdma_intr_enable; +} CMIC_CMC_PKTDMA_INTR_ENABLEr_t; + +#define CMIC_CMC_PKTDMA_INTR_ENABLEr_CLR(r) (r).cmic_cmc_pktdma_intr_enable[0] = 0 +#define CMIC_CMC_PKTDMA_INTR_ENABLEr_SET(r,d) (r).cmic_cmc_pktdma_intr_enable[0] = d +#define CMIC_CMC_PKTDMA_INTR_ENABLEr_GET(r) (r).cmic_cmc_pktdma_intr_enable[0] +#define CMIC_CMC_PKTDMA_INTR_ENABLEr_OFFSET 0x0000311c +#define CMIC_CMC_PKTDMA_INTR_ENABLEr_CHAIN_DONE_INTR_ENABLEf_GET(r) (((r).cmic_cmc_pktdma_intr_enable[0]) & 0x1) +#define CMIC_CMC_PKTDMA_INTR_ENABLEr_CHAIN_DONE_INTR_ENABLEf_SET(r,f) (r).cmic_cmc_pktdma_intr_enable[0]=(((r).cmic_cmc_pktdma_intr_enable[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) +#define CMIC_CMC_PKTDMA_INTR_ENABLEr_DESC_DONE_INTR_ENABLEf_GET(r) ((((r).cmic_cmc_pktdma_intr_enable[0]) >> 1) & 0x1) +#define CMIC_CMC_PKTDMA_INTR_ENABLEr_DESC_DONE_INTR_ENABLEf_SET(r,f) (r).cmic_cmc_pktdma_intr_enable[0]=(((r).cmic_cmc_pktdma_intr_enable[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) +#define CMIC_CMC_PKTDMA_INTR_ENABLEr_DESC_CONTROLLED_INTR_ENABLEf_GET(r) ((((r).cmic_cmc_pktdma_intr_enable[0]) >> 2) & 0x1) +#define CMIC_CMC_PKTDMA_INTR_ENABLEr_DESC_CONTROLLED_INTR_ENABLEf_SET(r,f) (r).cmic_cmc_pktdma_intr_enable[0]=(((r).cmic_cmc_pktdma_intr_enable[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) +#define CMIC_CMC_PKTDMA_INTR_ENABLEr_INTR_COALESCING_INTR_ENABLEf_GET(r) ((((r).cmic_cmc_pktdma_intr_enable[0]) >> 3) & 0x1) +#define CMIC_CMC_PKTDMA_INTR_ENABLEr_INTR_COALESCING_INTR_ENABLEf_SET(r,f) (r).cmic_cmc_pktdma_intr_enable[0]=(((r).cmic_cmc_pktdma_intr_enable[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) +#define READ_CMIC_CMC_PKTDMA_INTR_ENABLEr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_INTR_ENABLEr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_intr_enable) +#define WRITE_CMIC_CMC_PKTDMA_INTR_ENABLEr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_INTR_ENABLEr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_intr_enable) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT. + * + */ +typedef union CMIC_CMC_PKTDMA_PKT_COUNT_RXPKTr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_pkt_count_rxpkt[1]; + uint32_t _cmic_cmc_pktdma_pkt_count_rxpkt; +} CMIC_CMC_PKTDMA_PKT_COUNT_RXPKTr_t; + +#define CMIC_CMC_PKTDMA_PKT_COUNT_RXPKTr_CLR(r) (r).cmic_cmc_pktdma_pkt_count_rxpkt[0] = 0 +#define CMIC_CMC_PKTDMA_PKT_COUNT_RXPKTr_SET(r,d) (r).cmic_cmc_pktdma_pkt_count_rxpkt[0] = d +#define CMIC_CMC_PKTDMA_PKT_COUNT_RXPKTr_GET(r) (r).cmic_cmc_pktdma_pkt_count_rxpkt[0] +#define CMIC_CMC_PKTDMA_PKT_COUNT_RXPKTr_OFFSET 0x00003148 +#define CMIC_CMC_PKTDMA_PKT_COUNT_RXPKTr_COUNTf_GET(r) ((r).cmic_cmc_pktdma_pkt_count_rxpkt[0]) +#define CMIC_CMC_PKTDMA_PKT_COUNT_RXPKTr_COUNTf_SET(r,f) (r).cmic_cmc_pktdma_pkt_count_rxpkt[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_PKT_COUNT_RXPKTr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_PKT_COUNT_RXPKTr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_pkt_count_rxpkt) +#define WRITE_CMIC_CMC_PKTDMA_PKT_COUNT_RXPKTr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_PKT_COUNT_RXPKTr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_pkt_count_rxpkt) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROP. + * + */ +typedef union CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROPr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_pkt_count_rxpkt_drop[1]; + uint32_t _cmic_cmc_pktdma_pkt_count_rxpkt_drop; +} CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROPr_t; + +#define CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROPr_CLR(r) (r).cmic_cmc_pktdma_pkt_count_rxpkt_drop[0] = 0 +#define CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROPr_SET(r,d) (r).cmic_cmc_pktdma_pkt_count_rxpkt_drop[0] = d +#define CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROPr_GET(r) (r).cmic_cmc_pktdma_pkt_count_rxpkt_drop[0] +#define CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROPr_OFFSET 0x00003150 +#define CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROPr_COUNTf_GET(r) ((r).cmic_cmc_pktdma_pkt_count_rxpkt_drop[0]) +#define CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROPr_COUNTf_SET(r,f) (r).cmic_cmc_pktdma_pkt_count_rxpkt_drop[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROPr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROPr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_pkt_count_rxpkt_drop) +#define WRITE_CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROPr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_PKT_COUNT_RXPKT_DROPr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_pkt_count_rxpkt_drop) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_PKT_COUNT_TXPKT. + * + */ +typedef union CMIC_CMC_PKTDMA_PKT_COUNT_TXPKTr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_pkt_count_txpkt[1]; + uint32_t _cmic_cmc_pktdma_pkt_count_txpkt; +} CMIC_CMC_PKTDMA_PKT_COUNT_TXPKTr_t; + +#define CMIC_CMC_PKTDMA_PKT_COUNT_TXPKTr_CLR(r) (r).cmic_cmc_pktdma_pkt_count_txpkt[0] = 0 +#define CMIC_CMC_PKTDMA_PKT_COUNT_TXPKTr_SET(r,d) (r).cmic_cmc_pktdma_pkt_count_txpkt[0] = d +#define CMIC_CMC_PKTDMA_PKT_COUNT_TXPKTr_GET(r) (r).cmic_cmc_pktdma_pkt_count_txpkt[0] +#define CMIC_CMC_PKTDMA_PKT_COUNT_TXPKTr_OFFSET 0x0000314c +#define CMIC_CMC_PKTDMA_PKT_COUNT_TXPKTr_COUNTf_GET(r) ((r).cmic_cmc_pktdma_pkt_count_txpkt[0]) +#define CMIC_CMC_PKTDMA_PKT_COUNT_TXPKTr_COUNTf_SET(r,f) (r).cmic_cmc_pktdma_pkt_count_txpkt[0]=((uint32_t)f) +#define READ_CMIC_CMC_PKTDMA_PKT_COUNT_TXPKTr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_PKT_COUNT_TXPKTr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_pkt_count_txpkt) +#define WRITE_CMIC_CMC_PKTDMA_PKT_COUNT_TXPKTr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_PKT_COUNT_TXPKTr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_pkt_count_txpkt) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIG. + * + */ +typedef union CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_rxbuf_threshold_config[1]; + uint32_t _cmic_cmc_pktdma_rxbuf_threshold_config; +} CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_t; + +#define CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_CLR(r) (r).cmic_cmc_pktdma_rxbuf_threshold_config[0] = 0 +#define CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_SET(r,d) (r).cmic_cmc_pktdma_rxbuf_threshold_config[0] = d +#define CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_GET(r) (r).cmic_cmc_pktdma_rxbuf_threshold_config[0] +#define CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_OFFSET 0x00003138 +#define CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_RXBUF_THRESHOLDf_GET(r) (((r).cmic_cmc_pktdma_rxbuf_threshold_config[0]) & 0x1ff) +#define CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_RXBUF_THRESHOLDf_SET(r,f) (r).cmic_cmc_pktdma_rxbuf_threshold_config[0]=(((r).cmic_cmc_pktdma_rxbuf_threshold_config[0] & ~((uint32_t)0x1ff)) | (((uint32_t)f) & 0x1ff)) +#define CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_ENABLEf_GET(r) ((((r).cmic_cmc_pktdma_rxbuf_threshold_config[0]) >> 9) & 0x1) +#define CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_ENABLEf_SET(r,f) (r).cmic_cmc_pktdma_rxbuf_threshold_config[0]=(((r).cmic_cmc_pktdma_rxbuf_threshold_config[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) +#define READ_CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_rxbuf_threshold_config) +#define WRITE_CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_RXBUF_THRESHOLD_CONFIGr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_rxbuf_threshold_config) + +/* + * This structure should be used to declare and program CMIC_CMC_PKTDMA_STAT. + * + */ +typedef union CMIC_CMC_PKTDMA_STATr_s { + uint32_t v[1]; + uint32_t cmic_cmc_pktdma_stat[1]; + uint32_t _cmic_cmc_pktdma_stat; +} CMIC_CMC_PKTDMA_STATr_t; + +#define CMIC_CMC_PKTDMA_STATr_CLR(r) (r).cmic_cmc_pktdma_stat[0] = 0 +#define CMIC_CMC_PKTDMA_STATr_SET(r,d) (r).cmic_cmc_pktdma_stat[0] = d +#define CMIC_CMC_PKTDMA_STATr_GET(r) (r).cmic_cmc_pktdma_stat[0] +#define CMIC_CMC_PKTDMA_STATr_OFFSET 0x00003114 +#define CMIC_CMC_PKTDMA_STATr_CHAIN_DONEf_GET(r) (((r).cmic_cmc_pktdma_stat[0]) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_CHAIN_DONEf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) +#define CMIC_CMC_PKTDMA_STATr_DMA_ACTIVEf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 1) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_DMA_ACTIVEf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) +#define CMIC_CMC_PKTDMA_STATr_STWT_ADDR_DECODE_ERRf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 2) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_STWT_ADDR_DECODE_ERRf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) +#define CMIC_CMC_PKTDMA_STATr_PKTWRRD_ADDR_DECODE_ERRf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 3) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_PKTWRRD_ADDR_DECODE_ERRf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) +#define CMIC_CMC_PKTDMA_STATr_DESCRD_ADDR_DECODE_ERRf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 4) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_DESCRD_ADDR_DECODE_ERRf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) +#define CMIC_CMC_PKTDMA_STATr_PKTWR_ECC_ERRf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 5) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_PKTWR_ECC_ERRf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 5)) | ((((uint32_t)f) & 0x1) << 5)) +#define CMIC_CMC_PKTDMA_STATr_CH_IN_HALTf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 6) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_CH_IN_HALTf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 6)) | ((((uint32_t)f) & 0x1) << 6)) +#define CMIC_CMC_PKTDMA_STATr_RELOAD_UNALIGNED_ERRf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 7) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_RELOAD_UNALIGNED_ERRf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 7)) | ((((uint32_t)f) & 0x1) << 7)) +#define CMIC_CMC_PKTDMA_STATr_DESC_DONEf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 8) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_DESC_DONEf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) +#define CMIC_CMC_PKTDMA_STATr_DESC_CONTROLLEDf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 9) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_DESC_CONTROLLEDf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) +#define CMIC_CMC_PKTDMA_STATr_INTR_COALESCINGf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 10) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_INTR_COALESCINGf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) +#define CMIC_CMC_PKTDMA_STATr_DYN_RCNFG_ERRf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 11) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_DYN_RCNFG_ERRf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 11)) | ((((uint32_t)f) & 0x1) << 11)) +#define CMIC_CMC_PKTDMA_STATr_INVALID_AXI_CMD_ERRf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 12) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_INVALID_AXI_CMD_ERRf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) +#define CMIC_CMC_PKTDMA_STATr_DMA_IS_ENf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 13) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_DMA_IS_ENf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 13)) | ((((uint32_t)f) & 0x1) << 13)) +#define CMIC_CMC_PKTDMA_STATr_DESC_MEM_ECC_ERRf_GET(r) ((((r).cmic_cmc_pktdma_stat[0]) >> 14) & 0x1) +#define CMIC_CMC_PKTDMA_STATr_DESC_MEM_ECC_ERRf_SET(r,f) (r).cmic_cmc_pktdma_stat[0]=(((r).cmic_cmc_pktdma_stat[0] & ~((uint32_t)0x1 << 14)) | ((((uint32_t)f) & 0x1) << 14)) +#define READ_CMIC_CMC_PKTDMA_STATr(u,_cmc,_ch,r) BCMDRD_DEV_READ32(u,CMIC_CMC_PKTDMA_STATr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_stat) +#define WRITE_CMIC_CMC_PKTDMA_STATr(u,_cmc,_ch,r) BCMDRD_DEV_WRITE32(u,CMIC_CMC_PKTDMA_STATr_OFFSET+(0x80*(_ch))+(0x2000*(_cmc)),r._cmic_cmc_pktdma_stat) + +#define RX_DCB_SIZE 16 +#define TX_DCB_SIZE 16 + +/* + * This structure should be used to declare and program TX_DCB. + * + */ +typedef union TX_DCB_s { + uint32_t v[4]; + uint32_t tx_dcb[4]; + uint32_t _tx_dcb; +} TX_DCB_t; + +#define TX_DCB_CLR(r) sal_memset(&((r).tx_dcb[0]), 0, sizeof(TX_DCB_t)) +#define TX_DCB_SET(r,i,d) (r).tx_dcb[i] = d +#define TX_DCB_GET(r,i) (r).tx_dcb[i] +#define TX_DCB_OFFSET 0x00000000 +#define TX_DCB_BYTES_TRANSFERREDf_GET(r) (((r).tx_dcb[3]) & 0xffff) +#define TX_DCB_BYTES_TRANSFERREDf_SET(r,f) (r).tx_dcb[3]=(((r).tx_dcb[3] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) +#define TX_DCB_DONEf_GET(r) ((((r).tx_dcb[3]) >> 31) & 0x1) +#define TX_DCB_DONEf_SET(r,f) (r).tx_dcb[3]=(((r).tx_dcb[3] & ~((uint32_t)0x1 << 31)) | ((((uint32_t)f) & 0x1) << 31)) +#define TX_DCB_BYTE_COUNTf_GET(r) (((r).tx_dcb[2]) & 0xffff) +#define TX_DCB_BYTE_COUNTf_SET(r,f) (r).tx_dcb[2]=(((r).tx_dcb[2] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) +#define TX_DCB_CHAINf_GET(r) ((((r).tx_dcb[2]) >> 16) & 0x1) +#define TX_DCB_CHAINf_SET(r,f) (r).tx_dcb[2]=(((r).tx_dcb[2] & ~((uint32_t)0x1 << 16)) | ((((uint32_t)f) & 0x1) << 16)) +#define TX_DCB_SGf_GET(r) ((((r).tx_dcb[2]) >> 17) & 0x1) +#define TX_DCB_SGf_SET(r,f) (r).tx_dcb[2]=(((r).tx_dcb[2] & ~((uint32_t)0x1 << 17)) | ((((uint32_t)f) & 0x1) << 17)) +#define TX_DCB_RELOADf_GET(r) ((((r).tx_dcb[2]) >> 18) & 0x1) +#define TX_DCB_RELOADf_SET(r,f) (r).tx_dcb[2]=(((r).tx_dcb[2] & ~((uint32_t)0x1 << 18)) | ((((uint32_t)f) & 0x1) << 18)) +#define TX_DCB_HGf_GET(r) ((((r).tx_dcb[2]) >> 19) & 0x1) +#define TX_DCB_HGf_SET(r,f) (r).tx_dcb[2]=(((r).tx_dcb[2] & ~((uint32_t)0x1 << 19)) | ((((uint32_t)f) & 0x1) << 19)) +#define TX_DCB_ALIGN_BYTESf_GET(r) ((((r).tx_dcb[2]) >> 20) & 0x3) +#define TX_DCB_ALIGN_BYTESf_SET(r,f) (r).tx_dcb[2]=(((r).tx_dcb[2] & ~((uint32_t)0x3 << 20)) | ((((uint32_t)f) & 0x3) << 20)) +#define TX_DCB_PURGEf_GET(r) ((((r).tx_dcb[2]) >> 22) & 0x1) +#define TX_DCB_PURGEf_SET(r,f) (r).tx_dcb[2]=(((r).tx_dcb[2] & ~((uint32_t)0x1 << 22)) | ((((uint32_t)f) & 0x1) << 22)) +#define TX_DCB_DESC_DONE_INTRf_GET(r) ((((r).tx_dcb[2]) >> 23) & 0x1) +#define TX_DCB_DESC_DONE_INTRf_SET(r,f) (r).tx_dcb[2]=(((r).tx_dcb[2] & ~((uint32_t)0x1 << 23)) | ((((uint32_t)f) & 0x1) << 23)) +#define TX_DCB_DESC_CTRL_INTRf_GET(r) ((((r).tx_dcb[2]) >> 24) & 0x1) +#define TX_DCB_DESC_CTRL_INTRf_SET(r,f) (r).tx_dcb[2]=(((r).tx_dcb[2] & ~((uint32_t)0x1 << 24)) | ((((uint32_t)f) & 0x1) << 24)) +#define TX_DCB_DESC_REMAINf_GET(r) ((((r).tx_dcb[2]) >> 25) & 0x3f) +#define TX_DCB_DESC_REMAINf_SET(r,f) (r).tx_dcb[2]=(((r).tx_dcb[2] & ~((uint32_t)0x3f << 25)) | ((((uint32_t)f) & 0x3f) << 25)) +#define TX_DCB_DESC_STAT_WR_DISABLEf_GET(r) ((((r).tx_dcb[2]) >> 31) & 0x1) +#define TX_DCB_DESC_STAT_WR_DISABLEf_SET(r,f) (r).tx_dcb[2]=(((r).tx_dcb[2] & ~((uint32_t)0x1 << 31)) | ((((uint32_t)f) & 0x1) << 31)) +#define TX_DCB_ADDR_HIf_GET(r) ((r).tx_dcb[1]) +#define TX_DCB_ADDR_HIf_SET(r,f) (r).tx_dcb[1]=((uint32_t)f) +#define TX_DCB_ADDR_LOf_GET(r) ((r).tx_dcb[0]) +#define TX_DCB_ADDR_LOf_SET(r,f) (r).tx_dcb[0]=((uint32_t)f) + +/* + * This structure should be used to declare and program RX_DCB. + * + */ +typedef union RX_DCB_s { + uint32_t v[4]; + uint32_t rx_dcb[4]; + uint32_t _rx_dcb; +} RX_DCB_t; + +#define RX_DCB_CLR(r) sal_memset(&((r).rx_dcb[0]), 0, sizeof(RX_DCB_t)) +#define RX_DCB_SET(r,i,d) (r).rx_dcb[i] = d +#define RX_DCB_GET(r,i) (r).rx_dcb[i] +#define RX_DCB_OFFSET 0x00000000 +#define RX_DCB_BYTES_TRANSFERREDf_GET(r) (((r).rx_dcb[3]) & 0xffff) +#define RX_DCB_BYTES_TRANSFERREDf_SET(r,f) (r).rx_dcb[3]=(((r).rx_dcb[3] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) +#define RX_DCB_END_BITf_GET(r) ((((r).rx_dcb[3]) >> 16) & 0x1) +#define RX_DCB_END_BITf_SET(r,f) (r).rx_dcb[3]=(((r).rx_dcb[3] & ~((uint32_t)0x1 << 16)) | ((((uint32_t)f) & 0x1) << 16)) +#define RX_DCB_START_BITf_GET(r) ((((r).rx_dcb[3]) >> 17) & 0x1) +#define RX_DCB_START_BITf_SET(r,f) (r).rx_dcb[3]=(((r).rx_dcb[3] & ~((uint32_t)0x1 << 17)) | ((((uint32_t)f) & 0x1) << 17)) +#define RX_DCB_CELL_ERRORf_GET(r) ((((r).rx_dcb[3]) >> 18) & 0x1) +#define RX_DCB_CELL_ERRORf_SET(r,f) (r).rx_dcb[3]=(((r).rx_dcb[3] & ~((uint32_t)0x1 << 18)) | ((((uint32_t)f) & 0x1) << 18)) +#define RX_DCB_ECC_ERRORf_GET(r) ((((r).rx_dcb[3]) >> 19) & 0x1) +#define RX_DCB_ECC_ERRORf_SET(r,f) (r).rx_dcb[3]=(((r).rx_dcb[3] & ~((uint32_t)0x1 << 19)) | ((((uint32_t)f) & 0x1) << 19)) +#define RX_DCB_DONEf_GET(r) ((((r).rx_dcb[3]) >> 31) & 0x1) +#define RX_DCB_DONEf_SET(r,f) (r).rx_dcb[3]=(((r).rx_dcb[3] & ~((uint32_t)0x1 << 31)) | ((((uint32_t)f) & 0x1) << 31)) +#define RX_DCB_BYTE_COUNTf_GET(r) (((r).rx_dcb[2]) & 0xffff) +#define RX_DCB_BYTE_COUNTf_SET(r,f) (r).rx_dcb[2]=(((r).rx_dcb[2] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) +#define RX_DCB_CHAINf_GET(r) ((((r).rx_dcb[2]) >> 16) & 0x1) +#define RX_DCB_CHAINf_SET(r,f) (r).rx_dcb[2]=(((r).rx_dcb[2] & ~((uint32_t)0x1 << 16)) | ((((uint32_t)f) & 0x1) << 16)) +#define RX_DCB_SGf_GET(r) ((((r).rx_dcb[2]) >> 17) & 0x1) +#define RX_DCB_SGf_SET(r,f) (r).rx_dcb[2]=(((r).rx_dcb[2] & ~((uint32_t)0x1 << 17)) | ((((uint32_t)f) & 0x1) << 17)) +#define RX_DCB_RELOADf_GET(r) ((((r).rx_dcb[2]) >> 18) & 0x1) +#define RX_DCB_RELOADf_SET(r,f) (r).rx_dcb[2]=(((r).rx_dcb[2] & ~((uint32_t)0x1 << 18)) | ((((uint32_t)f) & 0x1) << 18)) +#define RX_DCB_ALIGN_BYTESf_GET(r) ((((r).rx_dcb[2]) >> 20) & 0x3) +#define RX_DCB_ALIGN_BYTESf_SET(r,f) (r).rx_dcb[2]=(((r).rx_dcb[2] & ~((uint32_t)0x3 << 20)) | ((((uint32_t)f) & 0x3) << 20)) +#define RX_DCB_DESC_DONE_INTRf_GET(r) ((((r).rx_dcb[2]) >> 23) & 0x1) +#define RX_DCB_DESC_DONE_INTRf_SET(r,f) (r).rx_dcb[2]=(((r).rx_dcb[2] & ~((uint32_t)0x1 << 23)) | ((((uint32_t)f) & 0x1) << 23)) +#define RX_DCB_DESC_CTRL_INTRf_GET(r) ((((r).rx_dcb[2]) >> 24) & 0x1) +#define RX_DCB_DESC_CTRL_INTRf_SET(r,f) (r).rx_dcb[2]=(((r).rx_dcb[2] & ~((uint32_t)0x1 << 24)) | ((((uint32_t)f) & 0x1) << 24)) +#define RX_DCB_DESC_REMAINf_GET(r) ((((r).rx_dcb[2]) >> 25) & 0x3f) +#define RX_DCB_DESC_REMAINf_SET(r,f) (r).rx_dcb[2]=(((r).rx_dcb[2] & ~((uint32_t)0x3f << 25)) | ((((uint32_t)f) & 0x3f) << 25)) +#define RX_DCB_DESC_STAT_WR_DISABLEf_GET(r) ((((r).rx_dcb[2]) >> 31) & 0x1) +#define RX_DCB_DESC_STAT_WR_DISABLEf_SET(r,f) (r).rx_dcb[2]=(((r).rx_dcb[2] & ~((uint32_t)0x1 << 31)) | ((((uint32_t)f) & 0x1) << 31)) +#define RX_DCB_ADDR_HIf_GET(r) ((r).rx_dcb[1]) +#define RX_DCB_ADDR_HIf_SET(r,f) (r).rx_dcb[1]=((uint32_t)f) +#define RX_DCB_ADDR_LOf_GET(r) ((r).rx_dcb[0]) +#define RX_DCB_ADDR_LOf_SET(r,f) (r).rx_dcb[0]=((uint32_t)f) + +#endif /* BCMCNET_CMICR_ACC_H */ diff --git a/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicx.h b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicx.h new file mode 100644 index 0000000..076c06d --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_cmicx.h @@ -0,0 +1,397 @@ +/*! \file bcmcnet_cmicx.h + * + * CMICx registers and descriptors definitions. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMCNET_CMICX_H +#define BCMCNET_CMICX_H + +/*! + * \name CMICX PDMA HW definitions + */ +/*! \{ */ +/*! CMICX CMC number */ +#define CMICX_PDMA_CMC_MAX 2 +/*! CMICX CMC PDMA channels */ +#define CMICX_PDMA_CMC_CHAN 8 +/*! CMICX PDMA DCB size */ +#define CMICX_PDMA_DCB_SIZE 16 +/*! \} */ + +/*! + * \name CMICX PCIe device address definitions + */ +/*! \{ */ +/*! CMICX PCIE offset */ +#define CMICX_PCIE_SO_OFFSET 0x10000000 +#ifdef IPROC_CMICD +#define DMA_TO_BUS_HI(dma) (dma) +#define BUS_TO_DMA_HI(bus) (bus) +#else +/*! Higher DMA address to bus address */ +#define DMA_TO_BUS_HI(dma) ((dma) | CMICX_PCIE_SO_OFFSET) +/*! Higher bus address to DMA address */ +#define BUS_TO_DMA_HI(bus) ((bus) & ~CMICX_PCIE_SO_OFFSET) +#endif +/*! \} */ + +/*! + * \name CMICX PDMA register definitions + */ +/*! \{ */ +#define CMICX_PDMA_CTRLr 0x2100 +#define CMICX_PDMA_STATr 0x2114 +#define CMICX_PDMA_DESC_LOr 0x2104 +#define CMICX_PDMA_DESC_HIr 0x2108 +#define CMICX_PDMA_CURR_DESC_LOr 0x2124 +#define CMICX_PDMA_CURR_DESC_HIr 0x2128 +#define CMICX_PDMA_DESC_HALT_LOr 0x210c +#define CMICX_PDMA_DESC_HALT_HIr 0x2110 +#define CMICX_PDMA_COS_CTRL_RX0r 0x2118 +#define CMICX_PDMA_COS_CTRL_RX1r 0x211c +#define CMICX_PDMA_INTR_COALr 0x2120 +#define CMICX_PDMA_RBUF_THREr 0x212c +#define CMICX_PDMA_DEBUG_CTRLr 0x2130 +#define CMICX_PDMA_DEBUG_SM_STATr 0x2134 +#define CMICX_PDMA_DEBUG_STATr 0x2138 +#define CMICX_PDMA_COUNT_RXr 0x213c +#define CMICX_PDMA_COUNT_TXr 0x2140 +#define CMICX_PDMA_COUNT_RX_DROPr 0x2144 +#define CMICX_PDMA_DESC_CNT_REQr 0x2148 +#define CMICX_PDMA_DESC_CNT_RXr 0x214c +#define CMICX_PDMA_DESC_CNT_STATr 0x2150 +#define CMICX_PDMA_IRQ_STATr 0x106c +#define CMICX_PDMA_IRQ_STAT_CLRr 0x1074 +/*! \} */ + +/*! + * \name CMICX PDMA register address + */ +/*! \{ */ +/*! Base address */ +#define CMICX_GRP_BASE(g) (0x00000000 + 0x3000 * g) +/*! Control register address */ +#define CMICX_PDMA_CTRL(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_CTRLr + q * 0x80) +/*! Status register address */ +#define CMICX_PDMA_STAT(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_STATr + q * 0x80) +/*! Descriptor Address Lower register address */ +#define CMICX_PDMA_DESC_LO(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_DESC_LOr + q * 0x80) +/*! Descriptor Address Higher register address */ +#define CMICX_PDMA_DESC_HI(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_DESC_HIr + q * 0x80) +/*! Current Descriptor Address Lower register address */ +#define CMICX_PDMA_CURR_DESC_LO(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_CURR_DESC_LOr + q * 0x80) +/*! Current Descriptor Address Higher register address */ +#define CMICX_PDMA_CURR_DESC_HI(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_CURR_DESC_HIr + q * 0x80) +/*! Descriptor Halt Address Lower register address */ +#define CMICX_PDMA_DESC_HALT_LO(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_DESC_HALT_LOr + q * 0x80) +/*! Descriptor Halt Address Higher register address */ +#define CMICX_PDMA_DESC_HALT_HI(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_DESC_HALT_HIr + q * 0x80) +/*! COS Control Rx0 register address */ +#define CMICX_PDMA_COS_CTRL_RX0(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_COS_CTRL_RX0r + q * 0x80) +/*! COS Control Rx1 register address */ +#define CMICX_PDMA_COS_CTRL_RX1(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_COS_CTRL_RX1r + q * 0x80) +/*! Interrupt Coalesce register address */ +#define CMICX_PDMA_INTR_COAL(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_INTR_COALr + q * 0x80) +/*! Rx Buffer Threshhold register address */ +#define CMICX_PDMA_RBUF_THRE(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_RBUF_THREr + q * 0x80) +/*! Debug Control register address */ +#define CMICX_PDMA_DEBUG_CTRL(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_DEBUG_CTRLr + q * 0x80) +/*! Debug Status register address */ +#define CMICX_PDMA_DEBUG_STAT(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_DEBUG_STATr + q * 0x80) +/*! Debug State Machine Status register address */ +#define CMICX_PDMA_DEBUG_SM_STAT(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_DEBUG_SM_STATr + q * 0x80) +/*! Rx Packet Count register address */ +#define CMICX_PDMA_COUNT_RX(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_COUNT_RXr + q * 0x80) +/*! Tx Packet Count register address */ +#define CMICX_PDMA_COUNT_TX(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_COUNT_TXr + q * 0x80) +/*! Dropped Rx Packet Count register address */ +#define CMICX_PDMA_COUNT_RX_DROP(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_COUNT_RX_DROPr + q * 0x80) +/*! Requested Descriptor Count register address */ +#define CMICX_PDMA_DESC_CNT_REQ(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_DESC_CNT_REQr + q * 0x80) +/*! Received Descriptor Count register address */ +#define CMICX_PDMA_DESC_CNT_RX(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_DESC_CNT_RXr + q * 0x80) +/*! Updated Descriptor Count register address */ +#define CMICX_PDMA_DESC_CNT_STAT(g, q) (CMICX_GRP_BASE(g) + CMICX_PDMA_DESC_CNT_STATr + q * 0x80) +/*! Interrupt Status register address */ +#define CMICX_PDMA_IRQ_STAT(g) (CMICX_GRP_BASE(g) + CMICX_PDMA_IRQ_STATr) +/*! Interrupt Status Clear register address */ +#define CMICX_PDMA_IRQ_STAT_CLR(g) (CMICX_GRP_BASE(g) + CMICX_PDMA_IRQ_STAT_CLRr) +/*! Interrupt Enable register address0 */ +#define CMICX_PDMA_IRQ_ENAB0 0x18013100 +/*! Interrupt Enable register address1 */ +#define CMICX_PDMA_IRQ_ENAB1 0x18013104 +/*! Interrupt Enable register address2 */ +#define CMICX_PDMA_IRQ_ENAB2 0x18013108 +/*! Interrupt raw status register address0 */ +#define CMICX_PDMA_IRQ_RAW_STAT0 0x18013150 +/*! Interrupt raw status register address1 */ +#define CMICX_PDMA_IRQ_RAW_STAT1 0x18013154 +/*! Interrupt raw status register address2 */ +#define CMICX_PDMA_IRQ_RAW_STAT2 0x18013158 +/*! EP_TO_CPU Header Size register address */ +#define CMICX_EP_TO_CPU_HEADER_SIZE 0x00000004 +/*! Top config register address */ +#define CMICX_TOP_CONFIG 0x00000008 +/*! Credits release register address */ +#define CMICX_EPINTF_RELEASE_CREDITS 0x0000006c +/*! Max credits register address */ +#define CMICX_EPINTF_MAX_CREDITS 0x00000070 +/*! \} */ + +/*! + * \name Control register definitions + */ +/*! \{ */ +/*! Disable abort on error */ +#define CMICX_PDMA_NO_ABORT_ON_ERR 0x00002000 +/*! EP_TO_CPU header big endianess */ +#define CMICX_PDMA_HDR_BIG_ENDIAN 0x00001000 +/*! Continuous descriptor mode */ +#define CMICX_PDMA_CONTINUOUS_DESC 0x00000200 +/*! Continuous DMA mode */ +#define CMICX_PDMA_CONTINUOUS 0x00000100 +/*! Interrupt after descriptor */ +#define CMICX_PDMA_INTR_ON_DESC 0x00000080 +/*! Update status on reload */ +#define CMICX_PDMA_RLD_STAT_DIS 0x00000040 +/*! Dropped on chain end */ +#define CMICX_PDMA_DROP_ON_END 0x00000020 +/*! Descriptor big endianess */ +#define CMICX_PDMA_DESC_BIG_ENDIAN 0x00000010 +/*! Packet DMA big endianess */ +#define CMICX_PDMA_PKT_BIG_ENDIAN 0x00000008 +/*! Abort DMA */ +#define CMICX_PDMA_ABORT 0x00000004 +/*! Enable DMA */ +#define CMICX_PDMA_ENABLE 0x00000002 +/*! DMA direction */ +#define CMICX_PDMA_DIR 0x00000001 +/*! EP_TO_CPU header alignment bytes */ +#define CMICX_PDMA_HDR_ALMNT(bytes) (((bytes) & 0x3) << 10) +/*! \} */ + +/*! + * \name Status register definitions + */ +/*! \{ */ +/*! Channel in halt */ +#define CMICX_PDMA_IN_HALT 0x00000040 +/*! Channel active */ +#define CMICX_PDMA_IS_ACTIVE 0x00000002 +/*! Chain done */ +#define CMICX_PDMA_CHAIN_DONE 0x00000001 +/*! \} */ + +/*! + * \name Interrupt_coalesce register definitions + */ +/*! \{ */ +/*! Interrupt coalesce enable */ +#define CMICX_PDMA_INTR_COAL_ENA (1 << 31) +/*! Interrupt coalesce threshhold */ +#define CMICX_PDMA_INTR_THRESH(cnt) (((cnt) & 0x7fff) << 16) +/*! Interrupt coalesce timeout */ +#define CMICX_PDMA_INTR_TIMER(tmr) ((tmr) & 0xffff) +/*! \} */ + +/*! + * \name Interrupt status&clear register definitions + */ +/*! \{ */ +/*! Descriptor done */ +#define CMICX_PDMA_IRQ_DESC_DONE(q) (0x00000001 << ((q) * 4)) +/*! Chain done */ +#define CMICX_PDMA_IRQ_CHAIN_DONE(q) (0x00000002 << ((q) * 4)) +/*! Coalescing interrupt */ +#define CMICX_PDMA_IRQ_COALESCE_INTR(q) (0x00000004 << ((q) * 4)) +/*! Controlled interrupt */ +#define CMICX_PDMA_IRQ_CTRLD_INTR(q) (0x00000008 << ((q) * 4)) +/*! Interrupt mask */ +#define CMICX_PDMA_IRQ_MASK(q) (0xf << ((q) * 4)) +/*! Interrupt start number */ +#define CMICX_IRQ_START_NUM (128 + 3) +/*! Interrupt number offset */ +#define CMICX_IRQ_NUM_OFFSET 4 +/*! Interrupt mask shift */ +#define CMICX_IRQ_MASK_SHIFT 16 +/*! \} */ + +/*! 32-bit register read */ +#define DEV_READ32(_c, _a, _p) \ + do { \ + if ((_c)->dev->mode != DEV_MODE_VNET) { \ + *(_p) = ((volatile uint32_t *)(_c)->hw_addr)[(_a) / 4]; \ + } \ + } while (0) + +/*! 32-bit register write */ +#define DEV_WRITE32(_c, _a, _v) \ + do { \ + if ((_c)->dev->mode != DEV_MODE_VNET) { \ + ((volatile uint32_t *)(_c)->hw_addr)[(_a) / 4] = (_v); \ + } \ + } while (0) + +/*! + * \brief Rx descriptor. + */ +struct cmicx_rx_desc { + /*! Packet address lower */ + volatile uint32_t addr_lo; + + /*! Packet address higher */ + volatile uint32_t addr_hi; + + /*! Packet control */ + volatile uint32_t ctrl; + + /*! Packet status */ + volatile uint32_t status; +} __attribute__((packed)); + +/*! + * \brief Tx descriptor. + */ +struct cmicx_tx_desc { + /*! Packet address lower */ + volatile uint32_t addr_lo; + + /*! Packet address higher */ + volatile uint32_t addr_hi; + + /*! Packet control */ + volatile uint32_t ctrl; + + /*! Packet status */ + volatile uint32_t status; +} __attribute__((packed)); + +/*! + * Flags related to descriptors. + */ +/*! Disable descriptor status write */ +#define CMICX_DESC_CTRL_STAT_WR_DIS (1 << 29) +/*! Descriptors remaining */ +#define CMICX_DESC_CTRL_REMAIN(cnt) (((cnt) & 0xf) << 25) +/*! Max remaining descriptors */ +#define CMICX_DESC_REMAIN_MAX 8 +/*! Controlled interrupt */ +#define CMICX_DESC_CTRL_CNTLD_INTR (1 << 24) +/*! Completed interrupt */ +#define CMICX_DESC_CTRL_CMPLT_INTR (1 << 23) +/*! Reload DCB */ +#define CMICX_DESC_CTRL_RELOAD (1 << 18) +/*! Scatter DCB */ +#define CMICX_DESC_CTRL_SCATTER (1 << 17) +/*! Chained DCB */ +#define CMICX_DESC_CTRL_CHAIN (1 << 16) +/*! Control flags */ +#define CMICX_DESC_CTRL_FLAGS(f) (((f) & 0xffff) << 16) +/*! Purge packet */ +#define CMICX_DESC_TX_PURGE_PKT (1 << 6) +/*! Higig packet */ +#define CMICX_DESC_TX_HIGIG_PKT (1 << 3) +/*! Packet length */ +#define CMICX_DESC_CTRL_LEN(len) ((len) & 0xffff) +/*! Done */ +#define CMICX_DESC_STAT_RTX_DONE (1u << 31) +/*! Ecc error */ +#define CMICX_DESC_STAT_DATA_ERR (1 << 19) +/*! Cell error */ +#define CMICX_DESC_STAT_CELL_ERR (1 << 18) +/*! Error mask */ +#define CMICX_DESC_STAT_ERR_MASK (CMICX_DESC_STAT_DATA_ERR | \ + CMICX_DESC_STAT_CELL_ERR) +/*! Packet start */ +#define CMICX_DESC_STAT_PKT_START (1 << 17) +/*! Packet end */ +#define CMICX_DESC_STAT_PKT_END (1 << 16) +/*! Get done state */ +#define CMICX_DESC_STAT_DONE(stat) ((stat) & CMICX_DESC_STAT_RTX_DONE) +/*! Get flags */ +#define CMICX_DESC_STAT_FLAGS(stat) (((stat) >> 16) & ~0x8003) +/*! Get packet length */ +#define CMICX_DESC_STAT_LEN(stat) ((stat) & 0xffff) + +/*! Tx packet header size */ +#define CMICX_TX_PKT_HDR_SIZE 16 + +/*! HW access retry times */ +#define CMICX_HW_RETRY_TIMES 100000 + +/*! + * \brief Initialize HW handles. + * + * \param [in] hw HW structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_cmicx_pdma_hw_hdls_init(struct pdma_hw *hw); + +/*! + * \brief Initialize descriptor operations. + * + * \param [in] hw HW structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_cmicx_pdma_desc_ops_init(struct pdma_hw *hw); + +/*! + * \brief Attach device driver. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_cmicx_pdma_driver_attach(struct pdma_dev *dev); + +/*! + * \brief Detach device driver. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_cmicx_pdma_driver_detach(struct pdma_dev *dev); + +#endif /* BCMCNET_CMICX_H */ + diff --git a/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_core.h b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_core.h new file mode 100644 index 0000000..25ccfab --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_core.h @@ -0,0 +1,1376 @@ +/*! \file bcmcnet_core.h + * + * Generic data structure definitions and APIs for BCMCNET driver. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMCNET_CORE_H +#define BCMCNET_CORE_H + +#include +#include + +/*! + * \brief Packet header structure. + */ +struct pkt_hdr { + /*! Meta data or outer header */ + uint8_t meta_data[16]; + + /*! Reserved */ + uint16_t rsvd0; + + /*! Packet signature */ + uint16_t pkt_sig; + + /*! Reserved */ + uint32_t rsvd1; + + /*! Data length */ + uint16_t data_len; + + /*! Header profile */ + uint16_t hdr_prof; + + /*! Meta length */ + uint8_t meta_len; + + /*! Queue index */ + uint8_t queue_id; + + /*! Attributes */ + uint16_t attrs; + /*! Tx higig packet */ +#define PDMA_TX_HIGIG_PKT (1 << 0) + /*! Tx pause packet */ +#define PDMA_TX_PAUSE_PKT (1 << 1) + /*! Tx purge packet */ +#define PDMA_TX_PURGE_PKT (1 << 2) + /*! Tx queue number */ +#define PDMA_TX_BIND_QUE (1 << 3) + /*! Tx cookded header */ +#define PDMA_TX_HDR_COOKED (1 << 4) + /*! Tx no pad */ +#define PDMA_TX_NO_PAD (1 << 5) + /*! Tx to HNET */ +#define PDMA_TX_TO_HNET (1 << 6) + /*! Tx data RAW mode */ +#define PDMA_TX_DATA_RAW (1 << 7) + /*! Rx to VNET */ +#define PDMA_RX_TO_VNET (1 << 10) + /*! Rx strip vlan tag */ +#define PDMA_RX_STRIP_TAG (1 << 11) + /*! Rx set protocol type */ +#define PDMA_RX_SET_PROTO (1 << 12) + /*! Rx IP checksum */ +#define PDMA_RX_IP_CSUM (1 << 13) + /*! Rx TCPUDP checksum */ +#define PDMA_RX_TU_CSUM (1 << 14) +}; + +/*! Packet header size */ +#define PKT_HDR_SIZE sizeof(struct pkt_hdr) + +/*! + * \brief Packet buffer structure. + */ +struct pkt_buf { + /*! Packet header */ + struct pkt_hdr pkh; + + /*! Packet data */ + uint8_t data; +}; + +/*! + * \brief Interrupt handle. + */ +struct intr_handle { + /*! Device number */ + int unit; + + /*! Group number */ + int group; + + /*! Channel number */ + int chan; + + /*! Queue number */ + int queue; + + /*! Direction */ + int dir; + + /*! Polling budget */ + int budget; + + /*! Device point */ + void *dev; + + /*! Private point */ + void *priv; + + /*! Interrupt number */ + int inum; + + /*! Interrupt flags */ + uint32_t intr_flags; + + /*! Extra polling after queue is empty */ + bool extra_poll; +}; + +/*! + * \brief Queue group structure. + */ +struct queue_group { + /*! Pointer to the device control structure */ + struct dev_ctrl *ctrl; + + /*! Interrupt handles */ + struct intr_handle intr_hdl[NUM_Q_PER_GRP]; + + /*! Rx queue pointers */ + void *rx_queue[NUM_Q_PER_GRP]; + + /*! Tx queue pointers */ + void *tx_queue[NUM_Q_PER_GRP]; + + /*! Virtual Rx queue pointers */ + void *vnet_rxq[NUM_Q_PER_GRP]; + + /*! Virtual Tx queue pointers */ + void *vnet_txq[NUM_Q_PER_GRP]; + + /*! Bitmap for Rx queues at work */ + uint32_t bm_rxq; + + /*! Bitmap for Tx queues at work */ + uint32_t bm_txq; + + /*! Number of Rx queues at work */ + uint32_t nb_rxq; + + /*! Number of Tx queues at work */ + uint32_t nb_txq; + + /*! Number of descriptors */ + uint32_t nb_desc[NUM_Q_PER_GRP]; + + /*! Rx buffer size */ + uint32_t rx_size[NUM_Q_PER_GRP]; + + /*! Queue mode */ + uint32_t que_ctrl[NUM_Q_PER_GRP]; + /*! Packet_byte_swap */ +#define PDMA_PKT_BYTE_SWAP (1 << 0) + /*! Non packet_byte_swap */ +#define PDMA_OTH_BYTE_SWAP (1 << 1) + /*! Header_byte_swap */ +#define PDMA_HDR_BYTE_SWAP (1 << 2) + + /*! Pipe interfaces */ + int pipe[NUM_Q_PER_GRP]; + + /*! Group ID */ + int id; + + /*! Queues need to poll */ + uint32_t poll_queues; + + /*! Active IRQs for DMA control */ + uint32_t irq_mask; + + /*! Indicating the group is attached */ + bool attached; +}; + +/*! + * \brief Device control structure. + */ +struct dev_ctrl { + /*! Pointer to the device structure */ + struct pdma_dev *dev; + + /*! Pointer to hardware-specific data */ + void *hw; + + /*! HW base address */ + volatile void *hw_addr; + + /*! Queue groups */ + struct queue_group grp[NUM_GRP_MAX]; + + /*! Pointers to Rx queues */ + void *rx_queue[NUM_Q_MAX]; + + /*! Pointers to Tx queues */ + void *tx_queue[NUM_Q_MAX]; + + /*! Pointers to virtual Rx queues */ + void *vnet_rxq[NUM_Q_MAX]; + + /*! Pointers to virtual Tx queues */ + void *vnet_txq[NUM_Q_MAX]; + + /*! Pointer to buffer manager */ + void *buf_mngr; + + /*! VNET sync data */ + vnet_sync_t vsync; + + /*! Bitmap of groups at work */ + uint32_t bm_grp; + + /*! Bitmap of Rx queues at work */ + uint32_t bm_rxq; + + /*! Bitmap of Tx queues at work */ + uint32_t bm_txq; + + /*! Number of groups at work */ + uint32_t nb_grp; + + /*! Number of Rx queues at work */ + uint32_t nb_rxq; + + /*! Number of Tx queues at work */ + uint32_t nb_txq; + + /*! Number of descriptors for a queue */ + uint32_t nb_desc; + + /*! Budget for once queue processing */ + uint32_t budget; + + /*! Common Rx buffer size for all queues */ + uint32_t rx_buf_size; + + /*! Rx descriptor size */ + uint32_t rx_desc_size; + + /*! Tx descriptor size */ + uint32_t tx_desc_size; +}; + +/*! + * Configure device. + * + * \param [in] dev Pointer to device structure. + * \param [in] bm_rxq Rx queue bitmap. + * \param [in] bm_txq Tx queue bitmap. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_dev_config_f)(struct pdma_dev *dev, uint32_t bm_rxq, uint32_t bm_txq); + +/*! + * Start device. + * + * \param [in] dev Pointer to device structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_dev_start_f)(struct pdma_dev *dev); + +/*! + * Stop device. + * + * \param [in] dev Pointer to device structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_dev_stop_f)(struct pdma_dev *dev); + +/*! + * Close device. + * + * \param [in] dev Pointer to device structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_dev_close_f)(struct pdma_dev *dev); + +/*! + * Suspend device. + * + * \param [in] dev Pointer to device structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_dev_suspend_f)(struct pdma_dev *dev); + +/*! + * Resume device. + * + * \param [in] dev Pointer to device structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_dev_resume_f)(struct pdma_dev *dev); + +/*! + * Get device information. + * + * \param [in] dev Pointer to device structure. + */ +typedef void (*pdma_dev_info_get_f)(struct pdma_dev *dev); + +/*! + * Get device statistics. + * + * \param [in] dev Pointer to device structure. + */ +typedef void (*pdma_dev_stats_get_f)(struct pdma_dev *dev); + +/*! + * Reset device statistics. + * + * \param [in] dev Pointer to device structure. + */ +typedef void (*pdma_dev_stats_reset_f)(struct pdma_dev *dev); + +/*! + * Convert logic queue to physical queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Logic queue number. + * \param [in] dir Transmit direction. + * \param [in] chan Channel number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_dev_lq2pq_f)(struct pdma_dev *dev, int queue, int dir, int *chan); + +/*! + * Convert physical queue to logic queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] chan Channel number. + * \param [in] queue Logic queue number. + * \param [in] dir Transmit direction. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_dev_pq2lq_f)(struct pdma_dev *dev, int chan, int *queue, int *dir); + +/*! + * Start queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_queue_start_f)(struct pdma_dev *dev, int queue); + +/*! + * Stop queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_queue_stop_f)(struct pdma_dev *dev, int queue); + +/*! + * Set up queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_queue_setup_f)(struct pdma_dev *dev, int queue); + +/*! + * Release queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_queue_release_f)(struct pdma_dev *dev, int queue); + +/*! + * Restore queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_queue_restore_f)(struct pdma_dev *dev, int queue); + +/*! + * Enable queue interrupt. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_intr_enable_f)(struct pdma_dev *dev, int queue); + +/*! + * Disable queue interrupt. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_intr_disable_f)(struct pdma_dev *dev, int queue); + +/*! + * Acknowledge queue interrupt. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_intr_ack_f)(struct pdma_dev *dev, int queue); + +/*! + * Query queue interrupt. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_intr_query_f)(struct pdma_dev *dev, int queue); + +/*! + * Check queue interrupt. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_intr_check_f)(struct pdma_dev *dev, int queue); + +/*! + * Suspend Rx queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_rx_queue_suspend_f)(struct pdma_dev *dev, int queue); + +/*! + * Resume Rx queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_rx_queue_resume_f)(struct pdma_dev *dev, int queue); + +/*! + * Wake up Tx queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_tx_queue_wakeup_f)(struct pdma_dev *dev, int queue); + +/*! + * Poll Rx queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * \param [in] budget Max number of descriptor to poll. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_rx_queue_poll_f)(struct pdma_dev *dev, int queue, int budget); + +/*! + * Poll Tx queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * \param [in] budget Max number of descriptor to poll. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_tx_queue_poll_f)(struct pdma_dev *dev, int queue, int budget); + +/*! + * Poll queue group. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Queue number. + * \param [in] budget Max number of descriptor to poll. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pdma_group_poll_f)(struct pdma_dev *dev, int group, int budget); + +/*! + * \brief Exported functions structure. + */ +struct dev_ops { + /*! Configure device */ + pdma_dev_config_f dev_config; + + /*! Start device */ + pdma_dev_start_f dev_start; + + /*! Stop device */ + pdma_dev_stop_f dev_stop; + + /*! Close device */ + pdma_dev_close_f dev_close; + + /*! Suspend device */ + pdma_dev_suspend_f dev_suspend; + + /*! Resume device */ + pdma_dev_resume_f dev_resume; + + /*! Get device information */ + pdma_dev_info_get_f dev_info_get; + + /*! Get device statistics */ + pdma_dev_stats_get_f dev_stats_get; + + /*! Reset device statistics */ + pdma_dev_stats_reset_f dev_stats_reset; + + /*! Logic queue to physical queue */ + pdma_dev_lq2pq_f dev_lq_to_pq; + + /*! Physical queue to logic queue */ + pdma_dev_pq2lq_f dev_pq_to_lq; + + /*! Start Rx for a queue */ + pdma_queue_start_f rx_queue_start; + + /*! Stop Rx for a queue */ + pdma_queue_stop_f rx_queue_stop; + + /*! Start Tx for a queue */ + pdma_queue_start_f tx_queue_start; + + /*! Stop Tx for a queue */ + pdma_queue_stop_f tx_queue_stop; + + /*! Set up Rx queue */ + pdma_queue_setup_f rx_queue_setup; + + /*! Release Rx queue */ + pdma_queue_release_f rx_queue_release; + + /*! Restore stopped Rx queue */ + pdma_queue_restore_f rx_queue_restore; + + /*! Set up virtual Rx queue */ + pdma_queue_setup_f rx_vqueue_setup; + + /*! Release virtual Rx queue */ + pdma_queue_release_f rx_vqueue_release; + + /*! Set up Tx queue */ + pdma_queue_setup_f tx_queue_setup; + + /*! Release Tx queue */ + pdma_queue_release_f tx_queue_release; + + /*! Restore stopped Tx queue */ + pdma_queue_restore_f tx_queue_restore; + + /*! Set up virtual Tx queue */ + pdma_queue_setup_f tx_vqueue_setup; + + /*! Release virtual Tx queue */ + pdma_queue_release_f tx_vqueue_release; + + /*! Enable Rx queue interrupt */ + pdma_intr_enable_f rx_queue_intr_enable; + + /*! Disable Rx queue interrupt */ + pdma_intr_disable_f rx_queue_intr_disable; + + /*! Acknowledge interrupt for Rx queue */ + pdma_intr_ack_f rx_queue_intr_ack; + + /*! Query interrupt status for Rx queue */ + pdma_intr_query_f rx_queue_intr_query; + + /*! Check interrupt validity for Rx queue */ + pdma_intr_check_f rx_queue_intr_check; + + /*! Enable Tx queue interrupt */ + pdma_intr_enable_f tx_queue_intr_enable; + + /*! Disable Tx queue interrupt */ + pdma_intr_disable_f tx_queue_intr_disable; + + /*! Acknowledge interrupt for Tx queue */ + pdma_intr_ack_f tx_queue_intr_ack; + + /*! Query interrupt status for Tx queue */ + pdma_intr_query_f tx_queue_intr_query; + + /*! Check interrupt validity for Tx queue */ + pdma_intr_check_f tx_queue_intr_check; + + /*! Suspend a Rx queue */ + pdma_rx_queue_suspend_f rx_queue_suspend; + + /*! Resume a Rx queue */ + pdma_rx_queue_resume_f rx_queue_resume; + + /*! Wake up a Tx queue to transmit */ + pdma_tx_queue_wakeup_f tx_queue_wakeup; + + /*! Poll for a Rx queue */ + pdma_rx_queue_poll_f rx_queue_poll; + + /*! Poll for a Tx queue */ + pdma_tx_queue_poll_f tx_queue_poll; + + /*! Poll for a group */ + pdma_group_poll_f group_poll; +}; + +/*! + * Read 32-bit device register. + * + * \param [in] dev Pointer to device structure. + * \param [in] addr Register address. + * \param [in] data Pointer to read data. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*reg32_read_f)(struct pdma_dev *dev, uint32_t addr, uint32_t *data); + +/*! + * Write 32-bit device register. + * + * \param [in] dev Pointer to device structure. + * \param [in] addr Register address. + * \param [in] data Data to write. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*reg32_write_f)(struct pdma_dev *dev, uint32_t addr, uint32_t data); + +/*! + * Receive packet. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Rx queue number. + * \param [in] buf Pointer to packet buffer. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*pdma_rx_f)(struct pdma_dev *dev, int queue, void *buf); + +/*! + * Transmit packet. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Tx queue number. + * \param [in] buf Pointer to packet buffer. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*pdma_tx_f)(struct pdma_dev *dev, int queue, void *buf); + +/*! + * Network device detach. + * + * \param [in] dev Pointer to device structure. + */ +typedef void (*sys_ndev_detach_f)(struct pdma_dev *dev); + +/*! + * Network device attach. + * + * \param [in] dev Pointer to device structure. + */ +typedef void (*sys_ndev_attach_f)(struct pdma_dev *dev); + +/*! + * Suspend Tx queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Tx queue number. + */ +typedef void (*sys_tx_suspend_f)(struct pdma_dev *dev, int queue); + +/*! + * Resume Tx queue. + * + * \param [in] dev Pointer to device structure. + * \param [in] queue Tx queue number. + */ +typedef void (*sys_tx_resume_f)(struct pdma_dev *dev, int queue); + +/*! + * Enable interrupts. + * + * \param [in] dev Pointer to device structure. + * \param [in] group Channel group number. + * \param [in] chan Channel number. + * \param [in] reg Interrupt enable register. + * \param [in] val Interrupt enable register value. + */ +typedef void (*sys_intr_unmask_f)(struct pdma_dev *dev, int group, int chan, + uint32_t reg, uint32_t val); + +/*! + * Disable interrupts. + * + * \param [in] dev Pointer to device structure. + * \param [in] group Channel group number. + * \param [in] chan Channel number. + * \param [in] reg Interrupt disable register. + * \param [in] val Interrupt disable register value. + */ +typedef void (*sys_intr_mask_f)(struct pdma_dev *dev, int group, int chan, + uint32_t reg, uint32_t val); + +/*! + * Wait for notification from the other side. + * + * \param [in] dev Pointer to device structure. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*xnet_wait_f)(struct pdma_dev *dev); + +/*! + * Wake up the other side. + * + * \param [in] dev Pointer to device structure. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*xnet_wake_f)(struct pdma_dev *dev); + +/*! + * Convert physical address to virtual address. + * + * \param [in] dev Pointer to device structure. + * \param [in] paddr Physical address. + * + * \retval Virtual address. + */ +typedef void *(*sys_p2v_f)(struct pdma_dev *dev, uint64_t paddr); + +/*! + * Convert virtual address to physical address. + * + * \param [in] dev Pointer to device structure. + * \param [in] vaddr Virtual address. + * + * \retval Physical address. + */ +typedef uint64_t (*sys_v2p_f)(struct pdma_dev *dev, void *vaddr); + +/*! + * \brief Device structure. + */ +struct pdma_dev { + /*! Device name */ + char name[DEV_NAME_LEN_MAX]; + + /*! Device ID */ + uint32_t dev_id; + + /*! Device type */ + uint32_t dev_type; + + /*! Device Number */ + int unit; + + /*! Device control structure */ + struct dev_ctrl ctrl; + + /*! Pointer to the exported funtions structure */ + struct dev_ops *ops; + + /*! Device information */ + struct bcmcnet_dev_info info; + + /*! Device statistics data */ + struct bcmcnet_dev_stats stats; + + /*! Private data */ + void *priv; + + /*! Read 32-bit device register */ + reg32_read_f dev_read32; + + /*! Write 32-bit device register */ + reg32_write_f dev_write32; + + /*! Packet reception */ + pdma_rx_f pkt_recv; + + /*! Packet transmission */ + pdma_tx_f pkt_xmit; + + /*! Network device detach */ + sys_ndev_detach_f ndev_detach; + + /*! Network device attach */ + sys_ndev_attach_f ndev_attach; + + /*! Tx suspend */ + sys_tx_suspend_f tx_suspend; + + /*! Tx resume */ + sys_tx_resume_f tx_resume; + + /*! Enable a set of interrupts */ + sys_intr_unmask_f intr_unmask; + + /*! Disable a set of interrupts */ + sys_intr_mask_f intr_mask; + + /*! Virtual network wait for */ + xnet_wait_f xnet_wait; + + /*! Virtual network wake up */ + xnet_wake_f xnet_wake; + + /*! Physical address to virtual address */ + sys_p2v_f sys_p2v; + + /*! Virtual address to physical address */ + sys_v2p_f sys_v2p; + + /*! Maximum number of groups */ + int num_groups; + + /*! Maximum number of group queues */ + int grp_queues; + + /*! Maximum number of queues */ + int num_queues; + + /*! Rx packet header size */ + uint32_t rx_ph_size; + + /*! Tx packet header size */ + uint32_t tx_ph_size; + + /*! Flags */ + uint32_t flags; + /*! Interrupt processing per group */ +#define PDMA_GROUP_INTR (1 << 0) + /*! Tx polling mode */ +#define PDMA_TX_POLLING (1 << 1) + /*! Rx batch refilling */ +#define PDMA_RX_BATCHING (1 << 2) + /*! DMA chain mode */ +#define PDMA_CHAIN_MODE (1 << 3) + /*! Descriptor prefetch mode */ +#define PDMA_DESC_PREFETCH (1 << 4) + /*! VNET is docked */ +#define PDMA_VNET_DOCKED (1 << 5) + /*! Abort PDMA mode for suspend and resume */ +#define PDMA_ABORT (1 << 6) + /*! No FCS for Rx/Tx packets */ +#define PDMA_NO_FCS (1 << 7) + + /*! Extra poll time in microseconds */ + int extra_poll_time; + + /*! Device mode */ + dev_mode_t mode; + + /*! Device is started */ + bool started; + + /*! Device is started but suspended */ + bool suspended; + + /*! Device is initialized and HMI driver is attached */ + bool attached; +}; + +/*! + * \brief Initialize device. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_init(struct pdma_dev *dev); + +/*! + * \brief Clean up device. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_cleanup(struct pdma_dev *dev); + +/*! + * \brief Start device. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_start(struct pdma_dev *dev); + +/*! + * \brief Stop device. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_stop(struct pdma_dev *dev); + +/*! + * \brief Suspend device. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_suspend(struct pdma_dev *dev); + +/*! + * \brief Resume device. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_resume(struct pdma_dev *dev); + +/*! + * \brief Suspend device Rx. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_rx_suspend(struct pdma_dev *dev); + +/*! + * \brief Resume device Rx. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_rx_resume(struct pdma_dev *dev); + +/*! + * \brief Dock device. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_dock(struct pdma_dev *dev); + +/*! + * \brief Undock device. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_undock(struct pdma_dev *dev); + +/*! + * \brief Get device information. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_info_get(struct pdma_dev *dev); + +/*! + * \brief Get device statistics. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_stats_get(struct pdma_dev *dev); + +/*! + * \brief Reset device statistics. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_stats_reset(struct pdma_dev *dev); + +/*! + * \brief Change queue number to channel number. + * + * \param [in] dev Device structure point. + * \param [in] queue Queue number. + * \param [in] dir Transmit direction. + * \param [out] chan Channel number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_queue_to_chan(struct pdma_dev *dev, int queue, int dir, int *chan); + +/*! + * \brief Change channel number to queue number. + * + * \param [in] dev Device structure point. + * \param [in] chan Channel number. + * \param [out] queue Queue number. + * \param [out] dir Transmit direction. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_dev_chan_to_queue(struct pdma_dev *dev, int chan, int *queue, int *dir); + +/*! + * \brief Enable Rx queue interrupt. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_rx_queue_intr_enable(struct pdma_dev *dev, int queue); + +/*! + * \brief Disable Rx queue interrupt. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_rx_queue_intr_disable(struct pdma_dev *dev, int queue); + +/*! + * \brief Acknowledge Rx queue interrupt. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_rx_queue_intr_ack(struct pdma_dev *dev, int queue); + +/*! + * \brief Check Rx queue interrupt. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_rx_queue_intr_check(struct pdma_dev *dev, int queue); + +/*! + * \brief Enable Tx queue interrupt. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_tx_queue_intr_enable(struct pdma_dev *dev, int queue); + +/*! + * \brief Disable Tx queue interrupt. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_tx_queue_intr_disable(struct pdma_dev *dev, int queue); + +/*! + * \brief Acknowledge Tx queue interrupt. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_tx_queue_intr_ack(struct pdma_dev *dev, int queue); + +/*! + * \brief Check Tx queue interrupt. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_tx_queue_intr_check(struct pdma_dev *dev, int queue); + +/*! + * \brief Enable queue interrupt. + * + * \param [in] dev Device structure point. + * \param [in] hdl Queue interrupt handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_queue_intr_enable(struct pdma_dev *dev, struct intr_handle *hdl); + +/*! + * \brief Disable queue interrupt. + * + * \param [in] dev Device structure point. + * \param [in] hdl Queue interrupt handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_queue_intr_disable(struct pdma_dev *dev, struct intr_handle *hdl); + +/*! + * \brief Acknowledge queue interrupt. + * + * \param [in] dev Device structure point. + * \param [in] hdl Queue interrupt handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_queue_intr_ack(struct pdma_dev *dev, struct intr_handle *hdl); + +/*! + * \brief Check queue interrupt. + * + * \param [in] dev Device structure point. + * \param [in] hdl Queue interrupt handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_queue_intr_check(struct pdma_dev *dev, struct intr_handle *hdl); + +/*! + * \brief Enable group interrupt. + * + * \param [in] dev Device structure point. + * \param [in] group Group number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_group_intr_enable(struct pdma_dev *dev, int group); + +/*! + * \brief Disable group interrupt. + * + * \param [in] dev Device structure point. + * \param [in] group Group number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_group_intr_disable(struct pdma_dev *dev, int group); + +/*! + * \brief Acknowledge group interrupt. + * + * \param [in] dev Device structure point. + * \param [in] group Group number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_group_intr_ack(struct pdma_dev *dev, int group); + +/*! + * \brief Check group interrupt. + * + * \param [in] dev Device structure point. + * \param [in] group Group number. + * + * \retval true Interrupt is active. + * \retval false Interrupt is not active. + */ +extern bool +bcmcnet_group_intr_check(struct pdma_dev *dev, int group); + +/*! + * \brief Poll Rx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * \param [in] budget Poll budget. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_rx_queue_poll(struct pdma_dev *dev, int queue, int budget); + +/*! + * \brief Poll Tx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * \param [in] budget Poll budget. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_tx_queue_poll(struct pdma_dev *dev, int queue, int budget); + +/*! + * \brief Poll queue. + * + * \param [in] dev Device structure point. + * \param [in] hdl Queue interrupt handle. + * \param [in] budget Poll budget. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_queue_poll(struct pdma_dev *dev, struct intr_handle *hdl, int budget); + +/*! + * \brief Poll group. + * + * \param [in] dev Device structure point. + * \param [in] group Group number. + * \param [in] budget Poll budget. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_group_poll(struct pdma_dev *dev, int group, int budget); + +#endif /* BCMCNET_CORE_H */ + diff --git a/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_dev.h b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_dev.h new file mode 100644 index 0000000..817e873 --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_dev.h @@ -0,0 +1,570 @@ +/*! \file bcmcnet_dev.h + * + * Generic data structure and macro definitions for BCMCNET device. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMCNET_DEV_H +#define BCMCNET_DEV_H + +#include + +/*! + * \brief HW information. + */ +struct hw_info { + /*! HW name */ + char *name; + + /*! HW version */ + int ver_no; + + /*! Device ID */ + uint32_t dev_id; + + /*! Revision ID */ + uint32_t rev_id; + + /*! Number of CMCs */ + uint32_t num_cmcs; + + /*! Number of CMC channels */ + uint32_t cmc_chans; + + /*! Number of channels */ + uint32_t num_chans; + + /*! Rx DCB size */ + uint32_t rx_dcb_size; + + /*! Tx DCB size */ + uint32_t tx_dcb_size; + + /*! Rx packet header size */ + uint32_t rx_ph_size; + + /*! Tx packet header size */ + uint32_t tx_ph_size; + + /*! HW structure point */ + struct pdma_hw *hw; +}; + +/*! + * \brief Read 32-bit register. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] addr Register address. + * \param [in] data Pointer to read data. + */ +typedef void (*reg_rd32_f)(struct pdma_hw *hw, uint32_t addr, uint32_t *data); + +/*! + * \brief Write 32-bit register. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] addr Register address. + * \param [in] data Data to write. + */ +typedef void (*reg_wr32_f)(struct pdma_hw *hw, uint32_t addr, uint32_t data); + +/*! + * \brief Pre-initialize hardware. + * + * \param [in] hw Pointer to hardware structure. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*pre_init_f)(struct pdma_hw *hw); + +/*! + * \brief Initialize hardware. + * + * \param [in] hw Pointer to hardware structure. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*hw_init_f)(struct pdma_hw *hw); + +/*! + * \brief Configure hardware. + * + * \param [in] hw Pointer to hardware structure. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*hw_config_f)(struct pdma_hw *hw); + +/*! + * \brief Reset hardware. + * + * \param [in] hw Pointer to hardware structure. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*hw_reset_f)(struct pdma_hw *hw); + +/*! + * \brief Start channel. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] chan Channel number. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*chan_start_f)(struct pdma_hw *hw, int chan); + +/*! + * \brief Stop channel. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] chan Channel number. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*chan_stop_f)(struct pdma_hw *hw, int chan); + +/*! + * \brief Set up channel. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] chan Channel number. + * \param [in] addr Start DMA address of descriptors. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*chan_setup_f)(struct pdma_hw *hw, int chan, uint64_t addr); + +/*! + * \brief Go to ohter descriptor. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] chan Channel number. + * \param [in] addr Destination DMA address of descriptors. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*chan_goto_f)(struct pdma_hw *hw, int chan, uint64_t addr); + +/*! + * \brief Clear channel. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] chan Channel number. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*chan_clear_f)(struct pdma_hw *hw, int chan); + +/*! + * \brief Check channel. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] chan Channel number. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*chan_check_f)(struct pdma_hw *hw, int chan); + +/*! + * \brief Get interrupt number. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] chan Channel number. + * + * \retval Returned interrupt number, errors if negative value. + */ +typedef int (*chan_intr_num_get_f)(struct pdma_hw *hw, int chan); + +/*! + * \brief Enable interrupt. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] chan Channel number. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*chan_intr_enable_f)(struct pdma_hw *hw, int chan); + +/*! + * \brief Disable interrupt. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] chan Channel number. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*chan_intr_disable_f)(struct pdma_hw *hw, int chan); + +/*! + * \brief Query interrupt. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] chan Channel number. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*chan_intr_query_f)(struct pdma_hw *hw, int chan); + +/*! + * \brief Check interrupt. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] chan Channel number. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*chan_intr_check_f)(struct pdma_hw *hw, int chan); + +/*! + * \brief Coalesce interrupt. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] chan Channel number. + * \param [in] count Count value to trigger interrupt. + * \param [in] timer Timer value to triggre interrupt. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*chan_intr_coalesce_f)(struct pdma_hw *hw, int chan, int count, int timer); + +/*! + * \brief Dump registers. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] chan Channel number. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*chan_reg_dump_f)(struct pdma_hw *hw, int chan); + +/*! + * \brief HW handlers. + */ +struct hw_handlers { + /*! 32 bits register read */ + reg_rd32_f reg_rd32; + + /*! 32 bits register write */ + reg_wr32_f reg_wr32; + + /*! HW pre-initialize */ + pre_init_f pre_init; + + /*! HW initialize */ + hw_init_f hw_init; + + /*! HW configure */ + hw_config_f hw_config; + + /*! HW reset */ + hw_reset_f hw_reset; + + /*! Channel start */ + chan_start_f chan_start; + + /*! Channel stop */ + chan_stop_f chan_stop; + + /*! Channel setup */ + chan_setup_f chan_setup; + + /*! Channel goto */ + chan_goto_f chan_goto; + + /*! Channel clear */ + chan_clear_f chan_clear; + + /*! Channel check */ + chan_check_f chan_check; + + /*! Channel interrupt number get */ + chan_intr_num_get_f chan_intr_num_get; + + /*! Channel interrupt enable */ + chan_intr_enable_f chan_intr_enable; + + /*! Channel interrupt disable */ + chan_intr_disable_f chan_intr_disable; + + /*! Channel interrupt query */ + chan_intr_query_f chan_intr_query; + + /*! Channel interrupt check */ + chan_intr_check_f chan_intr_check; + + /*! Channel interrupt coalesce */ + chan_intr_coalesce_f chan_intr_coalesce; + + /*! Channel registers dump */ + chan_reg_dump_f chan_reg_dump; +}; + +/*! + * \brief Initialize Rx descriptor. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] rxq Pointer to Rx queue struture. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_MEMORY Allocation failed. + */ +typedef int (*rx_desc_init_f)(struct pdma_hw *hw, struct pdma_rx_queue *rxq); + +/*! + * \brief Clean up Rx descriptor. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] rxq Pointer to Rx queue struture. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*rx_desc_clean_f)(struct pdma_hw *hw, struct pdma_rx_queue *rxq); + +/*! + * \brief Clean up Rx ring. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] rxq Pointer to Rx queue struture. + * \param [in] budget Budget for each operation. + * + * \retval Number of descriptors finished. + */ +typedef int (*rx_ring_clean_f)(struct pdma_hw *hw, struct pdma_rx_queue *rxq, int budget); + +/*! + * \brief Dump Rx ring. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] rxq Pointer to Rx queue struture. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*rx_ring_dump_f)(struct pdma_hw *hw, struct pdma_rx_queue *rxq); + +/*! + * \brief Suspend Rx queue. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] rxq Pointer to Rx queue struture. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*rx_suspend_f)(struct pdma_hw *hw, struct pdma_rx_queue *rxq); + +/*! + * \brief Resume Rx queue. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] rxq Pointer to Rx queue struture. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*rx_resume_f)(struct pdma_hw *hw, struct pdma_rx_queue *rxq); + +/*! + * \brief Initialize Tx descriptor. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] txq Pointer to Tx queue struture. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_MEMORY Allocation failed. + */ +typedef int (*tx_desc_init_f)(struct pdma_hw *hw, struct pdma_tx_queue *txq); + +/*! + * \brief Clean up Tx descriptor. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] txq Pointer to Tx queue struture. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*tx_desc_clean_f)(struct pdma_hw *hw, struct pdma_tx_queue *txq); + +/*! + * \brief Clean up Tx ring. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] txq Pointer to Tx queue struture. + * \param [in] budget Budget for each operation. + * + * \retval Number of descriptors finished. + */ +typedef int (*tx_ring_clean_f)(struct pdma_hw *hw, struct pdma_tx_queue *txq, int budget); + +/*! + * \brief Dump Tx ring. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] txq Pointer to Tx queue struture. + * + * \retval SHR_E_NONE No errors. + */ +typedef int (*tx_ring_dump_f)(struct pdma_hw *hw, struct pdma_tx_queue *txq); + +/*! + * \brief Transmit packet. + * + * \param [in] hw Pointer to hardware structure. + * \param [in] txq Pointer to Tx queue struture. + * \param [in] buf Pointer to packet buffer struture. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +typedef int (*pkt_xmit_f)(struct pdma_hw *hw, struct pdma_tx_queue *txq, void *buf); + +/*! + * \brief Descriptor operations. + */ +struct desc_operations { + /*! Rx descriptor initialize */ + rx_desc_init_f rx_desc_init; + + /*! Rx descriptor cleanup */ + rx_desc_clean_f rx_desc_clean; + + /*! Rx ring cleanup */ + rx_ring_clean_f rx_ring_clean; + + /*! Rx ring dump */ + rx_ring_dump_f rx_ring_dump; + + /*! Rx suspend */ + rx_suspend_f rx_suspend; + + /*! Rx resume */ + rx_resume_f rx_resume; + + /*! Tx descriptor initialize */ + tx_desc_init_f tx_desc_init; + + /*! Tx descriptor cleanup */ + tx_desc_clean_f tx_desc_clean; + + /*! Tx ring cleanup */ + tx_ring_clean_f tx_ring_clean; + + /*! Tx ring dump */ + tx_ring_dump_f tx_ring_dump; + + /*! Tx transmit */ + pkt_xmit_f pkt_xmit; +}; + +/*! + * \brief HW structure. + */ +struct pdma_hw { + /*! Device number */ + int unit; + + /*! Device structure point */ + struct pdma_dev *dev; + + /*! HW information */ + struct hw_info info; + + /*! HW handlers */ + struct hw_handlers hdls; + + /*! HW operations */ + struct desc_operations dops; +}; + +/*! + * \brief Open device. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_open(struct pdma_dev *dev); + +/*! + * \brief Coalesce Rx interrupt. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * \param [in] count Interrupt threshhold. + * \param [in] timer Timer value. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_rx_queue_int_coalesce(struct pdma_dev *dev, int queue, int count, int timer); + +/*! + * \brief Coalesce Tx interrupt. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * \param [in] count Interrupt threshhold. + * \param [in] timer Timer value. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_tx_queue_int_coalesce(struct pdma_dev *dev, int queue, int count, int timer); + +/*! + * \brief Dump Rx queue registers. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_rx_queue_reg_dump(struct pdma_dev *dev, int queue); + +/*! + * \brief Dump Tx queue registers. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_tx_queue_reg_dump(struct pdma_dev *dev, int queue); + +#endif /* BCMCNET_DEV_H */ + diff --git a/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_internal.h b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_internal.h new file mode 100644 index 0000000..3d6f18e --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_internal.h @@ -0,0 +1,322 @@ +/*! \file bcmcnet_internal.h + * + * BCMCNET internal data structure and macro definitions. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMCNET_INTERNAL_H +#define BCMCNET_INTERNAL_H + +#include + +/*! CMICD name */ +#define CMICD_DEV_NAME "cmicd" + +/*! CMICX name */ +#define CMICX_DEV_NAME "cmicx" + +/*! CMICR name */ +#define CMICR_DEV_NAME "cmicr" + +/*! + * \brief Allocate descriptor ring buffer. + * + * \param [in] dev Pointer to Packet DMA device. + * \param [in] dma DMA address of ring buffer. + * + * \retval Pointer to DMA buffer or NULL if an error occurred. + */ +typedef void *(*ring_buf_alloc_f)(struct pdma_dev *dev, uint32_t, dma_addr_t *dma); + +/*! + * \brief Free descriptor ring buffer. + * + * \param [in] dev Pointer to Packet DMA device. + * \param [in] size Size of DMA buffer. + * \param [in] mem Pointer to DMA buffer. + * \param [in] dma DMA address of ring buffer. + */ +typedef void (*ring_buf_free_f)(struct pdma_dev *dev, uint32_t size, void *mem, + dma_addr_t dma); + +/*! + * \brief Allocate Rx packet buffer. + * + * \param [in] dev Pointer to Packet DMA device. + * \param [in] rxq Pointer to Rx queue struture. + * \param [in] pbuf Pointer to packet buffer structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_MEMORY Allocation failed. + */ +typedef int (*rx_buf_alloc_f)(struct pdma_dev *dev, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf); + +/*! + * \brief Get Rx packet buffer DMA address. + * + * \param [in] dev Pointer to Packet DMA device. + * \param [in] rxq Pointer to Rx queue struture. + * \param [in] pbuf Pointer to packet buffer structure. + * \param [in] dma DMA address of packet buffer. + */ +typedef void (*rx_buf_dma_f)(struct pdma_dev *dev, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf, dma_addr_t *dma); + +/*! + * \brief Check Rx packet buffer validity. + * + * \param [in] dev Pointer to Packet DMA device. + * \param [in] rxq Pointer to Rx queue struture. + * \param [in] pbuf Pointer to packet buffer structure. + * + * \retval true Buffer is available. + * \retval false Buffer is not available. + */ +typedef bool (*rx_buf_avail_f)(struct pdma_dev *dev, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf); + +/*! + * \brief Get Rx packet buffer. + * + * \param [in] dev Pointer to Packet DMA device. + * \param [in] rxq Pointer to Rx queue struture. + * \param [in] pbuf Pointer to packet buffer structure. + * \param [in] len Packet length. + * + * \retval Pointer to packet header structure or NULL if failed. + */ +typedef struct pkt_hdr *(*rx_buf_get_f)(struct pdma_dev *dev, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf, int len); + +/*! + * \brief Put Rx packet buffer. + * + * \param [in] dev Pointer to Packet DMA device. + * \param [in] rxq Pointer to Rx queue struture. + * \param [in] pbuf Pointer to packet buffer structure. + * \param [in] len Packet length. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_MEMORY Allocation failed. + */ +typedef int (*rx_buf_put_f)(struct pdma_dev *dev, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf, int len); + +/*! + * \brief Free Rx packet buffer. + * + * \param [in] dev Pointer to Packet DMA device. + * \param [in] rxq Pointer to Rx queue struture. + * \param [in] pbuf Pointer to packet buffer structure. + */ +typedef void (*rx_buf_free_f)(struct pdma_dev *dev, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf); + +/*! + * \brief Get Rx packet buffer mode. + * + * \param [in] dev Pointer to Packet DMA device. + * \param [in] rxq Pointer to Rx queue struture. + * + * \retval Buffer mode. + */ +typedef enum buf_mode (*rx_buf_mode_f)(struct pdma_dev *dev, struct pdma_rx_queue *rxq); + +/*! + * \brief Get Tx packet buffer. + * + * \param [in] dev Pointer to Packet DMA device. + * \param [in] txq Pointer to Rx queue struture. + * \param [in] pbuf Pointer to packet buffer structure. + * \param [in] buf Packet buffer. + * + * \retval Pointer to packet header structure or NULL if failed. + */ +typedef struct pkt_hdr *(*tx_buf_get_f)(struct pdma_dev *dev, struct pdma_tx_queue *txq, + struct pdma_tx_buf *pbuf, void *buf); + +/*! + * \brief Get Tx packet buffer DMA address. + * + * \param [in] dev Pointer to Packet DMA device. + * \param [in] txq Pointer to Rx queue struture. + * \param [in] pbuf Pointer to packet buffer structure. + * \param [in] dma DMA address of packet buffer. + */ +typedef void (*tx_buf_dma_f)(struct pdma_dev *dev, struct pdma_tx_queue *txq, + struct pdma_tx_buf *pbuf, dma_addr_t *dma); + +/*! + * \brief Free Tx packet buffer. + * + * \param [in] dev Pointer to Packet DMA device. + * \param [in] txq Pointer to Rx queue struture. + * \param [in] pbuf Pointer to packet buffer structure. + */ +typedef void (*tx_buf_free_f)(struct pdma_dev *dev, struct pdma_tx_queue *txq, + struct pdma_tx_buf *pbuf); + +/*! + * \brief Buffer manager. + */ +struct pdma_buf_mngr { + /*! Allocate descriptor ring buffer */ + ring_buf_alloc_f ring_buf_alloc; + + /*! Free descriptor ring buffer */ + ring_buf_free_f ring_buf_free; + + /*! Allocate Rx packet buffer */ + rx_buf_alloc_f rx_buf_alloc; + + /*! Get Rx packet buffer DMA address */ + rx_buf_dma_f rx_buf_dma; + + /*! Check Rx packet buffer validity */ + rx_buf_avail_f rx_buf_avail; + + /*! Get Rx packet buffer */ + rx_buf_get_f rx_buf_get; + + /*! Put Rx packet buffer */ + rx_buf_put_f rx_buf_put; + + /*! Free Rx packet buffer */ + rx_buf_free_f rx_buf_free; + + /*! Get Rx packet buffer mode */ + rx_buf_mode_f rx_buf_mode; + + /*! Get Tx packet buffer */ + tx_buf_get_f tx_buf_get; + + /*! Get Tx packet buffer DMA address */ + tx_buf_dma_f tx_buf_dma; + + /*! Free Tx packet buffer */ + tx_buf_free_f tx_buf_free; +}; + +/*! + * \brief Wait for the kernel networking subsystem. + * + * \param [in] unit Device number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_FAIL Operation failed. + */ +typedef int (*bcmcnet_vnet_wait_f)(int unit); + +/*! + * \brief Wake up the kernel networking subsystem. + * + * \param [in] unit Device number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_FAIL Operation failed. + */ +typedef int (*bcmcnet_hnet_wake_f)(int unit); + +/*! + * \brief Dock to the kernel networking subsystem. + * + * \param [in] unit Device number. + * \param [in] vsync Sync data. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_FAIL Operation failed. + */ +typedef int (*bcmcnet_vnet_dock_f)(int unit, vnet_sync_t *vsync); + +/*! + * \brief Undock from the kernel networking subsystem. + * + * \param [in] unit Device number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_FAIL Operation failed. + */ +typedef int (*bcmcnet_vnet_undock_f)(int unit); + +/*! + * \brief VNET operations. + */ +typedef struct bcmcnet_vnet_ops_s { + /*! + * VNET wait for HNET. + * VNET calls this to wait for any notification from HNET. + */ + bcmcnet_vnet_wait_f vnet_wait; + + /*! + * VNET wake up HNET. + * VNET calls this to notify HNET that Tx/Rx is ready. + */ + bcmcnet_hnet_wake_f hnet_wake; + + /*! + * VNET dock to HNET. + * This is called to notify HNET that VNET is ready to work and synchronize + * vrings information to HNET. + */ + bcmcnet_vnet_dock_f vnet_dock; + + /*! + * VNET undock from HNET. + * This is called to notify HNET that VNET is ready to leave. + */ + bcmcnet_vnet_undock_f vnet_undock; +} bcmcnet_vnet_ops_t; + +/*! + * \brief Initialize buffer manager. + * + * \param [in] dev Device structure pointer. + */ +extern void +bcmcnet_buf_mngr_init(struct pdma_dev *dev); + +/*! + * \brief Register VNET operations. + * + * \param [in] unit Device number. + * \param [in] vnet_ops VNET operations. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM Invalid parameters. + */ +extern int +bcmcnet_vnet_ops_register(int unit, bcmcnet_vnet_ops_t *vnet_ops); + +#endif /* BCMCNET_INTERNAL_H */ + diff --git a/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_rxtx.h b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_rxtx.h new file mode 100644 index 0000000..e6f38ff --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_rxtx.h @@ -0,0 +1,539 @@ +/*! \file bcmcnet_rxtx.h + * + * Generic data structure and macro definitions for BCMCNET Rx/Tx. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMCNET_RXTX_H +#define BCMCNET_RXTX_H + +/*! Default timeout value (us) to wait for Tx resource. */ +#ifndef BCMCNET_TX_RSRC_WAIT_USEC +#define BCMCNET_TX_RSRC_WAIT_USEC 1000000 +#endif + +/*! Default descriptor number in each ring. */ +#define NUM_RING_DESC 64 + +/*! Maximum number of packets to be handled in one poll call. */ +#define NUM_RXTX_BUDGET 64 + +/*! + * \brief Rx buffer mode definitions. + */ +enum buf_mode { + /*! Private DMA buffer in user space */ + PDMA_BUF_MODE_PRIV, + + /*! SKB in kernel */ + PDMA_BUF_MODE_SKB, + + /*! Paged buffer in kernel */ + PDMA_BUF_MODE_PAGE, + + /*! Kernel buffer mapped to user space */ + PDMA_BUF_MODE_MAPPED, + + /*! MAX mode */ + PDMA_BUF_MODE_MAX +}; + +/*! + * \brief Rx queue statistics. + */ +struct rx_stats { + /*! Number of received packets */ + uint64_t packets; + + /*! Number of received bytes */ + uint64_t bytes; + + /*! Number of dropped packets */ + uint64_t dropped; + + /*! Number of errors */ + uint64_t errors; + + /*! Number of head errors */ + uint64_t head_errors; + + /*! Number of data errors */ + uint64_t data_errors; + + /*! Number of cell errors */ + uint64_t cell_errors; + + /*! Number of failed allocation */ + uint64_t nomems; +}; + +/*! + * Rx queue structure + */ +struct pdma_rx_queue { + /*! Group index to which this queue belongs */ + uint32_t group_id; + + /*! Global channel index */ + uint32_t chan_id; + + /*! Queue index */ + uint32_t queue_id; + + /*! Pointer to the device control structure */ + struct dev_ctrl *ctrl; + + /*! Rx packet buffer pointers */ + struct pdma_rx_buf *pbuf; + + /*! Rx ring address */ + void *ring; + + /*! Rx ring DMA address */ + dma_addr_t ring_addr; + + /*! Rx ring DMA halt address */ + dma_addr_t halt_addr; + + /*! Rx buffer size */ + uint32_t buf_size; + + /*! Total number of descriptors */ + uint32_t nb_desc; + + /*! Next free ring entry */ + uint32_t curr; + + /*! Halt ring entry */ + uint32_t halt; + + /*! Max free descriptors to hold */ + uint32_t free_thresh; + + /*! Rx interrupt coalesce value */ + uint32_t ic_val; + + /*! Rx interrupt coalescing */ + int intr_coalescing; + + /*! Queue statistics */ + struct rx_stats stats; + + /*! Rx queue spin lock */ + sal_spinlock_t lock; + + /*! Queue state */ + int state; + /*! Queue is used */ +#define PDMA_RX_QUEUE_USED (1 << 0) + /*! Queue is setup */ +#define PDMA_RX_QUEUE_SETUP (1 << 1) + /*! Queue is active */ +#define PDMA_RX_QUEUE_ACTIVE (1 << 2) + /*! Queue is busy */ +#define PDMA_RX_QUEUE_BUSY (1 << 3) + /*! Queue in batch refilling mode */ +#define PDMA_RX_BATCH_REFILL (1 << 4) + + /*! Queue status */ + uint32_t status; + /*! Queue is suspended */ +#define PDMA_RX_QUEUE_XOFF (1 << 0) + + /*! DMA buffer mode */ + enum buf_mode buf_mode; + + /*! Page order in PDMA_BUF_MODE_PAGE mode */ + uint32_t page_order; +}; + +/*! + * \brief Tx queue statistics. + */ +struct tx_stats { + /*! Number of sent packets */ + uint64_t packets; + + /*! Number of sent bytes */ + uint64_t bytes; + + /*! Number of dropped packets */ + uint64_t dropped; + + /*! Number of errors */ + uint64_t errors; + + /*! Number of suspends */ + uint64_t xoffs; +}; + +/*! + * \brief Tx queue structure. + */ +struct pdma_tx_queue { + /*! Group index to which this queue belongs */ + uint32_t group_id; + + /*! Global channel index */ + uint32_t chan_id; + + /*! Queue index */ + uint32_t queue_id; + + /*! pointer to the device control structure */ + struct dev_ctrl *ctrl; + + /*! Tx packet buffer pointers */ + struct pdma_tx_buf *pbuf; + + /*! Tx ring address */ + void *ring; + + /*! Tx ring DMA address */ + dma_addr_t ring_addr; + + /*! Tx ring DMA halt address */ + dma_addr_t halt_addr; + + /*! Total number of descriptors */ + uint32_t nb_desc; + + /*! Next free ring entry */ + uint32_t curr; + + /*! First entry to be transmitted */ + uint32_t dirt; + + /*! Halt ring entry */ + uint32_t halt; + + /*! Max free descriptors to hold in non-intr mode */ + uint32_t free_thresh; + + /*! Tx interrupt coalesce value */ + uint32_t ic_val; + + /*! Tx interrupt coalescing */ + int intr_coalescing; + + /*! Queue statistics */ + struct tx_stats stats; + + /*! Tx queue spin lock */ + sal_spinlock_t lock; + + /*! Tx mutex spin lock */ + sal_spinlock_t mutex; + + /*! Tx mutex and flow control semaphore */ + sal_sem_t sem; + + /*! Queue state */ + int state; + /*! Queue is used */ +#define PDMA_TX_QUEUE_USED (1 << 0) + /*! Queue is setup */ +#define PDMA_TX_QUEUE_SETUP (1 << 1) + /*! Queue is active */ +#define PDMA_TX_QUEUE_ACTIVE (1 << 2) + /*! Queue is setup */ +#define PDMA_TX_QUEUE_BUSY (1 << 3) + /*! Queue in polling mode */ +#define PDMA_TX_QUEUE_POLL (1 << 4) + + /*! Queue status */ + uint32_t status; + /*! Queue is suspended */ +#define PDMA_TX_QUEUE_XOFF (1 << 0) + + /*! DMA buffer mode */ + enum buf_mode buf_mode; +}; + +/*! + * \brief Setup Rx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_rx_queue_setup(struct pdma_dev *dev, int queue); + +/*! + * \brief Release Rx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_rx_queue_release(struct pdma_dev *dev, int queue); + +/*! + * \brief Restore Rx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_rx_queue_restore(struct pdma_dev *dev, int queue); + +/*! + * \brief Setup virtual Rx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_rx_vqueue_setup(struct pdma_dev *dev, int queue); + +/*! + * \brief Release virtual Rx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_rx_vqueue_release(struct pdma_dev *dev, int queue); + +/*! + * \brief Setup Tx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_tx_queue_setup(struct pdma_dev *dev, int queue); + +/*! + * \brief Release Tx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_tx_queue_release(struct pdma_dev *dev, int queue); + +/*! + * \brief Restore Tx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_tx_queue_restore(struct pdma_dev *dev, int queue); + +/*! + * \brief Setup virtual Tx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_tx_vqueue_setup(struct pdma_dev *dev, int queue); + +/*! + * \brief Release virtual Tx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_tx_vqueue_release(struct pdma_dev *dev, int queue); + +/*! + * \brief Suspend Rx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_rx_queue_suspend(struct pdma_dev *dev, int queue); + +/*! + * \brief Resume Rx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_rx_queue_resume(struct pdma_dev *dev, int queue); + +/*! + * \brief Suspend Tx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_tx_queue_suspend(struct pdma_dev *dev, int queue); + +/*! + * \brief Resume Tx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_tx_queue_resume(struct pdma_dev *dev, int queue); + +/*! + * \brief Wakeup Tx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_tx_queue_wakeup(struct pdma_dev *dev, int queue); + +/*! + * \brief Start Tx queue transmission. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * \param [in] buf Tx packet buffer. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_tx_queue_xmit(struct pdma_dev *dev, int queue, void *buf); + +/*! + * \brief Poll Rx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * \param [in] budget Poll budget. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_rx_queue_poll(struct pdma_dev *dev, int queue, int budget); + +/*! + * \brief Poll Tx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * \param [in] budget Poll budget. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_tx_queue_poll(struct pdma_dev *dev, int queue, int budget); + +/*! + * \brief Poll queue group. + * + * \param [in] dev Device structure point. + * \param [in] group Group number. + * \param [in] budget Poll budget. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_group_poll(struct pdma_dev *dev, int group, int budget); + +/*! + * \brief Dump Rx ring. + * + * \param [in] dev Device structure point. + * \param [in] queue Rx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_rx_ring_dump(struct pdma_dev *dev, int queue); + +/*! + * \brief Dump Tx ring. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +bcmcnet_pdma_tx_ring_dump(struct pdma_dev *dev, int queue); + +#endif /* BCMCNET_RXTX_H */ + diff --git a/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_types.h b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_types.h new file mode 100644 index 0000000..c2c8229 --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/include/bcmcnet/bcmcnet_types.h @@ -0,0 +1,282 @@ +/*! \file bcmcnet_types.h + * + * BCMCNET public data structure and macro definitions. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMCNET_TYPES_H +#define BCMCNET_TYPES_H + +#include + +/*! Maximum length of device name */ +#define DEV_NAME_LEN_MAX 16 + +/*! Maximum number of groups supported each device */ +#define NUM_GRP_MAX 4 + +/*! Maximum number of queues supported each group */ +#define NUM_Q_PER_GRP 16 + +/*! Maximum number of queues supported each device */ +#define NUM_Q_MAX (NUM_GRP_MAX * NUM_Q_PER_GRP) + +/*! Maximum length of jumbo frame */ +#define JUMBO_FRAME_LEN_MAX 0xffff + +/*! Maximum Rx buffer size */ +#define RX_BUF_SIZE_MAX JUMBO_FRAME_LEN_MAX + +/*! Minimum Rx buffer size */ +#define RX_BUF_SIZE_MIN 68 + +/*! Default Rx buffer size */ +#define RX_BUF_SIZE_DFLT 9216 + +/*! + * \brief Transmission direction. + */ +enum pdma_dir { + PDMA_Q_RX = 0, + PDMA_Q_TX +}; + +/*! + * \brief Device information. + */ +typedef struct bcmcnet_dev_info { + /*! Device name */ + char dev_name[DEV_NAME_LEN_MAX]; + + /*! Device ID */ + uint32_t dev_id; + + /*! Device type */ + uint32_t dev_type; + + /*! Maximum number of groups */ + uint32_t max_groups; + + /*! Maximum number of queues */ + uint32_t max_queues; + + /*! Bitmap of groups at work */ + uint32_t bm_groups; + + /*! Bitmap of Rx queues at work */ + uint32_t bm_rx_queues; + + /*! Bitmap of Tx queues at work */ + uint32_t bm_tx_queues; + + /*! Number of groups at work */ + uint32_t nb_groups; + + /*! Number of Rx queues at work */ + uint32_t nb_rx_queues; + + /*! Number of Tx queues at work */ + uint32_t nb_tx_queues; + + /*! Rx descriptor size */ + uint32_t rx_desc_size; + + /*! Tx descriptor size */ + uint32_t tx_desc_size; + + /*! Rx packet header size */ + uint32_t rx_ph_size; + + /*! Tx packet header size */ + uint32_t tx_ph_size; + + /*! Rx buffer size */ + uint32_t rx_buf_dflt; + + /*! Number of descriptors for a queue */ + uint32_t nb_desc_dflt; + + /*! Rx buffer size per queue */ + uint32_t rx_buf_size[NUM_Q_MAX]; + + /*! Number of Rx descriptors per queue */ + uint32_t nb_rx_desc[NUM_Q_MAX]; + + /*! State of Rx queues */ + uint32_t rxq_state[NUM_Q_MAX]; + + /*! Number of Tx descriptors per queue */ + uint32_t nb_tx_desc[NUM_Q_MAX]; + + /*! State of Tx queues */ + uint32_t txq_state[NUM_Q_MAX]; +} bcmcnet_dev_info_t; + +/*! + * \brief Device statistics. + */ +typedef struct bcmcnet_dev_stats { + /*! Number of successfully received packets */ + uint64_t rx_packets; + + /*! Number of successfully received bytes */ + uint64_t rx_bytes; + + /*! Number of dropped packets */ + uint64_t rx_dropped; + + /*! Number of erroneous received packets */ + uint64_t rx_errors; + + /*! Number of error head packets */ + uint64_t rx_head_errors; + + /*! Number of error data packets */ + uint64_t rx_data_errors; + + /*! Number of error cell packets */ + uint64_t rx_cell_errors; + + /*! Number of RX pktbuf allocation failures */ + uint64_t rx_nomems; + + /*! Number of successfully transmitted packets */ + uint64_t tx_packets; + + /*! Number of successfully transmitted bytes */ + uint64_t tx_bytes; + + /*! Number of dropped packets */ + uint64_t tx_dropped; + + /*! Number of failed transmitted packets */ + uint64_t tx_errors; + + /*! Number of suspended transmission */ + uint64_t tx_xoffs; + + /*! Number of interrupts */ + uint64_t intrs; + + /*! Number of successfully received packets per queue */ + uint64_t rxq_packets[NUM_Q_MAX]; + + /*! Number of successfully received bytes per queue */ + uint64_t rxq_bytes[NUM_Q_MAX]; + + /*! Number of dropped packets per queue */ + uint64_t rxq_dropped[NUM_Q_MAX]; + + /*! Number of erroneous received packets per queue */ + uint64_t rxq_errors[NUM_Q_MAX]; + + /*! Number of error head packets per queue */ + uint64_t rxq_head_errors[NUM_Q_MAX]; + + /*! Number of error data packets per queue */ + uint64_t rxq_data_errors[NUM_Q_MAX]; + + /*! Number of error cell packets per queue */ + uint64_t rxq_cell_errors[NUM_Q_MAX]; + + /*! Number of RX pktbuf allocation failures per queue */ + uint64_t rxq_nomems[NUM_Q_MAX]; + + /*! Number of successfully transmitted bytes per queue */ + uint64_t txq_packets[NUM_Q_MAX]; + + /*! Number of successfully transmitted bytes per queue */ + uint64_t txq_bytes[NUM_Q_MAX]; + + /*! Number of dropped packets per queue */ + uint64_t txq_dropped[NUM_Q_MAX]; + + /*! Number of failed transmitted packets per queue */ + uint64_t txq_errors[NUM_Q_MAX]; + + /*! Number of suspended transmission per queue */ + uint64_t txq_xoffs[NUM_Q_MAX]; +} bcmcnet_dev_stats_t; + +/*! + * \brief Device modes. + */ +typedef enum dev_mode_e { + /*! + * User network mode. + * The standalone CNET works in user space. + */ + DEV_MODE_UNET = 0, + + /*! + * Kernel network mode. + * Combined with KNET module, CNET works in kernel space. + */ + DEV_MODE_KNET, + + /*! + * Virtual network mode. + * CNET works in user space as a virtual network. + * The hypervisor must be deployed in KNET module. + */ + DEV_MODE_VNET, + + /*! + * Hyper network mode. + * Combined with KNET module, CNET works in kernel space as a hypervisor. + * The virtual network is not neccessary in this mode. + */ + DEV_MODE_HNET, + + /*! Maximum number of mode */ + DEV_MODE_MAX +} dev_mode_t; + +/*! + * \brief VNET sync data. + */ +typedef struct vnet_sync_s { + /*! Rx ring address */ + uint64_t rx_ring_addr[NUM_Q_MAX]; + + /*! Rx ring size */ + uint32_t rx_ring_size[NUM_Q_MAX]; + + /*! Tx ring address */ + uint64_t tx_ring_addr[NUM_Q_MAX]; + + /*! Tx ring size */ + uint32_t tx_ring_size[NUM_Q_MAX]; +} vnet_sync_t; + +#endif /* BCMCNET_TYPES_H */ + diff --git a/src/bcm/common/pktio/bcmcnet/main/bcmcnet_core.c b/src/bcm/common/pktio/bcmcnet/main/bcmcnet_core.c new file mode 100644 index 0000000..39a10ad --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/main/bcmcnet_core.c @@ -0,0 +1,799 @@ +/*! \file bcmcnet_core.c + * + * Utility routines for BCMCNET driver. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include + +/*! + * Initialize a device + */ +int +bcmcnet_pdma_dev_init(struct pdma_dev *dev) +{ + int rv; + + /* Open the device */ + rv = bcmcnet_pdma_open(dev); + if (SHR_FAILURE(rv)) { + return rv; + } + + dev->attached = true; + + return SHR_E_NONE; +} + +/*! + * Clean up a device + */ +int +bcmcnet_pdma_dev_cleanup(struct pdma_dev *dev) +{ + if (!dev->attached) { + return SHR_E_NONE; + } + + dev->ops->dev_close(dev); + dev->ops = NULL; + + dev->attached = false; + + return SHR_E_NONE; +} + +/*! + * Start a device + */ +int +bcmcnet_pdma_dev_start(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + uint32_t qi; + int rv; + + if (!dev->attached) { + return SHR_E_UNAVAIL; + } + + if (dev->started) { + return SHR_E_NONE; + } + + rv = dev->ops->dev_config(dev, ctrl->bm_rxq, ctrl->bm_txq); + if (SHR_FAILURE(rv)) { + return rv; + } + + dev->started = true; + + /* Start all the Rx queues */ + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + rv = dev->ops->rx_queue_setup(dev, qi); + if (SHR_FAILURE(rv)) { + return rv; + } + dev->ops->rx_queue_intr_enable(dev, qi); + dev->ops->rx_queue_start(dev, qi); + } + + /* Start all the Tx queues */ + for (qi = 0; qi < ctrl->nb_txq; qi++) { + rv = dev->ops->tx_queue_setup(dev, qi); + if (SHR_FAILURE(rv)) { + return rv; + } + dev->ops->tx_queue_intr_enable(dev, qi); + dev->ops->tx_queue_start(dev, qi); + } + + bcmcnet_pdma_dev_info_get(dev); + + return SHR_E_NONE; +} + +/*! + * Stop a device + */ +int +bcmcnet_pdma_dev_stop(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + uint32_t qi; + + if (!dev->attached) { + return SHR_E_UNAVAIL; + } + + if (!dev->started) { + return SHR_E_NONE; + } + + /* Stop all the Rx queues */ + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + dev->ops->rx_queue_stop(dev, qi); + dev->ops->rx_queue_release(dev, qi); + } + + /* Stop all the Tx queues */ + for (qi = 0; qi < ctrl->nb_txq; qi++) { + dev->ops->tx_queue_stop(dev, qi); + dev->ops->tx_queue_release(dev, qi); + } + + dev->started = false; + + /* Disable all the Rx interrupts */ + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + dev->ops->rx_queue_intr_disable(dev, qi); + } + + /* Disable all the Tx interrupts */ + for (qi = 0; qi < ctrl->nb_txq; qi++) { + dev->ops->tx_queue_intr_disable(dev, qi); + } + + return SHR_E_NONE; +} + +/*! + * Suspend a device + */ +int +bcmcnet_pdma_dev_suspend(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + uint32_t qi; + int rv; + + if (!dev->attached) { + return SHR_E_UNAVAIL; + } + + dev->suspended = true; + + rv = dev->ops->dev_suspend(dev); + if (SHR_FAILURE(rv)) { + return rv; + } + + if (dev->flags & PDMA_ABORT) { + /* Abort all the Tx queues */ + for (qi = 0; qi < ctrl->nb_txq; qi++) { + dev->ops->tx_queue_stop(dev, qi); + } + /* Abort all the Rx queues */ + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + dev->ops->rx_queue_stop(dev, qi); + } + } + + return SHR_E_NONE; +} + +/*! + * Resume a device + */ +int +bcmcnet_pdma_dev_resume(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + uint32_t qi; + int rv; + + if (!dev->attached) { + return SHR_E_UNAVAIL; + } + + dev->suspended = false; + + if (dev->flags & PDMA_ABORT) { + /* + * H/W configuration of Packet DMA is gone in the FFB apply phase, + * so we need to program it again. + */ + dev->ops->dev_config(dev, ctrl->bm_rxq, ctrl->bm_txq); + + /* Restart all the Rx queues */ + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + dev->ops->rx_queue_release(dev, qi); + dev->ops->rx_queue_setup(dev, qi); + dev->ops->rx_queue_intr_enable(dev, qi); + dev->ops->rx_queue_start(dev, qi); + } + /* Restart all the Tx queues */ + for (qi = 0; qi < ctrl->nb_txq; qi++) { + dev->ops->tx_queue_release(dev, qi); + dev->ops->tx_queue_setup(dev, qi); + dev->ops->tx_queue_intr_enable(dev, qi); + dev->ops->tx_queue_start(dev, qi); + } + } + + rv = dev->ops->dev_resume(dev); + if (SHR_FAILURE(rv)) { + return rv; + } + + if (dev->flags & PDMA_ABORT) { + dev->flags &= ~PDMA_ABORT; + } + + return rv; +} + +/*! + * Suspend Rx + */ +int +bcmcnet_pdma_dev_rx_suspend(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + uint32_t qi; + + if (!dev->attached) { + return SHR_E_UNAVAIL; + } + + /* Suspend all the Rx queues */ + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + dev->ops->rx_queue_suspend(dev, qi); + } + + return SHR_E_NONE; +} + +/*! + * Resume Rx + */ +int +bcmcnet_pdma_dev_rx_resume(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + uint32_t qi; + + if (!dev->attached) { + return SHR_E_UNAVAIL; + } + + /* Resume all the Rx queues */ + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + dev->ops->rx_queue_resume(dev, qi); + } + + return SHR_E_NONE; +} + +/*! + * Dock to HNET + */ +int +bcmcnet_pdma_dev_dock(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + uint32_t qi; + int rv; + + if (!dev->attached) { + return SHR_E_UNAVAIL; + } + + /* Set up all the virtual Rx queues */ + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + rv = dev->ops->rx_vqueue_setup(dev, qi); + if (SHR_FAILURE(rv)) { + return rv; + } + } + + /* Set up all the virtual Tx queues */ + for (qi = 0; qi < ctrl->nb_txq; qi++) { + rv = dev->ops->tx_vqueue_setup(dev, qi); + if (SHR_FAILURE(rv)) { + return rv; + } + } + + return SHR_E_NONE; +} + +/*! + * Undock from HNET + */ +int +bcmcnet_pdma_dev_undock(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + uint32_t qi; + + if (!dev->attached) { + return SHR_E_UNAVAIL; + } + + /* Release all the virtual Rx queues */ + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + dev->ops->rx_vqueue_release(dev, qi); + } + + /* Release all the virtual Tx queues */ + for (qi = 0; qi < ctrl->nb_txq; qi++) { + dev->ops->tx_vqueue_release(dev, qi); + } + + return SHR_E_NONE; +} + +/*! + * Get device information + */ +int +bcmcnet_pdma_dev_info_get(struct pdma_dev *dev) +{ + if (!dev->ops || !dev->ops->dev_info_get) { + return SHR_E_INTERNAL; + } + + dev->ops->dev_info_get(dev); + + return SHR_E_NONE; +} + +/*! + * Get device statistics + */ +int +bcmcnet_pdma_dev_stats_get(struct pdma_dev *dev) +{ + if (!dev->ops || !dev->ops->dev_stats_get) { + return SHR_E_INTERNAL; + } + + dev->ops->dev_stats_get(dev); + + return SHR_E_NONE; +} + +/*! + * Reset device statistics + */ +int +bcmcnet_pdma_dev_stats_reset(struct pdma_dev *dev) +{ + if (!dev->ops || !dev->ops->dev_stats_reset) { + return SHR_E_INTERNAL; + } + + dev->ops->dev_stats_reset(dev); + + return SHR_E_NONE; +} + +/*! + * Convert a queue index to channel index + */ +int +bcmcnet_pdma_dev_queue_to_chan(struct pdma_dev *dev, int queue, int dir, int *chan) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + + if (dir == PDMA_Q_RX) { + if ((uint32_t)queue >= ctrl->nb_rxq || chan == NULL) { + return SHR_E_PARAM; + } + } else { + if ((uint32_t)queue >= ctrl->nb_txq || chan == NULL) { + return SHR_E_PARAM; + } + } + + if (!dev->ops || !dev->ops->dev_lq_to_pq) { + return SHR_E_INTERNAL; + } + + return dev->ops->dev_lq_to_pq(dev, queue, dir, chan); +} + +/*! + * Convert a channel index to queue index + */ +int +bcmcnet_pdma_dev_chan_to_queue(struct pdma_dev *dev, int chan, int *queue, int *dir) +{ + if (chan < 0 || chan >= dev->num_queues || queue == NULL || dir == NULL) { + return SHR_E_PARAM; + } + + if (!dev->ops || !dev->ops->dev_pq_to_lq) { + return SHR_E_INTERNAL; + } + + return dev->ops->dev_pq_to_lq(dev, chan, queue, dir); +} + +/*! + * Enable interrupt for a Rx queue + */ +int +bcmcnet_rx_queue_intr_enable(struct pdma_dev *dev, int queue) +{ + if (!dev->ops || !dev->ops->rx_queue_intr_enable) { + return SHR_E_INTERNAL; + } + + return dev->ops->rx_queue_intr_enable(dev, queue); +} + +/*! + * Disable interrupt for a Rx queue + */ +int +bcmcnet_rx_queue_intr_disable(struct pdma_dev *dev, int queue) +{ + if (!dev->ops || !dev->ops->rx_queue_intr_disable) { + return SHR_E_INTERNAL; + } + + return dev->ops->rx_queue_intr_disable(dev, queue); +} + +/*! + * Acknowledge interrupt for a Rx queue + */ +int +bcmcnet_rx_queue_intr_ack(struct pdma_dev *dev, int queue) +{ + if (!dev->ops || !dev->ops->rx_queue_intr_ack) { + return SHR_E_INTERNAL; + } + + return dev->ops->rx_queue_intr_ack(dev, queue); +} + +/*! + * Check interrupt for a Rx queue + */ +int +bcmcnet_rx_queue_intr_check(struct pdma_dev *dev, int queue) +{ + if (!dev->ops || !dev->ops->rx_queue_intr_check) { + return SHR_E_INTERNAL; + } + + return dev->ops->rx_queue_intr_check(dev, queue); +} + +/*! + * Enable interrupt for a Tx queue + */ +int +bcmcnet_tx_queue_intr_enable(struct pdma_dev *dev, int queue) +{ + if (!dev->ops || !dev->ops->tx_queue_intr_enable) { + return SHR_E_INTERNAL; + } + + return dev->ops->tx_queue_intr_enable(dev, queue); +} + +/*! + * Disable interrupt for a Tx queue + */ +int +bcmcnet_tx_queue_intr_disable(struct pdma_dev *dev, int queue) +{ + if (!dev->ops || !dev->ops->tx_queue_intr_disable) { + return SHR_E_INTERNAL; + } + + return dev->ops->tx_queue_intr_disable(dev, queue); +} + +/*! + * Acknowledge interrupt for a Tx queue + */ +int +bcmcnet_tx_queue_intr_ack(struct pdma_dev *dev, int queue) +{ + if (!dev->ops || !dev->ops->tx_queue_intr_ack) { + return SHR_E_INTERNAL; + } + + return dev->ops->tx_queue_intr_ack(dev, queue); +} + +/*! + * Check interrupt for a Tx queue + */ +int +bcmcnet_tx_queue_intr_check(struct pdma_dev *dev, int queue) +{ + if (!dev->ops || !dev->ops->tx_queue_intr_check) { + return SHR_E_INTERNAL; + } + + return dev->ops->tx_queue_intr_check(dev, queue); +} + +/*! + * Enable interrupt for a queue + */ +int +bcmcnet_queue_intr_enable(struct pdma_dev *dev, struct intr_handle *hdl) +{ + if (hdl->dir == PDMA_Q_RX) { + return bcmcnet_rx_queue_intr_enable(dev, hdl->queue); + } else { + return bcmcnet_tx_queue_intr_enable(dev, hdl->queue); + } +} + +/*! + * Disable interrupt for a queue + */ +int +bcmcnet_queue_intr_disable(struct pdma_dev *dev, struct intr_handle *hdl) +{ + if (hdl->dir == PDMA_Q_RX) { + return bcmcnet_rx_queue_intr_disable(dev, hdl->queue); + } else { + return bcmcnet_tx_queue_intr_disable(dev, hdl->queue); + } +} + +/*! + * Acknowledge interrupt for a queue + */ +int +bcmcnet_queue_intr_ack(struct pdma_dev *dev, struct intr_handle *hdl) +{ + if (hdl->dir == PDMA_Q_RX) { + return bcmcnet_rx_queue_intr_ack(dev, hdl->queue); + } else { + return bcmcnet_tx_queue_intr_ack(dev, hdl->queue); + } +} + +/*! + * Check interrupt for a queue + */ +int +bcmcnet_queue_intr_check(struct pdma_dev *dev, struct intr_handle *hdl) +{ + if (hdl->dir == PDMA_Q_RX) { + return bcmcnet_rx_queue_intr_check(dev, hdl->queue); + } else { + return bcmcnet_tx_queue_intr_check(dev, hdl->queue); + } +} + +/*! + * Enable interrupt for a queue group + */ +int +bcmcnet_group_intr_enable(struct pdma_dev *dev, int group) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct queue_group *grp = &ctrl->grp[group]; + int queue, dir; + int i; + + if (!dev->ops) { + return SHR_E_INTERNAL; + } + + for (i = 0; i < dev->grp_queues; i++) { + if (1 << i & grp->bm_rxq) { + dev->ops->dev_pq_to_lq(dev, i + group * dev->grp_queues, &queue, &dir); + dev->ops->rx_queue_intr_enable(dev, queue); + } + } + + for (i = 0; i < dev->grp_queues; i++) { + if (1 << i & grp->bm_txq) { + dev->ops->dev_pq_to_lq(dev, i + group * dev->grp_queues, &queue, &dir); + dev->ops->tx_queue_intr_enable(dev, queue); + } + } + + return SHR_E_NONE; +} + +/*! + * Disable interrupt for a queue group + */ +int +bcmcnet_group_intr_disable(struct pdma_dev *dev, int group) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct queue_group *grp = &ctrl->grp[group]; + int queue, dir; + int i; + + if (!dev->ops) { + return SHR_E_INTERNAL; + } + + for (i = 0; i < dev->grp_queues; i++) { + if (1 << i & grp->bm_rxq) { + dev->ops->dev_pq_to_lq(dev, i + group * dev->grp_queues, &queue, &dir); + dev->ops->rx_queue_intr_disable(dev, queue); + } + } + + for (i = 0; i < dev->grp_queues; i++) { + if (1 << i & grp->bm_txq) { + dev->ops->dev_pq_to_lq(dev, i + group * dev->grp_queues, &queue, &dir); + dev->ops->tx_queue_intr_disable(dev, queue); + } + } + + return SHR_E_NONE; +} + +/*! + * Acknowledge interrupt for a queue group + */ +int +bcmcnet_group_intr_ack(struct pdma_dev *dev, int group) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct queue_group *grp = &ctrl->grp[group]; + int queue, dir; + int i; + + if (!dev->ops) { + return SHR_E_INTERNAL; + } + + for (i = 0; i < dev->grp_queues; i++) { + if (1 << i & grp->bm_rxq) { + dev->ops->dev_pq_to_lq(dev, i + group * dev->grp_queues, &queue, &dir); + dev->ops->rx_queue_intr_ack(dev, queue); + } + } + + for (i = 0; i < dev->grp_queues; i++) { + if (1 << i & grp->bm_txq) { + dev->ops->dev_pq_to_lq(dev, i + group * dev->grp_queues, &queue, &dir); + dev->ops->tx_queue_intr_ack(dev, queue); + } + } + + return SHR_E_NONE; +} + +/*! + * Check interrupt for a queue group + */ +bool +bcmcnet_group_intr_check(struct pdma_dev *dev, int group) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct queue_group *grp = &ctrl->grp[group]; + int queue, dir; + int i; + + if (!dev->ops) { + return false; + } + + for (i = 0; i < dev->grp_queues; i++) { + if (1 << i & grp->bm_rxq) { + dev->ops->dev_pq_to_lq(dev, i + group * dev->grp_queues, &queue, &dir); + if (dev->ops->rx_queue_intr_check(dev, queue)) { + return true; + } + } + } + + for (i = 0; i < dev->grp_queues; i++) { + if (1 << i & grp->bm_txq) { + dev->ops->dev_pq_to_lq(dev, i + group * dev->grp_queues, &queue, &dir); + if (dev->ops->tx_queue_intr_check(dev, queue)) { + return true; + } + } + } + + return false; +} + +/*! + * Poll a Rx queue + */ +int +bcmcnet_rx_queue_poll(struct pdma_dev *dev, int queue, int budget) +{ + if (!dev->started) { + return SHR_E_NONE; + } + + if (!dev->ops || !dev->ops->rx_queue_poll) { + return SHR_E_INTERNAL; + } + + return dev->ops->rx_queue_poll(dev, queue, budget); +} + +/*! + * Poll a Tx queue + */ +int +bcmcnet_tx_queue_poll(struct pdma_dev *dev, int queue, int budget) +{ + if (!dev->started) { + return SHR_E_NONE; + } + + if (!dev->ops || !dev->ops->tx_queue_poll) { + return SHR_E_INTERNAL; + } + + return dev->ops->tx_queue_poll(dev, queue, budget); +} + +/*! + * Poll a queue + */ +int +bcmcnet_queue_poll(struct pdma_dev *dev, struct intr_handle *hdl, int budget) +{ + if (!dev->started) { + return SHR_E_NONE; + } + + if (hdl->dir == PDMA_Q_RX) { + return bcmcnet_rx_queue_poll(dev, hdl->queue, budget); + } else { + return bcmcnet_tx_queue_poll(dev, hdl->queue, budget); + } +} + +/*! + * Poll a queue group + */ +int +bcmcnet_group_poll(struct pdma_dev *dev, int group, int budget) +{ + if (!dev->started) { + return SHR_E_NONE; + } + + if (!dev->ops || !dev->ops->group_poll) { + return SHR_E_INTERNAL; + } + + return dev->ops->group_poll(dev, group, budget); +} + diff --git a/src/bcm/common/pktio/bcmcnet/main/bcmcnet_dev.c b/src/bcm/common/pktio/bcmcnet/main/bcmcnet_dev.c new file mode 100644 index 0000000..fbafe90 --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/main/bcmcnet_dev.c @@ -0,0 +1,1135 @@ +/*! \file bcmcnet_dev.c + * + * Utility routines for BCMCNET device. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include + +/*! + * Free resource for a Rx queue + */ +static void +bcn_rx_queues_free(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_rx_queue *rxq = NULL; + int gi, qi; + + for (gi = 0; gi < dev->num_groups; gi++) { + for (qi = 0; qi < dev->grp_queues; qi++) { + rxq = (struct pdma_rx_queue *)ctrl->grp[gi].rx_queue[qi]; + if (!rxq) { + continue; + } + sal_free(rxq); + ctrl->grp[gi].rx_queue[qi] = NULL; + if (dev->mode == DEV_MODE_HNET && ctrl->grp[gi].vnet_rxq[qi]) { + sal_free(ctrl->grp[gi].vnet_rxq[qi]); + ctrl->grp[gi].vnet_rxq[qi] = NULL; + } + } + } +} + +/*! + * Allocate resource for a Rx queue + */ +static int +bcn_rx_queues_alloc(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_rx_queue *rxq = NULL, *vrxq = NULL; + int gi, qi; + + for (gi = 0; gi < dev->num_groups; gi++) { + for (qi = 0; qi < dev->grp_queues; qi++) { + rxq = sal_alloc(sizeof(*rxq), "bcmcnetRxQueue"); + if (!rxq) { + goto error; + } + ctrl->grp[gi].rx_queue[qi] = rxq; + sal_memset(rxq, 0, sizeof(*rxq)); + rxq->group_id = gi; + rxq->chan_id = qi + gi * dev->grp_queues; + rxq->ctrl = ctrl; + if (dev->mode == DEV_MODE_HNET) { + vrxq = sal_alloc(sizeof(*vrxq), "bcmcnetVnetRxQueue"); + if (!vrxq) { + goto error; + } + sal_memset(vrxq, 0, sizeof(*vrxq)); + vrxq->group_id = gi; + vrxq->chan_id = qi + gi * dev->grp_queues; + vrxq->ctrl = ctrl; + ctrl->grp[gi].vnet_rxq[qi] = vrxq; + } + } + } + + return SHR_E_NONE; + +error: + bcn_rx_queues_free(dev); + + return SHR_E_MEMORY; +} + +/*! + * Free resource for a Tx queue + */ +static void +bcn_tx_queues_free(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_tx_queue *txq = NULL; + int gi, qi; + + for (gi = 0; gi < dev->num_groups; gi++) { + for (qi = 0; qi < dev->grp_queues; qi++) { + txq = (struct pdma_tx_queue *)ctrl->grp[gi].tx_queue[qi]; + if (!txq) { + continue; + } + if (txq->sem) { + sal_sem_destroy(txq->sem); + } + sal_free(txq); + ctrl->grp[gi].tx_queue[qi] = NULL; + if (dev->mode == DEV_MODE_HNET && ctrl->grp[gi].vnet_txq[qi]) { + sal_free(ctrl->grp[gi].vnet_txq[qi]); + ctrl->grp[gi].vnet_txq[qi] = NULL; + } + } + } +} + +/*! + * Allocate resource for a Tx queue + */ +static int +bcn_tx_queues_alloc(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_tx_queue *txq = NULL, *vtxq = NULL; + int gi, qi; + + for (gi = 0; gi < dev->num_groups; gi++) { + for (qi = 0; qi < dev->grp_queues; qi++) { + txq = sal_alloc(sizeof(*txq), "bcmcnetTxQueue"); + if (!txq) { + goto error; + } + ctrl->grp[gi].tx_queue[qi] = txq; + sal_memset(txq, 0, sizeof(*txq)); + txq->group_id = gi; + txq->chan_id = qi + gi * dev->grp_queues; + txq->ctrl = ctrl; + txq->sem = sal_sem_create("bcmcnetTxMutexSem", SAL_SEM_BINARY, 1); + if (!txq->sem) { + goto error; + } + if (dev->mode == DEV_MODE_HNET) { + vtxq = sal_alloc(sizeof(*vtxq), "bcmcnetVnetTxQueue"); + if (!vtxq) { + goto error; + } + sal_memset(vtxq, 0, sizeof(*vtxq)); + vtxq->group_id = gi; + vtxq->chan_id = qi + gi * dev->grp_queues; + vtxq->ctrl = ctrl; + ctrl->grp[gi].vnet_txq[qi] = vtxq; + } + } + } + + return SHR_E_NONE; + +error: + bcn_tx_queues_free(dev); + + return SHR_E_MEMORY; +} + +/*! + * \brief Parse Rx groups + * + * \param [in] dev Device structure point. + * \param [in] qbm Rx queue bitmap. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +bcn_rx_queue_group_parse(struct pdma_dev *dev, uint32_t qbm) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)ctrl->buf_mngr; + struct pdma_rx_queue *rxq = NULL; + struct intr_handle *hdl = NULL; + uint32_t mask; + int gi, qi, qn; + + ctrl->nb_rxq = 0; + + /* Figure out available groups and Rx queues */ + for (gi = 0; gi < dev->num_groups; gi++) { + if (!ctrl->grp[gi].attached) { + continue; + } + qn = 0; + mask = 0; + for (qi = 0; qi < dev->grp_queues; qi++) { + rxq = (struct pdma_rx_queue *)ctrl->grp[gi].rx_queue[qi]; + hdl = &ctrl->grp[gi].intr_hdl[qi]; + if (1 << (qi + gi * dev->grp_queues) & qbm) { + /* Set the number of descriptors */ + rxq->nb_desc = ctrl->grp[gi].nb_desc[qi]; + if (!rxq->nb_desc) { + rxq->nb_desc = ctrl->nb_desc; + ctrl->grp[gi].nb_desc[qi] = rxq->nb_desc; + } + /* Set Rx buffer size */ + rxq->buf_size = ctrl->grp[gi].rx_size[qi]; + if (rxq->buf_size < RX_BUF_SIZE_MIN) { + rxq->buf_size = RX_BUF_SIZE_MIN; + ctrl->grp[gi].rx_size[qi] = rxq->buf_size; + } else if (rxq->buf_size > RX_BUF_SIZE_MAX) { + rxq->buf_size = ctrl->rx_buf_size; + ctrl->grp[gi].rx_size[qi] = rxq->buf_size; + } + rxq->buf_size += dev->rx_ph_size; + /* Set mode and state for the queue */ + rxq->buf_mode = bm->rx_buf_mode(dev, rxq); + rxq->state |= PDMA_RX_QUEUE_USED; + if (dev->flags & PDMA_RX_BATCHING) { + rxq->free_thresh = rxq->nb_desc / 4; + rxq->state |= PDMA_RX_BATCH_REFILL; + } + /* Update queue index */ + rxq->queue_id = ctrl->nb_rxq; + ctrl->rx_queue[rxq->queue_id] = rxq; + ctrl->nb_rxq++; + qn++; + mask |= 1 << qi; + /* Set up handler for the queue */ + hdl->queue = rxq->queue_id; + hdl->dir = PDMA_Q_RX; + hdl->budget = ctrl->budget < rxq->nb_desc ? + ctrl->budget : rxq->nb_desc; + if (dev->mode == DEV_MODE_HNET) { + ctrl->vnet_rxq[rxq->queue_id] = ctrl->grp[gi].vnet_rxq[qi]; + } + } else { + rxq->state = 0; + } + } + + /* Set group metadata */ + if (qn) { + ctrl->grp[gi].bm_rxq = mask; + ctrl->grp[gi].nb_rxq = qn; + } else { + ctrl->grp[gi].bm_rxq = 0; + ctrl->grp[gi].nb_rxq = 0; + } + } + + return SHR_E_NONE; +} + +/*! + * \brief Parse Tx groups + * + * \param [in] dev Device structure point. + * \param [in] qbm Tx queue bitmap. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +bcn_tx_queue_group_parse(struct pdma_dev *dev, uint32_t qbm) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_tx_queue *txq = NULL; + struct intr_handle *hdl = NULL; + uint32_t mask; + int gi, qi, qn; + + ctrl->nb_txq = 0; + + /* Figure out available groups and Tx queues */ + for (gi = 0; gi < dev->num_groups; gi++) { + if (!ctrl->grp[gi].attached) { + continue; + } + qn = 0; + mask = 0; + for (qi = 0; qi < dev->grp_queues; qi++) { + txq = (struct pdma_tx_queue *)ctrl->grp[gi].tx_queue[qi]; + hdl = &ctrl->grp[gi].intr_hdl[qi]; + if (1 << (qi + gi * dev->grp_queues) & qbm) { + /* Set the number of descriptors */ + txq->nb_desc = ctrl->grp[gi].nb_desc[qi]; + if (!txq->nb_desc) { + txq->nb_desc = ctrl->nb_desc; + ctrl->grp[gi].nb_desc[qi] = txq->nb_desc; + } + /* Set mode and state for the queue */ + txq->state |= PDMA_TX_QUEUE_USED; + if (dev->flags & PDMA_TX_POLLING) { + txq->free_thresh = txq->nb_desc / 4; + txq->state |= PDMA_TX_QUEUE_POLL; + } + /* Update queue index */ + txq->queue_id = ctrl->nb_txq; + ctrl->tx_queue[txq->queue_id] = txq; + ctrl->nb_txq++; + qn++; + mask |= 1 << qi; + /* Set up handler for the queue */ + hdl->queue = txq->queue_id; + hdl->dir = PDMA_Q_TX; + hdl->budget = ctrl->budget < txq->nb_desc ? + ctrl->budget : txq->nb_desc; + if (dev->mode == DEV_MODE_HNET) { + ctrl->vnet_txq[txq->queue_id] = ctrl->grp[gi].vnet_txq[qi]; + } + } else { + txq->state = 0; + } + } + + /* Set group metadata */ + if (qn) { + ctrl->grp[gi].bm_txq = mask; + ctrl->grp[gi].nb_txq = qn; + } else { + ctrl->grp[gi].bm_txq = 0; + ctrl->grp[gi].nb_txq = 0; + } + } + + return SHR_E_NONE; +} + +/*! + * \brief Configure device + * + * \param [in] dev Device structure point. + * \param [in] bm_rxq Rx queue bitmap. + * \param [in] bm_txq Tx queue bitmap. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +bcmcnet_pdma_config(struct pdma_dev *dev, uint32_t bm_rxq, uint32_t bm_txq) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + int gi; + + if (!bm_rxq || !bm_txq || (bm_rxq & bm_txq)) { + return SHR_E_PARAM; + } + + bcn_rx_queue_group_parse(dev, bm_rxq); + bcn_tx_queue_group_parse(dev, bm_txq); + + for (gi = 0; gi < dev->num_groups; gi++) { + if (!ctrl->grp[gi].attached) { + continue; + } + /* Update group metadata */ + if (!ctrl->grp[gi].bm_rxq && !ctrl->grp[gi].bm_txq) { + ctrl->grp[gi].attached = false; + ctrl->bm_grp &= ~(1 << gi); + ctrl->nb_grp--; + continue; + } + ctrl->grp[gi].ctrl = ctrl; + ctrl->grp[gi].id = gi; + ctrl->grp[gi].irq_mask = 0; + } + + return hw->hdls.hw_config(hw); +} + +/*! + * Close device + */ +static int +bcmcnet_pdma_close(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)dev->ctrl.hw; + int gi; + + hw->hdls.hw_reset(hw); + + for (gi = 0; gi < dev->num_groups; gi++) { + if (!ctrl->grp[gi].attached) { + continue; + } + /* Reset group metadata */ + ctrl->bm_grp &= ~(1 << gi); + ctrl->nb_grp--; + ctrl->grp[gi].irq_mask = 0; + ctrl->grp[gi].poll_queues = 0; + ctrl->grp[gi].attached = false; + } + + bcn_rx_queues_free(dev); + bcn_tx_queues_free(dev); + + return SHR_E_NONE; +} + +/*! + * Suspend device + */ +static int +bcmcnet_pdma_suspend(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + uint32_t qi; + + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + bcmcnet_pdma_rx_queue_suspend(dev, qi); + } + + if (dev->ndev_detach) { + dev->ndev_detach(dev); + } else { + for (qi = 0; qi < ctrl->nb_txq; qi++) { + bcmcnet_pdma_tx_queue_suspend(dev, qi); + } + } + + return SHR_E_NONE; +} + +/*! + * Resume device + */ +static int +bcmcnet_pdma_resume(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + uint32_t qi; + + if (dev->ndev_attach) { + dev->ndev_attach(dev); + } else { + for (qi = 0; qi < ctrl->nb_txq; qi++) { + bcmcnet_pdma_tx_queue_resume(dev, qi); + } + } + + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + bcmcnet_pdma_rx_queue_resume(dev, qi); + } + + return SHR_E_NONE; +} + +/*! + * Get device information + */ +static void +bcmcnet_pdma_info_get(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + struct pdma_tx_queue *txq = NULL; + uint32_t qi; + + sal_strncpy(dev->info.dev_name, dev->name, sizeof(dev->info.dev_name) - 1); + dev->info.dev_name[sizeof(dev->info.dev_name) - 1] = 0; + dev->info.dev_id = dev->dev_id; + dev->info.dev_type = dev->dev_type; + dev->info.max_groups = hw->info.num_cmcs; + dev->info.max_queues = hw->info.num_chans; + dev->info.bm_groups = ctrl->bm_grp; + dev->info.bm_rx_queues = ctrl->bm_rxq; + dev->info.bm_tx_queues = ctrl->bm_txq; + dev->info.nb_groups = ctrl->nb_grp; + dev->info.nb_rx_queues = ctrl->nb_rxq; + dev->info.nb_tx_queues = ctrl->nb_txq; + dev->info.rx_desc_size = hw->info.rx_dcb_size; + dev->info.tx_desc_size = hw->info.tx_dcb_size; + dev->info.rx_ph_size = hw->info.rx_ph_size; + dev->info.tx_ph_size = hw->info.tx_ph_size; + dev->info.rx_buf_dflt = ctrl->rx_buf_size; + dev->info.nb_desc_dflt = ctrl->nb_desc; + + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[qi]; + if (!rxq) { + continue; + } + dev->info.rx_buf_size[qi] = rxq->buf_size; + dev->info.nb_rx_desc[qi] = rxq->nb_desc; + dev->info.rxq_state[qi] = rxq->state; + } + + for (qi = 0; qi < ctrl->nb_txq; qi++) { + txq = (struct pdma_tx_queue *)ctrl->tx_queue[qi]; + if (!txq) { + continue; + } + dev->info.nb_tx_desc[qi] = txq->nb_desc; + dev->info.txq_state[qi] = txq->state; + } +} + +/*! + * Get device statistics + */ +static void +bcmcnet_pdma_stats_get(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_rx_queue *rxq = NULL; + struct pdma_tx_queue *txq = NULL; + uint32_t packets = 0, bytes = 0, dropped = 0, errors = 0, nomems = 0, xoffs = 0; + uint32_t head_errors = 0, data_errors = 0, cell_errors = 0; + uint32_t qi; + + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[qi]; + if (!rxq) { + continue; + } + packets += rxq->stats.packets; + bytes += rxq->stats.bytes; + dropped += rxq->stats.dropped; + errors += rxq->stats.errors; + head_errors += rxq->stats.head_errors; + data_errors += rxq->stats.data_errors; + cell_errors += rxq->stats.cell_errors; + nomems += rxq->stats.nomems; + dev->stats.rxq_packets[qi] = rxq->stats.packets; + dev->stats.rxq_bytes[qi] = rxq->stats.bytes; + dev->stats.rxq_dropped[qi] = rxq->stats.dropped; + dev->stats.rxq_errors[qi] = rxq->stats.errors; + dev->stats.rxq_head_errors[qi] = rxq->stats.head_errors; + dev->stats.rxq_data_errors[qi] = rxq->stats.data_errors; + dev->stats.rxq_cell_errors[qi] = rxq->stats.cell_errors; + dev->stats.rxq_nomems[qi] = rxq->stats.nomems; + } + + dev->stats.rx_packets = packets; + dev->stats.rx_bytes = bytes; + dev->stats.rx_dropped = dropped; + dev->stats.rx_errors = errors; + dev->stats.rx_head_errors = head_errors; + dev->stats.rx_data_errors = data_errors; + dev->stats.rx_cell_errors = cell_errors; + dev->stats.rx_nomems = nomems; + + packets = bytes = dropped = errors = 0; + for (qi = 0; qi < ctrl->nb_txq; qi++) { + txq = (struct pdma_tx_queue *)ctrl->tx_queue[qi]; + if (!txq) { + continue; + } + packets += txq->stats.packets; + bytes += txq->stats.bytes; + dropped += txq->stats.dropped; + errors += txq->stats.errors; + xoffs += txq->stats.xoffs; + dev->stats.txq_packets[qi] = txq->stats.packets; + dev->stats.txq_bytes[qi] = txq->stats.bytes; + dev->stats.txq_dropped[qi] = txq->stats.dropped; + dev->stats.txq_errors[qi] = txq->stats.errors; + dev->stats.txq_xoffs[qi] = txq->stats.xoffs; + } + + dev->stats.tx_packets = packets; + dev->stats.tx_bytes = bytes; + dev->stats.tx_dropped = dropped; + dev->stats.tx_errors = errors; + dev->stats.tx_xoffs = xoffs; +} + +/*! + * Reset device statistics + */ +static void +bcmcnet_pdma_stats_reset(struct pdma_dev *dev) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_rx_queue *rxq = NULL; + struct pdma_tx_queue *txq = NULL; + uint32_t qi; + + sal_memset(&dev->stats, 0, sizeof(struct bcmcnet_dev_stats)); + + for (qi = 0; qi < ctrl->nb_rxq; qi++) { + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[qi]; + if (!rxq) { + continue; + } + rxq->stats.packets = 0; + rxq->stats.bytes = 0; + rxq->stats.dropped = 0; + rxq->stats.errors = 0; + rxq->stats.head_errors = 0; + rxq->stats.data_errors = 0; + rxq->stats.cell_errors = 0; + rxq->stats.nomems = 0; + } + + for (qi = 0; qi < ctrl->nb_txq; qi++) { + txq = (struct pdma_tx_queue *)ctrl->tx_queue[qi]; + if (!txq) { + continue; + } + txq->stats.packets = 0; + txq->stats.bytes = 0; + txq->stats.dropped = 0; + txq->stats.errors = 0; + txq->stats.xoffs = 0; + } +} + +/*! + * Convert logic queue to physical queue + */ +static int +bcmcnet_pdma_lq_to_pq(struct pdma_dev *dev, int queue, int dir, int *chan) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_rx_queue *rxq = NULL; + struct pdma_tx_queue *txq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX) { + return SHR_E_PARAM; + } + + if (dir == PDMA_Q_RX) { + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + if (rxq->state & PDMA_RX_QUEUE_USED) { + *chan = rxq->chan_id; + return SHR_E_NONE; + } + } else { + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + if (txq->state & PDMA_TX_QUEUE_USED) { + *chan = txq->chan_id; + return SHR_E_NONE; + } + } + + return SHR_E_UNAVAIL; +} + +/*! + * Convert physical queue to logic queue + */ +static int +bcmcnet_pdma_pq_to_lq(struct pdma_dev *dev, int chan, int *queue, int *dir) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_rx_queue *rxq = NULL; + struct pdma_tx_queue *txq = NULL; + + rxq = ctrl->grp[chan / dev->grp_queues].rx_queue[chan % dev->grp_queues]; + if (rxq->state & PDMA_RX_QUEUE_USED) { + *queue = rxq->queue_id; + *dir = PDMA_Q_RX; + return SHR_E_NONE; + } + + txq = ctrl->grp[chan / dev->grp_queues].tx_queue[chan % dev->grp_queues]; + if (txq->state & PDMA_TX_QUEUE_USED) { + *queue = txq->queue_id; + *dir = PDMA_Q_TX; + return SHR_E_NONE; + } + + return SHR_E_UNAVAIL; +} + +/*! + * Start Rx queue + */ +static int +bcmcnet_pdma_rx_queue_start(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX) { + return SHR_E_PARAM; + } + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + rxq->state |= PDMA_RX_QUEUE_ACTIVE; + + return hw->hdls.chan_start(hw, rxq->chan_id); +} + +/*! + * Stop Rx queue + */ +static int +bcmcnet_pdma_rx_queue_stop(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX) { + return SHR_E_PARAM; + } + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + rxq->state &= ~PDMA_RX_QUEUE_ACTIVE; + + return hw->hdls.chan_stop(hw, rxq->chan_id); +} + +/*! + * Start Tx queue + */ +static int +bcmcnet_pdma_tx_queue_start(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_tx_queue *txq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX) { + return SHR_E_PARAM; + } + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + txq->state |= PDMA_TX_QUEUE_ACTIVE; + + return dev->flags & PDMA_CHAIN_MODE ? SHR_E_NONE : + hw->hdls.chan_start(hw, txq->chan_id); +} + +/*! + * Stop Tx queue + */ +static int +bcmcnet_pdma_tx_queue_stop(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_tx_queue *txq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX) { + return SHR_E_PARAM; + } + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + txq->state &= ~PDMA_TX_QUEUE_ACTIVE; + + return hw->hdls.chan_stop(hw, txq->chan_id); +} + +/*! + * Enable Rx queue interrupt + */ +static int +bcmcnet_pdma_rx_queue_intr_enable(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX) { + return SHR_E_PARAM; + } + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + + return hw->hdls.chan_intr_enable(hw, rxq->chan_id); +} + +/*! + * Disable Rx queue interrupt + */ +static int +bcmcnet_pdma_rx_queue_intr_disable(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX) { + return SHR_E_PARAM; + } + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + + return hw->hdls.chan_intr_disable(hw, rxq->chan_id); +} + +/*! + * Acknowledge Rx queue interrupt + */ +static int +bcmcnet_pdma_rx_queue_intr_ack(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX) { + return SHR_E_PARAM; + } + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + + return hw->hdls.chan_clear(hw, rxq->chan_id); +} + +/*! + * Query Rx queue interrupt + */ +static int +bcmcnet_pdma_rx_queue_intr_query(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX) { + return SHR_E_PARAM; + } + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + + return hw->hdls.chan_intr_query(hw, rxq->chan_id); +} + +/*! + * Check Rx queue interrupt + */ +static int +bcmcnet_pdma_rx_queue_intr_check(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX) { + return SHR_E_PARAM; + } + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + + return hw->hdls.chan_intr_check(hw, rxq->chan_id); +} + +/*! + * Enable Tx queue interrupt + */ +static int +bcmcnet_pdma_tx_queue_intr_enable(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_tx_queue *txq = NULL; + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + + if (txq->state & PDMA_TX_QUEUE_POLL) { + return SHR_E_NONE; + } else { + return hw->hdls.chan_intr_enable(hw, txq->chan_id); + } +} + +/*! + * Disable Tx queue interrupt + */ +static int +bcmcnet_pdma_tx_queue_intr_disable(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_tx_queue *txq = NULL; + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + + if (txq->state & PDMA_TX_QUEUE_POLL) { + return SHR_E_NONE; + } else { + return hw->hdls.chan_intr_disable(hw, txq->chan_id); + } +} + +/*! + * Acknowledge Tx queue interrupt + */ +static int +bcmcnet_pdma_tx_queue_intr_ack(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_tx_queue *txq = NULL; + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + + return hw->hdls.chan_clear(hw, txq->chan_id); +} + +/*! + * Query Tx queue interrupt + */ +static int +bcmcnet_pdma_tx_queue_intr_query(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_tx_queue *txq = NULL; + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + + return hw->hdls.chan_intr_query(hw, txq->chan_id); +} + +/*! + * Check Tx queue interrupt + */ +static int +bcmcnet_pdma_tx_queue_intr_check(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_tx_queue *txq = NULL; + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + + return hw->hdls.chan_intr_check(hw, txq->chan_id); +} + +/*! + * \brief Device operation functions. + */ +static const struct dev_ops pdma_dev_ops = { + .dev_config = bcmcnet_pdma_config, + .dev_close = bcmcnet_pdma_close, + .dev_suspend = bcmcnet_pdma_suspend, + .dev_resume = bcmcnet_pdma_resume, + .dev_info_get = bcmcnet_pdma_info_get, + .dev_stats_get = bcmcnet_pdma_stats_get, + .dev_stats_reset = bcmcnet_pdma_stats_reset, + .dev_lq_to_pq = bcmcnet_pdma_lq_to_pq, + .dev_pq_to_lq = bcmcnet_pdma_pq_to_lq, + .rx_queue_start = bcmcnet_pdma_rx_queue_start, + .rx_queue_stop = bcmcnet_pdma_rx_queue_stop, + .tx_queue_start = bcmcnet_pdma_tx_queue_start, + .tx_queue_stop = bcmcnet_pdma_tx_queue_stop, + .rx_queue_setup = bcmcnet_pdma_rx_queue_setup, + .rx_queue_release = bcmcnet_pdma_rx_queue_release, + .rx_queue_restore = bcmcnet_pdma_rx_queue_restore, + .rx_vqueue_setup = bcmcnet_pdma_rx_vqueue_setup, + .rx_vqueue_release = bcmcnet_pdma_rx_vqueue_release, + .tx_queue_setup = bcmcnet_pdma_tx_queue_setup, + .tx_queue_release = bcmcnet_pdma_tx_queue_release, + .tx_queue_restore = bcmcnet_pdma_tx_queue_restore, + .tx_vqueue_setup = bcmcnet_pdma_tx_vqueue_setup, + .tx_vqueue_release = bcmcnet_pdma_tx_vqueue_release, + .rx_queue_intr_enable = bcmcnet_pdma_rx_queue_intr_enable, + .rx_queue_intr_disable = bcmcnet_pdma_rx_queue_intr_disable, + .rx_queue_intr_ack = bcmcnet_pdma_rx_queue_intr_ack, + .rx_queue_intr_query = bcmcnet_pdma_rx_queue_intr_query, + .rx_queue_intr_check = bcmcnet_pdma_rx_queue_intr_check, + .tx_queue_intr_enable = bcmcnet_pdma_tx_queue_intr_enable, + .tx_queue_intr_disable = bcmcnet_pdma_tx_queue_intr_disable, + .tx_queue_intr_ack = bcmcnet_pdma_tx_queue_intr_ack, + .tx_queue_intr_query = bcmcnet_pdma_tx_queue_intr_query, + .tx_queue_intr_check = bcmcnet_pdma_tx_queue_intr_check, + .rx_queue_suspend = bcmcnet_pdma_rx_queue_suspend, + .rx_queue_resume = bcmcnet_pdma_rx_queue_resume, + .tx_queue_wakeup = bcmcnet_pdma_tx_queue_wakeup, + .rx_queue_poll = bcmcnet_pdma_rx_queue_poll, + .tx_queue_poll = bcmcnet_pdma_tx_queue_poll, + .group_poll = bcmcnet_pdma_group_poll, +}; + +/*! + * Open a device + */ +int +bcmcnet_pdma_open(struct pdma_dev *dev) +{ + struct pdma_hw *hw = (struct pdma_hw *)dev->ctrl.hw; + struct intr_handle *hdl = NULL; + int chan, gi, qi; + + if (!hw) { + return SHR_E_INIT; + } + + /* Initialize the hardware */ + hw->hdls.hw_reset(hw); + hw->hdls.hw_init(hw); + + if ((uint32_t)dev->num_groups > hw->info.num_cmcs) { + return SHR_E_PARAM; + } + dev->grp_queues = hw->info.cmc_chans; + dev->num_queues = hw->info.num_chans; + dev->rx_ph_size = hw->info.rx_ph_size; + dev->tx_ph_size = hw->info.tx_ph_size; + dev->ctrl.nb_desc = NUM_RING_DESC; + dev->ctrl.budget = NUM_RXTX_BUDGET; + dev->ctrl.rx_desc_size = hw->info.rx_dcb_size; + dev->ctrl.tx_desc_size = hw->info.tx_dcb_size; + + /* Initialize interrupt handler */ + for (chan = 0; chan < dev->num_queues; chan++) { + gi = chan / dev->grp_queues; + qi = chan % dev->grp_queues; + hdl = &dev->ctrl.grp[gi].intr_hdl[qi]; + hdl->unit = dev->unit; + hdl->group = gi; + hdl->chan = chan; + hdl->dev = dev; + hdl->inum = hw->hdls.chan_intr_num_get(hw, chan); + if (hdl->inum < 0) { + return SHR_E_INTERNAL; + } + } + + /* Initialize buffer manager */ + bcmcnet_buf_mngr_init(dev); + + /* Allocate all the queues */ + bcn_rx_queues_alloc(dev); + bcn_tx_queues_alloc(dev); + + dev->pkt_xmit = bcmcnet_pdma_tx_queue_xmit; + + dev->ops = (struct dev_ops *)&pdma_dev_ops; + + return SHR_E_NONE; +} + +/*! + * Coalesce Rx interrupt + */ +int +bcmcnet_pdma_rx_queue_int_coalesce(struct pdma_dev *dev, int queue, int count, int timer) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX || + (uint32_t)queue >= ctrl->nb_rxq) { + return SHR_E_PARAM; + } + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + rxq->intr_coalescing = 1; + rxq->ic_val = (count & 0x7fff) << 16 | (timer & 0xffff); + + return hw->hdls.chan_intr_coalesce(hw, rxq->chan_id, count, timer); +} + +/*! + * Coalesce Tx interrupt + */ +int +bcmcnet_pdma_tx_queue_int_coalesce(struct pdma_dev *dev, int queue, int count, int timer) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_tx_queue *txq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX || + (uint32_t)queue >= ctrl->nb_txq) { + return SHR_E_PARAM; + } + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + txq->intr_coalescing = 1; + txq->ic_val = (count & 0x7fff) << 16 | (timer & 0xffff); + + return hw->hdls.chan_intr_coalesce(hw, txq->chan_id, count, timer); +} + +/*! + * Dump Rx queue registers + */ +int +bcmcnet_pdma_rx_queue_reg_dump(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX || + (uint32_t)queue >= ctrl->nb_rxq) { + return SHR_E_PARAM; + } + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + + return hw->hdls.chan_reg_dump(hw, rxq->chan_id); +} + +/*! + * Dump Tx queue registers + */ +int +bcmcnet_pdma_tx_queue_reg_dump(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_tx_queue *txq = NULL; + + if ((uint32_t)queue >= NUM_Q_MAX || + (uint32_t)queue >= ctrl->nb_txq) { + return SHR_E_PARAM; + } + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + + return hw->hdls.chan_reg_dump(hw, txq->chan_id); +} + diff --git a/src/bcm/common/pktio/bcmcnet/main/bcmcnet_rxtx.c b/src/bcm/common/pktio/bcmcnet/main/bcmcnet_rxtx.c new file mode 100644 index 0000000..7588d51 --- /dev/null +++ b/src/bcm/common/pktio/bcmcnet/main/bcmcnet_rxtx.c @@ -0,0 +1,752 @@ +/*! \file bcmcnet_rxtx.c + * + * Utility routines for BCMCNET Rx/Tx. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include + +/*! + * Free a Rx ring + */ +static void +bcn_rx_ring_free(struct pdma_rx_queue *rxq) +{ + struct dev_ctrl *ctrl = rxq->ctrl; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)ctrl->buf_mngr; + + if (rxq->lock) { + sal_spinlock_destroy(rxq->lock); + rxq->lock = NULL; + } + + if (rxq->ring) { + bm->ring_buf_free(ctrl->dev, ctrl->rx_desc_size * (rxq->nb_desc + 1), + rxq->ring, rxq->ring_addr); + rxq->ring = NULL; + } + + if (rxq->pbuf) { + sal_free(rxq->pbuf); + rxq->pbuf = NULL; + } +} + +/*! + * Allocate a Rx ring + */ +static int +bcn_rx_ring_alloc(struct pdma_rx_queue *rxq) +{ + struct dev_ctrl *ctrl = rxq->ctrl; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)ctrl->buf_mngr; + + /* Setup pktbuf ring */ + rxq->pbuf = sal_alloc(sizeof(*rxq->pbuf) * rxq->nb_desc, "bcmcnetRxBufRing"); + if (!rxq->pbuf) { + goto cleanup; + } + sal_memset(rxq->pbuf, 0, sizeof(*rxq->pbuf) * rxq->nb_desc); + + /* Allocate memory for descriptors */ + rxq->ring = bm->ring_buf_alloc(ctrl->dev, ctrl->rx_desc_size * (rxq->nb_desc + 1), + &rxq->ring_addr); + if (!rxq->ring) { + goto cleanup; + } + sal_memset(rxq->ring, 0, ctrl->rx_desc_size * (rxq->nb_desc + 1)); + + rxq->lock = sal_spinlock_create("bcmcnetRxQueueLock"); + if (!rxq->lock) { + goto cleanup; + } + + return SHR_E_NONE; + +cleanup: + bcn_rx_ring_free(rxq); + + return SHR_E_MEMORY; +} + +/*! + * Free a Tx ring + */ +static void +bcn_tx_ring_free(struct pdma_tx_queue *txq) +{ + struct dev_ctrl *ctrl = txq->ctrl; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)ctrl->buf_mngr; + + if (txq->mutex) { + sal_spinlock_destroy(txq->mutex); + txq->mutex = NULL; + } + + if (txq->lock) { + sal_spinlock_destroy(txq->lock); + txq->lock = NULL; + } + + if (txq->ring) { + bm->ring_buf_free(ctrl->dev, ctrl->tx_desc_size * (txq->nb_desc + 1), + txq->ring, txq->ring_addr); + txq->ring = NULL; + } + + if (txq->pbuf) { + sal_free(txq->pbuf); + txq->pbuf = NULL; + } +} + +/*! + * Allocate a Tx ring + */ +static int +bcn_tx_ring_alloc(struct pdma_tx_queue *txq) +{ + struct dev_ctrl *ctrl = txq->ctrl; + struct pdma_buf_mngr *bm = (struct pdma_buf_mngr *)ctrl->buf_mngr; + + /* Setup pktbuf ring */ + txq->pbuf = sal_alloc(sizeof(*txq->pbuf) * txq->nb_desc, "bcmcnetTxBufRing"); + if (!txq->pbuf) { + goto cleanup; + } + sal_memset(txq->pbuf, 0, sizeof(*txq->pbuf) * txq->nb_desc); + + /* Allocate memory for descriptors */ + txq->ring = bm->ring_buf_alloc(ctrl->dev, ctrl->tx_desc_size * (txq->nb_desc + 1), + &txq->ring_addr); + if (!txq->ring) { + goto cleanup; + } + sal_memset(txq->ring, 0, ctrl->tx_desc_size * (txq->nb_desc + 1)); + + txq->lock = sal_spinlock_create("bcmcnetTxQueueLock"); + if (!txq->lock) { + goto cleanup; + } + + txq->mutex = sal_spinlock_create("bcmcnetTxMutexLock"); + if (!txq->mutex) { + goto cleanup; + } + + return SHR_E_NONE; + +cleanup: + bcn_tx_ring_free(txq); + + return SHR_E_MEMORY; +} + +/*! + * Rx polling + */ +static int +bcn_rx_poll(struct pdma_rx_queue *rxq, int budget) +{ + struct dev_ctrl *ctrl = rxq->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + + return hw->dops.rx_ring_clean(hw, rxq, budget); +} + +/*! + * Tx polling + */ +static int +bcn_tx_poll(struct pdma_tx_queue *txq, int budget) +{ + struct dev_ctrl *ctrl = txq->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + + return hw->dops.tx_ring_clean(hw, txq, budget); +} + +/*! + * Setup a Rx queue + */ +int +bcmcnet_pdma_rx_queue_setup(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + int rv; + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + if (rxq->state & PDMA_RX_QUEUE_SETUP) { + return SHR_E_NONE; + } + + rv = bcn_rx_ring_alloc(rxq); + if (SHR_FAILURE(rv)) { + return rv; + } + + rv = hw->dops.rx_desc_init(hw, rxq); + if (SHR_FAILURE(rv)) { + return rv; + } + + if (dev->mode == DEV_MODE_VNET) { + ctrl->vsync.rx_ring_addr[rxq->chan_id] = rxq->ring_addr; + ctrl->vsync.rx_ring_size[rxq->chan_id] = rxq->nb_desc; + } + + rxq->state |= PDMA_RX_QUEUE_SETUP; + + return SHR_E_NONE; +} + +/*! + * Release a Rx queue + */ +int +bcmcnet_pdma_rx_queue_release(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + if (rxq->state & PDMA_RX_QUEUE_SETUP) { + hw->dops.rx_desc_clean(hw, rxq); + bcn_rx_ring_free(rxq); + rxq->state &= ~PDMA_RX_QUEUE_SETUP; + } + + return SHR_E_NONE; +} + +/*! + * Restore a Rx queue + */ +int +bcmcnet_pdma_rx_queue_restore(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + if (rxq->state & PDMA_RX_QUEUE_SETUP) { + hw->dops.rx_desc_init(hw, rxq); + } + + return SHR_E_NONE; +} + +/*! + * Set up a virtual Rx queue + */ +int +bcmcnet_pdma_rx_vqueue_setup(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_rx_queue *vrxq = NULL; + + vrxq = (struct pdma_rx_queue *)ctrl->vnet_rxq[queue]; + if (vrxq->state & PDMA_RX_QUEUE_SETUP) { + return SHR_E_NONE; + } + + if (dev->ctrl.vsync.rx_ring_addr[vrxq->chan_id]) { + vrxq->curr = 0; + vrxq->nb_desc = dev->ctrl.vsync.rx_ring_size[vrxq->chan_id]; + vrxq->ring_addr = dev->ctrl.vsync.rx_ring_addr[vrxq->chan_id]; + vrxq->ring = dev->sys_p2v(dev, vrxq->ring_addr); + vrxq->state |= PDMA_RX_QUEUE_SETUP; + } + + return SHR_E_NONE; +} + +/*! + * Release a virtual Rx queue + */ +int +bcmcnet_pdma_rx_vqueue_release(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_rx_queue *vrxq = NULL; + + vrxq = (struct pdma_rx_queue *)ctrl->vnet_rxq[queue]; + if (vrxq->state & PDMA_RX_QUEUE_SETUP) { + vrxq->state &= ~PDMA_RX_QUEUE_SETUP; + vrxq->ring = NULL; + } + + return SHR_E_NONE; +} + +/*! + * Setup a Tx queue + */ +int +bcmcnet_pdma_tx_queue_setup(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_tx_queue *txq = NULL; + int rv; + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + if (txq->state & PDMA_TX_QUEUE_SETUP) { + return SHR_E_NONE; + } + + rv = bcn_tx_ring_alloc(txq); + if (SHR_FAILURE(rv)) { + return rv; + } + + rv = hw->dops.tx_desc_init(hw, txq); + if (SHR_FAILURE(rv)) { + return rv; + } + + if (dev->mode == DEV_MODE_VNET) { + ctrl->vsync.tx_ring_addr[txq->chan_id] = txq->ring_addr; + ctrl->vsync.tx_ring_size[txq->chan_id] = txq->nb_desc; + } + + txq->state |= PDMA_TX_QUEUE_SETUP; + + return SHR_E_NONE; +} + +/*! + * Release a Tx queue + */ +int +bcmcnet_pdma_tx_queue_release(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_tx_queue *txq = NULL; + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + if (txq->state & PDMA_TX_QUEUE_SETUP) { + hw->dops.tx_desc_clean(hw, txq); + bcn_tx_ring_free(txq); + txq->state &= ~PDMA_TX_QUEUE_SETUP; + } + + return SHR_E_NONE; +} + +/*! + * Restore a Tx queue + */ +int +bcmcnet_pdma_tx_queue_restore(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_tx_queue *txq = NULL; + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + if (txq->state & PDMA_TX_QUEUE_SETUP) { + hw->dops.tx_desc_init(hw, txq); + } + + return SHR_E_NONE; +} + +/*! + * Set up a virtual Tx queue + */ +int +bcmcnet_pdma_tx_vqueue_setup(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_tx_queue *vtxq = NULL; + + vtxq = (struct pdma_tx_queue *)ctrl->vnet_txq[queue]; + if (vtxq->state & PDMA_TX_QUEUE_SETUP) { + return SHR_E_NONE; + } + + if (dev->ctrl.vsync.tx_ring_addr[vtxq->chan_id]) { + vtxq->curr = 0; + vtxq->dirt = 0; + vtxq->nb_desc = dev->ctrl.vsync.tx_ring_size[vtxq->chan_id]; + vtxq->ring_addr = dev->ctrl.vsync.tx_ring_addr[vtxq->chan_id]; + vtxq->ring = dev->sys_p2v(dev, vtxq->ring_addr); + vtxq->state |= PDMA_TX_QUEUE_SETUP; + } + + return SHR_E_NONE; +} + +/*! + * Release a virtual Tx queue + */ +int +bcmcnet_pdma_tx_vqueue_release(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_tx_queue *vtxq = NULL; + + vtxq = (struct pdma_tx_queue *)ctrl->vnet_txq[queue]; + if (vtxq->state & PDMA_TX_QUEUE_SETUP) { + vtxq->state &= ~PDMA_TX_QUEUE_SETUP; + vtxq->ring = NULL; + } + + return SHR_E_NONE; +} + +/*! + * Suspend a Rx queue + */ +int +bcmcnet_pdma_rx_queue_suspend(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + if (!rxq || !(rxq->state & PDMA_RX_QUEUE_ACTIVE)) { + return SHR_E_UNAVAIL; + } + + return hw->dops.rx_suspend(hw, rxq); +} + +/*! + * Resume a Rx queue + */ +int +bcmcnet_pdma_rx_queue_resume(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + if (!rxq || !(rxq->state & PDMA_RX_QUEUE_ACTIVE)) { + return SHR_E_UNAVAIL; + } + + return hw->dops.rx_resume(hw, rxq); +} + +/*! + * Suspend a Tx queue + */ +int +bcmcnet_pdma_tx_queue_suspend(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_tx_queue *txq = NULL; + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + if (!txq || !(txq->state & PDMA_TX_QUEUE_ACTIVE)) { + return SHR_E_UNAVAIL; + } + + if (txq->sem) { + sal_sem_take(txq->sem, SAL_SEM_FOREVER); + } + if (dev->tx_suspend) { + dev->tx_suspend(dev, txq->queue_id); + } + + return SHR_E_NONE; +} + +/*! + * Resume a Tx queue + */ +int +bcmcnet_pdma_tx_queue_resume(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_tx_queue *txq = NULL; + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + if (!txq || !(txq->state & PDMA_TX_QUEUE_ACTIVE)) { + return SHR_E_UNAVAIL; + } + + if (txq->sem) { + sal_sem_give(txq->sem); + } + if (dev->tx_resume) { + dev->tx_resume(dev, txq->queue_id); + } + + return SHR_E_NONE; +} + +/*! + * Wake up a Tx queue + */ +int +bcmcnet_pdma_tx_queue_wakeup(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_tx_queue *txq = NULL; + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + if (txq->sem) { + sal_sem_give(txq->sem); + } + + return SHR_E_NONE; +} + +/*! + * Transmit a outputing packet + */ +int +bcmcnet_pdma_tx_queue_xmit(struct pdma_dev *dev, int queue, void *buf) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_tx_queue *txq = NULL; + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + if (!txq || (!(txq->state & PDMA_TX_QUEUE_ACTIVE) && !dev->suspended)) { + return SHR_E_DISABLED; + } + + return hw->dops.pkt_xmit(hw, txq, buf); +} + +/*! + * Poll a Rx queues + */ +int +bcmcnet_pdma_rx_queue_poll(struct pdma_dev *dev, int queue, int budget) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_rx_queue *rxq = ctrl->rx_queue[queue]; + + return bcn_rx_poll(rxq, budget); +} + +/*! + * Poll a Tx queues + */ +int +bcmcnet_pdma_tx_queue_poll(struct pdma_dev *dev, int queue, int budget) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_tx_queue *txq = ctrl->tx_queue[queue]; + + return bcn_tx_poll(txq, budget); +} + +/*! + * Poll for Rx/Tx queues in a group + */ +int +bcmcnet_pdma_group_poll(struct pdma_dev *dev, int group, int budget) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + struct pdma_tx_queue *txq = NULL; + struct queue_group *grp = &ctrl->grp[group]; + uint32_t intr_actives = 0; + int rx_done = 0, tx_done = 0, done_que, budget_que; + int i; + + /* Acknowledge the interrupts */ + for (i = 0; i < dev->grp_queues; i++) { + rxq = grp->rx_queue[i]; + if (rxq->state & PDMA_RX_QUEUE_ACTIVE) { + if (hw->hdls.chan_intr_query(hw, rxq->chan_id)) { + hw->hdls.chan_clear(hw, rxq->chan_id); + grp->poll_queues |= 1 << i; + intr_actives |= 1 << i; + } + if (rxq->state & PDMA_RX_QUEUE_BUSY) { + rxq->state &= ~PDMA_RX_QUEUE_BUSY; + grp->poll_queues |= 1 << i; + } + continue; + } + txq = grp->tx_queue[i]; + if (txq->state & PDMA_TX_QUEUE_ACTIVE) { + if (hw->hdls.chan_intr_query(hw, txq->chan_id)) { + hw->hdls.chan_clear(hw, txq->chan_id); + grp->poll_queues |= 1 << i; + intr_actives |= 1 << i; + } + if (txq->state & PDMA_TX_QUEUE_BUSY) { + txq->state &= ~PDMA_TX_QUEUE_BUSY; + grp->poll_queues |= 1 << i; + } + } + } + + /* Calculate per queue budget */ + if (!grp->poll_queues) { + grp->poll_queues = grp->bm_rxq | grp->bm_txq; + budget_que = budget / grp->nb_rxq; + } else { + budget_que = 0; + for (i = 0; i < dev->grp_queues; i++) { + if (1 << i & grp->bm_rxq & grp->poll_queues) { + budget_que++; + } + } + if (budget_que) { + budget_que = budget / budget_que; + } + } + + /* Poll Rx queues */ + for (i = 0; i < dev->grp_queues; i++) { + if (1 << i & grp->bm_rxq & grp->poll_queues) { + rxq = grp->rx_queue[i]; + done_que = bcn_rx_poll(rxq, budget_que); + if (done_que >= budget_que || + (done_que == 0 && (1 << i & intr_actives))) { + continue; + } + grp->poll_queues &= ~(1 << i); + rx_done += done_que; + } + } + + /* Poll Tx queues */ + for (i = 0; i < dev->grp_queues; i++) { + txq = grp->tx_queue[i]; + if (1 << i & grp->bm_txq & grp->poll_queues && !txq->free_thresh) { + done_que = bcn_tx_poll(txq, budget); + if (done_que >= budget || + (done_que == 0 && (1 << i & intr_actives))) { + continue; + } + grp->poll_queues &= ~(1 << i); + tx_done += done_que; + } + } + + /* Reschedule the poll if not completed */ + if (grp->poll_queues) { + return budget; + } + + /* Check channel status before exits */ + if (hw->hdls.chan_check) { + for (i = 0; i < dev->grp_queues; i++) { + rxq = grp->rx_queue[i]; + if (rxq->state & PDMA_RX_QUEUE_ACTIVE) { + if (hw->hdls.chan_check(hw, rxq->chan_id)) { + hw->hdls.chan_clear(hw, rxq->chan_id); + grp->poll_queues |= 1 << i; + } + continue; + } + txq = grp->tx_queue[i]; + if (txq->state & PDMA_TX_QUEUE_ACTIVE) { + if (hw->hdls.chan_check(hw, txq->chan_id)) { + hw->hdls.chan_clear(hw, txq->chan_id); + grp->poll_queues |= 1 << i; + } + } + } + return grp->poll_queues ? budget : rx_done; + } else { + return (rx_done + tx_done) ? budget : 0; + } +} + +/*! + * Dump a Rx ring + */ +int +bcmcnet_pdma_rx_ring_dump(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = ctrl->hw; + struct pdma_rx_queue *rxq = NULL; + + if ((uint32_t)queue >= ctrl->nb_rxq) { + return SHR_E_PARAM; + } + + rxq = (struct pdma_rx_queue *)ctrl->rx_queue[queue]; + if (rxq->state & PDMA_RX_QUEUE_ACTIVE) { + hw->dops.rx_ring_dump(hw, rxq); + } + if (dev->mode == DEV_MODE_HNET) { + rxq = (struct pdma_rx_queue *)ctrl->vnet_rxq[queue]; + if (rxq->state & PDMA_RX_QUEUE_SETUP) { + hw->dops.rx_ring_dump(hw, rxq); + } + } + + return SHR_E_NONE; +} + +/*! + * Dump a Tx ring + */ +int +bcmcnet_pdma_tx_ring_dump(struct pdma_dev *dev, int queue) +{ + struct dev_ctrl *ctrl = &dev->ctrl; + struct pdma_hw *hw = ctrl->hw; + struct pdma_tx_queue *txq = NULL; + + if ((uint32_t)queue >= ctrl->nb_txq) { + return SHR_E_PARAM; + } + + txq = (struct pdma_tx_queue *)ctrl->tx_queue[queue]; + if (txq->state & PDMA_TX_QUEUE_ACTIVE) { + hw->dops.tx_ring_dump(hw, txq); + } + if (dev->mode == DEV_MODE_HNET) { + txq = (struct pdma_tx_queue *)ctrl->vnet_txq[queue]; + if (txq->state & PDMA_TX_QUEUE_SETUP) { + hw->dops.tx_ring_dump(hw, txq); + } + } + + return SHR_E_NONE; +} + diff --git a/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd.h b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd.h new file mode 100644 index 0000000..2bd0b6f --- /dev/null +++ b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd.h @@ -0,0 +1,370 @@ +/*! \file bcmdrd.h + * + * External BCMDRD Device API. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMDRD_H +#define BCMDRD_H + +#include +#include + +/*! + * \brief Device identification structure. + * + * This information defines a specific device variant, and the + * information used to configure device drivers and features. + */ +typedef struct bcmdrd_dev_id_s { + + /*! Vendor ID (typically PCI vendor ID.) */ + uint16_t vendor_id; + + /*! Device ID (typically PCI device ID.) */ + uint16_t device_id; + + /*! Device revision (used to determine device features.) */ + uint16_t revision; + + /*! Additional identification (in case of ambiguous device IDs.) */ + uint16_t model; + +} bcmdrd_dev_id_t; + +/*! Device license type. */ +typedef enum bcmdrd_dev_license_type_e { + + /*! HLA (Hardware License Authenticator). */ + BCMDRD_DEV_LICENSE_TYPE_HLA = 0, + + /*! Number of license types. */ + BCMDRD_DEV_LICENSE_TYPE_COUNT + +} bcmdrd_dev_license_type_t; + +/*! + * \brief Device license structure. + * + * This structure contains pointers to a license file and an optional + * secure application image. The license file may contain hardware license + * (which allows hardware features to be enabled) or software license + * (which allows the secure application to be executed). If an application + * image is specified, the license file must contain the corresponding + * software license. The application will be automatically executed once + * the license file is authenticated. Optional arguments to be used + * by the application can also be supplied in the structure. + */ +typedef struct bcmdrd_dev_license_info_s { + + /*! License type. */ + bcmdrd_dev_license_type_t license_type; + + /*! Size of the license file in bytes. */ + size_t license_size; + + /*! Pointer to the license file byte array. */ + void *license_data; + + /*! Size of the secure application image in bytes. */ + size_t appl_size; + + /*! Pointer to the secure application image byte array. */ + void *appl_data; + + /*! Number of the secure application argument words. */ + size_t appl_argc; + + /*! Pointer to the secure application argument word array. */ + uint32_t *appl_argv; + +} bcmdrd_dev_license_info_t; + +/*! + * \brief Check if a device type is supported. + * + * \param [in] id Device ID structure. + * + * \return true if supported, otherwise false. + */ +extern bool +bcmdrd_dev_supported(bcmdrd_dev_id_t *id); + +/*! + * \brief Destroy a device. + * + * Remove a device from the DRD and free all associated resources. + * + * \param [in] unit Unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_INIT Device already destroyed (or never created). + */ +extern int +bcmdrd_dev_destroy(int unit); + +/*! + * \brief Create a device. + * + * Create a device in the DRD. This is a mandatory operation before + * any other operation can be performed on the device. + * + * If a negative unit number is passed in, then the first available + * unit number will be used. If no more unit numbers are available, + * the function will return SHR_E_FULL. + * + * \param [in] unit Unit number. + * \param [in] id Device ID structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_FULL No available unit numbers. + * \retval SHR_E_EXIST Device with this unit number already exists. + * \retval SHR_E_NOT_FOUND Device type not supported. + */ +extern int +bcmdrd_dev_create(int unit, bcmdrd_dev_id_t *id); + +/*! + * \brief Set first auto-unit number. + * + * Specify the first unit number to assign when -1 is passed as the + * unit number to \ref bcmdrd_dev_create. This is mainly intended as a + * tool for testing non-zero unit numbers on a single-unit system. + * + * \param [in] unit First auto-unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_first_auto_unit_set(int unit); + +/*! + * \brief Check if device exists. + * + * Check if a device has been created. + * + * \param [in] unit Unit number. + * + * \return true if device exists, otherwose false. + */ +extern bool +bcmdrd_dev_exists(int unit); + +/*! + * \brief Get device type. + * + * Get device type, which is an enumeration of all supported devices. + * + * \param [in] unit Unit number. + * + * \retval Device type. + */ +extern bcmdrd_dev_type_t +bcmdrd_dev_type(int unit); + +/*! + * \brief Get device type as a string. + * + * Get the device type as an ASCII string. If device does not exist, + * an empty string ("") is returned. + * + * The device type string corresponds to the device type returned by + * \ref bcmdrd_dev_type. + * + * \param [in] unit Unit number. + * + * \return Pointer to base device name. + */ +extern const char * +bcmdrd_dev_type_str(int unit); + +/*! + * \brief Get device revision string. + * + * Get a device revision string for use in the CLI. If device does not + * exist, an empty string ("") is returned. + * + * \param [in] unit Unit number. + * + * \return Pointer to device revision string. + */ +extern const char * +bcmdrd_dev_rev_str(int unit); + +/*! + * \brief Get device name. + * + * Get the official device (SKU) name. If device does not exist, an + * empty string ("") is returned. + * + * \param [in] unit Unit number. + * + * \return Pointer to device name. + */ +extern const char * +bcmdrd_dev_name(int unit); + +/*! + * \brief Get device identification information. + * + * \param [in] unit Unit number. + * \param [out] id Pointer to device identification structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_NOT_FOUND Device type not supported. + */ +extern int +bcmdrd_dev_id_get(int unit, bcmdrd_dev_id_t *id); + +/*! + * \brief Get ID structure for a given device name. + * + * Given a device name string, this API will look for a matching ID + * structure in the list of supported devices. + * + * Mainly intended for testing and debugging. + * + * \param [in] dev_name Device name, e.g. "bcm56800_a0". + * \param [out] id ID structure to be filled + * + * \retval SHR_E_NONE Match was found and ID structure was filled. + * \retval SHR_E_NOT_FOUND No match was found. + */ +extern int +bcmdrd_dev_id_from_name(const char *dev_name, bcmdrd_dev_id_t *id); + +/*! + * \brief Check is the device is variant SKU. + * + * \param [in] unit Unit number. + * + * \retval true The unit is variant SKU. + * \retval false The unit is base SKU. + */ +extern bool +bcmdrd_dev_is_variant_sku(int unit); + +/*! + * \brief Assign I/O resources to a device. + * + * I/O resources can be assigned either as one or more physical + * addresses of memory-mappable register windows, or as a set of + * system-provided register access functions. + * + * If physical I/O memory addresses are provided, then functions for + * mapping and unmapping I/O registers must be provided as well. + * + * \param [in] unit Unit number. + * \param [in] io I/O reousrce structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_NOT_FOUND Device does not exist. + */ +extern int +bcmdrd_dev_hal_io_init(int unit, bcmdrd_hal_io_t *io); + +/*! + * \brief Retrieve configured I/O resources for a device. + * + * Read back the I/O resource structure supplied via \ref + * bcmdrd_dev_hal_io_init. + * + * This API is mainly for diagnostic purposes. + * + * \param [in] unit Unit number. + * \param [out] io I/O reousrce structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_NOT_FOUND Device does not exist. + */ +extern int +bcmdrd_dev_hal_io_get(int unit, bcmdrd_hal_io_t *io); + +/*! + * \brief Assign DMA resources to a device. + * + * DMA resources are required for a number of device operations, and + * to make this possible, the system must provide functions for + * allocating and freeing DMA memory. + * + * \param [in] unit Unit number. + * \param [in] dma DMA resource structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_NOT_FOUND Device does not exist. + */ +extern int +bcmdrd_dev_hal_dma_init(int unit, bcmdrd_hal_dma_t *dma); + +/*! + * \brief Assign interrupt control API to a device. + * + * Allow the SDK to connect an interrupt handler to a hardwrae + * interrupt. + * + * \param [in] unit Unit number. + * \param [in] intr Interrupt control API structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_NOT_FOUND Device does not exist. + */ +extern int +bcmdrd_dev_hal_intr_init(int unit, bcmdrd_hal_intr_t *intr); + +/*! + * \brief Add device license. + * + * A device license is used to enable optional switch features and + * is applied during switch initialization. + * + * \param [in] unit Unit number. + * \param [in] license Device license structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Invalid license data. + * \retval SHR_E_MEMORY Insufficient memory to store license. + * \retval SHR_E_RESOURCE Maximum number of licenses exceeded. + * \retval SHR_E_UNAVAIL Unsupported license type. + */ +extern int +bcmdrd_dev_license_add(int unit, bcmdrd_dev_license_info_t *license); + +#endif /* BCMDRD_H */ diff --git a/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_chip.h b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_chip.h new file mode 100644 index 0000000..c99bf3f --- /dev/null +++ b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_chip.h @@ -0,0 +1,852 @@ +/*! \file bcmdrd_chip.h + * + * DRD APIs that operate on the chip_info structure. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMDRD_CHIP_H +#define BCMDRD_CHIP_H + +#include + +#include + +/*! Check if unit number is within the DRD supported range. */ +#define BCMDRD_UNIT_VALID(_u) ((unsigned int)(_u) < BCMDRD_CONFIG_MAX_UNITS) + +/*! Check if port number is within the DRD supported range. */ +#define BCMDRD_PORT_VALID(_p) ((unsigned int)(_p) < BCMDRD_CONFIG_MAX_PORTS) + +/*! + * \name Common chip flags. + * \anchor BCMDRD_CHIP_FLAG_xxx + */ + +/*! \{ */ + +/*! Indicates that the chip is a variant SKU, i.e. not a base device SKU. */ +#define BCMDRD_CHIP_FLAG_VARIANT 0x1 + +/*! Mask of common chip flags. */ +#define BCMDRD_CHIP_FLAG_MASK 0xffff + +/*! \} */ + +/*! + * \brief Block information structure. + * + * This structure will be auto-generated for each physical block in + * the device. + */ +typedef struct bcmdrd_block_s { + + /*! Block type */ + int type; + + /*! Physical block number */ + int blknum; + + /*! Port Bitmaps */ + bcmdrd_pbmp_t pbmps; + +} bcmdrd_block_t; + +/*! + * \brief Port-block information structure. + * + * This structure is used to extract detailed port and block + * information ofr a given port and block type. + */ +typedef struct bcmdrd_pblk_s { + + /*! Block type */ + int type; + + /*! Block type instance */ + int inst; + + /*! Physical Block Number */ + int blknum; + + /*! Port number within this block */ + int lane; + +} bcmdrd_pblk_t; + +/*! + * \brief Address calculation function for registers and memories. + * + * Used to override the default address calculation for a particular + * Host Management Interface (HMI). + * + * A typical use case is transitional devices, which use a new CMIC + * register interface, but retain the S-channel protocol of the + * previous CMIC version. Subsequent devices will also use a new + * S-channel protocol, so the address calculation of the transitional + * device(s) must be treated as an exception. + * + * \param [in] block Block number. + * \param [in] port Port number for block context. + * \param [in] offset Base address for register/memory. + * \param [in] idx Entry number for array-based register/memory. + * + * \return Lower 32-bit of register/memory address. + */ +typedef uint32_t (*bcmdrd_block_port_addr_f)(int block, int port, + uint32_t offset, uint32_t idx); + +/*! + * \brief Valid array indexes for a set of ports. + * + * This structure is a building block for constructing a complete + * definition of which indexes are valid for port-based register + * arrays. + * + * Please refer to \ref bcmdrd_numel_info_t for details. + */ +typedef struct bcmdrd_numel_range_s { + + /*! Array index minimum. */ + int min; + + /*! Array index maximum. */ + int max; + + /*! Ports for which index range is valid. */ + bcmdrd_pbmp_t pbmp; + +} bcmdrd_numel_range_t; + +/*! + * \brief Set of valid port/index ranges for a register. + * + * A set of valid port/index ranges is referred to as an + * encoding. Several registers may share the same encoding. + * + * Please refer to \ref bcmdrd_numel_info_t for details. + */ +typedef struct bcmdrd_numel_encoding_s { + + /*! List of range IDs, -1 marks end of list. */ + int range_id[8]; + +} bcmdrd_numel_encoding_t; + +/*! + * \brief Information for register arrays with per-port variable size. + * + * Since register arrays often have identical or similar per-port + * arrays sizes, this information is stored as shared encodings + * defined by two tables per chip. + * + * Each entry in the first table defines an index range and an + * associated set of ports. Entries in this table are referenced by a + * range ID which is simply the table index (first entry is range + * with ID 0, etc.) + * + * Each entry in the second table is a list of range IDs that defines + * the encoding for one or more registers. + * + * An encoding is defined as an index into the second table. Note that + * encoding 0 is reserved because the first entry of the second table + * contains the size of the table itself. + */ +typedef struct bcmdrd_numel_info_s { + + /*! Table of all index ranges for this chip. */ + bcmdrd_numel_range_t *chip_ranges; + + /*! Table of register array encodings for this chip. */ + bcmdrd_numel_encoding_t *encodings; + +} bcmdrd_numel_info_t; + +/*! + * \brief Chip parameter. + * + * Chip parameters are used to describe differences between a base + * device and a device variant (SKU). + * + * The parameter names are device-specific in nature, but different + * device types should ideally use the same name for the same device + * variant attribute. + */ +typedef struct bcmdrd_chip_param_s { + + /*! Chip parameter name. */ + char *name; + + /*! Chip parameter value. */ + uint32_t value; + +} bcmdrd_chip_param_t; + +/*! + * \brief Chip override value. + * + * Chip override values are used to override default values for a + * given device variant. + * + * Overrides are typically used for reduced SOC memory sizes, but they + * can also be used to mark a given symbol as non-existent in a given + * device variant. + */ +typedef struct bcmdrd_chip_override_s { + + /*! Indicates whether a given override value is active or not. */ + bool override; + + /*! Value to be used instead of the default value. */ + uint32_t value; + +} bcmdrd_chip_override_t; + +/*! + * \brief Chip modifier object. + * + * The chip modifier object is used to override one or more attributes + * of a device symbol (register/memory). + * + * Each override attribute has a flag to indicate whether the override + * is active or not. + */ +typedef struct bcmdrd_chip_mod_s { + + /*! Symbol ID. */ + bcmdrd_sid_t sid; + + /*! Optionally mark symbol as invalid (non-existent). */ + bcmdrd_chip_override_t valid; + + /*! Override default SOC memory size. */ + bcmdrd_chip_override_t index_max; + +} bcmdrd_chip_mod_t; + +/*! + * \brief Chip profile. + * + * The chip profile describes how a device variant (SKU) differs from + * the base device. + * + * Note that the list of valid ports for a given variant is not part + * of the chip profile, since it is part of the fixed chip information + * for each device variant. + */ +typedef struct bcmdrd_chip_profile_s { + + /*! Chip parameters. */ + bcmdrd_chip_param_t *params; + + /*! Symbol modifiers. */ + bcmdrd_chip_mod_t *mods; + +} bcmdrd_chip_profile_t; + +/*! Information for query multi-pipe XGS devices. */ +typedef struct bcmdrd_pipe_info_s { + + /*! Base offset (fixed address information). */ + uint32_t offset; + + /*! Access type (device-specific). */ + uint32_t acctype; + + /*! Block type (device-specific). */ + uint32_t blktype; + + /*! Base index (interpreted according to base type). */ + int baseidx; + + /*! Port number (required when querying for pipe index). */ + int port; + + /*! Pipe instance (required when querying for sub-pipe map). */ + int pipe_inst; + + /*! Sub-pipe instance (required when querying for sub-pipe map). */ + int subpipe_inst; + + /*! Port number domain (required when querying for pipe index). */ + bcmdrd_port_num_domain_t pnd; + + /*! Bitmap of valid pipes (legacy format - 32 pipes only). */ + uint32_t pipe_map; + + /*! Bitmap of valid pipes (input). */ + bcmdrd_pipemap_t pipemap_in; + + /*! Bitmap of valid pipes (output). */ + bcmdrd_pipemap_t pipemap_out; + + /*! Memory index (required when querying for memories index validation). */ + int memidx; + + /*! + * Maximum memory index (required when querying for memories index + * validation). + */ + int memidx_max; + +} bcmdrd_pipe_info_t; + +/*! Specified Key of information query of multi-pipe XGS devices. */ +typedef enum bcmdrd_pipe_info_type_e { + + /*! + * Query pipe instance bit map of access type UNIQUE for specified + * block type. + */ + BCMDRD_PIPE_INFO_TYPE_PMASK, + + /*! + * Query number of base type instances for specified block + * type. + */ + BCMDRD_PIPE_INFO_TYPE_LINST, + + /*! + * Query section size as log2(n) for specified block type and base + * type (derived from base address), e.g. 3=>8, 5=>32. Exception + * is 0=>0. + */ + BCMDRD_PIPE_INFO_TYPE_SECT_SHFT, + + /*! + * Query pipe instance bit map of access type UNIQUE for the + * specified base index. + */ + BCMDRD_PIPE_INFO_TYPE_BASETYPE_PMASK, + + /*! + * Query pipe instance bit map of access type SINGLE for the + * specified base index. This information is needed when the base + * type instances partially exist, e.g. in half-chip mode. + */ + BCMDRD_PIPE_INFO_TYPE_BASETYPE_SINGLE_PMASK, + + /*! + * Query global access type value for pipes with access type + * UNIQUE. + */ + BCMDRD_PIPE_INFO_TYPE_AT_UNIQUE_GLOBAL, + + /*! + * Query if a specified base index is invalid. + */ + BCMDRD_PIPE_INFO_TYPE_BASEIDX_INVALID, + + /*! + * Query the number of pipe instances for the specified block + * type. + */ + BCMDRD_PIPE_INFO_TYPE_NUM_PIPE_INST, + + /*! + * Query the pipe index for the specified port. + */ + BCMDRD_PIPE_INFO_TYPE_PIPE_INDEX_FROM_PORT, + + /*! + * Query the pipe map of block from device. + */ + BCMDRD_PIPE_INFO_TYPE_BLK_PIPE_MAP, + + /*! + * Return the pipe number of block type \c blktype that + * corresponds to the device pipe number provided in \c + * pipe_inst. If no translation exists for the device pipe number, + * the device pipe number should be returned (even if the device + * pipe number is invalid). + */ + BCMDRD_PIPE_INFO_TYPE_BLK_PIPE, + + /*! + * Query the physical device pipe map associated with the specified + * pipe instance and sub-pipe instance. + */ + BCMDRD_PIPE_INFO_TYPE_SUBPIPE_MAP, + + /*! + * Query if a specified memory index is invalid. + */ + BCMDRD_PIPE_INFO_TYPE_MEMIDX_INVALID, + +} bcmdrd_pipe_info_type_t; + +/*! + * \brief SBUS Address decoding function. + * + * \param [in] symbol Candidate symbol for address decoding. + * \param [in] block Block number. + * \param [in] addr Chip-specific SBUS address beat. + * \param [in] idx Entry number for array-based register/memory. + * \param [in] lane Port number for block context. + * + * \retval 0 on success, -1 on failure. + */ +typedef int (*bcmdrd_addr_decode_f)(const bcmdrd_symbol_t *symbol, + int block, uint32_t addr, + uint32_t *idx, uint32_t *lane); + +/*! + * \brief Fixed chip information. + */ +typedef struct bcmdrd_chip_info_s { + + /*! Optional register file digest. */ + const char *signature; + + /*! HMI protocol (typically S-bus address format version). */ + int hmi_proto; + + /*! HMI block (typically CMIC block number). */ + int hmi_block; + + /*! Number other (non-CMIC) block types. */ + int nblktypes; + + /*! Other (non-CMIC) block types. */ + const char **blktype_names; + + /*! Number of blocks of other (non-CMIC) block types. */ + const int *blktype_numblks; + + /*! + * Index of first block of given block type in the blocks array + * below. This can be used to optimize block search performance + * for devices with many (port) blocks. + */ + const int *blktype_start_idx; + + /*! Number of block structures. */ + int nblocks; + + /*! Block structure array. */ + const bcmdrd_block_t *blocks; + + /*! Valid ports for this chip. */ + bcmdrd_pbmp_t valid_pbmps[BCMDRD_PND_COUNT]; + + /*! + * Chip Flags. + * + * Lower 16 bits are generic flags (see \ref BCMDRD_CHIP_FLAG_xxx). + * Upper 16 bits are chip-specific, e.g. for controlling bond-options. + */ + uint32_t flags; + +#if BCMDRD_CONFIG_INCLUDE_CHIP_SYMBOLS == 1 + /*! Chip symbol table pointer. */ + const bcmdrd_symbols_t *symbols; +#endif + + /*! Variable size register arrays. */ + bcmdrd_numel_info_t *numel_info; + + /*! Symbol overrides and other configuration attributes. */ + bcmdrd_chip_profile_t *profile; + + /*! Offset/Address Vectors. */ + bcmdrd_block_port_addr_f block_port_addr; + + /*! Decode Address to symbol information */ + bcmdrd_addr_decode_f addr_decode; + + /*! Get port number domain for a register/memory. */ + bcmdrd_port_num_domain_t (*port_num_domain)(bcmdrd_sid_t sid, int blktype); + + /*! Get device-specific block type from genenraic port type. */ + int (*blktype_from_porttype)(bcmdrd_port_type_t ptype); + + /*! Get pipe info of this chip. */ + uint32_t (*pipe_info)(const struct bcmdrd_chip_info_s *cinfo, + bcmdrd_pipe_info_t *pi, + bcmdrd_pipe_info_type_t pi_type); + +} bcmdrd_chip_info_t; + +/*! + * \brief Calculate port block information. + * + * This function is used to calculated the port block information + * (\ref bcmdrd_pblk_t) based on the top-level port number and the + * block type. + * + * The input is typically retrieved from the DRD along with a dynamic + * top-level port number, and the output is the parameters needed to + * perform the associated CMIC S-channel access (block number and port + * block lane number). + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] port Top-level port number. + * \param [in] blktype Device-specific block type (GPORT, XLPORT, etc.). + * \param [out] pblk Port block information. + * + * \return 0 if no errors, otherwise -1. + */ +extern int +bcmdrd_chip_port_block(const bcmdrd_chip_info_t *cinfo, + int port, int blktype, bcmdrd_pblk_t *pblk); + +/*! + * \brief Calculate top-level port number. + * + * This function is used to get the top-level port number from + * block number and the port number within the block. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] blknum Device-specififc block number. + * \param [in] lane Port number within this block. + * + * \return Top-level port number if no errors, otherwise -1. + */ +extern int +bcmdrd_chip_port_number(const bcmdrd_chip_info_t *cinfo, int blknum, int lane); + +/*! + * \brief Get block structure from type and instance. + * + * Given a block type and an instance number of that block type, this + * function will return the corresponding block structure \ref bcmdrd_block_t. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] blktype Block type. + * \param [in] blkinst Instance number for block type. + * + * \return Pointer to block structure, or NULL if no matching block is found. + */ +const bcmdrd_block_t * +bcmdrd_chip_block(const bcmdrd_chip_info_t *cinfo, int blktype, int blkinst); + +/*! + * \brief Get block number from type and instance. + * + * Given a block type and an instance number of that block type, this + * function will return the corresponding physical block number. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] blktype Block type. + * \param [in] blkinst Instance number for block type. + * + * \return Physical block number, or -1 if no matching block is found. + */ +extern int +bcmdrd_chip_block_number(const bcmdrd_chip_info_t *cinfo, + int blktype, int blkinst); + +/*! + * \brief Get number of block instances from block type. + * + * This function will return the number of block instances for a given + * block type. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] blktype Block type. + * + * \return Number of block instances, or -1 if no matching block type is found. + */ +extern int +bcmdrd_chip_num_block_inst(const bcmdrd_chip_info_t *cinfo, int blktype); + +/*! + * \brief Get port bitmap for a block type. + * + * Given a block type, return a port bitmap (\ref bcmdrd_pbmp_t) of + * all ports belonging to blocks of this type. + * + * Typically used to get a list of ports of a particular type, + * e.g. XLPORT ports. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] blktype Block type. + * \param [out] pbmp Destination port bitmap. + * + * \retval 0 No errors. + * \retval -1 Invalid parameter. + */ +extern int +bcmdrd_chip_blktype_pbmp(const bcmdrd_chip_info_t *cinfo, int blktype, + bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Get block type and block instance from block number. + * + * This function calculates block type and block instance from a given + * physical block number. If \c blktype is not NULL, the calculated + * block type will be set to \c blktype. If \c blkinst is not NULL, the + * calculated block instance to be set to \c blklinst. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] blknum Physical block number. + * \param [out] blktype Calculated block type. + * \param [out] blkinst Calculated instance number for block type. + * + * \return 0 if no errors, otherwise -1. + */ +extern int +bcmdrd_chip_block_type(const bcmdrd_chip_info_t *cinfo, int blknum, + int *blktype, int *blkinst); + +/*! + * \brief Get port number domain for a register/memory. + * + * Port-based registers and memories use different port number domains + * in their physical address. For example, some registers use the + * physical port number, some registers use the logical port number + * and some use a MMU port number. + * + * If no exception is found for this particular symbol, then the + * default domain for the block type will be returned. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] sid Symbol enum value. + * \param [in] blktype Block type for this symbol. + * + * \return Port number domain. + */ +extern bcmdrd_port_num_domain_t +bcmdrd_chip_port_num_domain(const bcmdrd_chip_info_t *cinfo, bcmdrd_sid_t sid, + int blktype); + +/*! + * \brief Get the bitmap of valid ports for a given port number domain. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] pnd Port number domain. + * \param [out] pbmp Port bitmap of valid ports. + * + * \retval 0 No errors. + * \retval -1 Invalid parameter. + */ +extern int +bcmdrd_chip_valid_pbmp(const bcmdrd_chip_info_t *cinfo, + bcmdrd_port_num_domain_t pnd, bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Get bitmap of ports associated with a given switch pipeline. + * + * The returned port bitmap is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] pipe_no Switch pipeline index. + * \param [in] pnd Port number domain. + * \param [out] pbmp Bitmap of ports associated with the specified pipeline. + * + * \retval 0 No errors. + * \retval -1 Invalid parameter. + */ +extern int +bcmdrd_chip_pipe_pbmp(const bcmdrd_chip_info_t *cinfo, int pipe_no, + bcmdrd_port_num_domain_t pnd, bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Check if a port index is valid in the specified port number domain. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] pnd Port number domain. + * \param [in] port Port index to check. + * + * \retval true Port is valid. + * \retval false Port is not valid. + */ +extern bool +bcmdrd_chip_port_valid(const bcmdrd_chip_info_t *cinfo, + bcmdrd_port_num_domain_t pnd, int port); + +/*! + * \brief Get the bitmap of valid ports for a device-specific symbol ID. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] sid Symbol enum value. + * \param [out] pbmp Port bitmap of valid ports. + * + * \retval 0 No errors. + * \retval -1 Invalid parameter. + */ +extern int +bcmdrd_chip_port_reg_pbmp(const bcmdrd_chip_info_t *cinfo, + bcmdrd_sid_t sid, bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Check if port index is valid for a device-specific symbol ID. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] sid Symbol enum value. + * \param [in] port Port index to check. + * \param [in] regidx Index of variable register array to validate. + * + * \retval true Port is valid. + * \retval false Port is not valid. + */ +extern bool +bcmdrd_chip_port_reg_valid(const bcmdrd_chip_info_t *cinfo, + bcmdrd_sid_t sid, int port, int regidx); + +/*! + * \brief Validate index for per-port variable register array. + * + * This function chekes if the index of specified per-port variable + * register array is valid. The maximum index of the variable array + * may be stored in different ways in DRD symbol. The possible encoded + * values are retrieved from DRD symbol and pass through argument + * \c encoding and regidx_max for validation. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] port Top-level port number. + * \param [in] regidx Index of variable register array to validate. + * \param [in] encoding Encoding type from index word. + * \param [in] regidx_max real maximum table index based on raw values and flags. + * + * \return 1 if index is valid in variable register arrary, otherwise 0. + */ +extern int +bcmdrd_chip_reg_index_valid(const bcmdrd_chip_info_t *cinfo, int port, + int regidx, int encoding, int regidx_max); + +/*! + * \brief Get pipe information for multi-pipe device. + * + * It is assumed that the caller of this function is familiar with the + * S-channel access mechanism for multi-pipe XGS designs, including + * the concepts of access type and base type. + * + * This function will return different information based on different + * query key type \c pi_type(\ref bcmdrd_pipe_info_type_t). + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] pi Device-specific parameters to query related pipe information. + * \param [in] pi_type Query key for specific pipe information. + * + * \return Specific pipe information based on query key. + */ +extern uint32_t +bcmdrd_chip_pipe_info(const bcmdrd_chip_info_t *cinfo, + bcmdrd_pipe_info_t *pi, bcmdrd_pipe_info_type_t pi_type); + +/*! + * \brief Get access type of a device-specific symbol ID. + * + * This function returns the device-specific access type of a specified + * symbol ID. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] sid Device-specific Symbol ID. + * + * \return Access type value or -1 on failure. + */ +extern int +bcmdrd_chip_acctype_get(const bcmdrd_chip_info_t *cinfo, bcmdrd_sid_t sid); + +/*! + * \brief Get block type of a device-specific symbol ID. + * + * This function returns the device-specific block type of a specified + * symbol ID by passing 0 as the \c blktype. If the symbol contains multiple + * block types, the function can be called repeatedly by passing + * the previously returned block type value plus one until -1 is returned. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] sid Device-specific Symbol ID. + * \param [in] blktype The initial blktype value to be searched. + * + * \return Block type or -1 on failure. + */ +extern int +bcmdrd_chip_blktype_get(const bcmdrd_chip_info_t *cinfo, bcmdrd_sid_t sid, + int blktype); + +/*! + * \brief Get device-specific block type by block type name. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] name The name for the block type. + * + * \return Block type or -1 if not found. + */ +extern int +bcmdrd_chip_blktype_get_by_name(const bcmdrd_chip_info_t *cinfo, + const char *name); + +/*! + * \brief Get name of device-specific block type. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] blktype Device-specific block type. + * + * \return Block type name or NULL if not found. + */ +extern const char * +bcmdrd_chip_blktype_name(const bcmdrd_chip_info_t *cinfo, + int blktype); + +/*! + * \brief Get block structure that matches the specified block types. + * + * The \c info is a 32-bit word with encoded information of block types. + * This 32-bit word can be retrieved from the symbol table or from the + * pre-defined value in header files. + * This function returns the device-specific block structure by passing + * NULL as the \c pblk. Calling this function repeatedly by passing the + * previously returned block structure pointer plus one until NULL is returned + * can find all the blocks that match the specified block types within + * the device. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] info Device-specific block types to match. + * \param [in] pblk The initial pointer to the block structure to be searched. + * + * \return Pointer to the matched block structure or NULL on failure. + */ +extern const bcmdrd_block_t * +bcmdrd_chip_block_types_match(const bcmdrd_chip_info_t *cinfo, + uint32_t info, const bcmdrd_block_t *pblk); + +/*! + * \brief Get port bitmap of the specified port type. + * + * The returned port bitmap is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] cinfo Pointer to chip information structure. + * \param [in] ptype The specified port type. + * \param [out] pbmp Bitmap of ports. + * + * \return 0 No errors. + * \retval -1 Feature is not supported. + */ +extern int +bcmdrd_chip_port_type_pbmp(const bcmdrd_chip_info_t *cinfo, + bcmdrd_port_type_t ptype, bcmdrd_pbmp_t *pbmp); + +#endif /* BCMDRD_CHIP_H */ diff --git a/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_dev.h b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_dev.h new file mode 100644 index 0000000..4b612d9 --- /dev/null +++ b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_dev.h @@ -0,0 +1,1369 @@ +/*! \file bcmdrd_dev.h + * + * DRD device APIs. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMDRD_DEV_H +#define BCMDRD_DEV_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#include +#endif + +#include +#include +#include + +/*! Global pointers for direct access to memory-mapped registers. */ +extern volatile uint32_t *bcmdrd_reg32_iomem[BCMDRD_CONFIG_MAX_UNITS]; + +#if BCMDRD_CONFIG_MEMMAP_DIRECT == 1 + +static inline int +bcmdrd_hal_reg32_direct_read(int unit, uint32_t addr, uint32_t *val) +{ + *val = bcmdrd_reg32_iomem[unit][addr/4]; + return SHR_E_NONE; +} + +static inline int +bcmdrd_hal_reg32_direct_write(int unit, uint32_t addr, uint32_t val) +{ + bcmdrd_reg32_iomem[unit][addr/4] = val; + return SHR_E_NONE; +} + +#endif + +/*! + * \brief Read 32-bit device register. + * + * Wrapper for \ref bcmdrd_hal_reg32_read, which may be redefined to a + * direct memory-mapped access for maximum performance. + * + * \param [in] _unit Unit number. + * \param [in] _addr Register offset relative to register base. + * \param [out] _val Data read from register. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_FAIL I/O read returned an error. + */ +#if BCMDRD_CONFIG_MEMMAP_DIRECT == 1 +#define BCMDRD_DEV_READ32(_unit, _addr, _val) \ + bcmdrd_hal_reg32_direct_read(_unit, _addr, _val) +#else +#define BCMDRD_DEV_READ32(_unit, _addr, _val) \ + bcmdrd_hal_reg32_read(_unit, _addr, _val) +#endif + +/*! + * \brief Write 32-bit device register. + * + * Wrapper for \ref bcmdrd_hal_reg32_write, which may be redefined to + * a direct memory-mapped access for maximum performance. + * + * \param [in] _unit Unit number. + * \param [in] _addr Register offset relative to register base. + * \param [in] _val Data to write to register. + */ +#if BCMDRD_CONFIG_MEMMAP_DIRECT == 1 +#define BCMDRD_DEV_WRITE32(_unit, _addr, _val) \ + bcmdrd_hal_reg32_direct_write(_unit, _addr, _val) +#else +#define BCMDRD_DEV_WRITE32(_unit, _addr, _val) \ + bcmdrd_hal_reg32_write(_unit, _addr, _val) +#endif + +/*! + * \brief Read iProc register. + * + * The register address can be specified anywhere in the 32-bit AXI + * address space. + * + * \param [in] _unit Unit number. + * \param [in] _addr Absolute register offset in AXI address space. + * \param [out] _val Data read from register. + */ +#define BCMDRD_IPROC_READ(_unit, _addr, _val) \ + bcmdrd_hal_iproc_read(_unit, _addr, _val) + +/*! + * \brief Write iProc register. + * + * The register address can be specified anywhere in the 32-bit AXI + * address space. + * + * \param [in] _unit Unit number. + * \param [in] _addr Absolute register offset in AXI address space. + * \param [in] _val Data to write to register. + */ +#define BCMDRD_IPROC_WRITE(_unit, _addr, _val) \ + bcmdrd_hal_iproc_write(_unit, _addr, _val) + +/*! + * \brief Read 64-bit iProc register. + * + * The register address can be specified anywhere in the 32-bit AXI + * address space. + * + * If supported by the host CPU, the access will be performed + * atomically. + * + * \param [in] _unit Unit number. + * \param [in] _addr Absolute register offset in AXI address space. + * \param [out] _val64 Data read from register. + */ +#define BCMDRD_IPROC_READ64(_unit, _addr, _val64) \ + bcmdrd_hal_iproc_read64(_unit, _addr, _val64) + +/*! + * \brief Write 64-bit iProc register. + * + * The register address can be specified anywhere in the 32-bit AXI + * address space. + * + * If supported by the host CPU, the access will be performed + * atomically. + * + * \param [in] _unit Unit number. + * \param [in] _addr Absolute register offset in AXI address space. + * \param [in] _val64 Data to write to register. + */ +#define BCMDRD_IPROC_WRITE64(_unit, _addr, _val64) \ + bcmdrd_hal_iproc_write64(_unit, _addr, _val64) + +/*! + * \brief Check if multi-byte register access needs byte-swapping. + * + * If the endianness of the host CPU and the switch device differ, + * then it may be necessary to perform a byte-swap for each register + * access. + * + * The endianness information must be provided by the system when I/O + * resources are assigned. See also \ref bcmdrd_dev_hal_io_init. + * + * Byte-swapping may be implemented in either hardware or software + * depdending on the device capabilities. + * + * \param [in] unit Unit number. + * + * \return true if byte-swapping is required, otherwise false. + */ +extern bool +bcmdrd_dev_byte_swap_pio_get(int unit); + +/*! + * \brief Check if packet DMA needs byte-swapping. + * + * Packet data is represented as an array of bytes irrespective of the + * CPU endianness, however packet data may pass through a generic + * byte-swapping bridge during a DMA operation, in which case the + * packet data must be swapped back to its original format. + * + * The endianness information must be provided by the system when I/O + * resources are assigned. See also \ref bcmdrd_dev_hal_io_init. + * + * \param [in] unit Unit number. + * + * \return true if byte-swapping is required, otherwise + * false. + */ +extern bool +bcmdrd_dev_byte_swap_packet_dma_get(int unit); + +/*! + * \brief Check if non-packet DMA needs byte-swapping. + * + * If the endianness of the host CPU and the switch device differ, + * then it may be necessary to perform a byte-swap on data transferred + * between host memory and switch device memory via DMA. + * + * The endianness information must be provided by the system when I/O + * resources are assigned. See also \ref bcmdrd_dev_hal_io_init. + * + * \param [in] unit Unit number. + * + * \return true if byte-swapping is required, otherwise + * false. + */ +extern bool +bcmdrd_dev_byte_swap_non_packet_dma_get(int unit); + +/*! + * \brief Get device bus type. + * + * Get the bus type by which the device os connected to the host CPU. + * + * The bus type is normally PCI if an external host CPU is used, and + * AXI (ARM interconnect) is an embedded CPU is used. + * + * The bus type may affect both DMA access and register access + * configurations. + * + * \param [in] unit Unit number. + * + * \return Device bus type. + */ +extern bcmdrd_hal_bus_type_t +bcmdrd_dev_bus_type_get(int unit); + +/*! + * \brief Get device IO flags. + * + * Get device IO flags, (BCMDRD_HAL_IO_F_XXX). + * + * \param [in] unit Unit number. + * + * \retval Device IO flags. + */ +extern uint32_t +bcmdrd_dev_io_flags_get(int unit); + +/*! + * \brief Provide block of high-availability DMA memory. + * + * This function is used by the application to supply the SDK with a + * fixed-size block of high-availability DMA memory. + * + * The SDK will expect to get the same block of memory assigned after + * a warm-boot or a crash. + * + * The memory block must be physically contiguous and cache-coherent. + * + * \param [in] unit Unit number. + * \param [in] size Size of DMA memory block (in bytes). + * \param [in] ha_dma_mem Logical address of DMA memory block. + * \param [out] dma_addr Physical address of DMA memory block. + * + * \retval SHR_E_NONE No errors. + */ +extern int +bcmdrd_dev_ha_dma_mem_set(int unit, size_t size, + void *ha_dma_mem, uint64_t dma_addr); + +/*! + * \brief Get pointer to high-availability DMA memory. + * + * The SDK will use this API to access the HA DMA memory block + * provided by the application. + * + * The application may call this API with \c dma_addr as a NULL + * pointer to get the desired size of the HA DMA memory blcok. + * + * \param [in] unit Unit number. + * \param [in] size Size of DMA memory block (in bytes). + * \param [out] dma_addr Physical address of DMA memory block. + * + * \return Pointer to DMA memory block or NULL if an error occurred. + */ +extern void * +bcmdrd_dev_ha_dma_mem_get(int unit, size_t *size, uint64_t *dma_addr); + +/*! + * \brief Set chip information. + * + * The chip information consiste mainly of block and port information, + * but it may also provide functions to retrieve special register and + * memory attributes, etc. + * + * Note that only a pointer to the chip information structure will be + * stored in the DRD device strucutre. + * + * \param [in] unit Unit number. + * \param [in] chip_info Pointer to chip information structure. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_chip_info_set(int unit, const bcmdrd_chip_info_t *chip_info); + +/*! + * \brief Get a pointer to the chip information structure. + * + * \param [in] unit Unit number. + * + * \return Pointer to chip information, or NULL if not found. + */ +extern const bcmdrd_chip_info_t * +bcmdrd_dev_chip_info_get(int unit); + +/*! + * \brief Set chip profile. + * + * A chip profile contains information about how a given SKU variant + * differs from the base device. + * + * Note that only a pointer to the chip profile will be stored in the + * DRD device structure. + * + * If a NULL pointer is passed in as the chip profile pointer, then + * the default chip profile for this SKU device will be loaded. + * + * \param [in] unit Unit number. + * \param [in] profile Pointer to chip profile. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_chip_profile_set(int unit, bcmdrd_chip_profile_t *profile); + +/*! + * \brief Get a pointer to the current chip profile. + * + * \param [in] unit Unit number. + * + * \return Pointer to chip profile, or NULL if none found. + */ +extern bcmdrd_chip_profile_t * +bcmdrd_dev_chip_profile_get(int unit); + +/*! + * \brief Set the bitmap of valid ports for this unit. + * + * Ports not supported by the underlying device will be ignored. + * + * \param [in] unit Unit number. + * \param [in] pbmp Port bitmap of valid ports. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_valid_ports_set(int unit, const bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Get the bitmap of valid ports for this unit. + * + * \param [in] unit Unit number. + * \param [out] pbmp Port bitmap of valid ports. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_valid_ports_get(int unit, bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Set the bitmap of valid pipes for this unit. + * + * Override the default set of valid pipes for this unit. + * + * \param [in] unit Unit number. + * \param [in] pm Bitmap of valid pipes. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_valid_pipemap_set(int unit, bcmdrd_pipemap_t *pm); + +/*! + * \brief Get the bitmap of valid pipes for this unit. + * + * Pipes without any ports in the underlying device will be ignored. + * + * Ports that do not belong to a valid pipe will be removed from the + * bitmap of valid ports for this unit. + * + * \param [in] unit Unit number. + * \param [out] pm Bitmap of valid pipes. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Invalid parameter. + */ +extern int +bcmdrd_dev_valid_pipemap_get(int unit, bcmdrd_pipemap_t *pm); + +/*! + * \brief Set the bitmap of valid pipes for this unit. + * + * Override the default set of valid pipes for this unit. + * + * Note that this API only supports 32 pipes or fewer. + * + * See also \ref bcmdrd_dev_valid_pipemap_set. + * + * \param [in] unit Unit number. + * \param [in] pipe_map Bitmap of valid pipes. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_valid_pipes_set(int unit, uint32_t pipe_map); + +/*! + * \brief Get the bitmap of valid pipes for this unit. + * + * Pipes without any ports in the underlying device will be ignored. + * + * Ports that do not belong to a valid pipe will be removed from the + * bitmap of valid ports for this unit. + * + * Note that this API only supports 32 pipes or fewer. + * + * See also \ref bcmdrd_dev_valid_pipemap_get. + * + * \param [in] unit Unit number. + * \param [out] pipe_map Bitmap of valid pipes. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Invalid parameter. + */ +extern int +bcmdrd_dev_valid_pipes_get(int unit, uint32_t *pipe_map); + +/*! + * \brief Get the bitmap of valid pipes for a device-specific block type. + * + * This function transforms the bitmap of pipes from device basis to + * block basis. If \c dev_pipe_map is 0, the valid pipes bitmap of the device + * will be used for the transformation. + * + * Note that this API only supports 32 pipes or fewer. + * + * \param [in] unit Unit number. + * \param [in] dev_pipe_map Bitmap of pipes on device basis. + * \param [in] blktype Device-specific block type. + * \param [out] blk_pipe_map Bitmap of valid pipes for the specified block. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Invalid parameter. + */ +extern int +bcmdrd_dev_valid_blk_pipes_get(int unit, uint32_t dev_pipe_map, + int blktype, uint32_t *blk_pipe_map); + +/*! + * \brief Device-specific pipe number check. + * + * Check if pipe number is valid for a given block type. + * + * \param [in] unit Unit number. + * \param [in] blktype Device-specific block type. + * \param [in] pipe_no Pipe number to check. + * + * \retval true Pipe number is valid. + * \retval false Pipe number is not valid. + */ +typedef bool (*bcmdrd_dev_block_pipe_valid_f)(int unit, int blktype, + int pipe_no); + +/*! + * \brief Set device-specific function for checking of pipe number. + * + * This function installs a callback for the \ref + * bcmdrd_dev_block_pipe_valid API. The callback will override the + * default behavior of this API. + * + * \param [in] unit Unit number. + * \param [in] func Device-specific pipe number check function. + * + * \retval SHR_E_NONE Function successfully installed. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_block_pipe_valid_func_set(int unit, + bcmdrd_dev_block_pipe_valid_f func); + +/*! + * \brief Check if pipe number is valid for a given block type. + * + * \param [in] unit Unit number. + * \param [in] blktype Device-specific block type. + * \param [in] pipe_no Pipe number to check. + * + * \retval true Pipe number is valid. + * \retval false Pipe number is not valid. + */ +extern bool +bcmdrd_dev_block_pipe_valid(int unit, int blktype, int pipe_no); + +/*! + * \brief Get the bitmap of valid pipes for a device-specific block type. + * + * \param [in] unit Unit number. + * \param [in] blktype Device-specific block type. + * \param [out] pm Bitmap of valid pipes for the specified block. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Invalid parameter. + */ +extern int +bcmdrd_dev_valid_block_pipes_get(int unit, int blktype, bcmdrd_pipemap_t *pm); + +/*! + * \brief Get pointer to device symbol table. + * + * \param [in] unit Unit number. + * \param [in] idx Symbol table index (currently only 0 is valid). + * + * \return Pointer to symbol table, or NULL if not found. + */ +extern const bcmdrd_symbols_t * +bcmdrd_dev_symbols_get(int unit, int idx); + +/*! + * \brief Get device-specific flags. + * + * Get the flags defined in the chip information structure. + * + * \param [in] unit Unit number. + * + * \return Device-specific flags. + */ +extern uint32_t +bcmdrd_dev_flags_get(int unit); + +/*! + * \brief Set pipeline bypass mode. + * + * This setting may have different meanings on different devices all + * depending on the bypass capabilities of a particular device type. + * + * The base driver will use this setting to silently ignore access to + * bypassed registers and memories. Other driver components may use + * this setting to modify their internal behavior. + * + * \param [in] unit Unit number. + * \param [in] bypass_mode Device-specific bypass mode. + * + * \return Nothing. + */ +extern void +bcmdrd_dev_bypass_mode_set(int unit, uint32_t bypass_mode); + +/*! + * \brief Get pipeline bypass mode. + * + * See \ref bcmdrd_dev_bypass_mode_set for details. + * + * \param [in] unit Unit number. + * + * \return Device-specific bypass mode. + */ +extern uint32_t +bcmdrd_dev_bypass_mode_get(int unit); + +/*! + * \brief Set device operation mode. + * + * This setting may have different meanings on different devices all + * depending on how the \c opmode is interpreted by the target device. + * + * \param [in] unit Unit number. + * \param [in] opmode Device operation mode. + * + * \return Nothing. + */ +extern void +bcmdrd_dev_opmode_set(int unit, uint32_t opmode); + +/*! + * \brief Get device operation mode. + * + * See \ref bcmdrd_dev_opmode_set for details. + * + * \param [in] unit Unit number. + * + * \return Device operation mode. + */ +extern uint32_t +bcmdrd_dev_opmode_get(int unit); + +/*! + * \brief Set device bus initialization state. + * + * During warmboot it may interfere with ongoing device activities + * (e.g. in a Linux kernel module) if the device bus is reinitialized. + * This API allows system-level code to indicate that the device bus + * has already been initialized. + * + * \param [in] unit Unit number. + * \param [in] bus_initialized Whether device bus has been initialized. + * + * \return Nothing. + */ +extern void +bcmdrd_dev_bus_initialized_set(int unit, bool bus_initialized); + +/*! + * \brief Check if device bus has been initialized. + * + * Low-level device bus drivers (e.g. PCI bridge drivers) should + * consult this API to avoid reinitializing the device bus. This is + * especially important during warmboot where the device may be active + * even before the application is loaded. + * + * \param [in] unit Unit number. + * + * \return Whether device bus has been initialized. + */ +extern bool +bcmdrd_dev_bus_initialized_get(int unit); + +/*! + * \brief Get license data. + * + * Get hardware license data for download into the device. + * + * Currently only a single license is supported. + * + * \param [in] unit Unit number. + * \param [out] size Size of license data. + * + * \return License data or NULL if unavailable. + */ +extern uint8_t * +bcmdrd_dev_license_get(int unit, size_t *size); + +/*! + * \brief Remove all license data. + * + * This operation is also performed implicitly when calling \ref + * bcmdrd_dev_destroy. + * + * \param [in] unit + * + * \retval 0 No errors + */ +extern int +bcmdrd_dev_license_cleanup(int unit); + +/*! + * \brief Get pipe information for multi-pipe device. + * + * It is assumed that the caller of this function is familiar with the + * S-channel access mechanism for multi-pipe XGS designs, including + * the concepts of access type and base type. + * + * This function will return different information based on different + * query key type \c pi_type(\ref bcmdrd_pipe_info_type_t). + * + * \param [in] unit Unit number. + * \param [in] pi Device-specific parameters to query related pipe information. + * \param [in] pi_type Query key for specific pipe information. + * + * \return Specific pipe information based on query key. + */ +extern uint32_t +bcmdrd_dev_pipe_info(int unit, bcmdrd_pipe_info_t *pi, + bcmdrd_pipe_info_type_t pi_type); + +/*! + * \brief Get special address calculation function. + * + * Used for non-standard address calculations. See \ref + * bcmdrd_block_port_addr_f for details. + * + * \param [in] unit Unit number. + * + * \return Function pointer, or NULL if standard address calculation. + */ +extern bcmdrd_block_port_addr_f +bcmdrd_dev_block_port_addr_func(int unit); + +/*! + * \brief Get address decode function. + * + * Used for non-standard address decoding. See \ref + * bcmdrd_addr_decode_f for details. + * + * \param [in] unit Unit number. + * + * \return Function pointer, or NULL if standard address decoding. + */ +extern bcmdrd_addr_decode_f +bcmdrd_dev_addr_decode_func(int unit); + +/*! + * \brief Get pipeline index of a given physical port for this unit. + * + * \param [in] unit Unit number. + * \param [in] port Physical port number. + * + * \return Pipeline index, or -1 on error. + */ +extern int +bcmdrd_dev_phys_port_pipe(int unit, int port); + +/*! + * \brief Get pipeline index of a given logical port for this unit. + * + * \param [in] unit Unit number. + * \param [in] port Logical port number. + * + * \return Pipeline index, or -1 on error. + */ +extern int +bcmdrd_dev_logic_port_pipe(int unit, int port); + +/*! + * \brief Get pipeline index of a given MMU port for this unit. + * + * \param [in] unit Unit number. + * \param [in] port MMU port number. + * + * \return Pipeline index, or -1 on error. + */ +extern int +bcmdrd_dev_mmu_port_pipe(int unit, int port); + +/*! + * \brief Get device-specific block-based pipeline index of a given port. + * + * The port number domain of the specified port must match + * the port number domain of the specified block type. + * + * \param [in] unit Unit number. + * \param [in] blktype Device-specific block type. + * \param [in] port Port number. + * + * \return block-based pipeline index, or -1 on error. + */ +extern int +bcmdrd_dev_blk_port_pipe(int unit, int blktype, int port); + +/*! + * \brief Get bitmap of valid physical ports for this unit. + * + * The returned port bitmap is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] unit Unit number. + * \param [out] pbmp Bitmap of valid physical ports. + * + * \retval 0 No errors. + * \retval -1 Invalid parameter. + */ +extern int +bcmdrd_dev_phys_pbmp(int unit, bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Get bitmap of valid logical ports for this unit. + * + * The returned port bitmap is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] unit Unit number. + * \param [out] pbmp Bitmap of valid logical ports. + * + * \retval 0 No errors. + * \retval -1 Invalid parameter. + */ +extern int +bcmdrd_dev_logic_pbmp(int unit, bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Get bitmap of valid MMU ports for this unit. + * + * The returned port bitmap is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] unit Unit number. + * \param [out] pbmp Bitmap of valid MMU ports. + * + * \retval 0 No errors. + * \retval -1 Invalid parameter. + */ +extern int +bcmdrd_dev_mmu_pbmp(int unit, bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Get bitmap of ports associated with a given block type. + * + * The returned port bitmap is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * The block type enumeration is specific to the base device type. + * + * \param [in] unit Unit number. + * \param [in] blktype Device-specific block type. + * \param [out] pbmp Bitmap of ports associated with the specified block type. + * + * \retval 0 No errors. + * \retval -1 Invalid parameter. + */ +extern int +bcmdrd_dev_blktype_pbmp(int unit, int blktype, bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Get bitmap of physical ports associated with a given switch pipeline. + * + * The returned port bitmap is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] unit unit number. + * \param [in] pipe_no Switch pipeline index. + * \param [out] pbmp Bitmap of physical ports associated with the specified + * pipeline. + * + * \retval 0 No errors. + * \retval -1 Invalid parameter. + */ +extern int +bcmdrd_dev_pipe_phys_pbmp(int unit, int pipe_no, bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Get bitmap of logical ports associated with a given switch pipeline. + * + * The returned port bitmap is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] unit unit number. + * \param [in] pipe_no Switch pipeline index. + * \param [out] pbmp Bitmap of logical ports associated with the specified + * pipeline. + * + * \retval 0 No errors. + * \retval -1 Invalid parameter. + */ +extern int +bcmdrd_dev_pipe_logic_pbmp(int unit, int pipe_no, bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Get bitmap of MMU ports associated with a given switch pipeline. + * + * The returned port bitmap is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] unit unit number. + * \param [in] pipe_no Switch pipeline index. + * \param [out] pbmp Bitmap of MMU ports associated with the specified + * pipeline. + * + * \retval 0 No errors. + * \retval -1 Invalid parameter. + */ +extern int +bcmdrd_dev_pipe_mmu_pbmp(int unit, int pipe_no, bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Get bitmap of ports associated with a given block-based pipeline. + * + * The returned port bitmap is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] unit unit number. + * \param [in] blktype Device-specific block type. + * \param [in] blk_pipe_no Device-specific block-based pipeline index. + * \param [out] pbmp Bitmap of ports associated with the specified block-based + * pipeline. + * + * \retval 0 No errors. + * \retval -1 Invalid parameter. + */ +extern int +bcmdrd_dev_blk_pipe_pbmp(int unit, int blktype, int blk_pipe_no, + bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Get block pipe number associated with device pipe. + * + * \param [in] unit Unit number. + * \param [in] blktype Device-specific block type. + * \param [in] dev_pipe_no Device pipe number. + * + * \return Block pipe number or -1 on error. + */ +extern int +bcmdrd_dev_block_pipe(int unit, int blktype, int dev_pipe_no); + +/*! + * \brief Get block number from type and instance. + * + * Given a block type and an instance number of that block type, this + * function will return the corresponding physical block number. + * + * \param [in] unit unit number. + * \param [in] blktype Device-specific block type. + * \param [in] blkinst Instance number for block type. + * + * \return Physical block number, or -1 if no matching block is found. + */ +extern int +bcmdrd_dev_block_number(int unit, int blktype, int blkinst); + +/*! + * \brief Get number of block instances from block type. + * + * This function will return the number of block instances for a given + * block type. + * + * \param [in] unit unit number. + * \param [in] blktype Block type. + * + * \return Number of block instances, or -1 if no matching block type is found. + */ +extern int +bcmdrd_dev_num_block_inst(int unit, int blktype); + +/*! + * \brief Get bitmap of physical loopback ports. + * + * The returned port bitmap is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] unit unit number. + * \param [out] pbmp Bitmap of physical loopback ports. + * + * \retval 0 No errors. + * \retval -1 Feature is not supported for the specified device. + */ +extern int +bcmdrd_dev_lb_pbmp(int unit, bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Get number of physical ports associated with a given switch pipeline. + * + * The returned number of ports is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] unit unit number. + * \param [in] pipe_no Switch pipeline index. + * + * \return Number of physical ports, or -1 on error. + */ +extern int +bcmdrd_dev_pipe_num_phys_ports(int unit, int pipe_no); + +/*! + * \brief Get number of logical ports associated with a given switch pipeline. + * + * The returned number of ports is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] unit unit number. + * \param [in] pipe_no Switch pipeline index. + * + * \return Number of logical ports, or -1 on error. + */ +extern int +bcmdrd_dev_pipe_num_logic_ports(int unit, int pipe_no); + +/*! + * \brief Get number of MMU ports associated with a given switch pipeline. + * + * The returned number of ports is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] unit unit number. + * \param [in] pipe_no Switch pipeline index. + * + * \return Number of MMU ports, or -1 on error. + */ +extern int +bcmdrd_dev_pipe_num_mmu_ports(int unit, int pipe_no); + +/*! + * \brief Get number of ports associated with a given block-based pipeline. + * + * The returned number of ports is defined by the switch device type only, + * i.e. it is independent of the current switch configuration. + * + * \param [in] unit unit number. + * \param [in] blktype Device-specific block type. + * \param [in] blk_pipe_no Device-specific block-based pipeline index. + * + * \return Number of ports, or -1 on error. + */ +extern int +bcmdrd_dev_blk_pipe_num_ports(int unit, int blktype, int blk_pipe_no); + +/*! + * \brief Set the tainted state for this unit. + * + * \param [in] unit Unit number. + * \param [in] tainted Tainted state. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_tainted_set(int unit, bool tainted); + +/*! + * \brief Get the tainted state for this unit. + * + * \param [in] unit Unit number. + * \param [in] tainted Tainted state. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_tainted_get(int unit, bool *tainted); + +/*! + * \brief Get chip modifier object for a given symbol. + * + * \param [in] unit Unit number. + * \param [in] sid Device-specific symbol ID + * + * \return Pointer to chip modifier object or NULL if not found. + * + * \param [in] unit + * \param [in] sid + * + * \retval 0 No errors + */ +extern bcmdrd_chip_mod_t * +bcmdrd_dev_mod_get(int unit, bcmdrd_sid_t sid); + +/*! + * \brief Get adjusted maximum index of a specific memory. + * + * This function returns adjusted maximum index of a specific memory. + * Some device variant have smaller memories than the base device, and + * this function can be used to retrieve such override values. If no + * override information is found, then the input \c maxidx is + * returned. + * + * \param [in] unit Unit number. + * \param [in] sid Symbol index in DRD of the specific memory. + * \param [in] maxidx Default maximum index of the specific memory. + * + * \return Maximum index of a specific memory. + */ +extern uint32_t +bcmdrd_dev_mem_maxidx(int unit, bcmdrd_sid_t sid, uint32_t maxidx); + +/*! + * \brief Check if symbol is marked as invalid. + * + * For some device variants (SKUs) some registers and memories may + * have been disabled. + * + * \param [in] unit Unit number. + * \param [in] sid Symbol ID to check. + * + * \retval true Symbol is not marked as invalid. + * \retval false Symbol is marked as invalid. + */ +bool +bcmdrd_dev_sym_valid(int unit, bcmdrd_sid_t sid); + +/*! + * \brief Get chip parameter. + * + * Get device-specific device property value. + * + * \param [in] unit Unit number. + * \param [in] prm_name Parameter name. + * \param [out] prm_val Parameter value. + * + * \retval 0 No errors. + * \retval -1 Not found. + */ +extern int +bcmdrd_dev_param_get(int unit, const char *prm_name, uint32_t *prm_val); + +/*! + * \brief Get next supported chip parameter. + * + * Device variants may implement device-specific chip parameters + * whenever a device variant property differs from the base device. + * + * Pass in NULL to get the first supported parameter. Pass in the name + * of the first supported parameter to get the second parameter and so + * forth. + * + * \param [in] unit Unit number. + * \param [in] prm_name Parameter name. + * + * \return Name of next parameter or NULL if no more parameters. + */ +extern const char * +bcmdrd_dev_param_next(int unit, const char *prm_name); + + +/*! + * \brief Get device signature. + * + * Get pointer to a string containing a message digest generated + * across the symbol table. This string will change if there has been + * any changes to the register and memory definitions. + * + * \param [in] unit Unit number. + * + * \return Signature string or NULL if invalid unit number. + */ +extern const char * +bcmdrd_dev_signature_get(int unit); + +/*! + * \brief Get block structure that matches the specified block types. + * + * This function works like \ref bcmdrd_chip_block_types_match, but + * also provides an indicator of whether the block has any valid + * ports. The function uses a cached value for this indicator, since + * it is relatively expensive to calculate it each time the function + * is called. + * + * Please refer to \ref bcmdrd_chip_block_types_match for a detailed + * description of the \c info and \c pblk parameters. + * + * \param [in] unit Unit number. + * \param [in] info Device-specific block types to match. + * \param [in] pblk The initial pointer to the block structure to be searched. + * \param [out] valid_ports Whether this block has any valid ports. + * + * \retval 0 No errors + */ +extern const bcmdrd_block_t * +bcmdrd_dev_block_types_match(int unit, uint32_t info, + const bcmdrd_block_t *pblk, + bool *valid_ports); + +/*! + * \brief Device-specific function for registers/memories index validity. + * + * If there are exceptions of registers/memories that some indices or instances + * can not be accessed in the indices or instances range, this function can be + * implemented as device-specific to reflect the exceptions for table indices + * or instances. + * + * \param [in] unit Unit number. + * \param [in] sid Symbol ID to check. + * \param [in] tbl_inst Table instance to check. + * \param [in] tbl_idx Table index to check. + * \param [out] valid True if the \c idx for the \c sid is valid, + * otherwise false. + * + * \retval SHR_E_NONE The returned \c valid can be referenced as validity. + * \retval SHR_E_UNIT The Unit number \c unit is invalid. + * \retval SHR_E_PARAM The returned parameter \c valid is NULL. + * \retval SHR_E_UNAVAIL No exceptions check support for the \c unit or \c sid. + */ +typedef int (*bcmdrd_dev_pt_index_valid_f)(int unit, bcmdrd_sid_t sid, + int tbl_inst, int tbl_idx, + bool *valid); + +/*! + * \brief Set device-specific function of index validity. + * + * Set device-specific index validity function to the device resource database. + * Set \c func to NULL to clean up the database. + * + * \param [in] unit Unit number. + * \param [in] func Device-specific index validity function. + * + * \retval SHR_E_NONE Function successfully installed. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_pt_index_valid_func_set(int unit, bcmdrd_dev_pt_index_valid_f func); + +/*! + * \brief Check exceptions for registers/memories index or instance validity. + * + * This function can be used to check if there is any exception index or + * instance that can not be accessed in the indices or instances range of + * registers/memories. + * + * \param [in] unit Unit number. + * \param [in] sid Symbol ID to check. + * \param [in] tbl_inst Table instance to check. + * \param [in] tbl_idx Table index to check. + * \param [out] valid True if the \c tbl_inst and \c tbl_idx for the \c sid + * is valid, otherwise false. + * + * \retval SHR_E_NONE The returned \c valid can be referenced as validity. + * \retval SHR_E_UNIT The Unit number \c unit is invalid. + * \retval SHR_E_PARAM The returned parameter \c valid is NULL. + * \retval SHR_E_UNAVAIL No exceptions check support for the \c unit or \c sid. + */ +extern int +bcmdrd_dev_pt_index_valid(int unit, bcmdrd_sid_t sid, int tbl_inst, int tbl_idx, + bool *valid); + +/*! + * \brief Device-specific function for registers/memories validity. + * + * If there are exceptions of registers/memories validaty, this function can + * be implemented as device-specific to reflect the physical table validity + * exceptions at system initialization stage. + * + * \param [in] unit Unit number. + * \param [in] sid Symbol ID to check. + * + * \retval true SID is valid for the current device configuration. + * \retval false SID is not valid for the current device configuration. + */ +typedef bool (*bcmdrd_dev_pt_valid_f)(int unit, bcmdrd_sid_t sid); + +/*! + * \brief Set device-specific function of physical table validity. + * + * Set device-specific physical table validity function to the device + * resource database. Set \c func to NULL to clean up the database. + * + * \param [in] unit Unit number. + * \param [in] func Device-specific physical table validity function. + * + * \retval SHR_E_NONE Function successfully installed. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_pt_valid_func_set(int unit, bcmdrd_dev_pt_valid_f func); + +/*! + * \brief Check exceptions for registers/memories validity. + * + * This function can be used to check if there is any run-time exception of + * physical table that can not be accessed. + * + * \param [in] unit Unit number. + * \param [in] sid Symbol ID to check. + * + * \retval true SID is valid for the current device configuration. + * \retval false SID is not valid for the current device configuration. + */ +extern bool +bcmdrd_dev_pt_valid(int unit, bcmdrd_sid_t sid); + +/*! + * \brief Check if physical table index range is contiguous. + * + * Please refer to \ref bcmdrd_dev_pt_contiguous for more information. + * + * \param [in] unit Unit number. + * \param [in] sid Symbol ID to check. + * + * \retval true Table index range is contiguous (no holes). + * \retval false Table has holes in the index range. + */ +typedef bool (*bcmdrd_dev_pt_contiguous_f)(int unit, bcmdrd_sid_t sid); + +/*! + * \brief Set device-specific check for physical table index range. + * + * Set device-specific function that reports whether the indexes of a + * physical table are contiguous. Set \c func to NULL to use the + * default checker. + * + * \param [in] unit Unit number. + * \param [in] func Device-specific function for index table map. + * + * \retval SHR_E_NONE Function successfully installed. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_pt_contiguous_func_set(int unit, bcmdrd_dev_pt_contiguous_f func); + +/*! + * \brief Check if physical table index range is contiguous. + * + * Table DMA operations typically require that all indexes in a range + * are valid and accessible. This function checks if this is true for + * a given table, which in turn allows the DMA driver to check each + * table index for validity only for tables with holes. + * + * \param [in] unit Unit number. + * \param [in] sid Symbol ID to check. + * + * \retval true Table index range is contiguous (no holes). + * \retval false Table has holes in the index range. + */ +extern bool +bcmdrd_dev_pt_contiguous(int unit, bcmdrd_sid_t sid); + +/*! + * \brief Remap two-dimensional table instance to pipe and block instance. + * + * For symbol ID with two-dimensional table instance composed of pipe and + * block, this function can be used to remap the table instance to pipe + * instance and block instance. + * + * \param [in] unit Unit number. + * \param [in] sid Symbol ID to check. + * \param [in] tbl_inst Table instance to check. + * \param [out] pipe remapped pipe instance. + * \param [out] blkinst remapped block instance. + * + * \retval SHR_E_NONE The \c pipe and \c blkinst are successfully remapped. + * \retval SHR_E_UNIT The Unit number \c unit is invalid. + * \retval SHR_E_PARAM The returned parameter \c pipe or \c blkinst is NULL. + * \retval SHR_E_UNAVAIL No remap function available for the \c unit or \c sid. + */ +typedef int (*bcmdrd_dev_pt_inst_remap_f)(int unit, bcmdrd_sid_t sid, + int tbl_inst, + int *pipe, int *blkinst); + +/*! + * \brief Set device-specific function to remap two-dimensional table instance. + * + * Set device-specific table instance remap function to the device + * resource database. Set \c func to NULL to clean up the database. + * + * \param [in] unit Unit number. + * \param [in] func Device-specific table instance remap function. + * + * \retval SHR_E_NONE Function successfully installed. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmdrd_dev_pt_inst_remap_func_set(int unit, bcmdrd_dev_pt_inst_remap_f func); + +/*! + * \brief Remap two-dimensional table instance to pipe and block instance. + * + * For symbol ID with two-dimensional table instance composed of pipe and + * block, this function can be used to remap the table instance to pipe + * instance and block instance. + * + * \param [in] unit Unit number. + * \param [in] sid Symbol ID to check. + * \param [in] tbl_inst Table instance to check. + * \param [out] pipe remapped pipe instance. + * \param [out] blkinst remapped block instance. + * + * \retval SHR_E_NONE The \c pipe and \c blkinst are successfully remapped. + * \retval SHR_E_UNIT The Unit number \c unit is invalid. + * \retval SHR_E_PARAM The returned parameter \c pipe or \c blkinst is NULL. + * \retval SHR_E_UNAVAIL No remap function available for the \c unit or \c sid. + */ +extern int +bcmdrd_dev_pt_inst_remap(int unit, bcmdrd_sid_t sid, int tbl_inst, + int *pipe, int *blkinst); + +#endif /* BCMDRD_DEV_H */ diff --git a/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_devlist.h b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_devlist.h new file mode 100644 index 0000000..a9116f8 --- /dev/null +++ b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_devlist.h @@ -0,0 +1,266 @@ +/* + * DO NOT EDIT THIS FILE! + * This file is auto-generated. + * Edits to this file will be lost when it is regenerated. + * Tool: INTERNAL/drd/instpkgs.pl + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +/* + * This file contains the complete list of supported devices. + * No other device lists should be used anywhere in the SDK. + */ + +#ifndef BCMDRD_DEVIDS_H +#define BCMDRD_DEVIDS_H + +#include + +/* + * All Supported Devices and Revisions + */ + +#include + +/* + * End of Supported Devices and Revisions + */ + +#endif /* BCMDRD_DEVIDS_H */ + +#ifdef BCMDRD_DEVLIST_ENTRY +/* + * BCMDRD_DEVLIST_ENTRY macros. + * + * Before including this file, define BCMDRD_DEVLIST_ENTRY + * as a macro to operate on the following parameters: + * + * #define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) + * + * _nm: Chip Name + * _vn: Chip Vendor ID + * _dv: Chip Device ID + * _rv: Chip Revision + * _md: Chip Model + * _pi: Probe Information + * _bd: SW Base Driver + * _bc: SW Base Configuration + * _fn: SW Full Name + * _cn: Code Name + * _pf: Product Family + * _pd: Product Description + * _r0: Reserved + * _r1: Reserved + * + * Note that this macro will be undefined at the end of this file. + */ + +#if BCMDRD_CONFIG_INCLUDE_BCM88860_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +BCMDRD_DEVLIST_ENTRY(BCM88860, BROADCOM_VENDOR_ID, JERICHO3_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88860_a0, bcm88860_a0, bcm88860_a0, "JERICHO3", "BCM88860", "Multilayer Switch", 0, 0) + +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM88860, BROADCOM_VENDOR_ID, JERICHO3_DEVICE_ID, DNXC_A1_REV_ID, + 0, 0, + bcm88860_a0, bcm88860_a0, bcm88860_a1, "JERICHO3", "BCM88860", "Multilayer Switch", 0, 0) +BCMDRD_DEVLIST_ENTRY(BCM88860, BROADCOM_VENDOR_ID, JERICHO3_DEVICE_ID, DNXC_B0_REV_ID, + 0, 0, + bcm88860_a0, bcm88860_a0, bcm88860_b0, "JERICHO3", "BCM88860", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88867_C0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM88867, BROADCOM_VENDOR_ID, 0x8867, DNXC_C0_REV_ID, + 0, 0, + bcm88860_a0, bcm88860_a0, bcm88867_c0, "JERICHO3P", "BCM88867", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88890_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM88890, BROADCOM_VENDOR_ID, J3AI_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88860_a0, bcm88860_a0, bcm88890_a0, "J3AI", "BCM88890", "Multilayer Switch", 0, 0) +BCMDRD_DEVLIST_ENTRY(BCM88890, BROADCOM_VENDOR_ID, J3AI_DEVICE_ID, DNXC_A1_REV_ID, + 0, 0, + bcm88860_a0, bcm88860_a0, bcm88890_a1, "J3AI", "BCM88890", "Multilayer Switch", 0, 0) +BCMDRD_DEVLIST_ENTRY(BCM88890, BROADCOM_VENDOR_ID, J3AI_DEVICE_ID, DNXC_B0_REV_ID, + 0, 0, + bcm88860_a0, bcm88860_a0, bcm88890_b0, "J3AI", "BCM88890", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88897_C0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM88897, BROADCOM_VENDOR_ID, 0x8897, DNXC_C0_REV_ID, + 0, 0, + bcm88860_a0, bcm88860_a0, bcm88897_c0, "J3AIP", "BCM88897", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88870_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM88870, BROADCOM_VENDOR_ID, Q3D_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88860_a0, bcm88860_a0, bcm88870_a0, "Q3D", "BCM88870", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88490_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM88490, BROADCOM_VENDOR_ID, Q3A_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88860_a0, bcm88860_a0, bcm88490_a0, "Q3A", "BCM88490", "Multilayer Switch", 0, 0) +BCMDRD_DEVLIST_ENTRY(BCM884A0, BROADCOM_VENDOR_ID, Q3U_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88860_a0, bcm88860_a0, bcm884a0_a0, "Q3U", "BCM884A0", "Multilayer Switch", 0, 0) +BCMDRD_DEVLIST_ENTRY(BCM884A5, BROADCOM_VENDOR_ID, Q3N_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88860_a0, bcm88860_a0, bcm884a5_a0, "Q3N", "BCM884A5", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM99450_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +BCMDRD_DEVLIST_ENTRY(BCM99450, BROADCOM_VENDOR_ID, 0x9450, DNXC_A0_REV_ID, + 0, 0, + bcm99450_a0, bcm99450_a0, bcm99450_a0, "BCM99450", "BCM99450", "Multilayer Switch", 0, 0) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM99420, BROADCOM_VENDOR_ID, 0x9420, DNXC_A0_REV_ID, + 0, 0, + bcm99450_a0, bcm99450_a0, bcm99420_a0, "BCM99420", "BCM99420", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM99410_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM99410, BROADCOM_VENDOR_ID, 0x9410, DNXC_A0_REV_ID, + 0, 0, + bcm99450_a0, bcm99450_a0, bcm99410_a0, "BCM99410", "BCM99410", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM99430_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM99430, BROADCOM_VENDOR_ID, 0x9430, DNXC_A0_REV_ID, + 0, 0, + bcm99450_a0, bcm99450_a0, bcm99430_a0, "BCM99430", "BCM99430", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM994E0_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM994E0, BROADCOM_VENDOR_ID, 0x94e0, DNXC_A0_REV_ID, + 0, 0, + bcm99450_a0, bcm99450_a0, bcm994e0_a0, "BCM994E0", "BCM994E0", "Multilayer Switch", 0, 0) +#endif +#endif + +#if BCMDRD_CONFIG_INCLUDE_BCM88690_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +BCMDRD_DEVLIST_ENTRY(BCM88690, BROADCOM_VENDOR_ID, JERICHO2_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88690_a0, bcm88690_a0, bcm88690_a0, "JERICHO2", "BCM88690", "Multilayer Switch", 0, 0) +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88690_B0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM88690, BROADCOM_VENDOR_ID, JERICHO2_DEVICE_ID, DNXC_B0_REV_ID, + 0, 0, + bcm88690_a0, bcm88690_a0, bcm88690_b0, "JERICHO2", "BCM88690", "Multilayer Switch", 0, 0) +BCMDRD_DEVLIST_ENTRY(BCM88690, BROADCOM_VENDOR_ID, JERICHO2_DEVICE_ID, DNXC_B1_REV_ID, + 0, 0, + bcm88690_a0, bcm88690_a0, bcm88690_b1, "JERICHO2", "BCM88690", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88800_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM88800, BROADCOM_VENDOR_ID, J2C_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88690_a0, bcm88690_a0, bcm88800_a0, "J2C", "BCM88800", "Multilayer Switch", 0, 0) +BCMDRD_DEVLIST_ENTRY(BCM88820, BROADCOM_VENDOR_ID, J2C_2ND_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88690_a0, bcm88690_a0, bcm88820_a0, "J2C_2ND", "BCM88820", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88850_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM88850, BROADCOM_VENDOR_ID, J2P_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88690_a0, bcm88690_a0, bcm88850_a0, "J2P", "BCM88850", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88830_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM88830, BROADCOM_VENDOR_ID, J2X_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88690_a0, bcm88690_a0, bcm88830_a0, "J2X", "BCM88830", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88480_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM88480, BROADCOM_VENDOR_ID, Q2A_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88690_a0, bcm88690_a0, bcm88480_a0, "Q2A", "BCM88480", "Multilayer Switch", 0, 0) +BCMDRD_DEVLIST_ENTRY(BCM88280, BROADCOM_VENDOR_ID, Q2U_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88690_a0, bcm88690_a0, bcm88280_a0, "Q2U", "BCM88280", "Multilayer Switch", 0, 0) +BCMDRD_DEVLIST_ENTRY(BCM88290, BROADCOM_VENDOR_ID, Q2U_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88690_a0, bcm88690_a0, bcm88290_a0, "Q2N", "BCM88290", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88480_B0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM88480, BROADCOM_VENDOR_ID, Q2A_DEVICE_ID, DNXC_B0_REV_ID, + 0, 0, + bcm88690_a0, bcm88690_a0, bcm88480_b0, "Q2A", "BCM88480", "Multilayer Switch", 0, 0) +BCMDRD_DEVLIST_ENTRY(BCM88280, BROADCOM_VENDOR_ID, Q2U_DEVICE_ID, DNXC_B0_REV_ID, + 0, 0, + bcm88690_a0, bcm88690_a0, bcm88280_b0, "Q2U", "BCM88280", "Multilayer Switch", 0, 0) +BCMDRD_DEVLIST_ENTRY(BCM88290, BROADCOM_VENDOR_ID, Q2U_DEVICE_ID, DNXC_B0_REV_ID, + 0, 0, + bcm88690_a0, bcm88690_a0, bcm88290_b0, "Q2N", "BCM88290", "Multilayer Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88920_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +BCMDRD_DEVLIST_ENTRY(BCM88920, BROADCOM_VENDOR_ID, RAMON3_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88920_a0, bcm88920_a0, bcm88920_a0, "RAMON3", "BCM88920", "Fabric Switch", 0, 0) +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +BCMDRD_DEVLIST_ENTRY(BCM88910, BROADCOM_VENDOR_ID, RAMON2_DEVICE_ID, DNXC_A0_REV_ID, + 0, 0, + bcm88920_a0, bcm88920_a0, bcm88910_a0, "RAMON2", "BCM88910", "Fabric Switch", 0, 0) +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM99470_A0 == 1 || defined(BCMDRD_DEVLIST_OVERRIDE) +BCMDRD_DEVLIST_ENTRY(BCM99470, BROADCOM_VENDOR_ID, 0x9470, DNXC_A0_REV_ID, + 0, 0, + bcm99470_a0, bcm99470_a0, bcm99470_a0, "BCM99470", "BCM99470", "Fabric Switch", 0, 0) +#endif +/* End BCMDRD_DEVLIST_ENTRY Macros */ +#ifdef BCMDRD_DEVLIST_INCLUDE_ALL +#undef BCMDRD_DEVLIST_INCLUDE_ALL +#endif +#ifdef BCMDRD_DEVLIST_OVERRIDE +#undef BCMDRD_DEVLIST_OVERRIDE +#endif +#undef BCMDRD_DEVLIST_ENTRY +#endif /* BCMDRD_DEVLIST_ENTRY */ diff --git a/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_feature.h b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_feature.h new file mode 100644 index 0000000..2464124 --- /dev/null +++ b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_feature.h @@ -0,0 +1,116 @@ +/*! \file bcmdrd_feature.h + * + * DRD feature interface. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMDRD_FEATURE_H +#define BCMDRD_FEATURE_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif +#include + +/*! + * \brief Set a device feature as present. + * + * \param [in] unit Unit number. + * \param [in] feature Feature to enable for this device. + */ +extern void +bcmdrd_feature_enable(int unit, bcmdrd_feature_t feature); + +/*! + * \brief Set a device feature as not present. + * + * Passing feature \c BCMDRD_FT_ALL will clear all features. + * + * \param [in] unit Unit number. + * \param [in] feature Feature to disable for this device. + */ +extern void +bcmdrd_feature_disable(int unit, bcmdrd_feature_t feature); + +/*! + * \brief Check if a feature is present for a device. + * + * \param [in] unit Unit number + * \param [in] feature Feature to check for. + * + * \return true if feature is present, otherwise false. + */ +extern bool +bcmdrd_feature_enabled(int unit, bcmdrd_feature_t feature); + +/*! + * \brief Get the name of a feature. + * + * \param [in] unit Unit number + * \param [in] feature Feature to get the name for. + * + * \return Name of the specified feature. + */ +extern const char * +bcmdrd_feature_name(int unit, bcmdrd_feature_t feature); + +/*! + * \brief Test if running on real hardware. + * + * Convenience function to test that we are not running on a simulated + * or emulated device. + * + * \param [in] unit Unit number. + * + * \retval true Running on real hardware. + * \retval false Running on a simulated or emulated device. + */ +bool +bcmdrd_feature_is_real_hw(int unit); + +/*! + * \brief Test if running on a simulated device. + * + * Convenience function to test if we are running on a simulated + * device. + * + * \param [in] unit Unit number. + * + * \retval true Running on a simulated device. + * \retval false Running on real hardware or an emulated device. + */ +bool +bcmdrd_feature_is_sim(int unit); + +#endif /* BCMDRD_FEATURE_H */ diff --git a/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_feature_enum.h b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_feature_enum.h new file mode 100644 index 0000000..a3eb43e --- /dev/null +++ b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_feature_enum.h @@ -0,0 +1,236 @@ +/* + * DO NOT EDIT THIS FILE! + * This file is auto-generated. + * Edits to this file will be lost when it is regenerated. + * Tool: INTERNAL/drd/gen-feature.pl + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMDRD_FEATURE_ENUM_H +#define BCMDRD_FEATURE_ENUM_H + +#include + +/*! \file bcmdrd_feature_enum.h */ + +/*! + * Device features which are shared across all device families. + */ +typedef enum bcmdrd_feature_e { + + /*! + * This value can be passed to \ref bcmdrd_feature_disable to + * clear all features. + */ + BCMDRD_FT_ALL = 0, + + /*! + * Device is connected to an active simulator like BCMSIM and + * typically via the PLI protocol. An active simulator supports + * most hardware features including DMA and interrupts, but it + * will be much slower than real hardware. + */ + BCMDRD_FT_ACTIVE_SIM, + + /*! + * Device includes the Broadscan network telemetry engine. + */ + BCMDRD_FT_BROADSCAN, + + /*! + * Device HMI is based on iProc with CMICd. + */ + BCMDRD_FT_CMICD, + + /*! + * Device HMI is based on iProcR with 2nd generation CMICx. + */ + BCMDRD_FT_CMICR, + + /*! + * Device HMI is based on iProcR with 2nd generation CMICx v2. + */ + BCMDRD_FT_CMICR2, + + /*! + * Device HMI is based on iProc with CMICx. + */ + BCMDRD_FT_CMICX, + + /*! + * Device HMI is based on iProc with CMICx v2. + */ + BCMDRD_FT_CMICX2, + + /*! + * Device supports Channelization over Ethernet, which enables + * advanced traffic management for line cards via a backplane + * control switch. + */ + BCMDRD_FT_COE, + + /*! + * Device supports cut-through switching, i.e. a packet may be + * forwarded before the entire packet has been received. + */ + BCMDRD_FT_CUT_THRU, + + /*! + * Device supports Distributed Load Balancing across aggregated + * links. + */ + BCMDRD_FT_DLB, + + /*! + * Device is connected to an emulator like Quickturn, which will + * operate like real silicon, although many operations will be + * slower. The emulator is often limited in scope, e.g. reduced + * port count, no SerDes support, no embedded CPUs, etc. + */ + BCMDRD_FT_EMUL, + + /*! + * Device supports flex-code, which is micro-code that defines the + * device hardware behavior. Typically, flex-code is used to + * enable specific networking capabilities in hardware. + */ + BCMDRD_FT_FLEXCODE, + + /*! + * Device includes hardware flow tracking support to enable + * IPFIX-compliant monitoring applications like BroadView. + */ + BCMDRD_FT_FLOWTRACKER, + + /*! + * Device includes a Hardware License Authenticator (HLA) block, + * which provides the ability to enable additional switch features + * by downloading a license file to the HLA block. + */ + BCMDRD_FT_HLA, + + /*! + * Device HMI is iProc-based. + */ + BCMDRD_FT_IPROC, + + /*! + * Device supports Kernel Networking (KNET) mode where the + * low-level packet I/O is handled by a system device driver such + * as a Linux kernel driver. When operating in KNET mode, the SDK + * will interact with the system device driver instead of the raw + * hardware interface when performing packet I/O. + */ + BCMDRD_FT_KNET, + + /*! + * Device supports hardware learning of L2 MAC addresses, i.e. the + * source MAC address of an incoming packet is stored in a + * hardware table alongside the ingress port number. + */ + BCMDRD_FT_L2_HW_LEARN, + + /*! + * Device supports the Broadcom Process Monitoring library + * (LIB_PM), which is a standardized interface to monitor + * voltages, currents and other low-level aspects of the device. + */ + BCMDRD_FT_LIB_PM, + + /*! + * Device supports the MACSEC protocol in hardware. + */ + BCMDRD_FT_MACSEC, + + /*! + * Host CPU bus does not support DMA. This feature typically + * indicates that the device is connected to the host CPU via a + * simple boot or debug interface like SPI. + */ + BCMDRD_FT_NO_DMA, + + /*! + * Device is connected to a passive simulator like XGSSIM. This + * means that you always read what you write, and that DMA, + * interrupts and any kind of HMI broadcast (SBUS, pipes, etc.) + * are unsupported. + */ + BCMDRD_FT_PASSIVE_SIM, + + /*! + * Device is connected to a PHY simulator via the PHYMOD API. This + * feature enables more comprehensive testing capabilities in a + * simulation environment without real SerDes support. + */ + BCMDRD_FT_PHYMOD_SIM, + + /*! + * Device supports Visibility Compute Accelerator engine. + */ + BCMDRD_FT_VCA, + + /*! + * Number of features. + */ + BCMDRD_FT_COUNT + +} bcmdrd_feature_t; + +/*! + * Device features names for array initialization. + */ +#define BCMDRD_FT_NAMES \ + "ALL", \ + "ACTIVE_SIM", \ + "BROADSCAN", \ + "CMICD", \ + "CMICR", \ + "CMICR2", \ + "CMICX", \ + "CMICX2", \ + "COE", \ + "CUT_THRU", \ + "DLB", \ + "EMUL", \ + "FLEXCODE", \ + "FLOWTRACKER", \ + "HLA", \ + "IPROC", \ + "KNET", \ + "L2_HW_LEARN", \ + "LIB_PM", \ + "MACSEC", \ + "NO_DMA", \ + "PASSIVE_SIM", \ + "PHYMOD_SIM", \ + "VCA", \ + "COUNT" + +#endif /* BCMDRD_FEATURE_ENUM_H */ diff --git a/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_hal.h b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_hal.h new file mode 100644 index 0000000..47eb94d --- /dev/null +++ b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_hal.h @@ -0,0 +1,1153 @@ +/*! \file bcmdrd_hal.h + * + * Hardware abstraction layer. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMDRD_HAL_H +#define BCMDRD_HAL_H + +#include + +/*! Type of bus by which the device is connected to the host CPU */ +typedef enum bcmdrd_hal_bus_type_e { + BCMDRD_BT_UNKNOWN, + BCMDRD_BT_PCI, + BCMDRD_BT_AXI, + BCMDRD_BT_RCPU, + BCMDRD_BT_COUNT +} bcmdrd_hal_bus_type_t; + +/*! Special I/O considerations */ +#define BCMDRD_HAL_IO_F_MSI (1 << 0) + +/*! Maximum number of I/O spaces supported for each device. */ +#define BCMDRD_NUM_PHYS_ADDR 4 + +/*! + * \brief I/O space types used by read/write access functions. + * + * The generic device read/write functions may be used to access + * different types of I/O resources. Instead of defining multiple sets + * of read/write functions for different types of I/O, we use a simple + * enum to define the access type. + */ +typedef enum bcmdrd_hal_io_space_e { + + /*! Primary I/O space for the device. */ + BCMDRD_IOS_DEFAULT, + + /*! Bus-specific I/O space, e.g. PCI configuration space. */ + BCMDRD_IOS_BUS, + + /*! CPU I/O space, e.g. iProc AXI space. */ + BCMDRD_IOS_CPU, + + /*! Network I/O space. */ + BCMDRD_IOS_NET, + + /*! Number of I/O space types. */ + BCMDRD_IOS_COUNT + +} bcmdrd_hal_io_space_t; + +/*! + * \brief Memory pool information types. + * + * The types of information that can be extracted for debugging, + * testing and statistical purposes. + */ +typedef enum bcmdrd_hal_dma_info_e { + + /*! + * Total amount of DMA memory available (in bytes), i.e. the size + * of any reserved DMA memory plus the size of the pool of DMA + * memory used for dynamic allocations. + */ + BCMDRD_HAL_DMA_INFO_MEM_TOTAL, + + /*! + * Size of reserved DMA memory, e.g. for HA purposes (in bytes). + */ + BCMDRD_HAL_DMA_INFO_MEM_RESERVED, + + /*! + * Largest amount of DMA memory in use since pool creation. This + * value includes all control overhead and allocation "holes", + * such that it can be use to estimate the required amount of DMA + * memory for a given system configuration. + */ + BCMDRD_HAL_DMA_INFO_MEM_MAX, + + /*! + * Amount of DMA memory currently allocated (in bytes). + */ + BCMDRD_HAL_DMA_INFO_USAGE, + + /*! + * DMA blocks are allocated from chunks of this size. + */ + BCMDRD_HAL_DMA_INFO_CHUNK_SIZE + +} bcmdrd_hal_dma_info_t; + +/*! + * \brief Generic device read function. + * + * This API is used by the device driver to access all types of device + * I/O spaces. + * + * \param [in] devh Application-provided device handle. + * \param [in] io_space Type of I/O space. + * \param [in] addr I/O address to access. + * \param [in] buf Buffer to store input. + * \param [in] size Size of input buffer (in bytes.) + * + * \retval 0 No errors. + * \retval -1 Error reading from device. + */ +typedef int (*bcmdrd_hal_read_f)(void *devh, bcmdrd_hal_io_space_t io_space, + uint32_t addr, void *buf, size_t size); + +/*! + * \brief Generic device write function. + * + * This API is used by the device driver to access all types of device + * I/O spaces. + * + * \param [in] devh Application-provided device handle. + * \param [in] io_space Type of I/O space. + * \param [in] addr I/O address to access. + * \param [in] buf Data to write. + * \param [in] size Size of write data (in bytes.) + * + * \retval 0 No errors. + * \retval -1 Error writing to device. + */ +typedef int (*bcmdrd_hal_write_f)(void *devh, bcmdrd_hal_io_space_t io_space, + uint32_t addr, void *buf, size_t size); + +/*! + * \brief Map device I/O space into CPU memory space. + * + * In order to support high-performance memory-mapped I/O access, the + * application must provide functions to map and unmap device I/O + * space. + * + * \param [in] offset Physical address to map. + * \param [in] size Size of I/O space to be mapped. + * + * \return Pointer to mapped I/O space or NULL if an error occured. + */ +typedef void *(*bcmdrd_hal_ioremap_f)(uint64_t offset, size_t size); + +/*! + * \brief Unmap device I/O space from CPU memory space. + * + * Unmap I/O memory mapped by \ref bcmdrd_hal_ioremap_f. + * + * \param [in] iomem CPU memory space to be unmapped. + * + * \return Nothing. + */ +typedef void (*bcmdrd_hal_iounmap_f)(void *iomem, size_t size); + +/*! + * \brief System abstraction for PIO access to a device. + * + * As a minimum, an application must provide methods for programmed + * I/O (PIO) access to a device. The application must provide either + * a set of read/write functions or at least one physical I/O base + * address along with a set of I/O remapping functions. + */ +typedef struct bcmdrd_hal_io_s { + + /*! Host CPU PIO access requires byte-swap. */ + bool byte_swap_pio; + + /*! Host CPU packet DMA requires byte-swap. */ + bool byte_swap_packet_dma; + + /*! Host CPU non-packet DMA requires byte-swap. */ + bool byte_swap_non_packet_dma; + + /*! Host bus type by which the switch device is connected. */ + bcmdrd_hal_bus_type_t bus_type; + + /*! I/O flags (BCMDRD_HAL_IO_F_xxx). */ + uint32_t flags; + + /*! Physical address(es) for memory-mapped I/O. */ + uint64_t phys_addr[BCMDRD_NUM_PHYS_ADDR]; + + /*! Device handle for I/O call-backs. */ + void *devh; + + /*! Device read function. */ + bcmdrd_hal_read_f read; + + /*! Device write function. */ + bcmdrd_hal_write_f write; + + /*! Map I/O memory into CPU space. */ + bcmdrd_hal_ioremap_f ioremap; + + /*! Unmap I/O memory from CPU space. */ + bcmdrd_hal_iounmap_f iounmap; + +} bcmdrd_hal_io_t; + + +/*! + * \brief Allocate DMA memory. + * + * This function must allocate a block of physically contiguous + * memory. + * + * If \c dma_addr is not NULL, then the memory must be cache-coherent + * as well and the physical bus address must be returned in \c + * dma_addr. The returned \c dma_addr can be used to program the device + * DMA engine. + * + * This function will return the logical address of the DMA memory block. + * + * \param [in] devh Application-provided device handle. + * \param [in] size Size of DMA memory block (in bytes.) + * \param [out] dma_addr Physical address of cache-coherent DMA memory block + * if not NULL. + * + * \return Logical address of DMA memory block or NULL if an error occurred. + */ +typedef void *(*bcmdrd_hal_dma_alloc_f)(void *devh, size_t size, + uint64_t *dma_addr); + +/*! + * \brief Free DMA memory. + * + * This function must free memory blocks allocated with \ref + * bcmdrd_hal_dma_alloc_f. + * + * \param [in] devh Application-provided device handle. + * \param [in] size Size of DMA memory block (in bytes.) + * \param [in] dma_mem Logical address of DMA memory block. + * \param [in] dma_addr Physical address of DMA memory block. + * + * \return Nothing. + */ +typedef void (*bcmdrd_hal_dma_free_f)(void *devh, size_t size, + void *dma_mem, uint64_t dma_addr); + +/*! + * \brief Map DMA memory for a device. + * + * This function must be called before a DMA operation on + * (potentially) non-coherent memory. + * + * If \c to_dev is true, the function must ensure that the DMA buffer + * is flushed from the CPU cache to main memory. + * + * The returned physical address can be used to program the device + * DMA engine. + * + * \param [in] devh Application-provided device handle. + * \param [in] dma_mem CPU address of memory block to map. + * \param [in] size Size of memory block to map. + * \param [in] to_dev True if transferring from host memory to device. + * + * \return Physical bus address or 0 if error. + */ +typedef uint64_t (*bcmdrd_hal_dma_map_f)(void *devh, void *dma_mem, + size_t size, bool to_dev); + +/*! + * \brief Unmap DMA memory for a device. + * + * This function must be called after a DMA operation on (potentially) + * non-coherent memory. + * + * If \c to_dev is false, the function must ensure that any CPU cache + * lines associated with the DMA buffer are invalidated. + * + * The \c dma_mem and \c size parameters must match the values used to + * map the memory. + * + * \param [in] devh Application-provided device handle. + * \param [in] dma_addr Physical bus address of mapped memory. + * \param [in] size Size of memory block to unmap. + * \param [in] to_dev True if transferring from host memory to device. + * + * \return Nothing. + */ +typedef void (*bcmdrd_hal_dma_unmap_f)(void *devh, uint64_t dma_addr, + size_t size, bool to_dev); + +/*! + * \brief Get DMA memory information. + * + * Optional information that can be requested from the + * application-provided DMA memory allocator. Please refer to \ref + * bcmdrd_hal_dma_info_t for a description of the types of information + * that may be requested. + * + * \param [in] devh Application-provided device handle. + * \param [in] type Information type. + * \param [out] data Information data. + * + * \retval 0 No errors. + * \retval -1 Unsupported information type. + */ +typedef int (*bcmdrd_hal_dma_info_get_f)(void *devh, + bcmdrd_hal_dma_info_t type, + uint32_t *data); + +/*! + * \brief System abstraction for DMA memory management. + */ +typedef struct bcmdrd_hal_dma_s { + + /*! Device handle for I/O call-backs. */ + void *devh; + + /*! Allocate DMA memory. */ + bcmdrd_hal_dma_alloc_f dma_alloc; + + /*! Free coherent DMA memory. */ + bcmdrd_hal_dma_free_f dma_free; + + /*! Map non-coherent DMA memory. */ + bcmdrd_hal_dma_map_f dma_map; + + /*! Unmap non-coherent DMA memory. */ + bcmdrd_hal_dma_unmap_f dma_unmap; + + /*! Get DMA memory information from system implementation. */ + bcmdrd_hal_dma_info_get_f dma_info_get; + +} bcmdrd_hal_dma_t; + + +/*! + * \brief Interrupt handler function type. + * + * Used for registering device driver interrupt handlers with the + * system. + * + * \param [in] data Interrupt handler context. + * + * \return Nothing. + */ +typedef void (*bcmdrd_hal_isr_func_f)(void *data); + +/*! + * \brief Register interrupt handler with the system. + * + * The \c irq_num parameter is used to associate the interrupt handler + * with a specific interrupt line, if the device supports multiple + * interrupt lines (e.g. MSI vectors) per device. + * + * \param [in] devh Application-provided device handle. + * \param [in] irq_num Interrupt line number (starting at zero). + * \param [in] isr_func Interrupt handler function. + * \param [in] isr_data Interrupt handler context. + * + * \retval 0 Handler successfully registered. + * \retval -1 Error connecting to interrupt. + */ +typedef int (*bcmdrd_hal_intr_connect_f)(void *devh, int irq_num, + bcmdrd_hal_isr_func_f isr_func, + void *isr_data); + +/*! + * \brief Unregister interrupt handler with the system. + * + * \param [in] devh Application-provided device handle. + * \param [in] irq_num Interrupt line number (starting at zero). + * + * \retval 0 Handler successfully unregistered. + * \retval -1 Error disconnecting from interrupt. + */ +typedef int (*bcmdrd_hal_intr_disconnect_f)(void *devh, int irq_num); + +/*! + * \brief Callback function for interrupt synchronization. + * + * A function of this type maybe serialized with the interrupt handler + * context if called through the \ref bcmdrd_hal_intr_sync API. + * + * \param [in] data Thread context. + * + * \return Return value is application-specific. + */ +typedef int (*bcmdrd_intr_sync_cb_f)(void *data); + +/*! + * \brief Synchronize thread execution with interrupt context. + * + * This function is called from thread context when concurrent data + * access from thread and interrupt context must be prevented. The + * underlying function will ensure that the execution of the provided + * callback function is serialized with the interrupt handler + * function. + * + * The \c irq_num parameter is used to associate the access with a + * specific interrupt line, if the device supports multiple interrupt + * lines (e.g. MSI vectors) per device. + * + * \param [in] devh Application-provided device handle. + * \param [in] irq_num Interrupt line number (starting at zero). + * \param [in] cb Function to be serialized with interrupt context. + * \param [in] data Pass-through data for \c cb function. + * + * \return Return value of callback function. + */ +typedef int (*bcmdrd_hal_intr_sync_f)(void *devh, int irq_num, + bcmdrd_intr_sync_cb_f cb, void *data); + +/*! Maximum number of interrupt registers per IRQ line. */ +#define BCMDRD_HAL_IRQ_REGS_MAX 16 + +/*! + * \name Interrupt register access flags. + * \anchor BCMDRD_HAL_IRQ_REG_F_xxx + */ + +/*! \{ */ + +/*! Interrupt mask register is of type "write 1 to clear". */ +#define BCMDRD_HAL_IRQ_REG_F_W1TC (1 << 0) + +/*! + * Indicates that the interrupt status register is a bitwise AND of + * mask and raw status, i.e. there is no need to read the interrupt + * mask register to determine which interrupts are active. + */ +#define BCMDRD_HAL_IRQ_REG_F_MASKED (1 << 1) + +/*! + * Indicates that the \c kmask value is valid. This is mainly to + * distinguish a \c kmask value of zero from the \c kmask value being + * uninitialized, as this matters during a warm boot, where we do not + * want to disturb e.g. an active Linux KNET driver. + */ +#define BCMDRD_HAL_IRQ_REG_F_KMASK (1 << 2) + +/*! \} */ + +/*! + * \brief Interrupt status register information. + * + * This structure defines an interrupt status register and an + * associated interrupt mask register. + * + * An interrupt service routine (ISR) can read these registers to + * determine whether any interrupts are active. + * + * An optional kernel mask (\c kmask) can be used to indicate that + * certain interrupts are handled by a secondary interrupt handler in + * the system kernel (for example a Linux KNET driver). + */ +typedef struct bcmdrd_hal_irq_reg_s { + + /*! Interrupt status register offset. */ + uint32_t status_reg; + + /*! Interrupt mask register offset. */ + uint32_t mask_reg; + + /*! Mask of interrupts handled by primary (SDK) ISR. */ + uint32_t umask; + + /*! Mask of interrupts handled by secondary (system) ISR. */ + uint32_t kmask; + + /*! Flags for special handling (\ref BCMDRD_HAL_IRQ_REG_F_xxx). */ + uint32_t flags; + +} bcmdrd_hal_irq_reg_t; + +/*! + * \name Interrupt ACK register access flags. + * \anchor BCMDRD_HAL_IRQ_ACK_F_xxx + */ + +/*! \{ */ + +/*! ACK registers resides in PCI bridge I/O window. */ +#define BCMDRD_HAL_IRQ_ACK_F_PAXB (1 << 0) + +/*! \} */ + +/*! + * \brief Interrupt ACK register information. + * + * An interrupt service routine (ISR) can write ACK value to + * corresponding ACK register to acknowledge interrupt. + * + */ +typedef struct bcmdrd_hal_irq_ack_reg_s { + + /*! Interrupt ACK register offset. */ + uint32_t ack_reg; + + /*! Interrupt ACK value. */ + uint32_t ack_val; + + /*! Flags to indicate ack_reg resides in PCI bridge window. */ + uint32_t flags; + +} bcmdrd_hal_irq_ack_reg_t; + +/*! + * \brief Interrupt handler information. + * + * This structure is used to provide information to a thread-based + * interrupt handler. + * + * The thread-based interrupt handler will typically rely on a primary + * interrupt service routine (ISR), which will mask off active + * interrupts and launch the interrupt handler thread. + * + * The information in this structure is primarily used to allow the + * ISR to access the relevant hardware registers. + * + * The interrupt controller register information only needs to be + * populated if the interrupt controller is separate from the main + * switch device. + */ +typedef struct bcmdrd_hal_intr_info_s { + + /*! Physical address of memory-mapped device registers. */ + uint64_t piowin_addr; + + /*! Size of memory-mapped device register window. */ + uint32_t piowin_size; + + /*! Physical address of interrupt controller registers. */ + uint64_t iiowin_addr; + + /*! Size of memory-mapped interrupt controller register window. */ + uint32_t iiowin_size; + + /*! Physical address of PCI bridge registers. */ + uint64_t paxbwin_addr; + + /*! Size of memory-mapped PCI bridge register window. */ + uint32_t paxbwin_size; + + /*! Number of interrupt status/mask registers. */ + uint32_t num_irq_regs; + + /*! Detailed interrupt status/mask register information. */ + bcmdrd_hal_irq_reg_t irq_regs[BCMDRD_HAL_IRQ_REGS_MAX]; + + /*! Interrupt ACK register/value information. */ + bcmdrd_hal_irq_ack_reg_t irq_ack; + +} bcmdrd_hal_intr_info_t; + +/*! + * \brief Configure interrupt handler thread. + * + * This function is used to configure a thread-based interrupt handler + * for environments, where interrupts cannot be handled in true + * interrupt context. + * + * The \c irq_num parameter is used to associate the interrupt + * configuration with a specific interrupt line, if the device + * supports multiple interrupt lines (e.g. MSI vectors) per device. + * + * \param [in] devh Application-provided device handle. + * \param [in] irq_num Interrupt line number (starting at zero). + * \param [in] intr_info Interrupt control information. + * + * \retval 0 Interrupt thread successfully configured. + * \retval -1 Error configuring interrupt thread. + */ +typedef int (*bcmdrd_hal_intr_configure_f)(void *devh, int irq_num, + bcmdrd_hal_intr_info_t *intr_info); + +/*! + * \brief Write shared interrupt mask register. + * + * This function is used by the user-mode interrupt handler when a + * shared interrupt mask register needs to be updated. + * + * Since the register is shared with another (kernel mode) interrupt + * handler, access must be protected by a lock. + * + * \param [in] devh Application-provided device handle. + * \param [in] irq_num Interrupt line number (starting at zero). + * \param [in] offs Interrupt mask register offset. + * \param [in] val New value to write to register. + * + * \retval 0 No errors + * \retval <0 Something went wrong. + */ +typedef int (*bcmdrd_hal_intr_mask_write_f)(void *devh, int irq_num, + uint32_t offs, uint32_t val); + +/*! + * \brief Initialize system interrupts. + * + * This function is used by the interrupt driver to allocate multiple + * interrupt lines for a single device (if supported by the system). + * + * Some systems may benefit from having multiple per-device interrupt + * lines, and the interrupt driver can use the \c irq_max parameter + * for this purpose by using a value greater than one. + * + * This function is optional and if unsupported, a single interrupt + * line is assumed. + * + * \param [in] devh Application-provided device handle. + * \param [in] irq_max Desired number of per-device interrupt lines. + * \param [out] num_irq Actual number of per-device interrupt lines. + * + * \retval 0 No errors + * \retval <0 Something went wrong. + */ +typedef int (*bcmdrd_hal_intr_init_f)(void *devh, int irq_max, int *num_irq); + +/*! + * \brief System abstraction for interrupt control. + */ +typedef struct bcmdrd_hal_intr_s { + + /*! Device handle for interrupt control call-backs. */ + void *devh; + + /*! Initialize system interrupts. */ + bcmdrd_hal_intr_init_f intr_init; + + /*! Connect to system interrupt handler. */ + bcmdrd_hal_intr_connect_f intr_connect; + + /*! Disconnect from system interrupt handler. */ + bcmdrd_hal_intr_disconnect_f intr_disconnect; + + /*! Synchronize thread execution with interrupt handler. */ + bcmdrd_hal_intr_sync_f intr_sync; + + /*! Configure system interrupt handler. */ + bcmdrd_hal_intr_configure_f intr_configure; + + /*! Write to shared interrupt mask register. */ + bcmdrd_hal_intr_mask_write_f intr_mask_write; + +} bcmdrd_hal_intr_t; + +/*! + * \brief Initialize 32-bit device register access. + * + * Initialize read/write access to primary device I/O registers such + * as memory-mapped PCI registers. + * + * If the installed CM I/O structure \ref bcmdrd_hal_io_t supports + * memory-mapped registers, then the specified I/O window will be + * mapped. First I/O window (typically PCI BAR0) has index 0, next I/O + * window has index 1, and so forth. + * + * If the I/O structure does not support memory-mapped registers, then + * the read/write functions vectors in the CM I/O structure will be + * used for 32-bit register access. + * + * \param [in] unit Unit number. + * \param [in] iomem_idx Device I/O window to map (if supported). + * \param [in] size Size of device I/O window to map (in bytes). + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_EXISTS 32-bit register access already initialized. + * \retval SHR_E_INIT CM I/O structure invalid or missing. + * \retval SHR_E_NOT_FOUND Specified I/O window not supported. + * \retval SHR_E_FAIL Memory-map failed. + */ +extern int +bcmdrd_hal_reg32_init(int unit, unsigned int iomem_idx, size_t size); + +/*! + * \brief Clean up resources for 32-bit register access. + * + * Free all resources used by 32-bit register access and reset + * associated data structures. + * + * \param [in] unit Unit number. + * + * \retval SHR_E_NONE No errors. + */ +extern int +bcmdrd_hal_reg32_cleanup(int unit); + +/*! + * \brief Read 32-bit device register. + * + * Read 32-bit primary device register, typically a memory-mapped PCI + * register. + * + * \param [in] unit Unit number. + * \param [in] addr Register offset relative to register base. + * \param [out] val Data read from register. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_FAIL I/O read returned an error. + */ +extern int +bcmdrd_hal_reg32_read(int unit, uint32_t addr, uint32_t *val); + +/*! + * \brief Write 32-bit device register. + * + * Write 32-bit primary device register, typically a memory-mapped PCI + * register. + * + * \param [in] unit Unit number. + * \param [in] addr Register offset relative to register base. + * \param [in] val Data to write to register. + */ +extern int +bcmdrd_hal_reg32_write(int unit, uint32_t addr, uint32_t val); + +/*! iProc configuration (primarily used for PCI-AXI bridge) */ +typedef struct bcmdrd_hal_iproc_cfg_s { + + /*! iProc profile version. */ + uint32_t iproc_ver; + + /*! iProc DMA high bits configuration. */ + uint32_t dma_hi_bits; + +} bcmdrd_hal_iproc_cfg_t; + +/*! + * \brief Initialize 32-bit iProc register access. + * + * Initialize read/write access to iProc I/O registers. + * + * If the installed CM I/O structure \ref bcmdrd_hal_io_t supports + * memory-mapped registers, then the specified I/O window will be + * mapped if the bus type is PCI. First I/O window (typically PCI + * BAR0) has index 0, next I/O window has index 1, and so forth. If + * the bus type is AXI (ARM interconnect), then a number of + * sub-windows to thew full AXI memory space will be mapped on-demand. + * + * If the I/O structure does not support memory-mapped registers, then + * the read/write functions vectors in the CM I/O structure will be + * used for 32-bit register access. + * + * \param [in] unit Unit number. + * \param [in] iomem_idx Device I/O window to map (if supported). + * \param [in] size Size of device I/O window to map (in bytes). + * \param [in] icfg iProc configuration for PAXB initialization. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_EXISTS 32-bit register access already initialized. + * \retval SHR_E_INIT CM I/O structure invalid or missing. + * \retval SHR_E_NOT_FOUND Specified I/O window not supported. + * \retval SHR_E_FAIL Memory-map failed. + * \retval SHR_E_UNAVAIL Device has no iProc registers. + */ +extern int +bcmdrd_hal_iproc_init(int unit, unsigned int iomem_idx, size_t size, + bcmdrd_hal_iproc_cfg_t *icfg); + +/*! + * \brief Clean up resources for iProc-bit register access. + * + * Free all resources used by iProc register access and reset + * associated data structures. + * + * \param [in] unit Unit number. + * + * \retval SHR_E_NONE No errors. + */ +extern int +bcmdrd_hal_iproc_cleanup(int unit); + +/*! + * \brief Get physical address base for iProc register block. + * + * This function is used to get the physical base address to map into + * host memory space in order to access a block of iProc registers. + * + * The function will take into consideration whether the registers are + * accessed directly across the AXI bus or through a PCI BAR + * sub-window. + * + * If the access is done through a PCI BAR sub-window, the sub-window + * will be locked in order to prevent accidental remapping through the + * PAXB map registers. + * + * \param [in] unit Unit number. + * \param [in] paxb_base PCI BAR address for iProc access. + * \param [in] axi_addr Any AXI address within the register block. + * + * \return Physical address to map into host memory space. + */ +extern uint64_t +bcmdrd_hal_iproc_phys_base_get(int unit, uint64_t paxb_base, uint32_t axi_addr); + +/*! + * \brief Get host memory window for regsiter access. + * + * Non-CMIC drivers can use this function to reserve an iProc + * sub-window for exclusive use. This means that the sub-window will + * never be remapped, and that the driver can use direct register + * access instead of going through the DRD HAL API for each access. + * + * \param [in] unit Unit number. + * \param [in] axi_base 4K-aligned base address in AXI space. + * + * \retval Pointer to mapped registers or NULL if error. + */ +volatile uint32_t * +bcmdrd_hal_iproc_mmap_get(int unit, uint32_t axi_base); + +/*! + * \brief Read 32-bit iProc register. + * + * Since the full 32-bit iProc (AXI) memory space cannot be exposed + * directly, specific register ranges are exposed through a number of + * sub-windows. In case a register access falls outside any of the + * existing sub-windows, a new sub-window will be allocated, or an + * existing sub-window will be reconfigured. + * + * \param [in] unit Unit number. + * \param [in] addr Register offset relative to register base. + * \param [out] val Data read from register. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_FAIL I/O read returned an error. + */ +extern int +bcmdrd_hal_iproc_read(int unit, uint32_t addr, uint32_t *val); + +/*! + * \brief Write 32-bit iProc register. + * + * Refer to \ref bcmdrd_hal_iproc_read for a description of the iProc + * sub-window management. + * + * \param [in] unit Unit number. + * \param [in] addr Register offset relative to register base. + * \param [in] val Data to write to register. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_FAIL I/O read returned an error. + */ +extern int +bcmdrd_hal_iproc_write(int unit, uint32_t addr, uint32_t val); + +/*! + * \brief Read 64-bit iProc register. + * + * If supported by the host CPU, the access will be performed + * atomically. + * + * Refer to \ref bcmdrd_hal_iproc_read for a description of the iProc + * sub-window management. + * + * \param [in] unit Unit number. + * \param [in] addr Register offset relative to register base. + * \param [out] val64 Data read from register. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_FAIL I/O read returned an error. + */ +extern int +bcmdrd_hal_iproc_read64(int unit, uint32_t addr, uint64_t *val64); + +/*! + * \brief Write 64-bit iProc register. + * + * If supported by the host CPU, the access will be performed + * atomically. + * + * Refer to \ref bcmdrd_hal_iproc_read for a description of the iProc + * sub-window management. + * + * \param [in] unit Unit number. + * \param [in] addr Register offset relative to register base. + * \param [in] val64 Data to write to register. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_FAIL I/O read returned an error. + */ +extern int +bcmdrd_hal_iproc_write64(int unit, uint32_t addr, uint64_t val64); + +/*! + * \brief Set MSI interrupt auto-clear mode. + * + * Selects whether MSI interrupts should be cleared manually or not. + * + * \param [in] unit Unit number. + * \param [in] auto_clr Set zero to disable MSI auto-clear mode. + * + * \retval SHR_E_NONE No errors. + */ +extern int +bcmdrd_hal_iproc_msi_auto_clear_set(int unit, int auto_clr); + +/*! + * \brief Set MSI interrupt auto-clear clear delay timer. + * + * Assign delay timer value to clear specific MSI interrupt line. + * This is only used for MSI auto-clear mode. + * + * \param [in] unit Unit number. + * \param [in] intr_num MSI interrupt line. + * \param [in] delay_us Delay time in microsecond unit. + * + * \retval SHR_E_NONE No errors. + */ +extern int +bcmdrd_hal_iproc_msi_auto_clear_delay_set(int unit, int intr_num, int delay_us); + +/*! + * \brief Allocate DMA memory. + * + * This function must allocate a block of physically contiguous + * memory. + * + * If \c dma_addr is not NULL, then the memory must be cache-coherent + * as well and the physical bus address must be returned in \c + * dma_addr. The returned \c dma_addr can be used to program the device + * DMA engine. + * + * This function will return the logical address of the DMA memory block. + * + * \param [in] unit Unit number. + * \param [in] size Size of DMA memory block (in bytes.) + * \param [in] s Signature string for resource tracking. + * \param [out] dma_addr Physical address of cache-coherent DMA memory block + * if not NULL. + * + * \return Logical address of DMA memory block or NULL if an error occurred. + */ +extern void * +bcmdrd_hal_dma_alloc(int unit, size_t size, const char *s, uint64_t *dma_addr); + +/*! + * \brief Free DMA memory. + * + * This function must free memory blocks allocated with \ref + * bcmdrd_hal_dma_alloc_f. + * + * \param [in] unit Unit number. + * \param [in] size Size of DMA memory block (in bytes.) + * \param [in] dma_mem Pointer returned by \ref bcmdrd_hal_dma_alloc. + * \param [in] dma_addr Physical address of DMA memory block. + * + * \return Nothing. + */ +extern void +bcmdrd_hal_dma_free(int unit, size_t size, void *dma_mem, uint64_t dma_addr); + +/*! + * \brief Map DMA memory for a device. + * + * This function must be called before a DMA operation on + * (potentially) non-coherent memory. + * + * If \c to_dev is true, the function must ensure that the DMA buffer + * is flushed from the CPU cache to main memory. + * + * The returned \c dma_mem address can be used to program the device + * DMA engine. + * + * \param [in] unit Unit number. + * \param [in] dma_mem CPU address of memory block to map. + * \param [in] size Size of memory block to map. + * \param [in] to_dev True if transferring from host memory to device. + * + * \return Physical bus address or 0 if error. + */ +extern uint64_t +bcmdrd_hal_dma_map(int unit, void *dma_mem, size_t size, bool to_dev); + +/*! + * \brief Unmap DMA memory for a device. + * + * This function must be called after a DMA operation on (potentially) + * non-coherent memory. + * + * If \c to_dev is false, the function must ensure that any CPU cache + * lines associated with the DMA buffer are invalidated. + * + * The \c dma_addr and \c size parameters must match the values used to + * map the memory. + * + * \param [in] unit Unit number. + * \param [in] dma_addr Physical bus address of mapped memory. + * \param [in] size Size of memory block to unmap. + * \param [in] to_dev True if transferring from host memory to device. + * + * \return Nothing. + */ +extern void +bcmdrd_hal_dma_unmap(int unit, uint64_t dma_addr, size_t size, bool to_dev); + +/*! + * \brief Get DMA memory information. + * + * Optional information provided by the application-provided DMA + * memory allocator. Please refer to \ref bcmdrd_hal_dma_info_t for a + * description of the types of information that may be requested. + * + * \param [in] unit Unit number. + * \param [in] type Information type. + * \param [out] data Information data. + * + * \retval 0 No errors + */ +extern int +bcmdrd_hal_dma_info_get(int unit, bcmdrd_hal_dma_info_t type, uint32_t *data); + +/*! + * \brief Initialize system interrupts. + * + * This function is used by the user-mode interrupt driver to allocate + * multiple interrupt lines if supported by the system. + * + * Some systems may benefit from having multiple per-device interrupt + * lines, and the user mode driver can use the \c irq_max parameter + * for this purpose by using a value >1. + * + * \param [in] unit Unit number. + * \param [in] irq_max Desired number of per-device interrupt lines. + * \param [out] num_irq Actual number of per-device interrupt lines. + * + * \retval 0 No errors + * \retval <0 Something went wrong. + */ +extern int +bcmdrd_hal_intr_init(int unit, int irq_max, int *num_irq); + +/*! + * \brief Register interrupt handler with the system. + * + * The \c irq_num parameter is used to associate the interrupt + * handler with a specific interrupt line, if the device supports + * multiple interrupt lines (e.g. MSI vectors) per device. + * + * \param [in] unit Unit number. + * \param [in] irq_num Interrupt line number (starting at zero). + * \param [in] isr_func Interrupt handler function. + * \param [in] isr_data Interrupt handler context. + * + * \retval 0 Handler successfully registered. + * \retval <0 Error connecting to interrupt. + */ +extern int +bcmdrd_hal_intr_connect(int unit, int irq_num, + bcmdrd_hal_isr_func_f isr_func, void *isr_data); + +/*! + * \brief Unregister interrupt handler with the system. + * + * \param [in] unit Unit number. + * \param [in] irq_num Interrupt line number (starting at zero). + * + * \retval 0 Handler successfully unregistered. + * \retval <0 Error disconnecting from interrupt. + */ +extern int +bcmdrd_hal_intr_disconnect(int unit, int irq_num); + +/*! + * \brief Synchronize thread execution with interrupt context. + * + * This function is called from thread context when concurrent data + * access from thread and interrupt context must be prevented. The + * underlying function will ensure that the execution of the provided + * callback function is serialized with the interrupt handler + * function. + * + * The \c irq_num parameter is used to associate the access with a + * specific interrupt line, if the device supports multiple interrupt + * lines (e.g. MSI vectors) per device. + * + * \param [in] unit Unit number. + * \param [in] irq_num Interrupt line number (starting at zero). + * \param [in] cb Function to be serialized with interrupt context. + * \param [in] data Pass-through data for \c cb function. + * + * \retval 0 Handler successfully unregistered. + * \retval -1 Error disconnecting from interrupt. + */ +extern int +bcmdrd_hal_intr_sync(int unit, int irq_num, + bcmdrd_intr_sync_cb_f cb, void *data); + +/*! + * \brief Configure interrupt handler thread. + * + * This function is used to configure a thread-based interrupt handler + * for environments, where interrupts cannot be handled in true + * interrupt context. + * + * The \c irq_num parameter is used to associate the interrupt + * configuration with a specific interrupt line, if the device + * supports multiple interrupt lines (e.g. MSI vectors) per device. + * + * \param [in] unit Unit number. + * \param [in] irq_num Interrupt line number (starting at zero). + * \param [in] intr_info Interrupt control information. + * + * \retval 0 Interrupt thread successfully configured. + * \retval <0 Error configuring interrupt thread. + */ +extern int +bcmdrd_hal_intr_configure(int unit, int irq_num, + bcmdrd_hal_intr_info_t *intr_info); + +/*! + * \brief Write shared interrupt mask register. + * + * This function is used by the user-mode interrupt handler when a + * shared interrupt mask register needs to be updated. + * + * Since the register is shared with another (kernel mode) interrupt + * handler, access must be protected by a lock. + * + * \param [in] unit Unit number. + * \param [in] irq_num Interrupt line number (starting at zero). + * \param [in] offs Interrupt mask register offset. + * \param [in] val New value to write to register. + * + * \retval 0 No errors + * \retval <0 Something went wrong. + */ +extern int +bcmdrd_hal_intr_mask_write(int unit, int irq_num, + uint32_t offs, uint32_t val); + +#endif /* BCMDRD_HAL_H */ diff --git a/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_internal.h b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_internal.h new file mode 100644 index 0000000..173d2e4 --- /dev/null +++ b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_internal.h @@ -0,0 +1,141 @@ +/*! \file bcmdrd_internal.h + * + * Internal DRD APIs. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMDRD_INTERNAL_H +#define BCMDRD_INTERNAL_H + +#include +#ifndef PKTIO_IMPL +#include + +#include +#endif +/*! Pseudo-block-type for device pipes in \ref bcmdrd_pipe_data_t. */ +#define BLKTYPE_DEV 0 + +/*! + * Cached information about valid pipes. + * + * Information is stored per block type and block type 0 is used for + * the device pipes. + */ +typedef struct bcmdrd_pipe_data_s { + + /*! Map of valid pipes for a given block type. */ + bcmdrd_pipemap_t pipemap; + + /*! Number valid pipes in a given block type. */ + uint16_t num_pipes; + + /*! Maximum valid pipe index for a given block type. */ + uint16_t pipe_max; + +} bcmdrd_pipe_data_t; + +/*! + * \brief BCMDRD Device structure. + */ +typedef struct bcmdrd_dev_s { + + /*! Device identification (typically PCI vendor/device ID). */ + bcmdrd_dev_id_t id; + + /*! Global chip flags. */ + uint32_t flags; + + /*! Revision string (e.g. "A0"). */ + char rev_str[4]; + + /*! Device name (e.g. "BCM56801"). */ + const char *name; + + /*! Device type string (e.g. "bcm56800_a0"). */ + const char *type_str; + + /*! Device type (enumeration of supported devices). */ + bcmdrd_dev_type_t type; + + /*! I/O access functions and info */ + bcmdrd_hal_io_t io; + + /*! DMA access functions */ + bcmdrd_hal_dma_t dma; + + /*! Interrupt control API */ + bcmdrd_hal_intr_t intr; + + /*! Chip information structure. */ + const bcmdrd_chip_info_t *chip_info; +#ifndef PKTIO_IMPL + /*! Chip profile (typically NULL if base device). */ + bcmdrd_chip_profile_t *chip_profile; + + /*! Port information array. */ + const bcmdrd_port_info_t *port_info; + + /*! Bit map of valid physical ports in the device. */ + bcmdrd_pbmp_t valid_ports; + + /*! Bit map of valid pipes in the device. */ + bcmdrd_pipe_data_t *valid_pipes; + + /*! Pipeline bypass mode (device-specific). */ + uint32_t bypass_mode; + + /*! Operation mode (device-specific). */ + uint32_t opmode; + + /*! Whether device bus has been initialized. */ + bool bus_initialized; + + /*! Hash-based lookup for chip symbol modifiers. */ + shr_cht_t *chip_mod_cht; + + /*! Whether physical block has any valid ports. */ + bool *blk_has_valid_ports; +#endif +} bcmdrd_dev_t; + +/*! + * \brief Get DRD device handle. + * + * \param [in] unit Unit number. + * + * \return DRD device handle or NULL if not found. + */ +extern bcmdrd_dev_t * +bcmdrd_dev_get(int unit); + +#endif /* BCMDRD_INTERNAL_H */ diff --git a/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_symbol_types.h b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_symbol_types.h new file mode 100644 index 0000000..29dd0e3 --- /dev/null +++ b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_symbol_types.h @@ -0,0 +1,227 @@ +/*! \file bcmdrd_symbol_types.h + * + * + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMDRD_SYMBOL_TYPES_H +#define BCMDRD_SYMBOL_TYPES_H + +#include + +/*! + * \name Symbol flags. + * \anchor BCMDRD_SYMBOL_FLAG_xxx + */ + +/*! \{ */ + +/*! Symbol applicable for SER test. */ +#define BCMDRD_SYMBOL_FLAG_SER_TEST (1U << 7) + +/*! Symbol data will be cleared on read. */ +#define BCMDRD_SYMBOL_FLAG_CLEAR_ON_READ (1U << 8) + +/*! Symbol data can be updated by hardware. */ +#define BCMDRD_SYMBOL_FLAG_HW_UPDATED (1U << 9) + +/*! Symbol should not be accessed with traffic running. */ +#define BCMDRD_SYMBOL_FLAG_ACC_IDLE (1U << 10) + +/*! Symbol validity can be decided dynamically at system initialization. */ +#define BCMDRD_SYMBOL_FLAG_DYNAMIC (1U << 11) + +/*! Symbol represents a special access. */ +#define BCMDRD_SYMBOL_FLAG_SPECIAL (1U << 12) + +/*! Symbol access type represents a unique pipe. */ +#define BCMDRD_SYMBOL_FLAG_ACC_UNIQUE_PIPE (1U << 13) + +/*! Symbol is associated with a specific sub-pipe. */ +#define BCMDRD_SYMBOL_FLAG_SUB_PIPE (1U << 14) + +/*! Symbol is write-only. */ +#define BCMDRD_SYMBOL_FLAG_WRITEONLY (1U << 15) + +/*! Symbol is not suitable for read/write tests. */ +#define BCMDRD_SYMBOL_FLAG_NOTEST (1U << 16) + +/*! Symbol is a non-CMIC iProc register. */ +#define BCMDRD_SYMBOL_FLAG_IPROC (1U << 17) + +/*! Symbol is an overlay of other symbols. */ +#define BCMDRD_SYMBOL_FLAG_OVERLAY (1U << 18) + +/*! Symbol is read-only or any field within the symbol is read-only. */ +#define BCMDRD_SYMBOL_FLAG_READONLY (1U << 19) + +/*! Symbol with FIFO operations. */ +#define BCMDRD_SYMBOL_FLAG_FIFO (1U << 20) + +/*! Symbol is reasonable to cache in S/W. */ +#define BCMDRD_SYMBOL_FLAG_CACHEABLE (1U << 21) + +/*! Symbol is a hashed table. */ +#define BCMDRD_SYMBOL_FLAG_HASHED (1U << 22) + +/*! Symbol is an external CAM. */ +#define BCMDRD_SYMBOL_FLAG_EXT_CAM (1U << 23) + +/*! Symbol is a CAM. */ +#define BCMDRD_SYMBOL_FLAG_CAM (1U << 24) + +/*! Symbol is a register. */ +#define BCMDRD_SYMBOL_FLAG_REGISTER (1U << 25) + +/*! Symbol is a port-based register, i.e. one ionstance per port. */ +#define BCMDRD_SYMBOL_FLAG_PORT (1U << 26) + +/*! Symbol is a counter register. */ +#define BCMDRD_SYMBOL_FLAG_COUNTER (1U << 27) + +/*! Symbol is a memory. */ +#define BCMDRD_SYMBOL_FLAG_MEMORY (1U << 28) + +/*! Symbol uses big endian word ordering. */ +#define BCMDRD_SYMBOL_FLAG_BIG_ENDIAN (1U << 29) + +/*! Symbol is a memory-mapped register. */ +#define BCMDRD_SYMBOL_FLAG_MEMMAPPED (1U << 30) + +/*! Symbol is a port-block register, i.e. one instance per port-block. */ +#define BCMDRD_SYMBOL_FLAG_SOFT_PORT (1U << 31) + +/*! \} */ + +/*! + * \name Symbol attributes. + * \anchor BCMDRD_SYM_ATTR_xxx + */ + +/*! \{ */ + +/*! Symbol is a CAM. */ +#define BCMDRD_SYM_ATTR_CAM (1 << 0) + +/*! Symbol is a hashed memory. */ +#define BCMDRD_SYM_ATTR_HASHED (1 << 1) + +/*! Symbol is not visible in this configuration. */ +#define BCMDRD_SYM_ATTR_HIDDEN (1 << 2) + +/*! \} */ + +/*! + * \brief Symbol (register/memory) information + * + * The symbol information is dynamic information about a symbol in the + * current device configuraton. In many situations, this information + * will be identical to the static symbol information of the base + * device. + */ +typedef struct { + + /*! Symbol ID (unique per device). */ + bcmdrd_sid_t sid; + + /*! Symbol name, e.g. "VLANm" or "MISCCONFIGr". */ + const char *name; + + /*! Mask of block types this symbol is valid for. */ + uint32_t blktypes; + + /*! Special attributes of this symbol (\ref BCMDRD_SYMBOL_FLAG_xxx). */ + uint32_t flags; + + /*! Fixed part of symbol address (composition is device-dependent). */ + uint32_t offset; + + /*! Minimum valid index for array-type symbols. */ + uint32_t index_min; + + /*! Maximum valid index for array-type symbols. */ + uint32_t index_max; + + /*! Size of symbol data (or entry if array-type) in 32-bit words. */ + uint32_t entry_wsize; + + /*! Index address step value for array-type symbols. */ + uint32_t step_size; + +} bcmdrd_sym_info_t; + +/*! + * \name Symbol field flags. + * \anchor BCMDRD_SYMBOL_FIELD_FLAG_xxx + */ + +/*! \{ */ + +/*! Symbol field is a counter field. */ +#define BCMDRD_SYMBOL_FIELD_FLAG_COUNTER (1 << 0) + +/*! Symbol field is a key field. */ +#define BCMDRD_SYMBOL_FIELD_FLAG_KEY (1 << 1) + +/*! Symbol field is a mask field. */ +#define BCMDRD_SYMBOL_FIELD_FLAG_MASK (1 << 2) + +/*! \} */ + +/*! + * \brief Field information structure. + * + * This structure defines a single field within a symbol. + */ +typedef struct bcmdrd_sym_field_info_s { + + /*! Field name, e.g. "VLANf" or "VALIDf". */ + const char *name; + + /*! Field ID (unique per device). */ + int fid; + + /*! Special field ID, which defines how multi-view memories are decoded. */ + int view; + + /*! Special attributes of this field (\ref BCMDRD_SYMBOL_FIELD_FLAG_xxx). */ + uint32_t flags; + + /*! First bit of this field. */ + uint16_t minbit; + + /*! Last bit of this field. */ + uint16_t maxbit; + +} bcmdrd_sym_field_info_t; + +#endif /* BCMDRD_SYMBOL_TYPES_H */ diff --git a/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_symbols.h b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_symbols.h new file mode 100644 index 0000000..13b7535 --- /dev/null +++ b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_symbols.h @@ -0,0 +1,1152 @@ +/*! \file bcmdrd_symbols.h + * + * Chip symbol table definitions. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMDRD_SYMBOLS_H +#define BCMDRD_SYMBOLS_H + +/******************************************************************************* + * BCMDRD symbol formats + ******************************************************************************/ + +#include + +/******************************************************************************* + * Resolve compile depedencies for optimized code size reduction. + ******************************************************************************/ + +#if BCMDRD_CONFIG_INCLUDE_CHIP_SYMBOLS == 0 +#undef BCMDRD_CONFIG_INCLUDE_FIELD_INFO +#define BCMDRD_CONFIG_INCLUDE_FIELD_INFO 0 +#endif + +/*! + * \name Symbol index information. + * \anchor BCMDRD_SYMBOL_INDEX_F_xxx + * + * In order to maintain a compact symbol table format the entry size + * and the minimum/maximum table indexes are encoded into a single + * 32-bit word. + * + * The following flags and macros are used to encode and extract the + * above information to/from the 32-bit index word. + */ + +/*! \{ */ + +/*! + * \brief Flag indicating exponential index calculation. + * + * Used if real maximum cannot be contained within max field. + * + * Real maximum is encoded as ((1 << min) * max) - 1). + * + * Real minimum is always zero. + * + * Example: + * (max,min)=(17,12) + * => real max = ((1 << 12) * 17) - 1) = 0x10fff + */ +#define BCMDRD_SYMBOL_INDEX_F_EXP 0x1 + +/*! + * \brief Flag indicating variable index maximum. + * + * Used e.g. if register array size is port-dependent. + * + * Real maximum and minimum depend on configuration. + * + * The min value is used as an encoding key which may be passed to a + * chip-specific function. + */ +#define BCMDRD_SYMBOL_INDEX_F_VAR 0x2 + +/*! + * \brief Flag indicating address step different from 1. + * + * Used e.g. if address step for a register array is non-standard. + * + * Real minimum is always zero. + * + * The min value is interpreted as (address step - 1). + * + * Example: + * (max,min)=(11,3) + * => 12 elements with addr(i+1) = addr(i)+4 + */ +#define BCMDRD_SYMBOL_INDEX_F_STEP 0x4 + +/*! Encode entry size into index word. */ +#define BCMDRD_SYMBOL_INDEX_SIZE_ENCODE(s) F32_ENCODE((uint32_t)s, 0, 8) + +/*! Extract entry size from index word. */ +#define BCMDRD_SYMBOL_INDEX_SIZE_GET(w) F32_GET(w, 0, 8) + +/*! Encode minimum table index into index word. */ +#define BCMDRD_SYMBOL_INDEX_MIN_ENCODE(s) F32_ENCODE((uint32_t)s, 8, 5) + +/*! Extract raw minimum table index from index word. */ +#define BCMDRD_SYMBOL_INDEX_MIN_GETRAW(w) F32_GET(w, 8, 5) + +/*! Encode maximum table index into index word. */ +#define BCMDRD_SYMBOL_INDEX_MAX_ENCODE(s) F32_ENCODE((uint32_t)s, 13, 16) + +/*! Extract raw maximum table index from index word. */ +#define BCMDRD_SYMBOL_INDEX_MAX_GETRAW(w) F32_GET(w, 13, 16) + +/*! Encode index flags into index word. */ +#define BCMDRD_SYMBOL_INDEX_FLAGS_ENCODE(s) F32_ENCODE((uint32_t)s, 29, 3) + +/*! Extract index flags from index word. */ +#define BCMDRD_SYMBOL_INDEX_FLAGS_GET(w) F32_GET(w, 29, 3) + +/*! Get real minimum table index based on raw values and flags. */ +#define BCMDRD_SYMBOL_INDEX_MIN_GET(w) \ + (BCMDRD_SYMBOL_INDEX_FLAGS_GET(w) ? \ + 0 : \ + BCMDRD_SYMBOL_INDEX_MIN_GETRAW(w)) + +/*! Get encoding type from index word. */ +#define BCMDRD_SYMBOL_INDEX_ENC_GET(w) BCMDRD_SYMBOL_INDEX_MIN_GETRAW(w) + +/*! Get real maximum table index based on raw values and flags. */ +#define BCMDRD_SYMBOL_INDEX_MAX_GET(w) \ + ((BCMDRD_SYMBOL_INDEX_FLAGS_GET(w) & BCMDRD_SYMBOL_INDEX_F_EXP) ? \ + (BCMDRD_SYMBOL_INDEX_MAX_GETRAW(w) * \ + (1U << BCMDRD_SYMBOL_INDEX_MIN_GETRAW(w))) - 1 : \ + BCMDRD_SYMBOL_INDEX_MAX_GETRAW(w)) + +/*! Get per-index address step value. */ +#define BCMDRD_SYMBOL_INDEX_STEP_GET(w) \ + ((BCMDRD_SYMBOL_INDEX_FLAGS_GET(w) & BCMDRD_SYMBOL_INDEX_F_STEP) ? \ + (BCMDRD_SYMBOL_INDEX_MIN_GETRAW(w) + 1) : \ + 1) + +/*! \} */ + +/*! + * \name Symbol field encode information. + * + * Symbol field information is encoded in variable size. The supported formats + * are depicted in the following tables: + * + * - Single Word Field Format + * | Bits | Name | Description | + * | :---: | --------- | ------------------------------------------- | + * | 31:31 | LastField | Indicates this is the last field descriptor word in a field array. | + * | 30:30 | Ext | Indicates that this is the first word in a Double Word Field, not a Single Word Field.
This word and the next form a Double Word Field. | + * | 29:29 | Ext2 | Indicates that this field is visible only in certain memory views.
This word and the next two form a Triple Word Field. | + * | 28:15 | FieldId | This is the unique field id for this field. | + * | 14:7 | Minbit | This is the field's minbit. | + * | 6:0 | Width | This is the field's width (in bits). | + *
+ * + * - Double Word Field Format + * | Word | Bits | Name | Description | + * | :--: | :---: | --------- | ------------------------------------------- | + * | 0 | 31:31 | LastField | Indicates this is the last field descriptor word in a field array. | + * | 0 | 30:30 | Ext | Indicates this is the start of a Double Word field. | + * | 0 | 29:29 | Ext2 | Must be zero for Double Word fields. | + * | 0 | 28:28 | Cnt | Indicates that field is a counter. | + * | 0 | 27:27 | Key | Indicates that field is a key. | + * | 0 | 26:26 | Mask | Indicates that field is a mask. | + * | 0 | 25:24 | Rsvd | Reserved for future field attributes. | + * | 0 | 23:0 | FieldId | This is the unique field id for this field. | + * | 1 | 31:16 | Minbit | This is the field's minbit. | + * | 1 | 15:0 | Width | This is the field's width (in bits). | + *
+ * + * - Triple Word Field Format + * | Word | Bits | Name | Description | + * | :--: | :---: | --------- | ------------------------------------------- | + * | 0 | 31:31 | LastField | Indicates this is the last field descriptor word in a field array. | + * | 0 | 30:30 | Ext | Must be zero for Triple Word fields. | + * | 0 | 29:29 | Ext2 | Indicates that this word and the next two form a Triple Word Field. | + * | 0 | 28:28 | Cnt | Indicates that field is a counter. | + * | 0 | 27:27 | Key | Indicates that field is a key. | + * | 0 | 26:26 | Mask | Indicates that field is a mask. | + * | 0 | 25:24 | Rsvd | Reserved for future field attributes. | + * | 0 | 23:0 | FieldId | This is the unique field id for this field. | + * | 1 | 31:16 | Minbit | This is the field's minbit. | + * | 1 | 15:0 | Width | This is the field's width (in bits). | + * | 2 | 23:0 | ViewId | This is the unique field view id for this field. | + *
+ */ + +/*! \{ */ + +/*! Indicates last field descriptor word in a field array. */ +#define BCMDRD_SYM_FIELD_FLAG_LAST (1U << 31) + +/*! Indicates double-word field descriptor. */ +#define BCMDRD_SYM_FIELD_FLAG_EXT (1U << 30) + +/*! Indicates triple-word field descriptor. */ +#define BCMDRD_SYM_FIELD_FLAG_EXT2 (1U << 29) + +/*! Indicates counter attribute in a field */ +#define BCMDRD_SYM_FIELD_ATTR_COUNTER (1U << 28) + +/*! Indicates key attribute in a field */ +#define BCMDRD_SYM_FIELD_ATTR_KEY (1U << 27) + +/*! Indicates mask attribute in a field */ +#define BCMDRD_SYM_FIELD_ATTR_MASK (1U << 26) + +/*! Test field descriptor word for \ref BCMDRD_SYM_FIELD_FLAG_LAST. */ +#define BCMDRD_SYM_FIELD_LAST(w) ((w) & BCMDRD_SYM_FIELD_FLAG_LAST) + +/*! Test field descriptor word for \ref BCMDRD_SYM_FIELD_FLAG_EXT. */ +#define BCMDRD_SYM_FIELD_EXT(w) ((w) & BCMDRD_SYM_FIELD_FLAG_EXT) + +/*! Test field descriptor word for \ref BCMDRD_SYM_FIELD_FLAG_EXT2. */ +#define BCMDRD_SYM_FIELD_EXT2(w) ((w) & BCMDRD_SYM_FIELD_FLAG_EXT2) + + +/*! Encode field ID into a single-word field descriptor. */ +#define BCMDRD_SYM_FIELD_ID_ENCODE(id) F32_ENCODE(id, 15, 14) + +/*! Encode field start-bit into a single-word field descriptor. */ +#define BCMDRD_SYM_FIELD_MIN_ENCODE(b) F32_ENCODE(b, 7, 8) + +/*! Encode field size into a single-word field descriptor. */ +#define BCMDRD_SYM_FIELD_WIDTH_ENCODE(b) F32_ENCODE(b, 0, 7) + +/*! Extract field ID from a single-word field descriptor. */ +#define BCMDRD_SYM_FIELD_ID_GET(w) F32_GET(w, 15, 14) + +/*! Extract field start-bit from a single-word field descriptor. */ +#define BCMDRD_SYM_FIELD_MIN_GET(w) F32_GET(w, 7, 8) + +/*! Extract field size from a single-word field descriptor. */ +#define BCMDRD_SYM_FIELD_WIDTH_GET(w) F32_GET(w, 0, 7) + +/*! Encode field information into a single-word field descriptor. */ +#define BCMDRD_SYM_FIELD_ENCODE(id, min, width) \ + (BCMDRD_SYM_FIELD_ID_ENCODE(id) | \ + BCMDRD_SYM_FIELD_MIN_ENCODE(min) | \ + BCMDRD_SYM_FIELD_WIDTH_ENCODE(width)) + +/*! Encode field ID into a double-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT_ID_ENCODE(id) F32_ENCODE(id, 0, 24) + +/*! Encode field start-bit into a double-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT_MIN_ENCODE(b) F32_ENCODE(b, 16, 16) + +/*! Encode field size into a double-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT_WIDTH_ENCODE(b) F32_ENCODE(b, 0, 16) + +/*! Extract field ID from a double-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT_ID_GET(w) F32_GET(w, 0, 24) + +/*! Extract field start-bit from a double-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT_MIN_GET(w) F32_GET((&(w))[1], 16, 16) + +/*! Extract field size from a double-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT_WIDTH_GET(w) F32_GET((&(w))[1], 0, 16) + +/*! Encode field information into a double-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT_ENCODE(id, min, width) \ + (BCMDRD_SYM_FIELD_FLAG_EXT | BCMDRD_SYM_FIELD_EXT_ID_ENCODE(id)), \ + (BCMDRD_SYM_FIELD_EXT_MIN_ENCODE(min) | \ + BCMDRD_SYM_FIELD_EXT_WIDTH_ENCODE(width)) + +/*! + * Test field attribute for \ref BCMDRD_SYM_FIELD_ATTR_COUNTER + * in double-word field descriptor. + */ +#define BCMDRD_SYM_FIELD_EXT_ATTR_IS_COUNTER(w) \ + ((w) & BCMDRD_SYM_FIELD_ATTR_COUNTER) + +/*! + * Test field attribute for \ref BCMDRD_SYM_FIELD_ATTR_KEY + * in double-word field descriptor. + */ +#define BCMDRD_SYM_FIELD_EXT_ATTR_IS_KEY(w) \ + ((w) & BCMDRD_SYM_FIELD_ATTR_KEY) + +/*! + * Test field attribute for \ref BCMDRD_SYM_FIELD_ATTR_MASK + * in double-word field descriptor. + */ +#define BCMDRD_SYM_FIELD_EXT_ATTR_IS_MASK(w) \ + ((w) & BCMDRD_SYM_FIELD_ATTR_MASK) + + +/*! Encode field ID into a triple-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT2_ID_ENCODE(id) F32_ENCODE(id, 0, 24) + +/*! Encode field start-bit into a triple-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT2_MIN_ENCODE(b) F32_ENCODE(b, 16, 16) + +/*! Encode field size into a triple-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT2_WIDTH_ENCODE(b) F32_ENCODE(b, 0, 16) + +/*! Encode field view ID into a triple-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT2_VIEW_ENCODE(b) F32_ENCODE(b, 0, 24) + +/*! Extract field ID from a triple-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT2_ID_GET(w) F32_GET(w, 0, 24) + +/*! Extract field start-bit from a triple-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT2_MIN_GET(w) F32_GET((&(w))[1], 16, 16) + +/*! Extract field width from a triple-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT2_WIDTH_GET(w) F32_GET((&(w))[1], 0, 16) + +/*! Extract field view ID from a triple-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT2_VIEW_GET(w) F32_GET((&(w))[2], 0, 24) + +/*! Encode field information into a triple-word field descriptor. */ +#define BCMDRD_SYM_FIELD_EXT2_ENCODE(id, min, width, view) \ + (BCMDRD_SYM_FIELD_FLAG_EXT2 | BCMDRD_SYM_FIELD_EXT2_ID_ENCODE(id)), \ + (BCMDRD_SYM_FIELD_EXT2_MIN_ENCODE(min) | \ + BCMDRD_SYM_FIELD_EXT2_WIDTH_ENCODE(width)), \ + BCMDRD_SYM_FIELD_EXT2_VIEW_ENCODE(view) + +/*! + * Test field attribute for \ref BCMDRD_SYM_FIELD_ATTR_COUNTER + * in triple-word field descriptor. + */ +#define BCMDRD_SYM_FIELD_EXT2_ATTR_IS_COUNTER(w) \ + ((w) & BCMDRD_SYM_FIELD_ATTR_COUNTER) + +/*! + * Test field attribute for \ref BCMDRD_SYM_FIELD_ATTR_KEY + * in triple-word field descriptor. + */ +#define BCMDRD_SYM_FIELD_EXT2_ATTR_IS_KEY(w) \ + ((w) & BCMDRD_SYM_FIELD_ATTR_KEY) + +/*! + * Test field attribute for \ref BCMDRD_SYM_FIELD_ATTR_MASK + * in triple-word field descriptor. + */ +#define BCMDRD_SYM_FIELD_EXT2_ATTR_IS_MASK(w) \ + ((w) & BCMDRD_SYM_FIELD_ATTR_MASK) + +/*! \} */ + + +/*! + * \brief Iterate over all fields for a symbol. + * + * Given a pointer to a field descriptor word array, this macro will + * fill out the \ref bcmdrd_sym_field_info_t structure for each field + * in the field descriptor word array. + * + * If a list of corresponding fieln names is given, the field + * information will include the symbolic field name. + * + * The macro must be terminated with \ref BCMDRD_SYM_FIELDS_ITER_END. + */ +#define BCMDRD_SYM_FIELDS_ITER_BEGIN(start, finfo, fnames) { \ + uint32_t *_fp = start; \ + for (;;) { \ + if (!_fp) { \ + break; \ + } else { \ + _fp = bcmdrd_sym_field_info_decode(_fp, (fnames), &(finfo)); + +/*! Refer to \ref BCMDRD_SYM_FIELDS_ITER_BEGIN. */ +#define BCMDRD_SYM_FIELDS_ITER_END() }}} + +/*! + * Symbol information structure (single symbol). + */ +typedef struct bcmdrd_symbol_s { + + /*! Base offset (fixed address information). */ + uint32_t addr; + + /*! Encoded information about valid indexes for arrays. */ + uint32_t index; + + /*! Symbol flags (\ref BCMDRD_SYMBOL_FLAG_xxx). */ + uint32_t flags; + + /*! + * Device-specific information. + * | Bits | Name | Description | + * | :---: | ----------------- | ---------------------------------------- | + * | 31:24 | HMI-specific data | This is 8-bit symbol HMI-specific data. | + * | 23:21 | Sub-pipe instance | Sub-pipe association (if any). | + * | 20:14 | Access type | This is the symbol access type. | + * | 13:7 | Block type 1 | The 2nd symbol block type (> 0 if any). | + * | 6:0 | Block type 0 | The 1st symbol block type (> 0 always). | + */ + uint32_t info; + + /*! Profile information for default value, SER information, etc. */ + uint32_t pfinfo; + +#if BCMDRD_CONFIG_INCLUDE_FIELD_INFO == 1 + /*! Pointer to field information data. */ + uint32_t *fields; +#endif + + /*! Symbol name. */ + const char *name; + +#if BCMDRD_CONFIG_INCLUDE_ALIAS_NAMES == 1 + /*! + * Alternative symbol name (typically used if hardware and + * software names differ). + */ + const char *alias; + + /*! + * User-fiendly symbol name (typically a shorter a more meaningful + * name). + */ + const char *ufname; +#endif + +} bcmdrd_symbol_t; + +/*! Maximum block types encoded in the symbol device-specific information. */ +#define BCMDRD_SYM_INFO_MAX_BLKTYPES 2 + +/*! Bit number of the encoded block type. */ +#define BCMDRD_SYM_INFO_BLKTYPE_BITS 7 + +/*! Bit mask of the encoded block type. */ +#define BCMDRD_SYM_INFO_BLKTYPE_MASK ((1U << BCMDRD_SYM_INFO_BLKTYPE_BITS) - 1) + +/*! Bit mask of all the encoded block types. */ +#define BCMDRD_SYM_INFO_BLKTYPES_MASK \ + ((1U << (BCMDRD_SYM_INFO_MAX_BLKTYPES * BCMDRD_SYM_INFO_BLKTYPE_BITS)) - 1) + +/*! Extract block types from symbol device-specific information. */ +#define BCMDRD_SYM_INFO_BLKTYPES(_w) ((_w) & BCMDRD_SYM_INFO_BLKTYPES_MASK) + +/*! Bit number of the encoded access type. */ +#define BCMDRD_SYM_INFO_ACCTYPE_SHIFT \ + (BCMDRD_SYM_INFO_MAX_BLKTYPES * BCMDRD_SYM_INFO_BLKTYPE_BITS) + +/*! Bit number of the encoded access type. */ +#define BCMDRD_SYM_INFO_ACCTYPE_BITS 7 + +/*! Bit mask of the encoded access type. */ +#define BCMDRD_SYM_INFO_ACCTYPE_MASK ((1U << BCMDRD_SYM_INFO_ACCTYPE_BITS) - 1) + +/*! Extract access type from symbol device-specific information. */ +#define BCMDRD_SYM_INFO_ACCTYPE(_w) \ + (((_w) >> BCMDRD_SYM_INFO_ACCTYPE_SHIFT) & BCMDRD_SYM_INFO_ACCTYPE_MASK) + +/*! Bit number of the encoded sub-pipe instance. */ +#define BCMDRD_SYM_INFO_SUBPIPE_INST_BITS 3 + +/*! Bit mask of the encoded sub-pipe instance. */ +#define BCMDRD_SYM_INFO_SUBPIPE_INST_MASK \ + ((1U << BCMDRD_SYM_INFO_SUBPIPE_INST_BITS) - 1) + +/*! Extract sub-pipe instance from symbol device-specific information. */ +#define BCMDRD_SYM_INFO_SUBPIPE_INST(_w) \ + (((_w) >> 21) & BCMDRD_SYM_INFO_SUBPIPE_INST_MASK) + +/*! Extract block type by index from symbol device-specific information. */ +#define BCMDRD_SYM_INFO_BLKTYPE(_w, _i) \ + ((BCMDRD_SYM_INFO_BLKTYPES(_w) >> \ + (BCMDRD_SYM_INFO_BLKTYPE_BITS * (_i))) & BCMDRD_SYM_INFO_BLKTYPE_MASK) + +/*! + * \name Symbol profile information. + */ + +/*! \{ */ + +/*! Set profile offset for memory symbol. */ +#define BCMDRD_SYM_MEMPF_OFFSET_SET(_p) F32_ENCODE((_p), 0, 12) + +/*! Get profile offset for memory. */ +#define BCMDRD_SYM_MEMPF_OFFSET_GET(_pi) F32_GET((_pi), 0, 12) + +/*! Set profile offset for register. */ +#define BCMDRD_SYM_REGPF_OFFSET_SET(_p) F32_ENCODE((_p), 0, 12) + +/*! Get profile offset for register. */ +#define BCMDRD_SYM_REGPF_OFFSET_GET(_pi) F32_GET((_pi), 0, 12) + +/*! Set profile offset for MOR of symbol. */ +#define BCMDRD_SYM_MORPF_OFFSET_SET(_p) F32_ENCODE((_p), 12, 8) + +/*! Get profile offset for MOR of symbol. */ +#define BCMDRD_SYM_MORPF_OFFSET_GET(_pi) F32_GET((_pi), 12, 8) + +/*! Set profile offset for error correction information of symbol. */ +#define BCMDRD_SYM_ECCPF_OFFSET_SET(_p) F32_ENCODE((_p), 20, 12) + +/*! Get profile offset for error correction information of symbol. */ +#define BCMDRD_SYM_ECCPF_OFFSET_GET(_pi) F32_GET((_pi), 20, 12) + +/*! \} */ + + +/*! + * \brief Memory comparison function. + * + * \param [in] ent_a Element a of memory to be compared. + * \param [in] ent_b Element b of memory to be compared. + * + * \return 0 if two memory elements equal, otherwise unequal. + */ +typedef int (*bcmdrd_sym_mem_cmp_f)(void *ent_a, void *ent_b); + +/*! + * Memory profile structure. + */ +typedef struct bcmdrd_sym_mem_profile_s { + + /*! Memory comparison function. */ + bcmdrd_sym_mem_cmp_f cmp_fn; + + /*! Null entry data array. */ + const void *null_ent; + +} bcmdrd_sym_mem_profile_t; + +/*! + * MOR profile structure. + */ +typedef struct bcmdrd_sym_mor_profile_s { + + /*! MOR read. */ + uint32_t mrd; + + /*! MOR write. */ + uint32_t mwr; + +} bcmdrd_sym_mor_profile_t; + +/*! + * Symbols table structure (all symbols). + */ +typedef struct bcmdrd_symbols_s { + + /*! List of all symbols used by this device. */ + const bcmdrd_symbol_t *symbols; + + /*! Number of entries in symbols array. */ + const uint32_t size; + + /*! Number of entries in each symbols array section. */ + const uint32_t sect_size[2]; + + /*! List of all field names used by this device. */ + const char **field_names; + + /*! List of all reset values/masks used by this device. */ + const uint32_t *reg_profiles; + + /*! List of all memory profiles used by this device. */ + const bcmdrd_sym_mem_profile_t *mem_profiles; + + /*! List of all MOR profiles used by this device. */ + const bcmdrd_sym_mor_profile_t *mor_profiles; + + /*! SER data used by this device. */ + const void *ser_data; + +#if BCMDRD_CONFIG_INCLUDE_ALIAS_NAMES == 1 + /*! List of all symbols alias names used in this device. */ + const bcmdrd_enum_map_t *alias_names; + + /*! Number of entries in symbols alias names array */ + const uint32_t alias_names_size; +#endif + + /*! Symbols are sorted and searchable by bsearch. */ + const bool sorted; + +} bcmdrd_symbols_t; + + +/*! + * \brief Search a symbol array. + * + * Search symbol array by comparing input name to each symbol name. + * + * This function is primarily intended for internal use, and should + * normally not be called directly. + * + * \param [in] name Symbol name to search for. + * \param [in] table Array of symbol structures. + * \param [in] size Size of symbol array. + * \param [out] sid Symbol ID if match is found. + * + * \retval Pointer to symbol structure, or NULL if not found. + */ +extern const bcmdrd_symbol_t * +bcmdrd_symbol_find(const char *name, + const bcmdrd_symbol_t *table, uint32_t size, + bcmdrd_sid_t *sid); + +/*! + * \brief Binary search a symbol table. + * + * Binary search a symbol table from symbol names or alternative names. + * The symbol table should be sorted properly for the binary search support. + * + * This function is primarily intended for internal use, and should + * normally not be called directly. + * + * \param [in] name Symbol name to look for. + * \param [in] symbols Symbol table structure. + * \param [out] sid Symbol ID if match is found. + * + * \retval Pointer to symbol structure, or NULL if not found. + */ +const bcmdrd_symbol_t * +bcmdrd_symbols_fast_find(const char *name, const bcmdrd_symbols_t *symbols, + bcmdrd_sid_t *sid); + +/*! + * \brief Search a symbol table. + * + * Primary symbol search function. Takes a pointer to the symbols + * structure, finds the name in either one, and returns a full symbol + * structure. + * + * \param [in] name Symbol name to look for. + * \param [in] symbols Symbol table structure. + * \param [out] sid Symbol ID if match is found. + * + * \retval Pointer to symbol structure, or NULL if not found. + */ +extern const bcmdrd_symbol_t * +bcmdrd_symbols_find(const char *name, const bcmdrd_symbols_t *symbols, + bcmdrd_sid_t *sid); + +/*! + * \brief Get a specific symbol by index. + * + * \param [in] symbols - Symbols information structure for device. + * \param [in] sindex - Symbol index (usually same as symbol ID). + * \param [out] rsym - Symbol information structure to fill. + * + * \retval 0 No errors, or -1 if not found + */ +extern int +bcmdrd_symbols_get(const bcmdrd_symbols_t *symbols, uint32_t sindex, + bcmdrd_symbol_t *rsym); + +/*! + * \brief Get index of a specific symbol. + * + * \param [in] symbols - Symbols information structure for device. + * \param [in] symbol - Specific symbol structure. + * + * \retval Symbol index, or -1 if not found + */ +extern int +bcmdrd_symbols_index(const bcmdrd_symbols_t *symbols, + const bcmdrd_symbol_t *symbol); + +/*! + * \brief Get symbol information. + * + * Retrieve dynamic symbol information for register/memory. + * + * \param [in] symbols - Symbols information structure for device. + * \param [in] sid Device-specific symbol ID + * \param [out] sinfo Symbol information structure to fill if not NULL + * + * \retval Raw symbol structure, or NULL if not found. + */ +extern const bcmdrd_symbol_t * +bcmdrd_sym_info_get(const bcmdrd_symbols_t *symbols, bcmdrd_sid_t sid, + bcmdrd_sym_info_t *sinfo); + +/*! + * \name Symbol matching modes. + * \anchor BCMDRD_SYMBOLS_ITER_MODE_xxx + */ + +/*! \{ */ + +/*! Symbol table iterator must match exact symbol name. */ +#define BCMDRD_SYMBOLS_ITER_MODE_EXACT 0 + +/*! Symbol table iterator must match beginning of symbol name. */ +#define BCMDRD_SYMBOLS_ITER_MODE_START 1 + +/*! Symbol table iterator must match any sub-string in symbol name. */ +#define BCMDRD_SYMBOLS_ITER_MODE_STRSTR 2 + +/*! \} */ + +/*! + * \brief Symbols iteration call-back function. + * + * \param [in] symbol Symbol structure (single symbol). + * \param [in] sid Symbol ID. + * \param [in] vptr Caller-provided context. + * + * \retval 0 on success, -1 on failure. + */ +typedef int (*bcmdrd_symbols_iter_cb_f)(const bcmdrd_symbol_t *symbol, + bcmdrd_sid_t sid, + void *vptr); + +/*! + * \brief Symbol table iterator control structure. + * + * This structure contains symbol matching information and call-back + * function information for the symbol table iterator function. + */ +typedef struct bcmdrd_symbols_iter_s { + + /*! String to match against each symbol. */ + const char *name; + + /*! Defines valid matches (\ref BCMDRD_SYMBOLS_ITER_MODE_xxx) */ + int matching_mode; + + /*! Symbol flags that must be present. */ + uint32_t pflags; + + /*! Symbol flags that must be absent. */ + uint32_t aflags; + + /*! + * Block types that must be present. + * List of block types terminated by -1 if not NULL. + */ + int *pblktypes; + + /*! + * Block types that must be absent. + * List of block types terminated by -1 if not NULL. + */ + int *ablktypes; + + /*! + * Access types that must be present. + * List of access types terminated by -1 if not NULL. + */ + int *pacctypes; + + /*! + * Access types that must be absent. + * List of access types terminated by -1 if not NULL. + */ + int *aacctypes; + + /*! Symbols information structure for device. */ + const bcmdrd_symbols_t *symbols; + + /*! Function to be called for each matching symbol. */ + bcmdrd_symbols_iter_cb_f function; + + /*! Context for call-back function. */ + void *vptr; + +} bcmdrd_symbols_iter_t; + +/*! + * \brief Field filtering call-back function. + * + * This function will indicate whether a particular field should be + * filtered out for the current memory view. + * + * The field-view encoding string has the following syntax: + * + * {[\]:\:\[|\ ... ]} + * + * Ideally the keysrc is the same data entry which is + * being decoded, and in this case it can left out, e.g.: + * + * {:KEY_TYPEf:1} + * + * This example encoding means that if KEY_TYPEf=1, then + * this field is valid for this view. + * + * Note that a field can be for multiple views, e.g.: + * + * {:KEY_TYPEf:1|3} + * + * This example encoding means that this field is valid + * if KEY_TYPEf=1 or KEY_TYPEf=3. + * + * The special \=-1 means that this field is valid + * even if there is no context (cookie=NULL). + * + * \param [in] symbol Symbol structure (single symbol). + * \param [in] fnames List of all field names for this unit. + * \param [in] encoding Field-view encoding string. + * \param [in] cookie Caller-provided context. + * + * \retval true if field should be filtered out, otherwise false. + */ +typedef int (*bcmdrd_symbol_filter_cb_f)(const bcmdrd_symbol_t *symbol, + const char **fnames, + const char *encoding, + void *cookie); + +/*! + * \brief Customized symbol filtering call-back function. + * + * This function will indicate whether a particular name with + * with extra flags information should be filtered out. + * + * \param [in] symbol Symbol structure (single symbol). + * \param [in] name Name of the identifier. + * \param [in] flags Flags carried with the identifier. + * \param [in] data Table entry data to process. + * \param [in] cookie Caller-provided context. + * + * \retval true if field should be filtered out, otherwise false. + */ +typedef int (*bcmdrd_symbol_custom_filter_cb_f)(const bcmdrd_symbol_t *symbol, + const char *name, + uint32_t flags, + uint32_t *data, + void *cookie); + +/*! + * \brief Iterate over all symbols in a symbol table. + * + * Search symbol table and call a user-defined function for each + * matched symbol. Useful if multiple partial matches may occur. + * + * Iteration will stop if the call-back function returns a non-zero + * value. + * + * \param [in] iter Iterator control structure (see \ref + * bcmdrd_symbols_iter_t). + * + * \retval 0 No errors, otherwise call-back function return value. + */ +extern int +bcmdrd_symbols_iter(bcmdrd_symbols_iter_t *iter); + +/*! + * \brief Default field-view filtering function. + * + * See \ref bcmdrd_symbol_filter_cb_f for a detailed description. + * + * \param [in] symbol Symbol structure (single symbol). + * \param [in] fnames List of all field names for this unit. + * \param [in] encoding Field-view encoding string. + * \param [in] cookie Caller-provided context. + * + * \retval true if field should be filtered out, otherwise false. + */ +extern int +bcmdrd_symbol_field_filter(const bcmdrd_symbol_t *symbol, + const char **fnames, + const char *encoding, + void *cookie); + +/*! + * \brief Get list of fields IDs for given symbol ID. + * + * The function will always return the total number of valid field IDs + * in num_fid, irrespective of the value of list_max, i.e. if num_fid + * is greater than list_max, then the returned fid_list was truncated. + * + * For example, if list_max is zero, then the number of valid field + * IDs is returned in num_fid, but the fid_list is not updated (can be + * specified as NULL). The returned num_fid can then be used to + * allocate a sufficiently large fid_list array. + * + * \param [in] symbols - Symbols information structure for device. + * \param [in] sid Device-specific symbol ID + * \param [in] list_max Maximum number of entries in field ID list + * \param [out] fid_list Field ID list + * \param [out] num_fid Total number of field IDs for this symbold ID + * + * \retval 0 No errors + */ +int +bcmdrd_sym_fid_list_get(const bcmdrd_symbols_t *symbols, + bcmdrd_sid_t sid, size_t list_max, + bcmdrd_fid_t *fid_list, size_t *num_fid); + +/*! + * \brief Get field information for register/memory field. + * + * Obtain field information (name, start bit, end bit, etc.) for + * specified symbol ID and field ID. + * + * \param [in] symbols - Symbols information structure for device. + * \param [in] sid Device-specific symbol ID + * \param [in] fid Device-specific field ID + * \param [out] finfo Field information structure to fill + * + * \retval Pointer to symbol entry, or NULL if not found + */ +extern const bcmdrd_symbol_t * +bcmdrd_sym_field_info_get(const bcmdrd_symbols_t *symbols, + bcmdrd_sid_t sid, bcmdrd_fid_t fid, + bcmdrd_sym_field_info_t *finfo); + +/*! + * \brief Get field information for register/memory field. + * + * Obtain field information (name, start bit, end bit, etc.) for + * specified symbol ID and field name. + * + * \param [in] symbols - Symbols information structure for device. + * \param [in] sid Device-specific symbol ID + * \param [in] fname Field name (ASCII string) + * \param [out] finfo Field information structure to fill + * + * \return Pointer to symbol entry, or NULL if not found. + */ +extern const bcmdrd_symbol_t * +bcmdrd_sym_field_info_get_by_name(const bcmdrd_symbols_t *symbols, + bcmdrd_sid_t sid, const char *fname, + bcmdrd_sym_field_info_t *finfo); + +/*! + * \brief Decode raw field information. + * + * This function decodes raw field information as encoded in the + * symbol table. + * + * FOR INTERNAL USE ONLY. + * + * \param [in] fp Pointer to raw field encoding + * \param [in] fnames Device-specfic list of all field names + * \param [out] finfo Field information structure + * + * \return Pointer to the next field encoding, or NULL if end of list. + */ +extern uint32_t * +bcmdrd_sym_field_info_decode(uint32_t *fp, const char **fnames, + bcmdrd_sym_field_info_t *finfo); + +/*! + * \brief Return the number of fields in a register/memory entry. + * + * FOR INTERNAL USE ONLY. + * + * \param [in] fp Pointer to raw field encoding + * + * \return Number of fields in this register/memory entry. + */ +extern uint32_t +bcmdrd_sym_field_info_count(uint32_t *fp); + +/*! + * \brief Common memory comparison function. + * + * \param [in] ent_a Element a of memory to be compared. + * \param [in] ent_b Element b of memory to be compared. + * + * \return 0 if two memory elements equal, otherwise unequal. + */ +extern int +bcmdrd_sym_mem_cmp_undef(void *ent_a, void *ent_b); + +/*! + * \brief Memory comparison function with inverted mask. + * + * This function will compare only the specified mask bits in + * memory \c ent_a and \c ent_b. The memory mask will be specified + * in an inverted bit mask by \c imask. For example, if bits 0~3 are + * intended to be compared in a 32-bit entry, the contents of \c imask + * would be 0xfffffff0. + * + * \param [in] ent_a Memory entry a to be compared. + * \param [in] ent_b Memory entry b to be compared. + * \param [in] imask Invert mask of Memory entry to be masked with memory entry. + * \param [in] size Compared memory entry size in byte. + * + * \return 0 if two values equal, -1 if ent_a < ent_b, and 1 if ent_a > ent_b. + */ +extern int +bcmdrd_sym_mem_cmp_imask(void *ent_a, void *ent_b, void *imask, int size); + +/*! + * \brief Memory comparison function with mask. + * + * This function will compare only the specified mask bits in + * memory \c ent_a and \c ent_b. The memory mask will be specified in an + * bit mask by \c mask. For example, if bits 0~3 are intended to be compared + * in a 32-bit entry, the contents of \c mask would be 0x0000000f. + * + * \param [in] ent_a Memory entry a to be compared. + * \param [in] ent_b Memory entry b to be compared. + * \param [in] mask Mask of Memory entry to be masked with memory entry. + * \param [in] size Compared memory entry size in byte. + * + * \return 0 if two values equal, -1 if ent_a < ent_b, and 1 if ent_a > ent_b. + */ +extern int +bcmdrd_sym_mem_cmp_mask(void *ent_a, void *ent_b, void *mask, int size); + +/*! + * Memory element value comparison macro. + * The macro will not return only if the comparing values a and b + * are equal. + */ +#define BCMDRD_SYM_MEM_VAL_CMP_RETURN(_a, _b) { \ + if ((_a) < (_b)) { \ + return -1; \ + } \ + if ((_a) > (_b)) { \ + return 1; \ + } \ +} + +/*! + * \brief Get comparison function of a specified memory symbol. + * + * The comparison function is stored in \c profile of \ref bcmdrd_symbol_t. + * And \ref bcmdrd_sym_mem_profile_t is used for profile structure of + * memory symbols. The function is mainly to retrieve the memory + * comparison function pre-defined for memory symbols. + * + * \param [in] symbols Symbol table structure. + * \param [in] symbol Symbol structure. + * + * \return Memory comparison function. NULL on failure or + * no comparison function is specified. + */ +extern bcmdrd_sym_mem_cmp_f +bcmdrd_sym_mem_cmp_fun_get(const bcmdrd_symbols_t *symbols, + const bcmdrd_symbol_t *symbol); + +/*! + * \brief Get null entry of a specified memory symbol. + * + * The memory null entry is stored in \c profile of \ref bcmdrd_symbol_t. + * And \ref bcmdrd_sym_mem_profile_t is used for profile structure of + * memory symbols. The function is mainly to retrieve the null-entry + * pre-defined for memory symbols. + * + * \param [in] symbols Symbol table structure. + * \param [in] symbol Symbol structure. + * + * \return Memory null entry pointer. NULL on failure or + * no null entry is specified. + */ +extern const void * +bcmdrd_sym_mem_null_ent_get(const bcmdrd_symbols_t *symbols, + const bcmdrd_symbol_t *symbol); + +/*! + * \brief Get reset value and mask of a specified register symbol. + * + * This function returns the reset value and reset mask in variable length + * according to the word-size of the specified register symbol. + * The first n-word(s) of the return value is the reset value of the specified + * register which size is n word(s). The following n-word(s) of the + * return value is the reset mask of the specified register. + * + * \param [in] symbols Symbol table structure. + * \param [in] symbol Symbol structure. + * + * \return Pointer to reset value and reset mask or Null on failure. + */ +extern const uint32_t * +bcmdrd_sym_reg_resetval_get(const bcmdrd_symbols_t *symbols, + const bcmdrd_symbol_t *symbol); + +/*! + * \brief Check if default value of a specified symbol is non-zero. + * + * \param [in] symbols Symbol table structure. + * \param [in] symbol Symbol structure. + * + * \retval true Default value is non-zero. + * \retval false Default value is zero. + */ +extern bool +bcmdrd_sym_default_value_is_nonzero(const bcmdrd_symbols_t *symbols, + const bcmdrd_symbol_t *symbol); + +/*! + * \brief Get MOR clocks value of a specified symbol for read operation. + * + * The MOR (Multiple Outstanding Requests) clocks value is supposed to be + * used to optimize the CMIC S-bus DMA read opreration performance + * for this symbol. + * The returned value from this function can be taken as a reference for the + * MOR clocks value setting. + * + * \param [in] symbols Symbol table structure. + * \param [in] symbol Symbol structure. + * + * \return MOR clocks value or 0 if not supported. + */ +extern uint32_t +bcmdrd_sym_mor_clks_read_get(const bcmdrd_symbols_t *symbols, + const bcmdrd_symbol_t *symbol); + +/*! + * \brief Get MOR clocks value of a specified symbol for write operation. + * + * The MOR (Multiple Outstanding Requests) clocks value is supposed to be + * used to optimize the CMIC S-bus DMA write opreration performance + * for this symbol. + * The returned value from this function can be taken as a reference for the + * MOR clocks value setting. + * + * \param [in] symbols Symbol table structure. + * \param [in] symbol Symbol structure. + * + * \return MOR clocks value or 0 if not supported. + */ +extern uint32_t +bcmdrd_sym_mor_clks_write_get(const bcmdrd_symbols_t *symbols, + const bcmdrd_symbol_t *symbol); + +/*! + * \brief Get device-specific SER data structure. + * + * \param [in] symbols Symbol table structure. + * + * \return Device-specific SER data structure or NULL if not support. + */ +extern const void * +bcmdrd_sym_ser_data_get(const bcmdrd_symbols_t *symbols); + +/*! + * \brief Get SER profile offset of a specified symbol. + * + * Note that the given symbol is indicated to have no SER support if + * the returned offset is 0. + * + * \param [in] symbol Symbol structure. + * + * \return Offset to SER profile for a given symbol. + */ +extern int +bcmdrd_sym_ser_profile_offset_get(const bcmdrd_symbol_t *symbol); + +#endif /* BCMDRD_SYMBOLS_H */ diff --git a/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_types.h b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_types.h new file mode 100644 index 0000000..94919c6 --- /dev/null +++ b/src/bcm/common/pktio/bcmdrd/include/bcmdrd/bcmdrd_types.h @@ -0,0 +1,694 @@ +/*! \file bcmdrd_types.h + * + * Basic DRD types, which may be used outside the DRD as well. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMDRD_TYPES_H +#define BCMDRD_TYPES_H + +#include + +#ifdef PKTIO_IMPL +#include +#else +#include +#include + +#include +#endif + +/*! 16-bit-safe left shift */ +#define LSHIFT32(_val, _cnt) ((uint32_t)(_val) << (_cnt)) + +/*! 32-bit-safe left shift */ +#define LSHIFT64(_val, _cnt) ((uint64_t)(_val) << (_cnt)) + +#ifndef F32_MASK +/*! Create a bit mask of w bits as a 32-bit word. */ +#define F32_MASK(w) \ + ((((w) > 31) ? 0 : ((uint32_t)1 << (w))) - 1) +#endif + +#ifndef F64_MASK +/*! Create a bit mask of w bits as a 64-bit dword. */ +#define F64_MASK(w) \ + ((((w) > 63) ? 0 : ((uint64_t)1 << (w))) - 1) +#endif + +#ifndef F32_GET +/*! Extract a field of w bits at offset o from a 32-bit word d. */ +#define F32_GET(d,o,w) \ + (((d) >> o) & F32_MASK(w)) +#endif + +#ifndef F64_GET +/*! Extract a field of w bits at offset o from a 64-bit word d. */ +#define F64_GET(d,o,w) \ + (((d) >> o) & F64_MASK(w)) +#endif + +#ifndef F32_SET +/*! Set a field of w bits at offset o in a 32-bit word d. */ +#define F32_SET(d,o,w,v) \ + (d = ((d & ~(F32_MASK(w) << o)) | (((v) & F32_MASK(w)) << o))) +#endif + +#ifndef F64_SET +/*! Set a field of w bits at offset o in a 64-bit word d. */ +#define F64_SET(d,o,w,v) \ + (d = ((d & ~(F64_MASK(w) << o)) | (((v) & F64_MASK(w)) << o))) +#endif + +/*! Optionally force an error in compiler pre-processor. */ +#if BCMDRD_CONFIG_INCLUDE_FIELD_CHECKS +#define BCMDRD_COMPILER_ERROR (1 << 99) +#else +#define BCMDRD_COMPILER_ERROR 0 +#endif + +#ifndef F32_ENCODE +/*! + * Encode a value of a given width at a given offset. Optionally + * performs compile-time error checking on the value to ensure it fits + * within the given width. + */ +#define F32_ENCODE(v,o,w) \ + ( ((v & F32_MASK(w)) == v) ? \ + /* Value fits in width */ ( (uint32_t)(v) << o ) : \ + /* Value does not fit */ BCMDRD_COMPILER_ERROR) + +#endif + +#ifndef F64_ENCODE +/*! + * Encode a value of a given width at a given offset. Performs + * compile-time error checking on the value to ensure it fits within + * the given width. + */ +#define F64_ENCODE(v,o,w) \ + ( ((v & F64_MASK(w)) == v) ? \ + /* Value fits in width */ ( (uint64_t)(v) << o ) : \ + /* Value does not fit */ BCMDRD_COMPILER_ERROR) + +#endif + +/*! Words in port bit maps */ +#define BCMDRD_PBMP_WORD_MAX (((BCMDRD_CONFIG_MAX_PORTS - 1) >> 5) + 1) + +/*! + * Bitmap of ports of a particular type or properties. + */ +typedef struct bcmdrd_pbmp_s { + /*! Word array. */ + uint32_t w[BCMDRD_PBMP_WORD_MAX]; +} bcmdrd_pbmp_t; + +/* Port bitmap helper functions */ + +/*! + * \brief Check if port bitmap is empty. + * + * Check that no bits are set in a port bitmap of type \ref + * bcmdrd_pbmp_t. + * + * \param [in] pbmp Port bitmap. + * + * \retval true Port bitmap is empty. + * \retval false Port bitmap is not empty. + */ +extern int +bcmdrd_pbmp_is_null(const bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Parse a port list string into a port bitmap. + * + * The port list string may contain commas to separate port numbers + * and hyphens to indicate port ranges. + * + * Examples: "2" "2,5" "2,5,7-13,43" + * + * \param [in] str String to be parsed. + * \param [out] pbmp Port bitmap. + * + * \retval 0 No errors. + * \retval -1 Fail to parse the string to a port bitmap. + */ +extern int +bcmdrd_pbmp_parse(const char *str, bcmdrd_pbmp_t *pbmp); + +/*! + * \brief Get bitmap word index for a given port. + * + * A port bitmap is an array of data words, and this macro will return + * the index of the data word associated with a given port number. + * + * No range check is performed on the port number. + * + * \param [in] _pbmp Port bitmap. + * \param [in] _port Port number to check. + */ +#define BCMDRD_PBMP_WORD(_pbmp, _port) \ + (&(_pbmp))->w[(_port) >> 5] + +/*! + * \brief Check if a port is member of a port bitmap. + * + * Check if a port is member of a port bitmap of type \ref + * bcmdrd_pbmp_t. + * + * No range check is performed on the port number. + * + * \param [in] _pbmp Port bitmap. + * \param [in] _port Port number to check. + */ +#define BCMDRD_PBMP_MEMBER(_pbmp, _port) \ + (BCMDRD_PBMP_WORD(_pbmp, _port) & LSHIFT32(1, (_port) & 0x1f)) + +/*! + * \brief Iterate over a port bitmap. + * + * Iterate over a port bitmap of type \ref bcmdrd_pbmp_t and execute + * the subsequent statement for all bits set in the port bitmap. + * + * \param [in] _pbmp Port bitmap. + * \param [out] _port Port iterator variable. + */ +#define BCMDRD_PBMP_ITER(_pbmp, _port) \ + for (_port = 0; _port < BCMDRD_CONFIG_MAX_PORTS; _port++) \ + if (BCMDRD_PBMP_WORD(_pbmp, _port) == 0) \ + _port += 31; \ + else if (BCMDRD_PBMP_MEMBER(_pbmp, _port)) + +/*! + * \brief Iterate over a port bitmap with maximum. + * + * Iterate over a port bitmap of type \ref bcmdrd_pbmp_t and execute + * the subsequent statement for all bits set in the port bitmap. + * + * The iteration will be terminated if the iterator variable reaches + * the value of \c _port_max. This macro is mainly intended to prevent + * false errors from static analysis tools like Coverity. + * + * \param [in] _pbmp Port bitmap. + * \param [in] _port_max Maximum number of ports. + * \param [out] _port Port iterator variable. + */ +#define BCMDRD_PBMP_MAX_ITER(_pbmp, _port_max, _port) \ + for (_port = 0; \ + _port < _port_max && _port < BCMDRD_CONFIG_MAX_PORTS; \ + _port++) \ + if (BCMDRD_PBMP_WORD(_pbmp, _port) == 0) \ + _port += 31; \ + else if (BCMDRD_PBMP_MEMBER(_pbmp, _port)) + +/*! + * \brief Add a port to a port bitmap. + * + * Add a port to a port bitmap of type \ref bcmdrd_pbmp_t. + * + * No range check is performed on the port number. + * + * \param [in] _pbmp Port bitmap. + * \param [in] _port Port number to add. + */ +#define BCMDRD_PBMP_PORT_ADD(_pbmp, _port) \ + (BCMDRD_PBMP_WORD(_pbmp, _port) |= LSHIFT32(1, (_port) & 0x1f)) + +/*! + * \brief Remove a port from a port bitmap. + * + * Remove a port from a port bitmap of type \ref bcmdrd_pbmp_t. + * + * No range check is performed on the port number. + * + * \param [in] _pbmp Port bitmap. + * \param [in] _port Port number to remove. + */ +#define BCMDRD_PBMP_PORT_REMOVE(_pbmp, _port) \ + (BCMDRD_PBMP_WORD(_pbmp, _port) &= ~(LSHIFT32(1, (_port) & 0x1f))) + +/*! + * \brief Clear a port bitmap. + * + * Clear a port bitmap of type \ref bcmdrd_pbmp_t. + * + * After clearing the port bitmap, it will have no members.. + * + * \param [in] _pbmp Port bitmap. + */ +#define BCMDRD_PBMP_CLEAR(_pbmp) sal_memset(&_pbmp, 0, sizeof(bcmdrd_pbmp_t)) + +/*! + * \brief Get a word from a port bitmap. + * + * Get a 32-bit word from a port bitmap of type \ref bcmdrd_pbmp_t. + * + * \param [in] _pbmp Port bitmap. + * \param [in] _w Word number to get (first word is word 0). + */ +#define BCMDRD_PBMP_WORD_GET(_pbmp, _w) ((&(_pbmp))->w[_w]) + +/*! + * \brief Set a word in a port bitmap. + * + * Set a 32-bit word in a port bitmap of type \ref bcmdrd_pbmp_t. + * + * \param [in] _pbmp Port bitmap. + * \param [in] _w Word number to set (first word is word 0). + * \param [in] _val Value of word to set. + */ +#define BCMDRD_PBMP_WORD_SET(_pbmp, _w, _val) ((&(_pbmp))->w[_w]) = (_val) + +/*! + * \brief Helper macro for port bimap operations. + * + * \param [in] _pbmp0 First port bitmap. + * \param [in] _pbmp1 Second port bitmap. + * \param [in] _op Port bitmap operator. + */ +#define BCMDRD_PBMP_BMOP(_pbmp0, _pbmp1, _op) \ + do { \ + int _w; \ + for (_w = 0; _w < BCMDRD_PBMP_WORD_MAX; _w++) { \ + BCMDRD_PBMP_WORD_GET(_pbmp0, _w) _op BCMDRD_PBMP_WORD_GET(_pbmp1, _w); \ + } \ + } while (0) + +/*! Return true if port bitmap _pbmp is empty. */ +#define BCMDRD_PBMP_IS_NULL(_pbmp) (bcmdrd_pbmp_is_null(&(_pbmp))) + +/*! Return true if port bitmap _pbmp is not empty. */ +#define BCMDRD_PBMP_NOT_NULL(_pbmp) (!(bcmdrd_pbmp_is_null(&(_pbmp)))) + +/*! Assign port bitmap src to port bitmap dst. */ +#define BCMDRD_PBMP_ASSIGN(dst, src) sal_memcpy(&(dst), &(src), sizeof(bcmdrd_pbmp_t)) + +/*! + * Perform a logical AND operation between all bits of port bitmaps _pbmp0 and + * pbmp1. + */ +#define BCMDRD_PBMP_AND(_pbmp0, _pbmp1) BCMDRD_PBMP_BMOP(_pbmp0, _pbmp1, &=) + +/*! + * Perform a logical OR operation between all bits of port bitmaps _pbmp0 and + * pbmp1. + */ +#define BCMDRD_PBMP_OR(_pbmp0, _pbmp1) BCMDRD_PBMP_BMOP(_pbmp0, _pbmp1, |=) + +/*! + * Perform a logical XOR operation between all bits of port bitmaps _pbmp0 and + * pbmp1. + */ +#define BCMDRD_PBMP_XOR(_pbmp0, _pbmp1) BCMDRD_PBMP_BMOP(_pbmp0, _pbmp1, ^=) + +/*! + * Remove all bits in port bitmap _pbmp1 from port bitmap _pbmp0. + */ +#define BCMDRD_PBMP_REMOVE(_pbmp0, _pbmp1) BCMDRD_PBMP_BMOP(_pbmp0, _pbmp1, &= ~) + +/*! + * Assign an inversed port bitmap _pbmp1 to port bitmap _pbmp0, + * i.e. any port which is a member of _pbmp1 will not be a member of + * _pbmp0 and vice versa. + */ +#define BCMDRD_PBMP_NEGATE(_pbmp0, _pbmp1) BCMDRD_PBMP_BMOP(_pbmp0, _pbmp1, = ~) + +/*! Convert a number of (8-bit) bytes to a number of bits. */ +#define BCMDRD_BYTES2BITS(_x) ((_x) * 8) + +/*! Convert a number of (8-bit) bytes to a number of 32-bit words. */ +#define BCMDRD_BYTES2WORDS(_x) (((_x) + 3) / 4) + +/*! Convert a number of 32-bit words to a number of bits. */ +#define BCMDRD_WORDS2BITS(_x) ((_x) * 32) + +/*! Convert a number of 32-bit words to a number of (8-bit) bytes. */ +#define BCMDRD_WORDS2BYTES(_x) ((_x) * 4) + +/*! Align a size to a specific number of bytes. */ +#define BCMDRD_ALIGN(_s, _a) (((_s) + ((_a) - 1)) & ~((_a) - 1)) + +/*! Maximum size of physical table entry (in words). */ +#define BCMDRD_MAX_PT_WSIZE \ + BCMDRD_BYTES2WORDS(BCMDRD_CONFIG_MAX_PT_ENTRY_SIZE) + +/*! Create enumeration values from list of supported devices. */ +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + BCMDRD_DEV_T_##_bd, +/*! Enumeration for all base device types. */ +typedef enum { + BCMDRD_DEV_T_NONE = 0, +/*! \cond */ +#include +/*! \endcond */ + BCMDRD_DEV_T_COUNT +} bcmdrd_dev_type_t; + +/*! Generic ID (enum). */ +typedef uint32_t bcmdrd_id_t; + +/*! Generic invalid ID value. */ +#define BCMDRD_INVALID_ID ((bcmdrd_id_t)-1) + +/*! Invalid register value. */ +#define INVALIDr BCMDRD_INVALID_ID + +/*! Invalid memory value. */ +#define INVALIDm BCMDRD_INVALID_ID + +/*! Invalid field value. */ +#define INVALIDf BCMDRD_INVALID_ID + +/*! Check if an ID is valid, i.e. different from BCMDRD_INVALID_ID. */ +#define BCMDRD_ID_VALID(_id) \ + ((_id) != BCMDRD_INVALID_ID) + +/*! Device-specific symbol ID (enum). */ +typedef bcmdrd_id_t bcmdrd_sid_t; + +/*! Device-specific field ID (enum). */ +typedef bcmdrd_id_t bcmdrd_fid_t; + +/*! Enum for string/value map. */ +typedef shr_enum_map_t bcmdrd_enum_map_t; + +/*! + * \brief Port number domain. + * + * Port-based registers and memories use different port number domains + * in their physical address. For example, some registers use the + * physical port number, some registers use the logical port number + * and some use a MMU port number. + * + * For most devices, each block type use the same port number domain, + * but there are a few exceptions, so this needs to be a per-reg/mem + * property. + */ +typedef enum bcmdrd_port_num_domain_e { + BCMDRD_PND_PHYS = 0, + BCMDRD_PND_LOGIC = 1, + BCMDRD_PND_MMU = 2, + BCMDRD_PND_COUNT +} bcmdrd_port_num_domain_t; + +/*! + * \name Port types. + * \anchor BCMDRD_PORT_TYPE_xxx + * + * Port types are defined as bit masks, such that it is possible to + * group multiple types into a single one, e.g. CPU and loopback ports + * could be greoup as internal ports. + */ + +/*! \{ */ + +/*! Port type undefined. */ +#define BCMDRD_PORT_TYPE_UNDEF 0 + +/*! Reserved port (e.g. spare port or other unused port). */ +#define BCMDRD_PORT_TYPE_RSVD (1U << 0) + +/*! CPU/HMI port (internal). */ +#define BCMDRD_PORT_TYPE_CPU (1U << 1) + +/*! Loopback port (internal). */ +#define BCMDRD_PORT_TYPE_LB (1U << 2) + +/*! Front-panel port. */ +#define BCMDRD_PORT_TYPE_FPAN (1U << 3) + +/*! Up-link port. */ +#define BCMDRD_PORT_TYPE_UPLINK (1U << 4) + +/*! Management port. */ +#define BCMDRD_PORT_TYPE_MGMT (1U << 5) + +/*! RDB port. */ +#define BCMDRD_PORT_TYPE_RDB (1U << 6) + +/*! FAE port. */ +#define BCMDRD_PORT_TYPE_FAE (1U << 7) + +/*! AUX port. */ +#define BCMDRD_PORT_TYPE_AUX (1U << 8) +/*! } */ + +/*! + * \brief Port category. + * + * Please refer to \ref BCMDRD_PORT_TYPE_xxx for a list possible + * values (categories). + * + * Values are bit-based such that a port can belong to multiple + * categories. + */ +typedef uint32_t bcmdrd_port_type_t; + +/*! Words in pipe maps */ +#define BCMDRD_PIPEMAP_WORD_MAX (((BCMDRD_CONFIG_MAX_PIPES - 1) >> 5) + 1) + +/*! + * Bitmap of pipes of a particular type. + */ +typedef struct bcmdrd_pipemap_s { + /*! Word array. */ + uint32_t w[BCMDRD_PIPEMAP_WORD_MAX]; +} bcmdrd_pipemap_t; + +/* pipe map helper functions */ + +/*! + * \brief Check if pipe map is empty. + * + * Check that no bits are set in a pipe map of type \ref + * bcmdrd_pipemap_t. + * + * \param [in] pm pipe map. + * + * \retval true Pipe map is empty. + * \retval false Pipe map is not empty. + */ +extern bool +bcmdrd_pipemap_is_null(const bcmdrd_pipemap_t *pm); + +/*! + * \brief Get bitmap word index for a given pipe. + * + * A pipe map is an array of data words, and this macro will return + * the index of the data word associated with a given pipe number. + * + * No range check is performed on the pipe number. + * + * \param [in] _pm Pipe map. + * \param [in] _pipe Pipe number to check. + */ +#define BCMDRD_PIPEMAP_WORD(_pm, _pipe) \ + (&(_pm))->w[(_pipe) >> 5] + +/*! + * \brief Check if a pipe is member of a pipe map. + * + * Check if a pipe is member of a pipe map of type \ref + * bcmdrd_pipemap_t. + * + * No range check is performed on the pipe number. + * + * \param [in] _pm Pipe map. + * \param [in] _pipe Pipe number to check. + */ +#define BCMDRD_PIPEMAP_MEMBER(_pm, _pipe) \ + (BCMDRD_PIPEMAP_WORD(_pm, _pipe) & LSHIFT32(1, (_pipe) & 0x1f)) + +/*! + * \brief Iterate over a pipe map. + * + * Iterate over a pipe map of type \ref bcmdrd_pipemap_t and + * execute the subsequent statement for all bits set in the pipe + * bitmap. + * + * \param [in] _pm Pipe map. + * \param [out] _pipe Pipe iterator variable. + */ +#define BCMDRD_PIPEMAP_ITER(_pm, _pipe) \ + for (_pipe = 0; _pipe < BCMDRD_CONFIG_MAX_PIPES; _pipe++) \ + if (BCMDRD_PIPEMAP_WORD(_pm, _pipe) == 0) \ + _pipe += 31; \ + else if (BCMDRD_PIPEMAP_MEMBER(_pm, _pipe)) + +/*! + * \brief Iterate over a pipe map with maximum. + * + * Iterate over a pipe map of type \ref bcmdrd_pipemap_t and + * execute the subsequent statement for all bits set in the pipe + * bitmap. + * + * The iteration will be terminated if the iterator variable reaches + * the value of \c _pipe_max. This macro is mainly intended to prevent + * false errors from static analysis tools like Coverity. + * + * \param [in] _pm Pipe map. + * \param [in] _pipe_max Maximum number of pipes. + * \param [out] _pipe Pipe iterator variable. + */ +#define BCMDRD_PIPEMAP_MAX_ITER(_pm, _pipe_max, _pipe) \ + for (_pipe = 0; \ + _pipe < _pipe_max && _pipe < BCMDRD_CONFIG_MAX_PIPES; \ + _pipe++) \ + if (BCMDRD_PIPEMAP_WORD(_pm, _pipe) == 0) \ + _pipe += 31; \ + else if (BCMDRD_PIPEMAP_MEMBER(_pm, _pipe)) + +/*! + * \brief Add a pipe to a pipe map. + * + * Add a pipe to a pipe map of type \ref bcmdrd_pipemap_t. + * + * No range check is performed on the pipe number. + * + * \param [in] _pm Pipe map. + * \param [in] _pipe Pipe number to add. + */ +#define BCMDRD_PIPEMAP_PIPE_ADD(_pm, _pipe) \ + (BCMDRD_PIPEMAP_WORD(_pm, _pipe) |= LSHIFT32(1, (_pipe) & 0x1f)) + +/*! + * \brief Remove a pipe from a pipe map. + * + * Remove a pipe from a pipe map of type \ref bcmdrd_pipemap_t. + * + * No range check is performed on the pipe number. + * + * \param [in] _pm Pipe map. + * \param [in] _pipe Pipe number to remove. + */ +#define BCMDRD_PIPEMAP_PIPE_REMOVE(_pm, _pipe) \ + (BCMDRD_PIPEMAP_WORD(_pm, _pipe) &= ~(LSHIFT32(1, (_pipe) & 0x1f))) + +/*! + * \brief Clear a pipe map. + * + * Clear a pipe map of type \ref bcmdrd_pipemap_t. + * + * After clearing the pipe map, it will have no members. + * + * \param [in] _pm Pipe map. + */ +#define BCMDRD_PIPEMAP_CLEAR(_pm) \ + sal_memset(&_pm, 0, sizeof(bcmdrd_pipemap_t)) + +/*! + * \brief Get a word from a pipe map. + * + * Get a 32-bit word from a pipe map of type \ref bcmdrd_pipemap_t. + * + * \param [in] _pm Pipe map. + * \param [in] _w Word number to get (first word is word 0). + */ +#define BCMDRD_PIPEMAP_WORD_GET(_pm, _w) \ + ((&(_pm))->w[_w]) + +/*! + * \brief Set a word in a pipe map. + * + * Set a 32-bit word in a pipe map of type \ref bcmdrd_pipemap_t. + * + * \param [in] _pm Pipe map. + * \param [in] _w Word number to set (first word is word 0). + * \param [in] _val Value of word to set. + */ +#define BCMDRD_PIPEMAP_WORD_SET(_pm, _w, _val) \ + ((&(_pm))->w[_w]) = (_val) + +/*! + * \brief Helper macro for pipe map operations. + * + * \param [in] _pm0 First pipe map. + * \param [in] _pm1 Second pipe map. + * \param [in] _op Pipe map operator. + */ +#define BCMDRD_PIPEMAP_BMOP(_pm0, _pm1, _op) \ + do { \ + int _w; \ + for (_w = 0; _w < BCMDRD_PIPEMAP_WORD_MAX; _w++) { \ + BCMDRD_PIPEMAP_WORD_GET(_pm0, _w) _op BCMDRD_PIPEMAP_WORD_GET(_pm1, _w); \ + } \ + } while (0) + +/*! Return true if pipe map _pm is empty. */ +#define BCMDRD_PIPEMAP_IS_NULL(_pm) \ + (bcmdrd_pipemap_is_null(&(_pm))) + +/*! Return true if pipe map _pm is not empty. */ +#define BCMDRD_PIPEMAP_NOT_NULL(_pm) \ + (!(bcmdrd_pipemap_is_null(&(_pm)))) + +/*! Assign pipe map src to pipe map dst. */ +#define BCMDRD_PIPEMAP_ASSIGN(dst, src) \ + sal_memcpy(&(dst), &(src), sizeof(bcmdrd_pipemap_t)) + +/*! + * Perform a logical AND operation between all bits of pipe maps _pm0 + * and _pm1. + */ +#define BCMDRD_PIPEMAP_AND(_pm0, _pm1) \ + BCMDRD_PIPEMAP_BMOP(_pm0, _pm1, &=) + +/*! + * Perform a logical OR operation between all bits of pipe maps _pm0 + * and _pm1. + */ +#define BCMDRD_PIPEMAP_OR(_pm0, _pm1) \ + BCMDRD_PIPEMAP_BMOP(_pm0, _pm1, |=) + +/*! + * Perform a logical XOR operation between all bits of pipe maps _pm0 + * and _pm1. + */ +#define BCMDRD_PIPEMAP_XOR(_pm0, _pm1) \ + BCMDRD_PIPEMAP_BMOP(_pm0, _pm1, ^=) + +/*! + * Remove all bits in pipe map _pm1 from pipe map _pm0. + */ +#define BCMDRD_PIPEMAP_REMOVE(_pm0, _pm1) \ + BCMDRD_PIPEMAP_BMOP(_pm0, _pm1, &= ~) + +/*! + * Assign an inversed pipe map _pm1 to pipe map _pm0, i.e. any pipe + * which is a member of _pm1 will not be a member of _pm0 and vice + * versa. + */ +#define BCMDRD_PIPEMAP_NEGATE(_pm0, _pm1) \ + BCMDRD_PIPEMAP_BMOP(_pm0, _pm1, = ~) + +#endif /* BCMDRD_TYPES_H */ diff --git a/src/bcm/common/pktio/bcmdrd/include/bcmdrd_config.h b/src/bcm/common/pktio/bcmdrd/include/bcmdrd_config.h new file mode 100644 index 0000000..9ae4c9a --- /dev/null +++ b/src/bcm/common/pktio/bcmdrd/include/bcmdrd_config.h @@ -0,0 +1,202 @@ +/*! \file bcmdrd_config.h + * + * This config file defines all compilation-time specifications for + * the BCMDRD. + * + * Reasonable defaults are provided for all configuration options + * where appropriate. + * + * You need not edit this file directly to change your configuration, + * nor is modifying this file advised -- so doing will require + * manually merging whenever the BCMDRD is upgraded. + * + * You should provide your own configuration options or overrides + * through a combination of: + * + * 1. The compiler command line, such as -D{OPTION}={VALUE} + * + * 2. Create your own custom configuration file: + * a) Create a file called 'bcmdrd_custom_config.h' + * b) Define all custom settings, using this file as + * the reference + * c) Add -DBCMDRD_INCLUDE_CUSTOM_CONFIG to your + * compilation + * d) Make sure the compilation include path includes + * 'bcmdrd_custom_config.h' + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMDRD_CONFIG_H +#define BCMDRD_CONFIG_H + +/* + * Include system config file if specified: + */ +#ifdef BCMDRD_INCLUDE_CUSTOM_CONFIG +#include +#endif + +/* + * OPTIONAL configuration and feature values. + * Defaults are provided for all non-specified values. + */ + +/*! Maximum number of chips supported. */ +#ifndef BCMDRD_CONFIG_MAX_UNITS +#define BCMDRD_CONFIG_MAX_UNITS 8 +#endif + +/*! Maximum number of ports per chip supported. */ +#ifndef BCMDRD_CONFIG_MAX_PORTS +#define BCMDRD_CONFIG_MAX_PORTS 1088 +#endif + +/*! Maximum number of pipes per chip supported. */ +#ifndef BCMDRD_CONFIG_MAX_PIPES +#define BCMDRD_CONFIG_MAX_PIPES 96 +#endif + +/*! Maximum size of physical table entries (in bytes). */ +#ifndef BCMDRD_CONFIG_MAX_PT_ENTRY_SIZE +#define BCMDRD_CONFIG_MAX_PT_ENTRY_SIZE 128 +#endif + +/*! Maximum number of interrupt lines per chip supported. */ +#ifndef BCMDRD_CONFIG_MAX_IRQ_LINES +#define BCMDRD_CONFIG_MAX_IRQ_LINES 16 +#endif + +/*! Direct access to memory-mapped registers. */ +#ifndef BCMDRD_CONFIG_MEMMAP_DIRECT +#define BCMDRD_CONFIG_MEMMAP_DIRECT 0 +#endif + +/*! + * \brief Include chip symbol tables. + * + * No symbolic debugging (register/memory names) will be available + * without this defined. + * + * This define is required to get any symbols at all. + * + * Symbols tables are required for normal SDK operation, but may be + * excluded for small footprint base driver applications. + * + * If you only wish to include symbols for a subset of chips in the + * system (probably for code space reasons), you can define the + * following for each chip whose symbols you wish to EXCLUDE: + * + * BCMDRD_CONFIG_EXCLUDE_CHIP_SYMBOLS_ + * + */ +#ifndef BCMDRD_CONFIG_INCLUDE_CHIP_SYMBOLS +#define BCMDRD_CONFIG_INCLUDE_CHIP_SYMBOLS 1 +#endif + +/*! + * \brief Include register and memory field information. + * + * This provides encoding, decoding, and displaying individual field + * values for each register and memory. + * + * Requires more code space than just the chip symbols alone. + * + * Symbols field information is required for normal SDK operation, but + * may be excluded for small footprint base driver applications. + * + * The per-chip exclusion define + * (BCMDRD_CONFIG_EXCLUDE_FIELD_INFO_) also applies. + */ +#ifndef BCMDRD_CONFIG_INCLUDE_FIELD_INFO +#define BCMDRD_CONFIG_INCLUDE_FIELD_INFO 1 +#endif + +/*! + * \brief Include alternative symbol names for registers and memories. + * + * Mainly for internal Broadcom use, so you can safely leave this + * option off. + */ +#ifndef BCMDRD_CONFIG_INCLUDE_ALIAS_NAMES +#define BCMDRD_CONFIG_INCLUDE_ALIAS_NAMES 1 +#endif + +/*! + * \brief Include field size checks for registers and memories. + * + * This option adds compile-time checks for field values exceeding the + * size of the field being assigned. The check in mainly intended for + * internal use, and it may trigger warnings from various memory + * sanity checker tools. + */ +#ifndef BCMDRD_CONFIG_INCLUDE_FIELD_CHECKS +#define BCMDRD_CONFIG_INCLUDE_FIELD_CHECKS 0 +#endif + +#endif /* BCMDRD_CONFIG_H */ + +#ifdef CONFIG_OPTION +#ifdef BCMDRD_INCLUDE_CUSTOM_CONFIG +CONFIG_OPTION(BCMDRD_INCLUDE_CUSTOM_CONFIG) +#endif +#ifdef BCMDRD_CONFIG_MAX_UNITS +CONFIG_OPTION(BCMDRD_CONFIG_MAX_UNITS) +#endif +#ifdef BCMDRD_CONFIG_MAX_PORTS +CONFIG_OPTION(BCMDRD_CONFIG_MAX_PORTS) +#endif +#ifdef BCMDRD_CONFIG_MAX_PIPES +CONFIG_OPTION(BCMDRD_CONFIG_MAX_PIPES) +#endif +#ifdef BCMDRD_CONFIG_MAX_PT_ENTRY_SIZE +CONFIG_OPTION(BCMDRD_CONFIG_MAX_PT_ENTRY_SIZE) +#endif +#ifdef BCMDRD_CONFIG_MAX_IRQ_LINES +CONFIG_OPTION(BCMDRD_CONFIG_MAX_IRQ_LINES) +#endif +#ifdef BCMDRD_CONFIG_MEMMAP_DIRECT +CONFIG_OPTION(BCMDRD_CONFIG_MEMMAP_DIRECT) +#endif +#ifdef BCMDRD_CONFIG_INCLUDE_CHIP_SYMBOLS +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_CHIP_SYMBOLS) +#endif +#ifdef BCMDRD_CONFIG_INCLUDE_FIELD_INFO +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_FIELD_INFO) +#endif +#ifdef BCMDRD_CONFIG_INCLUDE_ALIAS_NAMES +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_ALIAS_NAMES) +#endif +#ifdef BCMDRD_CONFIG_INCLUDE_FIELD_CHECKS +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_FIELD_CHECKS) +#endif +#endif /* CONFIG_OPTION */ +#include "bcmdrd_config_chips.h" diff --git a/src/bcm/common/pktio/bcmdrd/include/bcmdrd_config_chips.h b/src/bcm/common/pktio/bcmdrd/include/bcmdrd_config_chips.h new file mode 100644 index 0000000..27be6d9 --- /dev/null +++ b/src/bcm/common/pktio/bcmdrd/include/bcmdrd_config_chips.h @@ -0,0 +1,550 @@ +/* + * DO NOT EDIT THIS FILE! + * This file is auto-generated. + * Edits to this file will be lost when it is regenerated. + * Tool: INTERNAL/drd/instpkgs.pl + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +/* + * Chip inclusion and exclusion support within the BCMDRD can be + * specified as a combination of the following defines: + * + * (1) #define BCMDRD_CONFIG_INCLUDE_ [1|0] + * -- Include or exclude all revisions of the given device + * Example: #define BCMDRD_CONFIG_INCLUDE_BCM78920 1 + * + * (2) #define BCMDRD_CONFIG_INCLUDE__X [1|0] + * -- Include or exclude all versions of the given revision + * Example: #define BCMDRD_CONFIG_INCLUDE_BCM78920_Ax 0 + * #define BCMDRD_CONFIG_INCLUde_BCM78920_Bx 1 + * + * (3) #define BCMDRD_CONFIG_INCLUDE_ [1|0] + * -- Include or exclude an exact device + * Example: #define BCMDRD_CONFIG_INCLUDE_BCM78920_A0 1 + * #define BCMDRD_CONFIG_INCLUDE_BCM78920_A1 0 + * + * + * The value of BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT is used for any + * chips which are left unspecified. Set this value to 1 or 0 to + * include or exclude all chips by default. + * + */ + +#ifndef BCMDRD_CONFIG_CHIPS_H +#define BCMDRD_CONFIG_CHIPS_H + +/* This determines whether a chip is included or excluded by default */ +#ifndef BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#define BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT 1 +#endif + +/* + * Default configuration and dependencies for all chips + */ + +/* + * BCM88860 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88860 +#define BCMDRD_CONFIG_INCLUDE_BCM88860 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88860_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM88860_Ax BCMDRD_CONFIG_INCLUDE_BCM88860 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88860_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88860_A0 BCMDRD_CONFIG_INCLUDE_BCM88860_Ax +#endif + +/* + * BCM88867 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88867 +#define BCMDRD_CONFIG_INCLUDE_BCM88867 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88867_Cx +#define BCMDRD_CONFIG_INCLUDE_BCM88867_Cx BCMDRD_CONFIG_INCLUDE_BCM88867 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88867_C0 +#define BCMDRD_CONFIG_INCLUDE_BCM88867_C0 BCMDRD_CONFIG_INCLUDE_BCM88867_Cx +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88867_C0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM88860_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM88860_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88860_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM88860_A0_IMPLIED 1 +#endif +#endif + +/* + * BCM88890 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88890 +#define BCMDRD_CONFIG_INCLUDE_BCM88890 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88890_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM88890_Ax BCMDRD_CONFIG_INCLUDE_BCM88890 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88890_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88890_A0 BCMDRD_CONFIG_INCLUDE_BCM88890_Ax +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88890_A0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM88860_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM88860_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88860_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM88860_A0_IMPLIED 1 +#endif +#endif + +/* + * BCM88897 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88897 +#define BCMDRD_CONFIG_INCLUDE_BCM88897 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88897_Cx +#define BCMDRD_CONFIG_INCLUDE_BCM88897_Cx BCMDRD_CONFIG_INCLUDE_BCM88890 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88897_C0 +#define BCMDRD_CONFIG_INCLUDE_BCM88897_C0 BCMDRD_CONFIG_INCLUDE_BCM88897_Cx +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88897_C0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM88860_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM88860_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88860_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM88860_A0_IMPLIED 1 +#endif +#endif + +/* + * BCM88870 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88870 +#define BCMDRD_CONFIG_INCLUDE_BCM88870 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88870_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM88870_Ax BCMDRD_CONFIG_INCLUDE_BCM88870 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88870_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88870_A0 BCMDRD_CONFIG_INCLUDE_BCM88870_Ax +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88870_A0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM88860_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM88860_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88860_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM88860_A0_IMPLIED 1 +#endif +#endif + +/* + * BCM88490 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88490 +#define BCMDRD_CONFIG_INCLUDE_BCM88490 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88490_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM88490_Ax BCMDRD_CONFIG_INCLUDE_BCM88490 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88490_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88490_A0 BCMDRD_CONFIG_INCLUDE_BCM88490_Ax +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88490_A0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM88860_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM88860_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88860_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM88860_A0_IMPLIED 1 +#endif +#endif + +/* + * BCM99450 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM99450 +#define BCMDRD_CONFIG_INCLUDE_BCM99450 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM99450_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM99450_Ax BCMDRD_CONFIG_INCLUDE_BCM99450 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM99450_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM99450_A0 BCMDRD_CONFIG_INCLUDE_BCM99450_Ax +#endif + +/* + * BCM99410 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM99410 +#define BCMDRD_CONFIG_INCLUDE_BCM99410 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM99410_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM99410_Ax BCMDRD_CONFIG_INCLUDE_BCM99410 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM99410_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM99410_A0 BCMDRD_CONFIG_INCLUDE_BCM99410_Ax +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM99410_A0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM99450_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM99450_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM99450_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM99450_A0_IMPLIED 1 +#endif +#endif + +/* + * BCM99430 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM99430 +#define BCMDRD_CONFIG_INCLUDE_BCM99430 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM99430_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM99430_Ax BCMDRD_CONFIG_INCLUDE_BCM99430 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM99430_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM99430_A0 BCMDRD_CONFIG_INCLUDE_BCM99430_Ax +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM99430_A0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM99450_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM99450_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM99450_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM99450_A0_IMPLIED 1 +#endif +#endif + +/* + * BCM994E0 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM994E0 +#define BCMDRD_CONFIG_INCLUDE_BCM994E0 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM994E0_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM994E0_Ax BCMDRD_CONFIG_INCLUDE_BCM994E0 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM994E0_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM994E0_A0 BCMDRD_CONFIG_INCLUDE_BCM994E0_Ax +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM994E0_A0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM99450_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM99450_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM99450_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM99450_A0_IMPLIED 1 +#endif +#endif + + + + +/* + * BCM88690 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88690 +#define BCMDRD_CONFIG_INCLUDE_BCM88690 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88690_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM88690_Ax BCMDRD_CONFIG_INCLUDE_BCM88690 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88690_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88690_A0 BCMDRD_CONFIG_INCLUDE_BCM88690_Ax +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88690_Bx +#define BCMDRD_CONFIG_INCLUDE_BCM88690_Bx BCMDRD_CONFIG_INCLUDE_BCM88690 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88690_B0 +#define BCMDRD_CONFIG_INCLUDE_BCM88690_B0 BCMDRD_CONFIG_INCLUDE_BCM88690_Bx +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88690_B0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM88690_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM88690_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88690_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM88690_A0_IMPLIED 1 +#endif +#endif + +/* + * BCM88800 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88800 +#define BCMDRD_CONFIG_INCLUDE_BCM88800 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88800_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM88800_Ax BCMDRD_CONFIG_INCLUDE_BCM88800 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88800_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88800_A0 BCMDRD_CONFIG_INCLUDE_BCM88800_Ax +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88800_A0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM88690_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM88690_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88690_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM88690_A0_IMPLIED 1 +#endif +#endif + +/* + * BCM88850 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88850 +#define BCMDRD_CONFIG_INCLUDE_BCM88850 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88850_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM88850_Ax BCMDRD_CONFIG_INCLUDE_BCM88850 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88850_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88850_A0 BCMDRD_CONFIG_INCLUDE_BCM88850_Ax +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88850_A0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM88690_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM88690_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88690_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM88690_A0_IMPLIED 1 +#endif +#endif + +/* + * BCM88830 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88830 +#define BCMDRD_CONFIG_INCLUDE_BCM88830 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88830_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM88830_Ax BCMDRD_CONFIG_INCLUDE_BCM88830 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88830_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88830_A0 BCMDRD_CONFIG_INCLUDE_BCM88830_Ax +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88830_A0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM88690_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM88690_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88690_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM88690_A0_IMPLIED 1 +#endif +#endif + +/* + * BCM88480 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88480 +#define BCMDRD_CONFIG_INCLUDE_BCM88480 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88480_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM88480_Ax BCMDRD_CONFIG_INCLUDE_BCM88480 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88480_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88480_A0 BCMDRD_CONFIG_INCLUDE_BCM88480_Ax +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88480_Bx +#define BCMDRD_CONFIG_INCLUDE_BCM88480_Bx BCMDRD_CONFIG_INCLUDE_BCM88480 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88480_B0 +#define BCMDRD_CONFIG_INCLUDE_BCM88480_B0 BCMDRD_CONFIG_INCLUDE_BCM88480_Bx +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88480_B0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM88480_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM88480_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88480_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM88480_A0_IMPLIED 1 +#endif +#endif +#if BCMDRD_CONFIG_INCLUDE_BCM88480_A0 == 1 +#if BCMDRD_CONFIG_INCLUDE_BCM88690_A0 != 1 +#undef BCMDRD_CONFIG_INCLUDE_BCM88690_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88690_A0 1 +#define BCMDRD_CONFIG_INCLUDE_BCM88690_A0_IMPLIED 1 +#endif +#endif + +/* + * BCM88920 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88920 +#define BCMDRD_CONFIG_INCLUDE_BCM88920 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88920_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM88920_Ax BCMDRD_CONFIG_INCLUDE_BCM88920 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM88920_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM88920_A0 BCMDRD_CONFIG_INCLUDE_BCM88920_Ax +#endif + +/* + * BCM99470 + */ + +/* Sets the default include state if it was not given */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM99470 +#define BCMDRD_CONFIG_INCLUDE_BCM99470 BCMDRD_CONFIG_INCLUDE_CHIP_DEFAULT +#endif +/* Resolve revision dependencies */ +#ifndef BCMDRD_CONFIG_INCLUDE_BCM99470_Ax +#define BCMDRD_CONFIG_INCLUDE_BCM99470_Ax BCMDRD_CONFIG_INCLUDE_BCM99470 +#endif +#ifndef BCMDRD_CONFIG_INCLUDE_BCM99470_A0 +#define BCMDRD_CONFIG_INCLUDE_BCM99470_A0 BCMDRD_CONFIG_INCLUDE_BCM99470_Ax +#endif + +#endif /* BCMDRD_CONFIG_CHIPS_H */ + +/* + * CONFIG_OPTION Macros. Can be used to determine the build configuration. + */ + +#ifdef CONFIG_OPTION +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88860) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88860_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88860_A0) + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88867) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88867_Cx) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88867_C0) + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88890) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88890_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88890_A0) + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88897) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88897_Cx) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88897_C0) + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88870) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88870_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88870_A0) + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88490) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88490_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88490_A0) +#ifdef BCMDRD_CONFIG_INCLUDE_BCM88860_A0_IMPLIED +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88860_A0_IMPLIED) +#endif + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM99450) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM99450_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM99450_A0) + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM99410) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM99410_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM99410_A0) + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM99430) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM99430_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM99430_A0) + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM994E0) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM994E0_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM994E0_A0) + + + + +#ifdef BCMDRD_CONFIG_INCLUDE_BCM99450_A0_IMPLIED +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM99450_A0_IMPLIED) +#endif + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88690) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88690_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88690_A0) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88690_Bx) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88690_B0) + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88800) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88800_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88800_A0) + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88850) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88850_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88850_A0) + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88830) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88830_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88830_A0) + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88480) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88480_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88480_A0) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88480_Bx) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88480_B0) +#ifdef BCMDRD_CONFIG_INCLUDE_BCM88690_A0_IMPLIED +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88690_A0_IMPLIED) +#endif + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88920) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88920_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM88920_A0) + +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM99470) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM99470_Ax) +CONFIG_OPTION(BCMDRD_CONFIG_INCLUDE_BCM99470_A0) +#undef CONFIG_OPTION +#endif /* #ifdef CONFIG_OPTION */ diff --git a/src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_conf.h b/src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_conf.h new file mode 100644 index 0000000..1bad50e --- /dev/null +++ b/src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_conf.h @@ -0,0 +1,180 @@ +/*! \file bcmlrd_conf.h + * + * \brief Public interface to access the configuration. + * + * This file should not depend on any other header files than the SAL + * types. It is used for building libraries that are only a small + * subset of the full SDK (e.g. the PMD library). + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMLRD_CONF_H +#define BCMLRD_CONF_H + +#ifndef PKTIO_IMPL +#include +#endif + +/*! Create enumeration values from list of supported variants. */ +#define BCMLRD_VARIANT_ENTRY(_bd,_bu,_va,_ve,_vu,_vv,_vo,_vd,_r0,_r1)\ + BCMLRD_VARIANT_T_##_bd##_##_ve, + +/*! Enumeration for all device variants. */ +typedef enum bcmlrd_variant_e { + BCMLRD_VARIANT_T_NONE = 0, +/*! \cond */ +#include +/*! \endcond */ + BCMLRD_VARIANT_T_COUNT +} bcmlrd_variant_t; + +/*! + * \brief Get device variant. + * + * Get device logical table variant, + * which is an enumeration of all supported logical table variants. + * + * \param [in] unit Unit number. + * + * \retval Variant type. + */ +extern bcmlrd_variant_t +bcmlrd_variant_get(int unit); + +/*! + * \brief Set device variant. + * + * Set device logical table variant, + * which is an enumeration of all supported logical table variants. + * + * \param [in] unit Unit number. + * \param [in] variant BCMLRD variant enumeration. + * + * \retval 0 OK + * \retval <0 ERROR + */ +extern int +bcmlrd_variant_set(int unit, bcmlrd_variant_t variant); + +/*! + * \brief Return bcmlrd_variant_t enum from LTL DEVICE_VARIANT_T. + * + * Return a bcmlrd_variant_t enum value from a LTL DEVICE_VARIANT_T + * symbolic value. + * + * The DEVICE_VARIANT_T LTL enum is based on all the devices and + * variants present in the source tree when SDKLT logical table code + * is generated and is numbered starting at one, assigning a unique + * integer for each base and variant logical table configuration. The + * bcmlrd_variant_t C enum values are determined at compile time based + * on which BCMDRD devices are configured for a particular compile and is + * also numbered starting at one. If a device is not enabled by + * BCMDRD, then all of the associated bcmlrd_variant_t enum symbols + * associated with that device are not present. + * + * \param [in] device_variant DEVICE_VARIANT_T symbolic value. + * + * \retval bcmlrd_variant_t value + */ +bcmlrd_variant_t +bcmlrd_variant_from_device_variant_t(uint64_t device_variant); + +/*! + * \brief Return LTL DEVICE_VARIANT_T from the variant_t. + * + * Return a LTL DEVICE_VARIANT_T symbolic value from a + * bcmlrd_variant enum value. + * + * \param [in] variant bcmlrd_variant_t value. + * + * \retval DEVICE_VARIANT_T symbolic value. + * + */ +uint64_t +bcmlrd_device_variant_t_from_variant(bcmlrd_variant_t variant); + +/*! + * \brief Return a bcmlrd_variant_t enum value from a given variant string. + * + * Return a bcmlrd_variant_t enum value from a given variant string. + * + * \param [in] unit Unit number. + * \param [in] variant_string variant name. + * \param [out] variant variant value. + * + * \retval 0 OK + * \retval <0 ERROR + */ +int +bcmlrd_variant_from_variant_string(int unit, + const char* variant_string, + bcmlrd_variant_t* variant); + +/*! + * \brief Get base device variant. + * + * Get device logical table base variant, which is a set of initial + * mappings for a device. + * + * \param [in] unit Unit number. + * + * \retval Variant type. + */ +extern bcmlrd_variant_t +bcmlrd_base_get(int unit); + +/*! + * \brief Get variant string. + * + * Get the variant string for the given bcmlrd_variant_t. + * + * \param [in] variant Variant enumeration value. + * + * \return Pointer to variant name. + */ +extern const char * +bcmlrd_variant_string(bcmlrd_variant_t variant); + +/*! + * \brief Get variant name. + * + * Get the variant name for the given unit. If the unit does not + * exist, an empty string ("") is returned. + * + * \param [in] unit Unit number. + * + * \return Pointer to variant name. + */ +extern const char * +bcmlrd_variant_name(int unit); + +#endif /* BCMLRD_CONF_H */ diff --git a/src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_id_types.h b/src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_id_types.h new file mode 100644 index 0000000..855412c --- /dev/null +++ b/src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_id_types.h @@ -0,0 +1,57 @@ +/*! \file bcmlrd_id_types.h + * + * \brief Logical Table ID Types + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMLRD_ID_TYPES_H +#define BCMLRD_ID_TYPES_H + +#include + +/*! + * \brief Table identifier. + * + * Table identifier similar to those used by the DRD. + * + */ +typedef bcmltd_sid_t bcmlrd_sid_t; /* Generic table ID local to symbol. */ + +/*! + * \brief Field identifier. + * + * Field identifiers similar to those used by the DRD. + * + */ +typedef bcmltd_fid_t bcmlrd_fid_t; /* DRD compatible field ID local to logical. */ + +#endif /* BCMLRD_ID_TYPES_H */ diff --git a/src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_match_id_db.h b/src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_match_id_db.h new file mode 100644 index 0000000..ebecea0 --- /dev/null +++ b/src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_match_id_db.h @@ -0,0 +1,387 @@ +/*! \file bcmlrd_match_id_db.h + * + * \brief Match ID DB data structures and APIs. + * + * This file constains the collection of + * Match ID DB related data structures and APIs. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMLRD_MATCH_ID_DB_H +#define BCMLRD_MATCH_ID_DB_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif +#include + +/*! + * \brief Information on match ID fields. + * + * This structure is used to store information for each + * match id field. + * + */ +typedef struct bcmlrd_match_id_db_s { + /*! Match ID name. */ + const char *name; + + /*! Match. */ + uint32_t match; + + /*! Mask for match. */ + uint32_t match_mask; + + /*! Maxbit of the match id field in the physical container. */ + uint8_t match_maxbit; + + /*! Minbit of the match id field in the physical container. */ + uint8_t match_minbit; + + /*! Maxbit of the match id field. */ + uint8_t maxbit; + + /*! Minbit of the match id field. */ + uint8_t minbit; + + /*! Default value for the match id field. */ + uint32_t value; + + /*! Mask for the default value for the match id field. */ + uint32_t mask; + + /*! Maxbit of the field within match_id container. */ + uint8_t pmaxbit; + + /*! Minbit of the field within match_id container. */ + uint8_t pminbit; + + /*! ARC ID zone minbit. */ + uint8_t zone_minbit; + + /*! ARC ID mask. */ + uint64_t arc_id_mask; + + /*! Number of words used by zone bitmap. */ + uint8_t num_zone_bmp_words; + + /*! Zone bitmap. */ + uint32_t *zone_bmp; +} bcmlrd_match_id_db_t; + +/*! + * \brief Information on match ID fields. + * + * This structure is used to store information match id data. + * + */ +typedef struct bcmlrd_match_id_db_info_s { + /*! Number of entries in the match ID DB. */ + uint32_t num_entries; + + /*! Pointer to match ID DB. */ + const bcmlrd_match_id_db_t *db; +} bcmlrd_match_id_db_info_t; + +/*! + * \brief Function pointer to retrieve the match id information. + */ +typedef int (*bcmlrd_match_id_db_get_t)(int unit, const bcmlrd_sid_t sid, + const bcmlrd_fid_t fid, + const bcmlrd_match_id_db_t **info); + +/*! + * \brief Information on physical containers. + * + * This structure is used to store information for each + * physical container that a logical field is mapped to. + * + */ +typedef struct bcmlrd_cont_info_s { + /*! Section in which the container is available. */ + uint8_t section_id; + + /*! Offset of the container within the section. */ + uint16_t cont_id; + + /*! Width of the container in the section. */ + uint8_t width; + + /*! Bit offset of the container within the section. */ + uint16_t bit_offset; +} bcmlrd_cont_info_t; + +/*! + * \brief PDD information for physical containers. + * + * This structure is used to store PDD information for each + * physical container that a logical field is mapped to. + * + */ +typedef struct bcmlrd_pdd_info_s { + /*! + * Physical container id. This is the bit id of + * the physical container in the PDD bitmap. + */ + uint16_t phy_cont_id; + + /*! + * SBR Physical container id. This is the bit id of + * the physical container in the SBR bitmap. + */ + uint16_t sbr_phy_cont_id; + + /*! Physical container size. */ + uint16_t phy_cont_size; + + /*! Offset of action in the physical container. */ + uint8_t offset; + + /*! Width of action in the physical container from the offset */ + uint8_t width; + + /*! MFAP_INDEX to represend order of containers in contiguous */ + uint8_t mfap_index; + + /*! If set, then PDD is aligned from LSB. */ + bool is_lsb; + + /*! Absolute offset of container in the container list. */ + uint16_t bit_offset; +} bcmlrd_pdd_info_t; + +/*! + * \brief Container information per logical field. + * + * This structure is used to maintain the container information + * per logical field. + * + * Each logical field can be mapped to multiple containers. + * In which case, the information would be available as + * an array of this structure. + * Count specifies the array length. + * + */ +typedef struct bcmlrd_field_cont_info_s { + /*! Number of instances that physical container is mapped in the TILE. */ + uint8_t instances; + + /*! Number of containers that logical field is mapped to. */ + uint8_t count; + + /*! Physical container information. */ + const bcmlrd_cont_info_t *info; +} bcmlrd_field_cont_info_t; + +/*! + * \brief SBR type. + */ +typedef enum bcmlrd_field_sbr_type_e { + /*! Non SBR eligible action. */ + BCMLRD_SBR_NONE, + + /*! Non SBR eligible action, mapped to SBR container. */ + BCMLRD_SBR_INTERNAL, + + /*! SBR eligible action, mapped to SBR container. */ + BCMLRD_SBR_EXTERNAL +} bcmlrd_field_sbr_type_t; + +/*! + * \brief PDD information on containers per logical field. + * + * This structure is used to maintain the PDD information for containers + * per logical field. + * + * Each logical field can be mapped to multiple containers. + * In which case, the information would be available as + * an array of this structure. + * Count specifies the array length. + * + */ +typedef struct bcmlrd_field_pdd_info_s { + /*! SBR type of the field. */ + bcmlrd_field_sbr_type_t sbr_type; + + /*! Number of containers that logical field is mapped to. */ + uint8_t count; + + /*! PDD information for each physical container. */ + const bcmlrd_pdd_info_t *info; +} bcmlrd_field_pdd_info_t; + +/*! + * \brief Container map information for logical field. + * + * This structure provides container and PDD information for + * each physical container that the logical field is mapped to. + * + */ +typedef struct bcmlrd_field_info_s { + /*! Name of the physical field. */ + const char *name; + + /*! Field ID. */ + bcmltd_fid_t id; + + /*! Container information for the logical field. */ + const bcmlrd_field_cont_info_t *cont_info; + + /*! PDD container information for the logical field. */ + const bcmlrd_field_pdd_info_t *pdd_info; + +} bcmlrd_field_info_t; + +/*! + * \brief Table tile information for the special tables. + * + * This structure provides physical container information for each + * logical field in the tile mapped to the table. + * + */ + +typedef struct bcmlrd_tile_pcm_info_s { + /*! Mux information for this logical table. */ + uint32_t tile_id; + + /*! Number of fields in the table. */ + uint16_t field_count; + + /*! Field information for each field. */ + const bcmlrd_field_info_t *field_info; + +} bcmlrd_tile_pcm_info_t; + +/*! + * \brief Table information for the special tables. + * + * This structure provides physical container information for each + * logical field. + * + */ +typedef struct bcmlrd_table_pcm_info_s { + /*! Logical Table source ID. */ + uint32_t src_id; + + /*! Number of tiles in the table. */ + uint8_t tile_count; + + /*! Tile PCM information for each field. */ + const bcmlrd_tile_pcm_info_t *tile_info; + +} bcmlrd_table_pcm_info_t; + +/*! + * \brief Table PCM configuration storage compact representation. + */ +typedef struct bcmlrd_pcm_conf_compact_rep_s { + /*! PCM configuration name. */ + const char *name; + + /*! Number of tables that support PCM in the device. */ + uint32_t num_pcm; + + /*! Pointer to the array of PCM configurations. */ + const bcmlrd_table_pcm_info_t **pcm; + +} bcmlrd_pcm_conf_compact_rep_t; + +/*! + * \brief Table PCM configuration storage representation. + */ +typedef bcmlrd_pcm_conf_compact_rep_t bcmlrd_pcm_conf_rep_t; + +/*! + * \brief Return the PCM configuration for the given table. + * + * This routine returns the PCM configuration + * for the given unit, sid. + * + * \param [in] unit Unit number. + * \param [in] sid Logical Table symbol ID. + * \param [out] pcm_info PCM configuration. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNAVAIL Unit/Table/PCM configuration not found. + * + */ +extern int +bcmlrd_table_pcm_conf_get(int unit, + bcmlrd_sid_t sid, + const bcmlrd_table_pcm_info_t **pcm_info); + +/*! + * \brief Return the match id information. + * + * This routine returns the match id information + * for the given unit, table and field. + * + * \param [in] unit Unit number. + * \param [in] sid Logical Table symbol ID. + * \param [in] fid Logical field symbol ID. + * \param [out] info Match ID data. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_PARAM Invalid unit, sid, fid or info. + * \retval SHR_E_UNAVAIL Match ID data is not found. + * + */ +extern int +bcmlrd_table_match_id_db_get(int unit, + const bcmlrd_sid_t sid, + const bcmlrd_fid_t fid, + const bcmlrd_match_id_db_t **info); + +/*! + * \brief Return the match id information. + * + * This routine returns the match id information + * for the given match id in string format. + * + * \param [in] unit Unit number. + * \param [in] spec Match ID name. + * \param [out] info Match ID data. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_PARAM Invalid unit, sid, fid or info. + * \retval SHR_E_NOT_FOUND Match ID data is not found. + * + */ +extern int +bcmlrd_table_match_id_data_get(int unit, + const char *spec, + const bcmlrd_match_id_db_t **info); + + +#endif /* BCMLRD_MATCH_ID_DB_H */ diff --git a/src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_variant.h b/src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_variant.h new file mode 100644 index 0000000..38c84a4 --- /dev/null +++ b/src/bcm/common/pktio/bcmlrd/include/bcmlrd/bcmlrd_variant.h @@ -0,0 +1,53 @@ +/*! \file bcmlrd_variant.h + * + * \brief BCMLRD Variant interfaces and definitions + * + * BCMLRD_VARIANT_ENTRY macros. + * + * If a list of variant entries is needed, before including this file, + * define BCMLRD_VARIANT_ENTRY as a macro. See bcmltd/include/bcmltd_variant.h + * for the parameters for BCMLRD_VARIANT_ENTRY, which are exactly the same as + * those for BCMLTD_VARIANT_ENTRY. + * + * Note that BCMLTD_VARIANT_ENTRY will be undefined at the end of this file. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMLRD_VARIANT_H +#define BCMLRD_VARIANT_H + +/* The contents between the include guard is deliberately empty. */ + +#endif /* BCMLRD_VARIANT_H */ + +/* This include must be placed outside the include guard. */ +#include diff --git a/src/bcm/common/pktio/bcmlrd/include/bcmlrd/chip/bcmlrd_chip_variant.h b/src/bcm/common/pktio/bcmlrd/include/bcmlrd/chip/bcmlrd_chip_variant.h new file mode 100644 index 0000000..5a2501b --- /dev/null +++ b/src/bcm/common/pktio/bcmlrd/include/bcmlrd/chip/bcmlrd_chip_variant.h @@ -0,0 +1,60 @@ +/*! \file bcmlrd_chip_variant.h + * + * \brief BCMLRD variant definitions + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMLRD_CHIP_VARIANT_H +#define BCMLRD_CHIP_VARIANT_H + +#include + +#endif /* BCMLRD_CHIP_VARIANT_H */ + +#ifndef DOXYGEN_IGNORE_AUTOGEN + +#ifdef BCMLTD_VARIANT_OVERRIDE +#error "Use BCMLRD_VARIANT_OVERRIDE instead." +#endif +#ifdef BCMLRD_VARIANT_OVERRIDE +#define BCMLTD_VARIANT_OVERRIDE +#endif +#ifdef BCMLRD_VARIANT_ENTRY +#define BCMLTD_VARIANT_ENTRY(...) BCMLRD_VARIANT_ENTRY(__VA_ARGS__) +#include +#ifdef BCMLRD_VARIANT_OVERRIDE +#undef BCMLRD_VARIANT_OVERRIDE +#endif +#undef BCMLRD_VARIANT_ENTRY +#endif /* BCMLRD_VARIANT_ENTRY */ + +#endif /* DOXYGEN_IGNORE_AUTOGEN */ diff --git a/src/bcm/common/pktio/bcmlrd/include/bcmlrd/chip/bcmlrd_variant_defs.h b/src/bcm/common/pktio/bcmlrd/include/bcmlrd/chip/bcmlrd_variant_defs.h new file mode 100644 index 0000000..1cca942 --- /dev/null +++ b/src/bcm/common/pktio/bcmlrd/include/bcmlrd/chip/bcmlrd_variant_defs.h @@ -0,0 +1,53 @@ +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated by fltg from Logical Table mapping files. + * Edits to this file will be lost when it is regenerated. + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + ******************************************************************************/ + +#ifndef BCMLRD_CHIP_VARIANT_DEFS_H +#define BCMLRD_CHIP_VARIANT_DEFS_H + +#ifndef DOXYGEN_IGNORE_AUTOGEN + +#include + +#define BCMLRD_VARIANT_BCM88860_A0_BASE BCMLTD_VARIANT_BCM88860_A0_BASE +#define BCMLRD_VARIANT_BCM99450_A0_BASE BCMLTD_VARIANT_BCM99450_A0_BASE +#define BCMLRD_VARIANT_BCM88690_A0_BASE BCMLTD_VARIANT_BCM88690_A0_BASE +#define BCMLRD_VARIANT_BCM88920_A0_BASE BCMLTD_VARIANT_BCM88920_A0_BASE +#define BCMLRD_VARIANT_BCM99470_A0_BASE BCMLTD_VARIANT_BCM99470_A0_BASE +#define BCMLRD_VARIANT_MAX BCMLTD_VARIANT_MAX + +#endif /* DOXYGEN_IGNORE_AUTOGEN */ + +#endif /* BCMLRD_CHIP_VARIANT_DEFS_H */ diff --git a/src/bcm/common/pktio/bcmltd/include/bcmltd/bcmltd_id_types.h b/src/bcm/common/pktio/bcmltd/include/bcmltd/bcmltd_id_types.h new file mode 100644 index 0000000..6e667ac --- /dev/null +++ b/src/bcm/common/pktio/bcmltd/include/bcmltd/bcmltd_id_types.h @@ -0,0 +1,72 @@ +/*! \file bcmltd_id_types.h + * + * Logical Table Data ID Types header file + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMLTD_ID_TYPES_H +#define BCMLTD_ID_TYPES_H + +/*! + * \brief Logical table ID type. + */ +typedef uint32_t bcmltd_sid_t; + +/*! + * \brief Logical field ID type. + */ +typedef uint32_t bcmltd_fid_t; + +/*! + * \brief Global logical field ID type. + */ +typedef bcmltd_fid_t bcmltd_gfid_t; + +/*! + * \brief Invalid logical table ID. + */ +#define BCMLTD_SID_INVALID ((bcmltd_sid_t)-1) + +/*! + * \brief Invalid logical table ID + * + * To store invalid LTID in HA for ISSU upgrade, + * this invalid LTID has to be used. + */ +#define BCMLTD_INVALID_LT BCMLTD_SID_INVALID + +/*! + * \brief Invalid logical field ID. + */ +#define BCMLTD_FID_INVALID ((bcmltd_fid_t)-1) + +#endif /* BCMLTD_ID_TYPES_H */ diff --git a/src/bcm/common/pktio/bcmltd/include/bcmltd/bcmltd_variant.h b/src/bcm/common/pktio/bcmltd/include/bcmltd/bcmltd_variant.h new file mode 100644 index 0000000..2ce0ec0 --- /dev/null +++ b/src/bcm/common/pktio/bcmltd/include/bcmltd/bcmltd_variant.h @@ -0,0 +1,77 @@ +/*! \file bcmltd_variant.h + * + * \brief BCMLTD Variant interfaces and definitions + * + * Logical table variant inclusion and exclusion support within the + * BCMLTD can be specified as a combination of the following defines: + * + * #define BCMLTD_CONFIG_INCLUDE__X_ [1|0] + * -- Include or exclude the specified variant + * Example: #define BCMLTD_CONFIG_INCLUDE_BCM56880_A0_DNA_6_5_30_1_1 1 + * + * The value of BCMLTD_CONFIG_INCLUDE_VARIANT_DEFAULT is used for any + * variants which are left unspecified. Set this value to 1 or 0 to + * include or exclude all variants by default. + * + * BCMLTD_VARIANT_ENTRY macros. + * + * If a list of variant entries is needed, before including this file, + * define BCMLTD_VARIANT_ENTRY as a macro to operate on the following + * parameters: + * + * #define BCMLTD_VARIANT_ENTRY(_bd,_bu,_va,_ve,_vu,_vv,_vo,_vd,_r0,_r1) + * + * _bd: SW Base Driver (lower case) + * _bu: SW Base Driver (upper case) + * _va: Variant name (lower case or empty for BASE) + * _ve: Variant enum symbol (upper case) + * _vu: Variant name (underscore or empty for BASE) + * _vv: Variant numeric value + * _vo: Device relative offset + * _vd: Variant Description + * _r0: Reserved + * _r1: Reserved + * + * Note that BCMLTD_VARIANT_ENTRY will be undefined at the end of this file. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMLTD_VARIANT_H +#define BCMLTD_VARIANT_H + +#include + +#endif /* BCMLTD_VARIANT_H */ + +/* This include must be placed outside the include guard. */ +#include + diff --git a/src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_chip_variant.h b/src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_chip_variant.h new file mode 100644 index 0000000..f38d16f --- /dev/null +++ b/src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_chip_variant.h @@ -0,0 +1,54 @@ +/*! \file bcmltd_chip_variant.h + * + * \brief BCMLTD variant definitions + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMLTD_CHIP_VARIANT_H +#define BCMLTD_CHIP_VARIANT_H + +#include + +#endif /* BCMLTD_CHIP_VARIANT_H */ + +#ifndef DOXYGEN_IGNORE_AUTOGEN + +#ifdef BCMLTD_VARIANT_ENTRY +#include +#ifdef BCMLTD_VARIANT_OVERRIDE +#undef BCMLTD_VARIANT_OVERRIDE +#endif +#undef BCMLTD_VARIANT_ENTRY + +#endif /* BCMLTD_VARIANT_ENTRY */ + +#endif /* DOXYGEN_IGNORE_AUTOGEN */ diff --git a/src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_config_variant.h b/src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_config_variant.h new file mode 100644 index 0000000..ee69411 --- /dev/null +++ b/src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_config_variant.h @@ -0,0 +1,91 @@ +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated by fltg from Logical Table mapping files. + * Edits to this file will be lost when it is regenerated. + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + ******************************************************************************/ + +#ifndef BCMLTD_CHIP_CONFIG_VARIANT_H +#define BCMLTD_CHIP_CONFIG_VARIANT_H + +#ifndef DOXYGEN_IGNORE_AUTOGEN + +#include + +/* This determines whether a variant is included or excluded by default */ +#ifndef BCMLTD_CONFIG_INCLUDE_VARIANT_DEFAULT +#define BCMLTD_CONFIG_INCLUDE_VARIANT_DEFAULT 1 +#endif + +#if BCMDRD_CONFIG_INCLUDE_BCM88860_A0 +#ifndef BCMLTD_CONFIG_INCLUDE_BCM88860_A0_BASE +#define BCMLTD_CONFIG_INCLUDE_BCM88860_A0_BASE BCMLTD_CONFIG_INCLUDE_VARIANT_DEFAULT +#endif +#else +#define BCMLTD_CONFIG_INCLUDE_BCM88860_A0_BASE 0 +#endif + +#if BCMDRD_CONFIG_INCLUDE_BCM99450_A0 +#ifndef BCMLTD_CONFIG_INCLUDE_BCM99450_A0_BASE +#define BCMLTD_CONFIG_INCLUDE_BCM99450_A0_BASE BCMLTD_CONFIG_INCLUDE_VARIANT_DEFAULT +#endif +#else +#define BCMLTD_CONFIG_INCLUDE_BCM99450_A0_BASE 0 +#endif + +#if BCMDRD_CONFIG_INCLUDE_BCM88690_A0 +#ifndef BCMLTD_CONFIG_INCLUDE_BCM88690_A0_BASE +#define BCMLTD_CONFIG_INCLUDE_BCM88690_A0_BASE BCMLTD_CONFIG_INCLUDE_VARIANT_DEFAULT +#endif +#else +#define BCMLTD_CONFIG_INCLUDE_BCM88690_A0_BASE 0 +#endif + +#if BCMDRD_CONFIG_INCLUDE_BCM88920_A0 +#ifndef BCMLTD_CONFIG_INCLUDE_BCM88920_A0_BASE +#define BCMLTD_CONFIG_INCLUDE_BCM88920_A0_BASE BCMLTD_CONFIG_INCLUDE_VARIANT_DEFAULT +#endif +#else +#define BCMLTD_CONFIG_INCLUDE_BCM88920_A0_BASE 0 +#endif + +#if BCMDRD_CONFIG_INCLUDE_BCM99470_A0 +#ifndef BCMLTD_CONFIG_INCLUDE_BCM99470_A0_BASE +#define BCMLTD_CONFIG_INCLUDE_BCM99470_A0_BASE BCMLTD_CONFIG_INCLUDE_VARIANT_DEFAULT +#endif +#else +#define BCMLTD_CONFIG_INCLUDE_BCM99470_A0_BASE 0 +#endif + +#endif /* DOXYGEN_IGNORE_AUTOGEN */ + +#endif /* BCMLTD_CHIP_CONFIG_VARIANT_H */ diff --git a/src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_variant_defs.h b/src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_variant_defs.h new file mode 100644 index 0000000..60319a6 --- /dev/null +++ b/src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_variant_defs.h @@ -0,0 +1,48 @@ +/*! \file bcmltd_variant_defs.h + * + * \brief BCMLTD variant definitions + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMLTD_VARIANT_DEFS_H +#define BCMLTD_VARIANT_DEFS_H +#ifndef DOXYGEN_IGNORE_AUTOGEN + +#define BCMLTD_VARIANT_BCM88860_A0_BASE 1 +#define BCMLTD_VARIANT_BCM99450_A0_BASE 1 +#define BCMLTD_VARIANT_BCM88690_A0_BASE 1 +#define BCMLTD_VARIANT_BCM88920_A0_BASE 1 +#define BCMLTD_VARIANT_BCM99470_A0_BASE 1 +#define BCMLTD_VARIANT_MAX 1 + +#endif /* DOXYGEN_IGNORE_AUTOGEN */ +#endif /* BCMLTD_VARIANT_DEFS_H */ diff --git a/src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_variant_entry.h b/src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_variant_entry.h new file mode 100644 index 0000000..3238348 --- /dev/null +++ b/src/bcm/common/pktio/bcmltd/include/bcmltd/chip/bcmltd_variant_entry.h @@ -0,0 +1,63 @@ +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated by fltg from Logical Table definition files. + * + * Tool: $SDK/tools/fltg/bin/fltg + * + * Edits to this file will be lost when it is regenerated. + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + ******************************************************************************/ +#ifndef GEN_BCMLTD_VARIANT_ENTRY_H +#define GEN_BCMLTD_VARIANT_ENTRY_H +/* guard deliberately empty */ +#endif /* GEN_BCMLTD_VARIANT_ENTRY_H */ +#ifndef DOXYGEN_IGNORE_AUTOGEN +/*+replace variant */ + +#if BCMLTD_CONFIG_INCLUDE_BCM88860_A0_BASE == 1 || defined(BCMLTD_VARIANT_OVERRIDE) + BCMLTD_VARIANT_ENTRY(bcm88860_a0, BCM88860_A0,, BASE,, 1, 0, NULL, 0, 0) +#endif +#if BCMLTD_CONFIG_INCLUDE_BCM99450_A0_BASE == 1 || defined(BCMLTD_VARIANT_OVERRIDE) + BCMLTD_VARIANT_ENTRY(bcm99450_a0, BCM99450_A0,, BASE,, 1, 0, NULL, 0, 0) +#endif +#if BCMLTD_CONFIG_INCLUDE_BCM88690_A0_BASE == 1 || defined(BCMLTD_VARIANT_OVERRIDE) + BCMLTD_VARIANT_ENTRY(bcm88690_a0, BCM88690_A0,, BASE,, 1, 0, NULL, 0, 0) +#endif +#if BCMLTD_CONFIG_INCLUDE_BCM88920_A0_BASE == 1 || defined(BCMLTD_VARIANT_OVERRIDE) + BCMLTD_VARIANT_ENTRY(bcm88920_a0, BCM88920_A0,, BASE,, 1, 0, NULL, 0, 0) +#endif +#if BCMLTD_CONFIG_INCLUDE_BCM99470_A0_BASE == 1 || defined(BCMLTD_VARIANT_OVERRIDE) + BCMLTD_VARIANT_ENTRY(bcm99470_a0, BCM99470_A0,, BASE,, 1, 0, NULL, 0, 0) +#endif + +/*-replace*/ +#endif /* DOXYGEN_IGNORE_AUTOGEN */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_buf.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_buf.h new file mode 100644 index 0000000..43afe7a --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_buf.h @@ -0,0 +1,568 @@ +/*! \file bcmpkt_buf.h + * + * Interfaces for packet buffer management. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_BUF_H +#define BCMPKT_BUF_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif +#include + +/*! Default packet pool size (number of packets). */ +#define BCMPKT_PPOOL_COUNT_DEF 128 + +/*! Default buffer pool size (number of buffers). */ +#define BCMPKT_BPOOL_BCOUNT_DEF 256 + +/*! Minimum buffer size of the buffer pool to be created. */ +#define BCMPKT_BPOOL_BSIZE_MIN (1536) + +/*! Minimum packet size. (not include CRC) */ +#define BCMPKT_FRAME_SIZE_MIN (14) + +/*! Buffer operation overhead. */ +#define BCMPKT_BUF_SIZE_OVERHEAD (BCMPKT_RCPU_MAX_ENCAP_SIZE + \ + sizeof(bcmpkt_data_buf_t)) + +/** + * \name BCMPKT buffer allocation flags. + * \anchor BCMPKT_BUF_F_XXX + */ +/*! \{ */ +/*! Reserve space for TX overhead. + * This flag is used to reserve a space which size is BCMPKT_TX_HDR_RSV + * in the front of data buffer for internal transmit overhead. + */ +#define BCMPKT_BUF_F_TX (0x1 << 0) +/*! \} */ + +/*! Packet data buffer pool structure. + * + * Packet data buffer pool hosts buffers for bcmpkt_packet_t.data_buf + * usage. Every buffer has same size (\c buf_size) which includes operation + * overhead (\c BCMPKT_BUF_SIZE_OVERHEAD). + * + * Per device DMA-capable buffer is used for UNET mode to get performance from + * zero-copy. + * + * The pool is available only when \c active is true and \c free_count + * is not 0. + */ +typedef struct bcmpkt_bpool_status_s { + /*! Active status. */ + bool active; + /*! Buffer size. */ + uint32_t buf_size; + /*! Total buffer count. */ + uint32_t buf_count; + /*! Available buffer count. */ + uint32_t free_count; +} bcmpkt_bpool_status_t; + +/*! Packet operation header pool. + * + * The pool is available only when \c active is true. + * If \c free_count is 0, a new allocation of bcmpkt_packet_t will + * be done from sal_alloc, and the new buffer will be added into + * the packet pool. + */ +typedef struct bcmpkt_ppool_status_s { + /*! Active status. */ + bool active; + /*! Total packet count. */ + uint32_t pkt_count; + /*! Available packet count. */ + uint32_t free_count; +} bcmpkt_ppool_status_t; + +/*! + * \brief Allocate a packet object. + * + * Create packet operation header and allocate data buffer. + * If \c BCMPKT_BUF_F_TX is set, TX internal operation header space will be + * created in the front of data_buf. + * + * \param [in] unit Switch unit number. + * \param [in] len The size packet data buffer to be allocated (unit is byte). + * \param [in] flags Reserved. + * \param [out] packet Packet handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Input len is too small. + * \retval SHR_E_MEMORY Allocate failed. + */ +extern int +bcmpkt_alloc(int unit, uint32_t len, uint32_t flags, bcmpkt_packet_t **packet); + +/*! + * \brief Release packet object. + * + * Release packet data buffer into bpool, and release packet operation header + * buffer into ppool. + * + * \param [in] unit Switch unit number. + * \param [in] packet Packet handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Parameter is NULL. + */ +extern int +bcmpkt_free(int unit, bcmpkt_packet_t *packet); + +/*! + * \brief Reserve buffer size in headroom. + * + * Reserve space in the buffer headroom for potential header encapsulation. + * The reservation should be done prior to adding packet data (when packet len + * is 0). + * + * \param [in,out] dbuf Packet data buffer handle. + * \param [in] len Number of bytes to reserve. + * + * \return A pointer to the updated packet->data_buf->data. + */ +extern uint8_t * +bcmpkt_reserve(bcmpkt_data_buf_t *dbuf, uint32_t len); + +/*! + * \brief Add bytes in the front of packet data. + * + * This function extends the used data area in the beginning when the headroom + * has enough space for the request. + * + * \param [in,out] dbuf Packet data buffer handle. + * \param [in] len Bytes to add. + * + * \return A pointer to the first byte of the extra data. NULL for failure. + */ +extern uint8_t * +bcmpkt_push(bcmpkt_data_buf_t *dbuf, uint32_t len); + +/*! + * \brief Add bytes at the end of packet data. + * + * This function extends the used data area of the buffer at the buffer end when + * the tailroom has enough space for the request. + * + * \param [in,out] dbuf Packet data buffer handle. + * \param [in] len Number of bytes to add. + * + * \return A pointer to the first byte of the extra data. NULL for failure. + */ +extern uint8_t * +bcmpkt_put(bcmpkt_data_buf_t *dbuf, uint32_t len); + +/*! + * \brief Remove bytes from the start of packet data. + * + * This function removes some bytes from the start of a packet data, and returns + * the memory to the headroom. A pointer to the next data in the packet data + * buffer is returned. Once the data has been pulled, future pushes will + * overwrite the old data. + * + * \param [in,out] dbuf Packet data buffer handle. + * \param [in] len Bytes to be removed. + * + * \return A pointer to the next data in the buffer. + */ +extern uint8_t * +bcmpkt_pull(bcmpkt_data_buf_t *dbuf, uint32_t len); + +/*! + * \brief Remove end from packet buffer. + * + * Cut the length of a buffer down by removing data from the tail. If + * the buffer is already under the length specified, will return with no action. + * + * \param [in,out] dbuf Packet data buffer handle. + * \param [in] len New data length. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM Input len is too small. + */ +extern int +bcmpkt_trim(bcmpkt_data_buf_t *dbuf, uint32_t len); + +/*! + * \brief Get headroom size. + * + * Get free space size before packet data in the packet buffer. + * + * \param [in] dbuf Packet data buffer handle. + * + * \return Available bytes for push. + */ +extern uint32_t +bcmpkt_headroom(bcmpkt_data_buf_t *dbuf); + +/*! + * \brief Get tailroom size. + * + * Get free space after packet data in the packet buffer. + * + * \param [in] dbuf Packet data buffer handle. + * + * \return Available bytes for put. + */ +extern uint32_t +bcmpkt_tailroom(bcmpkt_data_buf_t *dbuf); + +/*! + * \brief Create a buffer pool. + * + * The \c buf_size must be large enough to hold the components show below, + * where (m) denotes mandatory components (part of all packets) and (o) + * denotes optional components. + * + * (m) Maximum size ethernet packet + * (m) Buffer control (bcmpkt_data_buf_t) + * (o) RCPU header + * (o) Tx meta data (Tx PMD) + * (o) Loopback header + * (o) HiGig header + * + * + * \param [in] unit Switch unit number. + * \param [in] buf_size Number of bytes for each buffer. + * \param [in] buf_count Number of buffers. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Input parameter(s) is(are) invalid. + * \retval SHR_E_MEMORY Allocate failed. + */ +extern int +bcmpkt_bpool_create(int unit, int buf_size, int buf_count); + +/*! + * \brief Destroy a buffer pool. + * + * \param [in] unit Switch unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmpkt_bpool_destroy(int unit); + +/*! + * \brief Destroy all buffer pools. + * + * \retval SHR_E_NONE No errors. + */ +extern int +bcmpkt_bpool_cleanup(void); + +/*! + * \brief Fetch a buffer pool status. + * + * \param [in] unit Switch unit number. + * \param [out] status Buffer pool status handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM The \c status is a NULL pointer. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmpkt_bpool_status_get(int unit, bcmpkt_bpool_status_t *status); + +/*! + * \brief Dump buffer pool information. + * + * Dump a buffer pool's configuration and status. + * + * \param [in] unit Switch unit number. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM The \c pb is a NULL pointer. + */ +extern int +bcmpkt_bpool_info_dump(int unit, shr_pb_t *pb); + +/*! + * \brief Allocate a packet data buffer. + * + * \param [in] unit Switch unit number. + * \param [in] size Number of bytes for each buffer. + * \param [in] dbuf Data buffer handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Input parameter(s) is(are) invalid. + * \retval SHR_E_MEMORY Out of memory. + */ +extern int +bcmpkt_data_buf_alloc(int unit, uint32_t size, bcmpkt_data_buf_t **dbuf); + +/*! + * \brief Release a packet data buffer. + * + * \param [in] unit Switch unit number. + * \param [in] dbuf Data buffer handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Input parameter(s) is(are) invalid. + * \retval SHR_E_MEMORY The dbuf does not belong to the unit's buffer pool. + * \retval SHR_E_FAIL Could not get lock. + */ +extern int +bcmpkt_data_buf_free(int unit, bcmpkt_data_buf_t *dbuf); + +/*! + * \brief Clone a packet. + * + * Create a new packet, copy meta data content and refer to the same data_buf. + * + * \param [in] unit Switch number. + * \param [in] pkt Packet handle. + * \param [out] new_pkt New packet handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Input parameter(s) is(are) invalid. + * \retval SHR_E_MEMORY Allocate failed. + */ +extern int +bcmpkt_packet_clone(int unit, bcmpkt_packet_t *pkt, bcmpkt_packet_t **new_pkt); + +/*! + * \brief Claim the packet. + * + * Create a new packet. Copy metadata. Try to take over\c pkt->data_buf. If + * can't take over it because of different unit, will create a new data_buf + * and copy content. + * + * \param [in] unit Switch number, from which buffer pool allocate new buffer. + * \param [in] pkt Packet handle. + * \param [out] new_pkt New packet handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Input parameter(s) is(are) invalid. + * \retval SHR_E_MEMORY Allocate failed. + */ +extern int +bcmpkt_packet_claim(int unit, bcmpkt_packet_t *pkt, bcmpkt_packet_t **new_pkt); + +/*! + * \brief Create a new similar data buffer with same content. + * + * Allocate a new data buffer, and copy \c dbuf content to it. + * + * \param [in] unit Switch number, from which buffer pool allocate new buffer. + * \param [in] dbuf Packet data buffer for copy. + * \param [out] new_dbuf New packet data buffer. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Input parameter(s) is(are) invalid. + * \retval SHR_E_MEMORY Allocate failed. + */ +extern int +bcmpkt_data_buf_copy(int unit, bcmpkt_data_buf_t *dbuf, + bcmpkt_data_buf_t **new_dbuf); + +/*! + * \brief Create packet pool. + * + * This API is for creating a bcmpkt_packet_t object pool for allocation with + * low allocation overhead. + + * If the packet pool is not active, bcmpkt_alloc() will allocate + * bcmpkt_packet_t object from sal_alloc(), and bcmpkt_free() will release + * the buffer through sal_free(). + * + * If packet pool is active, bcmpkt_alloc() will allocate bcmpkt_packet_t + * object from the packet pool. When there is not available packet buffer, + * a new buffer will be allocated from sal_alloc() internally. And, + * bcmpkt_free() is to return every packet buffer into packet pool, when + * packet pool free count is under \c pkt_count. If free count reached + * \c pkt_count, the buffer will be released by sal_free(). + * + * \param [in] pkt_count Number of buffers. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Invalid packet count. + * \retval SHR_E_MEMORY Allocate failed. + */ +extern int +bcmpkt_ppool_create(int pkt_count); + +/*! + * \brief Destroy packet pool. + * + * \retval SHR_E_NONE No errors. + */ +extern int +bcmpkt_ppool_destroy(void); + +/*! + * \brief Dump packet pool information. + * + * \retval SHR_E_NONE No errors. + */ + +/*! + * \brief Fetch the packet pool status. + * + * \param [out] status Packet pool status handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM The \c status is a NULL pointer. + */ +extern int +bcmpkt_ppool_status_get(bcmpkt_ppool_status_t *status); + +/*! + * \brief Dump packet pool information. + * + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM The \c pb is a NULL pointer. + */ +extern int +bcmpkt_ppool_info_dump(shr_pb_t *pb); + +/*! + * \brief Format packet metadata structure. + * + * Link packet metadata pointers to their data without touching the data content. + * + * \param [in] packet Packet handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM Invalid packet handle. + */ +extern int +bcmpkt_pmd_format(bcmpkt_packet_t *packet); + +/*! + * \brief Get Higig handle from a packet handle. + * + * This function is for getting HiGig handle from a packet handle. + * + * \param [in] packet Packet handle. + * \param [out] hg_hdr HiGig header handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM Invalid packet handle or invalid HiGig header handle. + */ +extern int +bcmpkt_higig_get(bcmpkt_packet_t *packet, uint32_t **hg_hdr); + +/*! + * \brief Get RXPMD handle from a packet handle. + * + * This function is for getting RXPMD handle from a packet handle. + * + * \param [in] packet Packet handle. + * \param [out] rxpmd RX Packet MetaData handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM Invalid packet handle or invalid RXPMD handle. + */ +extern int +bcmpkt_rxpmd_get(bcmpkt_packet_t *packet, uint32_t **rxpmd); + +/*! + * \brief Get TXPMD handle from a packet handle. + * + * This function is for getting TXPMD handle from a packet handle. + * + * \param [in] packet Packet handle. + * \param [out] txpmd TXPMD handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM Invalid packet handle or invalid TXPMD handle. + */ +extern int +bcmpkt_txpmd_get(bcmpkt_packet_t *packet, uint32_t **txpmd); + +/*! + * \brief Get loopback header handle from a packet handle. + * + * This function is for getting loopback header handle from a packet handle. + * + * \param [in] packet Packet handle. + * \param [out] lbhdr Loopback header handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM nvalid packet handle or invalid loopback header handle. + */ +extern int +bcmpkt_lbhdr_get(bcmpkt_packet_t *packet, uint32_t **lbhdr); + +/*! + * \brief Set minimum packet size (not includng CRC). + * + * This function is used for setting allowable minimum packet size for packet + * transmission (not includng CRC). + * + * The valid range for the minimum packet size is from [1 to 60]. The default + * value is \ref BCMPKT_FRAME_SIZE_MIN. + * + * Note: + * This is a debug function and should keep default value for normal case. + * + * \param [in] size The minimum packet size to use (unit is bytes). + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM Requested minimum packet size is out of valid range. + */ +extern int +bcmpkt_framesize_min_set(uint32_t size); + +/*! + * \brief Get current minimum packet size (not includng CRC). + * + * This function is used for getting the current minimum packet size for packet + * transmission. Default is \ref BCMPKT_FRAME_SIZE_MIN. + * + * \retval Current minimum packet size. + */ +extern uint32_t +bcmpkt_framesize_min_get(void); + +#endif /* BCMPKT_BUF_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_dev.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_dev.h new file mode 100644 index 0000000..bf6d1aa --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_dev.h @@ -0,0 +1,1063 @@ +/*! \file bcmpkt_dev.h + * + * Interfaces for packet device configuration access. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_DEV_H +#define BCMPKT_DEV_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#include +#include +#endif +#include +#include +#include + +/*! Maximum chars are allowed in packet device name. */ +#define BCMPKT_DEV_NAME_MAX 16 + +/*! + * Device driver types. + * BCMPKT_DEV_DRV_T_AUTO type is for attach function ONLY. When it's input type, + * Packet I/O module will select an appropriate packet device driver by taking + * KNET as priority. + */ +typedef enum bcmpkt_dev_drv_types_e { + BCMPKT_DEV_DRV_T_NONE, /*! No device driver. */ + BCMPKT_DEV_DRV_T_AUTO, /*! Automatically select driver. */ + BCMPKT_DEV_DRV_T_UNET, /*! User land DMA driver. */ + BCMPKT_DEV_DRV_T_KNET, /*! KNET Packet_mmap driver. */ + BCMPKT_DEV_DRV_T_COUNT /*! Must be end. */ +} bcmpkt_dev_drv_types_t; + +/*! + * Device family types. + */ +typedef enum bcmpkt_dev_info_family_types_e { + BCMPKT_DEV_INFO_FAMILY_T_NONE, /*! Type not specified. */ + BCMPKT_DEV_INFO_FAMILY_T_XFS, /*! XFS type header. */ + BCMPKT_DEV_INFO_FAMILY_T_XGS, /*! XGS type header. */ + BCMPKT_DEV_INFO_FAMILY_T_XFS_XGS, /*! XFS+XGS type header. */ + BCMPKT_DEV_INFO_FAMILY_T_DNX, /*! DNX type header. */ + BCMPKT_DEV_INFO_FAMILY_T_DNXF, /*! DNX type header. */ + BCMPKT_DEV_INFO_FAMILY_T_COUNT /*! Must be end. */ +} bcmpkt_dev_info_family_types_t; + +/*! + * \name DMA channel direction flags. + * \anchor BCMPKT_DMA_CH_DIR_XXX + */ +/*! \{ */ +/*! For "direction", DMA channel is RX */ +#define BCMPKT_DMA_CH_DIR_RX 0 +/*! For "direction", DMA channel is TX */ +#define BCMPKT_DMA_CH_DIR_TX 1 +/*! \} */ + +/*! \brief DMA channel configuration structure. + * + * This structure defines DMA channel configuration parameters. + * + * DMA channel may work for transmitting or for receiving. The user configures + * "dir" to set the channel for transmitting or for receiving. + * + * "ring_size" is the maximum number of packet descriptors supported by the + * ring. Each descriptor is for one packet transmitting or receiving. So, it + * may be taken as maximum packet number. 0 means the channel was not + * initialized. + * + * "max_frame_size" means the maximum size packets are allowed to pass through + * the DMA channel. + */ +typedef struct bcmpkt_dma_chan_s { + /*! DMA channel index. */ + int id; + + /*! Channel direction, refer to \ref BCMPKT_DMA_CH_DIR_XXX. */ + uint32_t dir; + + /*! + * Maximum number of buffers in the ring. + * Configurable range [16, 512]. + */ + uint32_t ring_size; + + /*! + * Maximum frame size (bytes). + * This is for RX only. + * Configurable range [512, 16384]. + */ + uint32_t max_frame_size; + + /*! Pipe specified for Rx/Tx */ + int pipe; +} bcmpkt_dma_chan_t; + +/*! + * \name DMA device configuration flags. + * \anchor BCMPKT_DMA_DEV_XXX + */ +/*! \{ */ +/*! + * Set this flag to launch a separate Rx thread for each Rx DMA channel. + * On multi-core CPU systems, this allows all Rx DMA channels to be processed in + * parallel. Setting this flag on a single-core CPU system will most likely have + * a negative impact on performance. + */ +#define BCMPKT_DMA_DEV_RX_POLL_SQ (1 << 0) +/*! \} */ + +/*! + * \brief Packet device configuration structure. + * + * This structure defines netdevice hardware configuration parameters. + * The cgrp_size and cgrp_bmp could be got from bcmdrd APIs. + */ +typedef struct bcmpkt_dev_init_s { + /*! Packet device name. */ + char name[BCMPKT_DEV_NAME_MAX]; + + /*! MAC address for default network interface. */ + shr_mac_t mac_addr; + + /*! Number of channels in each group. */ + uint32_t cgrp_size; + + /*! Channel Group bitmap. */ + uint32_t cgrp_bmp; + + /*! Extra poll time in microseconds */ + int extra_poll_time; + + /*! Configuration flags, refer to \ref BCMPKT_DMA_DEV_XXX. */ + uint32_t flags; + +} bcmpkt_dev_init_t; + +/*! + * \brief Packet device driver's statistics. + * + * This structure defines packet device driver's basic counters. + */ +typedef struct bcmpkt_dev_stat_s { + /*! Number of successfully received packets */ + uint64_t rx_packets; + + /*! Number of dropped packets */ + uint64_t rx_dropped; + + /*! Number of successfully transmitted packets */ + uint64_t tx_packets; + + /*! Number of dropped packets */ + uint64_t tx_dropped; + + /*! Number of interrupts */ + uint64_t intrs; + +}bcmpkt_dev_stat_t; + +/*! + * \brief DMA channel configuration function. + * + * \param [in] unit Switch unit number. + * \param [in] chan DMA channel config handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_dma_chan_set_f) (int unit, bcmpkt_dma_chan_t *chan); + +/*! + * \brief DMA channel setting retrieve function. + * + * \param [in] unit Switch unit number. + * \param [in] chan_id DMA channel number. + * \param [out] chan DMA channel config handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_dma_chan_get_f) (int unit, int chan_id, + bcmpkt_dma_chan_t *chan); + +/*! + * \brief DMA channel list retrieve function. + * + * Retrieve a list of DMA channels' configurations. + * + * \param [in] unit Switch unit number. + * \param [in] size The maximum number of \ref bcmpkt_dma_chan_t elements + * can be held. + * \param [out] chans The \ref bcmpkt_dma_chan_t elements array. + * \param [out] num_elements The number of \ref bcmpkt_dma_chan_t elements + * copied to 'chans', if size > 0; total number of + * DMA channel in the unit can be used by packet + * APIs, if size = 0. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_dma_chan_get_list_f) (int unit, uint32_t size, + bcmpkt_dma_chan_t *chans, + uint32_t *num_elements); + +/*! + * \brief Packet module suspend function. + * + * This function is to be called to suspend packet module. + * + * - Suspend all packet DMA channels. + * - SW resources of packet module are preserved. + * + * \param [in] unit Switch unit number. + * \param [in] graceful Indicating graceful or abrupt suspend. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_dev_suspend_f) (int unit, bool graceful); + +/*! + * \brief Packet module resume function. + * + * This function is to be called to resume packet module. + * + * - Resume all packet DMA channels. + * + * \param [in] unit Switch unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_dev_resume_f) (int unit); + +/*! + * \brief Packet module initial function. + * + * This function is to be called for packet module initialization: + * - Initialize packet device driver. + * - Setup RX DMA channels and TX DMA channels. + * - Create default netif (Netif index is 0). + * - Optionally create SOCKET on default netif. + * + * \param [in] unit Switch unit number. + * \param [in] init Packet module initiation handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_EXISTS Net Device already initialized. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_dev_init_f) (int unit, const bcmpkt_dev_init_t *init); + +/*! + * \brief Packet device clean up function. + * + * This function is to be called for packet device clean up. + * - Cleanup all packet I/O DMA channels; + * - Free allocated memories; + * - Destroy netifs and SOCKETs; + * + * \param [in] unit Switch unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_FAIL Cleanup failed. + */ +typedef int (*bcmpkt_dev_cleanup_f) (int unit); + +/*! + * \brief Enable a packet device. + * + * This function is used for activating an initialized packet device. If the + * SOCKET was created on the defualt network interface, the device was enabled + * when created the SOCKET, and the device is not allowed to enable/disable + * through these APIs before destroy it. + * + * \param [in] unit Switch unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Enable failed. + */ +typedef int (*bcmpkt_dev_enable_f) (int unit); + +/*! + * \brief Disable a packet device. + * + * This function is used for deactivating an initialized packet device. If the + * SOCKET was created on the defualt network interface, the device was enabled + * when created the SOCKET, and the device is not allowed to enable/disable + * through these APIs before destroy it. + * + * \param [in] unit Switch unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Disable failed. + */ +typedef int (*bcmpkt_dev_disable_f) (int unit); + +/*! + * \brief Dump packet device information into \c pb. + * + * \param [in] unit Switch unit number. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Device info access failed. + */ +typedef int (*bcmpkt_dev_info_dump_f) (int unit, shr_pb_t *pb); + +/*! + * \brief Packet device statistics dump function. + * + * + * \param [in] unit Switch unit number. + * \param [out] stats Device statistics in driver. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Device statistics access failed. + */ +typedef int (*bcmpkt_dev_stats_get_f) (int unit, bcmpkt_dev_stat_t *stats); + +/*! + * \brief Dump packet device statistics into \c pb. + * + * \param [in] unit Switch unit number. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Device info access failed. + */ +typedef int (*bcmpkt_dev_stats_dump_f) (int unit, shr_pb_t *pb); + +/*! + * \brief Get packet device initialization status. + * + * \param [in] unit Switch unit number. + * \param [out] initialized Initialized or not. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +typedef int (*bcmpkt_dev_initialized_f) (int unit, bool *initialized); + +/*! + * \brief Get packet device running status. + * + * \param [in] unit Switch unit number. + * \param [out] enabled Enabled or not. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +typedef int (*bcmpkt_dev_enabled_f) (int unit, bool *enabled); + +/*! + * \brief Packet device statistics clear function. + * + * \param [in] unit Switch unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Device info access failed. + */ +typedef int (*bcmpkt_dev_stats_clear_f) (int unit); + +/*! + * \brief RCPU header format configuration function. + * + * RCPU header is used for delivering packet metadata between SDK API and + * network driver. + * + * SDK has default RCPU header format configuration support. The user may + * use this API to configure special RCPU header format. + * + * \param [in] unit Switch unit number. + * \param [in] hdr RCPU header configuration handle. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Transmit failed. + */ +typedef int (*bcmpkt_rcpu_hdr_set_f)(int unit, bcmpkt_rcpu_hdr_t *hdr); + +/*! + * \brief RCPU header format retrieve function. + * + * Fetch current RCPU header format configuration. + * + * \param [in] unit Switch unit number. + * \param [in] hdr RCPU header configuration handle. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Transmit failed. + */ +typedef int (*bcmpkt_rcpu_hdr_get_f)(int unit, bcmpkt_rcpu_hdr_t *hdr); + +/*! + * \brief DMA channel operations structure. + */ +typedef struct bcmpkt_dma_chan_ops_s { + + /*! Configure a DMA channel. */ + bcmpkt_dma_chan_set_f set; + + /*! Retrieve a DMA channel's configuration. */ + bcmpkt_dma_chan_get_f get; + + /*! Get multiple DMA channels' configuration. */ + bcmpkt_dma_chan_get_list_f get_list; + +} bcmpkt_dma_chan_ops_t; + +/*! + * \brief Per device info structure. + */ +typedef struct bcmpkt_dev_info_s { + + /*! Family type of the device. */ + bcmpkt_dev_info_family_types_t family_type; + +} bcmpkt_dev_info_t; + +/*! + * \brief RX rate limit set function. + * + * This function is used for setting RX speed limit in terms of KPPS. + * The \c rate = -1 means to disable rate limit. + * + * \param [in] unit Switch unit number. + * \param [in] rate RX maximum rate. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_UNAVAIL function is not supported. + */ +typedef int (*bcmpkt_rx_rate_limit_set_f) (int unit, int rate); + +/*! + * \brief RX rate limit get function. + * + * This function is used for getting RX speed limit in terms of KPPS. + * The \c rate = -1 means rate limit is disabled. + * + * \param [in] unit Switch unit number. + * \param [out] rate RX maximum rate. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Invalid rate point value. + * \retval SHR_E_UNAVAIL function is not supported. + */ +typedef int (*bcmpkt_rx_rate_limit_get_f) (int unit, int *rate); + +/*! + * \brief Packet device rate limit operation vector. + */ +typedef struct bcmpkt_rx_rate_limit_ops_s { + + /*! Set RX rate limit. */ + bcmpkt_rx_rate_limit_set_f set; + + /*! Get RX rate limit. */ + bcmpkt_rx_rate_limit_get_f get; +} bcmpkt_rx_rate_limit_ops_t; + +/*! + * \brief Get per device info. + * + * \param [in] unit Unit number. + * \param [out] info Device info structure. + * + * \return SHR_E_NONE on success, error code otherwise. + */ +typedef int(*bcmpkt_dev_info_get_f)(int unit, + bcmpkt_dev_info_t *info); + +/*! + * \brief Network device operations vector. + */ +typedef struct bcmpkt_dev_s { + /*! Initialized flag: 0 - uninitialized 1 - initialized. */ + int initialized; + + /*! Packet device driver name. */ + char driver_name[128]; + + /*! Packet device driver type. */ + bcmpkt_dev_drv_types_t driver_type; + + /*! Packet device initial function. */ + bcmpkt_dev_init_f init; + + /*! Packet device suspend function. */ + bcmpkt_dev_suspend_f suspend; + + /*! Packet device resume function. */ + bcmpkt_dev_resume_f resume; + + /*! Packet device cleanup function */ + bcmpkt_dev_cleanup_f cleanup; + + /*! Packet device enable function. */ + bcmpkt_dev_enable_f enable; + + /*! Packet device disable function. */ + bcmpkt_dev_disable_f disable; + + /*! Packet device initialization status get function. */ + bcmpkt_dev_initialized_f dev_initialized; + + /*! acket device enabled status get function. */ + bcmpkt_dev_enabled_f enabled; + + /*! DMA channel operations vector. */ + bcmpkt_dma_chan_ops_t dma_chan_ops; + + /*! Dump device information. */ + bcmpkt_dev_info_dump_f info_dump; + + /*! Get device statistics. */ + bcmpkt_dev_stats_get_f stats_get; + + /*! Dump device statistics. */ + bcmpkt_dev_stats_dump_f stats_dump; + + /*! Clear device statistics. */ + bcmpkt_dev_stats_clear_f stats_clear; + + /*! Configure RCPU header format. */ + bcmpkt_rcpu_hdr_set_f rcpu_hdr_set; + + /*! Retrieve RCPU header format. */ + bcmpkt_rcpu_hdr_get_f rcpu_hdr_get; + + /*! Rate limit operations vector. */ + bcmpkt_rx_rate_limit_ops_t rx_rate_limit_ops; + + /*! Get device information. */ + bcmpkt_dev_info_get_f dev_info_get; + +} bcmpkt_dev_t; + +/*! + * \brief DMA channel Configuration function. + * + * \param [in] unit Switch unit number. + * \param [in] chan DMA channel config handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_dma_chan_set(int unit, bcmpkt_dma_chan_t *chan); + +/*! + * \brief DMA channel setting retrieve function. + * + * + * \param [in] unit Switch unit number. + * \param [in] chan_id DMA channel number. + * \param [out] chan DMA channel config handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_dma_chan_get(int unit, int chan_id, bcmpkt_dma_chan_t *chan); + +/*! + * \brief DMA channel list retrieve function. + * + * Retrieve a list of DMA channels' configurations. + * + * \param [in] unit Switch unit number. + * \param [in] size The maximum number of \ref bcmpkt_dma_chan_t elements + * can be held. + * \param [out] chans The \ref bcmpkt_dma_chan_t elements array. + * \param [out] num_elements The number of \ref bcmpkt_dma_chan_t elements + * copied to 'chans', if size > 0; total number of + * DMA channel in the unit can be used by packet + * APIs, if size = 0. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_dma_chan_get_list(int unit, uint32_t size, bcmpkt_dma_chan_t *chans, + uint32_t *num_elements); + +/*! + * \brief Packet module suspend function. + * + * This function is to be called to suspend packet module. + * + * - Suspend by stoping all packet DMA channels. + * - Active netifs and SOCKETs are changing to idle. + * - Allocated memories are all preserved. + * + * \param [in] unit Switch unit number. + * \param [in] graceful Indicating graceful or abrupt suspend. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_dev_suspend(int unit, bool graceful); + +/*! + * \brief Packet module resume function. + * + * This function is to be called to resume packet module. + * + * \param [in] unit Switch unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_dev_resume(int unit); + +/*! + * \brief Packet module initial function. + * + * This function is to be called for packet module initialization: + * - Initialize packet device driver. + * - Setup RX DMA channels and TX DMA channels. + * - Create default netif (Netif index is 0). + * - Optionally create SOCKET on default netif. + * + * \param [in] unit Switch unit number. + * \param [in] init Packet module initiation handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_EXISTS Net Device already initialized. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_dev_init(int unit, const bcmpkt_dev_init_t *init); + +/*! + * \brief Packet device clean up function. + * + * This function is to be called for packet device clean up. + * - Cleanup all packet I/O DMA channels; + * - Free allocated memories; + * - Destroy netifs and SOCKETs; + * + * \param [in] unit Switch unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_FAIL Cleanup failed. + */ +extern int +bcmpkt_dev_cleanup(int unit); + +/*! + * \brief Enable a packet device. + * + * This function is used for activating an initialized packet device. If the + * SOCKET was created on the defualt network interface, the device was enabled + * when created the SOCKET, and the device is not allowed to enable/disable + * through these APIs before destroy it. + * + * \param [in] unit Switch unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Enable failed. + */ +extern int +bcmpkt_dev_enable(int unit); + +/*! + * \brief Disable a packet device. + * + * This function is used for deactivating an initialized packet device. If the + * SOCKET was created on the defualt network interface, the device was enabled + * when created the SOCKET, and the device is not allowed to enable/disable + * through these APIs before destroy it. + * + * \param [in] unit Switch unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Disable failed. + */ +extern int +bcmpkt_dev_disable(int unit); + +/*! + * \brief Get packet device initialization status. + * + * \param [in] unit Switch unit number. + * \param [out] initialized Initialized or not. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmpkt_dev_initialized(int unit, bool *initialized); + +/*! + * \brief Get packet device running status. + * + * \param [in] unit Switch unit number. + * \param [out] enabled Enabled or not. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmpkt_dev_enabled(int unit, bool *enabled); + +/*! + * \brief Dump packet device information into \c pb. + * + * \param [in] unit Switch unit number. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Device info access failed. + */ +extern int +bcmpkt_dev_info_dump(int unit, shr_pb_t *pb); + +/*! + * \brief Packet device statistics get function. + * + * + * \param [in] unit Switch unit number. + * \param [out] stats Device statistics in driver. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Device statistics access failed. + */ +extern int +bcmpkt_dev_stats_get(int unit, bcmpkt_dev_stat_t *stats); + +/*! + * \brief Dump packet device statistics into \c pb. + * + * \param [in] unit Switch unit number. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Device info access failed. + */ +extern int +bcmpkt_dev_stats_dump(int unit, shr_pb_t *pb); + +/*! + * \brief Packet device statistics clear function. + * + * \param [in] unit Switch unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Device info access failed. + */ +extern int +bcmpkt_dev_stats_clear(int unit); + +/*! + * \brief Register a device driver. + * + * \param [in] dev_drv Device driver handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_CONFIG Invalid driver. + * \retval SHR_E_PARAM Invalid parameter. + * \retval SHR_E_EXISTS Driver registered already. + */ +extern int +bcmpkt_dev_drv_register(bcmpkt_dev_t *dev_drv); + +/*! + * \brief Unregister a device driver. + * + * \param [in] type Device driver type. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM Invalid type. + * \retval SHR_E_BUSY The driver is in using. + */ +extern int +bcmpkt_dev_drv_unregister(bcmpkt_dev_drv_types_t type); + +/*! + * \brief Check if packet device driver is attached. + * + * \param [in] unit Unit number. + * + * \retval true Packet device driver already attached. + * \retval false Packet device driver not attached. + */ +extern bool +bcmpkt_dev_drv_attached(int unit); + +/*! + * \brief Attach packet device driver. + * + * This function is used for attach a driver onto a packet device. + * + * The BCMPKT_DEV_DRV_T_AUTO type is used for automatically select device + * driver. In this case, if linux_ngknet.ko was loaded, the KNET driver will be + * selected; otherwise, the corret CMIC driver will be attached onto the device. + * + * \param [in] unit Switch unit number. + * \param [in] type Device driver type. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_PARAM Invalid type. + * \retval SHR_E_EXISTS Driver exists. + * \retval SHR_E_FAIL Attach failed. + */ +extern int +bcmpkt_dev_drv_attach(int unit, bcmpkt_dev_drv_types_t type); + +/*! + * \brief Register UNET device driver. + * + * This function must be called before attaching the + * UNET driver onto a device unit. It has been handled in + * bcmmgmt_pkt_core_init() function in the initialization process. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_CONFIG Invalid driver. + * \retval SHR_E_PARAM Invalid parameter. + * \retval SHR_E_EXISTS Driver registered already. + */ +extern int +bcmpkt_dev_drv_unet_attach(void); + +/*! + * \brief Unregister UNET device driver. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM Invalid type. + * \retval SHR_E_BUSY The driver is in using. + */ +extern int +bcmpkt_dev_drv_unet_detach(void); + +/*! + * \brief Get device driver's type. + * + * \param [in] unit Switch unit number. + * \param [out] type Device driver type. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmpkt_dev_drv_type_get(int unit, bcmpkt_dev_drv_types_t *type); + +/*! + * \brief Detach a device driver. + * + * This function will not call \ref bcmpkt_dev_cleanup to cleanup the packet device + * before the driver is detached. + * + * \param [in] unit Switch unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmpkt_dev_drv_detach(int unit); + +/*! + * \brief Get device driver. + * + * \param [in] unit Unit number. + * \param [out] dev Device driver. + * + * \retval SHR_E_NONE Succeed. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmpkt_dev_drv_get(int unit, bcmpkt_dev_t **dev); + +/*! + * \brief Get device type. + * + * \param [in] unit Unit number. + * \param [out] type Device type. + * + * \retval SHR_E_NONE Succeed. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Input len is too small. + * \retval SHR_E_NOT_FOUND Devuce name not found. + */ +extern int +bcmpkt_dev_type_get(int unit, bcmdrd_dev_type_t *type); + +/*! + * \brief RCPU header format configuration function. + * + * RCPU header is used for delivering packet metadata between SDK API and + * network driver. + * + * SDK has default RCPU header format configuration support. The user may + * use this API to configure special RCPU header format. + * + * \param [in] unit Switch unit number. + * \param [in] hdr RCPU header configuration handle. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Transmit failed. + */ +extern int +bcmpkt_rcpu_hdr_set(int unit, bcmpkt_rcpu_hdr_t *hdr); + +/*! + * \brief RCPU header format retrieve function. + * + * Fetch current RCPU header format configuration. + * + * \param [in] unit Switch unit number. + * \param [in] hdr RCPU header configuration handle. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Transmit failed. + */ +extern int +bcmpkt_rcpu_hdr_get(int unit, bcmpkt_rcpu_hdr_t *hdr); + +/*! + * \brief RX rate limit set function. + * + * This function is used for setting RX speed limit in terms of KPPS. + * The \c rate = -1 means to disable rate limit. + * + * \param [in] unit Switch unit number. + * \param [in] rate RX maximum rate. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_UNAVAIL function is not supported. + */ +extern int +bcmpkt_rx_rate_limit_set(int unit, int rate); + +/*! + * \brief RX rate limit get function. + * + * This function is used for getting RX speed limit in terms of KPPS. + * The \c rate = -1 means rate limit is disabled. + * + * \param [in] unit Switch unit number. + * \param [out] rate RX maximum rate. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Invalid rate pointer value. + * \retval SHR_E_UNAVAIL function is not supported. + */ +extern int +bcmpkt_rx_rate_limit_get(int unit, int *rate); + +#endif /* BCMPKT_DEV_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_dump.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_dump.h new file mode 100644 index 0000000..993fd0b --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_dump.h @@ -0,0 +1,309 @@ +/*! \file bcmpkt_dump.h + * + * \brief Packet dump functions. + * + * The defintions are kept separate to minimize the header file + * dependencies for the stand-alone PMD library. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_DUMP_H +#define BCMPKT_DUMP_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif +#include +#include +#include + +/*! + * \name BCMPKT dump flags. + * \anchor BCMPKT_DUMP_F_XXX + */ +/*! \{ */ +/*! Dump all fields contents. (deprecated) */ +#define BCMPKT_DUMP_F_ALL 0 +/*! Dump non-zero field content only. */ +#define BCMPKT_DUMP_F_NONZERO (0x1 << 0) +/*! \} */ + +/*! + * \brief Dump raw data buffer into \c pb. + * + * \param [in,out] pb Print buffer handle. + * \param [in] data Data to be printed. + * \param [in] size print bytes. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM Invalid type. + */ +extern int +bcmpkt_data_dump(shr_pb_t *pb, const uint8_t *data, int size); + +/*! + * \brief Dump packet data buffer into \c pb. + * + * \param [in,out] pb Print buffer handle. + * \param [in] dbuf Data buffer to be printed. + * + * \retval None. + */ +extern void +bcmpkt_data_buf_dump(bcmpkt_data_buf_t *dbuf, shr_pb_t *pb); + +/*! + * \brief Dump all supported RXPMD fields into \c pb. + * + * If view_name is given, dump common fields and the fields belonging to the + * view. If view_name is NULL, dump common fields and the fields of all view's. + * If view_name is unknown, only dump common fields. + * + * \param [in] dev_type Device type. + * \param [in] view_name RXPMD view name. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE success + * \retval SHR_E_PARAM Check parameter failed + * \retval SHR_E_INTERNAL API internal error. + */ +extern int +bcmpkt_rxpmd_field_list_dump(bcmdrd_dev_type_t dev_type, char *view_name, + shr_pb_t *pb); + +/*! + * \brief Dump RXPMD content into \c pb. + * + * This function is used for dumping the content of an RXPMD. If the + * BCMPKT_DUMP_F_NONZERO is set, only dump non-zero fields. + * + * \param [in] dev_type Device type. + * \param [in] rxpmd RXPMD handle. + * \param [in] flags Refer to \ref BCMPKT_RXPMD_DUMP_F_XXX. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE success + * \retval SHR_E_PARAM Check parameter failed + * \retval SHR_E_INTERNAL API internal error. + */ +extern int +bcmpkt_rxpmd_dump(bcmdrd_dev_type_t dev_type, uint32_t *rxpmd, uint32_t flags, + shr_pb_t *pb); + +/*! + * \brief Dump RX reasons into \c pb. + * + * \param [in] dev_type Device type. + * \param [in] rxpmd RXPMD handle. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE success + * \retval SHR_E_PARAM Check parameter failed + * \retval SHR_E_UNAVAIL Not support Reason. + * \retval SHR_E_INTERNAL API internal error. + */ +extern int +bcmpkt_rx_reason_dump(bcmdrd_dev_type_t dev_type, uint32_t *rxpmd, + shr_pb_t *pb); + +/*! + * \brief Dump all supported TXPMD fields into \c pb. + * + * If view_name is given, dump common fields and the fields belonging to the + * view. If view_name is NULL, dump common fields and the fields of all view's. + * If view_name is unknown, only dump common fields. + * + * \param [in] dev_type Device type. + * \param [in] view_name TXPMD view name. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE success + * \retval SHR_E_PARAM Check parameter failed + * \retval SHR_E_INTERNAL API internal error. + */ +extern int +bcmpkt_txpmd_field_list_dump(bcmdrd_dev_type_t dev_type, char *view_name, + shr_pb_t *pb); + +/*! + * \brief Dump TXPMD content into \c pb. + * + * This function is used for dumping the content of a TXPMD. If the + * BCMPKT_DUMP_F_NONZERO is set, only dump non-zero fields. + * + * \param [in] dev_type Device type. + * \param [in] txpmd TXPMD handle. + * \param [in] flags Defined as \ref BCMPKT_TXPMD_DUMP_F_XXX. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_txpmd_dump(bcmdrd_dev_type_t dev_type, uint32_t *txpmd, uint32_t flags, + shr_pb_t *pb); + +/*! + * \brief Dump all supported LBHDR fields into \c pb. + * + * If view_name is given, dump common fields and the fields belonging to the + * view. If view_name is NULL, dump common fields and the fields of all view's. + * If view_name is unknown, only dump common fields. + * + * \param [in] dev_type Device type. + * \param [in] view_name LBHDR view name. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE success + * \retval SHR_E_PARAM Check parameter failed + * \retval SHR_E_INTERNAL API internal error. + */ +extern int +bcmpkt_lbhdr_field_list_dump(bcmdrd_dev_type_t dev_type, char *view_name, + shr_pb_t *pb); + +/*! + * \brief Dump LBHDR content into \c pb. + * + * This function is used for dumping the content of a LBHDR. If the + * BCMPKT_DUMP_F_NONZERO is set, only dump non-zero fields. + * + * \param [in] dev_type Device type. + * \param [in] lbhdr LBHDR handle. + * \param [in] flags Defined as \ref BCMPKT_LBHDR_DUMP_F_XXX. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_lbhdr_dump(bcmdrd_dev_type_t dev_type, uint32_t *lbhdr, uint32_t flags, + shr_pb_t *pb); + +/*! + * \brief Dump all supported flexhdr fields into \c pb. + * + * If view_name is given, dump common fields and the fields belonging to the + * view. If view_name is NULL, dump common fields and the fields of all view's. + * If view_name is unknown, only dump common fields. + * + * \param [in] variant variant type. + * \param [in] hid flexhdr ID. + * \param [in] view_name flexhdr view name. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE success + * \retval SHR_E_PARAM Check parameter failed + * \retval SHR_E_INTERNAL API internal error. + */ +extern int +bcmpkt_flexhdr_field_list_dump(bcmlrd_variant_t variant, uint32_t hid, + char *view_name, shr_pb_t *pb); + +/*! + * \brief Dump flexhdr content into \c pb. + * + * This function is used for dumping the content of a flexhdr. If the + * BCMPKT_DUMP_F_NONZERO is set, only dump non-zero fields. + * + * \param [in] variant Variant type. + * \param [in] hid flexhdr ID. + * \param [in] flexhdr flexhdr handle. + * \param [in] flags Defined as \ref BCMPKT_DUMP_F_XXX. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_flexhdr_dump(bcmlrd_variant_t variant, uint32_t hid, uint32_t *flexhdr, + uint32_t flags, shr_pb_t *pb); + +/*! + * \brief Dump RXPMD_FLEX content into \c pb. + * + * This function is used for dumping the content of an RXPMD_FLEX. If the + * BCMPKT_DUMP_F_NONZERO is set, only dump non-zero fields. + * + * \param [in] variant Variant type. + * \param [in] rxpmd_flex RXPMD_FLEX handle. + * \param [in] profile Flexible data profile. + * \param [in] flags Refer to \ref BCMPKT_DUMP_F_XXX. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE success + * \retval SHR_E_PARAM Check parameter failed + * \retval SHR_E_INTERNAL API internal error. + */ +extern int +bcmpkt_rxpmd_flex_dump(bcmlrd_variant_t variant, uint32_t *rxpmd_flex, + uint32_t profile, uint32_t flags, shr_pb_t *pb); + +/*! + * \brief Dump RXPMD_FLEX content into \c pb. + * + * This function is used for dumping the content of an RXPMD_FLEX. If the + * BCMPKT_DUMP_F_NONZERO is set, only dump non-zero fields. + * + * \param [in] unit Device unit. + * \param [in] rxpmd_flex RXPMD_FLEX handle. + * \param [in] profile Flexible data profile. + * \param [in] flags Refer to \ref BCMPKT_DUMP_F_XXX. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE success + * \retval SHR_E_PARAM Check parameter failed + * \retval SHR_E_INTERNAL API internal error. + */ +extern int +bcmpkt_rxpmd_device_flex_dump(int unit, uint32_t *rxpmd_flex, + uint32_t profile, uint32_t flags, shr_pb_t *pb); + +/*! + * \brief Dump RX reasons into \c pb. + * + * \param [in] variant Variant type. + * \param [in] rxpmd_flex RXPMD_FLEX handle. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE success + * \retval SHR_E_PARAM Check parameter failed + * \retval SHR_E_UNAVAIL Not support Reason. + * \retval SHR_E_INTERNAL API internal error. + */ +extern int +bcmpkt_rxpmd_flex_reason_dump(bcmlrd_variant_t variant, + uint32_t *rxpmd_flex, shr_pb_t *pb); + +#endif /* BCMPKT_DUMP_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_flexhdr.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_flexhdr.h new file mode 100644 index 0000000..8e38dca --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_flexhdr.h @@ -0,0 +1,409 @@ +/*! \file bcmpkt_flexhdr.h + * + * Flexhdr access interface. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_FLEXHDR_H +#define BCMPKT_FLEXHDR_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#include +#endif +#include +#include +#include +#include +#include + +/*! Invalid profile ID. */ +#define BCMPKT_FLEXHDR_PROFILE_NONE -1 + +/*! Max profile count. */ +#define BCMPKT_FLEXHDR_PROFILE_MAX 64 + +/*! Max profile count. */ +#define BCMPKT_FLEXHDR_PROFILE_BITMAP_MAX 4 + +/*! CELL Error status bitmap. */ +#define BCMPKT_RXFLEXMETA_ST_CELL_ERROR (0x1 << 18) + +/*! + * \name Packet FLEX reason utility macros. + * \anchor BCMPKT_RXPMD_FLEX_REASON_OPS + */ +/*! \{ */ +/*! + * Macro to check if a reason is included in a + * set of reasons (\ref bcmpkt_bitmap_t). Returns: + * zero => reason is not included in the set + * non-zero => reason is included in the set + */ +#define BCMPKT_RXPMD_FLEX_REASON_GET(_reasons, _reason) \ + SHR_BITGET(((_reasons).pbits), (_reason)) + +/*! + * Macro to add a reason to a set of + * reasons (\ref bcmpkt_bitmap_t) + */ +#define BCMPKT_RXPMD_FLEX_REASON_SET(_reasons, _reason) \ + SHR_BITSET(((_reasons).pbits), (_reason)) + +/*! + * Macro to clear a reason from a set of + * reasons (\ref bcmpkt_bitmap_t) + */ +#define BCMPKT_RXPMD_FLEX_REASON_CLEAR(_reasons, _reason) \ + SHR_BITCLR(((_reasons).pbits), (_reason)) + +/*! + * Macro to add all reasons to a set of reasons. + */ +#define BCMPKT_RXPMD_FLEX_REASON_SET_ALL(_reasons, _count) \ + SHR_BITSET_RANGE(((_reasons).pbits), 0, _count) + +/*! + * Macro to clear all reasons. + */ +#define BCMPKT_RXPMD_FLEX_REASON_CLEAR_ALL(_reasons, _count) \ + SHR_BITCLR_RANGE(((_reasons).pbits), 0, _count) + +/*! + * Macro to check for no reason. + */ +#define BCMPKT_RXPMD_FLEX_REASON_IS_NULL(_reasons, _count) \ + SHR_BITNULL_RANGE(((_reasons).pbits), 0, _count) + +/*! + * Macro to get reasons number. + */ +#define BCMPKT_RXPMD_FLEX_REASONS_COUNT(_reasons, _count, _reason_count) \ + SHR_BITCOUNT_RANGE(((_reasons).pbits), _count, 0, _reason_count) + +/*! + * Macro to compare 2 reasons, return 1 for exact match. + */ +#define BCMPKT_RXPMD_FLEX_REASON_EQ(_reasons1, _reasons2, _count) \ + SHR_BITEQ_RANGE(((_reasons1).pbits), ((_reasons2).pbits), \ + 0, _count) +/*! \} */ + +/*! + * Flex header field profile info. + */ +typedef struct bcmpkt_flex_field_profile_s { + /*! Minbit in NPL header. */ + uint32_t minbit; + + /*! Maxbit in NPL header. */ + uint32_t maxbit; +} bcmpkt_flex_field_profile_t; + +/*! + * Flex header field data. + */ +typedef struct bcmpkt_flex_field_metadata_s { + /*! Field name. */ + char *name; + + /*! Field ID. */ + int fid; + + /*! Number of profiles defined in NPL. */ + int profile_cnt; + + /*! Field boundary for each profile defined in NPL. */ + bcmpkt_flex_field_profile_t profile[BCMPKT_FLEXHDR_PROFILE_MAX]; +} bcmpkt_flex_field_metadata_t; + +/*! + * Flex header field info structure. + */ +typedef struct bcmpkt_flex_field_info_s { + + /*! Number of header fields. */ + int num_fields; + + /*! Header field names. */ + bcmpkt_flex_field_metadata_t *info; + + /*! Profile bitmap count. */ + int profile_bmp_cnt; + + /*! Profile bitmap. */ + uint32_t profile_bmp[BCMPKT_FLEXHDR_PROFILE_BITMAP_MAX]; +} bcmpkt_flex_field_info_t; + +/*! RXPMD data update function pointer. */ +typedef int (*bcmpkt_rxpmd_data_set_f)( + int unit, + bcmpkt_flex_field_metadata_t *pmd_fld_info); + +/*! Process RXPMD entry. */ +typedef int (*bcmpkt_rxpmd_data_process_f)(int unit, uint64_t prof_id); + +/*! Update RXMPMD data from HW during warmboot. */ +typedef int (*bcmpkt_rxpmd_data_update_f)(int unit); + +/*! Array of RXPMD LT subscribe function pointers. */ +typedef struct bcmpkt_rxpmd_func_s { + /*! Set RXMPMD data. */ + bcmpkt_rxpmd_data_set_f rxpmd_data_set; + + /*! Process RXMPMD data flow entry. */ + bcmpkt_rxpmd_data_process_f rxpmd_data_flow; + + /*! Process RXMPMD data remap entry. */ + bcmpkt_rxpmd_data_process_f rxpmd_data_remap; + + /*! Update RXMPMD data from HW during warmboot. */ + bcmpkt_rxpmd_data_update_f rxpmd_data_update; +} bcmpkt_rxpmd_func_t; + +/*! Externs for the rxpmd functions. */ +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern const bcmpkt_rxpmd_func_t _bd##_rxpmd_func; +#include + +/*! + * \brief Get Header name for a given header ID. + * + * \param [in] variant Variant type. + * \param [in] hid flexhdr ID. + * \param [out] name flexhdr name string. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_flexhdr_header_name_get(bcmlrd_variant_t variant, + uint32_t hid, char **name); + +/*! + * \brief Get Header encapsulation length for a given header ID. + * + * \param [in] variant Variant type. + * \param [in] hid flexhdr ID. + * \param [out] len header length. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_flexhdr_len_get(bcmlrd_variant_t variant, uint32_t hid, + uint32_t *len); + +/*! + * \brief Get Header ID for a given flexhdr name. + * + * \param [in] variant Variant type. + * \param [in] name flexhdr name string. + * \param [out] hid flexhdr ID. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_NOT_FOUND Not found the name. + */ +extern int +bcmpkt_flexhdr_header_id_get(bcmlrd_variant_t variant, + char* name, uint32_t *hid); + +/*! + * \brief Check if flexhdr is supported. + * + * \param [in] variant Variant type. + * \param [in] hid flexhdr ID. + * \param [out] is_supported Supported for flexhdr. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not supported. + */ +extern int +bcmpkt_flexhdr_is_supported(bcmlrd_variant_t variant, uint32_t hid, + bool *is_supported); + +/*! + * \brief Get field name for a given flexhdr field ID. + * + * \param [in] variant Variant type. + * \param [in] hid flexhdr ID. + * \param [in] fid flexhdr field ID. + * \param [out] name flexhdr field name string. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_flexhdr_field_name_get(bcmlrd_variant_t variant, uint32_t hid, + int fid, char **name); + +/*! + * \brief Get field ID for a given flexhdr field name. + * + * \param [in] variant Variant type. + * \param [in] hid flexhdr ID. + * \param [in] name flexhdr field name string. + * \param [out] fid flexhdr Field ID. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_NOT_FOUND Not found the name. + */ +extern int +bcmpkt_flexhdr_field_id_get(bcmlrd_variant_t variant, uint32_t hid, + char* name, int *fid); + +/*! + * \brief Get field info for a given flexhdr type. + * + * \param [in] variant Variant type. + * \param [in] hid flexhdr ID. + * \param [out] info field information. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_NOT_FOUND Not found the name. + */ +extern int +bcmpkt_flexhdr_field_info_get(bcmlrd_variant_t variant, uint32_t hid, + bcmpkt_flex_field_info_t *info); + +/*! + * \brief Get RX reasons from RXPMD_FLEX. + * + * Decode packet's RX reasons into "reasons". A received packet may have one RX + * reason, multiple RX reasons, or none reason. RX reasons are in the format of + * bitmap. Each bit means one reason type (refer to \ref BCMPKT_RX_REASON_XXX). + * + * User may use \ref BCMPKT_RXPMD_FLEX_REASON_OPS to parse each individual reason based + * on this function's return value "reasons". + * + * \param [in] variant Variant type. + * \param [in] rxpmd_flex RXPMD_FLEX handle. + * \param [out] reasons RX reasons in bit array. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support Reason. + * \retval SHR_E_INTERNAL Internal issue. + */ +extern int +bcmpkt_rxpmd_flex_reasons_get(bcmlrd_variant_t variant, uint32_t *rxpmd_flex, + bcmpkt_bitmap_t *reasons); + +/*! + * \brief Set RX reasons into the RXPMD_FLEX. (Internally used for filter configuration.) + * + * Set RX reasons into RXPMD_FLEX data for packet filter purpose. + * + * \param [in] variant Variant type. + * \param [in] reasons Reasons bit array. + * \param [in,out] rxpmd_flex RXPMD_FLEX handle. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support Reason. + * \retval SHR_E_INTERNAL Internal issue. + */ +extern int +bcmpkt_rxpmd_flex_reasons_set(bcmlrd_variant_t variant, + bcmpkt_bitmap_t *reasons, uint32_t *rxpmd_flex); + +/*! + * \brief Get an RX reason's name. + * + * \param [in] variant Variant type. + * \param [in] reason Reason ID. + * \param [out] name Reason name string handle. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_rxpmd_flex_reason_name_get(bcmlrd_variant_t variant, + int reason, char **name); + +/*! + * \brief Get max number of RX reason types. + * + * \param [in] variant Variant type. + * \param [out] num Maximum RX reason types. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_rxpmd_flex_reason_max_get(bcmlrd_variant_t variant, uint32_t *num); + +/*! + * \brief Get reason ID for a given RX reason name. + * + * \param [in] variant Variant type. + * \param [in] name Reason name string handle. + * \param [out] rid Reason ID. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_NOT_FOUND Not found the name. + */ +extern int +bcmpkt_rxpmd_flex_reason_id_get(bcmlrd_variant_t variant, + char* name, int *rid); + +/*! + * \brief Intialize RXPMD module + * + * \param [in] unit Device ID. + * \param [in] warm Warmboot flag. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNIT Incorrect unit. + */ +extern int +bcmpkt_flexhdr_init(int unit, bool warm); + +/*! + * \brief Cleanup RXPMD module + * + * \param [in] unit Device ID. + * + * \retval SHR_E_NONE success. + */ +extern int +bcmpkt_flexhdr_cleanup(int unit); + +#endif /* BCMPKT_FLEXHDR_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_flexhdr_field.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_flexhdr_field.h new file mode 100644 index 0000000..2427bf3 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_flexhdr_field.h @@ -0,0 +1,113 @@ +/*! \file bcmpkt_flexhdr_field.h + * + * Flexhdr field access interface. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_FLEXHDR_FIELD_H +#define BCMPKT_FLEXHDR_FIELD_H + +/*! + * \brief Get value from a flexhdr field. + * + * \param [in] variant Variant type. + * \param [in] hid flexhdr ID. + * \param [in] flexhdr flexhdr handle. + * \param [in] profile Flexible data profile. + * \param [in] fid flexhdr field ID. + * \param [out] val Field value. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support the field. + */ +extern int +bcmpkt_flexhdr_field_get(bcmlrd_variant_t variant, uint32_t hid, + uint32_t *flexhdr, int profile, int fid, uint32_t *val); + +/*! + * \brief Set value into a flexhdr field. + * + * \param [in] variant Variant type. + * \param [in] hid flexhdr ID. + * \param [in,out] flexhdr flexhdr handle. + * \param [in] profile Flexible data profile. + * \param [in] fid flexhdr field ID. + * \param [in] val Set value. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support the field. + */ +extern int +bcmpkt_flexhdr_field_set(bcmlrd_variant_t variant, uint32_t hid, + uint32_t *flexhdr, int profile, int fid, uint32_t val); + +/*! + * \brief Get value from a flexhdr field. + * + * \param [in] unit Device unit number. + * \param [in] hid flexhdr ID. + * \param [in] flexhdr flexhdr handle. + * \param [in] profile Flexible data profile. + * \param [in] fid flexhdr field ID. + * \param [out] val Field value. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support the field. + */ +extern int +bcmpkt_flexhdr_device_field_get(int unit, uint32_t hid, + uint32_t *flexhdr, int profile, int fid, + uint32_t *val); + +/*! + * \brief Set value into a flexhdr field. + * + * \param [in] unit Device unit number. + * \param [in] hid flexhdr ID. + * \param [in,out] flexhdr flexhdr handle. + * \param [in] profile Flexible data profile. + * \param [in] fid flexhdr field ID. + * \param [in] val Set value. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support the field. + */ +extern int +bcmpkt_flexhdr_device_field_set(int unit, uint32_t hid, + uint32_t *flexhdr, int profile, int fid, + uint32_t val); + +#endif /* BCMPKT_FLEXHDR_FIELD_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_flexhdr_internal.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_flexhdr_internal.h new file mode 100644 index 0000000..8851a13 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_flexhdr_internal.h @@ -0,0 +1,177 @@ +/*! \file bcmpkt_flexhdr_internal.h + * + * \brief Flex Packet MetaData internal library. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_FLEXHDR_INTERNAL_H +#define BCMPKT_FLEXHDR_INTERNAL_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif +#include +#include + +/*! PMD types. + * This has to match the header IDs present in + * xfc_map_parser/hdr/header_map.yml file. + */ +/*! Generic loopback header type */ +#define BCMPKT_GENERIC_LOOPBACK_T 0 +/*! Higig 3 header type */ +#define BCMPKT_HG3_BASE_T 1 +/*! Higig3 extension 0 header type */ +#define BCMPKT_HG3_EXTENSION_0_T 2 +/*! RXPMD flex header type */ +#define BCMPKT_RXPMD_FLEX_T 3 +/*! Count of PMD types */ +#define BCMPKT_PMD_COUNT 4 + +/*! Get a flex field from a PMD buffer. */ +typedef int32_t (*bcmpkt_flex_field_get_f)(uint32_t *data, int profile, uint32_t *val); + +/*! Set a flex field within a PMD buffer. */ +typedef int32_t (*bcmpkt_flex_field_set_f)(uint32_t *data, int profile, uint32_t val); + +/*! Decode flex packet's RX reasons. */ +typedef void (*bcmpkt_flex_reason_decode_f) (uint32_t *data, bcmpkt_bitmap_t *reasons); + +/*! Encode flex packet's RX reasons */ +typedef void (*bcmpkt_flex_reason_encode_f) (bcmpkt_bitmap_t *reasons, uint32_t *data); + +/*! Get a flex field from a PMD buffer. */ +typedef int (*bcmpkt_flex_field_common_get_f)( + uint32_t *data, + bcmpkt_flex_field_metadata_t *fld_info, + int profile, + uint32_t *val); + +/*! Set a flex field from a PMD buffer. */ +typedef int (*bcmpkt_flex_field_common_set_f)( + uint32_t *data, + bcmpkt_flex_field_metadata_t *fld_info, + int profile, + uint32_t val); + +/*! + * \brief Flex Packet reasons information structure. + */ +typedef struct bcmpkt_flex_reasons_info_s { + /*! Number of reasons supported. */ + int num_reasons; + + /*! Reason names. */ + shr_enum_map_t *reason_names; + + /*! Encode RX reasons */ + bcmpkt_flex_reason_encode_f reason_encode; + + /*! Decode RX reasons */ + bcmpkt_flex_reason_decode_f reason_decode; + +} bcmpkt_flex_reasons_info_t; + +/*! + * \brief Flex Packet metadata information structure. + */ +typedef struct bcmpkt_flex_pmd_info_s { + + /*! Header field info. */ + bcmpkt_flex_field_info_t *field_info; + + /*! Header support */ + bool is_supported; + + /*! Flex reasons info */ + bcmpkt_flex_reasons_info_t *reasons_info; + + /*! Flex field get functions. */ + bcmpkt_flex_field_get_f *flex_fget; + + /*! Flex field set functions. */ + bcmpkt_flex_field_set_f *flex_fset; + + /*! Flex field common get functions. */ + bcmpkt_flex_field_common_get_f flex_common_fget; + + /*! Flex field common set functions. */ + bcmpkt_flex_field_common_set_f flex_common_fset; +} bcmpkt_flex_pmd_info_t; +#ifndef PKTIO_IMPL +/*! \cond Externs for the required functions. */ +#define BCMLRD_VARIANT_ENTRY(_bd,_bu,_va,_ve,_vu,_vv,_vo,_vd,_r0,_r1) \ + extern bcmpkt_flex_pmd_info_t * _bd##_vu##_va##_flex_pmd_info_get(uint32_t hid); +#define BCMLRD_VARIANT_OVERRIDE +#include +#endif +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern bcmpkt_flex_pmd_info_t * _bc##_flex_pmd_info_get(uint32_t hid); +#define BCMDRD_DEVLIST_OVERRIDE +#include +#ifndef PKTIO_IMPL +#define BCMLRD_VARIANT_ENTRY(_bd,_bu,_va,_ve,_vu,_vv,_vo,_vd,_r0,_r1) \ + extern shr_enum_map_t * _bd##_vu##_va##_flexhdr_map_get(void); +#define BCMLRD_VARIANT_OVERRIDE +#include +#endif +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern shr_enum_map_t * _bc##_flexhdr_map_get(void); +#define BCMDRD_DEVLIST_OVERRIDE +#include +#ifndef PKTIO_IMPL +#define BCMLRD_VARIANT_ENTRY(_bd,_bu,_va,_ve,_vu,_vv,_vo,_vd,_r0,_r1) \ + extern int _bd##_vu##_va##_flexhdr_variant_support_map[BCMPKT_PMD_COUNT]; +#define BCMLRD_VARIANT_OVERRIDE +#include +#endif +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern int _bc##_flexhdr_variant_support_map[BCMPKT_PMD_COUNT]; +#define BCMDRD_DEVLIST_OVERRIDE +#include +/*! \endcond */ + +/*! + * \brief Get flex header support mapping for a given variant. + * + * \param [in] variant Variant type. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_NOT_FOUND Not found the name. + */ +extern int * +bcmpkt_flexhdr_support_map_get(bcmlrd_variant_t variant); + +#endif /* BCMPKT_FLEXHDR_INTERNAL_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_hg3.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_hg3.h new file mode 100644 index 0000000..d3c7f99 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_hg3.h @@ -0,0 +1,62 @@ +/*! \file bcmpkt_hg3.h + * + * Common macros and definitions for Higig3 protocol + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_HG3_H +#define BCMPKT_HG3_H + +/* Note, ether type set to same value as reset value of R_GSH_ETHERTYPEr(700) */ +/*! Ethernet type used for Higig3 header */ +#define BCMPKT_HG3_ETHER_TYPE 0x2BC + +/*! Higig3 base header size (bytes). */ +#define BCMPKT_HG3_BASE_HEADER_SIZE_BYTES 8 +/*! Higig3 base header size (words). */ +#define BCMPKT_HG3_BASE_HEADER_SIZE_WORDS 2 + +/*! Higig3 extension 0 header size (bytes). */ +#define BCMPKT_HG3_EXT0_HEADER_SIZE_BYTES 8 +/*! Higig3 extension 0 header size (words). */ +#define BCMPKT_HG3_EXT0_HEADER_SIZE_WORDS 2 + +/*! Higig3 header size (bytes). Includes base and ext0 header */ +#define BCMPKT_HG3_SIZE_BYTES (BCMPKT_HG3_BASE_HEADER_SIZE_BYTES + \ + BCMPKT_HG3_EXT0_HEADER_SIZE_BYTES) +/*! Higig3 header size (words). Includes base and ext0 header */ +#define BCMPKT_HG3_SIZE_WORDS (BCMPKT_HG3_BASE_HEADER_SIZE_WORDS + \ + BCMPKT_HG3_EXT0_HEADER_SIZE_WORDS) + +/*! Higig3 extension 0 field max. */ +#define BCMPKT_HG3_EXT0_FID_MAX 32 +#endif /* BCMPKT_HG3_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_higig_defs.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_higig_defs.h new file mode 100644 index 0000000..d810e25 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_higig_defs.h @@ -0,0 +1,359 @@ +#ifndef BCMPKT_HIGIG_DEFS_H +#define BCMPKT_HIGIG_DEFS_H +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * Tool: INTERNAL/regs/xgs/generate-chip.pl + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides access macros for the HiGig module header. + * + ******************************************************************************/ + +#include + +/******************************************************************************* + * + * HIGIG DEFINITIONS BEGIN HERE + * + ******************************************************************************/ + + +/* Start of HiGig packet indicators */ +#define BCMPKT_HIGIG_SOF 0xfb +#define BCMPKT_HIGIG2_SOF 0xfc + + +/* HiGig module header size (in bytes) */ +#define BCMPKT_HIGIG_SIZE 12 +#define BCMPKT_HIGIG2_SIZE 16 + + +/* HiGig module header size (in words) */ +#define BCMPKT_HIGIG_WSIZE 3 +#define BCMPKT_HIGIG2_WSIZE 4 + + +/******************************************************************************* + * SWFORMAT: HIGIG + * BLOCKS: + * SIZE: 96 + ******************************************************************************/ +#define HIGIG_OFFSET 0x00000000 + +#define HIGIG_BLKACC () + +#define HIGIG_SIZE 12 + +/* + * This structure should be used to declare and program HIGIG. + * + */ +typedef union HIGIG_s { + uint32_t v[3]; + uint32_t higig[3]; + uint32_t _higig; +} HIGIG_t; + +#define HIGIG_CLR(r) sal_memset(&((r).higig[0]), 0, sizeof(HIGIG_t)) +#define HIGIG_SET(r,i,d) (r).higig[i] = d +#define HIGIG_GET(r,i) (r).higig[i] + +/* + * These macros can be used to access individual fields. + * + */ +#define HIGIG_VC_LABELf_GET(r) (((r).higig[2]) & 0xfffff) +#define HIGIG_VC_LABELf_SET(r,f) (r).higig[2]=(((r).higig[2] & ~((uint32_t)0xfffff)) | (((uint32_t)f) & 0xfffff)) +#define HIGIG_CLASSIFICATION_TAGf_GET(r) ((((r).higig[2]) >> 16) & 0xffff) +#define HIGIG_CLASSIFICATION_TAGf_SET(r,f) (r).higig[2]=(((r).higig[2] & ~((uint32_t)0xffff << 16)) | ((((uint32_t)f) & 0xffff) << 16)) +#define HIGIG_LABEL_PRESENTf_GET(r) ((((r).higig[2]) >> 20) & 0x1) +#define HIGIG_LABEL_PRESENTf_SET(r,f) (r).higig[2]=(((r).higig[2] & ~((uint32_t)0x1 << 20)) | ((((uint32_t)f) & 0x1) << 20)) +#define HIGIG_L3f_GET(r) ((((r).higig[2]) >> 21) & 0x1) +#define HIGIG_L3f_SET(r,f) (r).higig[2]=(((r).higig[2] & ~((uint32_t)0x1 << 21)) | ((((uint32_t)f) & 0x1) << 21)) +#define HIGIG_DST_MODID_5f_GET(r) ((((r).higig[2]) >> 22) & 0x1) +#define HIGIG_DST_MODID_5f_SET(r,f) (r).higig[2]=(((r).higig[2] & ~((uint32_t)0x1 << 22)) | ((((uint32_t)f) & 0x1) << 22)) +#define HIGIG_SRC_MODID_5f_GET(r) ((((r).higig[2]) >> 23) & 0x1) +#define HIGIG_SRC_MODID_5f_SET(r,f) (r).higig[2]=(((r).higig[2] & ~((uint32_t)0x1 << 23)) | ((((uint32_t)f) & 0x1) << 23)) +#define HIGIG_MIRRORf_GET(r) ((((r).higig[2]) >> 24) & 0x1) +#define HIGIG_MIRRORf_SET(r,f) (r).higig[2]=(((r).higig[2] & ~((uint32_t)0x1 << 24)) | ((((uint32_t)f) & 0x1) << 24)) +#define HIGIG_MIRROR_DONEf_GET(r) ((((r).higig[2]) >> 25) & 0x1) +#define HIGIG_MIRROR_DONEf_SET(r,f) (r).higig[2]=(((r).higig[2] & ~((uint32_t)0x1 << 25)) | ((((uint32_t)f) & 0x1) << 25)) +#define HIGIG_MIRROR_ONLYf_GET(r) ((((r).higig[2]) >> 26) & 0x1) +#define HIGIG_MIRROR_ONLYf_SET(r,f) (r).higig[2]=(((r).higig[2] & ~((uint32_t)0x1 << 26)) | ((((uint32_t)f) & 0x1) << 26)) +#define HIGIG_INGRESS_TAGGEDf_GET(r) ((((r).higig[2]) >> 27) & 0x1) +#define HIGIG_INGRESS_TAGGEDf_SET(r,f) (r).higig[2]=(((r).higig[2] & ~((uint32_t)0x1 << 27)) | ((((uint32_t)f) & 0x1) << 27)) +#define HIGIG_DST_TGIDf_GET(r) ((((r).higig[2]) >> 28) & 0x7) +#define HIGIG_DST_TGIDf_SET(r,f) (r).higig[2]=(((r).higig[2] & ~((uint32_t)0x7 << 28)) | ((((uint32_t)f) & 0x7) << 28)) +#define HIGIG_DST_Tf_GET(r) ((((r).higig[2]) >> 31) & 0x1) +#define HIGIG_DST_Tf_SET(r,f) (r).higig[2]=(((r).higig[2] & ~((uint32_t)0x1 << 31)) | ((((uint32_t)f) & 0x1) << 31)) +#define HIGIG_DST_MODID_LSf_GET(r) (((r).higig[1]) & 0x1f) +#define HIGIG_DST_MODID_LSf_SET(r,f) (r).higig[1]=(((r).higig[1] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) +#define HIGIG_CNGf_GET(r) ((((r).higig[1]) >> 5) & 0x1) +#define HIGIG_CNGf_SET(r,f) (r).higig[1]=(((r).higig[1] & ~((uint32_t)0x1 << 5)) | ((((uint32_t)f) & 0x1) << 5)) +#define HIGIG_HEADER_TYPEf_GET(r) ((((r).higig[1]) >> 6) & 0x3) +#define HIGIG_HEADER_TYPEf_SET(r,f) (r).higig[1]=(((r).higig[1] & ~((uint32_t)0x3 << 6)) | ((((uint32_t)f) & 0x3) << 6)) +#define HIGIG_PRIORITYf_GET(r) ((((r).higig[1]) >> 8) & 0x7) +#define HIGIG_PRIORITYf_SET(r,f) (r).higig[1]=(((r).higig[1] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) +#define HIGIG_DST_PORTf_GET(r) ((((r).higig[1]) >> 11) & 0x1f) +#define HIGIG_DST_PORTf_SET(r,f) (r).higig[1]=(((r).higig[1] & ~((uint32_t)0x1f << 11)) | ((((uint32_t)f) & 0x1f) << 11)) +#define HIGIG_SRC_PORT_TGIDf_GET(r) ((((r).higig[1]) >> 16) & 0x3f) +#define HIGIG_SRC_PORT_TGIDf_SET(r,f) (r).higig[1]=(((r).higig[1] & ~((uint32_t)0x3f << 16)) | ((((uint32_t)f) & 0x3f) << 16)) +#define HIGIG_PFMf_GET(r) ((((r).higig[1]) >> 22) & 0x3) +#define HIGIG_PFMf_SET(r,f) (r).higig[1]=(((r).higig[1] & ~((uint32_t)0x3 << 22)) | ((((uint32_t)f) & 0x3) << 22)) +#define HIGIG_OPCODEf_GET(r) ((((r).higig[1]) >> 24) & 0x7) +#define HIGIG_OPCODEf_SET(r,f) (r).higig[1]=(((r).higig[1] & ~((uint32_t)0x7 << 24)) | ((((uint32_t)f) & 0x7) << 24)) +#define HIGIG_SRC_MODID_LSf_GET(r) ((((r).higig[1]) >> 27) & 0x1f) +#define HIGIG_SRC_MODID_LSf_SET(r,f) (r).higig[1]=(((r).higig[1] & ~((uint32_t)0x1f << 27)) | ((((uint32_t)f) & 0x1f) << 27)) +#define HIGIG_VTAGf_GET(r) (((r).higig[0]) & 0xffff) +#define HIGIG_VTAGf_SET(r,f) (r).higig[0]=(((r).higig[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) +#define HIGIG_DST_MODID_6f_GET(r) ((((r).higig[0]) >> 16) & 0x1) +#define HIGIG_DST_MODID_6f_SET(r,f) (r).higig[0]=(((r).higig[0] & ~((uint32_t)0x1 << 16)) | ((((uint32_t)f) & 0x1) << 16)) +#define HIGIG_SRC_MODID_6f_GET(r) ((((r).higig[0]) >> 17) & 0x1) +#define HIGIG_SRC_MODID_6f_SET(r,f) (r).higig[0]=(((r).higig[0] & ~((uint32_t)0x1 << 17)) | ((((uint32_t)f) & 0x1) << 17)) +#define HIGIG_HDR_EXT_LENf_GET(r) ((((r).higig[0]) >> 18) & 0x7) +#define HIGIG_HDR_EXT_LENf_SET(r,f) (r).higig[0]=(((r).higig[0] & ~((uint32_t)0x7 << 18)) | ((((uint32_t)f) & 0x7) << 18)) +#define HIGIG_CNG1f_GET(r) ((((r).higig[0]) >> 21) & 0x1) +#define HIGIG_CNG1f_SET(r,f) (r).higig[0]=(((r).higig[0] & ~((uint32_t)0x1 << 21)) | ((((uint32_t)f) & 0x1) << 21)) +#define HIGIG_HGIf_GET(r) ((((r).higig[0]) >> 22) & 0x3) +#define HIGIG_HGIf_SET(r,f) (r).higig[0]=(((r).higig[0] & ~((uint32_t)0x3 << 22)) | ((((uint32_t)f) & 0x3) << 22)) +#define HIGIG_STARTf_GET(r) ((((r).higig[0]) >> 24) & 0xff) +#define HIGIG_STARTf_SET(r,f) (r).higig[0]=(((r).higig[0] & ~((uint32_t)0xff << 24)) | ((((uint32_t)f) & 0xff) << 24)) + +/******************************************************************************* + * End of 'HIGIG' + ******************************************************************************/ + + + + +/******************************************************************************* + * SWFORMAT: HIGIG2 + * BLOCKS: + * SIZE: 128 + ******************************************************************************/ +#define HIGIG2_OFFSET 0x00000000 + +#define HIGIG2_BLKACC () + +#define HIGIG2_SIZE 16 + +/* + * This structure should be used to declare and program HIGIG2. + * + */ +typedef union HIGIG2_s { + uint32_t v[4]; + uint32_t higig2[4]; + uint32_t _higig2; +} HIGIG2_t; + +#define HIGIG2_CLR(r) sal_memset(&((r).higig2[0]), 0, sizeof(HIGIG2_t)) +#define HIGIG2_SET(r,i,d) (r).higig2[i] = d +#define HIGIG2_GET(r,i) (r).higig2[i] + +/* + * These macros can be used to access individual fields. + * + */ +#define HIGIG2_PPD_DATAf_GET(r,a) bcmdrd_field_be_get((r).higig2,4,0,63,a) +#define HIGIG2_PPD_DATAf_SET(r,a) bcmdrd_field_be_set((r).higig2,4,0,63,a) +#define HIGIG2_PPD0_RSVD_4_0f_GET(r) (((r).higig2[3]) & 0x1f) +#define HIGIG2_PPD0_RSVD_4_0f_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) +#define HIGIG2_PPD0_HDR_EXT_LENf_GET(r) ((((r).higig2[3]) >> 5) & 0x7) +#define HIGIG2_PPD0_HDR_EXT_LENf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x7 << 5)) | ((((uint32_t)f) & 0x7) << 5)) +#define HIGIG2_PPD0_OPCODEf_GET(r) ((((r).higig2[3]) >> 8) & 0x7) +#define HIGIG2_PPD0_OPCODEf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) +#define HIGIG2_PPD0_PRESERVE_DOT1Pf_GET(r) ((((r).higig2[3]) >> 11) & 0x1) +#define HIGIG2_PPD0_PRESERVE_DOT1Pf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 11)) | ((((uint32_t)f) & 0x1) << 11)) +#define HIGIG2_PPD0_PRESERVE_DSCPf_GET(r) ((((r).higig2[3]) >> 12) & 0x1) +#define HIGIG2_PPD0_PRESERVE_DSCPf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) +#define HIGIG2_PPD0_SRC_Tf_GET(r) ((((r).higig2[3]) >> 13) & 0x1) +#define HIGIG2_PPD0_SRC_Tf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 13)) | ((((uint32_t)f) & 0x1) << 13)) +#define HIGIG2_PPD0_PFMf_GET(r) ((((r).higig2[3]) >> 14) & 0x3) +#define HIGIG2_PPD0_PFMf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x3 << 14)) | ((((uint32_t)f) & 0x3) << 14)) +#define HIGIG2_PPD0_VID_LOWf_GET(r) ((((r).higig2[3]) >> 16) & 0xff) +#define HIGIG2_PPD0_VID_LOWf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0xff << 16)) | ((((uint32_t)f) & 0xff) << 16)) +#define HIGIG2_PPD0_VID_HIGHf_GET(r) ((((r).higig2[3]) >> 24) & 0xff) +#define HIGIG2_PPD0_VID_HIGHf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0xff << 24)) | ((((uint32_t)f) & 0xff) << 24)) +#define HIGIG2_PPD0_REP_IDf_GET(r) (((r).higig2[2]) & 0x7ffff) +#define HIGIG2_PPD0_REP_IDf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0x7ffff)) | (((uint32_t)f) & 0x7ffff)) +#define HIGIG2_PPD0_VC_LABELf_GET(r) (((r).higig2[2]) & 0xffff) +#define HIGIG2_PPD0_VC_LABELf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) +#define HIGIG2_PPD0_MIRROR_CLASSIFICATION_TAGf_GET(r) ((((r).higig2[2]) >> 4) & 0xffff) +#define HIGIG2_PPD0_MIRROR_CLASSIFICATION_TAGf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0xffff << 4)) | ((((uint32_t)f) & 0xffff) << 4)) +#define HIGIG2_PPD0_ORIG_SRC_PORTf_GET(r) ((((r).higig2[2]) >> 4) & 0xff) +#define HIGIG2_PPD0_ORIG_SRC_PORTf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) +#define HIGIG2_PPD0_ORIG_SRC_MODIDf_GET(r) ((((r).higig2[2]) >> 12) & 0xff) +#define HIGIG2_PPD0_ORIG_SRC_MODIDf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0xff << 12)) | ((((uint32_t)f) & 0xff) << 12)) +#define HIGIG2_PPD0_VC_LABEL_19_16f_GET(r) ((((r).higig2[2]) >> 16) & 0xf) +#define HIGIG2_PPD0_VC_LABEL_19_16f_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0xf << 16)) | ((((uint32_t)f) & 0xf) << 16)) +#define HIGIG2_PPD0_LABEL_PRESENTf_GET(r) ((((r).higig2[2]) >> 20) & 0x1) +#define HIGIG2_PPD0_LABEL_PRESENTf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0x1 << 20)) | ((((uint32_t)f) & 0x1) << 20)) +#define HIGIG2_PPD0_L3f_GET(r) ((((r).higig2[2]) >> 21) & 0x1) +#define HIGIG2_PPD0_L3f_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0x1 << 21)) | ((((uint32_t)f) & 0x1) << 21)) +#define HIGIG2_PPD0_LABEL_OVERLAY_TYPEf_GET(r) ((((r).higig2[2]) >> 22) & 0x3) +#define HIGIG2_PPD0_LABEL_OVERLAY_TYPEf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0x3 << 22)) | ((((uint32_t)f) & 0x3) << 22)) +#define HIGIG2_PPD0_MIRRORf_GET(r) ((((r).higig2[2]) >> 24) & 0x1) +#define HIGIG2_PPD0_MIRRORf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0x1 << 24)) | ((((uint32_t)f) & 0x1) << 24)) +#define HIGIG2_PPD0_MIRROR_DONEf_GET(r) ((((r).higig2[2]) >> 25) & 0x1) +#define HIGIG2_PPD0_MIRROR_DONEf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0x1 << 25)) | ((((uint32_t)f) & 0x1) << 25)) +#define HIGIG2_PPD0_MIRROR_ONLYf_GET(r) ((((r).higig2[2]) >> 26) & 0x1) +#define HIGIG2_PPD0_MIRROR_ONLYf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0x1 << 26)) | ((((uint32_t)f) & 0x1) << 26)) +#define HIGIG2_PPD0_INGRESS_TAGGEDf_GET(r) ((((r).higig2[2]) >> 27) & 0x1) +#define HIGIG2_PPD0_INGRESS_TAGGEDf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0x1 << 27)) | ((((uint32_t)f) & 0x1) << 27)) +#define HIGIG2_PPD0_DST_TGIDf_GET(r) ((((r).higig2[2]) >> 28) & 0x7) +#define HIGIG2_PPD0_DST_TGIDf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0x7 << 28)) | ((((uint32_t)f) & 0x7) << 28)) +#define HIGIG2_PPD0_DST_Tf_GET(r) ((((r).higig2[2]) >> 31) & 0x1) +#define HIGIG2_PPD0_DST_Tf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0x1 << 31)) | ((((uint32_t)f) & 0x1) << 31)) +#define HIGIG2_PPD1_RSVD_4_0f_GET(r) (((r).higig2[3]) & 0x1f) +#define HIGIG2_PPD1_RSVD_4_0f_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) +#define HIGIG2_PPD1_HDR_EXT_LENf_GET(r) ((((r).higig2[3]) >> 5) & 0x7) +#define HIGIG2_PPD1_HDR_EXT_LENf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x7 << 5)) | ((((uint32_t)f) & 0x7) << 5)) +#define HIGIG2_PPD1_OPCODEf_GET(r) ((((r).higig2[3]) >> 8) & 0x7) +#define HIGIG2_PPD1_OPCODEf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) +#define HIGIG2_PPD1_RSVD_12_11f_GET(r) ((((r).higig2[3]) >> 11) & 0x3) +#define HIGIG2_PPD1_RSVD_12_11f_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x3 << 11)) | ((((uint32_t)f) & 0x3) << 11)) +#define HIGIG2_PPD1_SRC_Tf_GET(r) ((((r).higig2[3]) >> 13) & 0x1) +#define HIGIG2_PPD1_SRC_Tf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 13)) | ((((uint32_t)f) & 0x1) << 13)) +#define HIGIG2_PPD1_PFMf_GET(r) ((((r).higig2[3]) >> 14) & 0x3) +#define HIGIG2_PPD1_PFMf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x3 << 14)) | ((((uint32_t)f) & 0x3) << 14)) +#define HIGIG2_PPD1_VID_LOWf_GET(r) ((((r).higig2[3]) >> 16) & 0xff) +#define HIGIG2_PPD1_VID_LOWf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0xff << 16)) | ((((uint32_t)f) & 0xff) << 16)) +#define HIGIG2_PPD1_VID_HIGHf_GET(r) ((((r).higig2[3]) >> 24) & 0xff) +#define HIGIG2_PPD1_VID_HIGHf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0xff << 24)) | ((((uint32_t)f) & 0xff) << 24)) +#define HIGIG2_PPD1_RSVD_48_32f_GET(r) (((r).higig2[2]) & 0xffff) +#define HIGIG2_PPD1_RSVD_48_32f_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) +#define HIGIG2_PPD1_CLASSIFICATION_TAGf_GET(r) ((((r).higig2[2]) >> 16) & 0xffff) +#define HIGIG2_PPD1_CLASSIFICATION_TAGf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0xffff << 16)) | ((((uint32_t)f) & 0xffff) << 16)) +#define HIGIG2_PPD2_SOURCE_TYPEf_GET(r) (((r).higig2[3]) & 0x1) +#define HIGIG2_PPD2_SOURCE_TYPEf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) +#define HIGIG2_PPD2_DEST_TYPEf_GET(r) ((((r).higig2[3]) >> 1) & 0x1) +#define HIGIG2_PPD2_DEST_TYPEf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) +#define HIGIG2_PPD2_PRESERVE_DOT1Pf_GET(r) ((((r).higig2[3]) >> 2) & 0x1) +#define HIGIG2_PPD2_PRESERVE_DOT1Pf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) +#define HIGIG2_PPD2_PRESERVE_DSCPf_GET(r) ((((r).higig2[3]) >> 3) & 0x1) +#define HIGIG2_PPD2_PRESERVE_DSCPf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) +#define HIGIG2_PPD2_VNI_HIGHf_GET(r) ((((r).higig2[3]) >> 4) & 0x3) +#define HIGIG2_PPD2_VNI_HIGHf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) +#define HIGIG2_PPD2_RSVD_7_6f_GET(r) ((((r).higig2[3]) >> 6) & 0x3) +#define HIGIG2_PPD2_RSVD_7_6f_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x3 << 6)) | ((((uint32_t)f) & 0x3) << 6)) +#define HIGIG2_PPD2_OPCODEf_GET(r) ((((r).higig2[3]) >> 8) & 0x7) +#define HIGIG2_PPD2_OPCODEf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) +#define HIGIG2_PPD2_REP_ID_17_16f_GET(r) ((((r).higig2[3]) >> 8) & 0x3) +#define HIGIG2_PPD2_REP_ID_17_16f_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) +#define HIGIG2_PPD2_RSVD_11f_GET(r) ((((r).higig2[3]) >> 11) & 0x1) +#define HIGIG2_PPD2_RSVD_11f_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 11)) | ((((uint32_t)f) & 0x1) << 11)) +#define HIGIG2_PPD2_LAG_FAILOVERf_GET(r) ((((r).higig2[3]) >> 12) & 0x1) +#define HIGIG2_PPD2_LAG_FAILOVERf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) +#define HIGIG2_PPD2_DO_NOT_LEARNf_GET(r) ((((r).higig2[3]) >> 13) & 0x1) +#define HIGIG2_PPD2_DO_NOT_LEARNf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 13)) | ((((uint32_t)f) & 0x1) << 13)) +#define HIGIG2_PPD2_DO_NOT_MODIFYf_GET(r) ((((r).higig2[3]) >> 14) & 0x1) +#define HIGIG2_PPD2_DO_NOT_MODIFYf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 14)) | ((((uint32_t)f) & 0x1) << 14)) +#define HIGIG2_PPD2_MIRRORf_GET(r) ((((r).higig2[3]) >> 15) & 0x1) +#define HIGIG2_PPD2_MIRRORf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 15)) | ((((uint32_t)f) & 0x1) << 15)) +#define HIGIG2_PPD2_SOURCE_VPf_GET(r) ((((r).higig2[3]) >> 16) & 0xffff) +#define HIGIG2_PPD2_SOURCE_VPf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0xffff << 16)) | ((((uint32_t)f) & 0xffff) << 16)) +#define HIGIG2_PPD2_DEST_VPf_GET(r) (((r).higig2[2]) & 0xffff) +#define HIGIG2_PPD2_DEST_VPf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) +#define HIGIG2_PPD2_REP_ID_15_0f_GET(r) (((r).higig2[2]) & 0xffff) +#define HIGIG2_PPD2_REP_ID_15_0f_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) +#define HIGIG2_PPD2_VNI_LOWf_GET(r) ((((r).higig2[2]) >> 16) & 0xff) +#define HIGIG2_PPD2_VNI_LOWf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0xff << 16)) | ((((uint32_t)f) & 0xff) << 16)) +#define HIGIG2_PPD2_VNI_MIDf_GET(r) ((((r).higig2[2]) >> 24) & 0x3) +#define HIGIG2_PPD2_VNI_MIDf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0x3 << 24)) | ((((uint32_t)f) & 0x3) << 24)) +#define HIGIG2_PPD2_FWD_TYPEf_GET(r) ((((r).higig2[2]) >> 26) & 0x1f) +#define HIGIG2_PPD2_FWD_TYPEf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0x1f << 26)) | ((((uint32_t)f) & 0x1f) << 26)) +#define HIGIG2_PPD2_MULTIPOINTf_GET(r) ((((r).higig2[2]) >> 31) & 0x1) +#define HIGIG2_PPD2_MULTIPOINTf_SET(r,f) (r).higig2[2]=(((r).higig2[2] & ~((uint32_t)0x1 << 31)) | ((((uint32_t)f) & 0x1) << 31)) +#define HIGIG2_PPD3_PPD3_CONTAINER_TYPEf_GET(r) (((r).higig2[3]) & 0xf) +#define HIGIG2_PPD3_PPD3_CONTAINER_TYPEf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) +#define HIGIG2_PPD3_RSVD_7_4f_GET(r) ((((r).higig2[3]) >> 4) & 0xf) +#define HIGIG2_PPD3_RSVD_7_4f_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) +#define HIGIG2_PPD3_OPCODEf_GET(r) ((((r).higig2[3]) >> 8) & 0x7) +#define HIGIG2_PPD3_OPCODEf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) +#define HIGIG2_PPD3_SOURCE_TYPEf_GET(r) ((((r).higig2[3]) >> 11) & 0x1) +#define HIGIG2_PPD3_SOURCE_TYPEf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 11)) | ((((uint32_t)f) & 0x1) << 11)) +#define HIGIG2_PPD3_RSVD_28f_GET(r) ((((r).higig2[3]) >> 12) & 0x1) +#define HIGIG2_PPD3_RSVD_28f_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) +#define HIGIG2_PPD3_DO_NOT_LEARNf_GET(r) ((((r).higig2[3]) >> 13) & 0x1) +#define HIGIG2_PPD3_DO_NOT_LEARNf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 13)) | ((((uint32_t)f) & 0x1) << 13)) +#define HIGIG2_PPD3_PRESERVE_DOT1Pf_GET(r) ((((r).higig2[3]) >> 14) & 0x1) +#define HIGIG2_PPD3_PRESERVE_DOT1Pf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 14)) | ((((uint32_t)f) & 0x1) << 14)) +#define HIGIG2_PPD3_PRESERVE_DSCPf_GET(r) ((((r).higig2[3]) >> 15) & 0x1) +#define HIGIG2_PPD3_PRESERVE_DSCPf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0x1 << 15)) | ((((uint32_t)f) & 0x1) << 15)) +#define HIGIG2_PPD3_SOURCE_INFOf_GET(r) ((((r).higig2[3]) >> 16) & 0xffff) +#define HIGIG2_PPD3_SOURCE_INFOf_SET(r,f) (r).higig2[3]=(((r).higig2[3] & ~((uint32_t)0xffff << 16)) | ((((uint32_t)f) & 0xffff) << 16)) +#define HIGIG2_PPD3_PPD3_DATA_CONTAINERf_GET(r) ((r).higig2[2]) +#define HIGIG2_PPD3_PPD3_DATA_CONTAINERf_SET(r,f) (r).higig2[2]=((uint32_t)f) +#define HIGIG2_PPD_TYPEf_GET(r) (((r).higig2[1]) & 0x7) +#define HIGIG2_PPD_TYPEf_SET(r,f) (r).higig2[1]=(((r).higig2[1] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) +#define HIGIG2_CCf_GET(r) ((((r).higig2[1]) >> 3) & 0x3) +#define HIGIG2_CCf_SET(r,f) (r).higig2[1]=(((r).higig2[1] & ~((uint32_t)0x3 << 3)) | ((((uint32_t)f) & 0x3) << 3)) +#define HIGIG2_EHVf_GET(r) ((((r).higig2[1]) >> 5) & 0x1) +#define HIGIG2_EHVf_SET(r,f) (r).higig2[1]=(((r).higig2[1] & ~((uint32_t)0x1 << 5)) | ((((uint32_t)f) & 0x1) << 5)) +#define HIGIG2_DPf_GET(r) ((((r).higig2[1]) >> 6) & 0x3) +#define HIGIG2_DPf_SET(r,f) (r).higig2[1]=(((r).higig2[1] & ~((uint32_t)0x3 << 6)) | ((((uint32_t)f) & 0x3) << 6)) +#define HIGIG2_LBIDf_GET(r) ((((r).higig2[1]) >> 8) & 0xff) +#define HIGIG2_LBIDf_SET(r,f) (r).higig2[1]=(((r).higig2[1] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) +#define HIGIG2_SRC_PIDf_GET(r) ((((r).higig2[1]) >> 16) & 0xff) +#define HIGIG2_SRC_PIDf_SET(r,f) (r).higig2[1]=(((r).higig2[1] & ~((uint32_t)0xff << 16)) | ((((uint32_t)f) & 0xff) << 16)) +#define HIGIG2_SRC_MODIDf_GET(r) ((((r).higig2[1]) >> 24) & 0xff) +#define HIGIG2_SRC_MODIDf_SET(r,f) (r).higig2[1]=(((r).higig2[1] & ~((uint32_t)0xff << 24)) | ((((uint32_t)f) & 0xff) << 24)) +#define HIGIG2_DST_PORT_MGIDLf_GET(r) (((r).higig2[0]) & 0xff) +#define HIGIG2_DST_PORT_MGIDLf_SET(r,f) (r).higig2[0]=(((r).higig2[0] & ~((uint32_t)0xff)) | (((uint32_t)f) & 0xff)) +#define HIGIG2_DST_MODID_MGIDHf_GET(r) ((((r).higig2[0]) >> 8) & 0xff) +#define HIGIG2_DST_MODID_MGIDHf_SET(r,f) (r).higig2[0]=(((r).higig2[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) +#define HIGIG2_TCf_GET(r) ((((r).higig2[0]) >> 16) & 0xf) +#define HIGIG2_TCf_SET(r,f) (r).higig2[0]=(((r).higig2[0] & ~((uint32_t)0xf << 16)) | ((((uint32_t)f) & 0xf) << 16)) +#define HIGIG2_MCSTf_GET(r) ((((r).higig2[0]) >> 20) & 0x1) +#define HIGIG2_MCSTf_SET(r,f) (r).higig2[0]=(((r).higig2[0] & ~((uint32_t)0x1 << 20)) | ((((uint32_t)f) & 0x1) << 20)) +#define HIGIG2_STARTf_GET(r) ((((r).higig2[0]) >> 24) & 0xff) +#define HIGIG2_STARTf_SET(r,f) (r).higig2[0]=(((r).higig2[0] & ~((uint32_t)0xff << 24)) | ((((uint32_t)f) & 0xff) << 24)) + +/******************************************************************************* + * End of 'HIGIG2' + ******************************************************************************/ + + + + +/******************************************************************************* + * + * HIGIG SYMBOL TABLE + * + ******************************************************************************/ + +extern bcmdrd_symbols_t higig_symbols; + + +#endif /* BCMPKT_HIGIG_DEFS_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_internal.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_internal.h new file mode 100644 index 0000000..120e2ee --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_internal.h @@ -0,0 +1,244 @@ +/*! \file bcmpkt_internal.h + * + * Internal common head file. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_INTERNAL_H +#define BCMPKT_INTERNAL_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#include +#include +#endif + +#include +#include +#include +#include + +/*! Get a field from a DOP Trace buffer. */ +typedef uint32_t (*bcmpkt_dop_field_get_f)(uint32_t *data_in, + uint32_t *data_out, + uint32_t data_out_len); + +/*! Get a field array from a DOP Trace buffer. */ +typedef uint32_t (*bcmpkt_pt_to_dop_info_array_get_f)(int unit, + const char *pt_name, + const uint8_t *data, + uint32_t port_id, + uint32_t *info_cnt, + uint32_t **info); + +/*! Get a field from a DOP Trace buffer. */ +typedef uint32_t (*bcmpkt_pt_to_dop_info_get_f)(int unit, const char *pt_name, + const uint8_t *data, + uint32_t port_id, + uint32_t *info); + +/*! Get a DOP data buffer. */ +typedef uint32_t (*bcmpkt_dop_fids_get_f)(uint32_t *fid_list, + uint8_t *fid_count); + +/*! Get a Trace DOP attributions. */ +typedef uint32_t (*bcmpkt_dop_iget_f)(void); + +/*! + * \brief RX callback information structure. + */ +typedef struct bcmpkt_rx_cb_info_s { + + /*! Next callback info handle. */ + struct bcmpkt_rx_cb_info_s *cb_next; + + /*! Callback flags. */ + uint32_t flags; + + /*! Callback function. */ + bcmpkt_rx_cb_f cb_func; + + /*! Callback application contex. */ + void *cb_data; + + /*! True: Pending in callback. */ + bool cb_pending; + + /*! True: Pending in callback unregistering state. */ + bool cb_unreging; + +} bcmpkt_rx_cb_info_t; + +/*! + * \brief Check if a registered device driver is being actively used. + * + * \param [in] type Device driver type. + * + * \retval 1 Some device is using the driver. + * \retval 0 No device is using the driver. + */ +extern int +bcmpkt_dev_drv_inuse(bcmpkt_dev_drv_types_t type); + +/*! + * \brief Check if a registered SOCKET driver is being actively used + * + * \param [in] type SOCKET driver type. + * + * \retval 1 Some device is using the driver. + * \retval 0 No device is using the driver. + */ +extern int +bcmpkt_socket_drv_inuse(bcmpkt_socket_drv_types_t type); + +/*! + * \brief Get device ID. + * + * \param [in] unit Unit number. + * \param [out] id Device ID. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_PARAM Input len is too small. + * \retval SHR_E_NOT_FOUND Devuce name not found. + */ +extern int +bcmpkt_dev_id_get(int unit, uint32_t *id); + +/*! + * \brief Get RCPU header's configuration handle. + * + * \param [in] unit Switch unit number. + * + * \retval RCPU header's configuration handle. + */ +extern bcmpkt_rcpu_hdr_t * +bcmpkt_rcpu_hdr(int unit); + +/*! + * \brief Suspend or resume KNET packet transmit function. + * + * This function is for suspend or resume packet transmission in KNET. + * + * \param [in] unit Switch unit number. + * \param [in] suspend True to suspend TX packets or false to resume. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_knet_tx_suspend_set(int unit, bool suspend); + +/*! + * \brief Generate TX header. + * + * \param [in] unit Unit number. + * \param [in] packet Packet data. + * \param [in] rhdr_en Enable RCPU header or not. + * + * \return SHR_E_NONE on success, error code otherwise. + */ +extern int +bcmpkt_dev_tx_hdr_generate(int unit, + bcmpkt_packet_t *packet, bool rhdr_en); + +/*! + * \brief Internal function for generating TX header for XGS devices. + * + * \param [in] unit Unit number. + * \param [in] packet Packet data. + * \param [in] rhdr_en Enable RCPU header or not. + * + * \return SHR_E_NONE on success, error code otherwise. + */ +extern int +bcmpkt_txhdr_xgs_gen(int unit, bcmpkt_packet_t *packet, bool rhdr_en); + +/*! + * \brief Internal function for generating TX header for XFS(flex) devices. + * + * \param [in] unit Unit number. + * \param [in] packet Packet data. + * \param [in] rhdr_en Enable RCPU header or not. + * + * \return SHR_E_NONE on success, error code otherwise. + */ +extern int +bcmpkt_txhdr_xfs_gen(int unit, bcmpkt_packet_t *packet, bool rhdr_en); + +/*! + * \brief Internal function for generating TX header for XFS + XGS devices. + * + * \param [in] unit Unit number. + * \param [in] packet Packet data. + * \param [in] rhdr_en Enable RCPU header or not. + * + * \return SHR_E_NONE on success, error code otherwise. + */ +extern int +bcmpkt_txhdr_xfs_xgs_gen(int unit, bcmpkt_packet_t *packet, bool rhdr_en); + +/*! + * \brief Internal function for generating TX header for DNX devices. + * + * \param [in] unit Unit number. + * \param [in] packet Packet data. + * \param [in] rhdr_en Enable RCPU header or not. + * + * \return SHR_E_NONE on success, error code otherwise. + */ +extern int +bcmpkt_txhdr_dnx_gen(int unit, bcmpkt_packet_t * packet, bool rhdr_en); + +/*! + * \brief Internal function for generating TX header for DNXF devices. + * + * \param [in] unit Unit number. + * \param [in] packet Packet data. + * \param [in] rhdr_en Enable RCPU header or not. + * + * \return SHR_E_NONE on success, error code otherwise. + */ +extern int +bcmpkt_txhdr_dnxf_gen(int unit, bcmpkt_packet_t * packet, bool rhdr_en); + +/*! \cond Externs for trace driver attach functions. */ +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern int _bd##_dev_drv_attach(bcmpkt_dev_t *drv); +#define BCMDRD_DEVLIST_OVERRIDE +#include +/*! \endcond */ + +#endif /* BCMPKT_INTERNAL_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_knet.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_knet.h new file mode 100644 index 0000000..7cd0569 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_knet.h @@ -0,0 +1,929 @@ +/*! \file bcmpkt_knet.h + * + * KNET access interfaces, including virtual network interface (netif) + * management and KNET packet filter. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_KNET_H +#define BCMPKT_KNET_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#include +#endif +#include +#include +#include + +/*! Maximum chars are allowed in network interface name. */ +#define BCMPKT_NETIF_NAME_MAX 16 + +/** + * \name Network interface creation flags. + * \anchor BCMPKT_NETIF_F_XXX + */ +/*! \{ */ +/*! + * RCPU header encapsulation is used for deliver packet metadata to/from + * applications. + * Applications should encapsulate RCPU header when send packets to the netif, + * and may parser RCPU header when receive packets from the netif. UNET could be + * created on such netif, which supports RCPU encapsulation, only. + */ +#define BCMPKT_NETIF_F_RCPU_ENCAP (1 << 0) +/*! + * Bind this netif with a RX DMA channel. All packets from + * the DMA channel will be forwarded to this netif. + */ +#define BCMPKT_NETIF_F_BIND_RX_CH (1 << 1) + +/*! + * Bind this network interface to a front-panel switch port for + * transmission. All packets from this network interface will be + * forwarded to the bound switch port. + */ +#define BCMPKT_NETIF_F_BIND_TX_PORT (1 << 2) + +/*! + * Add VLAN tag for packets transmitted via this network interface. + */ +#define BCMPKT_NETIF_F_ADD_TAG (1 << 3) + +/*! + * Create network interface with specified ID. + */ +#define BCMPKT_NETIF_F_WITH_ID (1 << 4) + +/*! + * Bingding packet metadata for transmission. + */ +#define BCMPKT_NETIF_F_BIND_TX_PMD (1 << 5) + +/*! + * Replace network interface with ID. + */ +#define BCMPKT_NETIF_F_REPLACE (1 << 6) + +/*! + * Use shared net device on composite devices. + */ +#define BCMPKT_NETIF_F_USE_SHARED_NDEV (1 << 10) + +/*! + * Network interface user data size in bytes. + */ +#define BCMPKT_NETIF_USER_DATA_SIZE 64 + +/*! \} */ + +/*! + * \brief Packet network interface structure. + * + * This structure defines a network interface configuration. + * + * "id" is allocated by \ref bcmpkt_netif_create_f function. + * + * "mac_addr" and "vlan" are the network interface's Layer 2 configuration. + * "port", "port_encap" and "port_queue" are for binding a switch front port. + * + * "dma_chan_id" works for binding a DMA channel with a netif. + */ +typedef struct bcmpkt_netif_s { + + /*! Network interface ID. */ + int id; + + /*! Creation flag. Refer to \ref BCMPKT_NETIF_F_XXX flags. */ + uint32_t flags; + + /*! MAC address associated with this network interface. */ + shr_mac_t mac_addr; + + /*! + * Default VLAN ID associated with this network interface. + * When the \ref BCMPKT_NETIF_F_ADD_TAG flag is configured, every TX packet + * will be added a VLAN tag with this value. + */ + uint16_t vlan; + + /*! + * Bind with a network interface for transmit destination port. All packet + * sent from the netif will be forwarded to this port directly. + */ + int port; + + /*! + * "port_encap" works with "port" to tell the encapsulation type of the port. + * "ieee", "higig" or "higig2". + * Only support "ieee" currently. NULL string is taken as "ieee". + */ + char port_encap[10]; + + /*! + * "port_queue" works with "port" to tell egress queue number. + */ + int port_queue; + + /*! + * This parameter works with \ref BCMPKT_NETIF_F_BIND_RX_CH to bind a RX DMA + * channel with this netif. + */ + int dma_chan_id; + + /*! + * Max packet size is for this netif. Any packet which size is bigger than + * this setting will be dropped. + */ + uint32_t max_frame_size; + + /*! Network interface name. */ + char name[BCMPKT_NETIF_NAME_MAX]; + + /*! Network interface user data. */ + uint8_t user_data[BCMPKT_NETIF_USER_DATA_SIZE]; + + /*! Packet metadata for transmission. */ + bcmpkt_pmd_t tx_pmd; + +} bcmpkt_netif_t; + +/*! + * \brief Network interface traverse callback function type. + * + * \param [in] unit Switch unit number. + * \param [in] netif Network interface. + * \param [in] cb_data Application-provided context for callback function. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_FAIL Failed. + */ +typedef int (*bcmpkt_netif_traverse_cb_f) (int unit, + const bcmpkt_netif_t *netif, + void *cb_data); + +/*! + * \brief Network interface create function. + * + * This function is used for creating a new network interface. + * + * The bcmpkt_netif_t.id is an output parameter. + * + * \param [in] unit Switch unit number. + * \param [in,out] netif Network interface handle. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameter failed. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_netif_create_f) (int unit, bcmpkt_netif_t *netif); + +/*! + * \brief Network interface get function. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [out] netif Network interface handle. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_BADID Invalid network interface ID. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + * \retval SHR_E_NOT_FOUND Not found the entry. + */ +typedef int (*bcmpkt_netif_get_f) (int unit, int netif_id, + bcmpkt_netif_t *netif); + +/*! + * \brief Network interface traverse function. + * + * This function is for traversing all network interfaces' configuration. + * The callback function will be called for each present netif. Refer to + * \ref bcmpkt_netif_traverse_cb_f for callback function type. + * + * \param [in] unit Switch unit number. + * \param [in] cb_func Network interface traverse callback function. + * \param [in] cb_data Application-provided context for callback function. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_netif_traverse_f) (int unit, + bcmpkt_netif_traverse_cb_f cb_func, + void *cb_data); + +/*! + * \brief Network destroy function. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_BADID Invalid network interface ID. + * \retval SHR_E_FAIL Access driver failed. + * \retval SHR_E_RESOURCE Not allowed to destroy a UNET netif. + */ +typedef int (*bcmpkt_netif_destroy_f) (int unit, int netif_id); + +/*! + * \brief Network interface link state update function. + * + * Notify the network stack of a change in port link state. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [in] linkup Link state of the port bound on the Network interface. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_BADID Invalid network interface ID. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_netif_link_update_f) (int unit, int netif_id, bool linkup); + +/*! + * \brief Get the max number of network interface. + * + * \param [in] unit Switch unit number. + * \param [out] max_num Max number of network interface. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_netif_max_get_f) (int unit, int *max_num); + +/** + * \name KNET filter types. + * \anchor BCMPKT_FILTER_T_XXX + */ +/*! \{ */ +/*! Packet filter for RX direction. */ +#define BCMPKT_FILTER_T_RX_PKT 1 +/*! \} */ + +/** + * \name KNET filter flags. + * \anchor BCMPKT_FILTER_F_XXX + */ +/*! \{ */ +/*! Match any packet. */ +#define BCMPKT_FILTER_F_ANY_DATA 0x00000001 + +/*! Strip VLAN tag from packets sent to vitual network interfaces. */ +#define BCMPKT_FILTER_F_STRIP_TAG 0x00000002 + +/*! Match RX DMA channel. */ +#define BCMPKT_FILTER_F_MATCH_DMA_CHAN 0x00000004 +/*! \} */ + +/** + * \name KNET filter destination types. + * \anchor BCMPKT_DEST_T_XXX + */ +/*! \{ */ +/*! Null destination (drop packet). */ +#define BCMPKT_DEST_T_NULL 0 + +/*! Send packet to virtual network interface. */ +#define BCMPKT_DEST_T_NETIF 1 + +/*! Send packet to BCM Rx API. */ +#define BCMPKT_DEST_T_BCM_RX_API 2 + +/*! Send packet to kernel filter call-back function. */ +#define BCMPKT_DEST_T_CALLBACK 3 +/*! \} */ + +/** + * \name KNET filter match flags. + * \anchor BCMPKT_FILTER_M_XXX + */ +/*! \{ */ +/*! Match raw packet data */ +#define BCMPKT_FILTER_M_RAW 0x00000001 +/*! Match VLAN ID */ +#define BCMPKT_FILTER_M_VLAN 0x00000002 +/*! Match local ingress port */ +#define BCMPKT_FILTER_M_INGPORT 0x00000004 +/*! Match source module port */ +#define BCMPKT_FILTER_M_SRC_MODPORT 0x00000008 +/*! Match source module ID */ +#define BCMPKT_FILTER_M_SRC_MODID 0x00000010 +/*! Match copy-to-CPU reason code */ +#define BCMPKT_FILTER_M_REASON 0x00000020 +/*! Match filter processor rule number */ +#define BCMPKT_FILTER_M_FP_RULE 0x00000040 +/*! Match error bit */ +#define BCMPKT_FILTER_M_ERROR 0x00000080 +/*! Match CPU queue (rx queue) */ +#define BCMPKT_FILTER_M_CPU_QUEUE 0x00000100 +/*! + * Match raw meta data. When the flag is set, the other BCMPKT_FILTER_M_XXX + * flags are not allowed to be set together except BCMPKT_FILTER_M_RAW and + * BCMPKT_FILTER_M_ERROR. + */ +#define BCMPKT_FILTER_M_RAW_METADATA 0x00000200 +/*! \} */ + +/*! Filter description maximum size */ +#define BCMPKT_FILTER_DESC_MAX 32 + +/*! Packet raw data maximum size */ +#define BCMPKT_FILTER_SIZE_MAX 256 + +/*! + * Filter user data size in bytes. + */ +#define BCMPKT_FILTER_USER_DATA_SIZE 64 + +/*! \brief Packet filter structure. + */ +typedef struct bcmpkt_filter_s { + /*! Filter ID. */ + int id; + /*! Filter type. Refer to \ref BCMPKT_FILTER_T_XXX. */ + uint32_t type; + /*! Filter flags. Refer to \ref BCMPKT_FILTER_F_XXX. */ + uint32_t flags; + /*! Filter priority (0 is highest). */ + uint32_t priority; + /*! Destination type. Refer to \ref BCMPKT_DEST_T_XXX. */ + uint32_t dest_type; + /*! Filter destination ID. */ + int dest_id; + /*! + * If non-zero this value overrides the default protocol type when + * matching packet is passed to network stack. + */ + uint16_t dest_proto; + /*! Destination type. Refer to \ref BCMPKT_DEST_T_XXX. */ + uint32_t mirror_type; + /*! Mirror destination ID. */ + int mirror_id; + /*! + * If non-zero this value overrides the default protocol type when + * matching packet is passed to network stack. + */ + uint16_t mirror_proto; + + /*! + * Source RX DMA channel to match. \ref BCMPKT_FILTER_F_MATCH_DMA_CHAN + * is required to take effect. Otherwise, filter won't match RX DMA + * channel. + */ + int dma_chan; + + /*! Refer to \ref BCMPKT_FILTER_M_XXX. */ + uint32_t match_flags; + + /*! Filter description (optional) */ + char desc[BCMPKT_FILTER_DESC_MAX]; + /*! VLAN ID to match. */ + uint16_t m_vlan; + /*! Local ingress port to match. */ + int m_ingport; + /*! Source module port to match. */ + int m_src_modport; + /*! Source module ID to match. */ + int m_src_modid; + /*! Source CPU port queue to match. */ + int m_cpu_queue; + /*! Copy-to-CPU reason to match. */ + bcmpkt_rx_reasons_t m_reason; + /*! Copy-to-CPU flex reason to match. */ + bcmpkt_bitmap_t m_flex_reason; + /*! Filter processor rule to match. */ + uint32_t m_fp_rule; + /*! Size of valid raw data and mask. */ + uint32_t raw_size; + /*! Raw data to match. */ + uint8_t m_raw_data[BCMPKT_FILTER_SIZE_MAX]; + /*! Raw data mask for match. */ + uint8_t m_raw_mask[BCMPKT_FILTER_SIZE_MAX]; + /*! User data. */ + uint8_t user_data[BCMPKT_FILTER_USER_DATA_SIZE]; + /*! Raw metadata to match. */ + uint32_t m_raw_metadata[BCMPKT_RXPMD_SIZE_WORDS]; + /*! Raw metadata mask for match. */ + uint32_t m_raw_metadata_mask[BCMPKT_RXPMD_SIZE_WORDS]; +} bcmpkt_filter_t; + +/*! + * \brief Network filter traverse callback function type. + * + * \param [in] unit Switch unit number. + * \param [in] filter KNET filter handle. + * \param [in] cb_data Application-provided context for callback function. + * + * \retval SHR_E_NONE No Error. + * \retval SHR_E_FAIL Failed. + */ +typedef int (*bcmpkt_filter_traverse_cb_f) (int unit, + const bcmpkt_filter_t *filter, + void *cb_data); + +/*! + * \brief Network filter create function. + * + * This function is to be called for creating a new network filter. + * The filter may be used for dispatching matched packets to a specific + * destination, and/or mirror those to another destination, or drop those + * directly. + * + * The bcmpkt_filter_t.id is an output parameter. + * + * \param [in] unit Switch unit number. + * \param [in,out] filter KNET filter handle. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_filter_create_f) (int unit, bcmpkt_filter_t *filter); + +/*! + * \brief Network filter get function. + * + * \param [in] unit Switch unit number. + * \param [in] filter_id KNET filter ID. + * \param [out] filter KNET filter handle. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + * \retval SHR_E_NOT_FOUND Not found the entry. + */ +typedef int (*bcmpkt_filter_get_f) (int unit, int filter_id, + bcmpkt_filter_t *filter); + +/*! + * \brief Network filter traverse function. + * + * This function for traversing all network filter configuration. + * + * \param [in] unit Switch unit number. + * \param [in] cb_func KNET filter traverse callback function. + * \param [in] cb_data Application-provided context for callback function. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_filter_traverse_f) (int unit, + bcmpkt_filter_traverse_cb_f cb_func, + void *cb_data); + +/*! + * \brief Network filter destroy function. + * + * + * \param [in] unit Switch unit number. + * \param [in] filter_id KNET filter ID. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_filter_destroy_f) (int unit, int filter_id); + +/*! + * \brief Get the max number of filter. + * + * \param [in] unit Switch unit number. + * \param [out] max_num Max number of filter. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_filter_max_get_f) (int unit, int *max_num); + +/*! + * \brief Suspend or resume TX. + * + * \param [in] unit Switch unit number. + * \param [in] on True to suspend TX packets or false to resume. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_knet_tx_suspend_set_f) (int unit, bool on); + +/** + * \name OneSync PTP clock driver sub command. + * + * Sub commands are used to configure PHC driver and + * OneSync FW. + * + * \anchor BCMPKT_ONESYNC_XXX + */ +/*! \{ */ +/*! Initialize PHC driver. */ +#define BCMPKT_ONESYNC_HW_INIT 0 +/*! Clean up PHC driver. */ +#define BCMPKT_ONESYNC_HW_CLEANUP 1 +/*! \} */ + +/*! Maximum data from user. */ +#define BCMPKT_ONESYNC_USER_DATA_MAX 12 + +/*! Maximum IEEE1588 packet metadata. */ +#define BCMPKT_ONESYNC_IEEE1588_PKT_METADATA_MAX 72 + +/*! \brief OneSync PHC structure. + */ +typedef struct bcmpkt_onesync_s { + /*! Device Unit. */ + int unit; + /*! PCH Sub command. Refer BCMPKT_ONESYNC_XXX. */ + int sub_cmd; + /*! Data specific to sub command. */ + int32_t data[BCMPKT_ONESYNC_USER_DATA_MAX]; +} bcmpkt_onesync_t; + +/*! + * \brief OneSync configuration. + * + * \param [in] unit Switch unit number. + * \param [in] cfg Configuration information. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_FAIL Access driver failed. + */ +typedef int (*bcmpkt_onesync_cfg_f) (int unit, bcmpkt_onesync_t *cfg); + +/*! + * \brief Network interface operation vector. + */ +typedef struct bcmpkt_netif_ops_s { + + /*! Create a netif. */ + bcmpkt_netif_create_f create; + + /*! Get a netif's configuration. */ + bcmpkt_netif_get_f get; + + /*! Traverse netifs. */ + bcmpkt_netif_traverse_f traverse; + + /*! Destroy a netif. */ + bcmpkt_netif_destroy_f destroy; + + /*! Port link update of the netif. */ + bcmpkt_netif_link_update_f link_update; + + /*! Get max number of network interface. */ + bcmpkt_netif_max_get_f netif_max_get; +} bcmpkt_netif_ops_t; + +/*! + * \brief KNET filter operation vector. + */ +typedef struct bcmpkt_filter_ops_s { + + /*! Create a filter. */ + bcmpkt_filter_create_f create; + + /*! Get a filter configuration. */ + bcmpkt_filter_get_f get; + + /*! Traverse filter configurations. */ + bcmpkt_filter_traverse_f traverse; + + /*! Destroy a filter. */ + bcmpkt_filter_destroy_f destroy; + + /*! Get max number of filter. */ + bcmpkt_filter_max_get_f filter_max_get; +} bcmpkt_filter_ops_t; + +/*! + * \brief KNET vector. + */ +typedef struct bcmpkt_knet_s { + /*! initialized flag: 0 - uninitialized 1 - initialized. */ + int initialized; + + /*! KNET driver name, such as "KNET". */ + char driver_name[128]; + + /*! Netif operations vector. */ + bcmpkt_netif_ops_t netif_ops; + + /*! KNET filter operations vector. */ + bcmpkt_filter_ops_t filter_ops; + + /*! KNET TX suspend. */ + bcmpkt_knet_tx_suspend_set_f tx_suspend_set; + + /*! Broadcom OneSync configuration. */ + bcmpkt_onesync_cfg_f onesync_cfg; + +} bcmpkt_knet_t; + +/*! + * \brief Register KNET operations. + * + * Enable KNET operations. + * + * \param [in] knet_drv KNET vectors. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_CONFIG Invalid driver. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_knet_drv_register(bcmpkt_knet_t *knet_drv); + +/*! + * \brief Unregister KNET driver. + * + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_BUSY The driver is in using. + */ +extern int +bcmpkt_knet_drv_unregister(void); + +/*! + * \brief Network interface create function. + * + * This function is used for creating a new network interface. + * + * The bcmpkt_netif_t.id is an output parameter. + * + * \param [in] unit Switch unit number. + * \param [in,out] netif Network interface handle. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameter failed. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_netif_create(int unit, bcmpkt_netif_t *netif); + +/*! + * \brief Network interface get function. + * + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [out] netif Network interface handle. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_BADID Invalid network interface ID. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + * \retval SHR_E_NOT_FOUND Not found the entry. + */ +extern int +bcmpkt_netif_get(int unit, int netif_id, bcmpkt_netif_t *netif); + +/*! + * \brief Network interface traverse function. + * + * This function is for traversing all network interfaces' configuration. + * The callback function will be called for each present netif. Refer to + * \ref bcmpkt_netif_traverse_cb_f for callback function type. + * + * \param [in] unit Switch unit number. + * \param [in] cb_func Network interface traverse callback function. + * \param [in] cb_data Application-provided context for callback function. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_netif_traverse(int unit, bcmpkt_netif_traverse_cb_f cb_func, + void *cb_data); + +/*! + * \brief Network destroy function. + * + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_BADID Invalid network interface ID. + * \retval SHR_E_FAIL Access driver failed. + * \retval SHR_E_RESOURCE Not allowed to destroy a UNET netif. + */ +extern int +bcmpkt_netif_destroy(int unit, int netif_id); + +/*! + * \brief Network interface link state update function. + * + * Notify the network stack of a change in port link state. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [in] linkup Link state of the port bound on the Network interface. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_BADID Invalid network interface ID. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_netif_link_update(int unit, int netif_id, bool linkup); + +/*! + * \brief Get the max number of network interface. + * + * \param [in] unit Switch unit number. + * \param [out] max_num Max number of network interface. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_netif_max_get(int unit, int *max_num); + +/*! + * \brief Network filter create function. + * + * This function is to be called for creating a new network filter. + * The filter may be used for dispatching matched packets to a specific + * destination, and/or mirror those to another destination, or drop those + * directly. + * + * The bcmpkt_filter_t.id is an output parameter. + * + * \param [in] unit Switch unit number. + * \param [in,out] filter KNET filter handle. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_filter_create(int unit, bcmpkt_filter_t *filter); + +/*! + * \brief Network filter get function. + * + * + * \param [in] unit Switch unit number. + * \param [in] filter_id KNET filter ID. + * \param [out] filter KNET filter handle. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + * \retval SHR_E_NOT_FOUND Not found the entry. + */ +extern int +bcmpkt_filter_get(int unit, int filter_id, bcmpkt_filter_t *filter); + +/*! + * \brief Network filter traverse function. + * + * This function for traversing all network filter configuration. + * + * \param [in] unit Switch unit number. + * \param [in] cb_func KNET filter traverse callback function. + * \param [in] cb_data Application-provided context for callback function. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_filter_traverse(int unit, bcmpkt_filter_traverse_cb_f cb_func, + void *cb_data); + +/*! + * \brief Network filter destroy function. + * + * + * \param [in] unit Switch unit number. + * \param [in] filter_id KNET filter ID. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_filter_destroy(int unit, int filter_id); + +/*! + * \brief Get the max number of filter. + * + * \param [in] unit Switch unit number. + * \param [out] max_num Max number of filter. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit number. + * \retval SHR_E_CONFIG Network device was not initialized. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_filter_max_get(int unit, int *max_num); + +/*! + * \brief PHC initialize function. + * + * This function is to be called for initilizing the PTP clock driver. + * The PHC releated sub command in dispatched from KNET driver. + * + * \param [in] unit Switch unit number. + * \param [in] cfg sub command information. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_FAIL Access driver failed. + * \retval SHR_E_RESOURCE FW is not initialized. + */ +extern int +bcmpkt_onesync_init(int unit, bcmpkt_onesync_t *cfg); + +/*! + * \brief PHC clean up function. + * + * This function is to be called for deinitilizing the PTP clock driver. + * The PHC releated sub command in dispatched from KNET driver. + * + * \param [in] unit Switch unit number. + * \param [in] cfg sub command information. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_FAIL Access driver failed. + * \retval SHR_E_CONFIG Network device was not initialized. + */ +extern int +bcmpkt_onesync_cleanup(int unit, bcmpkt_onesync_t *cfg); + +#endif /* BCMPKT_KNET_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr.h new file mode 100644 index 0000000..a640c33 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr.h @@ -0,0 +1,156 @@ +/*! \file bcmpkt_lbhdr.h + * + * Loopback header (LBHDR, called LOOPBACK_MH in hardware) access interface. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_LBHDR_H +#define BCMPKT_LBHDR_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#include +#endif +#include +#include +#include + +/*! TX Packet MetaData size (bytes). */ +#define BCMPKT_LBHDR_SIZE_BYTES 16 +/*! TX Packet MetaData size (words). */ +#define BCMPKT_LBHDR_SIZE_WORDS 4 + +/*! + * \name LBHDR Dump flags. (deprecated by BCMPKT_DUMP_F_XXX) + * \anchor BCMPKT_LBHDR_DUMP_F_XXX + */ +/*! \{ */ +/*! + * Dump all fields contents. + */ +#define BCMPKT_LBHDR_DUMP_F_ALL 0 +/*! + * Dump non-zero field content only. + */ +#define BCMPKT_LBHDR_DUMP_F_NONE_ZERO 1 +/*! \} */ + +/*! + * \name BCMPKT_LBHDR_START encodings. + * \anchor BCMPKT_LBHDR_START_XXX + */ +/*! \{ */ +/*! + * Loopback header start of frame indicator's value. + */ +#define BCMPKT_LBHDR_START_IND 251 +/*! \} */ + +/*! \brief LBHDR field ID supported bit array. + * Array of bits indicating whether a LBHDR field ID is supported by a given + * device type. + */ +typedef struct bcmpkt_lbhdr_fid_support_s { + /*! Field ID bitmap container */ + SHR_BITDCLNAME(fbits, BCMPKT_LBHDR_FID_COUNT); +} bcmpkt_lbhdr_fid_support_t; + +/*! + * \name Utility macros for \ref bcmpkt_lbhdr_fid_support_t. + * \anchor BCMPKT_LBHDR_SUPPORT_OPS + */ +/*! \{ */ +/*! + * Macro to get a field ID's supported status. + * + * \retval zero Not supported + * \retval non-zero Supported + */ +#define BCMPKT_LBHDR_FID_SUPPORT_GET(_support, _fid) \ + SHR_BITGET(((_support).fbits), (_fid)) + +/*! + * Iterate over all supported LBHDR field IDs in the \c _support. + */ +#define BCMPKT_LBHDR_FID_SUPPORT_ITER(_support, _fid) \ + for(_fid = 0; _fid < BCMPKT_LBHDR_FID_COUNT; _fid++) \ + if(BCMPKT_LBHDR_FID_SUPPORT_GET(_support, _fid)) +/*! \} */ + +/*! + * \brief Get field name for a given LBHDR field ID. + * + * \param [in] fid LBHDR field ID, refer to \ref BCMPKT_LBHDR_XXX. + * \param [out] name LBHDR field name string. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_lbhdr_field_name_get(int fid, char **name); + +/*! + * \brief Get field ID for a given LBHDR field name. + * + * \param [in] name LBHDR field name string. + * \param [out] fid LBHDR Field ID. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_NOT_FOUND Not found the name. + */ +extern int +bcmpkt_lbhdr_field_id_get(char* name, int *fid); + +/*! + * \brief Get supported LBHDR field IDs for a given device type. + * + * This function returns a structure with information about the LBHDR field IDs + * a given device type supports. + * + * Use \ref BCMPKT_LBHDR_FID_SUPPORT_GET on the returned structure to get the + * supported status of a specific field ID. + * + * \param [in] dev_type Device type. + * \param [out] support Field ID supported status bitmap. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_INTERNAL API internal error. + */ +extern int +bcmpkt_lbhdr_fid_support_get(bcmdrd_dev_type_t dev_type, + bcmpkt_lbhdr_fid_support_t *support); + +#endif /* BCMPKT_LBHDR_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr_defs.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr_defs.h new file mode 100644 index 0000000..577b1d6 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr_defs.h @@ -0,0 +1,381 @@ +#ifndef BCMPKT_LBHDR_DEFS_H +#define BCMPKT_LBHDR_DEFS_H +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * Tool: INTERNAL/regs/xgs/generate-pmd.pl + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides field macros for the Packet Loopback HeaDeR (LBHDR, called + * LOOPBACK_MH in hardware.) access. + * + ******************************************************************************/ + +/*! + * \name Loopback module header field IDs. + * \anchor BCMPKT_LBHDR_XXX + */ +/*! \{ */ +/*! Invalid BCMPKT_LBHDR FID indicator */ +#define BCMPKT_LBHDR_FID_INVALID -1 +/*! Start of frame indicator. */ +#define BCMPKT_LBHDR_START 0 +/*! + * 64 Header Types Supported. 1 means Packets from CPU with SOBMH header format + * to Passthru NLF + */ +#define BCMPKT_LBHDR_HEADER_TYPE 1 +/*! + * Indicates the loopback COS queue and is used by the MMU for per + * application group accounting for packets received from the internal + * loopback port. This must be put the PBI.INPUT_PRIORITY whenever the + * source port is the loopback port. + */ +#define BCMPKT_LBHDR_INPUT_PRIORITY 2 +/*! Pointer to CPU_PACKET_PROFILE_1/2 registers. */ +#define BCMPKT_LBHDR_PKT_PROFILE 3 +/*! Triggers capture of intermediate packet processing result of this packet. */ +#define BCMPKT_LBHDR_VISIBILITY_PKT 4 +/*! + * Source field for the packet. + * Contents of this field are determined by value of SOURCE_TYPE. + * SOURCE_TYPE=0x0: + * [15:0] SOURCE_VP + * SOURCE_TYPE=0x1: + * [15:8] SRC_MODID + * [7:0] SRC_PORT + */ +#define BCMPKT_LBHDR_SOURCE 5 +/*! Indicates contents of SOURCE field. 0x1: SGPP 0x0: SVP. */ +#define BCMPKT_LBHDR_SOURCE_TYPE 6 +/*! CNG Bits */ +#define BCMPKT_LBHDR_TRILL_AC_CNG 7 +/*! Traffic class */ +#define BCMPKT_LBHDR_TRILL_AC_TC 8 +/*! Do Not Learn Bit */ +#define BCMPKT_LBHDR_TRILL_AC_DO_NOT_LEARN 9 +/*! CNG Bits */ +#define BCMPKT_LBHDR_TRILL_NW_CNG 10 +/*! Traffic class */ +#define BCMPKT_LBHDR_TRILL_NW_TC 11 +/*! Destination type (see encodings). Valid only if SUBFLOW_TYPE=CPU_TX_PROC. */ +#define BCMPKT_LBHDR_ETH_DEST_TYPE 12 +/*! + * Destination based on DESTINATION_TYPE. (For ECMP/ECMP_MEMBER cases, this field + * contains ECMP_GROUP_PTR). Valid only if SUBFLOW_TYPE=CPU_TX_PROC. + */ +#define BCMPKT_LBHDR_ETH_DEST 13 +/*! Drop precedence for the apcket. Valid only if SUBFLOW_TYPE=CPU_TX_PROC. */ +#define BCMPKT_LBHDR_ETH_DP 14 +/*! + * ECMP member ID for case where DESTINATION_TYPE=ECMP_MEMBER. Only valid for single + * level ECMP. Valid only if SUBFLOW_TYPE=CPU_TX_PROC. + */ +#define BCMPKT_LBHDR_ETH_ECMP_MEMBER_ID 15 +/*! + * Internal Congestion to be used for the packet. Valid only if + * SUBFLOW_TYPE=CPU_TX_PROC. + */ +#define BCMPKT_LBHDR_ETH_INT_CN 16 +/*! + * Internal priority to be used for the packet. Valid only if + * SUBFLOW_TYPE=CPU_TX_PROC. + */ +#define BCMPKT_LBHDR_ETH_INT_PRI 17 +/*! + * Allows software to select load balancing bitmap for non-unicast packets. + * valid only if MCAST_LB_INDEX_VLD=1. + */ +#define BCMPKT_LBHDR_ETH_MCAST_LB_INDEX 18 +/*! If set, MCAST_LB_INDEX field is valid. */ +#define BCMPKT_LBHDR_ETH_MCAST_LB_INDEX_VLD 19 +/*! + * Device Port Number which is to be used for processing packet in Ingress + * Pipeline. + */ +#define BCMPKT_LBHDR_ETH_PP_PORT 20 +/*! + * If set, the qos fields (INT, PRI, etc) are specified in the header and + * override the pre-IFP assignment. Else, derived based on packet lookups. + * Valid only if SUBFLOW_TYPE=CPU_TX_PROC. + */ +#define BCMPKT_LBHDR_ETH_QOS_FIELDS_VLD 21 +/*! + * Indicates whether packets should be treated as routed or bridged. Valid + * only if SUBFLOW_TYPE=CPU_TX_PROC. + */ +#define BCMPKT_LBHDR_ETH_ROUTED_PKT 22 +/*! Identifies sub-flow (see encodings). */ +#define BCMPKT_LBHDR_ETH_SUBFLOW_TYPE 23 +/*! VRF */ +#define BCMPKT_LBHDR_ETHERNET_VRF 24 +/*! VRF valid */ +#define BCMPKT_LBHDR_ETHERNET_VRF_VALID 25 +/*! MUST Always be 0 */ +#define BCMPKT_LBHDR_ZERO 26 +/*! + * Device Port Number which is to be used for processing packet in Ingress + * Pipeline. + */ +#define BCMPKT_LBHDR_PP_PORT 27 +/*! + * Indicates whether packets should be treated as routed or bridged. Valid + * only if SUBFLOW_TYPE=CPU_TX_PROC. + */ +#define BCMPKT_LBHDR_ROUTED_PKT 28 +/*! VRF */ +#define BCMPKT_LBHDR_VRF 29 +/*! VRF valid */ +#define BCMPKT_LBHDR_VRF_VALID 30 +/*! Qos field valid */ +#define BCMPKT_LBHDR_QOS_FIELD_VALID 31 +/*! Opaque object */ +#define BCMPKT_LBHDR_OPAQUE_OBJECT 32 +/*! Qos field ethernet */ +#define BCMPKT_LBHDR_QOS_FIELD_ETH 33 +/*! Internal priority ethernet */ +#define BCMPKT_LBHDR_INT_PRI_ETH 34 +/*! Internal CN ethernet */ +#define BCMPKT_LBHDR_INT_CN_ETH 35 +/*! CNG ethernet */ +#define BCMPKT_LBHDR_CNG_ETH 36 +/*! */ +#define BCMPKT_LBHDR_PKT_PROFILE_MD_ETH 37 +/*! */ +#define BCMPKT_LBHDR_QOS_FIELD_VALID_MD_ETH 38 +/*! */ +#define BCMPKT_LBHDR_PP_PORT_MD_ETH 39 +/*! */ +#define BCMPKT_LBHDR_DESTINATION_MD_ETH 40 +/*! */ +#define BCMPKT_LBHDR_SVTAG_TX_PRESENT_MD_ETH 41 +/*! */ +#define BCMPKT_LBHDR_EXTENDED_DELETE_ENABLE_MD_ETH 42 +/*! */ +#define BCMPKT_LBHDR_EXTENDED_DELETE_BYTE_COUNT_MD_ETH 43 +/*! */ +#define BCMPKT_LBHDR_IFA_AT_OUTER_LAYER_MD_ETH 44 +/*! */ +#define BCMPKT_LBHDR_OPAQUE_OBJECT_MD_ETH 45 +/*! */ +#define BCMPKT_LBHDR_QOS_FIELD_ETH_MD_ETH 46 +/*! */ +#define BCMPKT_LBHDR_INPUT_PRIORITY_MD_ETH 47 +/*! */ +#define BCMPKT_LBHDR_CNP 48 +/*! */ +#define BCMPKT_LBHDR_FLIP_SECOND_PASS_L2_DENSE_MODE_ADDRESS 49 +/*! */ +#define BCMPKT_LBHDR_VFI_VALID_MD_ETH 50 +/*! */ +#define BCMPKT_LBHDR_VFI_MD_ETH 51 +/*! */ +#define BCMPKT_LBHDR_TRUNCATE_MD_ETH 52 +/*! */ +#define BCMPKT_LBHDR_TRUNCATE_OFFSET_MD_ETH 53 +/*! */ +#define BCMPKT_LBHDR_SVP_MD_ETH 54 +/*! */ +#define BCMPKT_LBHDR_CNP_OR_CNM_MD_ETH 55 +/*! */ +#define BCMPKT_LBHDR_COPY_PRIORITY_MD_ETH 56 +/*! LBHDR FIELD ID NUMBER */ +#define BCMPKT_LBHDR_FID_COUNT 57 +/*! \} */ + +/*! LBHDR field name strings for debugging. */ +#define BCMPKT_LBHDR_FIELD_NAME_MAP_INIT \ + {"START", BCMPKT_LBHDR_START},\ + {"HEADER_TYPE", BCMPKT_LBHDR_HEADER_TYPE},\ + {"INPUT_PRIORITY", BCMPKT_LBHDR_INPUT_PRIORITY},\ + {"PKT_PROFILE", BCMPKT_LBHDR_PKT_PROFILE},\ + {"VISIBILITY_PKT", BCMPKT_LBHDR_VISIBILITY_PKT},\ + {"SOURCE", BCMPKT_LBHDR_SOURCE},\ + {"SOURCE_TYPE", BCMPKT_LBHDR_SOURCE_TYPE},\ + {"TRILL_AC::CNG", BCMPKT_LBHDR_TRILL_AC_CNG},\ + {"TRILL_AC::TC", BCMPKT_LBHDR_TRILL_AC_TC},\ + {"TRILL_AC::DO_NOT_LEARN", BCMPKT_LBHDR_TRILL_AC_DO_NOT_LEARN},\ + {"TRILL_NW::CNG", BCMPKT_LBHDR_TRILL_NW_CNG},\ + {"TRILL_NW::TC", BCMPKT_LBHDR_TRILL_NW_TC},\ + {"ETH::DEST_TYPE", BCMPKT_LBHDR_ETH_DEST_TYPE},\ + {"ETH::DEST", BCMPKT_LBHDR_ETH_DEST},\ + {"ETH::DP", BCMPKT_LBHDR_ETH_DP},\ + {"ETH::ECMP_MEMBER_ID", BCMPKT_LBHDR_ETH_ECMP_MEMBER_ID},\ + {"ETH::INT_CN", BCMPKT_LBHDR_ETH_INT_CN},\ + {"ETH::INT_PRI", BCMPKT_LBHDR_ETH_INT_PRI},\ + {"ETH::MCAST_LB_INDEX", BCMPKT_LBHDR_ETH_MCAST_LB_INDEX},\ + {"ETH::MCAST_LB_INDEX_VLD", BCMPKT_LBHDR_ETH_MCAST_LB_INDEX_VLD},\ + {"ETH::PP_PORT", BCMPKT_LBHDR_ETH_PP_PORT},\ + {"ETH::QOS_FIELDS_VLD", BCMPKT_LBHDR_ETH_QOS_FIELDS_VLD},\ + {"ETH::ROUTED_PKT", BCMPKT_LBHDR_ETH_ROUTED_PKT},\ + {"ETH::SUBFLOW_TYPE", BCMPKT_LBHDR_ETH_SUBFLOW_TYPE},\ + {"ETHERNET::VRF", BCMPKT_LBHDR_ETHERNET_VRF},\ + {"ETHERNET::VRF_VALID", BCMPKT_LBHDR_ETHERNET_VRF_VALID},\ + {"ZERO", BCMPKT_LBHDR_ZERO},\ + {"PP_PORT", BCMPKT_LBHDR_PP_PORT},\ + {"ROUTED_PKT", BCMPKT_LBHDR_ROUTED_PKT},\ + {"VRF", BCMPKT_LBHDR_VRF},\ + {"VRF_VALID", BCMPKT_LBHDR_VRF_VALID},\ + {"QOS_FIELD_VALID", BCMPKT_LBHDR_QOS_FIELD_VALID},\ + {"OPAQUE_OBJECT", BCMPKT_LBHDR_OPAQUE_OBJECT},\ + {"QOS_FIELD_ETH", BCMPKT_LBHDR_QOS_FIELD_ETH},\ + {"INT_PRI_ETH", BCMPKT_LBHDR_INT_PRI_ETH},\ + {"INT_CN_ETH", BCMPKT_LBHDR_INT_CN_ETH},\ + {"CNG_ETH", BCMPKT_LBHDR_CNG_ETH},\ + {"PKT_PROFILE_MD_ETH", BCMPKT_LBHDR_PKT_PROFILE_MD_ETH},\ + {"QOS_FIELD_VALID_MD_ETH", BCMPKT_LBHDR_QOS_FIELD_VALID_MD_ETH},\ + {"PP_PORT_MD_ETH", BCMPKT_LBHDR_PP_PORT_MD_ETH},\ + {"DESTINATION_MD_ETH", BCMPKT_LBHDR_DESTINATION_MD_ETH},\ + {"SVTAG_TX_PRESENT_MD_ETH", BCMPKT_LBHDR_SVTAG_TX_PRESENT_MD_ETH},\ + {"EXTENDED_DELETE_ENABLE_MD_ETH", BCMPKT_LBHDR_EXTENDED_DELETE_ENABLE_MD_ETH},\ + {"EXTENDED_DELETE_BYTE_COUNT_MD_ETH", BCMPKT_LBHDR_EXTENDED_DELETE_BYTE_COUNT_MD_ETH},\ + {"IFA_AT_OUTER_LAYER_MD_ETH", BCMPKT_LBHDR_IFA_AT_OUTER_LAYER_MD_ETH},\ + {"OPAQUE_OBJECT_MD_ETH", BCMPKT_LBHDR_OPAQUE_OBJECT_MD_ETH},\ + {"QOS_FIELD_ETH_MD_ETH", BCMPKT_LBHDR_QOS_FIELD_ETH_MD_ETH},\ + {"INPUT_PRIORITY_MD_ETH", BCMPKT_LBHDR_INPUT_PRIORITY_MD_ETH},\ + {"CNP", BCMPKT_LBHDR_CNP},\ + {"FLIP_SECOND_PASS_L2_DENSE_MODE_ADDRESS", BCMPKT_LBHDR_FLIP_SECOND_PASS_L2_DENSE_MODE_ADDRESS},\ + {"VFI_VALID_MD_ETH", BCMPKT_LBHDR_VFI_VALID_MD_ETH},\ + {"VFI_MD_ETH", BCMPKT_LBHDR_VFI_MD_ETH},\ + {"TRUNCATE_MD_ETH", BCMPKT_LBHDR_TRUNCATE_MD_ETH},\ + {"TRUNCATE_OFFSET_MD_ETH", BCMPKT_LBHDR_TRUNCATE_OFFSET_MD_ETH},\ + {"SVP_MD_ETH", BCMPKT_LBHDR_SVP_MD_ETH},\ + {"CNP_OR_CNM_MD_ETH", BCMPKT_LBHDR_CNP_OR_CNM_MD_ETH},\ + {"COPY_PRIORITY_MD_ETH", BCMPKT_LBHDR_COPY_PRIORITY_MD_ETH},\ + {"fid count", BCMPKT_LBHDR_FID_COUNT} + +/*! + * \name BCMPKT_LBHDR_HEADER_TYPE encodings. + * \anchor BCMPKT_LBHDR_HEADER_TYPE_XXX + */ +/*! \{ */ +/*! MinM, L2GRE and VXLAN tunnel terminated packet */ +#define BCMPKT_LBHDR_HEADER_T_TUNNEL_TERM 0 +/*! Trill Network Packets to Passthru NLF */ +#define BCMPKT_LBHDR_HEADER_T_TRILL_NW 1 +/*! Trill Access Layer Packets to Passthru NLF */ +#define BCMPKT_LBHDR_HEADER_T_TRILL_AC 2 +/*! Process as if it was received on front panel port. */ +#define BCMPKT_LBHDR_HEADER_T_ETHERNET 3 +/*! MAC in MAC packets to Passthru NLF */ +#define BCMPKT_LBHDR_HEADER_T_MIM 4 +/*! QCN Packets to Passthru NLF */ +#define BCMPKT_LBHDR_HEADER_T_QCN 5 +/*! Generic loopback */ +#define BCMPKT_LBHDR_HEADER_T_GENERIC 6 +/*! LB Hdr type ETH */ +#define BCMPKT_LBHDR_HEADER_T_LOOPBACK_MH 7 +/*! Transport header */ +#define BCMPKT_LBHDR_HEADER_T_TRANSPORT 7 +/*! \} */ + +/*! BCMPKT_LBHDR_HEADER_TYPE encoding name strings for debugging. */ +#define BCMPKT_LBHDR_HEADER_TYPE_NAME_MAP_INIT \ + {"TUNNEL_TERM", BCMPKT_LBHDR_HEADER_T_TUNNEL_TERM},\ + {"TRILL_NW", BCMPKT_LBHDR_HEADER_T_TRILL_NW},\ + {"TRILL_AC", BCMPKT_LBHDR_HEADER_T_TRILL_AC},\ + {"ETHERNET", BCMPKT_LBHDR_HEADER_T_ETHERNET},\ + {"MIM", BCMPKT_LBHDR_HEADER_T_MIM},\ + {"QCN", BCMPKT_LBHDR_HEADER_T_QCN},\ + {"GENERIC", BCMPKT_LBHDR_HEADER_T_GENERIC},\ + {"LOOPBACK_MH", BCMPKT_LBHDR_HEADER_T_LOOPBACK_MH},\ + {"TRANSPORT", BCMPKT_LBHDR_HEADER_T_TRANSPORT},\ + +/*! + * \name BCMPKT_LBHDR_ETH_DEST_TYPE encodings. + * \anchor BCMPKT_LBHDR_ETH_DEST_TYPE_XXX + */ +/*! \{ */ +/*! + * Destination GLP. Note that despite the name, only physical ports (DGPP) + * are supported. Trunking is not supported. + */ +#define BCMPKT_LBHDR_ETH_DEST_T_DGLP 0 +/*! Next hop */ +#define BCMPKT_LBHDR_ETH_DEST_T_NHI 1 +/*! ECMP group */ +#define BCMPKT_LBHDR_ETH_DEST_T_ECMP 2 +/*! ECMP member */ +#define BCMPKT_LBHDR_ETH_DEST_T_ECMP_MEMBER 3 +/*! IPMC */ +#define BCMPKT_LBHDR_ETH_DEST_T_IPMC 4 +/*! L2MC */ +#define BCMPKT_LBHDR_ETH_DEST_T_L2MC 5 +/*! Vlan flooding */ +#define BCMPKT_LBHDR_ETH_DEST_T_VLAN_FLOOD 6 +/*! \} */ + +/*! BCMPKT_LBHDR_ETH_DEST_TYPE encoding name strings for debugging. */ +#define BCMPKT_LBHDR_ETH_DEST_TYPE_NAME_MAP_INIT \ + {"DGLP", BCMPKT_LBHDR_ETH_DEST_T_DGLP},\ + {"NHI", BCMPKT_LBHDR_ETH_DEST_T_NHI},\ + {"ECMP", BCMPKT_LBHDR_ETH_DEST_T_ECMP},\ + {"ECMP_MEMBER", BCMPKT_LBHDR_ETH_DEST_T_ECMP_MEMBER},\ + {"IPMC", BCMPKT_LBHDR_ETH_DEST_T_IPMC},\ + {"L2MC", BCMPKT_LBHDR_ETH_DEST_T_L2MC},\ + {"VLAN_FLOOD", BCMPKT_LBHDR_ETH_DEST_T_VLAN_FLOOD},\ + +/*! + * \name BCMPKT_LBHDR_ETH_SUBFLOW_TYPE encodings. + * \anchor BCMPKT_LBHDR_ETH_SUBFLOW_TYPE_XXX + */ +/*! \{ */ +/*! CPU masquerade flow */ +#define BCMPKT_LBHDR_ETH_SUBFLOW_T_CPU_MASQUERADE 0 +/*! CPU_TX_PROC */ +#define BCMPKT_LBHDR_ETH_SUBFLOW_T_CPU_TX_PROC 1 +/*! \} */ + +/*! BCMPKT_LBHDR_ETH_SUBFLOW_TYPE encoding name strings for debugging. */ +#define BCMPKT_LBHDR_ETH_SUBFLOW_TYPE_NAME_MAP_INIT \ + {"CPU_MASQUERADE", BCMPKT_LBHDR_ETH_SUBFLOW_T_CPU_MASQUERADE},\ + {"CPU_TX_PROC", BCMPKT_LBHDR_ETH_SUBFLOW_T_CPU_TX_PROC},\ + +/*! + * \name Loopback module header internal usage field IDs. + * \anchor BCMPKT_LBHDR_I_XXX + */ +/*! \{ */ +/*! Invalid BCMPKT_LBHDR_I FID indicator */ +#define BCMPKT_LBHDR_I_FID_INVALID -1 +/*! LBHDR RX raw data size. */ +#define BCMPKT_LBHDR_I_SIZE 0 +/*! LBHDR_I FIELD ID NUMBER */ +#define BCMPKT_LBHDR_I_FID_COUNT 1 +/*! \} */ + +/*! LBHDR_I field name strings for debugging. */ +#define BCMPKT_LBHDR_I_FIELD_NAME_MAP_INIT \ + {"SIZE", BCMPKT_LBHDR_I_SIZE},\ + {"fid count", BCMPKT_LBHDR_I_FID_COUNT} + +#endif /*! BCMPKT_LBHDR_DEFS_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr_field.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr_field.h new file mode 100644 index 0000000..0add4c3 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr_field.h @@ -0,0 +1,72 @@ +/*! \file bcmpkt_lbhdr_field.h + * + * Loopback header (LBHDR, LOOPBACK_MH in hardware) field access interface. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_LBHDR_FIELD_H +#define BCMPKT_LBHDR_FIELD_H + +/*! + * \brief Get value from a LBHDR field. + * + * \param [in] dev_type Device type. + * \param [in] lbhdr LBHDR handle. + * \param [in] fid LBHDR field ID, refer to \ref BCMPKT_LBHDR_XXX. + * \param [out] val Field value. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support the field. + */ +extern int +bcmpkt_lbhdr_field_get(bcmdrd_dev_type_t dev_type, uint32_t *lbhdr, + int fid, uint32_t *val); + +/*! + * \brief Set value into a LBHDR field. + * + * \param [in] dev_type Device type. + * \param [in,out] lbhdr LBHDR handle. + * \param [in] fid LBHDR field ID, refer to \ref BCMPKT_LBHDR_XXX. + * \param [in] val Set value. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support the field. + */ +extern int +bcmpkt_lbhdr_field_set(bcmdrd_dev_type_t dev_type, uint32_t *lbhdr, + int fid, uint32_t val); + +#endif /* BCMPKT_LBHDR_FIELD_H */ + diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr_internal.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr_internal.h new file mode 100644 index 0000000..ef96b9e --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_lbhdr_internal.h @@ -0,0 +1,80 @@ +/*! \file bcmpkt_lbhdr_internal.h + * + * Loopback header (LBHDR, called LOOPBACK_MH in hardware) access interface + * (Internal use only). + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_LBHDR_INTERNAL_H +#define BCMPKT_LBHDR_INTERNAL_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif +#include +#include +#include + +/*! + * Array of LBHDR field getter functions for a particular device + * type. + */ +typedef struct bcmpkt_lbhdr_fget_s { + bcmpkt_field_get_f fget[BCMPKT_LBHDR_FID_COUNT]; +} bcmpkt_lbhdr_fget_t; + +/*! + * Array of LBHDR field setter functions for a particular device + * type. These functions are used for internally configuring packet + * filter. + */ +typedef struct bcmpkt_lbhdr_fset_s { + bcmpkt_field_set_f fset[BCMPKT_LBHDR_FID_COUNT]; +} bcmpkt_lbhdr_fset_t; + +/*! + * Array of LBHDR field address and length getter functions for a multiple + * words field of a particular device type. *addr is output address and return + * length. + */ +typedef struct bcmpkt_lbhdr_figet_s { + bcmpkt_ifield_get_f fget[BCMPKT_LBHDR_I_FID_COUNT]; +} bcmpkt_lbhdr_figet_t; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern void _bd##_lbhdr_view_info_get(bcmpkt_pmd_view_info_t *info); +#define BCMDRD_DEVLIST_OVERRIDE +#include + +#endif /* BCMPKT_LBHDR_INTERNAL_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_mhdr_defs.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_mhdr_defs.h new file mode 100644 index 0000000..e068dea --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_mhdr_defs.h @@ -0,0 +1,184 @@ +#ifndef BCMPKT_MHDR_DEFS_H +#define BCMPKT_MHDR_DEFS_H +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * Tool: INTERNAL/regs/xgs/generate-chip.pl + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides access macros for the module header included + * in packet send to CPU. + * + ******************************************************************************/ + +#include + +/******************************************************************************* + * + * MHDR DEFINITIONS BEGIN HERE + * + ******************************************************************************/ + + +/* Start of module header packet indicators */ +#define BCMPKT_MHDR_SOF 0xfb + + +/* Module header size (in bytes) */ +#define BCMPKT_MHDR_SIZE 16 + + +/* Module header size (in words) */ +#define BCMPKT_MHDR_WSIZE 4 + + +/******************************************************************************* + * SWFORMAT: MHDR + * BLOCKS: + * SIZE: 128 + ******************************************************************************/ +#define MHDR_OFFSET 0x00000000 + +#define MHDR_BLKACC () + +#define MHDR_SIZE 16 + +/* + * This structure should be used to declare and program MHDR. + * + */ +typedef union MHDR_s { + uint32_t v[4]; + uint32_t mhdr[4]; + uint32_t _mhdr; +} MHDR_t; + +#define MHDR_CLR(r) sal_memset(&((r).mhdr[0]), 0, sizeof(MHDR_t)) +#define MHDR_SET(r,i,d) (r).mhdr[i] = d +#define MHDR_GET(r,i) (r).mhdr[i] + +/* + * These macros can be used to access individual fields. + * + */ +#define MHDR_PPD_DATAf_GET(r,a) bcmdrd_field_be_get((r).mhdr,4,0,63,a) +#define MHDR_PPD_DATAf_SET(r,a) bcmdrd_field_be_set((r).mhdr,4,0,63,a) +#define MHDR_PPD0_MH_OPCODEf_GET(r) ((((r).mhdr[3]) >> 8) & 0x7) +#define MHDR_PPD0_MH_OPCODEf_SET(r,f) (r).mhdr[3]=(((r).mhdr[3] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) +#define MHDR_PPD0_PRESERVE_DOT1Pf_GET(r) ((((r).mhdr[3]) >> 11) & 0x1) +#define MHDR_PPD0_PRESERVE_DOT1Pf_SET(r,f) (r).mhdr[3]=(((r).mhdr[3] & ~((uint32_t)0x1 << 11)) | ((((uint32_t)f) & 0x1) << 11)) +#define MHDR_PPD0_PRESERVE_DSCPf_GET(r) ((((r).mhdr[3]) >> 12) & 0x1) +#define MHDR_PPD0_PRESERVE_DSCPf_SET(r,f) (r).mhdr[3]=(((r).mhdr[3] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) +#define MHDR_PPD0_VID_LOWf_GET(r) ((((r).mhdr[3]) >> 16) & 0xff) +#define MHDR_PPD0_VID_LOWf_SET(r,f) (r).mhdr[3]=(((r).mhdr[3] & ~((uint32_t)0xff << 16)) | ((((uint32_t)f) & 0xff) << 16)) +#define MHDR_PPD0_VID_HIGHf_GET(r) ((((r).mhdr[3]) >> 24) & 0xff) +#define MHDR_PPD0_VID_HIGHf_SET(r,f) (r).mhdr[3]=(((r).mhdr[3] & ~((uint32_t)0xff << 24)) | ((((uint32_t)f) & 0xff) << 24)) +#define MHDR_PPD0_VFIf_GET(r) (((r).mhdr[2]) & 0x1fff) +#define MHDR_PPD0_VFIf_SET(r,f) (r).mhdr[2]=(((r).mhdr[2] & ~((uint32_t)0x1fff)) | (((uint32_t)f) & 0x1fff)) +#define MHDR_PPD0_L3f_GET(r) ((((r).mhdr[2]) >> 21) & 0x1) +#define MHDR_PPD0_L3f_SET(r,f) (r).mhdr[2]=(((r).mhdr[2] & ~((uint32_t)0x1 << 21)) | ((((uint32_t)f) & 0x1) << 21)) +#define MHDR_PPD0_MIRRORf_GET(r) ((((r).mhdr[2]) >> 24) & 0x1) +#define MHDR_PPD0_MIRRORf_SET(r,f) (r).mhdr[2]=(((r).mhdr[2] & ~((uint32_t)0x1 << 24)) | ((((uint32_t)f) & 0x1) << 24)) +#define MHDR_PPD0_INGRESS_TAGGEDf_GET(r) ((((r).mhdr[2]) >> 27) & 0x1) +#define MHDR_PPD0_INGRESS_TAGGEDf_SET(r,f) (r).mhdr[2]=(((r).mhdr[2] & ~((uint32_t)0x1 << 27)) | ((((uint32_t)f) & 0x1) << 27)) +#define MHDR_PPD0_LAG_FAILOVERf_GET(r) ((((r).mhdr[2]) >> 28) & 0x1) +#define MHDR_PPD0_LAG_FAILOVERf_SET(r,f) (r).mhdr[2]=(((r).mhdr[2] & ~((uint32_t)0x1 << 28)) | ((((uint32_t)f) & 0x1) << 28)) +#define MHDR_PPD0_DO_NOT_LEARNf_GET(r) ((((r).mhdr[2]) >> 29) & 0x1) +#define MHDR_PPD0_DO_NOT_LEARNf_SET(r,f) (r).mhdr[2]=(((r).mhdr[2] & ~((uint32_t)0x1 << 29)) | ((((uint32_t)f) & 0x1) << 29)) +#define MHDR_PPD2_PRESERVE_DOT1Pf_GET(r) ((((r).mhdr[3]) >> 2) & 0x1) +#define MHDR_PPD2_PRESERVE_DOT1Pf_SET(r,f) (r).mhdr[3]=(((r).mhdr[3] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) +#define MHDR_PPD2_PRESERVE_DSCPf_GET(r) ((((r).mhdr[3]) >> 3) & 0x1) +#define MHDR_PPD2_PRESERVE_DSCPf_SET(r,f) (r).mhdr[3]=(((r).mhdr[3] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) +#define MHDR_PPD2_VNI_HIGHf_GET(r) ((((r).mhdr[3]) >> 4) & 0x7) +#define MHDR_PPD2_VNI_HIGHf_SET(r,f) (r).mhdr[3]=(((r).mhdr[3] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) +#define MHDR_PPD2_OPCODEf_GET(r) ((((r).mhdr[3]) >> 8) & 0x7) +#define MHDR_PPD2_OPCODEf_SET(r,f) (r).mhdr[3]=(((r).mhdr[3] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) +#define MHDR_PPD2_LAG_FAILOVERf_GET(r) ((((r).mhdr[3]) >> 12) & 0x1) +#define MHDR_PPD2_LAG_FAILOVERf_SET(r,f) (r).mhdr[3]=(((r).mhdr[3] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) +#define MHDR_PPD2_DO_NOT_LEARNf_GET(r) ((((r).mhdr[3]) >> 13) & 0x1) +#define MHDR_PPD2_DO_NOT_LEARNf_SET(r,f) (r).mhdr[3]=(((r).mhdr[3] & ~((uint32_t)0x1 << 13)) | ((((uint32_t)f) & 0x1) << 13)) +#define MHDR_PPD2_MIRRORf_GET(r) ((((r).mhdr[3]) >> 15) & 0x1) +#define MHDR_PPD2_MIRRORf_SET(r,f) (r).mhdr[3]=(((r).mhdr[3] & ~((uint32_t)0x1 << 15)) | ((((uint32_t)f) & 0x1) << 15)) +#define MHDR_PPD2_SOURCE_VPf_GET(r) ((((r).mhdr[3]) >> 16) & 0x1fff) +#define MHDR_PPD2_SOURCE_VPf_SET(r,f) (r).mhdr[3]=(((r).mhdr[3] & ~((uint32_t)0x1fff << 16)) | ((((uint32_t)f) & 0x1fff) << 16)) +#define MHDR_PPD2_DEST_VPf_GET(r) (((r).mhdr[2]) & 0x1fff) +#define MHDR_PPD2_DEST_VPf_SET(r,f) (r).mhdr[2]=(((r).mhdr[2] & ~((uint32_t)0x1fff)) | (((uint32_t)f) & 0x1fff)) +#define MHDR_PPD2_VNI_LOWf_GET(r) ((((r).mhdr[2]) >> 16) & 0x3ff) +#define MHDR_PPD2_VNI_LOWf_SET(r,f) (r).mhdr[2]=(((r).mhdr[2] & ~((uint32_t)0x3ff << 16)) | ((((uint32_t)f) & 0x3ff) << 16)) +#define MHDR_PPD2_FWD_TYPEf_GET(r) ((((r).mhdr[2]) >> 26) & 0x1f) +#define MHDR_PPD2_FWD_TYPEf_SET(r,f) (r).mhdr[2]=(((r).mhdr[2] & ~((uint32_t)0x1f << 26)) | ((((uint32_t)f) & 0x1f) << 26)) +#define MHDR_PPD2_MULTIPOINTf_GET(r) ((((r).mhdr[2]) >> 31) & 0x1) +#define MHDR_PPD2_MULTIPOINTf_SET(r,f) (r).mhdr[2]=(((r).mhdr[2] & ~((uint32_t)0x1 << 31)) | ((((uint32_t)f) & 0x1) << 31)) +#define MHDR_PPD_TYPEf_GET(r) (((r).mhdr[1]) & 0x7) +#define MHDR_PPD_TYPEf_SET(r,f) (r).mhdr[1]=(((r).mhdr[1] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) +#define MHDR_CCf_GET(r) ((((r).mhdr[1]) >> 3) & 0x3) +#define MHDR_CCf_SET(r,f) (r).mhdr[1]=(((r).mhdr[1] & ~((uint32_t)0x3 << 3)) | ((((uint32_t)f) & 0x3) << 3)) +#define MHDR_DPf_GET(r) ((((r).mhdr[1]) >> 6) & 0x3) +#define MHDR_DPf_SET(r,f) (r).mhdr[1]=(((r).mhdr[1] & ~((uint32_t)0x3 << 6)) | ((((uint32_t)f) & 0x3) << 6)) +#define MHDR_DROP_REASONf_GET(r) ((((r).mhdr[1]) >> 8) & 0xff) +#define MHDR_DROP_REASONf_SET(r,f) (r).mhdr[1]=(((r).mhdr[1] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) +#define MHDR_SRC_PORT_TGIDf_GET(r) ((((r).mhdr[1]) >> 16) & 0x1ff) +#define MHDR_SRC_PORT_TGIDf_SET(r,f) (r).mhdr[1]=(((r).mhdr[1] & ~((uint32_t)0x1ff << 16)) | ((((uint32_t)f) & 0x1ff) << 16)) +#define MHDR_DST_PORT_MGIDLf_GET(r) (((r).mhdr[0]) & 0xff) +#define MHDR_DST_PORT_MGIDLf_SET(r,f) (r).mhdr[0]=(((r).mhdr[0] & ~((uint32_t)0xff)) | (((uint32_t)f) & 0xff)) +#define MHDR_DST_PORT_MGIDHf_GET(r) ((((r).mhdr[0]) >> 8) & 0xff) +#define MHDR_DST_PORT_MGIDHf_SET(r,f) (r).mhdr[0]=(((r).mhdr[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) +#define MHDR_TCf_GET(r) ((((r).mhdr[0]) >> 16) & 0xf) +#define MHDR_TCf_SET(r,f) (r).mhdr[0]=(((r).mhdr[0] & ~((uint32_t)0xf << 16)) | ((((uint32_t)f) & 0xf) << 16)) +#define MHDR_MCSTf_GET(r) ((((r).mhdr[0]) >> 20) & 0x1) +#define MHDR_MCSTf_SET(r,f) (r).mhdr[0]=(((r).mhdr[0] & ~((uint32_t)0x1 << 20)) | ((((uint32_t)f) & 0x1) << 20)) +#define MHDR_EGRESS_TAGGING_STATUSf_GET(r) ((((r).mhdr[0]) >> 21) & 0x1) +#define MHDR_EGRESS_TAGGING_STATUSf_SET(r,f) (r).mhdr[0]=(((r).mhdr[0] & ~((uint32_t)0x1 << 21)) | ((((uint32_t)f) & 0x1) << 21)) +#define MHDR_IEUf_GET(r) ((((r).mhdr[0]) >> 22) & 0x1) +#define MHDR_IEUf_SET(r,f) (r).mhdr[0]=(((r).mhdr[0] & ~((uint32_t)0x1 << 22)) | ((((uint32_t)f) & 0x1) << 22)) +#define MHDR_IEU_VALIDf_GET(r) ((((r).mhdr[0]) >> 23) & 0x1) +#define MHDR_IEU_VALIDf_SET(r,f) (r).mhdr[0]=(((r).mhdr[0] & ~((uint32_t)0x1 << 23)) | ((((uint32_t)f) & 0x1) << 23)) +#define MHDR_STARTf_GET(r) ((((r).mhdr[0]) >> 24) & 0xff) +#define MHDR_STARTf_SET(r,f) (r).mhdr[0]=(((r).mhdr[0] & ~((uint32_t)0xff << 24)) | ((((uint32_t)f) & 0xff) << 24)) + +/******************************************************************************* + * End of 'MHDR' + ******************************************************************************/ + + + + +/******************************************************************************* + * + * MHDR SYMBOL TABLE + * + ******************************************************************************/ + +extern bcmdrd_symbols_t mhdr_symbols; + + +#endif /* BCMPKT_MHDR_DEFS_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_net.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_net.h new file mode 100644 index 0000000..dcba460 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_net.h @@ -0,0 +1,367 @@ +/*! \file bcmpkt_net.h + * + * Interfaces for transmitting and receiving packets for the host CPU. + * + * On transmitting, the user calls \ref bcmpkt_tx_f to send out a packet from a + * network interface. The bcmpkt_txpmd_* interfaces could be used for defining + * specific destination, e.g. an egress queue of a local port. + * + * On receiving, the user registers application's callback onto a netif. + * When a packet received, the callback will be called by RX handler to receive + * the packet. Packet structure has a encoded packet metadata for forwarding + * information. The user calls bcmpkt_rxpmd_* interfaces to parsing forwarding + * informaiton for the packet. Refer \ref bcmpkt_rxpmd.h for packet metadata + * APIs. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_NET_H +#define BCMPKT_NET_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*! Loopback Header maximum size. (words) */ +#define BCMPKT_LBHDR_SIZE_WORDS 4 + +/*! + * NET driver types. + */ +typedef enum bcmpkt_net_drv_types_e { + BCMPKT_NET_DRV_T_NONE = BCMPKT_DEV_DRV_T_NONE, /*! No NET driver. */ + BCMPKT_NET_DRV_T_AUTO = BCMPKT_DEV_DRV_T_AUTO, /*! Reserved. */ + BCMPKT_NET_DRV_T_UNET = BCMPKT_DEV_DRV_T_UNET, /*! User land DMA driver. */ + BCMPKT_NET_DRV_T_TPKT = BCMPKT_SOCKET_DRV_T_TPKT,/*! Packet_mmap NET. */ + BCMPKT_NET_DRV_T_RAWSOCK = BCMPKT_SOCKET_DRV_T_RAWSOCK,/*! Raw socket NET. */ + BCMPKT_NET_DRV_T_COUNT /*! Must be end */ +} bcmpkt_net_drv_types_t; + +/*! + * \brief Packet receive callback function type. + * + * Callback function type for applications using RX facility. + * + * The user defines its callback function and register it onto a network + * interface to receive its packets. + * + * The 'packet' buffer should not be freed in application software. If the + * would like to use the packet out of its callback, the packet data should be + * copied in callback function for application usage. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [in] packet Packet handle. + * \param [in] cb_data Application-provided context. + * + * \return SHR_E_XXX Leave for future. + */ +typedef int (*bcmpkt_rx_cb_f)(int unit, int netif_id, bcmpkt_packet_t *packet, + void *cb_data); + +/*! + * \brief Packet receive callback register function. + * + * This function is for upper applications to regiter their callback functions + * onto RX packet handler to receive its packets. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [in] flags Reserved for future. + * \param [in] cb_func Packet receive callback function. + * \param [in] cb_data Application-provided context. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID The netif_id is invalid or doesn't support SOCKET. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_MEMORY Allocate buffer failed. + * \retval SHR_E_EXISTS Callback already exists. + */ +typedef int (*bcmpkt_rx_register_f)(int unit, int netif_id, uint32_t flags, + bcmpkt_rx_cb_f cb_func, void *cb_data); + +/*! + * \brief Packet receive callback deregister function. + * + * Remove callback function from the network interface to disable receive + * packets from it. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [in] cb_func Packet receive callback function. + * \param [in] cb_data Application-provided context. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Netif_id is invalid or doesn't support SOCKET. + * \retval SHR_E_PARAM Check parameters failed. + */ +typedef int (*bcmpkt_rx_unregister_f)(int unit, int netif_id, + bcmpkt_rx_cb_f cb_func, void *cb_data); + +/*! + * \brief Packet transmit function. + * + * This function is for application to send out a packet through Broadcom Packet + * API. + * + * If a packet is to be sent to a specific local port and/or go through Higig + * IPIPE, the metadata and/or Higig header should be configured into + * \ref bcmpkt_packet_t.pmd (\ref BCMPKT_FWD_T_NORMAL type) or encapsulated + * into RCPU/Higig header (\ref BCMPKT_FWD_T_RAW type). + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface number. + * \param [in] packet Packet handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Netif_id is invalid or doesn't support SOCKET. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Transmit failed. + */ +typedef int (*bcmpkt_tx_f)(int unit, int netif_id, bcmpkt_packet_t *packet); + +/*! + * \brief NET operation vector. + */ +typedef struct bcmpkt_net_s { + + /*! initialized flag: 0 - uninitialized 1 - initialized. */ + int initialized; + + /*! Driver name, such as "TPacket". */ + char driver_name[128]; + + /*! SOCKET driver type. */ + bcmpkt_net_drv_types_t driver_type; + + /*! Register RX callback. */ + bcmpkt_rx_register_f rx_register; + + /*! Unregister RX callback. */ + bcmpkt_rx_unregister_f rx_unregister; + + /*! Transmit function. */ + bcmpkt_tx_f tx; + +} bcmpkt_net_t; + +/*! + * \brief NET driver register function. + * + * + * \param [in] net_drv Network driver handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_CONFIG Invalid driver. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_net_drv_register(bcmpkt_net_t *net_drv); + +/*! + * \brief Unregister NET driver. + * + * \param [in] type NET driver type. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_BUSY The driver is in using. + */ +extern int +bcmpkt_net_drv_unregister(bcmpkt_net_drv_types_t type); + +/*! + * \brief Get NET driver's type. + * + * \param [in] unit Switch unit number. + * \param [out] type NET driver type. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + */ +extern int +bcmpkt_net_drv_type_get(int unit, bcmpkt_net_drv_types_t *type); + +/*! + * \brief Direct forwarding port set function. + * + * Configure a destination port for bypass CPU port IPIPE and forwarding the + * packet to the specific port directly. This function will set TXPMD (SOBMH) + * for the forwarding. + * + * \param [in] dev_type Switch device type. + * \param [in] port Packet destination port. + * \param [in,out] packet Packet handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_INTERNAL Internal failure. + */ +extern int +bcmpkt_fwd_port_set(bcmdrd_dev_type_t dev_type, int port, + bcmpkt_packet_t *packet); + +/*! + * \brief Packet forwarding type set function. + * + * Packet's default type is NORMAL. If the user want to change the type, this + * API is used for the purpose. + * + * \param [in] type Packet forward type. + * \param [in,out] packet Packet handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_fwd_type_set(bcmpkt_fwd_types_t type, bcmpkt_packet_t *packet); + +/*! + * \brief Packet receive callback register function. + * + * This function is for upper applications to regiter their callback functions + * onto RX packet handler to receive its packets. + * + * The 'netif_id' is not used for UNET driver and would be ignored. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [in] flags Reserved for future. + * \param [in] cb_func Packet receive callback function. + * \param [in] cb_data Application-provided context. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID The netif_id is invalid or doesn't support SOCKET. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_MEMORY Allocate buffer failed. + * \retval SHR_E_EXISTS Callback already exists. + */ +extern int +bcmpkt_rx_register(int unit, int netif_id, uint32_t flags, + bcmpkt_rx_cb_f cb_func, void *cb_data); + +/*! + * \brief Packet receive callback deregister function. + * + * Remove callback function from the network interface to disable receive + * packets from it. + * + * The 'netif_id' is not used for UNET driver and would be ignored. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [in] cb_func Packet receive callback function. + * \param [in] cb_data Application-provided context. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Netif_id is invalid or doesn't support SOCKET. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_rx_unregister(int unit, int netif_id, bcmpkt_rx_cb_f cb_func, + void *cb_data); + +/*! + * \brief Packet transmit function. + * + * This function is for application to send out a packet through Broadcom Packet + * API. + * + * If a packet is to be sent to a specific local port and/or go through Higig + * IPIPE, the metadata and/or Higig header should be configured into + * \ref bcmpkt_packet_t.pmd (\ref BCMPKT_FWD_T_NORMAL type) or encapsulated + * into RCPU/Higig header (\ref BCMPKT_FWD_T_RAW type). + * + * For UNET driver mode, 'netif_id' is TX DMA queue index (starts from 1). + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface number. + * \param [in] packet Packet handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Netif_id is invalid or doesn't support SOCKET. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_FAIL Transmit failed. + */ +extern int +bcmpkt_tx(int unit, int netif_id, bcmpkt_packet_t *packet); + +/*! + * \brief Suspend or resume packet transmit function. + * + * This function is for suspend or resume sending out a packet through + * bcmpkt_tx API. + * + * \param [in] unit Switch unit number. + * \param [in] suspend True to suspend TX packets or false to resume. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_tx_suspend_set(int unit, bool suspend); + +/*! + * \brief Get the suspend status of packet transmit function. + * + * This function is for getting the suspend status of packet transmission. + * + * \param [in] unit Switch unit number. + * \param [out] suspend True for suspended or false for not suspended. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_FAIL Access driver failed. + */ +extern int +bcmpkt_tx_suspend_get(int unit, bool *suspend); + +#endif /* BCMPKT_NET_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_packet.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_packet.h new file mode 100644 index 0000000..2130f44 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_packet.h @@ -0,0 +1,182 @@ +/*! \file bcmpkt_packet.h + * + * Packet definition for host CPU transmitting and receiving. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_PACKET_H +#define BCMPKT_PACKET_H + +#include + +/*! + * This size is for \ref bcmpkt_packet_t.pmd data. + * Including RXPMD, TXPMD, Higig, and Loopback Header. + * RXPMD use RX DCB size, and others use TX DCB Module header size. + * Real size of them will be take care in API. + */ +#define BCMPKT_PMD_SIZE_BYTES (BCMPKT_RCPU_RXPMD_SIZE + \ + BCMPKT_RCPU_TX_MH_SIZE * 3) + +/*! The bcmpkt_packet_t.pmd.data size. (number of words) */ +#define BCMPKT_PMD_SIZE_WORDS (BCMPKT_PMD_SIZE_BYTES / 4) + +/*! + * This space is reserved for (o) optional components. + * + * (o) RCPU header + * (o) Tx meta data (Tx PMD) + * (o) Loopback header + * (o) HiGig header * + */ +#define BCMPKT_TX_HDR_RSV BCMPKT_RCPU_MAX_ENCAP_SIZE + +/*! Packet data handle. */ +#define BCMPKT_PACKET_DATA(_pkt) (_pkt)->data_buf->data + +/*! Packet data length. */ +#define BCMPKT_PACKET_LEN(_pkt) (_pkt)->data_buf->data_len + +/*! + * Packet forwarding types. + * The \ref bcmpkt_packet_t.pmd defines normal packet forwarding and + * encapsulation information. For BCMPKT_PACKET_T_NORMAL type, SDk will refer + * \ref bcmpkt_packet_t.pmd for specific forwarding and Higig encapsulation. + * If BCMPKT_FWD_T_RAW type is set, SDK will ignore \ref bcmpkt_packet_t.pmd. + * In this case, the application user should take care of RCPU header and Higig + * header because call \ref bcmpkt_net_t.tx to send out the packet. + * The BCMPKT_FWD_T_RAW is normally used for debugging purpose. + */ +typedef enum bcmpkt_fwd_types_e { + /*! Normal Packet. */ + BCMPKT_FWD_T_NORMAL, + /*! Raw packet, may include RCPU header, TXPMD and/or Higig header. */ + BCMPKT_FWD_T_RAW, + /*! Must be end */ + BCMPKT_FWD_T_COUNT +} bcmpkt_fwd_types_t; + +/*! + * Packet metadata information. + */ +typedef struct bcmpkt_pmd_s { + + /*! RX Packet metadata handle. */ + uint32_t *rxpmd; + + /*! TX Packet metadata handle. */ + uint32_t *txpmd; + + /*! Higig handle. */ + uint32_t *higig; + + /*! Loopback Header handle. */ + uint32_t *lbhdr; + + /*! Headers' data. */ + uint32_t data[BCMPKT_PMD_SIZE_WORDS]; + +} bcmpkt_pmd_t; + +/*! + * Packet data buffer information. + * + * The 'head' is the packet data buffer's pointer. The space between 'head' and + * 'data' can be used for packet data content adjustment and/or RCPU header, + * TXPMD and Higig encapsulation. + * + * The \c ref_count is used for clone function. It increases for each packet + * clone function called, and decreases for each data buffer free called. When + * \c ref_count = 0, free the buffer. + */ +typedef struct bcmpkt_data_buf_s { + + /*! Packet buffer head pointer. */ + uint8_t *head; + + /*! Packet buffer size (start from head). */ + uint32_t len; + + /*! Packet data pointer. */ + uint8_t *data; + + /*! Packet data size, unit is byte. */ + uint32_t data_len; + + /*! Number of packets using this data buffer. */ + int ref_count; +} bcmpkt_data_buf_t; + +/*! + * \name Packet flags. + * \anchor BCMPKT_PACKET_F_XXX + */ +/*! \{ */ +/*! Do not pad runt TX packet. */ +#define BCMPKT_PACKET_F_TX_NO_PAD (1 << 0) +/*! \} */ + +/*! + * \brief Packet structure. + * + * \c unit is for per device DMA buffer management. + * \c type is packet forwarding type. + * \c pmd saves packet metadata information. + * \c data saves data buffer information. + */ +typedef struct bcmpkt_packet_s { + + /*! Point to next packet in the list. */ + struct bcmpkt_packet_s *next; + + /*! Point to previous packet in the list. */ + struct bcmpkt_packet_s *prev; + + /*! Switch unit number. */ + int unit; + + /*! Flags, refer to \ref BCMPKT_PACKET_F_XXX. */ + uint32_t flags; + + /*! Packet forwarding type, refer to \ref bcmpkt_fwd_types_t. */ + uint32_t type; + + /*! Packet metadata information. */ + bcmpkt_pmd_t pmd; + + /*! Packet data buffer information. */ + bcmpkt_data_buf_t *data_buf; + +} bcmpkt_packet_t; + +#endif /* BCMPKT_PACKET_H */ + diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_pmd.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_pmd.h new file mode 100644 index 0000000..189d879 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_pmd.h @@ -0,0 +1,66 @@ +/*! \file bcmpkt_pmd.h + * + * Common macros and definitions for PMD. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_PMD_H +#define BCMPKT_PMD_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif + +/* For application convenience */ +#include +#include +#include +#include +#include +#include +#include + +/*! Invalid PMD header field ID. */ +#define BCMPKT_FID_INVALID -1 + +/*! Bitmap array size. */ +#define BCMPKT_BITMAP_WORD_SIZE 16 + +/*! PMD header field ID bit array. */ +typedef struct bcmpkt_bitmap_s { + /*! Bit array */ + uint32_t pbits[BCMPKT_BITMAP_WORD_SIZE]; +} bcmpkt_bitmap_t; + +#endif /* BCMPKT_PMD_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_pmd_internal.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_pmd_internal.h new file mode 100644 index 0000000..b1a6c7b --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_pmd_internal.h @@ -0,0 +1,78 @@ +/*! \file bcmpkt_pmd_internal.h + * + * \brief Basic PMD definitions. + * + * The defintions are kept separate to minimize the header file + * dependencies for the stand-alone PMD library. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_PMD_INTERNAL_H +#define BCMPKT_PMD_INTERNAL_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif + +/*! Get a field from a PMD buffer. */ +typedef uint32_t (*bcmpkt_field_get_f)(uint32_t *data); + +/*! Set a field within a PMD buffer. */ +typedef void (*bcmpkt_field_set_f)(uint32_t *data, uint32_t val); + +/*! Get a complex field pointer or other attributions. */ +typedef uint32_t (*bcmpkt_ifield_get_f)(uint32_t *data, uint32_t **addr); + +/*! + * \brief Packet metadata information structure. + */ +typedef struct bcmpkt_pmd_view_info_s { + + /*! View type list. */ + shr_enum_map_t *view_types; + + /*! + * Each field's view code. + * -2 means unavailable field. + * -1 means common field. + * others are correspondent view codes defined in view types. + */ + int *view_infos; + + /*! View type get function. */ + bcmpkt_field_get_f view_type_get; + +} bcmpkt_pmd_view_info_t; + +#endif /* BCMPKT_PMD_INTERNAL_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rcpu_hdr.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rcpu_hdr.h new file mode 100644 index 0000000..58eccd6 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rcpu_hdr.h @@ -0,0 +1,146 @@ +/*! \file bcmpkt_rcpu_hdr.h + * + * RCPU header format definition. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_RCPU_HDR_H +#define BCMPKT_RCPU_HDR_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif + +/*! RCPU Header length. */ +#define BCMPKT_RCPU_HDR_LEN 32 +/*! RX PMD maximum size. */ +#define BCMPKT_RCPU_RXPMD_SIZE 96 +/*! RX Encapsulation size. */ +#define BCMPKT_RCPU_RX_ENCAP_SIZE (BCMPKT_RCPU_HDR_LEN + BCMPKT_RCPU_RXPMD_SIZE) +/*! TX Module Header size. */ +#define BCMPKT_RCPU_TX_MH_SIZE 32 +/*! TX Encapsulation size. */ +#define BCMPKT_RCPU_TX_ENCAP_SIZE (BCMPKT_RCPU_HDR_LEN + BCMPKT_RCPU_TX_MH_SIZE) +/*! Maximum Encapsulation size. */ +#define BCMPKT_RCPU_MAX_ENCAP_SIZE BCMPKT_RCPU_RX_ENCAP_SIZE + +/*! + * \name Packet RCPU operation types. + * \anchor BCMPKT_RCPU_OP_XXX + */ +/*! \{ */ +/*! No operation code. */ +#define BCMPKT_RCPU_OP_NONE 0x0 +/*! To CPU packet. */ +#define BCMPKT_RCPU_OP_RX 0x10 +/*! From CPU packet. */ +#define BCMPKT_RCPU_OP_TX 0x20 +/*! \} */ + +/*! + * \name Packet RCPU flags. + * \anchor BCMPKT_RCPU_F_XXX + */ +/*! \{ */ +/*! No operation code. */ +#define BCMPKT_RCPU_F_NONE 0 +/*! To CPU packet. */ +#define BCMPKT_RCPU_F_MODHDR (1 << 2) +/*! Tx queue number */ +#define BCMPKT_RCPU_F_TX_BIND_QUE (1 << 3) +/*! Do not pad runt TX packet. */ +#define BCMPKT_RCPU_F_TX_NO_PAD (1 << 4) +/*! TX packet in data RAW mode. */ +#define BCMPKT_RCPU_F_TX_DATA_RAW (1 << 5) +/*! \} */ + +/*! RCPU default VLAN ID with pri and cfi. */ +#define BCMPKT_RCPU_VLAN 0x01 + +/*! RCPU TPID. */ +#define BCMPKT_RCPU_TPID 0x8100 + +/*! RCPU Ethertype. */ +#define BCMPKT_RCPU_ETYPE 0xde08 + +/*! + * \brief The RCPU header format structure. + */ +typedef struct bcmpkt_rcpu_hdr_s { + + /*! RCPU header DMAC. */ + shr_mac_t dmac; + + /*! RCPU header SMAC. */ + shr_mac_t smac; + + /*! VLAN TPID. */ + uint16_t tpid; + + /*! VLAN TAG with cfi + pri. */ + uint16_t vlan; + + /*! Ether-type. */ + uint16_t ethertype; + + /*! RCPU signature. */ + uint16_t signature; + + /*! RCPU operation code. */ + uint8_t opcode; + + /*! RCPU operation code. */ + uint8_t flags; + + /*! RCPU operation code. */ + uint16_t transid; + + /*! Length of packet data. */ + uint16_t pkt_len; + + /*! Expect reply message length. */ + uint16_t reply_len; + + /*! packet meta data length. (Internal usage) */ + uint8_t meta_len; + + /*! Transmission queue number. (Internal usage) */ + uint8_t queue_id; + + /*! Reserved must be 0 */ + uint16_t reserved; + +} bcmpkt_rcpu_hdr_t; + +#endif /* BCMPKT_RCPU_HDR_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd.h new file mode 100644 index 0000000..0959f9a --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd.h @@ -0,0 +1,284 @@ +/*! \file bcmpkt_rxpmd.h + * + * RX Packet Meta Data (RXPMD, called EP_TO_CPU in hardware) access interfaces. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_RXPMD_H +#define BCMPKT_RXPMD_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#include +#endif +#include +#include +#include +#include +#include +#include +#include + +/*! RX raw packet metadata maximum size (words). */ +#define BCMPKT_RXPMD_SIZE_WORDS 18 + +/*! RX raw packet metadata maximum size (bytes). */ +#define BCMPKT_RXPMD_SIZE_BYTES (BCMPKT_RXPMD_SIZE_WORDS * 4) + +/*! CELL Error status bitmap. */ +#define BCMPKT_RXMETA_ST_CELL_ERROR (0x1 << 18) + +/*! \brief Packet reasons bitmap. + * Set of "reasons" (\ref BCMPKT_RX_REASON_XXX) why a packet came to the CPU. + */ +typedef struct bcmpkt_rx_reasons_s { + /*! Bitmap container */ + SHR_BITDCLNAME(pbits, BCMPKT_RX_REASON_COUNT); +} bcmpkt_rx_reasons_t; + +/*! + * \name RXPMD Dump flags. (deprecated by BCMPKT_DUMP_F_XXX) + * \anchor BCMPKT_RXPMD_DUMP_F_XXX + */ +/*! \{ */ +/*! + * Dump all fields contents. + */ +#define BCMPKT_RXPMD_DUMP_F_ALL 0 +/*! + * Dump non-zero field content only. + */ +#define BCMPKT_RXPMD_DUMP_F_NONE_ZERO 1 +/*! \} */ + +/*! + * \name Packet RX reason utility macros. + * \anchor BCMPKT_RX_REASON_OPS + */ +/*! \{ */ +/*! + * Macro to check if a reason (\ref BCMPKT_RX_REASON_XXX) is included in a + * set of reasons (\ref bcmpkt_rx_reasons_t). Returns: + * zero => reason is not included in the set + * non-zero => reason is included in the set + */ +#define BCMPKT_RX_REASON_GET(_reasons, _reason) \ + SHR_BITGET(((_reasons).pbits), (_reason)) + +/*! + * Macro to add a reason (\ref BCMPKT_RX_REASON_XXX) to a set of + * reasons (\ref bcmpkt_rx_reasons_t) + */ +#define BCMPKT_RX_REASON_SET(_reasons, _reason) \ + SHR_BITSET(((_reasons).pbits), (_reason)) + +/*! + * Macro to add all reasons (\ref BCMPKT_RX_REASON_XXX) to a set of + * reasons (\ref bcmpkt_rx_reasons_t) + */ +#define BCMPKT_RX_REASON_SET_ALL(_reasons) \ + SHR_BITSET_RANGE(((_reasons).pbits), 0, BCMPKT_RX_REASON_COUNT) + +/*! + * Macro to clear a reason (\ref BCMPKT_RX_REASON_XXX) from a set of + * reasons (\ref bcmpkt_rx_reasons_t) + */ +#define BCMPKT_RX_REASON_CLEAR(_reasons, _reason) \ + SHR_BITCLR(((_reasons).pbits), (_reason)) + +/*! + * Macro to clear a set of reasons (\ref bcmpkt_rx_reasons_t). + */ +#define BCMPKT_RX_REASON_CLEAR_ALL(_reasons) \ + SHR_BITCLR_RANGE(((_reasons).pbits), 0, BCMPKT_RX_REASON_COUNT) +/*! + * Macro to check for no reason (\ref bcmpkt_rx_reasons_t). + */ +#define BCMPKT_RX_REASON_IS_NULL(_reasons) \ + SHR_BITNULL_RANGE(((_reasons).pbits), \ + 0, BCMPKT_RX_REASON_COUNT) + +/*! + * Macro to iterate every reason (\ref bcmpkt_rx_reasons_t). + */ +#define BCMPKT_RX_REASON_ITER(_reasons, reason) \ + for(reason = BCMPKT_RX_REASON_NONE; reason < (int)BCMPKT_RX_REASON_COUNT; reason++) \ + if(BCMPKT_RX_REASON_GET(_reasons, reason)) + +/*! + * Macro to get reasons number (\ref bcmpkt_rx_reasons_t). + */ +#define BCMPKT_RX_REASONS_COUNT(_reasons, _count) \ + SHR_BITCOUNT_RANGE(((_reasons).pbits), _count, \ + 0, BCMPKT_RX_REASON_COUNT) + +/*! + * Macro to compare 2 reasons (\ref bcmpkt_rx_reasons_t), return 1 for exact match. + */ +#define BCMPKT_RX_REASON_EQ(_reasons1, _reasons2) \ + SHR_BITEQ_RANGE(((_reasons1).pbits), ((_reasons2).pbits), \ + 0, BCMPKT_RX_REASON_COUNT) +/*! \} */ + + +/*! + * \brief Get RXPMD's size for a given device type. + * + * \param [in] dev_type Device type. + * \param [out] len Bytes of RXPMD length. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Unsupported device type or bad \c len pointer. + * \retval SHR_E_UNAVAIL Not support RXPMD get function. + */ +extern int +bcmpkt_rxpmd_len_get(bcmdrd_dev_type_t dev_type, uint32_t *len); + + +/*! + * \brief Get module header's pointer of the RXPMD. + * + * This function is used for geting Module header's pointer in RXPMD. + * + * \param [in] dev_type Device type. + * \param [in] rxpmd RXPMD handle. + * \param [out] hg_hdr HiGig header handle. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support HiGig header. + * \retval SHR_E_INTERNAL Internal issue. + */ +extern int +bcmpkt_rxpmd_mh_get(bcmdrd_dev_type_t dev_type, uint32_t *rxpmd, + uint32_t **hg_hdr); + +/*! + * \brief Get RX reasons from RXPMD. + * + * Decode packet's RX reasons into "reasons". A received packet may have one RX + * reason, multiple RX reasons, or none reason. RX reasons are in the format of + * bitmap. Each bit means one reason type (refer to \ref BCMPKT_RX_REASON_XXX). + * + * User may use \ref BCMPKT_RX_REASON_OPS to parse each individual reason based + * on this function's return value "reasons". + * + * \param [in] dev_type Device type. + * \param [in] rxpmd RXPMD handle. + * \param [out] reasons RX reasons in bit array. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support Reason. + * \retval SHR_E_INTERNAL Internal issue. + */ +extern int +bcmpkt_rxpmd_reasons_get(bcmdrd_dev_type_t dev_type, uint32_t *rxpmd, + bcmpkt_rx_reasons_t *reasons); + +/*! + * \brief Set RX reasons into the RXPMD. (Internally used for filter configuration.) + * + * Set RX reasons into RXPMD data for packet filter purpose. + * + * \param [in] dev_type Device type. + * \param [in] reasons Reasons bit array. + * \param [in,out] rxpmd RXPMD handle. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support Reason. + * \retval SHR_E_INTERNAL Internal issue. + */ +extern int +bcmpkt_rxpmd_reasons_set(bcmdrd_dev_type_t dev_type, + bcmpkt_rx_reasons_t *reasons, uint32_t *rxpmd); + +/*! + * \brief Get field name for a given RXPMD field ID. + * + * \param [in] fid RXPMD field ID, refer to \ref BCMPKT_RXPMD_XXX. + * \param [out] name RXPMD field name string. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_rxpmd_field_name_get(int fid, char **name); + +/*! + * \brief Get field ID for a given RXPMD field name. + * + * \param [in] name RXPMD field name string. + * \param [out] fid RXPMD Field ID. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_NOT_FOUND Not found the name. + */ +extern int +bcmpkt_rxpmd_field_id_get(char* name, int *fid); + +/*! + * \brief Get an RX reason's name. + * + * \param [in] reason Reason ID. + * \param [out] name Reason name string handle. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_rx_reason_name_get(int reason, char **name); + +/*! + * \brief Return the RXPMD match id information. + * + * This routine returns the RXPMD match id information + * for the given match id name. + * + * \param [in] variant Variant type. + * \param [in] spec Match ID name. + * \param [out] info Match ID data. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_PARAM Invalid variant, spec or info. + * \retval SHR_E_UNAVAIL Match ID data is not available. + * + */ +extern int +bcmpkt_rxpmd_match_id_data_get(bcmlrd_variant_t variant, const char *spec, + const bcmlrd_match_id_db_t **info); + +#endif /* BCMPKT_RXPMD_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_defs.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_defs.h new file mode 100644 index 0000000..0199240 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_defs.h @@ -0,0 +1,1325 @@ +#ifndef BCMPKT_RXPMD_DEFS_H +#define BCMPKT_RXPMD_DEFS_H +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * Tool: INTERNAL/regs/xgs/generate-pmd.pl + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides field macros for RX Packet Metadata (RXPMD, called + * EP_TO_CPU in hardware) access. + * + ******************************************************************************/ + +/*! + * \name RX packet metadata field IDs. + * \anchor BCMPKT_RXPMD_XXX + */ +/*! \{ */ +/*! Invalid BCMPKT_RXPMD FID indicator */ +#define BCMPKT_RXPMD_FID_INVALID -1 +/*! Cell was stored in Unicast Queue in MMU. */ +#define BCMPKT_RXPMD_UNICAST_QUEUE 0 +/*! Queue number used in MMU, PBE field */ +#define BCMPKT_RXPMD_QUEUE_NUM 1 +/*! OVERLAY ON QUEUE_NUM Queue number used in MMU for cpu port, PBE field */ +#define BCMPKT_RXPMD_CPU_COS 2 +/*! + * Valid only for packets which came in on Higig+ source port. Higig+ module + * header field, PBE field. + */ +#define BCMPKT_RXPMD_HGI 3 +/*! Matched Rule, PBE field. */ +#define BCMPKT_RXPMD_MATCHED_RULE 4 +/*! DO NOT CHANGE, USED BY CMIC HW: Packet length after all modification. */ +#define BCMPKT_RXPMD_PKT_LENGTH 5 +/*! Source Port Number, PBE field. */ +#define BCMPKT_RXPMD_SRC_PORT_NUM 6 +/*! Inner VID. */ +#define BCMPKT_RXPMD_INNER_VID 7 +/*! Inner CFI */ +#define BCMPKT_RXPMD_INNER_CFI 8 +/*! Inner priority. */ +#define BCMPKT_RXPMD_INNER_PRI 9 +/*! Outer VID. */ +#define BCMPKT_RXPMD_OUTER_VID 10 +/*! Outer Canoncial Format Indicator. */ +#define BCMPKT_RXPMD_OUTER_CFI 11 +/*! Outer Priority. */ +#define BCMPKT_RXPMD_OUTER_PRI 12 +/*! Special packet. */ +#define BCMPKT_RXPMD_SPECIAL_PACKET_INDICATOR 13 +/*! Special packet type. */ +#define BCMPKT_RXPMD_SPECIAL_PACKET_TYPE 14 +/*! Set to 1 if the DSCP value has been changed by the EP */ +#define BCMPKT_RXPMD_CHANGE_DSCP 15 +/*! New DSCP value computed by the chip (EP) for the packet */ +#define BCMPKT_RXPMD_DSCP 16 +/*! Change the ECN as indicated by the IFP. */ +#define BCMPKT_RXPMD_CHANGE_ECN 17 +/*! New ECN value provided by the IFP. */ +#define BCMPKT_RXPMD_ECN 18 +/*! + * NEW This pretty much maps from EP_TO_CPU_HEADER_OVERLAY_TYPE from the MPB + * 0: Invalid + * 1: TIMESTAMP field carries the LM packet-count for an OAM loss measurement + * packet + * 2: TIMESTAMP_UPPER,TIMESTAMP fields carry the 64-bit DM Time-stamp for an + * OAMdelay measurement packet + * 3: 802.1AS timestamp in the TIMESTAMP field + */ +#define BCMPKT_RXPMD_TIMESTAMP_TYPE 19 +/*! Low 32 bits of timestamp. */ +#define BCMPKT_RXPMD_TIMESTAMP 20 +/*! High 32/16bits of timestamp. */ +#define BCMPKT_RXPMD_TIMESTAMP_HI 21 +/*! Mirror-to-Port Index, PBE field */ +#define BCMPKT_RXPMD_MTP_INDEX 22 +/*! BPDU Packet, PBE field */ +#define BCMPKT_RXPMD_BPDU 23 +/*! Indicates the packet is generated as a result of packet replication */ +#define BCMPKT_RXPMD_REPLICATION 24 +/*! L3 IP Multicast Packet Flag, PBE field */ +#define BCMPKT_RXPMD_L3ONLY 25 +/*! Indicates packet was routed - UC OR MC */ +#define BCMPKT_RXPMD_IP_ROUTED 26 +/*! Source port is Higig. */ +#define BCMPKT_RXPMD_SRC_HIGIG 27 +/*! Source port is Higig2. */ +#define BCMPKT_RXPMD_SRC_HIGIG2 28 +/*! Indicates all switch copies were dropped in MMU (for copies to CPU port). */ +#define BCMPKT_RXPMD_UC_SW_COPY_DROPPED 29 +/*! + * Flag to indicate this is a switched packet as opposed to a mirrored packet, + * PBE field + */ +#define BCMPKT_RXPMD_SWITCH 30 +/*! Indicates there is an SD tag in the packet */ +#define BCMPKT_RXPMD_SD_TAG_PRESENT 31 +/*! + * Indicates ingress inner VLAN tag action, PBE field: + * 0: do not modify, 1: add I-VID, 2: replace I-VID, 3: remove I-VID + */ +#define BCMPKT_RXPMD_ING_ITAG_ACTION 32 +/*! + * Indicates ingress outer VLAN tag action, PBE field: + * 0: do not modify, 1: add O-VID, 2: replace O-VID, 3: reserved + */ +#define BCMPKT_RXPMD_ING_OTAG_ACTION 33 +/*! + * Indicates the incoming tag status (INCOMING_TAG_STATUS): + * For single tag device: + * 0: untagged, 1: tagged + * For double tag device: + * 0: untagged, 1: single inner-tag, 2: single outer-tag, 3: double tagged + */ +#define BCMPKT_RXPMD_ING_TAG_TYPE 34 +/*! + * This field is set by the ingress chip to indicate to the egress chip that 1588 + * 1-step ingress correction update has been applied to this packet. Egress chip + * uses this bit when egress port CF_UPDATE_MODE is set to ING_UPDATE_BASED_ENABLE. + * Encodings are: + * 0: Ingress correction update has NOT been applied to the packet. When configured + * in coupled mode, egress chip must NOT apply the egress correction update for + * this packet. + * 1: Ingress correction update has been applied to the packet. When configured in + * coupled mode, egress chip must apply the egress correction update. + */ +#define BCMPKT_RXPMD_ONE_STEP_1588_ING_UPDATE_DONE 35 +/*! The full 32-bit EH tag */ +#define BCMPKT_RXPMD_EH_TAG 36 +/*! + * Defines the header type enabling flexibility for future applications. + * 0x0: Queue selections for Sirius/Arad. + * 0x1: ClassID + * 0x2: ClassID + QTag + * 0x3-0x15: Reserved for future use. + */ +#define BCMPKT_RXPMD_EH_TYPE 37 +/*! See EH_SEG_SEL_ENCODING format */ +#define BCMPKT_RXPMD_EH_TYPE_0_EH_SEG_SEL 38 +/*! + * EH queue tag assignment + * 00: No EH queue tag assignment, + * 01-11: EH queue tag assignment modes + */ +#define BCMPKT_RXPMD_EH_TYPE_0_EH_TAG_TYPE 39 +/*! EH queue tag */ +#define BCMPKT_RXPMD_EH_TYPE_0_EH_QUEUE_TAG 40 +/*! Type of CLASSID */ +#define BCMPKT_RXPMD_EH_TYPE_1_CLASSID_TYPE 41 +/*! L3_IIF */ +#define BCMPKT_RXPMD_EH_TYPE_1_L3_IIF 42 +/*! CLASSID */ +#define BCMPKT_RXPMD_EH_TYPE_1_CLASSID 43 +/*! Type of CLASSID */ +#define BCMPKT_RXPMD_EH_TYPE_2_CLASSID_TYPE 44 +/*! CLASSID */ +#define BCMPKT_RXPMD_EH_TYPE_2_CLASSID 45 +/*! L3_IIF */ +#define BCMPKT_RXPMD_EH_TYPE_2_EH_QUEUE_TAG 46 +/*! Indicates the Session ID for the Rx BFD packet.Valid when OAM_PKT_TYPE=2 */ +#define BCMPKT_RXPMD_RX_BFD_START_OFFSET 47 +/*! Indicates the Session ID for the Rx BFD packet.Valid when OAM_PKT_TYPE=2 */ +#define BCMPKT_RXPMD_RX_BFD_START_OFFSET_TYPE 48 +/*! Indicates the Session ID for the Rx BFD packet.Valid when OAM_PKT_TYPE=2 */ +#define BCMPKT_RXPMD_RX_BFD_SESSION_INDEX 49 +/*! The reason code TYPE. */ +#define BCMPKT_RXPMD_REASON_TYPE 50 +/*! + * This should be the final control in the EP indicating to not change the TTL, + * from any source. + */ +#define BCMPKT_RXPMD_DO_NOT_CHANGE_TTL 51 +/*! Valid for non-BFD packet */ +#define BCMPKT_RXPMD_I2E_CLASSID_TYPE 52 +/*! Valid for non-BFD packet */ +#define BCMPKT_RXPMD_I2E_CLASSID 53 +/*! Ingress L3 Intf number. */ +#define BCMPKT_RXPMD_ING_L3_INTF 54 +/*! Indication to next pass about the type of loopback. */ +#define BCMPKT_RXPMD_LOOPBACK_PACKET_TYPE 55 +/*! If set, then packet has been modified by the EP and CRC needs to be regenerated */ +#define BCMPKT_RXPMD_REGEN_CRC 56 +/*! Entropy label. */ +#define BCMPKT_RXPMD_ENTROPY_LABEL 57 +/*! Used to indicate if and how a tunnel has been decapsulated from the packet. */ +#define BCMPKT_RXPMD_TUNNEL_DECAP_TYPE 58 +/*! DLB_ID valid. */ +#define BCMPKT_RXPMD_DLB_ID_VALID 59 +/*! DLB_ID. */ +#define BCMPKT_RXPMD_DLB_ID 60 +/*! HG2 Extended Header Valid. (was in FRC_reserved) */ +#define BCMPKT_RXPMD_HG2_EXT_HDR_VALID 61 +/*! + * New field for VNTAG/ETAGs: 00: Do not Modify + * 01: Add/Replace incoming VNTAG/ETAG with Ingress Port Based VNTAG + * 10: Add/Replace incoming VNTAG/ETAG with Ingress Port Based ETAG. + * 11: Delete Packets VNTAG/ETAG + */ +#define BCMPKT_RXPMD_VNTAG_ACTION 62 +/*! If set, the DVP/NHOP_INDEX overlay has the DVP. Else, it has the Next Hop Index. */ +#define BCMPKT_RXPMD_DVP_NHI_SEL 63 +/*! Validates VFI field */ +#define BCMPKT_RXPMD_VFI_VALID 64 +/*! + * This field's msb is the replication type from the EGR_IPMC table. + * It is a flag that determines the contents of the lower 15-bits. + * 0 => Lower 16-bits contain the IPMC_INTF_NUM from the MMU + * 1 => Lower 16-bits contain the NEXT_HOP_INDEX from the Ingress Pipeline + */ +#define BCMPKT_RXPMD_REPLICATION_OR_NHOP_INDEX 65 +/*! Low 32 bits of the packet MATCH_ID. */ +#define BCMPKT_RXPMD_MATCH_ID_LO 66 +/*! High 18 bits of the packet MATCH_ID. */ +#define BCMPKT_RXPMD_MATCH_ID_HI 67 +/*! MPB flex data_type from MPB_FIXED.flex_data_type */ +#define BCMPKT_RXPMD_MPB_FLEX_DATA_TYPE 68 +/*! From EPRE/EDEV_CONFIG table EGR_INT_CN_UPDPATE.int_cn */ +#define BCMPKT_RXPMD_INT_CN 69 +/*! From MPB_FIXED */ +#define BCMPKT_RXPMD_CNG 70 +/*! From MPB_FIXED */ +#define BCMPKT_RXPMD_EGR_ZONE_REMAP_CTRL 71 +/*! Constant specified in NPL */ +#define BCMPKT_RXPMD_DMA_HEADER_VERSION 72 +/*! Multicast packet from MPB_FIXED */ +#define BCMPKT_RXPMD_MULTICAST 73 +/*! Copy to CPU from MPB_FIXED */ +#define BCMPKT_RXPMD_COPY_TO_CPU 74 +/*! Trucate CPU copy from MPB_FIXED */ +#define BCMPKT_RXPMD_TRUNCATE_CPU_COPY 75 +/*! Incoming INT header type. */ +#define BCMPKT_RXPMD_INCOMING_INT_HDR_TYPE 76 +/*! MPB_FIXED.dop_trigger. */ +#define BCMPKT_RXPMD_DOP_TRIGGER 77 +/*! From EPRE. If mirror pkt then == MIRROR_ENCAP_INDEx else == eparse_extract_offsets[3:0]. */ +#define BCMPKT_RXPMD_EPARSE_EXTRACT_OFFSETS_3_0_OR_MIRROR_ENCAP_INDEX 78 +/*! Eparse_extract_offsets[7:4]. */ +#define BCMPKT_RXPMD_EPARSE_EXTRACT_OFFSETS_7_4 79 +/*! Valid for non-BFD packet */ +#define BCMPKT_RXPMD_ING_L3_INTF_VALID 80 +/*! Overlay next hop. */ +#define BCMPKT_RXPMD_O_NHI 81 +/*! Inner Entropy Used indication */ +#define BCMPKT_RXPMD_IEU 82 +/*! IEU indication is valid */ +#define BCMPKT_RXPMD_IEU_VALID 83 +/*! incoming opaque tag status indication */ +#define BCMPKT_RXPMD_INCOMING_OPAQUE_TAG_STATUS 84 +/*! Eparse_extract_offsets[6:4]. */ +#define BCMPKT_RXPMD_EPARSE_EXTRACT_OFFSETS_6_4 85 +/*! From EDEV_CONFIG.SRC_SUBPORT_TABLE. */ +#define BCMPKT_RXPMD_ING_PP_PORT 86 +/*! Low 32 bits of the packet ARC_ID. */ +#define BCMPKT_RXPMD_ARC_ID_LO 87 +/*! High 18 bits of the packet ARC_ID. */ +#define BCMPKT_RXPMD_ARC_ID_HI 88 +/*! IEEE 802_1AS timestamp status. */ +#define BCMPKT_RXPMD_IEEE_802_1AS_TIMESTAMP_ENABLED 89 +/*! VRF */ +#define BCMPKT_RXPMD_VRF 90 +/*! RX chip port. */ +#define BCMPKT_RXPMD_RX_CHIP_PORT 91 +/*! VPP copy. */ +#define BCMPKT_RXPMD_VPP_COPY_TYPE 92 +/*! SV tag present status. */ +#define BCMPKT_RXPMD_SVTAG_PRESENT 93 +/*! Ingress vpp port. */ +#define BCMPKT_RXPMD_RX_VPP_PORT 94 +/*! Non switch copy. */ +#define BCMPKT_RXPMD_NONSW_COPY 95 +/*! */ +#define BCMPKT_RXPMD_MATCHED_RULE_EP 96 +/*! */ +#define BCMPKT_RXPMD_IS_EGR_TS 97 +/*! If set, then packet has been modified by the EP and CRC needs to be regenerated */ +#define BCMPKT_RXPMD_MODIFIED_PKT 98 +/*! RXPMD FIELD ID NUMBER */ +#define BCMPKT_RXPMD_FID_COUNT 99 +/*! \} */ + +/*! RXPMD field name strings for debugging. */ +#define BCMPKT_RXPMD_FIELD_NAME_MAP_INIT \ + {"UNICAST_QUEUE", BCMPKT_RXPMD_UNICAST_QUEUE},\ + {"QUEUE_NUM", BCMPKT_RXPMD_QUEUE_NUM},\ + {"CPU_COS", BCMPKT_RXPMD_CPU_COS},\ + {"HGI", BCMPKT_RXPMD_HGI},\ + {"MATCHED_RULE", BCMPKT_RXPMD_MATCHED_RULE},\ + {"PKT_LENGTH", BCMPKT_RXPMD_PKT_LENGTH},\ + {"SRC_PORT_NUM", BCMPKT_RXPMD_SRC_PORT_NUM},\ + {"INNER_VID", BCMPKT_RXPMD_INNER_VID},\ + {"INNER_CFI", BCMPKT_RXPMD_INNER_CFI},\ + {"INNER_PRI", BCMPKT_RXPMD_INNER_PRI},\ + {"OUTER_VID", BCMPKT_RXPMD_OUTER_VID},\ + {"OUTER_CFI", BCMPKT_RXPMD_OUTER_CFI},\ + {"OUTER_PRI", BCMPKT_RXPMD_OUTER_PRI},\ + {"SPECIAL_PACKET_INDICATOR", BCMPKT_RXPMD_SPECIAL_PACKET_INDICATOR},\ + {"SPECIAL_PACKET_TYPE", BCMPKT_RXPMD_SPECIAL_PACKET_TYPE},\ + {"CHANGE_DSCP", BCMPKT_RXPMD_CHANGE_DSCP},\ + {"DSCP", BCMPKT_RXPMD_DSCP},\ + {"CHANGE_ECN", BCMPKT_RXPMD_CHANGE_ECN},\ + {"ECN", BCMPKT_RXPMD_ECN},\ + {"TIMESTAMP_TYPE", BCMPKT_RXPMD_TIMESTAMP_TYPE},\ + {"TIMESTAMP", BCMPKT_RXPMD_TIMESTAMP},\ + {"TIMESTAMP_HI", BCMPKT_RXPMD_TIMESTAMP_HI},\ + {"MTP_INDEX", BCMPKT_RXPMD_MTP_INDEX},\ + {"BPDU", BCMPKT_RXPMD_BPDU},\ + {"REPLICATION", BCMPKT_RXPMD_REPLICATION},\ + {"L3ONLY", BCMPKT_RXPMD_L3ONLY},\ + {"IP_ROUTED", BCMPKT_RXPMD_IP_ROUTED},\ + {"SRC_HIGIG", BCMPKT_RXPMD_SRC_HIGIG},\ + {"SRC_HIGIG2", BCMPKT_RXPMD_SRC_HIGIG2},\ + {"UC_SW_COPY_DROPPED", BCMPKT_RXPMD_UC_SW_COPY_DROPPED},\ + {"SWITCH", BCMPKT_RXPMD_SWITCH},\ + {"SD_TAG_PRESENT", BCMPKT_RXPMD_SD_TAG_PRESENT},\ + {"ING_ITAG_ACTION", BCMPKT_RXPMD_ING_ITAG_ACTION},\ + {"ING_OTAG_ACTION", BCMPKT_RXPMD_ING_OTAG_ACTION},\ + {"ING_TAG_TYPE", BCMPKT_RXPMD_ING_TAG_TYPE},\ + {"ONE_STEP_1588_ING_UPDATE_DONE", BCMPKT_RXPMD_ONE_STEP_1588_ING_UPDATE_DONE},\ + {"EH_TAG", BCMPKT_RXPMD_EH_TAG},\ + {"EH_TYPE", BCMPKT_RXPMD_EH_TYPE},\ + {"EH_TYPE_0::EH_SEG_SEL", BCMPKT_RXPMD_EH_TYPE_0_EH_SEG_SEL},\ + {"EH_TYPE_0::EH_TAG_TYPE", BCMPKT_RXPMD_EH_TYPE_0_EH_TAG_TYPE},\ + {"EH_TYPE_0::EH_QUEUE_TAG", BCMPKT_RXPMD_EH_TYPE_0_EH_QUEUE_TAG},\ + {"EH_TYPE_1::CLASSID_TYPE", BCMPKT_RXPMD_EH_TYPE_1_CLASSID_TYPE},\ + {"EH_TYPE_1::L3_IIF", BCMPKT_RXPMD_EH_TYPE_1_L3_IIF},\ + {"EH_TYPE_1::CLASSID", BCMPKT_RXPMD_EH_TYPE_1_CLASSID},\ + {"EH_TYPE_2::CLASSID_TYPE", BCMPKT_RXPMD_EH_TYPE_2_CLASSID_TYPE},\ + {"EH_TYPE_2::CLASSID", BCMPKT_RXPMD_EH_TYPE_2_CLASSID},\ + {"EH_TYPE_2::EH_QUEUE_TAG", BCMPKT_RXPMD_EH_TYPE_2_EH_QUEUE_TAG},\ + {"RX_BFD_START_OFFSET", BCMPKT_RXPMD_RX_BFD_START_OFFSET},\ + {"RX_BFD_START_OFFSET_TYPE", BCMPKT_RXPMD_RX_BFD_START_OFFSET_TYPE},\ + {"RX_BFD_SESSION_INDEX", BCMPKT_RXPMD_RX_BFD_SESSION_INDEX},\ + {"REASON_TYPE", BCMPKT_RXPMD_REASON_TYPE},\ + {"DO_NOT_CHANGE_TTL", BCMPKT_RXPMD_DO_NOT_CHANGE_TTL},\ + {"I2E_CLASSID_TYPE", BCMPKT_RXPMD_I2E_CLASSID_TYPE},\ + {"I2E_CLASSID", BCMPKT_RXPMD_I2E_CLASSID},\ + {"ING_L3_INTF", BCMPKT_RXPMD_ING_L3_INTF},\ + {"LOOPBACK_PACKET_TYPE", BCMPKT_RXPMD_LOOPBACK_PACKET_TYPE},\ + {"REGEN_CRC", BCMPKT_RXPMD_REGEN_CRC},\ + {"ENTROPY_LABEL", BCMPKT_RXPMD_ENTROPY_LABEL},\ + {"TUNNEL_DECAP_TYPE", BCMPKT_RXPMD_TUNNEL_DECAP_TYPE},\ + {"DLB_ID_VALID", BCMPKT_RXPMD_DLB_ID_VALID},\ + {"DLB_ID", BCMPKT_RXPMD_DLB_ID},\ + {"HG2_EXT_HDR_VALID", BCMPKT_RXPMD_HG2_EXT_HDR_VALID},\ + {"VNTAG_ACTION", BCMPKT_RXPMD_VNTAG_ACTION},\ + {"DVP_NHI_SEL", BCMPKT_RXPMD_DVP_NHI_SEL},\ + {"VFI_VALID", BCMPKT_RXPMD_VFI_VALID},\ + {"REPLICATION_OR_NHOP_INDEX", BCMPKT_RXPMD_REPLICATION_OR_NHOP_INDEX},\ + {"MATCH_ID_LO", BCMPKT_RXPMD_MATCH_ID_LO},\ + {"MATCH_ID_HI", BCMPKT_RXPMD_MATCH_ID_HI},\ + {"MPB_FLEX_DATA_TYPE", BCMPKT_RXPMD_MPB_FLEX_DATA_TYPE},\ + {"INT_CN", BCMPKT_RXPMD_INT_CN},\ + {"CNG", BCMPKT_RXPMD_CNG},\ + {"EGR_ZONE_REMAP_CTRL", BCMPKT_RXPMD_EGR_ZONE_REMAP_CTRL},\ + {"DMA_HEADER_VERSION", BCMPKT_RXPMD_DMA_HEADER_VERSION},\ + {"MULTICAST", BCMPKT_RXPMD_MULTICAST},\ + {"COPY_TO_CPU", BCMPKT_RXPMD_COPY_TO_CPU},\ + {"TRUNCATE_CPU_COPY", BCMPKT_RXPMD_TRUNCATE_CPU_COPY},\ + {"INCOMING_INT_HDR_TYPE", BCMPKT_RXPMD_INCOMING_INT_HDR_TYPE},\ + {"DOP_TRIGGER", BCMPKT_RXPMD_DOP_TRIGGER},\ + {"EPARSE_EXTRACT_OFFSETS_3_0_OR_MIRROR_ENCAP_INDEX", BCMPKT_RXPMD_EPARSE_EXTRACT_OFFSETS_3_0_OR_MIRROR_ENCAP_INDEX},\ + {"EPARSE_EXTRACT_OFFSETS_7_4", BCMPKT_RXPMD_EPARSE_EXTRACT_OFFSETS_7_4},\ + {"ING_L3_INTF_VALID", BCMPKT_RXPMD_ING_L3_INTF_VALID},\ + {"O_NHI", BCMPKT_RXPMD_O_NHI},\ + {"IEU", BCMPKT_RXPMD_IEU},\ + {"IEU_VALID", BCMPKT_RXPMD_IEU_VALID},\ + {"INCOMING_OPAQUE_TAG_STATUS", BCMPKT_RXPMD_INCOMING_OPAQUE_TAG_STATUS},\ + {"EPARSE_EXTRACT_OFFSETS_6_4", BCMPKT_RXPMD_EPARSE_EXTRACT_OFFSETS_6_4},\ + {"ING_PP_PORT", BCMPKT_RXPMD_ING_PP_PORT},\ + {"ARC_ID_LO", BCMPKT_RXPMD_ARC_ID_LO},\ + {"ARC_ID_HI", BCMPKT_RXPMD_ARC_ID_HI},\ + {"IEEE_802_1AS_TIMESTAMP_ENABLED", BCMPKT_RXPMD_IEEE_802_1AS_TIMESTAMP_ENABLED},\ + {"VRF", BCMPKT_RXPMD_VRF},\ + {"RX_CHIP_PORT", BCMPKT_RXPMD_RX_CHIP_PORT},\ + {"VPP_COPY_TYPE", BCMPKT_RXPMD_VPP_COPY_TYPE},\ + {"SVTAG_PRESENT", BCMPKT_RXPMD_SVTAG_PRESENT},\ + {"RX_VPP_PORT", BCMPKT_RXPMD_RX_VPP_PORT},\ + {"NONSW_COPY", BCMPKT_RXPMD_NONSW_COPY},\ + {"MATCHED_RULE_EP", BCMPKT_RXPMD_MATCHED_RULE_EP},\ + {"IS_EGR_TS", BCMPKT_RXPMD_IS_EGR_TS},\ + {"MODIFIED_PKT", BCMPKT_RXPMD_MODIFIED_PKT},\ + {"fid count", BCMPKT_RXPMD_FID_COUNT} + +/*! + * \name BCMPKT_RXPMD_TIMESTAMP_TYPE encodings. + * \anchor BCMPKT_RXPMD_TIMESTAMP_TYPE_XXX + */ +/*! \{ */ +/*! */ +#define BCMPKT_RXPMD_TIMESTAMP_T_INVALID 0 +/*! */ +#define BCMPKT_RXPMD_TIMESTAMP_T_MMU_32NS 1 +/*! */ +#define BCMPKT_RXPMD_TIMESTAMP_T_OAM_LM 1 +/*! */ +#define BCMPKT_RXPMD_TIMESTAMP_T_OAM_DM 2 +/*! */ +#define BCMPKT_RXPMD_TIMESTAMP_T_PM_8NS 2 +/*! */ +#define BCMPKT_RXPMD_TIMESTAMP_T_IEEE_802_1AS 3 +/*! */ +#define BCMPKT_RXPMD_TIMESTAMP_T_PM_1NS 3 +/*! \} */ + +/*! BCMPKT_RXPMD_TIMESTAMP_TYPE encoding name strings for debugging. */ +#define BCMPKT_RXPMD_TIMESTAMP_TYPE_NAME_MAP_INIT \ + {"INVALID", BCMPKT_RXPMD_TIMESTAMP_T_INVALID},\ + {"MMU_32NS", BCMPKT_RXPMD_TIMESTAMP_T_MMU_32NS},\ + {"OAM_LM", BCMPKT_RXPMD_TIMESTAMP_T_OAM_LM},\ + {"OAM_DM", BCMPKT_RXPMD_TIMESTAMP_T_OAM_DM},\ + {"PM_8NS", BCMPKT_RXPMD_TIMESTAMP_T_PM_8NS},\ + {"IEEE_802_1AS", BCMPKT_RXPMD_TIMESTAMP_T_IEEE_802_1AS},\ + {"PM_1NS", BCMPKT_RXPMD_TIMESTAMP_T_PM_1NS},\ + +/*! + * \name BCMPKT_RXPMD_ING_TAG_TYPE encodings. + * \anchor BCMPKT_RXPMD_ING_TAG_TYPE_XXX + */ +/*! \{ */ +/*! No tag */ +#define BCMPKT_RXPMD_ING_TAG_T_NONE 0 +/*! Singgle inner tag */ +#define BCMPKT_RXPMD_ING_TAG_T_SINGLE_INNER 1 +/*! Tagged */ +#define BCMPKT_RXPMD_ING_TAG_T_TAGGED 1 +/*! Singgle outer tag */ +#define BCMPKT_RXPMD_ING_TAG_T_SINGLE_OUTER 2 +/*! Double tags */ +#define BCMPKT_RXPMD_ING_TAG_T_DOUBLE 3 +/*! \} */ + +/*! BCMPKT_RXPMD_ING_TAG_TYPE encoding name strings for debugging. */ +#define BCMPKT_RXPMD_ING_TAG_TYPE_NAME_MAP_INIT \ + {"NONE", BCMPKT_RXPMD_ING_TAG_T_NONE},\ + {"SINGLE_INNER", BCMPKT_RXPMD_ING_TAG_T_SINGLE_INNER},\ + {"TAGGED", BCMPKT_RXPMD_ING_TAG_T_TAGGED},\ + {"SINGLE_OUTER", BCMPKT_RXPMD_ING_TAG_T_SINGLE_OUTER},\ + {"DOUBLE", BCMPKT_RXPMD_ING_TAG_T_DOUBLE},\ + +/*! + * \name BCMPKT_RXPMD_EH_TYPE encodings. + * \anchor BCMPKT_RXPMD_EH_TYPE_XXX + */ +/*! \{ */ +/*! */ +#define BCMPKT_RXPMD_EH_T_0 0 +/*! */ +#define BCMPKT_RXPMD_EH_T_1 1 +/*! */ +#define BCMPKT_RXPMD_EH_T_2 2 +/*! \} */ + +/*! BCMPKT_RXPMD_EH_TYPE encoding name strings for debugging. */ +#define BCMPKT_RXPMD_EH_TYPE_NAME_MAP_INIT \ + {"EH_TYPE_0", BCMPKT_RXPMD_EH_T_0},\ + {"EH_TYPE_1", BCMPKT_RXPMD_EH_T_1},\ + {"EH_TYPE_2", BCMPKT_RXPMD_EH_T_2},\ + +/*! + * \name BCMPKT_RXPMD_REASON_TYPE encodings. + * \anchor BCMPKT_RXPMD_REASON_TYPE_XXX + */ +/*! \{ */ +/*! */ +#define BCMPKT_RXPMD_REASON_T_FROM_IP 0 +/*! */ +#define BCMPKT_RXPMD_REASON_T_FROM_EP 1 +/*! \} */ + +/*! BCMPKT_RXPMD_REASON_TYPE encoding name strings for debugging. */ +#define BCMPKT_RXPMD_REASON_TYPE_NAME_MAP_INIT \ + {"CTC_INITIATED_FROM_IP", BCMPKT_RXPMD_REASON_T_FROM_IP},\ + {"CTC_INITIATED_FROM_EP", BCMPKT_RXPMD_REASON_T_FROM_EP},\ + +/*! + * \name BCMPKT_RXPMD_TUNNEL_DECAP_TYPE encodings. + * \anchor BCMPKT_RXPMD_TUNNEL_DECAP_TYPE_XXX + */ +/*! \{ */ +/*! No decapsulation */ +#define BCMPKT_RXPMD_TUNNEL_DECAP_T_NONE 0 +/*! IP */ +#define BCMPKT_RXPMD_TUNNEL_DECAP_T_IP 1 +/*! L2 MPLS with one label */ +#define BCMPKT_RXPMD_TUNNEL_DECAP_T_L2MPLS_1LABEL 2 +/*! L2 MPLS with two labels */ +#define BCMPKT_RXPMD_TUNNEL_DECAP_T_L2MPLS_2LABEL 3 +/*! L2 MPLS with three labels */ +#define BCMPKT_RXPMD_TUNNEL_DECAP_T_L2MPLS_3LABEL 3 +/*! L3 MPLS with one label */ +#define BCMPKT_RXPMD_TUNNEL_DECAP_T_L3MPLS_1LABEL 5 +/*! L3 MPLS with two labels */ +#define BCMPKT_RXPMD_TUNNEL_DECAP_T_L3MPLS_2LABEL 6 +/*! L3 MPLS with three labels */ +#define BCMPKT_RXPMD_TUNNEL_DECAP_T_L3MPLS_3LABEL 7 +/*! VxLAN */ +#define BCMPKT_RXPMD_TUNNEL_DECAP_T_VXLAN 8 +/*! SRv6 with L2 */ +#define BCMPKT_RXPMD_TUNNEL_DECAP_T_SRV6_L2 9 +/*! SRv6 with SRH */ +#define BCMPKT_RXPMD_TUNNEL_DECAP_T_SRV6_SRH 10 +/*! \} */ + +/*! BCMPKT_RXPMD_TUNNEL_DECAP_TYPE encoding name strings for debugging. */ +#define BCMPKT_RXPMD_TUNNEL_DECAP_TYPE_NAME_MAP_INIT \ + {"NONE", BCMPKT_RXPMD_TUNNEL_DECAP_T_NONE},\ + {"IP", BCMPKT_RXPMD_TUNNEL_DECAP_T_IP},\ + {"L2MPLS_1LABEL", BCMPKT_RXPMD_TUNNEL_DECAP_T_L2MPLS_1LABEL},\ + {"L2MPLS_2LABEL", BCMPKT_RXPMD_TUNNEL_DECAP_T_L2MPLS_2LABEL},\ + {"L2MPLS_3LABEL", BCMPKT_RXPMD_TUNNEL_DECAP_T_L2MPLS_3LABEL},\ + {"L3MPLS_1LABEL", BCMPKT_RXPMD_TUNNEL_DECAP_T_L3MPLS_1LABEL},\ + {"L3MPLS_2LABEL", BCMPKT_RXPMD_TUNNEL_DECAP_T_L3MPLS_2LABEL},\ + {"L3MPLS_3LABEL", BCMPKT_RXPMD_TUNNEL_DECAP_T_L3MPLS_3LABEL},\ + {"VXLAN", BCMPKT_RXPMD_TUNNEL_DECAP_T_VXLAN},\ + {"SRV6_L2", BCMPKT_RXPMD_TUNNEL_DECAP_T_SRV6_L2},\ + {"SRV6_SRH", BCMPKT_RXPMD_TUNNEL_DECAP_T_SRV6_SRH},\ + +/*! + * \name RX packet metadata internal usage field IDs. + * \anchor BCMPKT_RXPMD_I_XXX + */ +/*! \{ */ +/*! Invalid BCMPKT_RXPMD_I FID indicator */ +#define BCMPKT_RXPMD_I_FID_INVALID -1 +/*! RXPMD raw data size. */ +#define BCMPKT_RXPMD_I_SIZE 0 +/*! Contains RX reasons. Refer to bcmpkt_rxpmd_reasons_get to decode reasons. */ +#define BCMPKT_RXPMD_I_REASON 1 +/*! Module Header information. Refer to Higig macros to encode/decode this erea. */ +#define BCMPKT_RXPMD_I_MODULE_HDR 2 +/*! MPB flex_data */ +#define BCMPKT_RXPMD_I_FLEX_DATA 3 +/*! RXPMD_I FIELD ID NUMBER */ +#define BCMPKT_RXPMD_I_FID_COUNT 4 +/*! \} */ + +/*! RXPMD_I field name strings for debugging. */ +#define BCMPKT_RXPMD_I_FIELD_NAME_MAP_INIT \ + {"SIZE", BCMPKT_RXPMD_I_SIZE},\ + {"REASON", BCMPKT_RXPMD_I_REASON},\ + {"MODULE_HDR", BCMPKT_RXPMD_I_MODULE_HDR},\ + {"FLEX_DATA", BCMPKT_RXPMD_I_FLEX_DATA},\ + {"fid count", BCMPKT_RXPMD_I_FID_COUNT} + +/*! + * \name Packet RX Reason Types. + * \anchor BCMPKT_RX_REASON_XXX + */ +/*! \{ */ +/*! No reason */ +#define BCMPKT_RX_REASON_NONE 0 +/*! Adapt miss. */ +#define BCMPKT_RX_REASON_ADAPT_MISS 1 +/*! IPMC interface mismatch */ +#define BCMPKT_RX_REASON_CPU_IPMC_INTERFACE_MISMATCH 2 +/*! Get: Indicate NAT REASON happened; Set: Configure NAT REASON mask. */ +#define BCMPKT_RX_REASON_NAT 3 +/*! TCP/UDP packet NAT lookup miss. */ +#define BCMPKT_RX_REASON_NAT_TCP_UDP_MISS 4 +/*! ICMP packet NAT lookup miss. */ +#define BCMPKT_RX_REASON_NAT_ICMP_MISS 5 +/*! NAT lookup on fragmented packet. */ +#define BCMPKT_RX_REASON_NAT_FRAGMENT 6 +/*! Non TCP/UDP/ICMP packet NAT lookup miss. */ +#define BCMPKT_RX_REASON_NAT_OTHER_MISS 7 +/*! FCOE zone check fail */ +#define BCMPKT_RX_REASON_FCOE_ZONE_CHECK_FAIL 11 +/*! VXLAN VNID miss */ +#define BCMPKT_RX_REASON_VXLAN_VN_ID_MISS 12 +/*! VXLAN SIP miss */ +#define BCMPKT_RX_REASON_VXLAN_SIP_MISS 13 +/*! QCN_CNM_PRP_DLF */ +#define BCMPKT_RX_REASON_QCN_CNM_PRP_DLF 14 +/*! QCN_CNM_PRP */ +#define BCMPKT_RX_REASON_QCN_CNM_PRP 15 +/*! MPLS_ALERT_LABEL */ +#define BCMPKT_RX_REASON_MPLS_ALERT_LABEL 16 +/*! MPLS_ILLEGAL_RESERVED_LABEL */ +#define BCMPKT_RX_REASON_MPLS_ILLEGAL_RESERVED_LABEL 17 +/*! ICNM */ +#define BCMPKT_RX_REASON_ICNM 18 +/*! Copy to CPU for visibility packet */ +#define BCMPKT_RX_REASON_PACKET_TRACE_TO_CPU 19 +/*! BFD Error */ +#define BCMPKT_RX_REASON_BFD_ERROR 20 +/*! BFD Slowpath to CPU */ +#define BCMPKT_RX_REASON_BFD_SLOWPATH 21 +/*! L2GRE_VPNID_MISS */ +#define BCMPKT_RX_REASON_L2GRE_VPNID_MISS 22 +/*! L2GRE_SIP_MISS */ +#define BCMPKT_RX_REASON_L2GRE_SIP_MISS 23 +/*! Get: Indicate TRILL REASON happened; Set: Configure TRILL REASON mask. */ +#define BCMPKT_RX_REASON_TRILL 24 +/*! Trill Header Error */ +#define BCMPKT_RX_REASON_TRILL_HDR_ERROR 25 +/*! Trill Lookup Miss */ +#define BCMPKT_RX_REASON_TRILL_LOOKUP_MISS 26 +/*! Trill RPF Check Fail */ +#define BCMPKT_RX_REASON_TRILL_RPF_CHECK_FAIL 27 +/*! Trill Slow Path */ +#define BCMPKT_RX_REASON_TRILL_SLOWPATH 28 +/*! Trill Core IS-IS */ +#define BCMPKT_RX_REASON_TRILL_CORE_IS_IS_PKT 29 +/*! Trill Hop Count Check Failure */ +#define BCMPKT_RX_REASON_TRILL_HOP_COUNT_CHECK_FAIL 30 +/*! Rbridge nickname lookup copy to cpu */ +#define BCMPKT_RX_REASON_TRILL_NICKNAME_TABLE 31 +/*! Tunnel decap ECN error */ +#define BCMPKT_RX_REASON_TUNNEL_DECAP_ECN_ERROR 32 +/*! OAM packets copied to the CPU for slowpath processing */ +#define BCMPKT_RX_REASON_OAM_SLOWPATH 33 +/*! + * Indicates packet was copied to CPU due to a network time sync packet. This is + * set either by dedicated IEEE 802.1AS controls or the FP. + */ +#define BCMPKT_RX_REASON_TIME_SYNC 34 +/*! Indicates packet was copied to the CPU due to VLAN Translation miss. */ +#define BCMPKT_RX_REASON_VXLT_MISS 35 +/*! Get: Indicate NIV REASON happened; Set: Configure NIV REASON mask. */ +#define BCMPKT_RX_REASON_NIV 36 +/*! Dot1p Admittance Discard */ +#define BCMPKT_RX_REASON_NIV_DOT1P_DROP 37 +/*! VIF Lookup Miss */ +#define BCMPKT_RX_REASON_NIV_VIF_MISS 38 +/*! RPF Lookup Miss */ +#define BCMPKT_RX_REASON_NIV_RPF_MISS 39 +/*! VNTAG Format Error */ +#define BCMPKT_RX_REASON_NIV_VNTAG_ERROR 40 +/*! VNTAG Present Drop */ +#define BCMPKT_RX_REASON_NIV_VNTAG_PRESENT 41 +/*! VNTAG Not Present Drop */ +#define BCMPKT_RX_REASON_NIV_VNTAG_NOT_PRESENT 42 +/*! Copy to CPU for MY_STATION match reason */ +#define BCMPKT_RX_REASON_MY_STATION 44 +/*! MPLS unknown ACH */ +#define BCMPKT_RX_REASON_MPLS_UNKNOWN_ACH_ERROR 45 +/*! ING_L3_NEXT_HOP table copy to CPU */ +#define BCMPKT_RX_REASON_L3_NEXT_HOP 46 +/*! Provider Backbone Transport pkt is not unicast */ +#define BCMPKT_RX_REASON_PBT_NONUC_PKT 47 +/*! Bit32 - MPLS sequence number check fail */ +#define BCMPKT_RX_REASON_MPLS_SEQ_NUM_FAIL 48 +/*! Bit31 - MPLS TTL check fail */ +#define BCMPKT_RX_REASON_MPLS_TTL_CHECK_FAIL 49 +/*! Bit30 - MPLS invalid payload */ +#define BCMPKT_RX_REASON_MPLS_INVALID_PAYLOAD 50 +/*! Bit29 - MPLS invalid label action */ +#define BCMPKT_RX_REASON_MPLS_INVALID_ACTION 51 +/*! Bit28 - MPLS label lookup miss */ +#define BCMPKT_RX_REASON_MPLS_LABEL_MISS 52 +/*! Copy to CPU for MAC to IP bind check failures */ +#define BCMPKT_RX_REASON_MAC_BIND_FAIL 53 +/*! Bit26 - CBSM_PREVENTED - copy to CPU */ +#define BCMPKT_RX_REASON_CBSM_PREVENTED 54 +/*! Bit25 - VFP Action - copy to CPU */ +#define BCMPKT_RX_REASON_CPU_VFP 55 +/*! Bit24 - Multicast index error */ +#define BCMPKT_RX_REASON_MCIDX_ERROR 56 +/*! Bit23 - HiGig Header error */ +#define BCMPKT_RX_REASON_HGHDR_ERROR 57 +/*! Bit22 - L3 MTU check fail to CPU */ +#define BCMPKT_RX_REASON_L3_MTU_CHECK_FAIL 58 +/*! Bit21 - Parity error on IP tables */ +#define BCMPKT_RX_REASON_PARITY_ERROR 59 +/*! Bit20 - L3 slow path CPU processed packets */ +#define BCMPKT_RX_REASON_L3_SLOWPATH 60 +/*! Bit19 - ICMP Redirect copy to CPU */ +#define BCMPKT_RX_REASON_ICMP_REDIRECT 61 +/*! Bit18 - Flex Sflow */ +#define BCMPKT_RX_REASON_CPU_SFLOW_FLEX 62 +/*! Bit17 - Tunnel error trap to CPU */ +#define BCMPKT_RX_REASON_CPU_TUNNEL_ERR 63 +/*! Bit16 - Martian address trap to CPU */ +#define BCMPKT_RX_REASON_CPU_MARTIAN_ADDR 64 +/*! Bit15 - DOS attack trap to CPU */ +#define BCMPKT_RX_REASON_CPU_DOS_ATTACK 65 +/*! Bit14 - Protocol Packet */ +#define BCMPKT_RX_REASON_CPU_PROTOCOL_PKT 66 +/*! Bit13 - L3 header - IP options, TTL=0, !IPv4 etc. */ +#define BCMPKT_RX_REASON_CPU_L3HDR_ERR 67 +/*! Bit12 - FFP Action - copy to CPU */ +#define BCMPKT_RX_REASON_CPU_FFP 68 +/*! Bit11 - IPMC miss - {SIP, DIP} miss or DIP miss */ +#define BCMPKT_RX_REASON_CPU_IPMC_MISS 69 +/*! Bit10 - MC miss */ +#define BCMPKT_RX_REASON_CPU_MC_MISS 70 +/*! Bit9 - Station Movement - L3 */ +#define BCMPKT_RX_REASON_CPU_L3SRC_MOVE 71 +/*! Bit8 - L3 DIP Miss */ +#define BCMPKT_RX_REASON_CPU_L3DST_MISS 72 +/*! Bit7 - L3 SIP Miss */ +#define BCMPKT_RX_REASON_CPU_L3SRC_MISS 73 +/*! Bit6 - sFlow - Dst */ +#define BCMPKT_RX_REASON_CPU_SFLOW_DST 74 +/*! Bit5 - sFlow - Src */ +#define BCMPKT_RX_REASON_CPU_SFLOW_SRC 75 +/*! Bit4 - L2_TABLE - copy to CPU */ +#define BCMPKT_RX_REASON_CPU_L2CPU 76 +/*! Bit3- Station Movement - L2 */ +#define BCMPKT_RX_REASON_CPU_L2MOVE 77 +/*! Bit2 - DLF, */ +#define BCMPKT_RX_REASON_CPU_DLF 78 +/*! Bit1 - SLF */ +#define BCMPKT_RX_REASON_CPU_SLF 79 +/*! Bit0- CPU Learn bit is set in PTABLE and SA is learnt; unknown VLAN; VID = 0xfff */ +#define BCMPKT_RX_REASON_CPU_UVLAN 80 +/*! Bit18 - protection data dropped packet copied to CPU */ +#define BCMPKT_RX_REASON_PROTECTION_DATA_DROP 81 +/*! OAM packets copied to the CPU for error cases */ +#define BCMPKT_RX_REASON_OAM_ERROR 82 +/*! Copy to CPU for OAM LMDM */ +#define BCMPKT_RX_REASON_OAM_LMDM 83 +/*! Get: Indicate SFLOW REASON happened; Set: Configure SFLOW REASON mask. */ +#define BCMPKT_RX_REASON_CPU_SFLOW 84 +/*! FP based Sflow */ +#define BCMPKT_RX_REASON_CPU_SFLOW_CPU_SFLOW_FLEX 85 +/*! Egress port-based Sflow */ +#define BCMPKT_RX_REASON_CPU_SFLOW_CPU_SFLOW_DST 86 +/*! Ingress port-based Sflow */ +#define BCMPKT_RX_REASON_CPU_SFLOW_CPU_SFLOW_SRC 87 +/*! Get: Indicate SFLOW REASON happened; Set: Configure SFLOW REASON mask. */ +#define BCMPKT_RX_REASON_MPLS_PROC_ERROR 88 +/*! Invalid payload. */ +#define BCMPKT_RX_REASON_MPLS_PROC_ERROR_INVALID_PAYLOAD 89 +/*! Invalid action. */ +#define BCMPKT_RX_REASON_MPLS_PROC_ERROR_INVALID_ACTION 90 +/*! Lookup label miss. */ +#define BCMPKT_RX_REASON_MPLS_PROC_ERROR_LABEL_MISS 91 +/*! TTL check fail. */ +#define BCMPKT_RX_REASON_MPLS_PROC_ERROR_TTL_CHECK_FAIL 92 +/*! TBD. */ +#define BCMPKT_RX_REASON_MPLS_UNKNOWN_CONTROL_PKT 96 +/*! Copied to CPU by ETRAP monitor. */ +#define BCMPKT_RX_REASON_ETRAP_MONITOR 97 +/*! Copied to CPU by Inband Telemetry turnaround. */ +#define BCMPKT_RX_REASON_INT_TURN_AROUND 98 +/*! Copied to CPU by DLB monitor. */ +#define BCMPKT_RX_REASON_DLB_MONITOR 99 +/*! Bit13 - L3 header - IP options, TTL=0, !IPv4 etc. */ +#define BCMPKT_RX_REASON_CPU_L3_HDR_MISMATCH 100 +/*! Bit31 - tunnel with object validation check fail */ +#define BCMPKT_RX_REASON_TUNNEL_OBJECT_VALIDATION_FAIL 101 +/*! L3 copy to CPU. */ +#define BCMPKT_RX_REASON_CPU_L3CPU 102 +/*! VNTAG unknown SUBTENDING port */ +#define BCMPKT_RX_REASON_VNTAG_UNKNOWN_SUBTENDING_PORT_ERROR 103 +/*! RPF Lookup Miss */ +#define BCMPKT_RX_REASON_RPF_MISS 104 +/*! Dot1p Admittance Discard */ +#define BCMPKT_RX_REASON_DOT1P_ADMITTANCE_DISCARD 105 +/*! + * It should be renamed to TUNNEL_ADAPT_LOOKUP_CPU. Indicates packet was copied + * to the CPU due to TUNNEL_ADAPT_LOOKUP's miss policy or hit policy copy to cpu. + */ +#define BCMPKT_RX_REASON_TUNNEL_ADAPT_LOOKUP_MISS_DROP 106 +/*! PKT_FLOW_SELECT_MISS_TO_CPU */ +#define BCMPKT_RX_REASON_PKT_FLOW_SELECT_MISS 107 +/*! Indicates packet was copied to the CPU due to PKT_FLOW_SELECT policy. */ +#define BCMPKT_RX_REASON_PKT_FLOW_SELECT 108 +/*! + * It should be renamed to TUNNEL_ADAPT_LOOKUP_MISS_TO_CPU_FROM_LOGICAL_TABLE_SEL. + * Indicates packet was copied to the CPU due to FORWARDING_LOOKUP miss. + */ +#define BCMPKT_RX_REASON_CPU_FORWARDING_OTHER 109 +/*! */ +#define BCMPKT_RX_REASON_INVALID_TPID 110 +/*! */ +#define BCMPKT_RX_REASON_MPLS_CONTROL_PKT 111 +/*! TUNNEL_ERR_TO_CPU */ +#define BCMPKT_RX_REASON_TUNNEL_ERR 112 +/*! TUNNEL_TTL_ERR_TO_CPU Error */ +#define BCMPKT_RX_REASON_TUNNEL_TTL_ERR 113 +/*! */ +#define BCMPKT_RX_REASON_L3_HDR_ERROR 114 +/*! */ +#define BCMPKT_RX_REASON_L2_HDR_ERROR 115 +/*! */ +#define BCMPKT_RX_REASON_TTL1_ERR 116 +/*! */ +#define BCMPKT_RX_REASON_TTL_ERR 117 +/*! Nat error packet. */ +#define BCMPKT_RX_REASON_NAT_ERROR 118 +/*! L2 MTU check fail to CPU */ +#define BCMPKT_RX_REASON_L2_MTU_CHECK_FAIL 119 +/*! Over system MAC limit threshold to CPU */ +#define BCMPKT_RX_REASON_L2_MAC_LIMIT 120 +/*! L2 STU check fail to CPU */ +#define BCMPKT_RX_REASON_L2_STU_CHECK_FAIL 121 +/*! SR counter threshold exceeded to CPU. */ +#define BCMPKT_RX_REASON_SR_COUNTER_LIMIT 122 +/*! SRV6_PROC_ERROR */ +#define BCMPKT_RX_REASON_SRV6_ERROR 123 +/*! Protection status = down. */ +#define BCMPKT_RX_REASON_NH_PROTO_STATUS_DOWN 124 +/*! Invalid opcode. */ +#define BCMPKT_RX_REASON_CPU_INVALID_REASON 125 +/*! MPLS TTL Check. */ +#define BCMPKT_RX_REASON_MPLS_TTL_CHECK 126 +/*! Bit Definitions of the CPU Opcodes. */ +#define BCMPKT_RX_REASON_SVTAG_CPU_BIT_SET 127 +/*! Subport ID lookup miss in Channelization. */ +#define BCMPKT_RX_REASON_SUBPORT_ID_LOOKUP_MISS 128 +/*! OAM operation. */ +#define BCMPKT_RX_REASON_OAM_PROCESSING 129 +/*! Invalid. */ +#define BCMPKT_RX_REASON_OAM_PROCESSING_INVALID 130 +/*! OAM CCM. */ +#define BCMPKT_RX_REASON_OAM_PROCESSING_OAM_CCM 131 +/*! OAM LM. */ +#define BCMPKT_RX_REASON_OAM_PROCESSING_OAM_LM 132 +/*! OAM DM. */ +#define BCMPKT_RX_REASON_OAM_PROCESSING_OAM_DM 133 +/*! OAM Other opcodes. */ +#define BCMPKT_RX_REASON_OAM_PROCESSING_OAM_OTHER_OPCODES 134 +/*! Invalid GSH or NON_GSH packet based on port configuration. */ +#define BCMPKT_RX_REASON_INVALID_GSH_NON_GSH 137 +/*! Copy to CPU triggered at egress pipeline. */ +#define BCMPKT_RX_REASON_EP_CTC 138 +/*! APU Policy CTC. */ +#define BCMPKT_RX_REASON_APU_POLICY_CTC 139 +/*! Delayed CTC. */ +#define BCMPKT_RX_REASON_DELAYED_CTC 140 +/*! Indicates Copy to CPU is for PORT_DOWN event. */ +#define BCMPKT_RX_REASON_PORT_DOWN 141 +/*! SRV6 Control Packet */ +#define BCMPKT_RX_REASON_SRV6_CONTROL_PKT 142 +/*! OUI Compression miss */ +#define BCMPKT_RX_REASON_OUI_COMPRESSION_MISS 143 +/*! BCMPKT_RX_REASON TYPE NUMBER */ +#define BCMPKT_RX_REASON_COUNT 144 +/*! \} */ + +/*! RXPMD reason name strings for debugging. */ +#define BCMPKT_REASON_NAME_MAP_INIT \ + {"NONE", BCMPKT_RX_REASON_NONE},\ + {"ADAPT_MISS", BCMPKT_RX_REASON_ADAPT_MISS},\ + {"CPU_IPMC_INTERFACE_MISMATCH", BCMPKT_RX_REASON_CPU_IPMC_INTERFACE_MISMATCH},\ + {"NAT", BCMPKT_RX_REASON_NAT},\ + {"NAT_TCP_UDP_MISS", BCMPKT_RX_REASON_NAT_TCP_UDP_MISS},\ + {"NAT_ICMP_MISS", BCMPKT_RX_REASON_NAT_ICMP_MISS},\ + {"NAT_FRAGMENT", BCMPKT_RX_REASON_NAT_FRAGMENT},\ + {"NAT_OTHER_MISS", BCMPKT_RX_REASON_NAT_OTHER_MISS},\ + {"RESERVED_REASON", 8},\ + {"RESERVED_REASON", 9},\ + {"RESERVED_REASON", 10},\ + {"FCOE_ZONE_CHECK_FAIL", BCMPKT_RX_REASON_FCOE_ZONE_CHECK_FAIL},\ + {"VXLAN_VN_ID_MISS", BCMPKT_RX_REASON_VXLAN_VN_ID_MISS},\ + {"VXLAN_SIP_MISS", BCMPKT_RX_REASON_VXLAN_SIP_MISS},\ + {"QCN_CNM_PRP_DLF", BCMPKT_RX_REASON_QCN_CNM_PRP_DLF},\ + {"QCN_CNM_PRP", BCMPKT_RX_REASON_QCN_CNM_PRP},\ + {"MPLS_ALERT_LABEL", BCMPKT_RX_REASON_MPLS_ALERT_LABEL},\ + {"MPLS_ILLEGAL_RESERVED_LABEL", BCMPKT_RX_REASON_MPLS_ILLEGAL_RESERVED_LABEL},\ + {"ICNM", BCMPKT_RX_REASON_ICNM},\ + {"PACKET_TRACE_TO_CPU", BCMPKT_RX_REASON_PACKET_TRACE_TO_CPU},\ + {"BFD_ERROR", BCMPKT_RX_REASON_BFD_ERROR},\ + {"BFD_SLOWPATH", BCMPKT_RX_REASON_BFD_SLOWPATH},\ + {"L2GRE_VPNID_MISS", BCMPKT_RX_REASON_L2GRE_VPNID_MISS},\ + {"L2GRE_SIP_MISS", BCMPKT_RX_REASON_L2GRE_SIP_MISS},\ + {"TRILL", BCMPKT_RX_REASON_TRILL},\ + {"TRILL_HDR_ERROR", BCMPKT_RX_REASON_TRILL_HDR_ERROR},\ + {"TRILL_LOOKUP_MISS", BCMPKT_RX_REASON_TRILL_LOOKUP_MISS},\ + {"TRILL_RPF_CHECK_FAIL", BCMPKT_RX_REASON_TRILL_RPF_CHECK_FAIL},\ + {"TRILL_SLOWPATH", BCMPKT_RX_REASON_TRILL_SLOWPATH},\ + {"TRILL_CORE_IS_IS_PKT", BCMPKT_RX_REASON_TRILL_CORE_IS_IS_PKT},\ + {"TRILL_HOP_COUNT_CHECK_FAIL", BCMPKT_RX_REASON_TRILL_HOP_COUNT_CHECK_FAIL},\ + {"TRILL_NICKNAME_TABLE", BCMPKT_RX_REASON_TRILL_NICKNAME_TABLE},\ + {"TUNNEL_DECAP_ECN_ERROR", BCMPKT_RX_REASON_TUNNEL_DECAP_ECN_ERROR},\ + {"OAM_SLOWPATH", BCMPKT_RX_REASON_OAM_SLOWPATH},\ + {"TIME_SYNC", BCMPKT_RX_REASON_TIME_SYNC},\ + {"VXLT_MISS", BCMPKT_RX_REASON_VXLT_MISS},\ + {"NIV", BCMPKT_RX_REASON_NIV},\ + {"NIV_DOT1P_DROP", BCMPKT_RX_REASON_NIV_DOT1P_DROP},\ + {"NIV_VIF_MISS", BCMPKT_RX_REASON_NIV_VIF_MISS},\ + {"NIV_RPF_MISS", BCMPKT_RX_REASON_NIV_RPF_MISS},\ + {"NIV_VNTAG_ERROR", BCMPKT_RX_REASON_NIV_VNTAG_ERROR},\ + {"NIV_VNTAG_PRESENT", BCMPKT_RX_REASON_NIV_VNTAG_PRESENT},\ + {"NIV_VNTAG_NOT_PRESENT", BCMPKT_RX_REASON_NIV_VNTAG_NOT_PRESENT},\ + {"RESERVED_REASON", 43},\ + {"MY_STATION", BCMPKT_RX_REASON_MY_STATION},\ + {"MPLS_UNKNOWN_ACH_ERROR", BCMPKT_RX_REASON_MPLS_UNKNOWN_ACH_ERROR},\ + {"L3_NEXT_HOP", BCMPKT_RX_REASON_L3_NEXT_HOP},\ + {"PBT_NONUC_PKT", BCMPKT_RX_REASON_PBT_NONUC_PKT},\ + {"MPLS_SEQ_NUM_FAIL", BCMPKT_RX_REASON_MPLS_SEQ_NUM_FAIL},\ + {"MPLS_TTL_CHECK_FAIL", BCMPKT_RX_REASON_MPLS_TTL_CHECK_FAIL},\ + {"MPLS_INVALID_PAYLOAD", BCMPKT_RX_REASON_MPLS_INVALID_PAYLOAD},\ + {"MPLS_INVALID_ACTION", BCMPKT_RX_REASON_MPLS_INVALID_ACTION},\ + {"MPLS_LABEL_MISS", BCMPKT_RX_REASON_MPLS_LABEL_MISS},\ + {"MAC_BIND_FAIL", BCMPKT_RX_REASON_MAC_BIND_FAIL},\ + {"CBSM_PREVENTED", BCMPKT_RX_REASON_CBSM_PREVENTED},\ + {"CPU_VFP", BCMPKT_RX_REASON_CPU_VFP},\ + {"MCIDX_ERROR", BCMPKT_RX_REASON_MCIDX_ERROR},\ + {"HGHDR_ERROR", BCMPKT_RX_REASON_HGHDR_ERROR},\ + {"L3_MTU_CHECK_FAIL", BCMPKT_RX_REASON_L3_MTU_CHECK_FAIL},\ + {"PARITY_ERROR", BCMPKT_RX_REASON_PARITY_ERROR},\ + {"L3_SLOWPATH", BCMPKT_RX_REASON_L3_SLOWPATH},\ + {"ICMP_REDIRECT", BCMPKT_RX_REASON_ICMP_REDIRECT},\ + {"CPU_SFLOW_FLEX", BCMPKT_RX_REASON_CPU_SFLOW_FLEX},\ + {"CPU_TUNNEL_ERR", BCMPKT_RX_REASON_CPU_TUNNEL_ERR},\ + {"CPU_MARTIAN_ADDR", BCMPKT_RX_REASON_CPU_MARTIAN_ADDR},\ + {"CPU_DOS_ATTACK", BCMPKT_RX_REASON_CPU_DOS_ATTACK},\ + {"CPU_PROTOCOL_PKT", BCMPKT_RX_REASON_CPU_PROTOCOL_PKT},\ + {"CPU_L3HDR_ERR", BCMPKT_RX_REASON_CPU_L3HDR_ERR},\ + {"CPU_FFP", BCMPKT_RX_REASON_CPU_FFP},\ + {"CPU_IPMC_MISS", BCMPKT_RX_REASON_CPU_IPMC_MISS},\ + {"CPU_MC_MISS", BCMPKT_RX_REASON_CPU_MC_MISS},\ + {"CPU_L3SRC_MOVE", BCMPKT_RX_REASON_CPU_L3SRC_MOVE},\ + {"CPU_L3DST_MISS", BCMPKT_RX_REASON_CPU_L3DST_MISS},\ + {"CPU_L3SRC_MISS", BCMPKT_RX_REASON_CPU_L3SRC_MISS},\ + {"CPU_SFLOW_DST", BCMPKT_RX_REASON_CPU_SFLOW_DST},\ + {"CPU_SFLOW_SRC", BCMPKT_RX_REASON_CPU_SFLOW_SRC},\ + {"CPU_L2CPU", BCMPKT_RX_REASON_CPU_L2CPU},\ + {"CPU_L2MOVE", BCMPKT_RX_REASON_CPU_L2MOVE},\ + {"CPU_DLF", BCMPKT_RX_REASON_CPU_DLF},\ + {"CPU_SLF", BCMPKT_RX_REASON_CPU_SLF},\ + {"CPU_UVLAN", BCMPKT_RX_REASON_CPU_UVLAN},\ + {"PROTECTION_DATA_DROP", BCMPKT_RX_REASON_PROTECTION_DATA_DROP},\ + {"OAM_ERROR", BCMPKT_RX_REASON_OAM_ERROR},\ + {"OAM_LMDM", BCMPKT_RX_REASON_OAM_LMDM},\ + {"CPU_SFLOW", BCMPKT_RX_REASON_CPU_SFLOW},\ + {"CPU_SFLOW_CPU_SFLOW_FLEX", BCMPKT_RX_REASON_CPU_SFLOW_CPU_SFLOW_FLEX},\ + {"CPU_SFLOW_CPU_SFLOW_DST", BCMPKT_RX_REASON_CPU_SFLOW_CPU_SFLOW_DST},\ + {"CPU_SFLOW_CPU_SFLOW_SRC", BCMPKT_RX_REASON_CPU_SFLOW_CPU_SFLOW_SRC},\ + {"MPLS_PROC_ERROR", BCMPKT_RX_REASON_MPLS_PROC_ERROR},\ + {"MPLS_PROC_ERROR_INVALID_PAYLOAD", BCMPKT_RX_REASON_MPLS_PROC_ERROR_INVALID_PAYLOAD},\ + {"MPLS_PROC_ERROR_INVALID_ACTION", BCMPKT_RX_REASON_MPLS_PROC_ERROR_INVALID_ACTION},\ + {"MPLS_PROC_ERROR_LABEL_MISS", BCMPKT_RX_REASON_MPLS_PROC_ERROR_LABEL_MISS},\ + {"MPLS_PROC_ERROR_TTL_CHECK_FAIL", BCMPKT_RX_REASON_MPLS_PROC_ERROR_TTL_CHECK_FAIL},\ + {"RESERVED_REASON", 93},\ + {"RESERVED_REASON", 94},\ + {"RESERVED_REASON", 95},\ + {"MPLS_UNKNOWN_CONTROL_PKT", BCMPKT_RX_REASON_MPLS_UNKNOWN_CONTROL_PKT},\ + {"ETRAP_MONITOR", BCMPKT_RX_REASON_ETRAP_MONITOR},\ + {"INT_TURN_AROUND", BCMPKT_RX_REASON_INT_TURN_AROUND},\ + {"DLB_MONITOR", BCMPKT_RX_REASON_DLB_MONITOR},\ + {"CPU_L3_HDR_MISMATCH", BCMPKT_RX_REASON_CPU_L3_HDR_MISMATCH},\ + {"TUNNEL_OBJECT_VALIDATION_FAIL", BCMPKT_RX_REASON_TUNNEL_OBJECT_VALIDATION_FAIL},\ + {"CPU_L3CPU", BCMPKT_RX_REASON_CPU_L3CPU},\ + {"VNTAG_UNKNOWN_SUBTENDING_PORT_ERROR", BCMPKT_RX_REASON_VNTAG_UNKNOWN_SUBTENDING_PORT_ERROR},\ + {"RPF_MISS", BCMPKT_RX_REASON_RPF_MISS},\ + {"DOT1P_ADMITTANCE_DISCARD", BCMPKT_RX_REASON_DOT1P_ADMITTANCE_DISCARD},\ + {"TUNNEL_ADAPT_LOOKUP_MISS_DROP", BCMPKT_RX_REASON_TUNNEL_ADAPT_LOOKUP_MISS_DROP},\ + {"PKT_FLOW_SELECT_MISS", BCMPKT_RX_REASON_PKT_FLOW_SELECT_MISS},\ + {"PKT_FLOW_SELECT", BCMPKT_RX_REASON_PKT_FLOW_SELECT},\ + {"CPU_FORWARDING_OTHER", BCMPKT_RX_REASON_CPU_FORWARDING_OTHER},\ + {"INVALID_TPID", BCMPKT_RX_REASON_INVALID_TPID},\ + {"MPLS_CONTROL_PKT", BCMPKT_RX_REASON_MPLS_CONTROL_PKT},\ + {"TUNNEL_ERR", BCMPKT_RX_REASON_TUNNEL_ERR},\ + {"TUNNEL_TTL_ERR", BCMPKT_RX_REASON_TUNNEL_TTL_ERR},\ + {"L3_HDR_ERROR", BCMPKT_RX_REASON_L3_HDR_ERROR},\ + {"L2_HDR_ERROR", BCMPKT_RX_REASON_L2_HDR_ERROR},\ + {"TTL1_ERR", BCMPKT_RX_REASON_TTL1_ERR},\ + {"TTL_ERR", BCMPKT_RX_REASON_TTL_ERR},\ + {"NAT_ERROR", BCMPKT_RX_REASON_NAT_ERROR},\ + {"L2_MTU_CHECK_FAIL", BCMPKT_RX_REASON_L2_MTU_CHECK_FAIL},\ + {"L2_MAC_LIMIT", BCMPKT_RX_REASON_L2_MAC_LIMIT},\ + {"L2_STU_CHECK_FAIL", BCMPKT_RX_REASON_L2_STU_CHECK_FAIL},\ + {"SR_COUNTER_LIMIT", BCMPKT_RX_REASON_SR_COUNTER_LIMIT},\ + {"SRV6_ERROR", BCMPKT_RX_REASON_SRV6_ERROR},\ + {"NH_PROTO_STATUS_DOWN", BCMPKT_RX_REASON_NH_PROTO_STATUS_DOWN},\ + {"CPU_INVALID_REASON", BCMPKT_RX_REASON_CPU_INVALID_REASON},\ + {"MPLS_TTL_CHECK", BCMPKT_RX_REASON_MPLS_TTL_CHECK},\ + {"SVTAG_CPU_BIT_SET", BCMPKT_RX_REASON_SVTAG_CPU_BIT_SET},\ + {"SUBPORT_ID_LOOKUP_MISS", BCMPKT_RX_REASON_SUBPORT_ID_LOOKUP_MISS},\ + {"OAM_PROCESSING", BCMPKT_RX_REASON_OAM_PROCESSING},\ + {"OAM_PROCESSING_INVALID", BCMPKT_RX_REASON_OAM_PROCESSING_INVALID},\ + {"OAM_PROCESSING_OAM_CCM", BCMPKT_RX_REASON_OAM_PROCESSING_OAM_CCM},\ + {"OAM_PROCESSING_OAM_LM", BCMPKT_RX_REASON_OAM_PROCESSING_OAM_LM},\ + {"OAM_PROCESSING_OAM_DM", BCMPKT_RX_REASON_OAM_PROCESSING_OAM_DM},\ + {"OAM_PROCESSING_OAM_OTHER_OPCODES", BCMPKT_RX_REASON_OAM_PROCESSING_OAM_OTHER_OPCODES},\ + {"RESERVED_REASON", 135},\ + {"RESERVED_REASON", 136},\ + {"INVALID_GSH_NON_GSH", BCMPKT_RX_REASON_INVALID_GSH_NON_GSH},\ + {"EP_CTC", BCMPKT_RX_REASON_EP_CTC},\ + {"APU_POLICY_CTC", BCMPKT_RX_REASON_APU_POLICY_CTC},\ + {"DELAYED_CTC", BCMPKT_RX_REASON_DELAYED_CTC},\ + {"PORT_DOWN", BCMPKT_RX_REASON_PORT_DOWN},\ + {"SRV6_CONTROL_PKT", BCMPKT_RX_REASON_SRV6_CONTROL_PKT},\ + {"OUI_COMPRESSION_MISS", BCMPKT_RX_REASON_OUI_COMPRESSION_MISS},\ + {"reason count", BCMPKT_RX_REASON_COUNT} + +/*! + * \name RX packet metadata field IDs on DNX. + * \anchor BCMPKT_RXPMD_XXX + */ + +/*! \{ */ + +/*! Invalid BCMPKT_RXPMD FID indicator */ +#define BCMPKT_RXPMD_DNX_FID_INVALID -1 +/*! Length of system headers */ +#define BCMPKT_RXPMD_SYSTEM_HEADER_LENGTH 0 +/*! The receiving DMA channel */ +#define BCMPKT_RXPMD_RX_CHANNEL 1 +/*! Traffic Class */ +#define BCMPKT_RXPMD_FTMH_TC 2 +/*! Source System Gport */ +#define BCMPKT_RXPMD_FTMH_SRC_SYSPORT 3 +/*! Trap ID */ +#define BCMPKT_RXPMD_INTERNAL_TRAP_ID 4 +/*! Trap Qualifier */ +#define BCMPKT_RXPMD_INTERNAL_TRAP_QUALIFIER 5 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_6 6 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_7 7 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_8 8 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_9 9 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_10 10 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_11 11 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_12 12 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_13 13 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_14 14 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_15 15 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_16 16 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_17 17 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_18 18 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_19 19 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_20 20 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_21 21 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_22 22 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_23 23 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_24 24 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_25 25 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_26 26 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_27 27 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_28 28 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_29 29 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_30 30 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_31 31 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_32 32 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_33 33 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_34 34 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_35 35 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_36 36 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_37 37 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_38 38 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_39 39 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_40 40 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_41 41 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_42 42 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_43 43 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_44 44 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_45 45 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_46 46 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_47 47 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_48 48 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_49 49 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_50 50 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_51 51 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_52 52 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_53 53 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_54 54 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_55 55 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_56 56 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_57 57 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_58 58 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_59 59 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_60 60 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_61 61 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_62 62 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_63 63 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_64 64 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_65 65 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_66 66 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_67 67 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_68 68 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_69 69 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_70 70 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_71 71 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_72 72 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_73 73 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_74 74 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_75 75 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_76 76 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_77 77 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_78 78 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_79 79 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_80 80 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_81 81 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_82 82 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_83 83 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_84 84 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_85 85 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_86 86 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_87 87 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_88 88 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_89 89 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_90 90 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_91 91 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_92 92 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_93 93 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_94 94 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_95 95 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_96 96 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_97 97 +/*! Reserved */ +#define BCMPKT_RXPMD_DNX_RESV_98 98 + +/*! BCMPKT_RXPMD_FID_COUNT */ +#define BCMPKT_RXPMD_DNX_FID_COUNT 99 +/*! \} */ + +/*! RXPMD field name strings for debugging. */ +#define BCMPKT_RXPMD_DNX_FIELD_NAME_MAP_INIT \ + {"SYSTEM_HEADER_LENGTH", BCMPKT_RXPMD_SYSTEM_HEADER_LENGTH},\ + {"RX_CHANNEL", BCMPKT_RXPMD_RX_CHANNEL},\ + {"TRAFFIC_CLASS", BCMPKT_RXPMD_FTMH_TC},\ + {"SRC_SYSPORT", BCMPKT_RXPMD_FTMH_SRC_SYSPORT},\ + {"TRAP_ID", BCMPKT_RXPMD_INTERNAL_TRAP_ID},\ + {"TRAP_QUALIFIER", BCMPKT_RXPMD_INTERNAL_TRAP_QUALIFIER},\ + {"Reserved_6", BCMPKT_RXPMD_DNX_RESV_6},\ + {"Reserved_7", BCMPKT_RXPMD_DNX_RESV_7},\ + {"Reserved_8", BCMPKT_RXPMD_DNX_RESV_8},\ + {"Reserved_9", BCMPKT_RXPMD_DNX_RESV_9},\ + {"Reserved_10", BCMPKT_RXPMD_DNX_RESV_10},\ + {"Reserved_11", BCMPKT_RXPMD_DNX_RESV_11},\ + {"Reserved_12", BCMPKT_RXPMD_DNX_RESV_12},\ + {"Reserved_13", BCMPKT_RXPMD_DNX_RESV_13},\ + {"Reserved_14", BCMPKT_RXPMD_DNX_RESV_14},\ + {"Reserved_15", BCMPKT_RXPMD_DNX_RESV_15},\ + {"Reserved_16", BCMPKT_RXPMD_DNX_RESV_16},\ + {"Reserved_17", BCMPKT_RXPMD_DNX_RESV_17},\ + {"Reserved_18", BCMPKT_RXPMD_DNX_RESV_18},\ + {"Reserved_19", BCMPKT_RXPMD_DNX_RESV_19},\ + {"Reserved_20", BCMPKT_RXPMD_DNX_RESV_20},\ + {"Reserved_21", BCMPKT_RXPMD_DNX_RESV_21},\ + {"Reserved_22", BCMPKT_RXPMD_DNX_RESV_22},\ + {"Reserved_23", BCMPKT_RXPMD_DNX_RESV_23},\ + {"Reserved_24", BCMPKT_RXPMD_DNX_RESV_24},\ + {"Reserved_25", BCMPKT_RXPMD_DNX_RESV_25},\ + {"Reserved_26", BCMPKT_RXPMD_DNX_RESV_26},\ + {"Reserved_27", BCMPKT_RXPMD_DNX_RESV_27},\ + {"Reserved_28", BCMPKT_RXPMD_DNX_RESV_28},\ + {"Reserved_30", BCMPKT_RXPMD_DNX_RESV_29},\ + {"Reserved_31", BCMPKT_RXPMD_DNX_RESV_30},\ + {"Reserved_32", BCMPKT_RXPMD_DNX_RESV_31},\ + {"Reserved_33", BCMPKT_RXPMD_DNX_RESV_32},\ + {"Reserved_34", BCMPKT_RXPMD_DNX_RESV_33},\ + {"Reserved_35", BCMPKT_RXPMD_DNX_RESV_34},\ + {"Reserved_36", BCMPKT_RXPMD_DNX_RESV_35},\ + {"Reserved_37", BCMPKT_RXPMD_DNX_RESV_36},\ + {"Reserved_38", BCMPKT_RXPMD_DNX_RESV_37},\ + {"Reserved_39", BCMPKT_RXPMD_DNX_RESV_38},\ + {"Reserved_40", BCMPKT_RXPMD_DNX_RESV_39},\ + {"Reserved_41", BCMPKT_RXPMD_DNX_RESV_40},\ + {"Reserved_42", BCMPKT_RXPMD_DNX_RESV_41},\ + {"Reserved_43", BCMPKT_RXPMD_DNX_RESV_42},\ + {"Reserved_44", BCMPKT_RXPMD_DNX_RESV_43},\ + {"Reserved_45", BCMPKT_RXPMD_DNX_RESV_44},\ + {"Reserved_46", BCMPKT_RXPMD_DNX_RESV_45},\ + {"Reserved_47", BCMPKT_RXPMD_DNX_RESV_46},\ + {"Reserved_48", BCMPKT_RXPMD_DNX_RESV_47},\ + {"Reserved_49", BCMPKT_RXPMD_DNX_RESV_48},\ + {"Reserved_50", BCMPKT_RXPMD_DNX_RESV_50},\ + {"Reserved_51", BCMPKT_RXPMD_DNX_RESV_51},\ + {"Reserved_52", BCMPKT_RXPMD_DNX_RESV_52},\ + {"Reserved_53", BCMPKT_RXPMD_DNX_RESV_53},\ + {"Reserved_54", BCMPKT_RXPMD_DNX_RESV_54},\ + {"Reserved_55", BCMPKT_RXPMD_DNX_RESV_55},\ + {"Reserved_56", BCMPKT_RXPMD_DNX_RESV_56},\ + {"Reserved_57", BCMPKT_RXPMD_DNX_RESV_57},\ + {"Reserved_58", BCMPKT_RXPMD_DNX_RESV_58},\ + {"Reserved_59", BCMPKT_RXPMD_DNX_RESV_59},\ + {"Reserved_60", BCMPKT_RXPMD_DNX_RESV_60},\ + {"Reserved_61", BCMPKT_RXPMD_DNX_RESV_61},\ + {"Reserved_62", BCMPKT_RXPMD_DNX_RESV_62},\ + {"Reserved_63", BCMPKT_RXPMD_DNX_RESV_63},\ + {"Reserved_64", BCMPKT_RXPMD_DNX_RESV_64},\ + {"Reserved_65", BCMPKT_RXPMD_DNX_RESV_65},\ + {"Reserved_66", BCMPKT_RXPMD_DNX_RESV_66},\ + {"Reserved_67", BCMPKT_RXPMD_DNX_RESV_67},\ + {"Reserved_68", BCMPKT_RXPMD_DNX_RESV_68},\ + {"Reserved_69", BCMPKT_RXPMD_DNX_RESV_69},\ + {"Reserved_70", BCMPKT_RXPMD_DNX_RESV_70},\ + {"Reserved_71", BCMPKT_RXPMD_DNX_RESV_71},\ + {"Reserved_72", BCMPKT_RXPMD_DNX_RESV_72},\ + {"Reserved_73", BCMPKT_RXPMD_DNX_RESV_73},\ + {"Reserved_74", BCMPKT_RXPMD_DNX_RESV_74},\ + {"Reserved_75", BCMPKT_RXPMD_DNX_RESV_75},\ + {"Reserved_76", BCMPKT_RXPMD_DNX_RESV_76},\ + {"Reserved_77", BCMPKT_RXPMD_DNX_RESV_77},\ + {"Reserved_78", BCMPKT_RXPMD_DNX_RESV_78},\ + {"Reserved_79", BCMPKT_RXPMD_DNX_RESV_79},\ + {"Reserved_80", BCMPKT_RXPMD_DNX_RESV_80},\ + {"Reserved_81", BCMPKT_RXPMD_DNX_RESV_81},\ + {"Reserved_82", BCMPKT_RXPMD_DNX_RESV_82},\ + {"Reserved_83", BCMPKT_RXPMD_DNX_RESV_83},\ + {"Reserved_84", BCMPKT_RXPMD_DNX_RESV_84},\ + {"Reserved_85", BCMPKT_RXPMD_DNX_RESV_85},\ + {"Reserved_86", BCMPKT_RXPMD_DNX_RESV_86},\ + {"Reserved_87", BCMPKT_RXPMD_DNX_RESV_87},\ + {"Reserved_88", BCMPKT_RXPMD_DNX_RESV_88},\ + {"Reserved_89", BCMPKT_RXPMD_DNX_RESV_89},\ + {"Reserved_90", BCMPKT_RXPMD_DNX_RESV_90},\ + {"Reserved_91", BCMPKT_RXPMD_DNX_RESV_91},\ + {"Reserved_92", BCMPKT_RXPMD_DNX_RESV_92},\ + {"Reserved_93", BCMPKT_RXPMD_DNX_RESV_93},\ + {"Reserved_94", BCMPKT_RXPMD_DNX_RESV_94},\ + {"Reserved_95", BCMPKT_RXPMD_DNX_RESV_95},\ + {"Reserved_96", BCMPKT_RXPMD_DNX_RESV_96},\ + {"Reserved_97", BCMPKT_RXPMD_DNX_RESV_97},\ + {"Reserved_98", BCMPKT_RXPMD_DNX_RESV_98},\ + {"fid count", BCMPKT_RXPMD_DNX_FID_COUNT} + +#endif /*! BCMPKT_RXPMD_DEFS_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_fid.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_fid.h new file mode 100644 index 0000000..d5455a7 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_fid.h @@ -0,0 +1,100 @@ +/*! \file bcmpkt_rxpmd_fid.h + * + * RX Packet Meta Data (RXPMD) field id header file. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_RXPMD_FID_H +#define BCMPKT_RXPMD_FID_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif +#include + +/*! \brief RXPMD field ID supported bit array. + * Array of bits indicating whether a RXPMD field ID is supported by a given + * device type. + */ +typedef struct bcmpkt_rxpmd_fid_support_s { + /*! Field ID bitmap container */ + SHR_BITDCLNAME(fbits, BCMPKT_RXPMD_FID_COUNT); +} bcmpkt_rxpmd_fid_support_t; + +/*! + * \name Utility macros for \ref bcmpkt_rxpmd_fid_support_t. + * \anchor BCMPKT_RXPMD_SUPPORT_OPS + */ +/*! \{ */ +/*! + * Macro to get a field ID's supported status. + * + * \retval zero Not supported + * \retval non-zero Supported + */ +#define BCMPKT_RXPMD_FID_SUPPORT_GET(_support, _fid) \ + SHR_BITGET(((_support).fbits), (_fid)) + +/*! + * Iterate over all supported RXPMD field IDs in the \c _support. + */ +#define BCMPKT_RXPMD_FID_SUPPORT_ITER(_support, _fid) \ + for(_fid = 0; _fid < BCMPKT_RXPMD_FID_COUNT; _fid++) \ + if(BCMPKT_RXPMD_FID_SUPPORT_GET(_support, _fid)) +/*! \} */ + + +/*! + * \brief Get supported RXPMD field IDs for a given device type. + * + * This function returns a structure with information about the RXPMD field IDs + * a given device type supports. + * + * Use \ref BCMPKT_RXPMD_FID_SUPPORT_GET on the returned structure to get the + * supported status of a specific field ID. + * + * \param [in] dev_type Device type. + * \param [out] support Field ID supported status bitmap. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_INTERNAL API internal error. + */ +extern int +bcmpkt_rxpmd_fid_support_get(bcmdrd_dev_type_t dev_type, + bcmpkt_rxpmd_fid_support_t *support); + + + +#endif /* BCMPKT_RXPMD_FID_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_field.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_field.h new file mode 100644 index 0000000..00bcf13 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_field.h @@ -0,0 +1,93 @@ +/*! \file bcmpkt_rxpmd_field.h + * + * RX Packet MetaData (RXPMD, called EP_TO_CPU in hardware) field api's. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_RXPMD_FIELD_H +#define BCMPKT_RXPMD_FIELD_H + + +/*! + * \brief Get value from an RXPMD field. + * + * \param [in] dev_type Device type. + * \param [in] rxpmd RXPMD handle. + * \param [in] fid RXPMD field ID, refer to \ref BCMPKT_RXPMD_XXX. + * \param [out] val Field value. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support the field. + */ +extern int +bcmpkt_rxpmd_field_get(bcmdrd_dev_type_t dev_type, uint32_t *rxpmd, + int fid, uint32_t *val); + +/*! + * \brief Set value into an RXPMD field. (Internally used for filter config.) + * + * \param [in] dev_type Device type. + * \param [in,out] rxpmd RXPMD handle. + * \param [in] fid RXPMD field ID, refer to \ref BCMPKT_RXPMD_XXX. + * \param [in] val Set value. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support the field. + */ +extern int +bcmpkt_rxpmd_field_set(bcmdrd_dev_type_t dev_type, uint32_t *rxpmd, + int fid, uint32_t val); + +/*! + * \brief Get flex data handle from the RXPMD. + * + * This function is used for geting flex data handle from the \c rxpmd. + * + * \param [in] dev_type Device type. + * \param [in] rxpmd RXPMD handle. + * \param [out] flexdata Flex data handle. + * \param [out] len Flex data size in 4-bytes. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support flex data. + * \retval SHR_E_INTERNAL Internal issue. + */ +extern int +bcmpkt_rxpmd_flexdata_get(bcmdrd_dev_type_t dev_type, uint32_t *rxpmd, + uint32_t **flexdata, uint32_t *len); + + +#endif /* BCMPKT_RXPMD_FIELD_H */ + diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_internal.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_internal.h new file mode 100644 index 0000000..3ab4670 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_internal.h @@ -0,0 +1,99 @@ +/*! \file bcmpkt_rxpmd_internal.h + * + * RX Packet MetaData internal library. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_RXPMD_INTERNAL_H +#define BCMPKT_RXPMD_INTERNAL_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif +#include +#include +#include + +/*! + * Array of RXPMD field getter functions for a particular device + * type. + */ +typedef struct bcmpkt_rxpmd_fget_s { + bcmpkt_field_get_f fget[BCMPKT_RXPMD_FID_COUNT]; +} bcmpkt_rxpmd_fget_t; + +/*! + * Array of RXPMD field setter functions for a particular device + * type. These functions are used for internally configuring packet + * filter. + */ +typedef struct bcmpkt_rxpmd_fset_s { + bcmpkt_field_set_f fset[BCMPKT_RXPMD_FID_COUNT]; +} bcmpkt_rxpmd_fset_t; + +/*! + * Array of RXPMD field address and length getter functions for a multiple + * words field of a particular device type. *addr is output address and return + * length. + */ +typedef struct bcmpkt_rxpmd_figet_s { + bcmpkt_ifield_get_f fget[BCMPKT_RXPMD_I_FID_COUNT]; +} bcmpkt_rxpmd_figet_t; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern void _bd##_rx_reason_decode(const uint32_t* data, bcmpkt_rx_reasons_t* reasons); +#define BCMDRD_DEVLIST_OVERRIDE +#include + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern void _bd##_rx_reason_encode(const bcmpkt_rx_reasons_t* reasons, uint32_t* data); +#define BCMDRD_DEVLIST_OVERRIDE +#include + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern void _bd##_rxpmd_view_info_get(bcmpkt_pmd_view_info_t *info); +#define BCMDRD_DEVLIST_OVERRIDE +#include + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern void _bd##_ep_rx_reason_decode(const uint32_t* data, bcmpkt_rx_reasons_t* reasons); +#define BCMDRD_DEVLIST_OVERRIDE +#include + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern void _bd##_ep_rx_reason_encode(const bcmpkt_rx_reasons_t* reasons, uint32_t* data); +#define BCMDRD_DEVLIST_OVERRIDE +#include + +#endif /* BCMPKT_RXPMD_INTERNAL_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_match_id.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_match_id.h new file mode 100644 index 0000000..d9a085b --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_rxpmd_match_id.h @@ -0,0 +1,192 @@ +/*! \file bcmpkt_rxpmd_match_id.h + * + * RX Packet Meta Data Match ID api's. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_RXPMD_MATCH_ID_H +#define BCMPKT_RXPMD_MATCH_ID_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#include +#endif +#include + +/*! + * \brief Does the match id data contain the specified type + * + * This routine returns the true for false for a given match id using the + * provided match id data. + * + * \param [in] variant Variant type. + * \param [in] match_id_array Match ID data. + * \param [in] array_len Match ID data length in words. + * \param [in] match_id Match ID. + * + * \retval SHR_E_NONE The match id data contains the specified type + * \retval SHR_E_* The match id data does not contain the specified + * type or there was an error. + * + */ +extern int +bcmpkt_rxpmd_match_id_present(bcmlrd_variant_t variant, + uint32_t *match_id_array, + uint32_t array_len, + uint32_t match_id); + +/*! + * \brief Does the arc id data contain the specified type + * + * This routine returns the true for false for a given match id using the + * provided arc id data. + * + * \param [in] variant Variant type. + * \param [in] arc_id_array ARC ID data. + * \param [in] array_len Match ID data length in words. + * \param [in] match_id Match ID. + * + * \retval SHR_E_NONE The arc id data contains the specified type + * \retval SHR_E_* The arc id data does not contain the specified + * type or there was an error. + * + */ +extern int +bcmpkt_rxpmd_match_id_from_arc_id_present(bcmlrd_variant_t variant, + uint32_t *arc_id_array, + uint32_t array_len, + uint32_t match_id); + +/*! + * \brief Does the match id data contain the specified type + * + * This routine returns the match id value for the specified variant given the + * match id name (string value). + * + * \param [in] variant Variant type. + * \param [in] name Match ID string name. + * \param [out] match_id Match ID value. + * + * \retval SHR_E_NONE The match id value was found for the given name + * \retval SHR_E_* There was an error + * + */ +extern int +bcmpkt_rxpmd_match_id_get(bcmlrd_variant_t variant, + char *name, + uint32_t *match_id); + +/*! + * \brief Information on match ID fields. + * + * This structure is used to store information for each + * match id field. + * + */ +typedef struct bcmpkt_rxpmd_match_id_db_s { + /*! Match ID name. */ + const char *name; + + /*! Match. */ + uint32_t match; + + /*! Mask for match. */ + uint32_t match_mask; + + /*! Maxbit of the match id field in the physical container. */ + uint8_t match_maxbit; + + /*! Minbit of the match id field in the physical container. */ + uint8_t match_minbit; + + /*! Maxbit of the match id field. */ + uint8_t maxbit; + + /*! Minbit of the match id field. */ + uint8_t minbit; + + /*! Default value for the match id field. */ + uint32_t value; + + /*! Mask for the default value for the match id field. */ + uint32_t mask; + + /*! Maxbit of the field within match_id container. */ + uint8_t pmaxbit; + + /*! Minbit of the field within match_id container. */ + uint8_t pminbit; + + /*! ARC id zone minbit. */ + uint8_t zone_minbit; + + /*! ARC id mask. */ + uint64_t arc_id_mask; + + /*! Number of words used by zone bitmap. */ + uint8_t num_zone_bmp_words; + + /*! Zone bitmap. */ + uint32_t *zone_bmp; +} bcmpkt_rxpmd_match_id_db_t; + +/*! + * \brief Information on match ID fields. + * + * This structure is used to store information for the match id data. + * + */ +typedef struct bcmpkt_rxpmd_match_id_db_info_s { + /*! Number of entries in the match ID DB. */ + uint32_t num_entries; + + /*! Pointer to match ID DB. */ + const bcmpkt_rxpmd_match_id_db_t *db; +} bcmpkt_rxpmd_match_id_db_info_t; + +/*! + * \brief Information for the match ID map. + * + * This structure is used to store information for the match id map. + * + */ +typedef struct bcmpkt_rxpmd_match_id_map_info_s { + /*! Number of entries in the match ID Map. */ + uint32_t num_entries; + + /*! Pointer to match ID Map. */ + const shr_enum_map_t *map; +} bcmpkt_rxpmd_match_id_map_info_t; + +#endif /* BCMPKT_RXPMD_MATCH_ID_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_socket.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_socket.h new file mode 100644 index 0000000..a513280 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_socket.h @@ -0,0 +1,339 @@ +/*! \file bcmpkt_socket.h + * + * Interfaces for NET (BCMPKT TX and TX) management access. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_SOCKET_H +#define BCMPKT_SOCKET_H + +#include +#ifdef PKTIO_IMPL +#include +#else +#include +#endif + +/*! + * SOCKET driver types. + * BCMPKT_DEV_DRV_T_AUTO type is for attach function ONLY. When it's input type, + * Packet I/O module will select an appropriate SOCKET driver. + */ +typedef enum bcmpkt_socket_drv_types_e { + BCMPKT_SOCKET_DRV_T_NONE = BCMPKT_DEV_DRV_T_NONE, /*! No SOCKET driver. */ + BCMPKT_SOCKET_DRV_T_AUTO = BCMPKT_DEV_DRV_T_AUTO, /*! Automatically select driver. */ + BCMPKT_SOCKET_DRV_T_TPKT = BCMPKT_DEV_DRV_T_KNET, /*! Packet_mmap. */ + BCMPKT_SOCKET_DRV_T_RAWSOCK, /*! Raw socket. */ + BCMPKT_SOCKET_DRV_T_COUNT /*! Must be end. */ +} bcmpkt_socket_drv_types_t; + +/*! + * \brief SOCKET configuration parameters. + * + */ +typedef struct bcmpkt_socket_cfg_s { + + /*! RX polling timeout value (ms). */ + int rx_poll_timeout; + + /*! RX configuration buffer size for mmap. Value 0 : use driver default value. */ + int rx_buf_size; + + /*! TX configuration buffer size for mmap. Value 0 : use driver default value. */ + int tx_buf_size; + +} bcmpkt_socket_cfg_t; + +/*! + * \brief SOCKET Create function. + * + * Create SOCKET onto a netif. If \c cfg = NULL, default settings will be + * used for SOCKET creation. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [in] cfg SOCKET configuration handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Invalid netif_id. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_MEMORY Allocate buffer failed. + * \retval SHR_E_EXISTS SOCKET exists on the network interface. + * \retval SHR_E_FAIL Other failure. + */ +typedef int (*bcmpkt_socket_create_f)(int unit, int netif_id, + bcmpkt_socket_cfg_t *cfg); + +/*! + * \brief SOCKET destroy function. + * + * Destory SOCKET from a netif. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Invalid netif_id. + */ +typedef int (*bcmpkt_socket_destroy_f)(int unit, int netif_id); + +/*! + * \brief SOCKET created status get function. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [out] created SOCKET created status. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Invalid netif_id. + */ +typedef int (*bcmpkt_socket_created_f)(int unit, int netif_id, bool *created); + +/*! + * \brief Dump SOCKET statistics dump into \c pb. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Invalid netif_id. + * \retval SHR_E_UNAVAIL Not support SOCKET. + */ +typedef int (*bcmpkt_socket_stats_dump_f) (int unit, int netif_id, shr_pb_t *pb); + +/*! + * \brief SOCKET statistics clear function. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Invalid netif_id. + * \retval SHR_E_UNAVAIL Not support SOCKET. + */ +typedef int (*bcmpkt_socket_stats_clear_f) (int unit, int netif_id); + +/*! + * \brief SOCKET vectors. + */ +typedef struct bcmpkt_socket_s { + + /*! initialized flag: 0 - uninitialized 1 - initialized. */ + int initialized; + + /*! Driver name, such as "TPacket". */ + char driver_name[128]; + + /*! SOCKET driver type. */ + bcmpkt_socket_drv_types_t driver_type; + + /*! Create SOCKET onto a netif. */ + bcmpkt_socket_create_f create; + + /*! Destroy SOCKET from a netif. */ + bcmpkt_socket_destroy_f destroy; + + /*! Get SOCKET created status. */ + bcmpkt_socket_created_f created; + + /*! Dump a SOCKET's statistics. */ + bcmpkt_socket_stats_dump_f stats_dump; + + /*! Clear a SOCKET's statistics. */ + bcmpkt_socket_stats_clear_f stats_clear; + +} bcmpkt_socket_t; + +/*! + * \brief SOCKET driver register function. + * + * This function is used for registering a low level SOCKET driver. + * For each device, the active SOCKET driver is set by \ref bcmpkt_socket_drv_attach. + * + * \param [in] socket_drv SOCKET driver handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_CONFIG Driver configuration mistake. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_socket_drv_register(bcmpkt_socket_t *socket_drv); + +/*! + * \brief Unregister a SOCKET driver. + * + * \param [in] type SOCKET driver type. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_PARAM Invalid type. + * \retval SHR_E_BUSY The driver is in using. + */ +extern int +bcmpkt_socket_drv_unregister(bcmpkt_socket_drv_types_t type); + +/*! + * \brief Attach a SOCKET drivre onto a device. + * + * + * \param [in] unit Switch unit number. + * \param [in] type SOCKET driver type. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_PARAM Invalid type. + * \retval SHR_E_EXISTS Driver exists. + * \retval SHR_E_FAIL Attach failed. + */ +extern int +bcmpkt_socket_drv_attach(int unit, bcmpkt_socket_drv_types_t type); + +/*! + * \brief Detach SOCKET driver from a device. + * + * \param [in] unit Switch unit number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + */ +extern int +bcmpkt_socket_drv_detach(int unit); + +/*! + * \brief Get SOCKET driver type. + * + * \param [in] unit Switch unit number. + * \param [out] type SOCKET driver type. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit number. + */ +extern int +bcmpkt_socket_drv_type_get(int unit, bcmpkt_socket_drv_types_t *type); + +/*! + * \brief SOCKET Create function. + * + * Create a SOCKET on a netif. If \c cfg = NULL, default settings will be + * used for SOCKET creation. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [in] cfg SOCKET configuration handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Invalid netif_id. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_MEMORY Allocate buffer failed. + * \retval SHR_E_EXISTS SOCKET exists on the network interface. + * \retval SHR_E_FAIL Other failure. + */ +extern int +bcmpkt_socket_create(int unit, int netif_id, bcmpkt_socket_cfg_t *cfg); + +/*! + * \brief SOCKET destroy function. + * + * Destory SOCKET from a netif. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Invalid netif_id. + */ +extern int +bcmpkt_socket_destroy(int unit, int netif_id); + +/*! + * \brief SOCKET clean up function. + * + * Destory all created SOCKETs. + * + * \param [in] unit Switch unit number. + * + * \retval None. + */ +extern void +bcmpkt_socket_cleanup(int unit); + +/*! + * \brief SOCKET created status get function. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [out] created SOCKET created status. + * + * \retval SHR_E_NONE Success. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Invalid netif_id. + */ +extern int +bcmpkt_socket_created(int unit, int netif_id, bool *created); + +/*! + * \brief Dump SOCKET statistics into \c pb. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface ID. + * \param [out] pb Print buffer handle. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Invalid netif_id. + * \retval SHR_E_UNAVAIL Not support SOCKET. + */ +extern int +bcmpkt_socket_stats_dump(int unit, int netif_id, shr_pb_t *pb); + +/*! + * \brief SOCKET statistics clear function. + * + * \param [in] unit Switch unit number. + * \param [in] netif_id Network interface number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_UNIT Invalid unit. + * \retval SHR_E_BADID Invalid netif_id. + * \retval SHR_E_UNAVAIL Not support SOCKET. + */ +extern int +bcmpkt_socket_stats_clear(int unit, int netif_id); + +#endif /* BCMPKT_SOCKET_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_trace_defs.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_trace_defs.h new file mode 100644 index 0000000..a68f4a1 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_trace_defs.h @@ -0,0 +1,11062 @@ +#ifndef BCMPKT_TRACE_DEFS_H +#define BCMPKT_TRACE_DEFS_H +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * Tool: INTERNAL/regs/xgs/generate-pmd.pl + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides field macros for TRACE INFO access. + * + ******************************************************************************/ + +/*! + * \name TRACE metadata field IDs. + * \anchor BCMPKT_TRACE_XXX + */ +/*! \{ */ +/*! Invalid BCMPKT_TRACE FID indicator */ +#define BCMPKT_TRACE_FID_INVALID -1 +/*! Indicates MY_STATION_TCAM lookup hit. */ +#define BCMPKT_TRACE_MY_STATION_HIT 0 +/*! Forward VLAN */ +#define BCMPKT_TRACE_FWD_VLAN 1 +/*! FP and PBM action */ +#define BCMPKT_TRACE_FP_AND_PBM_ACTION_VALID 2 +/*! FP replace PBM action. */ +#define BCMPKT_TRACE_FP_REPLACE_PBM_ACTION_VALID 3 +/*! FP or PBM Action */ +#define BCMPKT_TRACE_FP_OR_PBM_ACTION_VALID 4 +/*! Inner payload TAG status. */ +#define BCMPKT_TRACE_INNER_PAYLOAD_TAG_STATUS 5 +/*! Post VLAN Translation TAG status. */ +#define BCMPKT_TRACE_POST_VXLT_TAG_STATUS 6 +/*! Incoming TAG Status. */ +#define BCMPKT_TRACE_INCOMING_TAG_STATUS 7 +/*! Forwarding Field. */ +#define BCMPKT_TRACE_FORWARDING_FIELD 8 +/*! Forwarding Type. */ +#define BCMPKT_TRACE_FORWARDING_TYPE 9 +/*! Egress Mask Table index. */ +#define BCMPKT_TRACE_EGRESS_MASK_TABLE_INDEX 10 +/*! Egress Block Mask index. */ +#define BCMPKT_TRACE_EGRESS_BLOCK_MASK_INDEX 11 +/*! VLAN Mask index. */ +#define BCMPKT_TRACE_VLAN_MASK_INDEX 12 +/*! MAC Block index. */ +#define BCMPKT_TRACE_MAC_BLOCK_INDEX 13 +/*! Non Unicast Trunk Block Mask index */ +#define BCMPKT_TRACE_NONUC_TRUNK_BLOCK_MASK_INDEX 14 +/*! HiGig Hash Value. */ +#define BCMPKT_TRACE_HASH_VALUE_HG 15 +/*! HiGig Offset. */ +#define BCMPKT_TRACE_HG_OFFSET 16 +/*! HiGig Port. */ +#define BCMPKT_TRACE_HG_PORT 17 +/*! HiGig Trunk ID. */ +#define BCMPKT_TRACE_HG_TRUNK_ID 18 +/*! HiGig Trunk resolution done. */ +#define BCMPKT_TRACE_HG_TRUNK_RESOLUTION_DONE 19 +/*! Destination GPP. */ +#define BCMPKT_TRACE_DGPP 20 +/*! Next Hop. */ +#define BCMPKT_TRACE_NHOP 21 +/*! LAG Offset. */ +#define BCMPKT_TRACE_LAG_OFFSET 22 +/*! LAG Hash Value. */ +#define BCMPKT_TRACE_HASH_VALUE_LAG 23 +/*! LAG ID. */ +#define BCMPKT_TRACE_LAG_ID 24 +/*! LAG Indicator. */ +#define BCMPKT_TRACE_LAG_RESOLUTION_DONE 25 +/*! Resolved Network DVP. */ +#define BCMPKT_TRACE_RESOLVED_NETWORK_DVP 26 +/*! Network VP LAG Valid. */ +#define BCMPKT_TRACE_NETWORK_VP_LAG_VALID 27 +/*! ECMP Hash Value 2. */ +#define BCMPKT_TRACE_ECMP_HASH_VALUE2 28 +/*! ECMP Offset 2. */ +#define BCMPKT_TRACE_ECMP_OFFSET2 29 +/*! ECMP Group 2. */ +#define BCMPKT_TRACE_ECMP_GROUP2 30 +/*! ECMP Resolution Done 2. */ +#define BCMPKT_TRACE_ECMP_RESOLUTION_DONE2 31 +/*! ECMP Hash Value 1. */ +#define BCMPKT_TRACE_ECMP_HASH_VALUE1 32 +/*! ECMP Offset 1. */ +#define BCMPKT_TRACE_ECMP_OFFSET1 33 +/*! ECMP Group 1. */ +#define BCMPKT_TRACE_ECMP_GROUP1 34 +/*! ECMP Resolution Done 1. */ +#define BCMPKT_TRACE_ECMP_RESOLUTION_DONE1 35 +/*! Reserved. */ +#define BCMPKT_TRACE_FWD_DESTINATION_FIELD 36 +/*! Forward Destination Type. */ +#define BCMPKT_TRACE_FWD_DESTINATION_TYPE 37 +/*! Packet Resolution vector. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR 38 +/*! VXLT hit. */ +#define BCMPKT_TRACE_VXLT_HIT 39 +/*! Valid vlan ID. */ +#define BCMPKT_TRACE_VALID_VLAN_ID 40 +/*! Ingress stg state. */ +#define BCMPKT_TRACE_INGRESS_STG_STATE 41 +/*! L2 source hit. */ +#define BCMPKT_TRACE_L2_SRC_HIT 42 +/*! L2 source static. */ +#define BCMPKT_TRACE_L2_SRC_STATIC 43 +/*! L2 destination hit. */ +#define BCMPKT_TRACE_L2_DST_HIT 44 +/*! L2 user entry hit. */ +#define BCMPKT_TRACE_L2_USER_ENTRY_HIT 45 +/*! L3 entry source hit. */ +#define BCMPKT_TRACE_L3_ENTRY_SOURCE_HIT 46 +/*! L3 entry destination hit. */ +#define BCMPKT_TRACE_L3_ENTRY_DESTINATION_HIT 47 +/*! LPM hit. */ +#define BCMPKT_TRACE_LPM_HIT 48 +/*! Unresolved source address. */ +#define BCMPKT_TRACE_UNRESOLVED_SA 49 +/*! Dos attack. */ +#define BCMPKT_TRACE_DOS_ATTACK 50 +/*! L3 tunnel hit. */ +#define BCMPKT_TRACE_L3_TUNNEL_HIT 51 +/*! MPLS entry table lookup 0 hit. */ +#define BCMPKT_TRACE_MPLS_ENTRY_TABLE_LOOKUP_0_HIT 52 +/*! MPLS entry table lookup 1 hit. */ +#define BCMPKT_TRACE_MPLS_ENTRY_TABLE_LOOKUP_1_HIT 53 +/*! MPLS bos terminated. */ +#define BCMPKT_TRACE_MPLS_BOS_TERMINATED 54 +/*! LPM table source address half entry number. */ +#define BCMPKT_TRACE_SRC_TBL_HALF_ENTRY_NUM 55 +/*! LPM table source address table index */ +#define BCMPKT_TRACE_SRC_TBL_INDEX 56 +/*! LPM table destination address half entry number. */ +#define BCMPKT_TRACE_TBL_HALF_ENTRY_NUM 57 +/*! LPM table destination address table index. */ +#define BCMPKT_TRACE_TBL_INDEX 58 +/*! DEF64 source address public hit. */ +#define BCMPKT_TRACE_DEF64_SRC_PUBLIC_HIT 59 +/*! DEF64 source address private hit. */ +#define BCMPKT_TRACE_DEF64_SRC_PRIVATE_HIT 60 +/*! DEF64 destination address public hit. */ +#define BCMPKT_TRACE_DEF64_PUBLIC_HIT 61 +/*! DEF64 destination address private hit. */ +#define BCMPKT_TRACE_DEF64_PRIVATE_HIT 62 +/*! DEF128 source address public hit. */ +#define BCMPKT_TRACE_DEF128_SRC_PUBLIC_HIT 63 +/*! DEF128 source address private hit. */ +#define BCMPKT_TRACE_DEF128_SRC_PRIVATE_HIT 64 +/*! DEF128 destination address public hit. */ +#define BCMPKT_TRACE_DEF128_PUBLIC_HIT 65 +/*! DEF128 destination address private hit. */ +#define BCMPKT_TRACE_DEF128_PRIVATE_HIT 66 +/*! L3 lookup 2 key type */ +#define BCMPKT_TRACE_L3_LKUP2_KEY_TYPE 67 +/*! L3 lookup 1 key type. */ +#define BCMPKT_TRACE_L3_LKUP1_KEY_TYPE 68 +/*! L3 lookup source address entry bitmap. */ +#define BCMPKT_TRACE_SRC_L3_ENTRY_BITMAP 69 +/*! L3 lookup source address bucket index. */ +#define BCMPKT_TRACE_SRC_L3_BUCKET_INDEX 70 +/*! L3 lookup source address private hit. */ +#define BCMPKT_TRACE_SRC_PRIVATE_HIT 71 +/*! L3 lookup source address public hit. */ +#define BCMPKT_TRACE_SRC_PUBLIC_HIT 72 +/*! L3 lookup destination address L3 entry bitmap. */ +#define BCMPKT_TRACE_DST_L3_ENTRY_BITMAP 73 +/*! L3 lookup destination address bucket index. */ +#define BCMPKT_TRACE_DST_L3_BUCKET_INDEX 74 +/*! L3 lookup destination address private hit. */ +#define BCMPKT_TRACE_DST_PRIVATE_HIT 75 +/*! L3 lookup destination address public hit. */ +#define BCMPKT_TRACE_DST_PUBLIC_HIT 76 +/*! L2 lookup source index. */ +#define BCMPKT_TRACE_L2LU_SRC_INDEX 77 +/*! Key type used for Source lookup to L2 table. */ +#define BCMPKT_TRACE_L2LU_SRC_KEY_TYPE 78 +/*! Indicates Source lookup in L2 table hit. */ +#define BCMPKT_TRACE_L2LU_SRC_HIT 79 +/*! Resulting Index when destination lookup in L2 table hit. */ +#define BCMPKT_TRACE_L2LU_DST_IDX 80 +/*! Key type used for Destination lookup to L2 table. */ +#define BCMPKT_TRACE_L2LU_DST_KEY_TYPE 81 +/*! Indicates Destination lookup in L2 table hit. */ +#define BCMPKT_TRACE_L2LU_DST_HIT 82 +/*! Index when MPLS_ENTRY lookup 2 hit. */ +#define BCMPKT_TRACE_MPLS_ENTRY_INDEX_2 83 +/*! Key type used for MPLS_ENTRY lookup 2. */ +#define BCMPKT_TRACE_MPLS_ENTRY_KEY_TYPE_2 84 +/*! Index when MPLS_ENTRY lookup 1 hit. */ +#define BCMPKT_TRACE_MPLS_ENTRY_INDEX_1 85 +/*! Key type used for MPLS_ENTRY lookup 1. */ +#define BCMPKT_TRACE_MPLS_ENTRY_KEY_TYPE_1 86 +/*! Index for VLAN translation lookup 2 when hit. */ +#define BCMPKT_TRACE_VT_INDEX_2 87 +/*! Index for VLAN translation lookup 1 when hit. */ +#define BCMPKT_TRACE_VT_INDEX_1 88 +/*! Indicates MPLS_ENTRY lookup 1 hit. */ +#define BCMPKT_TRACE_MPLS_ENTRY_HIT_1 89 +/*! Indicates MPLS_ENTRY lookup 2 hit. */ +#define BCMPKT_TRACE_MPLS_ENTRY_HIT_2 90 +/*! Key type used for VLAN translation lookup 2. */ +#define BCMPKT_TRACE_VT_KEY_TYPE_2 91 +/*! Indicates VLAN translation lookup 2 hit. */ +#define BCMPKT_TRACE_VT_HIT_2 92 +/*! Key type used for VLAN translation lookup 1. */ +#define BCMPKT_TRACE_VT_KEY_TYPE_1 93 +/*! Indicates VLAN translation lookup 1 hit. */ +#define BCMPKT_TRACE_VT_HIT_1 94 +/*! Index for MY_STATION_TCAM when hit. */ +#define BCMPKT_TRACE_MY_STATION_INDEX 95 +/*! Entropy. */ +#define BCMPKT_TRACE_ENTROPY 96 +/*! + * Index of hitbit in the hit table. [15:0] is the index to the hit table, and [19:16] is the + * bit position within the entry. + */ +#define BCMPKT_TRACE_HIT_BIT_INDEX 97 +/*! 0: L3_DEFIP_LEVEL1_HIT, 1: L3_DEFIP_LEVEL2_HIT, 2: L3_DEFIP_LEVEL3_HIT. */ +#define BCMPKT_TRACE_HIT_BIT_TABLE 98 +/*! Sub DB Priority, used by Level1 resolution block. */ +#define BCMPKT_TRACE_SUB_DB_PRIORITY 99 +/*! L3 lookup destination address destination hit. */ +#define BCMPKT_TRACE_L3_ENTRY_DST_HIT 100 +/*! L3 lookup destination address source hit. */ +#define BCMPKT_TRACE_L3_ENTRY_SRC_HIT 101 +/*! Indicates L3_TUNNEL lookup hit. */ +#define BCMPKT_TRACE_L3_TUNNEL_HIT_1 102 +/*! Index when L3_TUNNEL lookup hit. */ +#define BCMPKT_TRACE_L3_TUNNEL_INDEX_1 103 +/*! Key type of L3_TUNNEL lookup hit. */ +#define BCMPKT_TRACE_L3_TUNNEL_KEY_TYPE_1 104 +/*! Indicates LPM table hit. */ +#define BCMPKT_TRACE_COMP_DST_HIT 105 +/*! Index of hitbit in the hit table. */ +#define BCMPKT_TRACE_COMP_DST_HIT_INDEX 106 +/*! 0: L3_DEFIP_LEVEL1_HIT, 1: L3_DEFIP_LEVEL2_HIT, 2: L3_DEFIP_LEVEL3_HIT. */ +#define BCMPKT_TRACE_COMP_DST_HIT_TABLE 107 +/*! Sub DB Priority, used by Level1 resolution block. */ +#define BCMPKT_TRACE_COMP_DST_SUB_DB_PRIORITY 108 +/*! Indicates LPM table hit. */ +#define BCMPKT_TRACE_COMP_SRC_HIT 109 +/*! Index of hitbit in the hit table. */ +#define BCMPKT_TRACE_COMP_SRC_HIT_INDEX 110 +/*! 0: L3_DEFIP_LEVEL1_HIT, 1: L3_DEFIP_LEVEL2_HIT, 2: L3_DEFIP_LEVEL3_HIT. */ +#define BCMPKT_TRACE_COMP_SRC_HIT_TABLE 111 +/*! Sub DB Priority, used by Level1 resolution block. */ +#define BCMPKT_TRACE_COMP_SRC_SUB_DB_PRIORITY 112 +/*! Indicates LPM table hit. */ +#define BCMPKT_TRACE_LPM_DST_HIT 113 +/*! Index of hitbit in the hit table. */ +#define BCMPKT_TRACE_LPM_DST_HIT_INDEX 114 +/*! + * 0: L3_DEFIP_LEVEL1_HIT. + * 1: L3_DEFIP_LEVEL2_HIT. + * 2: L3_DEFIP_LEVEL3_HIT. + */ +#define BCMPKT_TRACE_LPM_DST_HIT_TABLE 115 +/*! Sub DB Priority, used by Level1 resolution block. */ +#define BCMPKT_TRACE_LPM_DST_SUB_DB_PRIORITY 116 +/*! Indicates LPM table hit. */ +#define BCMPKT_TRACE_LPM_SRC_HIT 117 +/*! Index of hitbit in the hit table. */ +#define BCMPKT_TRACE_LPM_SRC_HIT_INDEX 118 +/*! + * 0: L3_DEFIP_LEVEL1_HIT. + * 1: L3_DEFIP_LEVEL2_HIT. + * 2: L3_DEFIP_LEVEL3_HIT. + */ +#define BCMPKT_TRACE_LPM_SRC_HIT_TABLE 119 +/*! Sub DB Priority, used by Level1 resolution block. */ +#define BCMPKT_TRACE_LPM_SRC_SUB_DB_PRIORITY 120 +/*! Indicates L3_TUNNEL_TcAM lookup hit. */ +#define BCMPKT_TRACE_L3_TUNNEL_TCAM_HIT 121 +/*! Index when L3_TUNNEL_TCAM lookup hit. */ +#define BCMPKT_TRACE_L3_TUNNEL_TCAM_INDEX 122 +/*! DVP. */ +#define BCMPKT_TRACE_DVP 123 +/*! SVP. */ +#define BCMPKT_TRACE_SVP 124 +/*! Inner L2 has a vlan tag. */ +#define BCMPKT_TRACE_INNER_L2_OUTER_TAGGED 125 +/*! Overlay Next Hop. */ +#define BCMPKT_TRACE_O_NEXT_HOP 126 +/*! VFI */ +#define BCMPKT_TRACE_VFI 127 +/*! Indicates MY_STATION_2_TCAM lookup hit. */ +#define BCMPKT_TRACE_MY_STATION_2_HIT 128 +/*! Index for MY_STATION_2_TCAM when hit. */ +#define BCMPKT_TRACE_MY_STATION_2_INDEX 129 +/*! Trunked Port (LAG) indication. */ +#define BCMPKT_TRACE_LAG_INDICATOR 130 +/*! MY_PREFIX TCAM hit. */ +#define BCMPKT_TRACE_MY_PREFIX_TCAM_HIT 131 +/*! Key type of L3_TUNNEL_TCAM lookup key type. */ +#define BCMPKT_TRACE_L3_TUNNEL_TCAM_KEY_TYPE 132 +/*! Key type of L3_TUNNEL hash lookup key type. */ +#define BCMPKT_TRACE_L3_TUNNEL_HASH_KEY_TYPE_1 133 +/*! TRACE FIELD ID NUMBER */ +#define BCMPKT_TRACE_FID_COUNT 134 +/*! \} */ + +/*! TRACE field name strings for debugging. */ +#define BCMPKT_TRACE_FIELD_NAME_MAP_INIT \ + {"MY_STATION_HIT", BCMPKT_TRACE_MY_STATION_HIT},\ + {"FWD_VLAN", BCMPKT_TRACE_FWD_VLAN},\ + {"FP_AND_PBM_ACTION_VALID", BCMPKT_TRACE_FP_AND_PBM_ACTION_VALID},\ + {"FP_REPLACE_PBM_ACTION_VALID", BCMPKT_TRACE_FP_REPLACE_PBM_ACTION_VALID},\ + {"FP_OR_PBM_ACTION_VALID", BCMPKT_TRACE_FP_OR_PBM_ACTION_VALID},\ + {"INNER_PAYLOAD_TAG_STATUS", BCMPKT_TRACE_INNER_PAYLOAD_TAG_STATUS},\ + {"POST_VXLT_TAG_STATUS", BCMPKT_TRACE_POST_VXLT_TAG_STATUS},\ + {"INCOMING_TAG_STATUS", BCMPKT_TRACE_INCOMING_TAG_STATUS},\ + {"FORWARDING_FIELD", BCMPKT_TRACE_FORWARDING_FIELD},\ + {"FORWARDING_TYPE", BCMPKT_TRACE_FORWARDING_TYPE},\ + {"EGRESS_MASK_TABLE_INDEX", BCMPKT_TRACE_EGRESS_MASK_TABLE_INDEX},\ + {"EGRESS_BLOCK_MASK_INDEX", BCMPKT_TRACE_EGRESS_BLOCK_MASK_INDEX},\ + {"VLAN_MASK_INDEX", BCMPKT_TRACE_VLAN_MASK_INDEX},\ + {"MAC_BLOCK_INDEX", BCMPKT_TRACE_MAC_BLOCK_INDEX},\ + {"NONUC_TRUNK_BLOCK_MASK_INDEX", BCMPKT_TRACE_NONUC_TRUNK_BLOCK_MASK_INDEX},\ + {"HASH_VALUE_HG", BCMPKT_TRACE_HASH_VALUE_HG},\ + {"HG_OFFSET", BCMPKT_TRACE_HG_OFFSET},\ + {"HG_PORT", BCMPKT_TRACE_HG_PORT},\ + {"HG_TRUNK_ID", BCMPKT_TRACE_HG_TRUNK_ID},\ + {"HG_TRUNK_RESOLUTION_DONE", BCMPKT_TRACE_HG_TRUNK_RESOLUTION_DONE},\ + {"DGPP", BCMPKT_TRACE_DGPP},\ + {"NHOP", BCMPKT_TRACE_NHOP},\ + {"LAG_OFFSET", BCMPKT_TRACE_LAG_OFFSET},\ + {"HASH_VALUE_LAG", BCMPKT_TRACE_HASH_VALUE_LAG},\ + {"LAG_ID", BCMPKT_TRACE_LAG_ID},\ + {"LAG_RESOLUTION_DONE", BCMPKT_TRACE_LAG_RESOLUTION_DONE},\ + {"RESOLVED_NETWORK_DVP", BCMPKT_TRACE_RESOLVED_NETWORK_DVP},\ + {"NETWORK_VP_LAG_VALID", BCMPKT_TRACE_NETWORK_VP_LAG_VALID},\ + {"ECMP_HASH_VALUE2", BCMPKT_TRACE_ECMP_HASH_VALUE2},\ + {"ECMP_OFFSET2", BCMPKT_TRACE_ECMP_OFFSET2},\ + {"ECMP_GROUP2", BCMPKT_TRACE_ECMP_GROUP2},\ + {"ECMP_RESOLUTION_DONE2", BCMPKT_TRACE_ECMP_RESOLUTION_DONE2},\ + {"ECMP_HASH_VALUE1", BCMPKT_TRACE_ECMP_HASH_VALUE1},\ + {"ECMP_OFFSET1", BCMPKT_TRACE_ECMP_OFFSET1},\ + {"ECMP_GROUP1", BCMPKT_TRACE_ECMP_GROUP1},\ + {"ECMP_RESOLUTION_DONE1", BCMPKT_TRACE_ECMP_RESOLUTION_DONE1},\ + {"FWD_DESTINATION_FIELD", BCMPKT_TRACE_FWD_DESTINATION_FIELD},\ + {"FWD_DESTINATION_TYPE", BCMPKT_TRACE_FWD_DESTINATION_TYPE},\ + {"PKT_RESOLUTION_VECTOR", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR},\ + {"VXLT_HIT", BCMPKT_TRACE_VXLT_HIT},\ + {"VALID_VLAN_ID", BCMPKT_TRACE_VALID_VLAN_ID},\ + {"INGRESS_STG_STATE", BCMPKT_TRACE_INGRESS_STG_STATE},\ + {"L2_SRC_HIT", BCMPKT_TRACE_L2_SRC_HIT},\ + {"L2_SRC_STATIC", BCMPKT_TRACE_L2_SRC_STATIC},\ + {"L2_DST_HIT", BCMPKT_TRACE_L2_DST_HIT},\ + {"L2_USER_ENTRY_HIT", BCMPKT_TRACE_L2_USER_ENTRY_HIT},\ + {"L3_ENTRY_SOURCE_HIT", BCMPKT_TRACE_L3_ENTRY_SOURCE_HIT},\ + {"L3_ENTRY_DESTINATION_HIT", BCMPKT_TRACE_L3_ENTRY_DESTINATION_HIT},\ + {"LPM_HIT", BCMPKT_TRACE_LPM_HIT},\ + {"UNRESOLVED_SA", BCMPKT_TRACE_UNRESOLVED_SA},\ + {"DOS_ATTACK", BCMPKT_TRACE_DOS_ATTACK},\ + {"L3_TUNNEL_HIT", BCMPKT_TRACE_L3_TUNNEL_HIT},\ + {"MPLS_ENTRY_TABLE_LOOKUP_0_HIT", BCMPKT_TRACE_MPLS_ENTRY_TABLE_LOOKUP_0_HIT},\ + {"MPLS_ENTRY_TABLE_LOOKUP_1_HIT", BCMPKT_TRACE_MPLS_ENTRY_TABLE_LOOKUP_1_HIT},\ + {"MPLS_BOS_TERMINATED", BCMPKT_TRACE_MPLS_BOS_TERMINATED},\ + {"SRC_TBL_HALF_ENTRY_NUM", BCMPKT_TRACE_SRC_TBL_HALF_ENTRY_NUM},\ + {"SRC_TBL_INDEX", BCMPKT_TRACE_SRC_TBL_INDEX},\ + {"TBL_HALF_ENTRY_NUM", BCMPKT_TRACE_TBL_HALF_ENTRY_NUM},\ + {"TBL_INDEX", BCMPKT_TRACE_TBL_INDEX},\ + {"DEF64_SRC_PUBLIC_HIT", BCMPKT_TRACE_DEF64_SRC_PUBLIC_HIT},\ + {"DEF64_SRC_PRIVATE_HIT", BCMPKT_TRACE_DEF64_SRC_PRIVATE_HIT},\ + {"DEF64_PUBLIC_HIT", BCMPKT_TRACE_DEF64_PUBLIC_HIT},\ + {"DEF64_PRIVATE_HIT", BCMPKT_TRACE_DEF64_PRIVATE_HIT},\ + {"DEF128_SRC_PUBLIC_HIT", BCMPKT_TRACE_DEF128_SRC_PUBLIC_HIT},\ + {"DEF128_SRC_PRIVATE_HIT", BCMPKT_TRACE_DEF128_SRC_PRIVATE_HIT},\ + {"DEF128_PUBLIC_HIT", BCMPKT_TRACE_DEF128_PUBLIC_HIT},\ + {"DEF128_PRIVATE_HIT", BCMPKT_TRACE_DEF128_PRIVATE_HIT},\ + {"L3_LKUP2_KEY_TYPE", BCMPKT_TRACE_L3_LKUP2_KEY_TYPE},\ + {"L3_LKUP1_KEY_TYPE", BCMPKT_TRACE_L3_LKUP1_KEY_TYPE},\ + {"SRC_L3_ENTRY_BITMAP", BCMPKT_TRACE_SRC_L3_ENTRY_BITMAP},\ + {"SRC_L3_BUCKET_INDEX", BCMPKT_TRACE_SRC_L3_BUCKET_INDEX},\ + {"SRC_PRIVATE_HIT", BCMPKT_TRACE_SRC_PRIVATE_HIT},\ + {"SRC_PUBLIC_HIT", BCMPKT_TRACE_SRC_PUBLIC_HIT},\ + {"DST_L3_ENTRY_BITMAP", BCMPKT_TRACE_DST_L3_ENTRY_BITMAP},\ + {"DST_L3_BUCKET_INDEX", BCMPKT_TRACE_DST_L3_BUCKET_INDEX},\ + {"DST_PRIVATE_HIT", BCMPKT_TRACE_DST_PRIVATE_HIT},\ + {"DST_PUBLIC_HIT", BCMPKT_TRACE_DST_PUBLIC_HIT},\ + {"L2LU_SRC_INDEX", BCMPKT_TRACE_L2LU_SRC_INDEX},\ + {"L2LU_SRC_KEY_TYPE", BCMPKT_TRACE_L2LU_SRC_KEY_TYPE},\ + {"L2LU_SRC_HIT", BCMPKT_TRACE_L2LU_SRC_HIT},\ + {"L2LU_DST_IDX", BCMPKT_TRACE_L2LU_DST_IDX},\ + {"L2LU_DST_KEY_TYPE", BCMPKT_TRACE_L2LU_DST_KEY_TYPE},\ + {"L2LU_DST_HIT", BCMPKT_TRACE_L2LU_DST_HIT},\ + {"MPLS_ENTRY_INDEX_2", BCMPKT_TRACE_MPLS_ENTRY_INDEX_2},\ + {"MPLS_ENTRY_KEY_TYPE_2", BCMPKT_TRACE_MPLS_ENTRY_KEY_TYPE_2},\ + {"MPLS_ENTRY_INDEX_1", BCMPKT_TRACE_MPLS_ENTRY_INDEX_1},\ + {"MPLS_ENTRY_KEY_TYPE_1", BCMPKT_TRACE_MPLS_ENTRY_KEY_TYPE_1},\ + {"VT_INDEX_2", BCMPKT_TRACE_VT_INDEX_2},\ + {"VT_INDEX_1", BCMPKT_TRACE_VT_INDEX_1},\ + {"MPLS_ENTRY_HIT_1", BCMPKT_TRACE_MPLS_ENTRY_HIT_1},\ + {"MPLS_ENTRY_HIT_2", BCMPKT_TRACE_MPLS_ENTRY_HIT_2},\ + {"VT_KEY_TYPE_2", BCMPKT_TRACE_VT_KEY_TYPE_2},\ + {"VT_HIT_2", BCMPKT_TRACE_VT_HIT_2},\ + {"VT_KEY_TYPE_1", BCMPKT_TRACE_VT_KEY_TYPE_1},\ + {"VT_HIT_1", BCMPKT_TRACE_VT_HIT_1},\ + {"MY_STATION_INDEX", BCMPKT_TRACE_MY_STATION_INDEX},\ + {"ENTROPY", BCMPKT_TRACE_ENTROPY},\ + {"HIT_BIT_INDEX", BCMPKT_TRACE_HIT_BIT_INDEX},\ + {"HIT_BIT_TABLE", BCMPKT_TRACE_HIT_BIT_TABLE},\ + {"SUB_DB_PRIORITY", BCMPKT_TRACE_SUB_DB_PRIORITY},\ + {"L3_ENTRY_DST_HIT", BCMPKT_TRACE_L3_ENTRY_DST_HIT},\ + {"L3_ENTRY_SRC_HIT", BCMPKT_TRACE_L3_ENTRY_SRC_HIT},\ + {"L3_TUNNEL_HIT_1", BCMPKT_TRACE_L3_TUNNEL_HIT_1},\ + {"L3_TUNNEL_INDEX_1", BCMPKT_TRACE_L3_TUNNEL_INDEX_1},\ + {"L3_TUNNEL_KEY_TYPE_1", BCMPKT_TRACE_L3_TUNNEL_KEY_TYPE_1},\ + {"COMP_DST_HIT", BCMPKT_TRACE_COMP_DST_HIT},\ + {"COMP_DST_HIT_INDEX", BCMPKT_TRACE_COMP_DST_HIT_INDEX},\ + {"COMP_DST_HIT_TABLE", BCMPKT_TRACE_COMP_DST_HIT_TABLE},\ + {"COMP_DST_SUB_DB_PRIORITY", BCMPKT_TRACE_COMP_DST_SUB_DB_PRIORITY},\ + {"COMP_SRC_HIT", BCMPKT_TRACE_COMP_SRC_HIT},\ + {"COMP_SRC_HIT_INDEX", BCMPKT_TRACE_COMP_SRC_HIT_INDEX},\ + {"COMP_SRC_HIT_TABLE", BCMPKT_TRACE_COMP_SRC_HIT_TABLE},\ + {"COMP_SRC_SUB_DB_PRIORITY", BCMPKT_TRACE_COMP_SRC_SUB_DB_PRIORITY},\ + {"LPM_DST_HIT", BCMPKT_TRACE_LPM_DST_HIT},\ + {"LPM_DST_HIT_INDEX", BCMPKT_TRACE_LPM_DST_HIT_INDEX},\ + {"LPM_DST_HIT_TABLE", BCMPKT_TRACE_LPM_DST_HIT_TABLE},\ + {"LPM_DST_SUB_DB_PRIORITY", BCMPKT_TRACE_LPM_DST_SUB_DB_PRIORITY},\ + {"LPM_SRC_HIT", BCMPKT_TRACE_LPM_SRC_HIT},\ + {"LPM_SRC_HIT_INDEX", BCMPKT_TRACE_LPM_SRC_HIT_INDEX},\ + {"LPM_SRC_HIT_TABLE", BCMPKT_TRACE_LPM_SRC_HIT_TABLE},\ + {"LPM_SRC_SUB_DB_PRIORITY", BCMPKT_TRACE_LPM_SRC_SUB_DB_PRIORITY},\ + {"L3_TUNNEL_TCAM_HIT", BCMPKT_TRACE_L3_TUNNEL_TCAM_HIT},\ + {"L3_TUNNEL_TCAM_INDEX", BCMPKT_TRACE_L3_TUNNEL_TCAM_INDEX},\ + {"DVP", BCMPKT_TRACE_DVP},\ + {"SVP", BCMPKT_TRACE_SVP},\ + {"INNER_L2_OUTER_TAGGED", BCMPKT_TRACE_INNER_L2_OUTER_TAGGED},\ + {"O_NEXT_HOP", BCMPKT_TRACE_O_NEXT_HOP},\ + {"VFI", BCMPKT_TRACE_VFI},\ + {"MY_STATION_2_HIT", BCMPKT_TRACE_MY_STATION_2_HIT},\ + {"MY_STATION_2_INDEX", BCMPKT_TRACE_MY_STATION_2_INDEX},\ + {"LAG_INDICATOR", BCMPKT_TRACE_LAG_INDICATOR},\ + {"MY_PREFIX_TCAM_HIT", BCMPKT_TRACE_MY_PREFIX_TCAM_HIT},\ + {"L3_TUNNEL_TCAM_KEY_TYPE", BCMPKT_TRACE_L3_TUNNEL_TCAM_KEY_TYPE},\ + {"L3_TUNNEL_HASH_KEY_TYPE_1", BCMPKT_TRACE_L3_TUNNEL_HASH_KEY_TYPE_1},\ + {"fid count", BCMPKT_TRACE_FID_COUNT} + +/*! + * \name BCMPKT_TRACE_INCOMING_TAG_STATUS encodings. + * \anchor BCMPKT_TRACE_INCOMING_TAG_STATUS_XXX + */ +/*! \{ */ +/*! Untagged. */ +#define BCMPKT_TRACE_INCOMING_TAG_STATUS_UNTAGGED 0 +/*! Tagged. */ +#define BCMPKT_TRACE_INCOMING_TAG_STATUS_TAGGED 1 +/*! \} */ + +/*! BCMPKT_TRACE_INCOMING_TAG_STATUS encoding name strings for debugging. */ +#define BCMPKT_TRACE_INCOMING_TAG_STATUS_NAME_MAP_INIT \ + {"UNTAGGED", BCMPKT_TRACE_INCOMING_TAG_STATUS_UNTAGGED},\ + {"TAGGED", BCMPKT_TRACE_INCOMING_TAG_STATUS_TAGGED},\ + +/*! + * \name BCMPKT_TRACE_FORWARDING_TYPE encodings. + * \anchor BCMPKT_TRACE_FORWARDING_TYPE_XXX + */ +/*! \{ */ +/*! L2 Forwarded based on VID. */ +#define BCMPKT_TRACE_FORWARDING_T_VID 0 +/*! L2 Forwarded based on Filtering Identifier. */ +#define BCMPKT_TRACE_FORWARDING_T_FID 1 +/*! SRv6 cross connect. */ +#define BCMPKT_TRACE_FORWARDING_T_L3_CROSS_CONNECT 2 +/*! Single cross connect. */ +#define BCMPKT_TRACE_FORWARDING_T_L2_CROSS_CONNECT 3 +/*! PHP on Bottom of Stack Label. */ +#define BCMPKT_TRACE_FORWARDING_T_L3_MPLS 4 +/*! L3 Forwarding based on VRF. */ +#define BCMPKT_TRACE_FORWARDING_T_VRF 5 +/*! LSR Operation (label SWAP or PHP on a non BOS label). */ +#define BCMPKT_TRACE_FORWARDING_T_MPLS 7 +/*! GSH transit. */ +#define BCMPKT_TRACE_FORWARDING_T_GSH_TRANSIT 8 +/*! \} */ + +/*! BCMPKT_TRACE_FORWARDING_TYPE encoding name strings for debugging. */ +#define BCMPKT_TRACE_FORWARDING_TYPE_NAME_MAP_INIT \ + {"VID", BCMPKT_TRACE_FORWARDING_T_VID},\ + {"FID", BCMPKT_TRACE_FORWARDING_T_FID},\ + {"L3_CROSS_CONNECT", BCMPKT_TRACE_FORWARDING_T_L3_CROSS_CONNECT},\ + {"L2_CROSS_CONNECT", BCMPKT_TRACE_FORWARDING_T_L2_CROSS_CONNECT},\ + {"L3_MPLS", BCMPKT_TRACE_FORWARDING_T_L3_MPLS},\ + {"VRF", BCMPKT_TRACE_FORWARDING_T_VRF},\ + {"RESERVED_COUNTER", 6},\ + {"MPLS", BCMPKT_TRACE_FORWARDING_T_MPLS},\ + {"GSH_TRANSIT", BCMPKT_TRACE_FORWARDING_T_GSH_TRANSIT},\ + +/*! + * \name BCMPKT_TRACE_FWD_DESTINATION_TYPE encodings. + * \anchor BCMPKT_TRACE_FWD_DESTINATION_TYPE_XXX + */ +/*! \{ */ +/*! Destination GLP. */ +#define BCMPKT_TRACE_FWD_DESTINATION_T_DGLP 0 +/*! Next hop. */ +#define BCMPKT_TRACE_FWD_DESTINATION_T_NHI 1 +/*! ECMP group. */ +#define BCMPKT_TRACE_FWD_DESTINATION_T_ECMP 2 +/*! L2MC. */ +#define BCMPKT_TRACE_FWD_DESTINATION_T_L2MC 3 +/*! IPMC. */ +#define BCMPKT_TRACE_FWD_DESTINATION_T_IPMC 4 +/*! DVP */ +#define BCMPKT_TRACE_FWD_DESTINATION_T_DVP 5 +/*! \} */ + +/*! BCMPKT_TRACE_FWD_DESTINATION_TYPE encoding name strings for debugging. */ +#define BCMPKT_TRACE_FWD_DESTINATION_TYPE_NAME_MAP_INIT \ + {"DGLP", BCMPKT_TRACE_FWD_DESTINATION_T_DGLP},\ + {"NHI", BCMPKT_TRACE_FWD_DESTINATION_T_NHI},\ + {"ECMP", BCMPKT_TRACE_FWD_DESTINATION_T_ECMP},\ + {"L2MC", BCMPKT_TRACE_FWD_DESTINATION_T_L2MC},\ + {"IPMC", BCMPKT_TRACE_FWD_DESTINATION_T_IPMC},\ + {"DVP", BCMPKT_TRACE_FWD_DESTINATION_T_DVP},\ + +/*! + * \name BCMPKT_TRACE_PKT_RESOLUTION_VECTOR encodings. + * \anchor BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_XXX + */ +/*! \{ */ +/*! Unknown packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_PKT 0 +/*! Ethernet Control (8808) packets. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_CONTROL_PKT 1 +/*! OAM packet that needs to be terminated locally. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_OAM_PKT 2 +/*! BFD packet that needs to be terminated locally. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_BFD_PKT 3 +/*! L2 user entry table BPDU bit. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_BPDU_PKT 4 +/*! 1588 message. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_PKT_IS_1588 6 +/*! Known destination L2 unicast packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_L2UC_PKT 8 +/*! Unknown destination L2 unicast packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_L2UC_PKT 9 +/*! Known L2 multicast packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_L2MC_PKT 10 +/*! Unknown L2 multicast packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_L2MC_PKT 11 +/*! L2 broadcast packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_L2BC_PKT 12 +/*! Known destination L3 unicast packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_L3UC_PKT 16 +/*! Unknown destination L3 unicast packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_L3UC_PKT 17 +/*! Known IP multicast packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_IPMC_PKT 18 +/*! Unknown IP multicast packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_IPMC_PKT 19 +/*! Point to point l2 MPLS terminated packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_MPLS_L2_PKT 24 +/*! MPLS packet with unknown/invalid forwarding label. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_MPLS_PKT 25 +/*! MPLS forwarding label action is PHP. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_MPLS_L3_PKT 26 +/*! MPLS transit packet with known forwarding label. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_MPLS_PKT 28 +/*! Point to point MIM terminated packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_MIM_PKT 32 +/*! MIM tunnel error packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_MIM_PKT 33 +/*! Known egress rbridge TRILL transit packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_TRILL_PKT 40 +/*! Unknown egress rbridge TRILL packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_TRILL_PKT 41 +/*! Known destination vif downstream NIV packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_NIV_PKT 48 +/*! Unknown destination vif downstream NIV packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_NIV_PKT 49 +/*! Known L2GRE packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_L2GRE_PKT 50 +/*! Known VXLAN packet. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_VXLAN_PKT 51 +/*! \} */ + +/*! BCMPKT_TRACE_PKT_RESOLUTION_VECTOR encoding name strings for debugging. */ +#define BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_NAME_MAP_INIT \ + {"UNKNOWN_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_PKT},\ + {"CONTROL_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_CONTROL_PKT},\ + {"OAM_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_OAM_PKT},\ + {"BFD_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_BFD_PKT},\ + {"BPDU_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_BPDU_PKT},\ + {"RESERVED_COUNTER", 5},\ + {"PKT_IS_1588", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_PKT_IS_1588},\ + {"RESERVED_COUNTER", 7},\ + {"KNOWN_L2UC_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_L2UC_PKT},\ + {"UNKNOWN_L2UC_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_L2UC_PKT},\ + {"KNOWN_L2MC_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_L2MC_PKT},\ + {"UNKNOWN_L2MC_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_L2MC_PKT},\ + {"L2BC_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_L2BC_PKT},\ + {"RESERVED_COUNTER", 13},\ + {"RESERVED_COUNTER", 14},\ + {"RESERVED_COUNTER", 15},\ + {"KNOWN_L3UC_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_L3UC_PKT},\ + {"UNKNOWN_L3UC_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_L3UC_PKT},\ + {"KNOWN_IPMC_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_IPMC_PKT},\ + {"UNKNOWN_IPMC_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_IPMC_PKT},\ + {"RESERVED_COUNTER", 20},\ + {"RESERVED_COUNTER", 21},\ + {"RESERVED_COUNTER", 22},\ + {"RESERVED_COUNTER", 23},\ + {"KNOWN_MPLS_L2_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_MPLS_L2_PKT},\ + {"UNKNOWN_MPLS_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_MPLS_PKT},\ + {"KNOWN_MPLS_L3_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_MPLS_L3_PKT},\ + {"RESERVED_COUNTER", 27},\ + {"KNOWN_MPLS_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_MPLS_PKT},\ + {"RESERVED_COUNTER", 29},\ + {"RESERVED_COUNTER", 30},\ + {"RESERVED_COUNTER", 31},\ + {"KNOWN_MIM_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_MIM_PKT},\ + {"UNKNOWN_MIM_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_MIM_PKT},\ + {"RESERVED_COUNTER", 34},\ + {"RESERVED_COUNTER", 35},\ + {"RESERVED_COUNTER", 36},\ + {"RESERVED_COUNTER", 37},\ + {"RESERVED_COUNTER", 38},\ + {"RESERVED_COUNTER", 39},\ + {"KNOWN_TRILL_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_TRILL_PKT},\ + {"UNKNOWN_TRILL_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_TRILL_PKT},\ + {"RESERVED_COUNTER", 42},\ + {"RESERVED_COUNTER", 43},\ + {"RESERVED_COUNTER", 44},\ + {"RESERVED_COUNTER", 45},\ + {"RESERVED_COUNTER", 46},\ + {"RESERVED_COUNTER", 47},\ + {"KNOWN_NIV_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_NIV_PKT},\ + {"UNKNOWN_NIV_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_UNKNOWN_NIV_PKT},\ + {"KNOWN_L2GRE_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_L2GRE_PKT},\ + {"KNOWN_VXLAN_PKT", BCMPKT_TRACE_PKT_RESOLUTION_VECTOR_KNOWN_VXLAN_PKT},\ + +/*! + * \name Packet Trace Internal Usage Field IDs. + * \anchor BCMPKT_TRACE_I_XXX + */ +/*! \{ */ +/*! Invalid BCMPKT_TRACE_I FID indicator */ +#define BCMPKT_TRACE_I_FID_INVALID -1 +/*! TRACE raw data size. */ +#define BCMPKT_TRACE_I_SIZE 0 +/*! Contains trace drop reasons. Refer to bcmpkt_trace_drop_reasons_get to decode reasons. */ +#define BCMPKT_TRACE_I_DROP_REASON 1 +/*! Contains trace counter. Refer to bcmpkt_trace_counter_get to decode counter. */ +#define BCMPKT_TRACE_I_COUNTER 2 +/*! TRACE_I FIELD ID NUMBER */ +#define BCMPKT_TRACE_I_FID_COUNT 3 +/*! \} */ + +/*! TRACE_I field name strings for debugging. */ +#define BCMPKT_TRACE_I_FIELD_NAME_MAP_INIT \ + {"SIZE", BCMPKT_TRACE_I_SIZE},\ + {"DROP_REASON", BCMPKT_TRACE_I_DROP_REASON},\ + {"COUNTER", BCMPKT_TRACE_I_COUNTER},\ + {"fid count", BCMPKT_TRACE_I_FID_COUNT} + +/*! + * \name Packet TRACE DROP Reason Types. + * \anchor BCMPKT_TRACE_DROP_REASON_XXX + */ +/*! \{ */ +/*! + * \name TRACE DOP field IDs. + * \anchor BCMPKT_TRACE_DOPXXX + * \format BCMPKT_TRACE_DOP__ + */ +/*! \{ */ +/*! Invalid BCMPKT_TRACE_DOP FID indicator */ +#define BCMPKT_TRACE_DOP_FID_INVALID -1 +/*! IPARSER0_HME_STAGE0_DOP_STAGE0_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER0_HME_STAGE0_DOP_STAGE0_HFE_PROFILE_PTR 0 +/*! IPARSER0_HME_STAGE0_DOP_STAGE0_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER0_HME_STAGE0_DOP_STAGE0_TCAM_TCAM_MATCH 1 +/*! IPARSER0_HME_STAGE0_DOP_STAGE0_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER0_HME_STAGE0_DOP_STAGE0_SHIFT_AMOUNT 2 +/*! IPARSER0_HME_STAGE0_DOP_STAGE0_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER0_HME_STAGE0_DOP_STAGE0_PKT_DATA 3 +/*! MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR 4 +/*! MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_RD 5 +/*! MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR 6 +/*! MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_RD 7 +/*! IFTA10_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA10_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 8 +/*! IFTA10_I1T_00_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA10_I1T_00_INDEX_DOP_LKP0_LTPR_WIN 9 +/*! MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR 10 +/*! MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_RD 11 +/*! MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR 12 +/*! MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_RD 13 +/*! IFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 14 +/*! IFTA20_I1T_00_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA20_I1T_00_INDEX_DOP_LKP0_LTPR_WIN 15 +/*! IPARSER1_HME_STAGE0_DOP_STAGE0_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE0_DOP_STAGE0_HFE_PROFILE_PTR 16 +/*! IPARSER1_HME_STAGE0_DOP_STAGE0_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE0_DOP_STAGE0_TCAM_TCAM_MATCH 17 +/*! IPARSER1_HME_STAGE0_DOP_STAGE0_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE0_DOP_STAGE0_SHIFT_AMOUNT 18 +/*! IPARSER1_HME_STAGE0_DOP_STAGE0_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE0_DOP_STAGE0_PKT_DATA 19 +/*! IPARSER1_HME_STAGE1_DOP_STAGE1_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE1_DOP_STAGE1_HFE_PROFILE_PTR 20 +/*! IPARSER1_HME_STAGE1_DOP_STAGE1_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE1_DOP_STAGE1_TCAM_TCAM_MATCH 21 +/*! IPARSER1_HME_STAGE1_DOP_STAGE1_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE1_DOP_STAGE1_SHIFT_AMOUNT 22 +/*! IPARSER1_HME_STAGE1_DOP_STAGE1_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE1_DOP_STAGE1_PKT_DATA 23 +/*! IPARSER1_HME_STAGE2_DOP_STAGE2_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE2_DOP_STAGE2_HFE_PROFILE_PTR 24 +/*! IPARSER1_HME_STAGE2_DOP_STAGE2_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE2_DOP_STAGE2_TCAM_TCAM_MATCH 25 +/*! IPARSER1_HME_STAGE2_DOP_STAGE2_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE2_DOP_STAGE2_SHIFT_AMOUNT 26 +/*! IPARSER1_HME_STAGE2_DOP_STAGE2_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE2_DOP_STAGE2_PKT_DATA 27 +/*! IPARSER1_HME_STAGE3_DOP_STAGE3_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE3_DOP_STAGE3_HFE_PROFILE_PTR 28 +/*! IPARSER1_HME_STAGE3_DOP_STAGE3_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE3_DOP_STAGE3_TCAM_TCAM_MATCH 29 +/*! IPARSER1_HME_STAGE3_DOP_STAGE3_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE3_DOP_STAGE3_SHIFT_AMOUNT 30 +/*! IPARSER1_HME_STAGE3_DOP_STAGE3_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE3_DOP_STAGE3_PKT_DATA 31 +/*! IPARSER1_HME_STAGE4_DOP_STAGE4_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE4_DOP_STAGE4_HFE_PROFILE_PTR 32 +/*! IPARSER1_HME_STAGE4_DOP_STAGE4_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE4_DOP_STAGE4_TCAM_TCAM_MATCH 33 +/*! IPARSER1_HME_STAGE4_DOP_STAGE4_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE4_DOP_STAGE4_SHIFT_AMOUNT 34 +/*! IPARSER1_HME_STAGE4_DOP_STAGE4_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE4_DOP_STAGE4_PKT_DATA 35 +/*! IPARSER1_HME_STAGE5_DOP_STAGE5_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE5_DOP_STAGE5_HFE_PROFILE_PTR 36 +/*! IPARSER1_HME_STAGE5_DOP_STAGE5_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE5_DOP_STAGE5_TCAM_TCAM_MATCH 37 +/*! IPARSER1_HME_STAGE5_DOP_STAGE5_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE5_DOP_STAGE5_SHIFT_AMOUNT 38 +/*! IPARSER1_HME_STAGE5_DOP_STAGE5_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE5_DOP_STAGE5_PKT_DATA 39 +/*! IFTA30_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 40 +/*! IFTA30_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 41 +/*! IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 42 +/*! IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 43 +/*! IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 44 +/*! IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 45 +/*! IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 46 +/*! IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 47 +/*! IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 48 +/*! IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 49 +/*! IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 50 +/*! IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 51 +/*! IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 52 +/*! IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 53 +/*! IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 54 +/*! IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID 55 +/*! IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE 56 +/*! IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH 57 +/*! IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID 58 +/*! IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE 59 +/*! IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH 60 +/*! IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 61 +/*! IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 62 +/*! IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 63 +/*! IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 64 +/*! IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 65 +/*! IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 66 +/*! IFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 67 +/*! IFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 68 +/*! MEMDB_TCAM_IFTA30_MEM0_1_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_1_KEY_DOP_MEM0_1_KEY 69 +/*! MEMDB_TCAM_IFTA30_MEM0_1_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_1_KEY_DOP_MEM0_1_PKT_RD 70 +/*! MEMDB_TCAM_IFTA30_MEM0_3_KEY_DOP_MEM0_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_3_KEY_DOP_MEM0_3_KEY 71 +/*! MEMDB_TCAM_IFTA30_MEM0_3_KEY_DOP_MEM0_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_3_KEY_DOP_MEM0_3_PKT_RD 72 +/*! MEMDB_TCAM_IFTA30_MEM0_2_KEY_DOP_MEM0_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_2_KEY_DOP_MEM0_2_KEY 73 +/*! MEMDB_TCAM_IFTA30_MEM0_2_KEY_DOP_MEM0_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_2_KEY_DOP_MEM0_2_PKT_RD 74 +/*! MEMDB_TCAM_IFTA30_MEM0_0_KEY_DOP_MEM0_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_0_KEY_DOP_MEM0_0_KEY 75 +/*! MEMDB_TCAM_IFTA30_MEM0_0_KEY_DOP_MEM0_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_0_KEY_DOP_MEM0_0_PKT_RD 76 +/*! MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX 77 +/*! MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH 78 +/*! MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX 79 +/*! MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH 80 +/*! MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX 81 +/*! MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH 82 +/*! MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX 83 +/*! MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH 84 +/*! IPARSER2_HME_STAGE0_DOP_STAGE0_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE0_DOP_STAGE0_HFE_PROFILE_PTR 85 +/*! IPARSER2_HME_STAGE0_DOP_STAGE0_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE0_DOP_STAGE0_TCAM_TCAM_MATCH 86 +/*! IPARSER2_HME_STAGE0_DOP_STAGE0_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE0_DOP_STAGE0_SHIFT_AMOUNT 87 +/*! IPARSER2_HME_STAGE0_DOP_STAGE0_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE0_DOP_STAGE0_PKT_DATA 88 +/*! IPARSER2_HME_STAGE1_DOP_STAGE1_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE1_DOP_STAGE1_HFE_PROFILE_PTR 89 +/*! IPARSER2_HME_STAGE1_DOP_STAGE1_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE1_DOP_STAGE1_TCAM_TCAM_MATCH 90 +/*! IPARSER2_HME_STAGE1_DOP_STAGE1_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE1_DOP_STAGE1_SHIFT_AMOUNT 91 +/*! IPARSER2_HME_STAGE1_DOP_STAGE1_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE1_DOP_STAGE1_PKT_DATA 92 +/*! IPARSER2_HME_STAGE2_DOP_STAGE2_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE2_DOP_STAGE2_HFE_PROFILE_PTR 93 +/*! IPARSER2_HME_STAGE2_DOP_STAGE2_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE2_DOP_STAGE2_TCAM_TCAM_MATCH 94 +/*! IPARSER2_HME_STAGE2_DOP_STAGE2_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE2_DOP_STAGE2_SHIFT_AMOUNT 95 +/*! IPARSER2_HME_STAGE2_DOP_STAGE2_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE2_DOP_STAGE2_PKT_DATA 96 +/*! IPARSER2_HME_STAGE3_DOP_STAGE3_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE3_DOP_STAGE3_HFE_PROFILE_PTR 97 +/*! IPARSER2_HME_STAGE3_DOP_STAGE3_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE3_DOP_STAGE3_TCAM_TCAM_MATCH 98 +/*! IPARSER2_HME_STAGE3_DOP_STAGE3_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE3_DOP_STAGE3_SHIFT_AMOUNT 99 +/*! IPARSER2_HME_STAGE3_DOP_STAGE3_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE3_DOP_STAGE3_PKT_DATA 100 +/*! IPARSER2_HME_STAGE4_DOP_STAGE4_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE4_DOP_STAGE4_HFE_PROFILE_PTR 101 +/*! IPARSER2_HME_STAGE4_DOP_STAGE4_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE4_DOP_STAGE4_TCAM_TCAM_MATCH 102 +/*! IPARSER2_HME_STAGE4_DOP_STAGE4_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE4_DOP_STAGE4_SHIFT_AMOUNT 103 +/*! IPARSER2_HME_STAGE4_DOP_STAGE4_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE4_DOP_STAGE4_PKT_DATA 104 +/*! IFTA40_E2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 105 +/*! IFTA40_E2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 106 +/*! IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 107 +/*! IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 108 +/*! IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 109 +/*! IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 110 +/*! IFTA40_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 111 +/*! IFTA40_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 112 +/*! IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 113 +/*! IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 114 +/*! IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 115 +/*! IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 116 +/*! IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 117 +/*! IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 118 +/*! IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 119 +/*! IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 120 +/*! IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 121 +/*! IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 122 +/*! IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 123 +/*! IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 124 +/*! IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 125 +/*! IFTA40_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 126 +/*! IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 127 +/*! IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 128 +/*! IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 129 +/*! IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 130 +/*! IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 131 +/*! IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 132 +/*! IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 133 +/*! IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 134 +/*! IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 135 +/*! IFTA40_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 136 +/*! IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 137 +/*! IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 138 +/*! IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 139 +/*! IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 140 +/*! IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 141 +/*! IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 142 +/*! IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 143 +/*! IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 144 +/*! IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 145 +/*! IFTA40_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 146 +/*! IFTA40_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 147 +/*! IFTA40_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY 148 +/*! IFTA40_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 149 +/*! IFTA40_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY 150 +/*! IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 151 +/*! IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 152 +/*! IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 153 +/*! IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 154 +/*! IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX 155 +/*! IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH 156 +/*! IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX 157 +/*! IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH 158 +/*! IFTA40_T4T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 159 +/*! IFTA40_T4T_01_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY 160 +/*! IFTA40_T4T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 161 +/*! IFTA40_T4T_01_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY 162 +/*! IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 163 +/*! IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 164 +/*! IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 165 +/*! IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 166 +/*! IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX 167 +/*! IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH 168 +/*! IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX 169 +/*! IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH 170 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 171 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 172 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 173 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 174 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 175 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 176 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 177 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 178 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 179 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID 180 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE 181 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH 182 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH 183 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID 184 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE 185 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH 186 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH 187 +/*! IFTA40_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 188 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 189 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 190 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 191 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 192 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 193 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 194 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 195 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 196 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 197 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID 198 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE 199 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH 200 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH 201 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID 202 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE 203 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH 204 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH 205 +/*! IFTA40_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 206 +/*! MEMDB_TCAM_IFTA40_MEM0_3_KEY_DOP_MEM0_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_3_KEY_DOP_MEM0_3_KEY 207 +/*! MEMDB_TCAM_IFTA40_MEM0_3_KEY_DOP_MEM0_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_3_KEY_DOP_MEM0_3_PKT_RD 208 +/*! MEMDB_TCAM_IFTA40_MEM1_2_KEY_DOP_MEM1_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_2_KEY_DOP_MEM1_2_KEY 209 +/*! MEMDB_TCAM_IFTA40_MEM1_2_KEY_DOP_MEM1_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_2_KEY_DOP_MEM1_2_PKT_RD 210 +/*! MEMDB_TCAM_IFTA40_MEM0_2_KEY_DOP_MEM0_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_2_KEY_DOP_MEM0_2_KEY 211 +/*! MEMDB_TCAM_IFTA40_MEM0_2_KEY_DOP_MEM0_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_2_KEY_DOP_MEM0_2_PKT_RD 212 +/*! MEMDB_TCAM_IFTA40_MEM0_0_KEY_DOP_MEM0_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_0_KEY_DOP_MEM0_0_KEY 213 +/*! MEMDB_TCAM_IFTA40_MEM0_0_KEY_DOP_MEM0_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_0_KEY_DOP_MEM0_0_PKT_RD 214 +/*! MEMDB_TCAM_IFTA40_MEM1_0_KEY_DOP_MEM1_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_0_KEY_DOP_MEM1_0_KEY 215 +/*! MEMDB_TCAM_IFTA40_MEM1_0_KEY_DOP_MEM1_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_0_KEY_DOP_MEM1_0_PKT_RD 216 +/*! MEMDB_TCAM_IFTA40_MEM1_1_KEY_DOP_MEM1_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_1_KEY_DOP_MEM1_1_KEY 217 +/*! MEMDB_TCAM_IFTA40_MEM1_1_KEY_DOP_MEM1_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_1_KEY_DOP_MEM1_1_PKT_RD 218 +/*! MEMDB_TCAM_IFTA40_MEM0_1_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_1_KEY_DOP_MEM0_1_KEY 219 +/*! MEMDB_TCAM_IFTA40_MEM0_1_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_1_KEY_DOP_MEM0_1_PKT_RD 220 +/*! MEMDB_TCAM_IFTA40_MEM1_3_KEY_DOP_MEM1_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_3_KEY_DOP_MEM1_3_KEY 221 +/*! MEMDB_TCAM_IFTA40_MEM1_3_KEY_DOP_MEM1_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_3_KEY_DOP_MEM1_3_PKT_RD 222 +/*! MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX 223 +/*! MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH 224 +/*! MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX 225 +/*! MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH 226 +/*! MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX 227 +/*! MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH 228 +/*! MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX 229 +/*! MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH 230 +/*! MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX 231 +/*! MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH 232 +/*! MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX 233 +/*! MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH 234 +/*! MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_2_MATCH_INDEX 235 +/*! MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_2_TCAM_MATCH 236 +/*! MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_3_MATCH_INDEX 237 +/*! MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_3_TCAM_MATCH 238 +/*! IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 239 +/*! IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 240 +/*! IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 241 +/*! IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 242 +/*! IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 243 +/*! IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 244 +/*! IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 245 +/*! IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 246 +/*! IFTA50_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 247 +/*! IFTA50_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY 248 +/*! IFTA50_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 249 +/*! IFTA50_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY 250 +/*! IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 251 +/*! IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 252 +/*! IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 253 +/*! IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 254 +/*! IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX 255 +/*! IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH 256 +/*! IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX 257 +/*! IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH 258 +/*! IFTA50_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA50_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 259 +/*! IFTA50_I1T_00_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA50_I1T_00_INDEX_DOP_LKP0_LTPR_WIN 260 +/*! IFTA50_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA50_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 261 +/*! IFTA50_I1T_01_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA50_I1T_01_INDEX_DOP_LKP0_LTPR_WIN 262 +/*! MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_KEY_DOP_TCAM_ONLY_KEY. */ +#define BCMPKT_TRACE_DOP_MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_KEY_DOP_TCAM_ONLY_KEY 263 +/*! MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_HIT_AND_INDEX_DOP_TCAM_ONLY_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_HIT_AND_INDEX_DOP_TCAM_ONLY_MATCH_INDEX 264 +/*! MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_HIT_AND_INDEX_DOP_TCAM_ONLY_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_HIT_AND_INDEX_DOP_TCAM_ONLY_TCAM_MATCH 265 +/*! MEMDB_TCAM_IFTA50_MEM0_1_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_1_KEY_DOP_MEM0_1_KEY 266 +/*! MEMDB_TCAM_IFTA50_MEM0_1_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_1_KEY_DOP_MEM0_1_PKT_RD 267 +/*! MEMDB_TCAM_IFTA50_MEM0_3_KEY_DOP_MEM0_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_3_KEY_DOP_MEM0_3_KEY 268 +/*! MEMDB_TCAM_IFTA50_MEM0_3_KEY_DOP_MEM0_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_3_KEY_DOP_MEM0_3_PKT_RD 269 +/*! MEMDB_TCAM_IFTA50_MEM0_2_KEY_DOP_MEM0_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_2_KEY_DOP_MEM0_2_KEY 270 +/*! MEMDB_TCAM_IFTA50_MEM0_2_KEY_DOP_MEM0_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_2_KEY_DOP_MEM0_2_PKT_RD 271 +/*! MEMDB_TCAM_IFTA50_MEM0_0_KEY_DOP_MEM0_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_0_KEY_DOP_MEM0_0_KEY 272 +/*! MEMDB_TCAM_IFTA50_MEM0_0_KEY_DOP_MEM0_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_0_KEY_DOP_MEM0_0_PKT_RD 273 +/*! MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX 274 +/*! MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH 275 +/*! MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX 276 +/*! MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH 277 +/*! MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX 278 +/*! MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH 279 +/*! MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX 280 +/*! MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH 281 +/*! MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR 282 +/*! MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM0_PKT_RD 283 +/*! MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR 284 +/*! MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM1_PKT_RD 285 +/*! MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR 286 +/*! MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM2_PKT_RD 287 +/*! MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR 288 +/*! MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM3_PKT_RD 289 +/*! MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR 290 +/*! MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM0_PKT_RD 291 +/*! MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR 292 +/*! MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM1_PKT_RD 293 +/*! MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR 294 +/*! MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM2_PKT_RD 295 +/*! MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR 296 +/*! MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM3_PKT_RD 297 +/*! MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR 298 +/*! MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM4_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM4_PKT_RD 299 +/*! MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR 300 +/*! MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM5_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM5_PKT_RD 301 +/*! IFTA60_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA60_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 302 +/*! IFTA60_I1T_00_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA60_I1T_00_INDEX_DOP_LKP0_LTPR_WIN 303 +/*! IFTA60_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA60_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 304 +/*! IFTA60_I1T_01_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA60_I1T_01_INDEX_DOP_LKP0_LTPR_WIN 305 +/*! IFTA60_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA60_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 306 +/*! IFTA60_I1T_02_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA60_I1T_02_INDEX_DOP_LKP0_LTPR_WIN 307 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 308 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 309 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 310 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 311 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 312 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 313 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 314 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 315 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 316 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID 317 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE 318 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH 319 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH 320 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID 321 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE 322 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH 323 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH 324 +/*! IFTA60_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 325 +/*! MEMDB_TCAM_IFTA60_MEM0_1_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_1_KEY_DOP_MEM0_1_KEY 326 +/*! MEMDB_TCAM_IFTA60_MEM0_1_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_1_KEY_DOP_MEM0_1_PKT_RD 327 +/*! MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_1_KEY 328 +/*! MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_1_PKT_RD 329 +/*! MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_1_KEY 330 +/*! MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_1_PKT_RD 331 +/*! MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_1_KEY 332 +/*! MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_1_PKT_RD 333 +/*! MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX 334 +/*! MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH 335 +/*! MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_0_TCAM_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_0_TCAM_INDEX 336 +/*! MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX 337 +/*! MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_1_TCAM_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_1_TCAM_INDEX 338 +/*! MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH 339 +/*! MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX 340 +/*! MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_2_TCAM_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_2_TCAM_INDEX 341 +/*! MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH 342 +/*! MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX 343 +/*! MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_3_TCAM_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_3_TCAM_INDEX 344 +/*! MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH 345 +/*! MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_3_KEY 346 +/*! MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_3_PKT_RD 347 +/*! MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_0_KEY 348 +/*! MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_0_PKT_RD 349 +/*! MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_2_KEY 350 +/*! MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_2_PKT_RD 351 +/*! FLEX_DIGEST_LKUP_FD_NET_LAYER_KEY_DOP_NET_LAYER_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_KEY_DOP_NET_LAYER_TCAM_0_KEY 352 +/*! FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_0_MATCH_INDEX 353 +/*! FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_1_MATCH_INDEX 354 +/*! FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_2_MATCH_INDEX 355 +/*! FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_0_TCAM_MATCH 356 +/*! FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_1_TCAM_MATCH 357 +/*! FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_2_TCAM_MATCH 358 +/*! FLEX_DIGEST_NORM_FD_NORM_DOP_OUT_FD_NORM_FLD_BUS. */ +#define BCMPKT_TRACE_DOP_FLEX_DIGEST_NORM_FD_NORM_DOP_OUT_FD_NORM_FLD_BUS 359 +/*! FLEX_DIGEST_HASH_FD_HASH_DOP_OUT_ING_HASH_BUS. */ +#define BCMPKT_TRACE_DOP_FLEX_DIGEST_HASH_FD_HASH_DOP_OUT_ING_HASH_BUS 360 +/*! MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR 361 +/*! MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM0_PKT_RD 362 +/*! MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR 363 +/*! MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM1_PKT_RD 364 +/*! MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR 365 +/*! MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM2_PKT_RD 366 +/*! MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR 367 +/*! MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM3_PKT_RD 368 +/*! IFTA70_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA70_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 369 +/*! IFTA70_I1T_00_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA70_I1T_00_INDEX_DOP_LKP0_LTPR_WIN 370 +/*! IFTA70_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA70_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 371 +/*! IFTA70_I1T_01_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA70_I1T_01_INDEX_DOP_LKP0_LTPR_WIN 372 +/*! IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 373 +/*! IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 374 +/*! IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 375 +/*! IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 376 +/*! IFTA80_E2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 377 +/*! IFTA80_E2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 378 +/*! IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 379 +/*! IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 380 +/*! IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 381 +/*! IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 382 +/*! IFTA80_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 383 +/*! IFTA80_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 384 +/*! IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 385 +/*! IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 386 +/*! IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 387 +/*! IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 388 +/*! IFTA80_E2T_03_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 389 +/*! IFTA80_E2T_03_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 390 +/*! IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 391 +/*! IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 392 +/*! IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 393 +/*! IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 394 +/*! IFTA80_E2T_02_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 395 +/*! IFTA80_E2T_02_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 396 +/*! IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 397 +/*! IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 398 +/*! IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 399 +/*! IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 400 +/*! IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 401 +/*! IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 402 +/*! IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 403 +/*! IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 404 +/*! IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 405 +/*! IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 406 +/*! IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 407 +/*! IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 408 +/*! IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 409 +/*! IFTA80_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 410 +/*! IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 411 +/*! IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 412 +/*! IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 413 +/*! IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 414 +/*! IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 415 +/*! IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 416 +/*! IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 417 +/*! IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 418 +/*! IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 419 +/*! IFTA80_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 420 +/*! IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 421 +/*! IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 422 +/*! IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 423 +/*! IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 424 +/*! IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 425 +/*! IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 426 +/*! IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 427 +/*! IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 428 +/*! IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 429 +/*! IFTA80_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 430 +/*! IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 431 +/*! IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 432 +/*! IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 433 +/*! IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 434 +/*! IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 435 +/*! IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 436 +/*! IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 437 +/*! IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 438 +/*! IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 439 +/*! IFTA80_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 440 +/*! IFTA80_T2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 441 +/*! IFTA80_T2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 442 +/*! IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 443 +/*! IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 444 +/*! IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 445 +/*! IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 446 +/*! IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 447 +/*! IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 448 +/*! IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 449 +/*! IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 450 +/*! IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 451 +/*! IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 452 +/*! IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 453 +/*! IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 454 +/*! IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 455 +/*! IFTA80_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 456 +/*! IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 457 +/*! IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 458 +/*! IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 459 +/*! IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 460 +/*! IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 461 +/*! IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 462 +/*! IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 463 +/*! IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 464 +/*! IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 465 +/*! IFTA80_T2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 466 +/*! IFTA80_T2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 467 +/*! IFTA80_T2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 468 +/*! IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 469 +/*! IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 470 +/*! IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 471 +/*! IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 472 +/*! FLEX_QOS_PHB_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_FLEX_QOS_PHB_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 473 +/*! FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_MATCH_INDEX 474 +/*! FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH 475 +/*! FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA. */ +#define BCMPKT_TRACE_DOP_FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA 476 +/*! FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX 477 +/*! FLEX_QOS_PHB2_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_FLEX_QOS_PHB2_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 478 +/*! FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH 479 +/*! FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA. */ +#define BCMPKT_TRACE_DOP_FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA 480 +/*! FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX 481 +/*! MEMDB_TCAM_IFTA80_MEM2_0_KEY_DOP_MEM2_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_0_KEY_DOP_MEM2_0_KEY 482 +/*! MEMDB_TCAM_IFTA80_MEM2_0_KEY_DOP_MEM2_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_0_KEY_DOP_MEM2_0_PKT_RD 483 +/*! MEMDB_TCAM_IFTA80_MEM1_0_KEY_DOP_MEM1_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_0_KEY_DOP_MEM1_0_KEY 484 +/*! MEMDB_TCAM_IFTA80_MEM1_0_KEY_DOP_MEM1_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_0_KEY_DOP_MEM1_0_PKT_RD 485 +/*! MEMDB_TCAM_IFTA80_MEM7_1_KEY_DOP_MEM7_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_1_KEY_DOP_MEM7_1_KEY 486 +/*! MEMDB_TCAM_IFTA80_MEM7_1_KEY_DOP_MEM7_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_1_KEY_DOP_MEM7_1_PKT_RD 487 +/*! MEMDB_TCAM_IFTA80_MEM6_0_KEY_DOP_MEM6_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_0_KEY_DOP_MEM6_0_KEY 488 +/*! MEMDB_TCAM_IFTA80_MEM6_0_KEY_DOP_MEM6_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_0_KEY_DOP_MEM6_0_PKT_RD 489 +/*! MEMDB_TCAM_IFTA80_MEM5_0_KEY_DOP_MEM5_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_0_KEY_DOP_MEM5_0_KEY 490 +/*! MEMDB_TCAM_IFTA80_MEM5_0_KEY_DOP_MEM5_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_0_KEY_DOP_MEM5_0_PKT_RD 491 +/*! MEMDB_TCAM_IFTA80_MEM2_1_KEY_DOP_MEM2_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_1_KEY_DOP_MEM2_1_KEY 492 +/*! MEMDB_TCAM_IFTA80_MEM2_1_KEY_DOP_MEM2_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_1_KEY_DOP_MEM2_1_PKT_RD 493 +/*! MEMDB_TCAM_IFTA80_MEM5_1_KEY_DOP_MEM5_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_1_KEY_DOP_MEM5_1_KEY 494 +/*! MEMDB_TCAM_IFTA80_MEM5_1_KEY_DOP_MEM5_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_1_KEY_DOP_MEM5_1_PKT_RD 495 +/*! MEMDB_TCAM_IFTA80_MEM0_0_KEY_DOP_MEM0_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_0_KEY_DOP_MEM0_0_KEY 496 +/*! MEMDB_TCAM_IFTA80_MEM0_0_KEY_DOP_MEM0_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_0_KEY_DOP_MEM0_0_PKT_RD 497 +/*! MEMDB_TCAM_IFTA80_MEM6_1_KEY_DOP_MEM6_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_1_KEY_DOP_MEM6_1_KEY 498 +/*! MEMDB_TCAM_IFTA80_MEM6_1_KEY_DOP_MEM6_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_1_KEY_DOP_MEM6_1_PKT_RD 499 +/*! MEMDB_TCAM_IFTA80_MEM1_1_KEY_DOP_MEM1_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_1_KEY_DOP_MEM1_1_KEY 500 +/*! MEMDB_TCAM_IFTA80_MEM1_1_KEY_DOP_MEM1_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_1_KEY_DOP_MEM1_1_PKT_RD 501 +/*! MEMDB_TCAM_IFTA80_MEM4_0_KEY_DOP_MEM4_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_0_KEY_DOP_MEM4_0_KEY 502 +/*! MEMDB_TCAM_IFTA80_MEM4_0_KEY_DOP_MEM4_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_0_KEY_DOP_MEM4_0_PKT_RD 503 +/*! MEMDB_TCAM_IFTA80_MEM3_1_KEY_DOP_MEM3_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_1_KEY_DOP_MEM3_1_KEY 504 +/*! MEMDB_TCAM_IFTA80_MEM3_1_KEY_DOP_MEM3_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_1_KEY_DOP_MEM3_1_PKT_RD 505 +/*! MEMDB_TCAM_IFTA80_MEM0_1_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_1_KEY_DOP_MEM0_1_KEY 506 +/*! MEMDB_TCAM_IFTA80_MEM0_1_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_1_KEY_DOP_MEM0_1_PKT_RD 507 +/*! MEMDB_TCAM_IFTA80_MEM4_1_KEY_DOP_MEM4_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_1_KEY_DOP_MEM4_1_KEY 508 +/*! MEMDB_TCAM_IFTA80_MEM4_1_KEY_DOP_MEM4_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_1_KEY_DOP_MEM4_1_PKT_RD 509 +/*! MEMDB_TCAM_IFTA80_MEM7_0_KEY_DOP_MEM7_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_0_KEY_DOP_MEM7_0_KEY 510 +/*! MEMDB_TCAM_IFTA80_MEM7_0_KEY_DOP_MEM7_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_0_KEY_DOP_MEM7_0_PKT_RD 511 +/*! MEMDB_TCAM_IFTA80_MEM3_0_KEY_DOP_MEM3_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_0_KEY_DOP_MEM3_0_KEY 512 +/*! MEMDB_TCAM_IFTA80_MEM3_0_KEY_DOP_MEM3_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_0_KEY_DOP_MEM3_0_PKT_RD 513 +/*! MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_0_MATCH_INDEX 514 +/*! MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_0_TCAM_MATCH 515 +/*! MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_1_MATCH_INDEX 516 +/*! MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_1_TCAM_MATCH 517 +/*! MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX 518 +/*! MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH 519 +/*! MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX 520 +/*! MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH 521 +/*! MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_0_MATCH_INDEX 522 +/*! MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_0_TCAM_MATCH 523 +/*! MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_1_MATCH_INDEX 524 +/*! MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_1_TCAM_MATCH 525 +/*! MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_0_MATCH_INDEX 526 +/*! MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_0_TCAM_MATCH 527 +/*! MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_1_MATCH_INDEX 528 +/*! MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_1_TCAM_MATCH 529 +/*! MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_0_MATCH_INDEX 530 +/*! MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_0_TCAM_MATCH 531 +/*! MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_1_MATCH_INDEX 532 +/*! MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_1_TCAM_MATCH 533 +/*! MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_0_MATCH_INDEX 534 +/*! MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_0_TCAM_MATCH 535 +/*! MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_1_MATCH_INDEX 536 +/*! MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_1_TCAM_MATCH 537 +/*! MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX 538 +/*! MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH 539 +/*! MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX 540 +/*! MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH 541 +/*! MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_0_MATCH_INDEX 542 +/*! MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_0_TCAM_MATCH 543 +/*! MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_1_MATCH_INDEX 544 +/*! MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_1_TCAM_MATCH 545 +/*! IFTA90_E2T_03_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 546 +/*! IFTA90_E2T_03_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 547 +/*! IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 548 +/*! IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 549 +/*! IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 550 +/*! IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 551 +/*! IFTA90_E2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 552 +/*! IFTA90_E2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 553 +/*! IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 554 +/*! IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 555 +/*! IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 556 +/*! IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 557 +/*! IFTA90_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 558 +/*! IFTA90_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 559 +/*! IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 560 +/*! IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 561 +/*! IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 562 +/*! IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 563 +/*! IFTA90_E2T_02_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 564 +/*! IFTA90_E2T_02_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 565 +/*! IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 566 +/*! IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 567 +/*! IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 568 +/*! IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 569 +/*! IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 570 +/*! IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 571 +/*! IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 572 +/*! IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 573 +/*! IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 574 +/*! IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 575 +/*! IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 576 +/*! IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 577 +/*! IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 578 +/*! IFTA90_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 579 +/*! IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 580 +/*! IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 581 +/*! IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 582 +/*! IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 583 +/*! IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 584 +/*! IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 585 +/*! IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 586 +/*! IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 587 +/*! IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 588 +/*! IFTA90_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 589 +/*! IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 590 +/*! IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 591 +/*! IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 592 +/*! IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 593 +/*! IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 594 +/*! IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 595 +/*! IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 596 +/*! IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 597 +/*! IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 598 +/*! IFTA90_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 599 +/*! IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 600 +/*! IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 601 +/*! IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 602 +/*! IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 603 +/*! IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 604 +/*! IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 605 +/*! IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 606 +/*! IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 607 +/*! IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 608 +/*! IFTA90_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 609 +/*! FLEX_CTR_ST_ING0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0 610 +/*! FLEX_CTR_ST_ING0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1 611 +/*! FLEX_CTR_ST_ING0_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID 612 +/*! FLEX_CTR_ST_ING0_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID 613 +/*! FLEX_CTR_ST_ING0_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID 614 +/*! FLEX_CTR_ST_ING0_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID 615 +/*! FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B0 616 +/*! FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B1 617 +/*! FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B2 618 +/*! FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B3 619 +/*! FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B0 620 +/*! FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B1 621 +/*! FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B2 622 +/*! FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B3 623 +/*! FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0 624 +/*! FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1 625 +/*! FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2 626 +/*! FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3 627 +/*! FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0 628 +/*! FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1 629 +/*! FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2 630 +/*! FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3 631 +/*! FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A0 632 +/*! FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A1 633 +/*! FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A2 634 +/*! FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A3 635 +/*! FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A0 636 +/*! FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A1 637 +/*! FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A2 638 +/*! FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A3 639 +/*! IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 640 +/*! IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 641 +/*! IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 642 +/*! IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 643 +/*! IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 644 +/*! IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 645 +/*! IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 646 +/*! IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 647 +/*! IFTA100_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 648 +/*! IFTA100_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY 649 +/*! IFTA100_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 650 +/*! IFTA100_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY 651 +/*! IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 652 +/*! IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 653 +/*! IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 654 +/*! IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 655 +/*! IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX 656 +/*! IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH 657 +/*! IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX 658 +/*! IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH 659 +/*! IFTA100_T4T_02_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 660 +/*! IFTA100_T4T_02_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY 661 +/*! IFTA100_T4T_02_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 662 +/*! IFTA100_T4T_02_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY 663 +/*! IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 664 +/*! IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 665 +/*! IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 666 +/*! IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 667 +/*! IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX 668 +/*! IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH 669 +/*! IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX 670 +/*! IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH 671 +/*! IFTA100_T4T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 672 +/*! IFTA100_T4T_01_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY 673 +/*! IFTA100_T4T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 674 +/*! IFTA100_T4T_01_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY 675 +/*! IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 676 +/*! IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 677 +/*! IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 678 +/*! IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 679 +/*! IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX 680 +/*! IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH 681 +/*! IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX 682 +/*! IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH 683 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 684 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 685 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 686 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 687 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 688 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 689 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 690 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 691 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 692 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID 693 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE 694 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH 695 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH 696 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID 697 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE 698 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH 699 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH 700 +/*! IFTA100_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 701 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 702 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 703 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 704 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 705 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 706 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 707 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 708 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 709 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 710 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID 711 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE 712 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH 713 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH 714 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID 715 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE 716 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH 717 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH 718 +/*! IFTA100_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 719 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 720 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 721 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 722 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 723 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 724 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 725 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 726 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 727 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 728 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID 729 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE 730 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH 731 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH 732 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID 733 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE 734 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH 735 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH 736 +/*! IFTA100_T4T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 737 +/*! IFTA100_T4T_03_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 738 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 739 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 740 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 741 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 742 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 743 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 744 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 745 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 746 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 747 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID 748 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE 749 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH 750 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH 751 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID 752 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE 753 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH 754 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH 755 +/*! MEMDB_IFTA100_MEM1_2_KEY_DOP_MEM1_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_2_KEY_DOP_MEM1_2_KEY 756 +/*! MEMDB_IFTA100_MEM1_2_KEY_DOP_MEM1_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_2_KEY_DOP_MEM1_2_PKT_RD 757 +/*! MEMDB_IFTA100_MEM0_2_KEY_DOP_MEM0_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_2_KEY_DOP_MEM0_2_KEY 758 +/*! MEMDB_IFTA100_MEM0_2_KEY_DOP_MEM0_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_2_KEY_DOP_MEM0_2_PKT_RD 759 +/*! MEMDB_IFTA100_MEM7_2_KEY_DOP_MEM7_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_2_KEY_DOP_MEM7_2_KEY 760 +/*! MEMDB_IFTA100_MEM7_2_KEY_DOP_MEM7_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_2_KEY_DOP_MEM7_2_PKT_RD 761 +/*! MEMDB_IFTA100_MEM8_2_KEY_DOP_MEM8_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_2_KEY_DOP_MEM8_2_KEY 762 +/*! MEMDB_IFTA100_MEM8_2_KEY_DOP_MEM8_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_2_KEY_DOP_MEM8_2_PKT_RD 763 +/*! MEMDB_IFTA100_MEM9_0_KEY_DOP_MEM9_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_0_KEY_DOP_MEM9_0_KEY 764 +/*! MEMDB_IFTA100_MEM9_0_KEY_DOP_MEM9_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_0_KEY_DOP_MEM9_0_PKT_RD 765 +/*! MEMDB_IFTA100_MEM11_3_KEY_DOP_MEM11_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_3_KEY_DOP_MEM11_3_KEY 766 +/*! MEMDB_IFTA100_MEM11_3_KEY_DOP_MEM11_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_3_KEY_DOP_MEM11_3_PKT_RD 767 +/*! MEMDB_IFTA100_MEM7_3_KEY_DOP_MEM7_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_3_KEY_DOP_MEM7_3_KEY 768 +/*! MEMDB_IFTA100_MEM7_3_KEY_DOP_MEM7_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_3_KEY_DOP_MEM7_3_PKT_RD 769 +/*! MEMDB_IFTA100_MEM8_0_KEY_DOP_MEM8_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_0_KEY_DOP_MEM8_0_KEY 770 +/*! MEMDB_IFTA100_MEM8_0_KEY_DOP_MEM8_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_0_KEY_DOP_MEM8_0_PKT_RD 771 +/*! MEMDB_IFTA100_MEM10_2_KEY_DOP_MEM10_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_2_KEY_DOP_MEM10_2_KEY 772 +/*! MEMDB_IFTA100_MEM10_2_KEY_DOP_MEM10_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_2_KEY_DOP_MEM10_2_PKT_RD 773 +/*! MEMDB_IFTA100_MEM5_0_KEY_DOP_MEM5_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_0_KEY_DOP_MEM5_0_KEY 774 +/*! MEMDB_IFTA100_MEM5_0_KEY_DOP_MEM5_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_0_KEY_DOP_MEM5_0_PKT_RD 775 +/*! MEMDB_IFTA100_MEM3_2_KEY_DOP_MEM3_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_2_KEY_DOP_MEM3_2_KEY 776 +/*! MEMDB_IFTA100_MEM3_2_KEY_DOP_MEM3_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_2_KEY_DOP_MEM3_2_PKT_RD 777 +/*! MEMDB_IFTA100_MEM8_3_KEY_DOP_MEM8_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_3_KEY_DOP_MEM8_3_KEY 778 +/*! MEMDB_IFTA100_MEM8_3_KEY_DOP_MEM8_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_3_KEY_DOP_MEM8_3_PKT_RD 779 +/*! MEMDB_IFTA100_MEM11_0_KEY_DOP_MEM11_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_0_KEY_DOP_MEM11_0_KEY 780 +/*! MEMDB_IFTA100_MEM11_0_KEY_DOP_MEM11_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_0_KEY_DOP_MEM11_0_PKT_RD 781 +/*! MEMDB_IFTA100_MEM2_1_KEY_DOP_MEM2_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_1_KEY_DOP_MEM2_1_KEY 782 +/*! MEMDB_IFTA100_MEM2_1_KEY_DOP_MEM2_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_1_KEY_DOP_MEM2_1_PKT_RD 783 +/*! MEMDB_IFTA100_MEM4_3_KEY_DOP_MEM4_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_3_KEY_DOP_MEM4_3_KEY 784 +/*! MEMDB_IFTA100_MEM4_3_KEY_DOP_MEM4_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_3_KEY_DOP_MEM4_3_PKT_RD 785 +/*! MEMDB_IFTA100_MEM4_2_KEY_DOP_MEM4_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_2_KEY_DOP_MEM4_2_KEY 786 +/*! MEMDB_IFTA100_MEM4_2_KEY_DOP_MEM4_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_2_KEY_DOP_MEM4_2_PKT_RD 787 +/*! MEMDB_IFTA100_MEM5_3_KEY_DOP_MEM5_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_3_KEY_DOP_MEM5_3_KEY 788 +/*! MEMDB_IFTA100_MEM5_3_KEY_DOP_MEM5_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_3_KEY_DOP_MEM5_3_PKT_RD 789 +/*! MEMDB_IFTA100_MEM10_1_KEY_DOP_MEM10_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_1_KEY_DOP_MEM10_1_KEY 790 +/*! MEMDB_IFTA100_MEM10_1_KEY_DOP_MEM10_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_1_KEY_DOP_MEM10_1_PKT_RD 791 +/*! MEMDB_IFTA100_MEM6_1_KEY_DOP_MEM6_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_1_KEY_DOP_MEM6_1_KEY 792 +/*! MEMDB_IFTA100_MEM6_1_KEY_DOP_MEM6_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_1_KEY_DOP_MEM6_1_PKT_RD 793 +/*! MEMDB_IFTA100_MEM10_3_KEY_DOP_MEM10_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_3_KEY_DOP_MEM10_3_KEY 794 +/*! MEMDB_IFTA100_MEM10_3_KEY_DOP_MEM10_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_3_KEY_DOP_MEM10_3_PKT_RD 795 +/*! MEMDB_IFTA100_MEM4_1_KEY_DOP_MEM4_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_1_KEY_DOP_MEM4_1_KEY 796 +/*! MEMDB_IFTA100_MEM4_1_KEY_DOP_MEM4_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_1_KEY_DOP_MEM4_1_PKT_RD 797 +/*! MEMDB_IFTA100_MEM9_2_KEY_DOP_MEM9_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_2_KEY_DOP_MEM9_2_KEY 798 +/*! MEMDB_IFTA100_MEM9_2_KEY_DOP_MEM9_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_2_KEY_DOP_MEM9_2_PKT_RD 799 +/*! MEMDB_IFTA100_MEM3_0_KEY_DOP_MEM3_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_0_KEY_DOP_MEM3_0_KEY 800 +/*! MEMDB_IFTA100_MEM3_0_KEY_DOP_MEM3_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_0_KEY_DOP_MEM3_0_PKT_RD 801 +/*! MEMDB_IFTA100_MEM2_0_KEY_DOP_MEM2_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_0_KEY_DOP_MEM2_0_KEY 802 +/*! MEMDB_IFTA100_MEM2_0_KEY_DOP_MEM2_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_0_KEY_DOP_MEM2_0_PKT_RD 803 +/*! MEMDB_IFTA100_MEM1_0_KEY_DOP_MEM1_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_0_KEY_DOP_MEM1_0_KEY 804 +/*! MEMDB_IFTA100_MEM1_0_KEY_DOP_MEM1_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_0_KEY_DOP_MEM1_0_PKT_RD 805 +/*! MEMDB_IFTA100_MEM11_1_KEY_DOP_MEM11_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_1_KEY_DOP_MEM11_1_KEY 806 +/*! MEMDB_IFTA100_MEM11_1_KEY_DOP_MEM11_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_1_KEY_DOP_MEM11_1_PKT_RD 807 +/*! MEMDB_IFTA100_MEM2_2_KEY_DOP_MEM2_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_2_KEY_DOP_MEM2_2_KEY 808 +/*! MEMDB_IFTA100_MEM2_2_KEY_DOP_MEM2_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_2_KEY_DOP_MEM2_2_PKT_RD 809 +/*! MEMDB_IFTA100_MEM8_1_KEY_DOP_MEM8_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_1_KEY_DOP_MEM8_1_KEY 810 +/*! MEMDB_IFTA100_MEM8_1_KEY_DOP_MEM8_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_1_KEY_DOP_MEM8_1_PKT_RD 811 +/*! MEMDB_IFTA100_MEM7_1_KEY_DOP_MEM7_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_1_KEY_DOP_MEM7_1_KEY 812 +/*! MEMDB_IFTA100_MEM7_1_KEY_DOP_MEM7_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_1_KEY_DOP_MEM7_1_PKT_RD 813 +/*! MEMDB_IFTA100_MEM9_3_KEY_DOP_MEM9_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_3_KEY_DOP_MEM9_3_KEY 814 +/*! MEMDB_IFTA100_MEM9_3_KEY_DOP_MEM9_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_3_KEY_DOP_MEM9_3_PKT_RD 815 +/*! MEMDB_IFTA100_MEM6_0_KEY_DOP_MEM6_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_0_KEY_DOP_MEM6_0_KEY 816 +/*! MEMDB_IFTA100_MEM6_0_KEY_DOP_MEM6_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_0_KEY_DOP_MEM6_0_PKT_RD 817 +/*! MEMDB_IFTA100_MEM6_2_KEY_DOP_MEM6_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_2_KEY_DOP_MEM6_2_KEY 818 +/*! MEMDB_IFTA100_MEM6_2_KEY_DOP_MEM6_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_2_KEY_DOP_MEM6_2_PKT_RD 819 +/*! MEMDB_IFTA100_MEM9_1_KEY_DOP_MEM9_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_1_KEY_DOP_MEM9_1_KEY 820 +/*! MEMDB_IFTA100_MEM9_1_KEY_DOP_MEM9_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_1_KEY_DOP_MEM9_1_PKT_RD 821 +/*! MEMDB_IFTA100_MEM5_1_KEY_DOP_MEM5_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_1_KEY_DOP_MEM5_1_KEY 822 +/*! MEMDB_IFTA100_MEM5_1_KEY_DOP_MEM5_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_1_KEY_DOP_MEM5_1_PKT_RD 823 +/*! MEMDB_IFTA100_MEM0_3_KEY_DOP_MEM0_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_3_KEY_DOP_MEM0_3_KEY 824 +/*! MEMDB_IFTA100_MEM0_3_KEY_DOP_MEM0_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_3_KEY_DOP_MEM0_3_PKT_RD 825 +/*! MEMDB_IFTA100_MEM3_3_KEY_DOP_MEM3_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_3_KEY_DOP_MEM3_3_KEY 826 +/*! MEMDB_IFTA100_MEM3_3_KEY_DOP_MEM3_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_3_KEY_DOP_MEM3_3_PKT_RD 827 +/*! MEMDB_IFTA100_MEM0_0_KEY_DOP_MEM0_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_0_KEY_DOP_MEM0_0_KEY 828 +/*! MEMDB_IFTA100_MEM0_0_KEY_DOP_MEM0_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_0_KEY_DOP_MEM0_0_PKT_RD 829 +/*! MEMDB_IFTA100_MEM1_1_KEY_DOP_MEM1_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_1_KEY_DOP_MEM1_1_KEY 830 +/*! MEMDB_IFTA100_MEM1_1_KEY_DOP_MEM1_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_1_KEY_DOP_MEM1_1_PKT_RD 831 +/*! MEMDB_IFTA100_MEM4_0_KEY_DOP_MEM4_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_0_KEY_DOP_MEM4_0_KEY 832 +/*! MEMDB_IFTA100_MEM4_0_KEY_DOP_MEM4_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_0_KEY_DOP_MEM4_0_PKT_RD 833 +/*! MEMDB_IFTA100_MEM3_1_KEY_DOP_MEM3_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_1_KEY_DOP_MEM3_1_KEY 834 +/*! MEMDB_IFTA100_MEM3_1_KEY_DOP_MEM3_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_1_KEY_DOP_MEM3_1_PKT_RD 835 +/*! MEMDB_IFTA100_MEM2_3_KEY_DOP_MEM2_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_3_KEY_DOP_MEM2_3_KEY 836 +/*! MEMDB_IFTA100_MEM2_3_KEY_DOP_MEM2_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_3_KEY_DOP_MEM2_3_PKT_RD 837 +/*! MEMDB_IFTA100_MEM10_0_KEY_DOP_MEM10_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_0_KEY_DOP_MEM10_0_KEY 838 +/*! MEMDB_IFTA100_MEM10_0_KEY_DOP_MEM10_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_0_KEY_DOP_MEM10_0_PKT_RD 839 +/*! MEMDB_IFTA100_MEM6_3_KEY_DOP_MEM6_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_3_KEY_DOP_MEM6_3_KEY 840 +/*! MEMDB_IFTA100_MEM6_3_KEY_DOP_MEM6_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_3_KEY_DOP_MEM6_3_PKT_RD 841 +/*! MEMDB_IFTA100_MEM0_1_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_1_KEY_DOP_MEM0_1_KEY 842 +/*! MEMDB_IFTA100_MEM0_1_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_1_KEY_DOP_MEM0_1_PKT_RD 843 +/*! MEMDB_IFTA100_MEM5_2_KEY_DOP_MEM5_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_2_KEY_DOP_MEM5_2_KEY 844 +/*! MEMDB_IFTA100_MEM5_2_KEY_DOP_MEM5_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_2_KEY_DOP_MEM5_2_PKT_RD 845 +/*! MEMDB_IFTA100_MEM7_0_KEY_DOP_MEM7_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_0_KEY_DOP_MEM7_0_KEY 846 +/*! MEMDB_IFTA100_MEM7_0_KEY_DOP_MEM7_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_0_KEY_DOP_MEM7_0_PKT_RD 847 +/*! MEMDB_IFTA100_MEM1_3_KEY_DOP_MEM1_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_3_KEY_DOP_MEM1_3_KEY 848 +/*! MEMDB_IFTA100_MEM1_3_KEY_DOP_MEM1_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_3_KEY_DOP_MEM1_3_PKT_RD 849 +/*! MEMDB_IFTA100_MEM11_2_KEY_DOP_MEM11_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_2_KEY_DOP_MEM11_2_KEY 850 +/*! MEMDB_IFTA100_MEM11_2_KEY_DOP_MEM11_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_2_KEY_DOP_MEM11_2_PKT_RD 851 +/*! MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_0_MATCH_INDEX 852 +/*! MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_0_TCAM_MATCH 853 +/*! MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_1_MATCH_INDEX 854 +/*! MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_1_TCAM_MATCH 855 +/*! MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_2_MATCH_INDEX 856 +/*! MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_2_TCAM_MATCH 857 +/*! MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_3_MATCH_INDEX 858 +/*! MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_3_TCAM_MATCH 859 +/*! MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_0_MATCH_INDEX 860 +/*! MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_0_TCAM_MATCH 861 +/*! MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_1_MATCH_INDEX 862 +/*! MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_1_TCAM_MATCH 863 +/*! MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_2_MATCH_INDEX 864 +/*! MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_2_TCAM_MATCH 865 +/*! MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_3_MATCH_INDEX 866 +/*! MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_3_TCAM_MATCH 867 +/*! MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_0_MATCH_INDEX 868 +/*! MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_0_TCAM_MATCH 869 +/*! MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_1_MATCH_INDEX 870 +/*! MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_1_TCAM_MATCH 871 +/*! MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_2_MATCH_INDEX 872 +/*! MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_2_TCAM_MATCH 873 +/*! MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_3_MATCH_INDEX 874 +/*! MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_3_TCAM_MATCH 875 +/*! MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_0_MATCH_INDEX 876 +/*! MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_0_TCAM_MATCH 877 +/*! MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_1_MATCH_INDEX 878 +/*! MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_1_TCAM_MATCH 879 +/*! MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_2_MATCH_INDEX 880 +/*! MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_2_TCAM_MATCH 881 +/*! MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_3_MATCH_INDEX 882 +/*! MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_3_TCAM_MATCH 883 +/*! MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_0_MATCH_INDEX 884 +/*! MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_0_TCAM_MATCH 885 +/*! MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_1_MATCH_INDEX 886 +/*! MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_1_TCAM_MATCH 887 +/*! MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_2_MATCH_INDEX 888 +/*! MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_2_TCAM_MATCH 889 +/*! MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_3_MATCH_INDEX 890 +/*! MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_3_TCAM_MATCH 891 +/*! MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_0_MATCH_INDEX 892 +/*! MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_0_TCAM_MATCH 893 +/*! MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_1_MATCH_INDEX 894 +/*! MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_1_TCAM_MATCH 895 +/*! MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_2_MATCH_INDEX 896 +/*! MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_2_TCAM_MATCH 897 +/*! MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_3_MATCH_INDEX 898 +/*! MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_3_TCAM_MATCH 899 +/*! MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_0_MATCH_INDEX 900 +/*! MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_0_TCAM_MATCH 901 +/*! MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_1_MATCH_INDEX 902 +/*! MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_1_TCAM_MATCH 903 +/*! MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_2_MATCH_INDEX 904 +/*! MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_2_TCAM_MATCH 905 +/*! MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_3_MATCH_INDEX 906 +/*! MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_3_TCAM_MATCH 907 +/*! MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_0_MATCH_INDEX 908 +/*! MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_0_TCAM_MATCH 909 +/*! MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_1_MATCH_INDEX 910 +/*! MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_1_TCAM_MATCH 911 +/*! MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_2_MATCH_INDEX 912 +/*! MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_2_TCAM_MATCH 913 +/*! MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_3_MATCH_INDEX 914 +/*! MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_3_TCAM_MATCH 915 +/*! MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX 916 +/*! MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH 917 +/*! MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX 918 +/*! MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH 919 +/*! MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_2_MATCH_INDEX 920 +/*! MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_2_TCAM_MATCH 921 +/*! MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_3_MATCH_INDEX 922 +/*! MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_3_TCAM_MATCH 923 +/*! MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_0_MATCH_INDEX 924 +/*! MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_0_TCAM_MATCH 925 +/*! MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_1_MATCH_INDEX 926 +/*! MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_1_TCAM_MATCH 927 +/*! MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_2_MATCH_INDEX 928 +/*! MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_2_TCAM_MATCH 929 +/*! MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_3_MATCH_INDEX 930 +/*! MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_3_TCAM_MATCH 931 +/*! MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_0_MATCH_INDEX 932 +/*! MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_0_TCAM_MATCH 933 +/*! MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_1_MATCH_INDEX 934 +/*! MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_1_TCAM_MATCH 935 +/*! MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_2_MATCH_INDEX 936 +/*! MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_2_TCAM_MATCH 937 +/*! MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_3_MATCH_INDEX 938 +/*! MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_3_TCAM_MATCH 939 +/*! MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX 940 +/*! MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH 941 +/*! MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX 942 +/*! MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH 943 +/*! MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX 944 +/*! MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH 945 +/*! MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX 946 +/*! MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH 947 +/*! IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 948 +/*! IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 949 +/*! IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 950 +/*! IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 951 +/*! ECMP_GROUP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX. */ +#define BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX 952 +/*! ECMP_GROUP_LEVEL0_GROUP_TABLE_DATA_DOP_GROUP_TABLE_DATA. */ +#define BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL0_GROUP_TABLE_DATA_DOP_GROUP_TABLE_DATA 953 +/*! ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX. */ +#define BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX 954 +/*! ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP_HASH. */ +#define BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP_HASH 955 +/*! ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP_MODULO_OFFSET. */ +#define BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP_MODULO_OFFSET 956 +/*! MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR 957 +/*! MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM0_PKT_RD 958 +/*! MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR 959 +/*! MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM1_PKT_RD 960 +/*! ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_B1. */ +#define BCMPKT_TRACE_DOP_ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_B1 961 +/*! ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_B0. */ +#define BCMPKT_TRACE_DOP_ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_B0 962 +/*! ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_A1. */ +#define BCMPKT_TRACE_DOP_ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_A1 963 +/*! ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_A0. */ +#define BCMPKT_TRACE_DOP_ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_A0 964 +/*! ETRAP_ETR_HIT_RTAG_HASH_DOP_ETR_HIT. */ +#define BCMPKT_TRACE_DOP_ETRAP_ETR_HIT_RTAG_HASH_DOP_ETR_HIT 965 +/*! ETRAP_ETR_OUT_DOP_FLW_OFMT_FLOW_TABLE_HIT. */ +#define BCMPKT_TRACE_DOP_ETRAP_ETR_OUT_DOP_FLW_OFMT_FLOW_TABLE_HIT 966 +/*! ETRAP_ETR_OUT_DOP_EOP_FLOW_TABLE_HIT_PM2. */ +#define BCMPKT_TRACE_DOP_ETRAP_ETR_OUT_DOP_EOP_FLOW_TABLE_HIT_PM2 967 +/*! ETRAP_ETR_OUT_DOP_ETR_CNG. */ +#define BCMPKT_TRACE_DOP_ETRAP_ETR_OUT_DOP_ETR_CNG 968 +/*! ETRAP_ETR_OUT_DOP_ETR_VALID. */ +#define BCMPKT_TRACE_DOP_ETRAP_ETR_OUT_DOP_ETR_VALID 969 +/*! DLB_ECMP_DLB_ECMP_CURRENT_TIME_DOP_CURRENT_TIME. */ +#define BCMPKT_TRACE_DOP_DLB_ECMP_DLB_ECMP_CURRENT_TIME_DOP_CURRENT_TIME 970 +/*! DLB_ECMP_DLB_ECMP_FLOWSET_INDEX_DOP_FLOWSET_INDEX. */ +#define BCMPKT_TRACE_DOP_DLB_ECMP_DLB_ECMP_FLOWSET_INDEX_DOP_FLOWSET_INDEX 971 +/*! ECMP_GROUP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX. */ +#define BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX 972 +/*! ECMP_GROUP_LEVEL1_GROUP_TABLE_DATA_DOP_GROUP_TABLE_DATA. */ +#define BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL1_GROUP_TABLE_DATA_DOP_GROUP_TABLE_DATA 973 +/*! ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX. */ +#define BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX 974 +/*! ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP_HASH. */ +#define BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP_HASH 975 +/*! ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP_MODULO_OFFSET. */ +#define BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP_MODULO_OFFSET 976 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR 977 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM0_PKT_RD 978 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR 979 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM1_PKT_RD 980 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR 981 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM2_PKT_RD 982 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR 983 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM3_PKT_RD 984 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR 985 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM4_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM4_PKT_RD 986 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR 987 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM5_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM5_PKT_RD 988 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR 989 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM6_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM6_PKT_RD 990 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR 991 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM7_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM7_PKT_RD 992 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR 993 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM0_PKT_RD 994 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR 995 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM1_PKT_RD 996 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR 997 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM2_PKT_RD 998 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR 999 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM3_PKT_RD 1000 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR 1001 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM4_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM4_PKT_RD 1002 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR 1003 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM5_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM5_PKT_RD 1004 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR 1005 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM6_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM6_PKT_RD 1006 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR 1007 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM7_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM7_PKT_RD 1008 +/*! IFTA130_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA130_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1009 +/*! IFTA130_I1T_00_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA130_I1T_00_INDEX_DOP_LKP0_LTPR_WIN 1010 +/*! IFTA130_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA130_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1011 +/*! IFTA130_I1T_01_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA130_I1T_01_INDEX_DOP_LKP0_LTPR_WIN 1012 +/*! IFTA130_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA130_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1013 +/*! IFTA130_I1T_02_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA130_I1T_02_INDEX_DOP_LKP0_LTPR_WIN 1014 +/*! IFTA130_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA130_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1015 +/*! IFTA130_I1T_03_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA130_I1T_03_INDEX_DOP_LKP0_LTPR_WIN 1016 +/*! MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR 1017 +/*! MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM0_PKT_RD 1018 +/*! MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR 1019 +/*! MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM1_PKT_RD 1020 +/*! IFTA140_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA140_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1021 +/*! IFTA140_I1T_00_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA140_I1T_00_INDEX_DOP_LKP0_LTPR_WIN 1022 +/*! IFTA140_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA140_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1023 +/*! IFTA140_I1T_01_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA140_I1T_01_INDEX_DOP_LKP0_LTPR_WIN 1024 +/*! FLEX_CTR_ST_ING1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0 1025 +/*! FLEX_CTR_ST_ING1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1 1026 +/*! FLEX_CTR_ST_ING1_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID 1027 +/*! FLEX_CTR_ST_ING1_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID 1028 +/*! FLEX_CTR_ST_ING1_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID 1029 +/*! FLEX_CTR_ST_ING1_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID 1030 +/*! FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B0 1031 +/*! FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B1 1032 +/*! FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B2 1033 +/*! FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B3 1034 +/*! FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B0 1035 +/*! FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B1 1036 +/*! FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B2 1037 +/*! FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B3 1038 +/*! FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0 1039 +/*! FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1 1040 +/*! FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2 1041 +/*! FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3 1042 +/*! FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0 1043 +/*! FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1 1044 +/*! FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2 1045 +/*! FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3 1046 +/*! FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A0 1047 +/*! FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A1 1048 +/*! FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A2 1049 +/*! FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A3 1050 +/*! FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A0 1051 +/*! FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A1 1052 +/*! FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A2 1053 +/*! FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A3 1054 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1055 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 1056 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 1057 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 1058 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 1059 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1060 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 1061 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 1062 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 1063 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE 1064 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1065 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE 1066 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH 1067 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH 1068 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1069 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH 1070 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH 1071 +/*! IFTA150_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 1072 +/*! IFTA150_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 1073 +/*! IFTA150_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY 1074 +/*! IFTA150_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 1075 +/*! IFTA150_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY 1076 +/*! IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 1077 +/*! IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 1078 +/*! IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 1079 +/*! IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 1080 +/*! IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX 1081 +/*! IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH 1082 +/*! IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX 1083 +/*! IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH 1084 +/*! MEMDB_IFTA150_MEM0_1_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_1_KEY_DOP_MEM0_1_KEY 1085 +/*! MEMDB_IFTA150_MEM0_1_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_1_KEY_DOP_MEM0_1_PKT_RD 1086 +/*! MEMDB_IFTA150_MEM0_3_KEY_DOP_MEM0_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_3_KEY_DOP_MEM0_3_KEY 1087 +/*! MEMDB_IFTA150_MEM0_3_KEY_DOP_MEM0_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_3_KEY_DOP_MEM0_3_PKT_RD 1088 +/*! MEMDB_IFTA150_MEM0_2_KEY_DOP_MEM0_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_2_KEY_DOP_MEM0_2_KEY 1089 +/*! MEMDB_IFTA150_MEM0_2_KEY_DOP_MEM0_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_2_KEY_DOP_MEM0_2_PKT_RD 1090 +/*! MEMDB_IFTA150_MEM0_0_KEY_DOP_MEM0_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_0_KEY_DOP_MEM0_0_KEY 1091 +/*! MEMDB_IFTA150_MEM0_0_KEY_DOP_MEM0_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_0_KEY_DOP_MEM0_0_PKT_RD 1092 +/*! MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX 1093 +/*! MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH 1094 +/*! MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX 1095 +/*! MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH 1096 +/*! MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX 1097 +/*! MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH 1098 +/*! MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX 1099 +/*! MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH 1100 +/*! IPOST_DLB_LAG_DLB_LAG_CURRENT_TIME_DOP_CURRENT_TIME. */ +#define BCMPKT_TRACE_DOP_IPOST_DLB_LAG_DLB_LAG_CURRENT_TIME_DOP_CURRENT_TIME 1101 +/*! IPOST_DLB_LAG_DLB_LAG_FLOWSET_INDEX_DOP_FLOWSET_INDEX. */ +#define BCMPKT_TRACE_DOP_IPOST_DLB_LAG_DLB_LAG_FLOWSET_INDEX_DOP_FLOWSET_INDEX 1102 +/*! IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_BUS. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_BUS 1103 +/*! IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_0. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_0 1104 +/*! IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_1. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_1 1105 +/*! IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_2. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_2 1106 +/*! IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_3. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_3 1107 +/*! IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_4. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_4 1108 +/*! IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_5. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_5 1109 +/*! IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_6. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_6 1110 +/*! IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_7. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_7 1111 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_0_RDATA. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_0_RDATA 1112 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_1_RDATA. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_1_RDATA 1113 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_2_RDATA. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_2_RDATA 1114 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_3_RDATA. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_3_RDATA 1115 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_4_RDATA. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_4_RDATA 1116 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_5_RDATA. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_5_RDATA 1117 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_6_RDATA. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_6_RDATA 1118 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_7_RDATA. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_7_RDATA 1119 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_0_WINNER. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_0_WINNER 1120 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_1_WINNER. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_1_WINNER 1121 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_2_WINNER. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_2_WINNER 1122 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_3_WINNER. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_3_WINNER 1123 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_4_WINNER. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_4_WINNER 1124 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_5_WINNER. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_5_WINNER 1125 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_6_WINNER. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_6_WINNER 1126 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_7_WINNER. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_7_WINNER 1127 +/*! IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 1128 +/*! IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_INDEX_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_INDEX_DOP_LTS_TCAM_MATCH_INDEX 1129 +/*! IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH 1130 +/*! IPOST_CPU_COS_CPU_COS_MAP_TCAM_KEY_DOP_CPU_COS_MAP_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_IPOST_CPU_COS_CPU_COS_MAP_TCAM_KEY_DOP_CPU_COS_MAP_TCAM_KEY 1131 +/*! IPOST_CPU_COS_CPU_COS_MAP_TCAM_INDEX_DOP_CPU_COS_MAP_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IPOST_CPU_COS_CPU_COS_MAP_TCAM_INDEX_DOP_CPU_COS_MAP_TCAM_MATCH_INDEX 1132 +/*! IPOST_CPU_COS_CPU_COS_MAP_TCAM_INDEX_DOP_CPU_COS_MAP_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPOST_CPU_COS_CPU_COS_MAP_TCAM_INDEX_DOP_CPU_COS_MAP_TCAM_TCAM_MATCH 1133 +/*! IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY 1134 +/*! IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_MATCH_INDEX 1135 +/*! IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_TCAM_MATCH 1136 +/*! IPOST_MPB_ENCODE_MPB_FLEX_BUS_DOP_OUT_MPB_FLEX_BUS. */ +#define BCMPKT_TRACE_DOP_IPOST_MPB_ENCODE_MPB_FLEX_BUS_DOP_OUT_MPB_FLEX_BUS 1137 +/*! IPOST_MPB_CCBI_FIXED_CCBI_B_BUS_DOP_OUT_CCBI_B_BUS. */ +#define BCMPKT_TRACE_DOP_IPOST_MPB_CCBI_FIXED_CCBI_B_BUS_DOP_OUT_CCBI_B_BUS 1138 +/*! IPOST_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP_OUT_MPB_FIXED_BUS. */ +#define BCMPKT_TRACE_DOP_IPOST_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP_OUT_MPB_FIXED_BUS 1139 +/*! FLEX_CTR_ING_COUNTER_ACTION_VECTOR_DOP_ING_FLEX_CTR_BUS. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_ACTION_VECTOR_DOP_ING_FLEX_CTR_BUS 1140 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_2_DOP_COUNTER_EOP_BUFFER_2_PKT_WDATA_COUNTER_EOP_BUFFER_2_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_2_DOP_COUNTER_EOP_BUFFER_2_PKT_WDATA_COUNTER_EOP_BUFFER_2_PKT_WR 1141 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_11_DOP_COUNTER_EOP_BUFFER_11_PKT_WDATA_COUNTER_EOP_BUFFER_11_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_11_DOP_COUNTER_EOP_BUFFER_11_PKT_WDATA_COUNTER_EOP_BUFFER_11_PKT_WR 1142 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_8_DOP_COUNTER_EOP_BUFFER_8_PKT_WDATA_COUNTER_EOP_BUFFER_8_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_8_DOP_COUNTER_EOP_BUFFER_8_PKT_WDATA_COUNTER_EOP_BUFFER_8_PKT_WR 1143 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_7_DOP_COUNTER_EOP_BUFFER_7_PKT_WDATA_COUNTER_EOP_BUFFER_7_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_7_DOP_COUNTER_EOP_BUFFER_7_PKT_WDATA_COUNTER_EOP_BUFFER_7_PKT_WR 1144 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_5_DOP_COUNTER_EOP_BUFFER_5_PKT_WDATA_COUNTER_EOP_BUFFER_5_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_5_DOP_COUNTER_EOP_BUFFER_5_PKT_WDATA_COUNTER_EOP_BUFFER_5_PKT_WR 1145 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_9_DOP_COUNTER_EOP_BUFFER_9_PKT_WDATA_COUNTER_EOP_BUFFER_9_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_9_DOP_COUNTER_EOP_BUFFER_9_PKT_WDATA_COUNTER_EOP_BUFFER_9_PKT_WR 1146 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_6_DOP_COUNTER_EOP_BUFFER_6_PKT_WDATA_COUNTER_EOP_BUFFER_6_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_6_DOP_COUNTER_EOP_BUFFER_6_PKT_WDATA_COUNTER_EOP_BUFFER_6_PKT_WR 1147 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_0_DOP_COUNTER_EOP_BUFFER_0_PKT_WDATA_COUNTER_EOP_BUFFER_0_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_0_DOP_COUNTER_EOP_BUFFER_0_PKT_WDATA_COUNTER_EOP_BUFFER_0_PKT_WR 1148 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_1_DOP_COUNTER_EOP_BUFFER_1_PKT_WDATA_COUNTER_EOP_BUFFER_1_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_1_DOP_COUNTER_EOP_BUFFER_1_PKT_WDATA_COUNTER_EOP_BUFFER_1_PKT_WR 1149 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_4_DOP_COUNTER_EOP_BUFFER_4_PKT_WDATA_COUNTER_EOP_BUFFER_4_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_4_DOP_COUNTER_EOP_BUFFER_4_PKT_WDATA_COUNTER_EOP_BUFFER_4_PKT_WR 1150 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_3_DOP_COUNTER_EOP_BUFFER_3_PKT_WDATA_COUNTER_EOP_BUFFER_3_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_3_DOP_COUNTER_EOP_BUFFER_3_PKT_WDATA_COUNTER_EOP_BUFFER_3_PKT_WR 1151 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_10_DOP_COUNTER_EOP_BUFFER_10_PKT_WDATA_COUNTER_EOP_BUFFER_10_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_10_DOP_COUNTER_EOP_BUFFER_10_PKT_WDATA_COUNTER_EOP_BUFFER_10_PKT_WR 1152 +/*! IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 1153 +/*! IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 1154 +/*! IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 1155 +/*! IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 1156 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_4_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_4_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_4_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_4_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR 1157 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_1_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_1_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_1_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_1_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR 1158 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_3_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_3_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_3_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_3_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR 1159 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_2_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_2_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_2_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_2_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR 1160 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_0_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_0_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_0_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_0_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR 1161 +/*! EPRE_PARSER_ZONE_REMAP_EGR_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP_FIELD_EXTRACTION_PROFILE_CONTROL_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_EGR_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP_FIELD_EXTRACTION_PROFILE_CONTROL_PKT_ADDR 1162 +/*! EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER0_CTRL_DOP_OUT_EGR_SCR_EPRE2EPARSER0_BUS. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER0_CTRL_DOP_OUT_EGR_SCR_EPRE2EPARSER0_BUS 1163 +/*! EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER1_CTRL_DOP_OUT_EGR_SCR_EPRE2EPARSER1_BUS. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER1_CTRL_DOP_OUT_EGR_SCR_EPRE2EPARSER1_BUS 1164 +/*! EPRE_EDEV_CONFIG_EGR_INT_CN_UPDATE_INDEX_DOP_EGR_INT_CN_UPDATE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_EGR_INT_CN_UPDATE_INDEX_DOP_EGR_INT_CN_UPDATE_PKT_ADDR 1165 +/*! EPRE_EDEV_CONFIG_FORWARDING_TYPE_TABLE_INDEX_DOP_FORWARDING_TYPE_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_FORWARDING_TYPE_TABLE_INDEX_DOP_FORWARDING_TYPE_TABLE_PKT_ADDR 1166 +/*! EPRE_EDEV_CONFIG_MPB_FIXED_DOP_MPB_FIXED. */ +#define BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_MPB_FIXED_DOP_MPB_FIXED 1167 +/*! EPRE_EDEV_CONFIG_CCBE_DOP_CCBE_BUS. */ +#define BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_CCBE_DOP_CCBE_BUS 1168 +/*! EPRE_EDEV_CONFIG_EGR_TABLE_INDEX_UPDATE_PROFILE_INDEX_DOP_EGR_TABLE_INDEX_UPDATE_PROFILE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_EGR_TABLE_INDEX_UPDATE_PROFILE_INDEX_DOP_EGR_TABLE_INDEX_UPDATE_PROFILE_PKT_ADDR 1169 +/*! EPRE_EDEV_CONFIG_MIRROR_ATTRIBUTES_TABLE_INDEX_DOP_MIRROR_ATTRIBUTES_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_MIRROR_ATTRIBUTES_TABLE_INDEX_DOP_MIRROR_ATTRIBUTES_TABLE_PKT_ADDR 1170 +/*! EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP_PDD_PROFILE_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP_PDD_PROFILE_TABLE_PKT_ADDR 1171 +/*! EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP_MPB_FLEX. */ +#define BCMPKT_TRACE_DOP_EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP_MPB_FLEX 1172 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR 1173 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_RD 1174 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR 1175 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_RD 1176 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR 1177 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM2_PKT_RD 1178 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR 1179 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM3_PKT_RD 1180 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR 1181 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM4_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM4_PKT_RD 1182 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR 1183 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM5_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM5_PKT_RD 1184 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR 1185 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM6_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM6_PKT_RD 1186 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR 1187 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM7_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM7_PKT_RD 1188 +/*! EFTA10_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA10_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1189 +/*! EFTA10_I1T_00_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA10_I1T_00_INDEX_DOP_LKP0_LTPR_WIN 1190 +/*! EFTA10_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA10_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1191 +/*! EFTA10_I1T_01_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA10_I1T_01_INDEX_DOP_LKP0_LTPR_WIN 1192 +/*! EFTA10_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA10_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1193 +/*! EFTA10_I1T_02_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA10_I1T_02_INDEX_DOP_LKP0_LTPR_WIN 1194 +/*! EFTA10_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA10_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1195 +/*! EFTA10_I1T_03_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA10_I1T_03_INDEX_DOP_LKP0_LTPR_WIN 1196 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR 1197 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_RD 1198 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR 1199 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_RD 1200 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM10_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM10_PKT_ADDR 1201 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM10_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM10_PKT_RD 1202 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM11_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM11_PKT_ADDR 1203 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM11_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM11_PKT_RD 1204 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR 1205 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM2_PKT_RD 1206 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR 1207 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM3_PKT_RD 1208 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR 1209 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM4_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM4_PKT_RD 1210 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR 1211 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM5_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM5_PKT_RD 1212 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR 1213 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM6_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM6_PKT_RD 1214 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR 1215 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM7_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM7_PKT_RD 1216 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM8_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM8_PKT_ADDR 1217 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM8_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM8_PKT_RD 1218 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM9_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM9_PKT_ADDR 1219 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM9_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM9_PKT_RD 1220 +/*! EFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1221 +/*! EFTA20_I1T_00_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_00_INDEX_DOP_LKP0_LTPR_WIN 1222 +/*! EFTA20_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1223 +/*! EFTA20_I1T_01_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_01_INDEX_DOP_LKP0_LTPR_WIN 1224 +/*! EFTA20_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1225 +/*! EFTA20_I1T_02_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_02_INDEX_DOP_LKP0_LTPR_WIN 1226 +/*! EFTA20_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1227 +/*! EFTA20_I1T_03_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_03_INDEX_DOP_LKP0_LTPR_WIN 1228 +/*! EFTA20_I1T_04_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_04_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1229 +/*! EFTA20_I1T_04_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_04_INDEX_DOP_LKP0_LTPR_WIN 1230 +/*! EFTA20_I1T_05_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_05_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1231 +/*! EFTA20_I1T_05_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_05_INDEX_DOP_LKP0_LTPR_WIN 1232 +/*! EFTA20_I1T_06_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_06_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1233 +/*! EFTA20_I1T_06_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_06_INDEX_DOP_LKP0_LTPR_WIN 1234 +/*! EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 1235 +/*! EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 1236 +/*! EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 1237 +/*! EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 1238 +/*! EFTA30_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 1239 +/*! EFTA30_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 1240 +/*! EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 1241 +/*! EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 1242 +/*! EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 1243 +/*! EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 1244 +/*! EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 1245 +/*! EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 1246 +/*! EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1247 +/*! EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 1248 +/*! EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 1249 +/*! EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 1250 +/*! EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1251 +/*! EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 1252 +/*! EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 1253 +/*! EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 1254 +/*! EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 1255 +/*! EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1256 +/*! EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 1257 +/*! EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 1258 +/*! EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 1259 +/*! EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1260 +/*! EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 1261 +/*! EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 1262 +/*! EFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 1263 +/*! EFTA30_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 1264 +/*! EFTA30_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY 1265 +/*! EFTA30_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY 1266 +/*! EFTA30_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY 1267 +/*! EFTA30_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY 1268 +/*! EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX 1269 +/*! EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH 1270 +/*! EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX 1271 +/*! EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH 1272 +/*! EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX 1273 +/*! EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH 1274 +/*! EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX 1275 +/*! EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH 1276 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA 1277 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1278 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 1279 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 1280 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH 1281 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1282 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 1283 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 1284 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH 1285 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1286 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE 1287 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH 1288 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH 1289 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1290 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE 1291 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH 1292 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH 1293 +/*! EFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 1294 +/*! EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_EGR_TS_PROFILE_INDEX. */ +#define BCMPKT_TRACE_DOP_EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_EGR_TS_PROFILE_INDEX 1295 +/*! EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_EGR_INGRESS_TIMESTAMP_BUS. */ +#define BCMPKT_TRACE_DOP_EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_EGR_INGRESS_TIMESTAMP_BUS 1296 +/*! EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_TIMESTAMP_COUNT. */ +#define BCMPKT_TRACE_DOP_EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_TIMESTAMP_COUNT 1297 +/*! EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_INGRESS_TIMESTAMP. */ +#define BCMPKT_TRACE_DOP_EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_INGRESS_TIMESTAMP 1298 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBER_INDEX. */ +#define BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBER_INDEX 1299 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_PKT_ADDR 1300 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_UNTAG_BITMAP_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_UNTAG_BITMAP_PKT_ADDR 1301 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_STATE_PROFILE_LOWER_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_STATE_PROFILE_LOWER_PKT_ADDR 1302 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBERSHIP_PROFILE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBERSHIP_PROFILE_PKT_ADDR 1303 +/*! FLEX_CTR_ST_EGR_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0 1304 +/*! FLEX_CTR_ST_EGR_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1 1305 +/*! FLEX_CTR_ST_EGR_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID 1306 +/*! FLEX_CTR_ST_EGR_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID 1307 +/*! FLEX_CTR_ST_EGR_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID 1308 +/*! FLEX_CTR_ST_EGR_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID 1309 +/*! FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B0 1310 +/*! FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B1 1311 +/*! FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B2 1312 +/*! FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B3 1313 +/*! FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0 1314 +/*! FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1 1315 +/*! FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2 1316 +/*! FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3 1317 +/*! FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A0 1318 +/*! FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A1 1319 +/*! FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A2 1320 +/*! FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A3 1321 +/*! FLEX_CTR_ST_EGR0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0 1322 +/*! FLEX_CTR_ST_EGR0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1 1323 +/*! FLEX_CTR_ST_EGR0_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID 1324 +/*! FLEX_CTR_ST_EGR0_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID 1325 +/*! FLEX_CTR_ST_EGR0_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID 1326 +/*! FLEX_CTR_ST_EGR0_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID 1327 +/*! FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B0 1328 +/*! FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B1 1329 +/*! FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B2 1330 +/*! FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B3 1331 +/*! FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0 1332 +/*! FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1 1333 +/*! FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2 1334 +/*! FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3 1335 +/*! FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A0 1336 +/*! FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A1 1337 +/*! FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A2 1338 +/*! FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A3 1339 +/*! FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0 1340 +/*! FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1 1341 +/*! FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2 1342 +/*! FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3 1343 +/*! FLEX_CTR_ST_EGR1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0 1344 +/*! FLEX_CTR_ST_EGR1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1 1345 +/*! FLEX_CTR_ST_EGR1_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID 1346 +/*! FLEX_CTR_ST_EGR1_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID 1347 +/*! FLEX_CTR_ST_EGR1_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID 1348 +/*! FLEX_CTR_ST_EGR1_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID 1349 +/*! FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B0 1350 +/*! FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B1 1351 +/*! FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B2 1352 +/*! FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B3 1353 +/*! FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0 1354 +/*! FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1 1355 +/*! FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2 1356 +/*! FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3 1357 +/*! FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A0 1358 +/*! FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A1 1359 +/*! FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A2 1360 +/*! FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A3 1361 +/*! FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0 1362 +/*! FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1 1363 +/*! FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2 1364 +/*! FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3 1365 +/*! MEMDB_TCAM_EFTA30_MEM0_1_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_1_KEY_DOP_MEM0_1_KEY 1366 +/*! MEMDB_TCAM_EFTA30_MEM0_1_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_1_KEY_DOP_MEM0_1_PKT_RD 1367 +/*! MEMDB_TCAM_EFTA30_MEM0_3_KEY_DOP_MEM0_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_3_KEY_DOP_MEM0_3_KEY 1368 +/*! MEMDB_TCAM_EFTA30_MEM0_3_KEY_DOP_MEM0_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_3_KEY_DOP_MEM0_3_PKT_RD 1369 +/*! MEMDB_TCAM_EFTA30_MEM0_2_KEY_DOP_MEM0_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_2_KEY_DOP_MEM0_2_KEY 1370 +/*! MEMDB_TCAM_EFTA30_MEM0_2_KEY_DOP_MEM0_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_2_KEY_DOP_MEM0_2_PKT_RD 1371 +/*! MEMDB_TCAM_EFTA30_MEM0_0_KEY_DOP_MEM0_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_0_KEY_DOP_MEM0_0_KEY 1372 +/*! MEMDB_TCAM_EFTA30_MEM0_0_KEY_DOP_MEM0_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_0_KEY_DOP_MEM0_0_PKT_RD 1373 +/*! MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX 1374 +/*! MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH 1375 +/*! MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX 1376 +/*! MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH 1377 +/*! MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX 1378 +/*! MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH 1379 +/*! MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX 1380 +/*! MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH 1381 +/*! EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 1382 +/*! EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 1383 +/*! EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 1384 +/*! EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 1385 +/*! EGR_MIRROR_MIRROR2EDIT_CTRL_BUS_DOP_OUT_EGR_SCR_MIRROR2EDIT_CTRL_BUS. */ +#define BCMPKT_TRACE_DOP_EGR_MIRROR_MIRROR2EDIT_CTRL_BUS_DOP_OUT_EGR_SCR_MIRROR2EDIT_CTRL_BUS 1386 +/*! QOS_REMARKING_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_KEY. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_KEY 1387 +/*! QOS_REMARKING_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 1388 +/*! QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_ONLY_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_ONLY_MATCH_INDEX 1389 +/*! QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_ONLY_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_ONLY_TCAM_MATCH 1390 +/*! QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_POLICY_DATA. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_POLICY_DATA 1391 +/*! QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX 1392 +/*! QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_ONLY_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_ONLY_TCAM_MATCH 1393 +/*! QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA 1394 +/*! QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX 1395 +/*! QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH 1396 +/*! QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_4_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_4_PKT_ADDR 1397 +/*! QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_3_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_3_PKT_ADDR 1398 +/*! QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_2_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_2_PKT_ADDR 1399 +/*! QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_1_PKT_ADDR 1400 +/*! QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_0_PKT_ADDR 1401 +/*! QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_MPLS_QOS_MAP_TABLE_1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_MPLS_QOS_MAP_TABLE_1_PKT_ADDR 1402 +/*! QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_MPLS_QOS_MAP_TABLE_0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_MPLS_QOS_MAP_TABLE_0_PKT_ADDR 1403 +/*! QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_4_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_4_PKT_ADDR 1404 +/*! QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_3_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_3_PKT_ADDR 1405 +/*! QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_2_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_2_PKT_ADDR 1406 +/*! QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_1_PKT_ADDR 1407 +/*! QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_0_PKT_ADDR 1408 +/*! EDIT_CTRL_ZONE_4_TCAM_KEY_DOP_TCAM_4_A_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_KEY_DOP_TCAM_4_A_KEY 1409 +/*! EDIT_CTRL_ZONE_3_TCAM_KEY_DOP_TCAM_3_A_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_KEY_DOP_TCAM_3_A_KEY 1410 +/*! EDIT_CTRL_ZONE_1_TCAM_KEY_DOP_TCAM_1_A_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_KEY_DOP_TCAM_1_A_KEY 1411 +/*! EDIT_CTRL_ZONE_2_TCAM_KEY_DOP_TCAM_2_A_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_KEY_DOP_TCAM_2_A_KEY 1412 +/*! EDIT_CTRL_ZONE_0_TCAM_KEY_DOP_TCAM_0_A_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_KEY_DOP_TCAM_0_A_KEY 1413 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_TCAM_4_A_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_TCAM_4_A_KEY 1414 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_TCAM_4_A_UPPER_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_TCAM_4_A_UPPER_KEY 1415 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP_TCAM_3_A_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP_TCAM_3_A_KEY 1416 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_TCAM_2_A_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_TCAM_2_A_KEY 1417 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_TCAM_2_A_UPPER_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_TCAM_2_A_UPPER_KEY 1418 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP_TCAM_1_A_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP_TCAM_1_A_KEY 1419 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP_TCAM_0_A_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP_TCAM_0_A_KEY 1420 +/*! EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_C_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_C_TCAM_MATCH 1421 +/*! EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_C_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_C_MATCH_INDEX 1422 +/*! EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_B_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_B_TCAM_MATCH 1423 +/*! EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_B_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_B_MATCH_INDEX 1424 +/*! EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_A_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_A_TCAM_MATCH 1425 +/*! EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_A_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_A_MATCH_INDEX 1426 +/*! EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_C_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_C_TCAM_MATCH 1427 +/*! EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_C_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_C_MATCH_INDEX 1428 +/*! EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_B_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_B_TCAM_MATCH 1429 +/*! EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_B_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_B_MATCH_INDEX 1430 +/*! EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_A_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_A_TCAM_MATCH 1431 +/*! EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_A_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_A_MATCH_INDEX 1432 +/*! EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_C_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_C_TCAM_MATCH 1433 +/*! EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_C_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_C_MATCH_INDEX 1434 +/*! EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_B_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_B_TCAM_MATCH 1435 +/*! EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_B_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_B_MATCH_INDEX 1436 +/*! EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_A_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_A_TCAM_MATCH 1437 +/*! EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_A_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_A_MATCH_INDEX 1438 +/*! EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_C_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_C_TCAM_MATCH 1439 +/*! EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_C_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_C_MATCH_INDEX 1440 +/*! EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_B_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_B_TCAM_MATCH 1441 +/*! EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_B_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_B_MATCH_INDEX 1442 +/*! EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_A_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_A_TCAM_MATCH 1443 +/*! EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_A_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_A_MATCH_INDEX 1444 +/*! EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_C_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_C_TCAM_MATCH 1445 +/*! EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_C_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_C_MATCH_INDEX 1446 +/*! EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_B_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_B_TCAM_MATCH 1447 +/*! EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_B_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_B_MATCH_INDEX 1448 +/*! EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_A_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_A_TCAM_MATCH 1449 +/*! EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_A_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_A_MATCH_INDEX 1450 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_C_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_C_TCAM_MATCH 1451 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_C_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_C_MATCH_INDEX 1452 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_B_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_B_TCAM_MATCH 1453 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_B_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_B_MATCH_INDEX 1454 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_A_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_A_TCAM_MATCH 1455 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_A_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_A_MATCH_INDEX 1456 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_C_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_C_TCAM_MATCH 1457 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_C_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_C_MATCH_INDEX 1458 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_B_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_B_TCAM_MATCH 1459 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_B_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_B_MATCH_INDEX 1460 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_A_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_A_TCAM_MATCH 1461 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_A_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_A_MATCH_INDEX 1462 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_C_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_C_TCAM_MATCH 1463 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_C_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_C_MATCH_INDEX 1464 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_B_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_B_TCAM_MATCH 1465 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_B_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_B_MATCH_INDEX 1466 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_A_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_A_TCAM_MATCH 1467 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_A_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_A_MATCH_INDEX 1468 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_C_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_C_TCAM_MATCH 1469 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_C_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_C_MATCH_INDEX 1470 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_B_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_B_TCAM_MATCH 1471 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_B_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_B_MATCH_INDEX 1472 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_A_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_A_TCAM_MATCH 1473 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_A_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_A_MATCH_INDEX 1474 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_C_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_C_TCAM_MATCH 1475 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_C_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_C_MATCH_INDEX 1476 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_B_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_B_TCAM_MATCH 1477 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_B_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_B_MATCH_INDEX 1478 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_A_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_A_TCAM_MATCH 1479 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_A_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_A_MATCH_INDEX 1480 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_2_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_2_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1481 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_2_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_2_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1482 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_RW_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1483 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1484 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1485 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1486 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_3_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_3_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1487 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_RW_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1488 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1489 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1490 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1491 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_2_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_2_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1492 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1493 +/*! EGR_SEQUENCE_MIRROR_SEQUENCE_NUMBER_PROFILE_INDEX_DOP_MIRROR_SEQUENCE_NUMBER_PROFILE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_SEQUENCE_MIRROR_SEQUENCE_NUMBER_PROFILE_INDEX_DOP_MIRROR_SEQUENCE_NUMBER_PROFILE_PKT_ADDR 1494 +/*! EGR_SEQUENCE_SEQUENCE_NUMBER_TABLE_INDEX_DOP_NUMBER_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_SEQUENCE_SEQUENCE_NUMBER_TABLE_INDEX_DOP_NUMBER_TABLE_PKT_ADDR 1495 +/*! EGR_SEQUENCE_SEQUENCE_PROFILE_INDEX_DOP_PROFILE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_SEQUENCE_SEQUENCE_PROFILE_INDEX_DOP_PROFILE_PKT_ADDR 1496 +/*! EGR_SEQUENCE_NEW_SEQUENCE_NUM_DOP_NEW_SEQUENCE_NUM. */ +#define BCMPKT_TRACE_DOP_EGR_SEQUENCE_NEW_SEQUENCE_NUM_DOP_NEW_SEQUENCE_NUM 1497 +/*! EGR_SEQUENCE_PKT_SEQUENCE_NUM_DOP_PKT_SEQUENCE_NUM. */ +#define BCMPKT_TRACE_DOP_EGR_SEQUENCE_PKT_SEQUENCE_NUM_DOP_PKT_SEQUENCE_NUM 1498 +/*! FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_4. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_4 1499 +/*! FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_3. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_3 1500 +/*! FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_2. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_2 1501 +/*! FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_1. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_1 1502 +/*! FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_0. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_0 1503 +/*! FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_3. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_3 1504 +/*! FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_2. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_2 1505 +/*! FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_1. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_1 1506 +/*! FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_0. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_0 1507 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_4. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_4 1508 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_3. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_3 1509 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_2. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_2 1510 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_1. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_1 1511 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_0. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_0 1512 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_4. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_4 1513 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_3. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_3 1514 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_2. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_2 1515 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_1. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_1 1516 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_0. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_0 1517 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_4. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_4 1518 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_3. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_3 1519 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_2. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_2 1520 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_1. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_1 1521 +/*! FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_0. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_0 1522 +/*! FLEX_CTR_EGR_COUNTER_ACTION_VECTOR_DOP_EGR_FLEX_CTR_BUS. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_ACTION_VECTOR_DOP_EGR_FLEX_CTR_BUS 1523 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_2_DOP_COUNTER_EOP_BUFFER_2_PKT_WDATA_COUNTER_EOP_BUFFER_2_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_2_DOP_COUNTER_EOP_BUFFER_2_PKT_WDATA_COUNTER_EOP_BUFFER_2_PKT_WR 1524 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_7_DOP_COUNTER_EOP_BUFFER_7_PKT_WDATA_COUNTER_EOP_BUFFER_7_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_7_DOP_COUNTER_EOP_BUFFER_7_PKT_WDATA_COUNTER_EOP_BUFFER_7_PKT_WR 1525 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_5_DOP_COUNTER_EOP_BUFFER_5_PKT_WDATA_COUNTER_EOP_BUFFER_5_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_5_DOP_COUNTER_EOP_BUFFER_5_PKT_WDATA_COUNTER_EOP_BUFFER_5_PKT_WR 1526 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_6_DOP_COUNTER_EOP_BUFFER_6_PKT_WDATA_COUNTER_EOP_BUFFER_6_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_6_DOP_COUNTER_EOP_BUFFER_6_PKT_WDATA_COUNTER_EOP_BUFFER_6_PKT_WR 1527 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_0_DOP_COUNTER_EOP_BUFFER_0_PKT_WDATA_COUNTER_EOP_BUFFER_0_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_0_DOP_COUNTER_EOP_BUFFER_0_PKT_WDATA_COUNTER_EOP_BUFFER_0_PKT_WR 1528 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_1_DOP_COUNTER_EOP_BUFFER_1_PKT_WDATA_COUNTER_EOP_BUFFER_1_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_1_DOP_COUNTER_EOP_BUFFER_1_PKT_WDATA_COUNTER_EOP_BUFFER_1_PKT_WR 1529 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_4_DOP_COUNTER_EOP_BUFFER_4_PKT_WDATA_COUNTER_EOP_BUFFER_4_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_4_DOP_COUNTER_EOP_BUFFER_4_PKT_WDATA_COUNTER_EOP_BUFFER_4_PKT_WR 1530 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_3_DOP_COUNTER_EOP_BUFFER_3_PKT_WDATA_COUNTER_EOP_BUFFER_3_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_3_DOP_COUNTER_EOP_BUFFER_3_PKT_WDATA_COUNTER_EOP_BUFFER_3_PKT_WR 1531 +/*! APU_EGR0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY. */ +#define BCMPKT_TRACE_DOP_APU_EGR0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY 1532 +/*! APU_EGR1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY. */ +#define BCMPKT_TRACE_DOP_APU_EGR1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY 1533 +/*! APU_ING0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY. */ +#define BCMPKT_TRACE_DOP_APU_ING0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY 1534 +/*! APU_ING1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY. */ +#define BCMPKT_TRACE_DOP_APU_ING1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY 1535 +/*! ECMP_LEVEL0_GROUP_TABLE_DATA_DOP_GROUP_TABLE_DATA. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_TABLE_DATA_DOP_GROUP_TABLE_DATA 1536 +/*! ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX 1537 +/*! ECMP_LEVEL0_MEMBER_INDEX_DOP_HASH. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_HASH 1538 +/*! ECMP_LEVEL0_MEMBER_INDEX_DOP_MODULO_OFFSET. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_MODULO_OFFSET 1539 +/*! ECMP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX 1540 +/*! ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_DLB_NHI. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_DLB_NHI 1541 +/*! ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_ALT_NHI. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_ALT_NHI 1542 +/*! ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_ALT_HASH. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_ALT_HASH 1543 +/*! ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_ALT_MODULO_OFFSET. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_ALT_MODULO_OFFSET 1544 +/*! ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX 1545 +/*! ECMP_LEVEL1_MEMBER_INDEX_DOP_PRIM_HASH. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_PRIM_HASH 1546 +/*! ECMP_LEVEL1_MEMBER_INDEX_DOP_MODULO_OFFSET. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_MODULO_OFFSET 1547 +/*! ECMP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX 1548 +/*! EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY 1549 +/*! EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD 1550 +/*! EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX 1551 +/*! EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH 1552 +/*! EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY 1553 +/*! EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD 1554 +/*! EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX 1555 +/*! EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH 1556 +/*! EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY 1557 +/*! EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD 1558 +/*! EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX 1559 +/*! EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH 1560 +/*! EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY 1561 +/*! EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD 1562 +/*! EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX 1563 +/*! EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH 1564 +/*! EFTA40_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA40_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1565 +/*! EFTA40_I1T_00_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA40_I1T_00_INDEX_DOP_LKP0_LTPR_WIN 1566 +/*! EFTA40_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA40_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1567 +/*! EFTA40_I1T_01_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA40_I1T_01_INDEX_DOP_LKP0_LTPR_WIN 1568 +/*! EFTA40_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA40_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1569 +/*! EFTA40_I1T_02_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA40_I1T_02_INDEX_DOP_LKP0_LTPR_WIN 1570 +/*! EFTA40_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA40_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1571 +/*! EFTA40_I1T_03_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA40_I1T_03_INDEX_DOP_LKP0_LTPR_WIN 1572 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_1_LOWER_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_1_LOWER_PKT_ADDR 1573 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_UNTAG_BITMAP_LOWER_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_UNTAG_BITMAP_LOWER_PKT_ADDR 1574 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_STATE_PROFILE_LOWER_0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_STATE_PROFILE_LOWER_0_PKT_ADDR 1575 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBERSHIP_PROFILE_LOWER_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBERSHIP_PROFILE_LOWER_PKT_ADDR 1576 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR 1577 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR 1578 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR 1579 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR 1580 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR 1581 +/*! FLEX_EDITOR_ARC_ID_DOP_ARID_4. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_ARID_4 1582 +/*! FLEX_EDITOR_ARC_ID_DOP_ARID_3. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_ARID_3 1583 +/*! FLEX_EDITOR_ARC_ID_DOP_ARID_2. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_ARID_2 1584 +/*! FLEX_EDITOR_ARC_ID_DOP_ARID_1. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_ARID_1 1585 +/*! FLEX_EDITOR_ARC_ID_DOP_ARID_0. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_ARID_0 1586 +/*! HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_7_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_7_PKT_ADDR 1587 +/*! HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_6_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_6_PKT_ADDR 1588 +/*! HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_5_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_5_PKT_ADDR 1589 +/*! HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_4_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_4_PKT_ADDR 1590 +/*! HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_3_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_3_PKT_ADDR 1591 +/*! HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_2_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_2_PKT_ADDR 1592 +/*! HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_1_PKT_ADDR 1593 +/*! HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_0_PKT_ADDR 1594 +/*! HDR_STACK_EGR_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_EGR_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX 1595 +/*! HDR_STACK_EGR_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_EGR_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH 1596 +/*! HDR_STACK_EGR_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_EGR_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 1597 +/*! HDR_STACK_ING_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_ING_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX 1598 +/*! HDR_STACK_ING_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_ING_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH 1599 +/*! HDR_STACK_ING_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_ING_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 1600 +/*! IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1601 +/*! IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 1602 +/*! IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 1603 +/*! IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1604 +/*! IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 1605 +/*! IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 1606 +/*! IFTA5_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 1607 +/*! IPARSER1_HME_STAGE6_DOP_STAGE6_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE6_DOP_STAGE6_HFE_PROFILE_PTR 1608 +/*! IPARSER1_HME_STAGE6_DOP_STAGE6_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE6_DOP_STAGE6_TCAM_TCAM_MATCH 1609 +/*! IPARSER1_HME_STAGE6_DOP_STAGE6_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE6_DOP_STAGE6_SHIFT_AMOUNT 1610 +/*! IPARSER1_HME_STAGE6_DOP_STAGE6_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE6_DOP_STAGE6_PKT_DATA 1611 +/*! IPARSER1_HME_STAGE7_DOP_STAGE7_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE7_DOP_STAGE7_HFE_PROFILE_PTR 1612 +/*! IPARSER1_HME_STAGE7_DOP_STAGE7_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE7_DOP_STAGE7_TCAM_TCAM_MATCH 1613 +/*! IPARSER1_HME_STAGE7_DOP_STAGE7_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE7_DOP_STAGE7_SHIFT_AMOUNT 1614 +/*! IPARSER1_HME_STAGE7_DOP_STAGE7_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE7_DOP_STAGE7_PKT_DATA 1615 +/*! IPARSER2_HME_STAGE5_DOP_STAGE5_HFE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE5_DOP_STAGE5_HFE_PROFILE_PTR 1616 +/*! IPARSER2_HME_STAGE5_DOP_STAGE5_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE5_DOP_STAGE5_TCAM_TCAM_MATCH 1617 +/*! IPARSER2_HME_STAGE5_DOP_STAGE5_SHIFT_AMOUNT. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE5_DOP_STAGE5_SHIFT_AMOUNT 1618 +/*! IPARSER2_HME_STAGE5_DOP_STAGE5_PKT_DATA. */ +#define BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE5_DOP_STAGE5_PKT_DATA 1619 +/*! MEMDB_TCAM_IFTA5_MEM0_0_KEY_DOP_MEM0_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_0_KEY_DOP_MEM0_0_KEY 1620 +/*! MEMDB_TCAM_IFTA5_MEM0_0_KEY_DOP_MEM0_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_0_KEY_DOP_MEM0_0_PKT_RD 1621 +/*! MEMDB_TCAM_IFTA5_MEM0_1_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_1_KEY_DOP_MEM0_1_KEY 1622 +/*! MEMDB_TCAM_IFTA5_MEM0_1_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_1_KEY_DOP_MEM0_1_PKT_RD 1623 +/*! MEMDB_TCAM_IFTA5_MEM1_0_KEY_DOP_MEM1_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_0_KEY_DOP_MEM1_0_KEY 1624 +/*! MEMDB_TCAM_IFTA5_MEM1_0_KEY_DOP_MEM1_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_0_KEY_DOP_MEM1_0_PKT_RD 1625 +/*! MEMDB_TCAM_IFTA5_MEM1_1_KEY_DOP_MEM1_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_1_KEY_DOP_MEM1_1_KEY 1626 +/*! MEMDB_TCAM_IFTA5_MEM1_1_KEY_DOP_MEM1_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_1_KEY_DOP_MEM1_1_PKT_RD 1627 +/*! MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX 1628 +/*! MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH 1629 +/*! MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX 1630 +/*! MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH 1631 +/*! MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX 1632 +/*! MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH 1633 +/*! MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX 1634 +/*! MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH 1635 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_C_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_C_FINAL_TCAM_MATCH 1636 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_B_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_B_FINAL_TCAM_MATCH 1637 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_A_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_A_FINAL_TCAM_MATCH 1638 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_C_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_C_FINAL_TCAM_MATCH 1639 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_B_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_B_FINAL_TCAM_MATCH 1640 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_A_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_A_FINAL_TCAM_MATCH 1641 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_C_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_C_FINAL_TCAM_MATCH 1642 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_B_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_B_FINAL_TCAM_MATCH 1643 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_A_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_A_FINAL_TCAM_MATCH 1644 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_C_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_C_FINAL_TCAM_MATCH 1645 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_B_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_B_FINAL_TCAM_MATCH 1646 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_A_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_A_FINAL_TCAM_MATCH 1647 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_C_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_C_FINAL_TCAM_MATCH 1648 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_B_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_B_FINAL_TCAM_MATCH 1649 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_A_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_A_FINAL_TCAM_MATCH 1650 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_1_PKT_ADDR 1651 +/*! APU_EGR0_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0. */ +#define BCMPKT_TRACE_DOP_APU_EGR0_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0 1652 +/*! APU_EGR0_APU_TCAM_KEY_DOP_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_APU_EGR0_APU_TCAM_KEY_DOP_TCAM_KEY 1653 +/*! APU_EGR0_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY. */ +#define BCMPKT_TRACE_DOP_APU_EGR0_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY 1654 +/*! APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 1655 +/*! APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 1656 +/*! APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 1657 +/*! APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 1658 +/*! APU_EGR1_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0. */ +#define BCMPKT_TRACE_DOP_APU_EGR1_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0 1659 +/*! APU_EGR1_APU_TCAM_KEY_DOP_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_APU_EGR1_APU_TCAM_KEY_DOP_TCAM_KEY 1660 +/*! APU_EGR1_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY. */ +#define BCMPKT_TRACE_DOP_APU_EGR1_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY 1661 +/*! APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 1662 +/*! APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 1663 +/*! APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 1664 +/*! APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 1665 +/*! APU_ING0_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0. */ +#define BCMPKT_TRACE_DOP_APU_ING0_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0 1666 +/*! APU_ING0_APU_TCAM_KEY_DOP_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_APU_ING0_APU_TCAM_KEY_DOP_TCAM_KEY 1667 +/*! APU_ING0_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY. */ +#define BCMPKT_TRACE_DOP_APU_ING0_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY 1668 +/*! APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 1669 +/*! APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 1670 +/*! APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 1671 +/*! APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 1672 +/*! APU_ING1_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0. */ +#define BCMPKT_TRACE_DOP_APU_ING1_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0 1673 +/*! APU_ING1_APU_TCAM_KEY_DOP_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_APU_ING1_APU_TCAM_KEY_DOP_TCAM_KEY 1674 +/*! APU_ING1_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY. */ +#define BCMPKT_TRACE_DOP_APU_ING1_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY 1675 +/*! APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 1676 +/*! APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 1677 +/*! APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 1678 +/*! APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 1679 +/*! ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_CTRL_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_CTRL_PRE_SEL_MUX_OUT 1680 +/*! ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_SINGLE_POINTER_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_SINGLE_POINTER_TABLE_PKT_ADDR 1681 +/*! ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_ADDR 1682 +/*! ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_SHUFFLE_TABLE_INDEX. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_SHUFFLE_TABLE_INDEX 1683 +/*! ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_SINGLE_PTR_TBL_RD. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_SINGLE_PTR_TBL_RD 1684 +/*! ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_RD 1685 +/*! ECMP_LEVEL0_MEMBER_INDEX_DOP_MEMBER_TBL_RD. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_MEMBER_TBL_RD 1686 +/*! ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_OFFSET. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_OFFSET 1687 +/*! ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_INDEX. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_INDEX 1688 +/*! ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MODE. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MODE 1689 +/*! ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_MODULO_OFFSET. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_MODULO_OFFSET 1690 +/*! ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_HASH. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_HASH 1691 +/*! ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_ECMP_MEMBER_TBL_INDEX. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_ECMP_MEMBER_TBL_INDEX 1692 +/*! ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_MEMBER_TBL_RD. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_MEMBER_TBL_RD 1693 +/*! ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_ECMP_MEMBER_TBL_OFFSET. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_ECMP_MEMBER_TBL_OFFSET 1694 +/*! ECMP_LEVEL1_DLB_NHI_DOP_DLB_NHI_VALID. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_DLB_NHI_DOP_DLB_NHI_VALID 1695 +/*! ECMP_LEVEL1_DLB_NHI_DOP_DLB_NHI. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_DLB_NHI_DOP_DLB_NHI 1696 +/*! ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_CTRL_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_CTRL_PRE_SEL_MUX_OUT 1697 +/*! ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_ADDR 1698 +/*! ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_SHUFFLE_TABLE_INDEX. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_SHUFFLE_TABLE_INDEX 1699 +/*! ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_RD 1700 +/*! ECMP_LEVEL1_MEMBER_INDEX_DOP_MEMBER_TBL_RD. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_MEMBER_TBL_RD 1701 +/*! ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_OFFSET. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_OFFSET 1702 +/*! ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_INDEX. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_INDEX 1703 +/*! ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MODE. */ +#define BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MODE 1704 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID 1705 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID 1706 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_0_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_0_FINAL_TCAM_MATCH 1707 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_0_MATCH_INDEX 1708 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_1_MATCH_INDEX 1709 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID 1710 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_2_MATCH_INDEX 1711 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_1_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_1_FINAL_TCAM_MATCH 1712 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_2_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_2_FINAL_TCAM_MATCH 1713 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP_ZONE_0_PHYSICAL_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP_ZONE_0_PHYSICAL_TCAM_0_KEY 1714 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP_ZONE_0_PHYSICAL_TCAM_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP_ZONE_0_PHYSICAL_TCAM_0_PKT_RD 1715 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_0_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_0_FINAL_TCAM_MATCH 1716 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_2_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_2_FINAL_TCAM_MATCH 1717 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_0_MATCH_INDEX 1718 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID 1719 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID 1720 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_1_MATCH_INDEX 1721 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_1_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_1_FINAL_TCAM_MATCH 1722 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_2_MATCH_INDEX 1723 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID 1724 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP_ZONE_1_PHYSICAL_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP_ZONE_1_PHYSICAL_TCAM_0_KEY 1725 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP_ZONE_1_PHYSICAL_TCAM_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP_ZONE_1_PHYSICAL_TCAM_0_PKT_RD 1726 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_1_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_1_FINAL_TCAM_MATCH 1727 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_2_MATCH_INDEX 1728 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_0_MATCH_INDEX 1729 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID 1730 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_2_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_2_FINAL_TCAM_MATCH 1731 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID 1732 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID 1733 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_1_MATCH_INDEX 1734 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_0_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_0_FINAL_TCAM_MATCH 1735 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_ZONE_2_PHYSICAL_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_ZONE_2_PHYSICAL_TCAM_0_KEY 1736 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_ZONE_2_PHYSICAL_TCAM_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_ZONE_2_PHYSICAL_TCAM_0_PKT_RD 1737 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_0_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_0_FINAL_TCAM_MATCH 1738 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID 1739 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID 1740 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_2_MATCH_INDEX 1741 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_0_MATCH_INDEX 1742 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID 1743 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_2_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_2_FINAL_TCAM_MATCH 1744 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_1_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_1_FINAL_TCAM_MATCH 1745 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_1_MATCH_INDEX 1746 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP_ZONE_3_PHYSICAL_TCAM_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP_ZONE_3_PHYSICAL_TCAM_0_PKT_RD 1747 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP_ZONE_3_PHYSICAL_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP_ZONE_3_PHYSICAL_TCAM_0_KEY 1748 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_1_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_1_FINAL_TCAM_MATCH 1749 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_0_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_0_FINAL_TCAM_MATCH 1750 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID 1751 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_2_MATCH_INDEX 1752 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID 1753 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_1_MATCH_INDEX 1754 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID 1755 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_2_FINAL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_2_FINAL_TCAM_MATCH 1756 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_0_MATCH_INDEX 1757 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_ZONE_4_PHYSICAL_TCAM_0_KEY. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_ZONE_4_PHYSICAL_TCAM_0_KEY 1758 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_ZONE_4_PHYSICAL_TCAM_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_ZONE_4_PHYSICAL_TCAM_0_PKT_RD 1759 +/*! EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 1760 +/*! EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 1761 +/*! EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 1762 +/*! EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 1763 +/*! EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 1764 +/*! EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY 1765 +/*! EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH 1766 +/*! EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX 1767 +/*! EFTA10_I1T_04_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_EFTA10_I1T_04_INDEX_DOP_LKP0_LTPR_WIN 1768 +/*! EFTA10_I1T_04_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA10_I1T_04_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1769 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_PROFILE_PTR_3. */ +#define BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_PROFILE_PTR_3 1770 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_PROFILE_PTR_1. */ +#define BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_PROFILE_PTR_1 1771 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBERSHIP_PROFILE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBERSHIP_PROFILE_PKT_RD 1772 +/*! EGR_MIRROR_ENCAP_1_TABLE_INDEX_DOP_ENCAP_1_TABLE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EGR_MIRROR_ENCAP_1_TABLE_INDEX_DOP_ENCAP_1_TABLE_PKT_RD 1773 +/*! EGR_MIRROR_ENCAP_1_TABLE_INDEX_DOP_ENCAP_1_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_MIRROR_ENCAP_1_TABLE_INDEX_DOP_ENCAP_1_TABLE_PKT_ADDR 1774 +/*! EGR_MIRROR_ENCAP_TABLE_INDEX_DOP_ENCAP_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_MIRROR_ENCAP_TABLE_INDEX_DOP_ENCAP_TABLE_PKT_ADDR 1775 +/*! EGR_MIRROR_ENCAP_TABLE_INDEX_DOP_ENCAP_TABLE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EGR_MIRROR_ENCAP_TABLE_INDEX_DOP_ENCAP_TABLE_PKT_RD 1776 +/*! EGR_MIRROR_MIRROR2EDITOR2_BUS_DOP_OUT_EGR_SCR_MIRROR2EDITOR2_BUS. */ +#define BCMPKT_TRACE_DOP_EGR_MIRROR_MIRROR2EDITOR2_BUS_DOP_OUT_EGR_SCR_MIRROR2EDITOR2_BUS 1777 +/*! EGR_MIRROR_MIRROR2EDITOR_BUS_DOP_OUT_EGR_SCR_MIRROR2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EGR_MIRROR_MIRROR2EDITOR_BUS_DOP_OUT_EGR_SCR_MIRROR2EDITOR_BUS 1778 +/*! EGR_MIRROR_SESSION_CONTROL_TABLE_INDEX_DOP_SESSION_CONTROL_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_MIRROR_SESSION_CONTROL_TABLE_INDEX_DOP_SESSION_CONTROL_TABLE_PKT_ADDR 1779 +/*! EGR_MIRROR_SESSION_CONTROL_TABLE_INDEX_DOP_SESSION_CONTROL_TABLE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EGR_MIRROR_SESSION_CONTROL_TABLE_INDEX_DOP_SESSION_CONTROL_TABLE_PKT_RD 1780 +/*! EGR_SEQUENCE_MIRROR_SEQUENCE_NUMBER_PROFILE_INDEX_DOP_MIRROR_SEQUENCE_NUMBER_PROFILE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EGR_SEQUENCE_MIRROR_SEQUENCE_NUMBER_PROFILE_INDEX_DOP_MIRROR_SEQUENCE_NUMBER_PROFILE_PKT_RD 1781 +/*! EGR_SEQUENCE_NUMBER_TABLE_INDEX_DOP_NUMBER_TABLE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_SEQUENCE_NUMBER_TABLE_INDEX_DOP_NUMBER_TABLE_PKT_ADDR 1782 +/*! EGR_SEQUENCE_NUMBER_TABLE_INDEX_DOP_NUMBER_TABLE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EGR_SEQUENCE_NUMBER_TABLE_INDEX_DOP_NUMBER_TABLE_PKT_RD 1783 +/*! EGR_SEQUENCE_PROFILE_INDEX_DOP_PROFILE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_SEQUENCE_PROFILE_INDEX_DOP_PROFILE_PKT_ADDR 1784 +/*! EGR_SEQUENCE_PROFILE_INDEX_DOP_PROFILE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EGR_SEQUENCE_PROFILE_INDEX_DOP_PROFILE_PKT_RD 1785 +/*! EPOST_EPOST_DROP_TRACE_DOP_EGR_TRACE_BUS. */ +#define BCMPKT_TRACE_DOP_EPOST_EPOST_DROP_TRACE_DOP_EGR_TRACE_BUS 1786 +/*! EPOST_EPOST_DROP_TRACE_DOP_EGR_DROP_BUS. */ +#define BCMPKT_TRACE_DOP_EPOST_EPOST_DROP_TRACE_DOP_EGR_DROP_BUS 1787 +/*! EPRE_EDEV_CONFIG_CPU_DMA_FLEX_WORD_MUX_PROFILE_INDEX_DOP_CPU_DMA_FLEX_WORD_MUX_PROFILE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_CPU_DMA_FLEX_WORD_MUX_PROFILE_INDEX_DOP_CPU_DMA_FLEX_WORD_MUX_PROFILE_PKT_ADDR 1788 +/*! EPRE_EDEV_CONFIG_CPU_DMA_FLEX_WORD_MUX_PROFILE_INDEX_DOP_CPU_DMA_FLEX_WORD_MUX_PROFILE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_CPU_DMA_FLEX_WORD_MUX_PROFILE_INDEX_DOP_CPU_DMA_FLEX_WORD_MUX_PROFILE_PKT_RD 1789 +/*! EPRE_EDEV_CONFIG_EGR_TABLE_INDEX_UPDATE_PROFILE_INDEX_DOP_EGR_TABLE_INDEX_UPDATE_PROFILE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_EGR_TABLE_INDEX_UPDATE_PROFILE_INDEX_DOP_EGR_TABLE_INDEX_UPDATE_PROFILE_PKT_RD 1790 +/*! EPRE_EDEV_CONFIG_MIRROR_ATTRIBUTES_TABLE_INDEX_DOP_MIRROR_ATTRIBUTES_TABLE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_MIRROR_ATTRIBUTES_TABLE_INDEX_DOP_MIRROR_ATTRIBUTES_TABLE_PKT_RD 1791 +/*! EPRE_PARSER_ZONE_REMAP_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP_FIELD_EXTRACTION_PROFILE_CONTROL_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP_FIELD_EXTRACTION_PROFILE_CONTROL_PKT_RD 1792 +/*! EPRE_PARSER_ZONE_REMAP_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP_FIELD_EXTRACTION_PROFILE_CONTROL_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP_FIELD_EXTRACTION_PROFILE_CONTROL_PKT_ADDR 1793 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD 1794 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD 1795 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD 1796 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD 1797 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD 1798 +/*! FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_KEY 1799 +/*! FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_MATCH_INDEX 1800 +/*! FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_PKT_RD 1801 +/*! FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_TCAM_MATCH 1802 +/*! FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_KEY 1803 +/*! FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_MATCH_INDEX 1804 +/*! FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_PKT_RD 1805 +/*! FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_TCAM_MATCH 1806 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_8_DOP_COUNTER_EOP_BUFFER_8_PKT_WDATA_COUNTER_EOP_BUFFER_8_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_8_DOP_COUNTER_EOP_BUFFER_8_PKT_WDATA_COUNTER_EOP_BUFFER_8_PKT_WR 1807 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_9_DOP_COUNTER_EOP_BUFFER_9_PKT_WDATA_COUNTER_EOP_BUFFER_9_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_9_DOP_COUNTER_EOP_BUFFER_9_PKT_WDATA_COUNTER_EOP_BUFFER_9_PKT_WR 1808 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_12_DOP_COUNTER_EOP_BUFFER_12_PKT_WDATA_COUNTER_EOP_BUFFER_12_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_12_DOP_COUNTER_EOP_BUFFER_12_PKT_WDATA_COUNTER_EOP_BUFFER_12_PKT_WR 1809 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_13_DOP_COUNTER_EOP_BUFFER_13_PKT_WDATA_COUNTER_EOP_BUFFER_13_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_13_DOP_COUNTER_EOP_BUFFER_13_PKT_WDATA_COUNTER_EOP_BUFFER_13_PKT_WR 1810 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_14_DOP_COUNTER_EOP_BUFFER_14_PKT_WDATA_COUNTER_EOP_BUFFER_14_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_14_DOP_COUNTER_EOP_BUFFER_14_PKT_WDATA_COUNTER_EOP_BUFFER_14_PKT_WR 1811 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_15_DOP_COUNTER_EOP_BUFFER_15_PKT_WDATA_COUNTER_EOP_BUFFER_15_PKT_WR. */ +#define BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_15_DOP_COUNTER_EOP_BUFFER_15_PKT_WDATA_COUNTER_EOP_BUFFER_15_PKT_WR 1812 +/*! FLEX_EDITOR_ARC_ID_DOP_MIRROR_0_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_MIRROR_0_PROFILE_PTR 1813 +/*! FLEX_EDITOR_ARC_ID_DOP_TRUNCATE_PROFILE_PTR. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_TRUNCATE_PROFILE_PTR 1814 +/*! FLEX_EDITOR_ARC_ID_DOP_SOP. */ +#define BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_SOP 1815 +/*! IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1816 +/*! IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH 1817 +/*! IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1818 +/*! IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE 1819 +/*! IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE 1820 +/*! IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE 1821 +/*! IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH 1822 +/*! IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH 1823 +/*! IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1824 +/*! IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE. */ +#define BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE 1825 +/*! IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID. */ +#define BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID 1826 +/*! IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH 1827 +/*! IFTA105_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT 1828 +/*! IFTA130_I1T_04_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA130_I1T_04_INDEX_DOP_LKP0_LTPR_WIN 1829 +/*! IFTA130_I1T_04_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA130_I1T_04_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1830 +/*! IFTA70_I1T_02_INDEX_DOP_LKP0_LTPR_WIN. */ +#define BCMPKT_TRACE_DOP_IFTA70_I1T_02_INDEX_DOP_LKP0_LTPR_WIN 1831 +/*! IFTA70_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA70_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT 1832 +/*! IPOST_CPU_COS_CPU_COS_MAP_TCAM_KEY_DOP_CPU_COS_MAP_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_CPU_COS_CPU_COS_MAP_TCAM_KEY_DOP_CPU_COS_MAP_TCAM_PKT_RD 1833 +/*! IPOST_LAG_L2OIF_INDEX_DOP_L2OIF_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_LAG_L2OIF_INDEX_DOP_L2OIF_PKT_RD 1834 +/*! IPOST_LAG_L2OIF_INDEX_DOP_L2OIF_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_LAG_L2OIF_INDEX_DOP_L2OIF_PKT_ADDR 1835 +/*! IPOST_LAG_LAG_GROUP_INDEX_DOP_LAG_GROUP_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_LAG_LAG_GROUP_INDEX_DOP_LAG_GROUP_PKT_RD 1836 +/*! IPOST_LAG_LAG_GROUP_INDEX_DOP_LAG_GROUP_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_LAG_LAG_GROUP_INDEX_DOP_LAG_GROUP_PKT_ADDR 1837 +/*! IPOST_LAG_LAG_MEMBER_INDEX_DOP_LAG_MEMBER_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_LAG_LAG_MEMBER_INDEX_DOP_LAG_MEMBER_PKT_ADDR 1838 +/*! IPOST_LAG_LAG_MEMBER_INDEX_DOP_LAG_MEMBER_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_LAG_LAG_MEMBER_INDEX_DOP_LAG_MEMBER_PKT_RD 1839 +/*! IPOST_LAG_NONUCAST_LAG_BLOCK_MASK_INDEX_DOP_NONUCAST_LAG_BLOCK_MASK_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_LAG_NONUCAST_LAG_BLOCK_MASK_INDEX_DOP_NONUCAST_LAG_BLOCK_MASK_PKT_RD 1840 +/*! IPOST_LAG_NONUCAST_LAG_BLOCK_MASK_INDEX_DOP_NONUCAST_LAG_BLOCK_MASK_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_LAG_NONUCAST_LAG_BLOCK_MASK_INDEX_DOP_NONUCAST_LAG_BLOCK_MASK_PKT_ADDR 1841 +/*! IPOST_LAG_SYSTEM_LAG_GROUP_ID_BMAP_DOP_SYSTEM_LAG_GROUP_ID_BMAP. */ +#define BCMPKT_TRACE_DOP_IPOST_LAG_SYSTEM_LAG_GROUP_ID_BMAP_DOP_SYSTEM_LAG_GROUP_ID_BMAP 1842 +/*! IPOST_LAG_SYSTEM_LAG_MEMBER_INDEX_DOP_SYSTEM_LAG_MEMBER_INDEX. */ +#define BCMPKT_TRACE_DOP_IPOST_LAG_SYSTEM_LAG_MEMBER_INDEX_DOP_SYSTEM_LAG_MEMBER_INDEX 1843 +/*! IPOST_LAG_SYSTEM_PORT_INDEX_DOP_SYSTEM_PORT_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_LAG_SYSTEM_PORT_INDEX_DOP_SYSTEM_PORT_PKT_RD 1844 +/*! IPOST_LAG_SYSTEM_PORT_INDEX_DOP_SYSTEM_PORT_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_LAG_SYSTEM_PORT_INDEX_DOP_SYSTEM_PORT_PKT_ADDR 1845 +/*! IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_CHECK_BITMAP_INDEX_DOP_MEMBERSHIP_CHECK_BITMAP_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_CHECK_BITMAP_INDEX_DOP_MEMBERSHIP_CHECK_BITMAP_PKT_RD 1846 +/*! IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_CHECK_BITMAP_INDEX_DOP_MEMBERSHIP_CHECK_BITMAP_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_CHECK_BITMAP_INDEX_DOP_MEMBERSHIP_CHECK_BITMAP_PKT_ADDR 1847 +/*! IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_LOWER_INDEX_DOP_MEMBERSHIP_STATE_LOWER_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_LOWER_INDEX_DOP_MEMBERSHIP_STATE_LOWER_PKT_RD 1848 +/*! IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_LOWER_INDEX_DOP_MEMBERSHIP_STATE_LOWER_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_LOWER_INDEX_DOP_MEMBERSHIP_STATE_LOWER_PKT_ADDR 1849 +/*! IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_UPPER_INDEX_DOP_MEMBERSHIP_STATE_UPPER_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_UPPER_INDEX_DOP_MEMBERSHIP_STATE_UPPER_PKT_ADDR 1850 +/*! IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_UPPER_INDEX_DOP_MEMBERSHIP_STATE_UPPER_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_UPPER_INDEX_DOP_MEMBERSHIP_STATE_UPPER_PKT_RD 1851 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_6_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_6_PKT_RD 1852 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_3_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_3_PKT_ADDR 1853 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_5_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_5_PKT_RD 1854 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_2_PKT_RD 1855 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_3_PKT_RD 1856 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_1_PKT_ADDR 1857 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_6_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_6_PKT_ADDR 1858 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_4_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_4_PKT_RD 1859 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_7_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_7_PKT_RD 1860 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_0_PKT_ADDR 1861 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_1_PKT_RD 1862 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_2_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_2_PKT_ADDR 1863 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_0_PKT_RD 1864 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_5_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_5_PKT_ADDR 1865 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_4_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_4_PKT_ADDR 1866 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_7_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_7_PKT_ADDR 1867 +/*! IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_0_PKT_ADDR 1868 +/*! IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_3_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_3_PKT_ADDR 1869 +/*! IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_2_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_2_PKT_ADDR 1870 +/*! IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_0_PKT_RD 1871 +/*! IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_1_PKT_ADDR 1872 +/*! IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_2_PKT_RD 1873 +/*! IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_1_PKT_RD 1874 +/*! IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_3_PKT_RD 1875 +/*! IPOST_M_MPB_CCBI_FIXED_CCBI_B_BUS_DOP_OUT_CCBI_B_BUS. */ +#define BCMPKT_TRACE_DOP_IPOST_M_MPB_CCBI_FIXED_CCBI_B_BUS_DOP_OUT_CCBI_B_BUS 1876 +/*! IPOST_M_MPB_CCBI_FIXED_CCBI_MC_BUS_DOP_OUT_CCBI_MBUS. */ +#define BCMPKT_TRACE_DOP_IPOST_M_MPB_CCBI_FIXED_CCBI_MC_BUS_DOP_OUT_CCBI_MBUS 1877 +/*! IPOST_M_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP_OUT_MPB_FIXED_BUS. */ +#define BCMPKT_TRACE_DOP_IPOST_M_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP_OUT_MPB_FIXED_BUS 1878 +/*! IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_TCAM_MATCH 1879 +/*! IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_MATCH_INDEX 1880 +/*! IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY 1881 +/*! IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_PKT_RD 1882 +/*! IPOST_M_MPB_ENCODE_MPB_FLEX_BUS_DOP_OUT_MPB_FLEX_BUS. */ +#define BCMPKT_TRACE_DOP_IPOST_M_MPB_ENCODE_MPB_FLEX_BUS_DOP_OUT_MPB_FLEX_BUS 1883 +/*! IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD 1884 +/*! IPOST_TRACE_DROP_EVENT_ING_DROP_BUS_DOP_ING_DROP_BUS. */ +#define BCMPKT_TRACE_DOP_IPOST_TRACE_DROP_EVENT_ING_DROP_BUS_DOP_ING_DROP_BUS 1885 +/*! IPOST_TRACE_DROP_EVENT_ING_TRACE_BUS_DOP_ING_TRACE_BUS. */ +#define BCMPKT_TRACE_DOP_IPOST_TRACE_DROP_EVENT_ING_TRACE_BUS_DOP_ING_TRACE_BUS 1886 +/*! MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_BITMAP_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_BITMAP_PKT_ADDR 1887 +/*! MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_MEMBER_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_MEMBER_INDEX 1888 +/*! MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_STATE_PROFILE_LOWER_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_STATE_PROFILE_LOWER_PKT_RD 1889 +/*! MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_STATE_PROFILE_LOWER_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_STATE_PROFILE_LOWER_PKT_ADDR 1890 +/*! MEMDB_IFTA105_MEM0_0_KEY_DOP_MEM0_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_0_KEY_DOP_MEM0_0_PKT_RD 1891 +/*! MEMDB_IFTA105_MEM0_0_KEY_DOP_MEM0_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_0_KEY_DOP_MEM0_0_KEY 1892 +/*! MEMDB_IFTA105_MEM0_1_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_1_KEY_DOP_MEM0_1_PKT_RD 1893 +/*! MEMDB_IFTA105_MEM0_1_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_1_KEY_DOP_MEM0_1_KEY 1894 +/*! MEMDB_IFTA105_MEM0_2_KEY_DOP_MEM0_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_2_KEY_DOP_MEM0_2_PKT_RD 1895 +/*! MEMDB_IFTA105_MEM0_2_KEY_DOP_MEM0_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_2_KEY_DOP_MEM0_2_KEY 1896 +/*! MEMDB_IFTA105_MEM0_3_KEY_DOP_MEM0_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_3_KEY_DOP_MEM0_3_PKT_RD 1897 +/*! MEMDB_IFTA105_MEM0_3_KEY_DOP_MEM0_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_3_KEY_DOP_MEM0_3_KEY 1898 +/*! MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX 1899 +/*! MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX 1900 +/*! MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH 1901 +/*! MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX 1902 +/*! MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH 1903 +/*! MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH 1904 +/*! MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH 1905 +/*! MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX 1906 +/*! MINTERM_AGG_MINTERM_AGG2EDIT_CTRL_BUS_DOP_OUT_EGR_SCR_MINTERM_AGG2EDIT_CTRL_BUS. */ +#define BCMPKT_TRACE_DOP_MINTERM_AGG_MINTERM_AGG2EDIT_CTRL_BUS_DOP_OUT_EGR_SCR_MINTERM_AGG2EDIT_CTRL_BUS 1907 +/*! RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_0_PKT_RD 1908 +/*! RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_1_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_1_PKT_ADDR 1909 +/*! RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_1_PKT_RD 1910 +/*! RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_0_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_0_PKT_ADDR 1911 +/*! SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_TCAM_MATCH 1912 +/*! SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_MATCH_INDEX 1913 +/*! SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_PKT_RD. */ +#define BCMPKT_TRACE_DOP_SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_PKT_RD 1914 +/*! SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_KEY. */ +#define BCMPKT_TRACE_DOP_SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_KEY 1915 +/*! SIMPLE_MATCH_TABLE_INDEX_DOP_TABLE_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_SIMPLE_MATCH_TABLE_INDEX_DOP_TABLE_MATCH_INDEX 1916 +/*! SIMPLE_MATCH_TABLE_INDEX_DOP_TABLE_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_SIMPLE_MATCH_TABLE_INDEX_DOP_TABLE_TCAM_MATCH 1917 +/*! SIMPLE_MATCH_TABLE_KEY_DOP_TABLE_KEY. */ +#define BCMPKT_TRACE_DOP_SIMPLE_MATCH_TABLE_KEY_DOP_TABLE_KEY 1918 +/*! IPOST_CPU_COS_MAP_TCAM_INDEX_DOP_MAP_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_IPOST_CPU_COS_MAP_TCAM_INDEX_DOP_MAP_TCAM_MATCH_INDEX 1919 +/*! IPOST_CPU_COS_MAP_TCAM_INDEX_DOP_MAP_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_IPOST_CPU_COS_MAP_TCAM_INDEX_DOP_MAP_TCAM_TCAM_MATCH 1920 +/*! IPOST_CPU_COS_MAP_TCAM_KEY_DOP_MAP_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_IPOST_CPU_COS_MAP_TCAM_KEY_DOP_MAP_TCAM_KEY 1921 +/*! IPOST_CPU_COS_MAP_TCAM_KEY_DOP_MAP_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_CPU_COS_MAP_TCAM_KEY_DOP_MAP_TCAM_PKT_RD 1922 +/*! IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_PKT_RD. */ +#define BCMPKT_TRACE_DOP_IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_PKT_RD 1923 +/*! EFTA10_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA10_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT 1924 +/*! EFTA10_I1T_01_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA10_I1T_01_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT 1925 +/*! EFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT 1926 +/*! EFTA20_I1T_01_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_EFTA20_I1T_01_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT 1927 +/*! IFTA130_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA130_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT 1928 +/*! IFTA50_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA50_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT 1929 +/*! IFTA70_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA70_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT 1930 +/*! IFTA70_I1T_01_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA70_I1T_01_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT 1931 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1932 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1933 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1934 +/*! IDEV_CONFIG_DEBUG_CAPTURE_DATA_DOP_DEBUG_CAPTURE_PKT_WDATA. */ +#define BCMPKT_TRACE_DOP_IDEV_CONFIG_DEBUG_CAPTURE_DATA_DOP_DEBUG_CAPTURE_PKT_WDATA 1935 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1936 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1937 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1938 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1939 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1940 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1941 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1942 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1943 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1944 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1945 +/*! HDR_STACK_LITE_DEBUG_CAPTURE_DATA_DOP_DEBUG_CAPTURE_PKT_WDATA. */ +#define BCMPKT_TRACE_DOP_HDR_STACK_LITE_DEBUG_CAPTURE_DATA_DOP_DEBUG_CAPTURE_PKT_WDATA 1946 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1947 +/*! VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_2. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_2 1948 +/*! VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_1. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_1 1949 +/*! VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_1. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_1 1950 +/*! VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_1. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_1 1951 +/*! VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_3. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_3 1952 +/*! VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_3. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_3 1953 +/*! VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_0. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_0 1954 +/*! VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_0. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_0 1955 +/*! VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_0. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_0 1956 +/*! VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_2. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_2 1957 +/*! VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_2. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_2 1958 +/*! VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_3. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_3 1959 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1960 +/*! EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP_MPB_FLEX_BUS. */ +#define BCMPKT_TRACE_DOP_EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP_MPB_FLEX_BUS 1961 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1962 +/*! VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_1_KEY_PROFILE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_1_KEY_PROFILE_PKT_ADDR 1963 +/*! VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_2_KEY_PROFILE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_2_KEY_PROFILE_PKT_RD 1964 +/*! VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_3_KEY_PROFILE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_3_KEY_PROFILE_PKT_ADDR 1965 +/*! VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_3_KEY_PROFILE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_3_KEY_PROFILE_PKT_RD 1966 +/*! VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_2_KEY_PROFILE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_2_KEY_PROFILE_PKT_ADDR 1967 +/*! VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_0_KEY_PROFILE_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_0_KEY_PROFILE_PKT_ADDR 1968 +/*! VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_0_KEY_PROFILE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_0_KEY_PROFILE_PKT_RD 1969 +/*! VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_1_KEY_PROFILE_PKT_RD. */ +#define BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_1_KEY_PROFILE_PKT_RD 1970 +/*! VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_0. */ +#define BCMPKT_TRACE_DOP_VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_0 1971 +/*! VCA_IF_RESPONSE_VCA_DATA_DOP_BITP_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_VCA_IF_RESPONSE_VCA_DATA_DOP_BITP_MUX_OUT 1972 +/*! VCA_IF_RESPONSE_VCA_DATA_DOP_BOTP_MUX_IN. */ +#define BCMPKT_TRACE_DOP_VCA_IF_RESPONSE_VCA_DATA_DOP_BOTP_MUX_IN 1973 +/*! VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_2. */ +#define BCMPKT_TRACE_DOP_VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_2 1974 +/*! VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_1. */ +#define BCMPKT_TRACE_DOP_VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_1 1975 +/*! VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_3. */ +#define BCMPKT_TRACE_DOP_VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_3 1976 +/*! EGR_MIRROR_SEQUENCE_NUMBER_INDEX_DOP_SEQUENCE_NUMBER_PKT_RD. */ +#define BCMPKT_TRACE_DOP_EGR_MIRROR_SEQUENCE_NUMBER_INDEX_DOP_SEQUENCE_NUMBER_PKT_RD 1977 +/*! EGR_MIRROR_SEQUENCE_NUMBER_INDEX_DOP_SEQUENCE_NUMBER_PKT_ADDR. */ +#define BCMPKT_TRACE_DOP_EGR_MIRROR_SEQUENCE_NUMBER_INDEX_DOP_SEQUENCE_NUMBER_PKT_ADDR 1978 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1979 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1980 +/*! IFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT. */ +#define BCMPKT_TRACE_DOP_IFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT 1981 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1982 +/*! EPRE_EDEV_CONFIG_MPB_FIXED_DOP_MPB_FIXED_BUS. */ +#define BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_MPB_FIXED_DOP_MPB_FIXED_BUS 1983 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1984 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_TRUNCATE_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS. */ +#define BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_TRUNCATE_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS 1985 +/*! C7_DOP_VFI_2INDEX. */ +#define BCMPKT_TRACE_DOP_C7_DOP_VFI_2INDEX 1986 +/*! EFPMOD_MISC_DOP_CHANGE_DSCP. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_DSCP 1987 +/*! EFPMOD_MISC_DOP_LOOPBACK_PROFILE_HIGH_STR_INDEX. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_LOOPBACK_PROFILE_HIGH_STR_INDEX 1988 +/*! EFPMOD_MISC_DOP_ADD_EGRESS_TAIL_TS. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_ADD_EGRESS_TAIL_TS 1989 +/*! EFPMOD_MISC_DOP_LOOPBACK_PROFILE_NEXT_STR_INDEX. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_LOOPBACK_PROFILE_NEXT_STR_INDEX 1990 +/*! EFPMOD_MISC_DOP_CHANGE_MPLS_EXP. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_MPLS_EXP 1991 +/*! EFPMOD_MISC_DOP_CHANGE_VXLAN_FILEDS. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_VXLAN_FILEDS 1992 +/*! EFPMOD_MISC_DOP_CHANGE_OUTER_TPID. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_OUTER_TPID 1993 +/*! EFPMOD_MISC_DOP_CHANGE_OUTER_VLAN_TAG. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_OUTER_VLAN_TAG 1994 +/*! EFPMOD_MISC_DOP_ADD_INGRESS_TAIL_TS. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_ADD_INGRESS_TAIL_TS 1995 +/*! EFPMOD_MISC_DOP_UPDATE_CPU_DMA. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_UPDATE_CPU_DMA 1996 +/*! EFPMOD_MISC_DOP_REPLACE_SRV6_FIELDS. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_REPLACE_SRV6_FIELDS 1997 +/*! EFPMOD_MISC_DOP_CHANGE_NTP_TC. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_NTP_TC 1998 +/*! EFPMOD_MISC_DOP_CHNAGE_LOOPBACK_FILEDS. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHNAGE_LOOPBACK_FILEDS 1999 +/*! EFPMOD_MISC_DOP_RECALCULATE_IP_CHECKSUM. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_RECALCULATE_IP_CHECKSUM 2000 +/*! EFPMOD_MISC_DOP_EPRC_COPY_TYPE_1. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_EPRC_COPY_TYPE_1 2001 +/*! EFPMOD_MISC_DOP_EPRC_COPY_VALID_1. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_EPRC_COPY_VALID_1 2002 +/*! EFPMOD_MISC_DOP_EPRC_COPY_VALID_0. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_EPRC_COPY_VALID_0 2003 +/*! EFPMOD_MISC_DOP_CHANGE_GSH_FILEDS. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_GSH_FILEDS 2004 +/*! EFPMOD_MISC_DOP_EP_POWER_ACTIVITY_MONITOR_FLOW_INDEX. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_EP_POWER_ACTIVITY_MONITOR_FLOW_INDEX 2005 +/*! EFPMOD_MISC_DOP_CHANGE_1588_CORRECTION_FIELD. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_1588_CORRECTION_FIELD 2006 +/*! EFPMOD_MISC_DOP_EPRC_COPY_TYPE_0. */ +#define BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_EPRC_COPY_TYPE_0 2007 +/*! EFPPARS_EFP_RANGE_CHECK_DOPS_EFP_RANGE_CHECK_BM. */ +#define BCMPKT_TRACE_DOP_EFPPARS_EFP_RANGE_CHECK_DOPS_EFP_RANGE_CHECK_BM 2008 +/*! EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_1. */ +#define BCMPKT_TRACE_DOP_EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_1 2009 +/*! EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_3. */ +#define BCMPKT_TRACE_DOP_EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_3 2010 +/*! EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_2. */ +#define BCMPKT_TRACE_DOP_EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_2 2011 +/*! EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_0. */ +#define BCMPKT_TRACE_DOP_EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_0 2012 +/*! EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_2. */ +#define BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_2 2013 +/*! EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_3. */ +#define BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_3 2014 +/*! EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_0. */ +#define BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_0 2015 +/*! EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_1. */ +#define BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_1 2016 +/*! EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_1. */ +#define BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_1 2017 +/*! EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_0. */ +#define BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_0 2018 +/*! EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_3. */ +#define BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_3 2019 +/*! EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_2. */ +#define BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_2 2020 +/*! EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_0. */ +#define BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_0 2021 +/*! EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_1. */ +#define BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_1 2022 +/*! EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_2. */ +#define BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_2 2023 +/*! EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_3. */ +#define BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_3 2024 +/*! EPARS_GROUP_4_DOPS_UNDERLAY_L3_OIF. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_UNDERLAY_L3_OIF 2025 +/*! EPARS_GROUP_4_DOPS_OVERLAY_NHI_VALID. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_OVERLAY_NHI_VALID 2026 +/*! EPARS_GROUP_4_DOPS_UNDERLAY_NHI_VALID. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_UNDERLAY_NHI_VALID 2027 +/*! EPARS_GROUP_4_DOPS_OVERLAY_NHI. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_OVERLAY_NHI 2028 +/*! EPARS_GROUP_4_DOPS_DVP. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_DVP 2029 +/*! EPARS_GROUP_4_DOPS_OVERLAY_L3_OIF_VALID. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_OVERLAY_L3_OIF_VALID 2030 +/*! EPARS_GROUP_4_DOPS_UNDERLAY_NHI. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_UNDERLAY_NHI 2031 +/*! EPARS_GROUP_4_DOPS_OVERLAY_L3_OIF. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_OVERLAY_L3_OIF 2032 +/*! EPARS_GROUP_4_DOPS_UNDERLAY_L3_OIF_VALID. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_UNDERLAY_L3_OIF_VALID 2033 +/*! EPARS_GROUP_9_1_DOPS_OVERLAY_EGR_VFI. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_9_1_DOPS_OVERLAY_EGR_VFI 2034 +/*! EPARS_GROUP_9_1_DOPS_UNDERLAY_EGR_VFI. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_9_1_DOPS_UNDERLAY_EGR_VFI 2035 +/*! EPARS_GROUP_9_2_DOPS_PCBE_EGRESS_PORT. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_9_2_DOPS_PCBE_EGRESS_PORT 2036 +/*! EPARS_GROUP_9_2_DOPS_MPLS_PSN_INDEX. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_9_2_DOPS_MPLS_PSN_INDEX 2037 +/*! EPARS_GROUP_9_2_DOPS_L3_TUNNEL_INDEX. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_9_2_DOPS_L3_TUNNEL_INDEX 2038 +/*! EPARS_GROUP_EGR_ADAPT_1_DOPS_EGR_ADAPT_LOOKUP_DONE. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_EGR_ADAPT_1_DOPS_EGR_ADAPT_LOOKUP_DONE 2039 +/*! EPARS_GROUP_EGR_ADAPT_1_DOPS_EGR_ADAPT_KEY. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_EGR_ADAPT_1_DOPS_EGR_ADAPT_KEY 2040 +/*! EPARS_GROUP_EGR_ADAPT_2_DOPS_EGR_ADAPT_HIT. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_EGR_ADAPT_2_DOPS_EGR_ADAPT_HIT 2041 +/*! EPARS_GROUP_EGR_ADAPT_2_DOPS_EGR_ADAPT_INDEX. */ +#define BCMPKT_TRACE_DOP_EPARS_GROUP_EGR_ADAPT_2_DOPS_EGR_ADAPT_INDEX 2042 +/*! EPMOD_MISC_DOP_SRV6_PATH_TRACE. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_SRV6_PATH_TRACE 2043 +/*! EPMOD_MISC_DOP_REPLACE_OUTER_VLAN. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REPLACE_OUTER_VLAN 2044 +/*! EPMOD_MISC_DOP_ADD_L3_INSTR_HDR. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_L3_INSTR_HDR 2045 +/*! EPMOD_MISC_DOP_INHERIT_ROCEV2_DCN_HEADER_FROM_PAYLOAD. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_INHERIT_ROCEV2_DCN_HEADER_FROM_PAYLOAD 2046 +/*! EPMOD_MISC_DOP_GEN_ROCEV2_CNP. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_GEN_ROCEV2_CNP 2047 +/*! EPMOD_MISC_DOP_ADD_ROCEV2_DCN_HEADER. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_ROCEV2_DCN_HEADER 2048 +/*! EPMOD_MISC_DOP_REMOVE_OPAQUE_TAG. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REMOVE_OPAQUE_TAG 2049 +/*! EPMOD_MISC_DOP_INSERT_INT_MD_HDR. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_INSERT_INT_MD_HDR 2050 +/*! EPMOD_MISC_DOP_L3_TUNNEL_ENCAP. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_L3_TUNNEL_ENCAP 2051 +/*! EPMOD_MISC_DOP_IFA_DEFERRED_INSERT. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_IFA_DEFERRED_INSERT 2052 +/*! EPMOD_MISC_DOP_SRH_DECAP. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_SRH_DECAP 2053 +/*! EPMOD_MISC_DOP_REMOVE_L3_INSTR_HDR. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REMOVE_L3_INSTR_HDR 2054 +/*! EPMOD_MISC_DOP_RECALCULATE_IP_CHECKSUM. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_RECALCULATE_IP_CHECKSUM 2055 +/*! EPMOD_MISC_DOP_ADD_MIRROR_ENCAP. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_MIRROR_ENCAP 2056 +/*! EPMOD_MISC_DOP_ADD_SVTAG. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_SVTAG 2057 +/*! EPMOD_MISC_DOP_REMOVE_IFA_HDR. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REMOVE_IFA_HDR 2058 +/*! EPMOD_MISC_DOP_ADD_DMA. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_DMA 2059 +/*! EPMOD_MISC_DOP_REMOVE_ROCE_DCN_HEADER. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REMOVE_ROCE_DCN_HEADER 2060 +/*! EPMOD_MISC_DOP_INSERT_INT_BASE_HDR. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_INSERT_INT_BASE_HDR 2061 +/*! EPMOD_MISC_DOP_REPLACE_TOP_LEVEL_MPLS_EXP. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REPLACE_TOP_LEVEL_MPLS_EXP 2062 +/*! EPMOD_MISC_DOP_L2_TUNNEL_DECAP. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_L2_TUNNEL_DECAP 2063 +/*! EPMOD_MISC_DOP_L3_TUNNEL_DECAP. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_L3_TUNNEL_DECAP 2064 +/*! EPMOD_MISC_DOP_PKT_PADDING. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_PKT_PADDING 2065 +/*! EPMOD_MISC_DOP_ADD_OPAQUE_TAG. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_OPAQUE_TAG 2066 +/*! EPMOD_MISC_DOP_REMOVE_SVTAG. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REMOVE_SVTAG 2067 +/*! EPMOD_MISC_DOP_ADD_OUTER_VLAN. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_OUTER_VLAN 2068 +/*! EPMOD_MISC_DOP_ADD_RSPAN_TAG. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_RSPAN_TAG 2069 +/*! EPMOD_MISC_DOP_REMOVE_L2_INSTR_TAG. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REMOVE_L2_INSTR_TAG 2070 +/*! EPMOD_MISC_DOP_REPLACE_TOP_LEVEL_MPLS_TTL. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REPLACE_TOP_LEVEL_MPLS_TTL 2071 +/*! EPMOD_MISC_DOP_DELETE_OUTER_VLAN. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_DELETE_OUTER_VLAN 2072 +/*! EPMOD_MISC_DOP_PREPEND_HEADERS_TO_PACKET. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_PREPEND_HEADERS_TO_PACKET 2073 +/*! EPMOD_MISC_DOP_L2_TUNNEL_ENCAP. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_L2_TUNNEL_ENCAP 2074 +/*! EPMOD_MISC_DOP_INHERIT_ROCEV2_DCN_HEADER_FROM_TUNNEL. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_INHERIT_ROCEV2_DCN_HEADER_FROM_TUNNEL 2075 +/*! EPMOD_MISC_DOP_MODIFY_DELETE_GSH. */ +#define BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_MODIFY_DELETE_GSH 2076 +/*! ESW_GROUP_1_DOPS_INPLACE_MACDA_CHANGED. */ +#define BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_MACDA_CHANGED 2077 +/*! ESW_GROUP_1_DOPS_INT_ACTION_PROFILE. */ +#define BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INT_ACTION_PROFILE 2078 +/*! ESW_GROUP_1_DOPS_INPLACE_TTL_CHANGED. */ +#define BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_TTL_CHANGED 2079 +/*! ESW_GROUP_1_DOPS_INPLACE_SRH_CHANGED. */ +#define BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_SRH_CHANGED 2080 +/*! ESW_GROUP_1_DOPS_INPLACE_DIP_CHANGED. */ +#define BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_DIP_CHANGED 2081 +/*! ESW_GROUP_1_DOPS_INPLACE_PAYLOAD_LENGTH_CHANGED. */ +#define BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_PAYLOAD_LENGTH_CHANGED 2082 +/*! ESW_GROUP_1_DOPS_INT_OPERATION. */ +#define BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INT_OPERATION 2083 +/*! ESW_GROUP_1_DOPS_INPLACE_MACSA_CHANGED. */ +#define BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_MACSA_CHANGED 2084 +/*! ESW_GROUP_1_DOPS_INPLACE_TOS_CHANGED. */ +#define BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_TOS_CHANGED 2085 +/*! ESW_GROUP_1_DOPS_INPLACE_ETYPE_CHANGED. */ +#define BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_ETYPE_CHANGED 2086 +/*! ESW_GROUP_1_DOPS_INPLACE_DCN_CHANGED. */ +#define BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_DCN_CHANGED 2087 +/*! ESW_GROUP_1_DOPS_INPLACE_NEXT_HDR_CHANGED. */ +#define BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_NEXT_HDR_CHANGED 2088 +/*! FP_GROUP2_DOP_THIRD_LKUP_KEY_7. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_7 2089 +/*! FP_GROUP2_DOP_THIRD_LKUP_KEY_6. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_6 2090 +/*! FP_GROUP2_DOP_THIRD_LKUP_KEY_5. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_5 2091 +/*! FP_GROUP2_DOP_THIRD_LKUP_KEY_4. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_4 2092 +/*! FP_GROUP2_DOP_THIRD_LKUP_KEY_3. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_3 2093 +/*! FP_GROUP2_DOP_THIRD_LKUP_KEY_2. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_2 2094 +/*! FP_GROUP2_DOP_THIRD_LKUP_KEY_1. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_1 2095 +/*! FP_GROUP2_DOP_THIRD_LKUP_KEY_0. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_0 2096 +/*! FP_GROUP2_DOP_THIRD_LKUP_KEY_8. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_8 2097 +/*! FP_GROUP2_DOP_SECOND_LKUP_KEY_8. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_8 2098 +/*! FP_GROUP2_DOP_SECOND_LKUP_KEY_3. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_3 2099 +/*! FP_GROUP2_DOP_SECOND_LKUP_KEY_2. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_2 2100 +/*! FP_GROUP2_DOP_SECOND_LKUP_KEY_1. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_1 2101 +/*! FP_GROUP2_DOP_SECOND_LKUP_KEY_0. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_0 2102 +/*! FP_GROUP2_DOP_SECOND_LKUP_KEY_7. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_7 2103 +/*! FP_GROUP2_DOP_SECOND_LKUP_KEY_6. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_6 2104 +/*! FP_GROUP2_DOP_SECOND_LKUP_KEY_5. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_5 2105 +/*! FP_GROUP2_DOP_SECOND_LKUP_KEY_4. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_4 2106 +/*! FP_GROUP2_DOP_FIRST_LKUP_KEY_0. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_0 2107 +/*! FP_GROUP2_DOP_FIRST_LKUP_KEY_1. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_1 2108 +/*! FP_GROUP2_DOP_FIRST_LKUP_KEY_2. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_2 2109 +/*! FP_GROUP2_DOP_FIRST_LKUP_KEY_3. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_3 2110 +/*! FP_GROUP2_DOP_FIRST_LKUP_KEY_4. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_4 2111 +/*! FP_GROUP2_DOP_FIRST_LKUP_KEY_5. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_5 2112 +/*! FP_GROUP2_DOP_FIRST_LKUP_KEY_6. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_6 2113 +/*! FP_GROUP2_DOP_FIRST_LKUP_KEY_7. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_7 2114 +/*! FP_GROUP2_DOP_FIRST_LKUP_KEY_8. */ +#define BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_8 2115 +/*! FP_GROUP8_DOP_LKUP_HIT3. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT3 2116 +/*! FP_GROUP8_DOP_LKUP_HIT2. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT2 2117 +/*! FP_GROUP8_DOP_LKUP_HIT_INDEX8. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX8 2118 +/*! FP_GROUP8_DOP_LKUP_HIT0. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT0 2119 +/*! FP_GROUP8_DOP_LKUP_HIT6. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT6 2120 +/*! FP_GROUP8_DOP_LKUP_HIT5. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT5 2121 +/*! FP_GROUP8_DOP_LKUP_HIT4. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT4 2122 +/*! FP_GROUP8_DOP_LKUP_HIT_INDEX2. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX2 2123 +/*! FP_GROUP8_DOP_LKUP_HIT_INDEX0. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX0 2124 +/*! FP_GROUP8_DOP_LKUP_HIT_INDEX1. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX1 2125 +/*! FP_GROUP8_DOP_LKUP_HIT_INDEX6. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX6 2126 +/*! FP_GROUP8_DOP_LKUP_HIT1. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT1 2127 +/*! FP_GROUP8_DOP_LKUP_HIT_INDEX4. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX4 2128 +/*! FP_GROUP8_DOP_LKUP_HIT_INDEX7. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX7 2129 +/*! FP_GROUP8_DOP_LKUP_HIT_INDEX3. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX3 2130 +/*! FP_GROUP8_DOP_LKUP_HIT7. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT7 2131 +/*! FP_GROUP8_DOP_LKUP_HIT_INDEX5. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX5 2132 +/*! FP_GROUP8_DOP_LKUP_HIT8. */ +#define BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT8 2133 +/*! IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOPKUP_IS_IPM. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOPKUP_IS_IPM 2134 +/*! IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOPKUP_IS_KICKED_OFF. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOPKUP_IS_KICKED_OFF 2135 +/*! IFWD1_GROUP_A_1_DOPS_LPM_SRC_LOOKUP_KEY. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_SRC_LOOKUP_KEY 2136 +/*! IFWD1_GROUP_A_1_DOPS_LPM_SRC_LOOPKUP_IS_V6. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_SRC_LOOPKUP_IS_V6 2137 +/*! IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOKUP_KEY. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOKUP_KEY 2138 +/*! IFWD1_GROUP_A_1_DOPS_LPM_SRC_LOOPKUP_IS_KICKED_OFF. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_SRC_LOOPKUP_IS_KICKED_OFF 2139 +/*! IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOPKUP_IS_V6. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOPKUP_IS_V6 2140 +/*! IFWD1_GROUP_A_2_DOPS_COMP_DST_LOOKUP_KEY. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_A_2_DOPS_COMP_DST_LOOKUP_KEY 2141 +/*! IFWD1_GROUP_A_2_DOPS_COMP_DST_LOOPKUP_IS_V6. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_A_2_DOPS_COMP_DST_LOOPKUP_IS_V6 2142 +/*! IFWD1_GROUP_A_2_DOPS_COMP_DST_LOOPKUP_IS_KICKED_OFF. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_A_2_DOPS_COMP_DST_LOOPKUP_IS_KICKED_OFF 2143 +/*! IFWD1_GROUP_A_2_DOPS_COMP_SRC_LOOKUP_KEY. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_A_2_DOPS_COMP_SRC_LOOKUP_KEY 2144 +/*! IFWD1_GROUP_A_2_DOPS_COMP_SRC_LOOPKUP_IS_KICKED_OFF. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_A_2_DOPS_COMP_SRC_LOOPKUP_IS_KICKED_OFF 2145 +/*! IFWD1_GROUP_A_2_DOPS_COMP_SRC_LOOPKUP_IS_V6. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_A_2_DOPS_COMP_SRC_LOOPKUP_IS_V6 2146 +/*! IFWD1_GROUP_B_DOPS_L2_USER_ENTRY_LOOKUP_DONE. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_B_DOPS_L2_USER_ENTRY_LOOKUP_DONE 2147 +/*! IFWD1_GROUP_B_DOPS_L2_SRC_LOOKUP_DONE. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_B_DOPS_L2_SRC_LOOKUP_DONE 2148 +/*! IFWD1_GROUP_B_DOPS_L2_USER_ENTRY_KEY. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_B_DOPS_L2_USER_ENTRY_KEY 2149 +/*! IFWD1_GROUP_B_DOPS_L2_DST_LOOKUP_DONE. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_B_DOPS_L2_DST_LOOKUP_DONE 2150 +/*! IFWD1_GROUP_B_DOPS_L2_SRC_LOOKUP_KEY. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_B_DOPS_L2_SRC_LOOKUP_KEY 2151 +/*! IFWD1_GROUP_B_DOPS_L2_DST_LOOKUP_KEY. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_B_DOPS_L2_DST_LOOKUP_KEY 2152 +/*! IFWD1_GROUP_C_DOPS_EM_LOOKUP_KEY. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_C_DOPS_EM_LOOKUP_KEY 2153 +/*! IFWD1_GROUP_C_DOPS_EM_LOOKUP_DONE. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_C_DOPS_EM_LOOKUP_DONE 2154 +/*! IFWD1_GROUP_D_DOPS_EM_LTS_TCAM_LOOKUP_KEY. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_D_DOPS_EM_LTS_TCAM_LOOKUP_KEY 2155 +/*! IFWD1_GROUP_D_DOPS_EM_LTS_TCAM_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_D_DOPS_EM_LTS_TCAM_HIT_INDEX 2156 +/*! IFWD1_GROUP_D_DOPS_EM_LTS_TCAM_HIT. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_D_DOPS_EM_LTS_TCAM_HIT 2157 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_8. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_8 2158 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_3. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_3 2159 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_LOOKUP_KEY_0. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_LOOKUP_KEY_0 2160 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_0. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_0 2161 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_7. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_7 2162 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_6. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_6 2163 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_5. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_5 2164 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_4. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_4 2165 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_8. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_8 2166 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_1. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_1 2167 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_2. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_2 2168 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_0. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_0 2169 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_1. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_1 2170 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_2. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_2 2171 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_3. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_3 2172 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_4. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_4 2173 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_5. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_5 2174 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_6. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_6 2175 +/*! IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_7. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_7 2176 +/*! IFWD1_GROUP_G_1_DOPS_LPM_SRC_HIT_TBL. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_1_DOPS_LPM_SRC_HIT_TBL 2177 +/*! IFWD1_GROUP_G_1_DOPS_LPM_SRC_HIT. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_1_DOPS_LPM_SRC_HIT 2178 +/*! IFWD1_GROUP_G_1_DOPS_LPM_DST_HIT. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_1_DOPS_LPM_DST_HIT 2179 +/*! IFWD1_GROUP_G_1_DOPS_LPM_SRC_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_1_DOPS_LPM_SRC_HIT_INDEX 2180 +/*! IFWD1_GROUP_G_1_DOPS_LPM_DST_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_1_DOPS_LPM_DST_HIT_INDEX 2181 +/*! IFWD1_GROUP_G_1_DOPS_LPM_DST_HIT_TBL. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_1_DOPS_LPM_DST_HIT_TBL 2182 +/*! IFWD1_GROUP_G_2_DOPS_LPM_SRC_HIT_TBL. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_2_DOPS_LPM_SRC_HIT_TBL 2183 +/*! IFWD1_GROUP_G_2_DOPS_LPM_SRC_HIT. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_2_DOPS_LPM_SRC_HIT 2184 +/*! IFWD1_GROUP_G_2_DOPS_LPM_DST_HIT. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_2_DOPS_LPM_DST_HIT 2185 +/*! IFWD1_GROUP_G_2_DOPS_LPM_SRC_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_2_DOPS_LPM_SRC_HIT_INDEX 2186 +/*! IFWD1_GROUP_G_2_DOPS_LPM_DST_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_2_DOPS_LPM_DST_HIT_INDEX 2187 +/*! IFWD1_GROUP_G_2_DOPS_LPM_DST_HIT_TBL. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_2_DOPS_LPM_DST_HIT_TBL 2188 +/*! IFWD1_GROUP_G_3_DOPS_L2_SRC_HIT. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_3_DOPS_L2_SRC_HIT 2189 +/*! IFWD1_GROUP_G_3_DOPS_L2_USER_ENTRY_HIT. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_3_DOPS_L2_USER_ENTRY_HIT 2190 +/*! IFWD1_GROUP_G_3_DOPS_L2_DST_HIT. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_3_DOPS_L2_DST_HIT 2191 +/*! IFWD1_GROUP_G_3_DOPS_L2_USER_ENTRY_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_3_DOPS_L2_USER_ENTRY_HIT_INDEX 2192 +/*! IFWD1_GROUP_G_3_DOPS_L2_SRC_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_3_DOPS_L2_SRC_HIT_INDEX 2193 +/*! IFWD1_GROUP_G_3_DOPS_L2_DST_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_3_DOPS_L2_DST_HIT_INDEX 2194 +/*! IFWD1_GROUP_G_4_DOPS_EM_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_4_DOPS_EM_HIT_INDEX 2195 +/*! IFWD1_GROUP_G_4_DOPS_EM_HIT. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_4_DOPS_EM_HIT 2196 +/*! IFWD1_GROUP_G_4_DOPS_EM_HIT_TBL. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_4_DOPS_EM_HIT_TBL 2197 +/*! IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_B0. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_B0 2198 +/*! IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_B1. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_B1 2199 +/*! IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_A1. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_A1 2200 +/*! IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_A0. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_A0 2201 +/*! IFWD1_GROUP_G_5_DOPS_DISABLE_VLAN_CHECKS. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_5_DOPS_DISABLE_VLAN_CHECKS 2202 +/*! IFWD1_GROUP_G_5_DOPS_LOOKUP_STATUS_VECTOR. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_5_DOPS_LOOKUP_STATUS_VECTOR 2203 +/*! IFWD1_GROUP_G_6_DOPS_REMAP_DOT1P_INDEX. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_6_DOPS_REMAP_DOT1P_INDEX 2204 +/*! IFWD1_GROUP_G_6_DOPS_REMAP_PAYLOAD_DOT1P. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_6_DOPS_REMAP_PAYLOAD_DOT1P 2205 +/*! IFWD1_GROUP_G_6_DOPS_REMAP_OUTER_DOT1P. */ +#define BCMPKT_TRACE_DOP_IFWD1_GROUP_G_6_DOPS_REMAP_OUTER_DOT1P 2206 +/*! IPARS_HASH_TABLE_DOP_L3_TUNNEL_LOOKUP_SEARCH_KEY. */ +#define BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_L3_TUNNEL_LOOKUP_SEARCH_KEY 2207 +/*! IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_1_HIT. */ +#define BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_1_HIT 2208 +/*! IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_2_SEARCH_KEY. */ +#define BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_2_SEARCH_KEY 2209 +/*! IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_1_SEARCH_KEY. */ +#define BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_1_SEARCH_KEY 2210 +/*! IPARS_HASH_TABLE_DOP_L3_TUNNEL_LOOKUP_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_L3_TUNNEL_LOOKUP_HIT_INDEX 2211 +/*! IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_2_HIT. */ +#define BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_2_HIT 2212 +/*! IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_2_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_2_HIT_INDEX 2213 +/*! IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_1_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_1_HIT_INDEX 2214 +/*! IPARS_HASH_TABLE_DOP_L3_TUNNEL_LOOKUP_HIT. */ +#define BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_L3_TUNNEL_LOOKUP_HIT 2215 +/*! IPARS_L3_TUNNEL_TCAM_DOP_SEARCH_KEY_1. */ +#define BCMPKT_TRACE_DOP_IPARS_L3_TUNNEL_TCAM_DOP_SEARCH_KEY_1 2216 +/*! IPARS_L3_TUNNEL_TCAM_DOP_SEARCH_KEY_0. */ +#define BCMPKT_TRACE_DOP_IPARS_L3_TUNNEL_TCAM_DOP_SEARCH_KEY_0 2217 +/*! IPARS_L3_TUNNEL_TCAM_DOP_TCAM_HIT. */ +#define BCMPKT_TRACE_DOP_IPARS_L3_TUNNEL_TCAM_DOP_TCAM_HIT 2218 +/*! IPARS_L3_TUNNEL_TCAM_DOP_TUNNEL_OR_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IPARS_L3_TUNNEL_TCAM_DOP_TUNNEL_OR_HIT_INDEX 2219 +/*! IPARS_MISC_DOP_IPAD_BUS. */ +#define BCMPKT_TRACE_DOP_IPARS_MISC_DOP_IPAD_BUS 2220 +/*! IPARS_MY_PREFIX_TCAM_DOP_MY_PREFIX_TCAM_HIT. */ +#define BCMPKT_TRACE_DOP_IPARS_MY_PREFIX_TCAM_DOP_MY_PREFIX_TCAM_HIT 2221 +/*! IPARS_MY_PREFIX_TCAM_DOP_MY_PREFIX_TCAM_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IPARS_MY_PREFIX_TCAM_DOP_MY_PREFIX_TCAM_HIT_INDEX 2222 +/*! IPARS_MY_PREFIX_TCAM_DOP_MY_PREFIX_TCAM_LOOKUP_KEY. */ +#define BCMPKT_TRACE_DOP_IPARS_MY_PREFIX_TCAM_DOP_MY_PREFIX_TCAM_LOOKUP_KEY 2223 +/*! IPARS_UDF_TCAM_DOP_UDF_TCAM_HIT. */ +#define BCMPKT_TRACE_DOP_IPARS_UDF_TCAM_DOP_UDF_TCAM_HIT 2224 +/*! IPARS_UDF_TCAM_DOP_UDF_TCAM_LOOKUP_KEY. */ +#define BCMPKT_TRACE_DOP_IPARS_UDF_TCAM_DOP_UDF_TCAM_LOOKUP_KEY 2225 +/*! IPARS_UDF_TCAM_DOP_UDF_TCAM_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_IPARS_UDF_TCAM_DOP_UDF_TCAM_HIT_INDEX 2226 +/*! MISC_DOP_DO_IPMC_LOOKUP. */ +#define BCMPKT_TRACE_DOP_MISC_DOP_DO_IPMC_LOOKUP 2227 +/*! MISC_DOP_ELIGIBLE_FOR_L3_LOOKUP. */ +#define BCMPKT_TRACE_DOP_MISC_DOP_ELIGIBLE_FOR_L3_LOOKUP 2228 +/*! MY_STATION_2_TCAM_DOP_MY_STATION_2_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_MY_STATION_2_TCAM_DOP_MY_STATION_2_TCAM_KEY 2229 +/*! MY_STATION_2_TCAM_DOP_MY_STATION_2_TCAM_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_MY_STATION_2_TCAM_DOP_MY_STATION_2_TCAM_HIT_INDEX 2230 +/*! MY_STATION_2_TCAM_DOP_MY_STATION_2_TCAM_HIT. */ +#define BCMPKT_TRACE_DOP_MY_STATION_2_TCAM_DOP_MY_STATION_2_TCAM_HIT 2231 +/*! MY_STATION_TCAM_DOP_MY_STATION_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_MY_STATION_TCAM_DOP_MY_STATION_TCAM_KEY 2232 +/*! MY_STATION_TCAM_DOP_MY_STATION_TCAM_HIT. */ +#define BCMPKT_TRACE_DOP_MY_STATION_TCAM_DOP_MY_STATION_TCAM_HIT 2233 +/*! MY_STATION_TCAM_DOP_MY_STATION_TCAM_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_MY_STATION_TCAM_DOP_MY_STATION_TCAM_HIT_INDEX 2234 +/*! RSEL_GROUP1_DOP_OL_WCMP_BUCKET_HASH_VALUE. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_WCMP_BUCKET_HASH_VALUE 2235 +/*! RSEL_GROUP1_DOP_OL_MEMBER_INDEX. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_MEMBER_INDEX 2236 +/*! RSEL_GROUP1_DOP_OL_L3_ECMP_HASH_VALUE. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_L3_ECMP_HASH_VALUE 2237 +/*! RSEL_GROUP1_DOP_OL_RESOLUTION_DONE. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_RESOLUTION_DONE 2238 +/*! RSEL_GROUP1_DOP_OL_GROUP_PTR. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_GROUP_PTR 2239 +/*! RSEL_GROUP1_DOP_OL_WCMP_WEIGHT_HASH_VALUE. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_WCMP_WEIGHT_HASH_VALUE 2240 +/*! RSEL_GROUP1_DOP_OL_NHI. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_NHI 2241 +/*! RSEL_GROUP2_1_DOP_UL_GROUP_PTR. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP2_1_DOP_UL_GROUP_PTR 2242 +/*! RSEL_GROUP2_2_DOP_PRIMARY_RH_FLOW_SET_INDEX. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP2_2_DOP_PRIMARY_RH_FLOW_SET_INDEX 2243 +/*! RSEL_GROUP2_2_DOP_PRIMARY_RH_ECMP_HASH. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP2_2_DOP_PRIMARY_RH_ECMP_HASH 2244 +/*! RSEL_GROUP2_3_DOP_SECONDARY_RH_ECMP_HASH. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP2_3_DOP_SECONDARY_RH_ECMP_HASH 2245 +/*! RSEL_GROUP2_3_DOP_SECONDARY_RH_FLOW_SET_INDEX. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP2_3_DOP_SECONDARY_RH_FLOW_SET_INDEX 2246 +/*! RSEL_GROUP3_1_DOP_PRIMARY_UL_NHI. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP3_1_DOP_PRIMARY_UL_NHI 2247 +/*! RSEL_GROUP3_1_DOP_PRIMARY_MEMBER_INDEX. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP3_1_DOP_PRIMARY_MEMBER_INDEX 2248 +/*! RSEL_GROUP3_1_DOP_PRIMARY_ECMP_L3_HASH_VALUE. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP3_1_DOP_PRIMARY_ECMP_L3_HASH_VALUE 2249 +/*! RSEL_GROUP3_2_DOP_SECONDARY_MEMBER_INDEX. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP3_2_DOP_SECONDARY_MEMBER_INDEX 2250 +/*! RSEL_GROUP3_2_DOP_SECONDARY_ECMP_L3_HASH_VALUE. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP3_2_DOP_SECONDARY_ECMP_L3_HASH_VALUE 2251 +/*! RSEL_GROUP3_2_DOP_SECONDARY_UL_NHI. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP3_2_DOP_SECONDARY_UL_NHI 2252 +/*! RSEL_GROUP3_3_DOP_PRIMARY_WCMP_BUCKET_HASH_VALUE. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP3_3_DOP_PRIMARY_WCMP_BUCKET_HASH_VALUE 2253 +/*! RSEL_GROUP3_3_DOP_SECONDARY_WCMP_BUCKET_HASH_VALUE. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP3_3_DOP_SECONDARY_WCMP_BUCKET_HASH_VALUE 2254 +/*! RSEL_GROUP3_4_DOP_TERTIARY_UL_NHI. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP3_4_DOP_TERTIARY_UL_NHI 2255 +/*! RSEL_GROUP3_5_DOP_PRIMARY_PATH. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP3_5_DOP_PRIMARY_PATH 2256 +/*! RSEL_GROUP3_5_DOP_PROTECTION_PATH_ACTIVE. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP3_5_DOP_PROTECTION_PATH_ACTIVE 2257 +/*! RSEL_GROUP3_5_DOP_TERTIARY_PATH. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP3_5_DOP_TERTIARY_PATH 2258 +/*! RSEL_GROUP3_5_DOP_SECONDARY_PATH. */ +#define BCMPKT_TRACE_DOP_RSEL_GROUP3_5_DOP_SECONDARY_PATH 2259 +/*! SW_GROUP1_1_DOP_ING_VFI. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_ING_VFI 2260 +/*! SW_GROUP1_1_DOP_VRF. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_VRF 2261 +/*! SW_GROUP1_1_DOP_L3_IIF. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_L3_IIF 2262 +/*! SW_GROUP1_1_DOP_FORWARDING_FIELD. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_FORWARDING_FIELD 2263 +/*! SW_GROUP1_1_DOP_FORWARDING_TYPE. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_FORWARDING_TYPE 2264 +/*! SW_GROUP1_1_DOP_DVP. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_DVP 2265 +/*! SW_GROUP1_1_DOP_SVP. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_SVP 2266 +/*! SW_GROUP1_2_DOP_INT_CN. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_2_DOP_INT_CN 2267 +/*! SW_GROUP1_3_DOP_L2MC_INDEX. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_3_DOP_L2MC_INDEX 2268 +/*! SW_GROUP1_4_DOP_MC_INDEX. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_4_DOP_MC_INDEX 2269 +/*! SW_GROUP1_5_DOP_LAG_ID. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_5_DOP_LAG_ID 2270 +/*! SW_GROUP1_5_DOP_HASH_VALUE_LAG. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_5_DOP_HASH_VALUE_LAG 2271 +/*! SW_GROUP1_6_DOP_IP_POWER_ACTIVITY_MONITOR_NUM_OF_ACTIVE_IFP_SLICES. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_6_DOP_IP_POWER_ACTIVITY_MONITOR_NUM_OF_ACTIVE_IFP_SLICES 2272 +/*! SW_GROUP1_6_DOP_IP_POWER_ACTIVITY_MONITOR_NUM_OF_ACTIVE_UFT_BANKS. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_6_DOP_IP_POWER_ACTIVITY_MONITOR_NUM_OF_ACTIVE_UFT_BANKS 2273 +/*! SW_GROUP1_7_DOP_CHANGE_DSCP. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_7_DOP_CHANGE_DSCP 2274 +/*! SW_GROUP1_7_DOP_PRESERVE_DSCP. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_7_DOP_PRESERVE_DSCP 2275 +/*! SW_GROUP1_7_DOP_DSCP. */ +#define BCMPKT_TRACE_DOP_SW_GROUP1_7_DOP_DSCP 2276 +/*! SW_GROUP2_1_DOP_L2MC_PBM. */ +#define BCMPKT_TRACE_DOP_SW_GROUP2_1_DOP_L2MC_PBM 2277 +/*! SW_GROUP2_2_DOP_OR_PBM. */ +#define BCMPKT_TRACE_DOP_SW_GROUP2_2_DOP_OR_PBM 2278 +/*! SW_GROUP2_3_DOP_LAG_OFFSET. */ +#define BCMPKT_TRACE_DOP_SW_GROUP2_3_DOP_LAG_OFFSET 2279 +/*! SW_GROUP2_4_DOP_FLOW_INDEX. */ +#define BCMPKT_TRACE_DOP_SW_GROUP2_4_DOP_FLOW_INDEX 2280 +/*! SW_GROUP3_DOP_AND_PBM. */ +#define BCMPKT_TRACE_DOP_SW_GROUP3_DOP_AND_PBM 2281 +/*! SW_GROUP4_DOP_CPU_COS_MAP_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_SW_GROUP4_DOP_CPU_COS_MAP_TCAM_KEY 2282 +/*! SW_GROUP5_1_DOP_CPU_COS_MAP_TCAM_HIT. */ +#define BCMPKT_TRACE_DOP_SW_GROUP5_1_DOP_CPU_COS_MAP_TCAM_HIT 2283 +/*! SW_GROUP5_1_DOP_CPU_COS_MAP_TCAM_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_SW_GROUP5_1_DOP_CPU_COS_MAP_TCAM_HIT_INDEX 2284 +/*! SW_GROUP5_2_DOP_ING_COUNTER_UPDATE_VECTOR. */ +#define BCMPKT_TRACE_DOP_SW_GROUP5_2_DOP_ING_COUNTER_UPDATE_VECTOR 2285 +/*! SW_GROUP5_3_DOP_CNG. */ +#define BCMPKT_TRACE_DOP_SW_GROUP5_3_DOP_CNG 2286 +/*! SW_GROUP5_3_DOP_COPY_TO_CPU. */ +#define BCMPKT_TRACE_DOP_SW_GROUP5_3_DOP_COPY_TO_CPU 2287 +/*! SW_GROUP5_3_DOP_TUNNEL_DECAP_TYPE. */ +#define BCMPKT_TRACE_DOP_SW_GROUP5_3_DOP_TUNNEL_DECAP_TYPE 2288 +/*! SW_GROUP5_3_DOP_INT_PRI. */ +#define BCMPKT_TRACE_DOP_SW_GROUP5_3_DOP_INT_PRI 2289 +/*! SW_GROUP5_3_DOP_PRESERVE_DOT1P. */ +#define BCMPKT_TRACE_DOP_SW_GROUP5_3_DOP_PRESERVE_DOT1P 2290 +/*! SW_GROUP5_3_DOP_DEST_PORT. */ +#define BCMPKT_TRACE_DOP_SW_GROUP5_3_DOP_DEST_PORT 2291 +/*! SW_GROUP6_1_DOP_L3_PBM. */ +#define BCMPKT_TRACE_DOP_SW_GROUP6_1_DOP_L3_PBM 2292 +/*! SW_GROUP6_1_DOP_L2_PBM. */ +#define BCMPKT_TRACE_DOP_SW_GROUP6_1_DOP_L2_PBM 2293 +/*! SW_GROUP6_2_DOP_CHANGE_ECN. */ +#define BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_CHANGE_ECN 2294 +/*! SW_GROUP6_2_DOP_EMIRROR. */ +#define BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_EMIRROR 2295 +/*! SW_GROUP6_2_DOP_MIRROR. */ +#define BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_MIRROR 2296 +/*! SW_GROUP6_2_DOP_UC_QUEUE_VALID. */ +#define BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_UC_QUEUE_VALID 2297 +/*! SW_GROUP6_2_DOP_ING_OTAG_ACTION. */ +#define BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_ING_OTAG_ACTION 2298 +/*! SW_GROUP6_2_DOP_ECN. */ +#define BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_ECN 2299 +/*! SW_GROUP6_2_DOP_ENTROPY. */ +#define BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_ENTROPY 2300 +/*! SW_GROUP6_2_DOP_MIRR3. */ +#define BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_MIRR3 2301 +/*! SW_GROUP6_2_DOP_MIRR2. */ +#define BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_MIRR2 2302 +/*! SW_GROUP6_2_DOP_MIRR1. */ +#define BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_MIRR1 2303 +/*! SW_GROUP6_2_DOP_MIRR0. */ +#define BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_MIRR0 2304 +/*! UDF_COND_TCAM_DOP_UDF_COND_TCAM_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_UDF_COND_TCAM_DOP_UDF_COND_TCAM_HIT_INDEX 2305 +/*! UDF_COND_TCAM_DOP_UDF_COND_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_UDF_COND_TCAM_DOP_UDF_COND_TCAM_KEY 2306 +/*! UDF_COND_TCAM_DOP_UDF_COND_TCAM_HIT. */ +#define BCMPKT_TRACE_DOP_UDF_COND_TCAM_DOP_UDF_COND_TCAM_HIT 2307 +/*! VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_0_B. */ +#define BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_0_B 2308 +/*! VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_0_A. */ +#define BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_0_A 2309 +/*! VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_2_A. */ +#define BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_2_A 2310 +/*! VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_2_B. */ +#define BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_2_B 2311 +/*! VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_1_B. */ +#define BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_1_B 2312 +/*! VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_1_A. */ +#define BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_1_A 2313 +/*! VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_3_A. */ +#define BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_3_A 2314 +/*! VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_3_B. */ +#define BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_3_B 2315 +/*! VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_0. */ +#define BCMPKT_TRACE_DOP_VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_0 2316 +/*! VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_1. */ +#define BCMPKT_TRACE_DOP_VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_1 2317 +/*! VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_2. */ +#define BCMPKT_TRACE_DOP_VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_2 2318 +/*! VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_0. */ +#define BCMPKT_TRACE_DOP_VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_0 2319 +/*! VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_3. */ +#define BCMPKT_TRACE_DOP_VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_3 2320 +/*! LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP_EGR_INCA_OPCODE_MAP_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP_EGR_INCA_OPCODE_MAP_TCAM_KEY 2321 +/*! LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP_EGR_INCA_OPCODE_MAP_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP_EGR_INCA_OPCODE_MAP_TCAM_MATCH_INDEX 2322 +/*! LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP_EGR_INCA_OPCODE_MAP_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP_EGR_INCA_OPCODE_MAP_TCAM_TCAM_MATCH 2323 +/*! LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_KEY 2324 +/*! LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_MATCH_INDEX 2325 +/*! LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_TCAM_MATCH 2326 +/*! LPP_EPARS_EGR_PP_PORT_DOP_EGR_PP_PORT_NUM_SOP. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EGR_PP_PORT_DOP_EGR_PP_PORT_NUM_SOP 2327 +/*! LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_DQP. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_DQP 2328 +/*! LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_INTERNAL_QP_ID. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_INTERNAL_QP_ID 2329 +/*! LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_OPCODE. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_OPCODE 2330 +/*! LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_PSN. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_PSN 2331 +/*! LPP_EPARS_EPARS_INCA_DOP_INCA_PSN_UPDATE_ENABLE. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_INCA_DOP_INCA_PSN_UPDATE_ENABLE 2332 +/*! LPP_EPARS_EPARS_INCA_DOP_INCA_UPDATE_OPCODE_ENABLE. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_INCA_DOP_INCA_UPDATE_OPCODE_ENABLE 2333 +/*! LPP_EPARS_EPARS_MATCH_ID_DOP_EPARS_MATCH_ID. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_MATCH_ID_DOP_EPARS_MATCH_ID 2334 +/*! LPP_EPARS_EPARS_TS_1588_DOP_EPARS_MSG_TYPE_1588. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_TS_1588_DOP_EPARS_MSG_TYPE_1588 2335 +/*! LPP_EPARS_EPARS_TS_1588_DOP_EPARS_TS_1588_PKT. */ +#define BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_TS_1588_DOP_EPARS_TS_1588_PKT 2336 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_ADD_OUTER_VLAN. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_ADD_OUTER_VLAN 2337 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_ADD_RX_MD_HDR. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_ADD_RX_MD_HDR 2338 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_CORRECTION_FIELD_UPDATED_1588. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_CORRECTION_FIELD_UPDATED_1588 2339 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_DELETE_OUTER_VLAN. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_DELETE_OUTER_VLAN 2340 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_EDITED_PKT_LENGTH. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_EDITED_PKT_LENGTH 2341 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_IFA_ACTION. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_IFA_ACTION 2342 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_IFA_MD_HDR_INSERTED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_IFA_MD_HDR_INSERTED 2343 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_INCA_INSERT_ROCEV2_RETH_HDR. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INCA_INSERT_ROCEV2_RETH_HDR 2344 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_INCA_ROCEV2_HDR_DELETED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INCA_ROCEV2_HDR_DELETED 2345 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_INCA_UPDATE_ROCEV2_RETH_HDR. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INCA_UPDATE_ROCEV2_RETH_HDR 2346 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_DCN_METADATA_UPDATED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_DCN_METADATA_UPDATED 2347 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_DIP_CHANGED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_DIP_CHANGED 2348 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_MACDA_CHANGED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_MACDA_CHANGED 2349 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_MACSA_CHANGED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_MACSA_CHANGED 2350 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_PAYLOAD_LENGTH_CHANGED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_PAYLOAD_LENGTH_CHANGED 2351 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_SIP_CHANGED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_SIP_CHANGED 2352 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_TOS_CHANGED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_TOS_CHANGED 2353 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_TTL_CHANGED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_TTL_CHANGED 2354 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_L2_INSTR_LOCATOR_METADATA_UPDATED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_L2_INSTR_LOCATOR_METADATA_UPDATED 2355 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_L2_INSTR_PERFORMANCE_METRICS_UPDATED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_L2_INSTR_PERFORMANCE_METRICS_UPDATED 2356 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_L2_INSTR_PKT_EDIT_ACTION. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_L2_INSTR_PKT_EDIT_ACTION 2357 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_REPLACE_OUTER_VLAN. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_REPLACE_OUTER_VLAN 2358 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP_UDP_CHECKSUM_UPDATED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_UDP_CHECKSUM_UPDATED 2359 +/*! LPP_EPMOD_EGR_COUNTERS_DOP_EGR_SOBMH_COUNTER. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_EGR_SOBMH_COUNTER 2360 +/*! LPP_EPMOD_EGR_COUNTERS_DOP_PRIORITY_VAL. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_PRIORITY_VAL 2361 +/*! LPP_EPMOD_EGR_COUNTERS_DOP_TDBGC. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TDBGC 2362 +/*! LPP_EPMOD_EGR_COUNTERS_DOP_TX_PARITY_ERROR_DROP. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_PARITY_ERROR_DROP 2363 +/*! LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS 2364 +/*! LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_IPV4. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_IPV4 2365 +/*! LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_IPV6. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_IPV6 2366 +/*! LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE 2367 +/*! LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE_ECN_MARKED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE_ECN_MARKED 2368 +/*! LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE_RED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE_RED 2369 +/*! LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE_YELLOW. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE_YELLOW 2370 +/*! LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_RED. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_RED 2371 +/*! LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_YELLOW. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_YELLOW 2372 +/*! LPP_EPMOD_EGR_EVENT_VECTOR_DOP_EGR_EVENT_VECTOR. */ +#define BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_EVENT_VECTOR_DOP_EGR_EVENT_VECTOR 2373 +/*! LPP_IFWD_ALPM_FXT_HASH_OUT_GEN_DOP_HASH_VAL. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_FXT_HASH_OUT_GEN_DOP_HASH_VAL 2374 +/*! LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY 2375 +/*! LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_PKT_RD 2376 +/*! LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_MATCH_INDEX 2377 +/*! LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_TCAM_MATCH 2378 +/*! LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY 2379 +/*! LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_PKT_RD 2380 +/*! LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_MATCH_INDEX 2381 +/*! LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_TCAM_MATCH 2382 +/*! LPP_IFWD_ALPM_LEVEL2_HIT_INFO_DOP_HIT_0. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_LEVEL2_HIT_INFO_DOP_HIT_0 2383 +/*! LPP_IFWD_ALPM_LEVEL2_HIT_INFO_DOP_HIT_0_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_LEVEL2_HIT_INFO_DOP_HIT_0_INDEX 2384 +/*! LPP_IFWD_ALPM_LPM_KEY_GEN_CONTROLS_DOP_ELIGIBLE_FOR_L3_LOOKUP. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_LPM_KEY_GEN_CONTROLS_DOP_ELIGIBLE_FOR_L3_LOOKUP 2385 +/*! LPP_IFWD_ALPM_LPM_KEY_GEN_CONTROLS_DOP_VRF. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_LPM_KEY_GEN_CONTROLS_DOP_VRF 2386 +/*! LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_FORWARDING_PROFILE. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_FORWARDING_PROFILE 2387 +/*! LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_OUTGOING_VLAN_PROFILE. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_OUTGOING_VLAN_PROFILE 2388 +/*! LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_AR_DESTINATION. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_AR_DESTINATION 2389 +/*! LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_AR_DESTINATION_VALID. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_AR_DESTINATION_VALID 2390 +/*! LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_DEFAULT_DESTINATION. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_DEFAULT_DESTINATION 2391 +/*! LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_DEFAULT_DESTINATION_TYPE. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_DEFAULT_DESTINATION_TYPE 2392 +/*! LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_DEFAULT_DESTINATION_VALID. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_DEFAULT_DESTINATION_VALID 2393 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_KEY 2394 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_MATCH_INDEX 2395 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_PKT_RD 2396 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_TCAM_MATCH 2397 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_KEY 2398 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_MATCH_INDEX 2399 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_PKT_RD 2400 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_TCAM_MATCH 2401 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_KEY 2402 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_MATCH_INDEX 2403 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_PKT_RD 2404 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_TCAM_MATCH 2405 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_KEY 2406 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_MATCH_INDEX 2407 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_PKT_RD 2408 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_TCAM_MATCH 2409 +/*! LPP_IPARS_FINAL_VRF_DOP_FINAL_VRF. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_FINAL_VRF_DOP_FINAL_VRF 2410 +/*! LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP_ING_LOCAL_INCA_COLLECTIVE_MAP_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP_ING_LOCAL_INCA_COLLECTIVE_MAP_TCAM_KEY 2411 +/*! LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP_ING_LOCAL_INCA_COLLECTIVE_MAP_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP_ING_LOCAL_INCA_COLLECTIVE_MAP_TCAM_MATCH_INDEX 2412 +/*! LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP_ING_LOCAL_INCA_COLLECTIVE_MAP_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP_ING_LOCAL_INCA_COLLECTIVE_MAP_TCAM_TCAM_MATCH 2413 +/*! LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP_ING_INCA_OPCODE_MAP_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP_ING_INCA_OPCODE_MAP_TCAM_KEY 2414 +/*! LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP_ING_INCA_OPCODE_MAP_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP_ING_INCA_OPCODE_MAP_TCAM_MATCH_INDEX 2415 +/*! LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP_ING_INCA_OPCODE_MAP_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP_ING_INCA_OPCODE_MAP_TCAM_TCAM_MATCH 2416 +/*! LPP_IPARS_IPARS_MAPPED_DSCP_DOP_IPARS_MAPPED_DSCP. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_IPARS_MAPPED_DSCP_DOP_IPARS_MAPPED_DSCP 2417 +/*! LPP_IPARS_LPP_IPAD_BUS_DOP_LPP_IPAD_BUS. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_LPP_IPAD_BUS_DOP_LPP_IPAD_BUS 2418 +/*! LPP_IPARS_MATCH_ID_DOP_BUS_MATCH_ID. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_MATCH_ID_DOP_BUS_MATCH_ID 2419 +/*! LPP_IPARS_MY_STATION_HIT_DOP_MY_STATION_HIT. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_MY_STATION_HIT_DOP_MY_STATION_HIT 2420 +/*! LPP_IPARS_UDF_TCAM_DOP_UDF_TCAM_TCAM_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_UDF_TCAM_DOP_UDF_TCAM_TCAM_HIT_INDEX 2421 +/*! LPP_IPARS_UDF_TCAM_DOP_UDF_TCAM_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_UDF_TCAM_DOP_UDF_TCAM_TCAM_KEY 2422 +/*! LPP_IPARS_UDF_TCAM_DOP_UDF_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_UDF_TCAM_DOP_UDF_TCAM_TCAM_MATCH 2423 +/*! LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP_VLAN_TO_VRF_MAPPING_TCAM_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP_VLAN_TO_VRF_MAPPING_TCAM_KEY 2424 +/*! LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP_VLAN_TO_VRF_MAPPING_TCAM_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP_VLAN_TO_VRF_MAPPING_TCAM_MATCH_INDEX 2425 +/*! LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP_VLAN_TO_VRF_MAPPING_TCAM_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP_VLAN_TO_VRF_MAPPING_TCAM_TCAM_MATCH 2426 +/*! LPP_IRSEL_AR_AR_INFO_DOP_AR_GROUP. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_AR_AR_INFO_DOP_AR_GROUP 2427 +/*! LPP_IRSEL_AR_AR_INFO_DOP_AR_RESOLUTION_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_AR_AR_INFO_DOP_AR_RESOLUTION_INDEX 2428 +/*! LPP_IRSEL_AR_AR_INFO_DOP_FLOWSET_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_AR_AR_INFO_DOP_FLOWSET_INDEX 2429 +/*! LPP_IRSEL_AR_AR_INFO_DOP_INGRESS_VC. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_AR_AR_INFO_DOP_INGRESS_VC 2430 +/*! LPP_IRSEL_AR_AR_INFO_DOP_TIMESTAMP. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_AR_AR_INFO_DOP_TIMESTAMP 2431 +/*! LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_AR_DR_FLAG. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_AR_DR_FLAG 2432 +/*! LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_ASSIGNED_MIRROR. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_ASSIGNED_MIRROR 2433 +/*! LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_CHOICE_TYPE. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_CHOICE_TYPE 2434 +/*! LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_COPY_TO_CPU. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_COPY_TO_CPU 2435 +/*! LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_DROP. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_DROP 2436 +/*! LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_DR_SELECTION. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_DR_SELECTION 2437 +/*! LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_DR_VSELECT. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_DR_VSELECT 2438 +/*! LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_EGRESS_PORT. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_EGRESS_PORT 2439 +/*! LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_EGRESS_PORT_VALID. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_EGRESS_PORT_VALID 2440 +/*! LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_EGRESS_VC. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_EGRESS_VC 2441 +/*! LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_MIRROR. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_MIRROR 2442 +/*! LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_VMAP_PRI_VC. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_VMAP_PRI_VC 2443 +/*! LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_PORT. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_PORT 2444 +/*! LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_PORT_VALID. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_PORT_VALID 2445 +/*! LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_TGID. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_TGID 2446 +/*! LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_TGID_VALID. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_TGID_VALID 2447 +/*! LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_DR_PORT_LINK_DOWN. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_DR_PORT_LINK_DOWN 2448 +/*! LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_DR_SAME_PORT_CHECK_FAIL. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_DR_SAME_PORT_CHECK_FAIL 2449 +/*! LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_PORT_PROTECTION_ENABLE. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_PORT_PROTECTION_ENABLE 2450 +/*! LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_SAME_PORT_PROT_ENABLE. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_SAME_PORT_PROT_ENABLE 2451 +/*! LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP_DR_NEXT_HOP. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP_DR_NEXT_HOP 2452 +/*! LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP_DR_NEXT_HOP_VALID. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP_DR_NEXT_HOP_VALID 2453 +/*! LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP_ECMP_MEMBER_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP_ECMP_MEMBER_INDEX 2454 +/*! LPP_IRSEL_RSEL_EGRESS_PORT_INFO_DOP_AR_PATH_CHOICE. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_EGRESS_PORT_INFO_DOP_AR_PATH_CHOICE 2455 +/*! LPP_IRSEL_RSEL_EGRESS_PORT_INFO_DOP_EGRESS_VC. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_EGRESS_PORT_INFO_DOP_EGRESS_VC 2456 +/*! LPP_IRSEL_RSEL_METER_INFO_DOP_METER_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_METER_INFO_DOP_METER_INDEX 2457 +/*! LPP_IRSEL_RSEL_METER_INFO_DOP_METER_UPDATE_BITMAP. */ +#define BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_METER_INFO_DOP_METER_UPDATE_BITMAP 2458 +/*! LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP_AUX_COPY_COS_PORT_MAP_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP_AUX_COPY_COS_PORT_MAP_KEY 2459 +/*! LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP_AUX_COPY_COS_PORT_MAP_MATCH_OUT. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP_AUX_COPY_COS_PORT_MAP_MATCH_OUT 2460 +/*! LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP_AUX_COPY_COS_PORT_MAP_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP_AUX_COPY_COS_PORT_MAP_TCAM_MATCH 2461 +/*! LPP_ISW_IFA_MIRROR_DOP_CBFCPKT. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_CBFCPKT 2462 +/*! LPP_ISW_IFA_MIRROR_DOP_IFA_ACTION. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_IFA_ACTION 2463 +/*! LPP_ISW_IFA_MIRROR_DOP_IFA_MD_FORMAT. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_IFA_MD_FORMAT 2464 +/*! LPP_ISW_IFA_MIRROR_DOP_LLR_LOSSLESS_PKT. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_LLR_LOSSLESS_PKT 2465 +/*! LPP_ISW_IFA_MIRROR_DOP_PORT_IS_AUX. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_PORT_IS_AUX 2466 +/*! LPP_ISW_IFA_MIRROR_DOP_SFLOW_ING_FLEX_MIRROR_ENABLE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_SFLOW_ING_FLEX_MIRROR_ENABLE 2467 +/*! LPP_ISW_IFA_MIRROR_DOP_SFLOW_ING_MIRROR_ENABLE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_SFLOW_ING_MIRROR_ENABLE 2468 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_FP_COUNTER. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_FP_COUNTER 2469 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_INCA_ICRCTR. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_INCA_ICRCTR 2470 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_INCA_MSG_CTR. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_INCA_MSG_CTR 2471 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_ING_VLAN_FILTER_DROP. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_ING_VLAN_FILTER_DROP 2472 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_PARITY_ERROR_DROP. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_PARITY_ERROR_DROP 2473 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_PORT_STATS_IN. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_PORT_STATS_IN 2474 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_PRIORITY_VAL. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_PRIORITY_VAL 2475 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_RDBGC. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RDBGC 2476 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_DISCARD. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_DISCARD 2477 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_DISCARD_IPV4. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_DISCARD_IPV4 2478 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_DISCARD_IPV6. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_DISCARD_IPV6 2479 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_INT_PRI_OR_COS_DISCARD. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_INT_PRI_OR_COS_DISCARD 2480 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_IN_IPV4. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_IN_IPV4 2481 +/*! LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_IN_IPV6. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_IN_IPV6 2482 +/*! LPP_ISW_MISC_2_DOP_CHANGE_DSCP. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_CHANGE_DSCP 2483 +/*! LPP_ISW_MISC_2_DOP_CNG. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_CNG 2484 +/*! LPP_ISW_MISC_2_DOP_CNP_ELIGIBLE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_CNP_ELIGIBLE 2485 +/*! LPP_ISW_MISC_2_DOP_DCN_ELIGIBLE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_DCN_ELIGIBLE 2486 +/*! LPP_ISW_MISC_2_DOP_FINAL_OUTGOING_DSCP. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_FINAL_OUTGOING_DSCP 2487 +/*! LPP_ISW_MISC_2_DOP_FP_CHANGE_ECN. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_FP_CHANGE_ECN 2488 +/*! LPP_ISW_MISC_2_DOP_FP_NEW_ECN. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_FP_NEW_ECN 2489 +/*! LPP_ISW_MISC_2_DOP_HIGHEST_PRIORITY_DROP_REASON. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_HIGHEST_PRIORITY_DROP_REASON 2490 +/*! LPP_ISW_MISC_2_DOP_ING_EVENT_VECTOR. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_ING_EVENT_VECTOR 2491 +/*! LPP_ISW_MISC_2_DOP_INT_CN. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_INT_CN 2492 +/*! LPP_ISW_MISC_2_DOP_INT_PRI. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_INT_PRI 2493 +/*! LPP_ISW_MISC_2_DOP_PRESERVE_DSCP. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_PRESERVE_DSCP 2494 +/*! LPP_ISW_MISC_DOP_COPY_TO_CPU_OPCODE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_COPY_TO_CPU_OPCODE 2495 +/*! LPP_ISW_MISC_DOP_ENTROPY_HASH. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_ENTROPY_HASH 2496 +/*! LPP_ISW_MISC_DOP_FORWARDING_PROFILE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_FORWARDING_PROFILE 2497 +/*! LPP_ISW_MISC_DOP_MIRROR. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_MIRROR 2498 +/*! LPP_ISW_MISC_DOP_OUTGOING_VLAN_PROFILE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_OUTGOING_VLAN_PROFILE 2499 +/*! LPP_ISW_MISC_DOP_TRUNK_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_TRUNK_INDEX 2500 +/*! LPP_ISW_MISC_DOP_VPP_AUX_COPY_BITMAP. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_VPP_AUX_COPY_BITMAP 2501 +/*! LPP_ISW_MISC_DOP_VPP_SW_COPY_REASON_CODE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_VPP_SW_COPY_REASON_CODE 2502 +/*! LPP_ISW_NEXT_HOP_DOP_AR_PORT_TO_NHOP_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_AR_PORT_TO_NHOP_INDEX 2503 +/*! LPP_ISW_NEXT_HOP_DOP_FINAL_NEXT_HOP. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_FINAL_NEXT_HOP 2504 +/*! LPP_ISW_NEXT_HOP_DOP_FINAL_NEXT_HOP_VALID. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_FINAL_NEXT_HOP_VALID 2505 +/*! LPP_ISW_NEXT_HOP_DOP_INCA_FLOW_TYPE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_INCA_FLOW_TYPE 2506 +/*! LPP_ISW_NEXT_HOP_DOP_L2_INSTR_RESOLVED_ACTION_PROFILE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_L2_INSTR_RESOLVED_ACTION_PROFILE 2507 +/*! LPP_ISW_NEXT_HOP_DOP_MOD_MMU_ELIGIBLE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_MOD_MMU_ELIGIBLE 2508 +/*! LPP_ISW_NEXT_HOP_DOP_MOD_MMU_PROFILE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_MOD_MMU_PROFILE 2509 +/*! LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_DEST_PORT. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_DEST_PORT 2510 +/*! LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_PROFILE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_PROFILE 2511 +/*! LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_QUEUE_NUM. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_QUEUE_NUM 2512 +/*! LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_TRUNCATE_ENABLE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_TRUNCATE_ENABLE 2513 +/*! LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_VALID. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_VALID 2514 +/*! LPP_ISW_PROTOCOL_TCAM_DOP_PROTOCOL_TCAM_HIT_INDEX. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_PROTOCOL_TCAM_DOP_PROTOCOL_TCAM_HIT_INDEX 2515 +/*! LPP_ISW_PROTOCOL_TCAM_DOP_PROTOCOL_TCAM_KEY_INT. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_PROTOCOL_TCAM_DOP_PROTOCOL_TCAM_KEY_INT 2516 +/*! LPP_ISW_PROTOCOL_TCAM_DOP_PROTOCOL_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_PROTOCOL_TCAM_DOP_PROTOCOL_TCAM_MATCH 2517 +/*! LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP_SW_COPY_COS_PORT_MAP_KEY. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP_SW_COPY_COS_PORT_MAP_KEY 2518 +/*! LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP_SW_COPY_COS_PORT_MAP_MATCH_OUT. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP_SW_COPY_COS_PORT_MAP_MATCH_OUT 2519 +/*! LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP_SW_COPY_COS_PORT_MAP_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP_SW_COPY_COS_PORT_MAP_TCAM_MATCH 2520 +/*! LPP_ISW_SW_COPY_DOP_SW_COPY_DEST_PORT. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_DOP_SW_COPY_DEST_PORT 2521 +/*! LPP_ISW_SW_COPY_DOP_SW_COPY_QUEUE_NUM. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_DOP_SW_COPY_QUEUE_NUM 2522 +/*! LPP_ISW_SW_COPY_DOP_SW_COPY_TYPE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_DOP_SW_COPY_TYPE 2523 +/*! LPP_ISW_SW_COPY_DOP_SW_COPY_VALID. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_DOP_SW_COPY_VALID 2524 +/*! LPP_ISW_SW_COPY_DOP_UNMOD_PKT_TYPE. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_DOP_UNMOD_PKT_TYPE 2525 +/*! LPP_ISW_SW_COPY_DOP_UNMOD_PKT_VALID. */ +#define BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_DOP_UNMOD_PKT_VALID 2526 +/*! MEMDB_TCAM_LPP_IFP_MEM0_0_KEY_DOP_MEM0_0_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_0_KEY_DOP_MEM0_0_KEY 2527 +/*! MEMDB_TCAM_LPP_IFP_MEM0_0_KEY_DOP_MEM0_0_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_0_KEY_DOP_MEM0_0_PKT_RD 2528 +/*! MEMDB_TCAM_LPP_IFP_MEM0_1_KEY_DOP_MEM0_1_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_1_KEY_DOP_MEM0_1_KEY 2529 +/*! MEMDB_TCAM_LPP_IFP_MEM0_1_KEY_DOP_MEM0_1_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_1_KEY_DOP_MEM0_1_PKT_RD 2530 +/*! MEMDB_TCAM_LPP_IFP_MEM0_2_KEY_DOP_MEM0_2_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_2_KEY_DOP_MEM0_2_KEY 2531 +/*! MEMDB_TCAM_LPP_IFP_MEM0_2_KEY_DOP_MEM0_2_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_2_KEY_DOP_MEM0_2_PKT_RD 2532 +/*! MEMDB_TCAM_LPP_IFP_MEM0_3_KEY_DOP_MEM0_3_KEY. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_3_KEY_DOP_MEM0_3_KEY 2533 +/*! MEMDB_TCAM_LPP_IFP_MEM0_3_KEY_DOP_MEM0_3_PKT_RD. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_3_KEY_DOP_MEM0_3_PKT_RD 2534 +/*! MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX 2535 +/*! MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH 2536 +/*! MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX 2537 +/*! MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH 2538 +/*! MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX 2539 +/*! MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH 2540 +/*! MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX 2541 +/*! MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH. */ +#define BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH 2542 +/*! TRACE_DOP FIELD ID NUMBER */ +#define BCMPKT_TRACE_DOP_FID_COUNT 2543 +/*! \} */ + +/*! TRACE_DOP field name strings for debugging. */ +#define BCMPKT_TRACE_DOP_FIELD_NAME_MAP_INIT \ + {"IPARSER0_HME_STAGE0_DOP_STAGE0_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER0_HME_STAGE0_DOP_STAGE0_HFE_PROFILE_PTR},\ + {"IPARSER0_HME_STAGE0_DOP_STAGE0_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER0_HME_STAGE0_DOP_STAGE0_TCAM_TCAM_MATCH},\ + {"IPARSER0_HME_STAGE0_DOP_STAGE0_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER0_HME_STAGE0_DOP_STAGE0_SHIFT_AMOUNT},\ + {"IPARSER0_HME_STAGE0_DOP_STAGE0_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER0_HME_STAGE0_DOP_STAGE0_PKT_DATA},\ + {"MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR},\ + {"MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_RD},\ + {"MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR},\ + {"MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_RD},\ + {"IFTA10_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA10_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA10_I1T_00_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA10_I1T_00_INDEX_DOP_LKP0_LTPR_WIN},\ + {"MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR},\ + {"MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_RD},\ + {"MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR},\ + {"MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_RD},\ + {"IFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA20_I1T_00_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA20_I1T_00_INDEX_DOP_LKP0_LTPR_WIN},\ + {"IPARSER1_HME_STAGE0_DOP_STAGE0_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE0_DOP_STAGE0_HFE_PROFILE_PTR},\ + {"IPARSER1_HME_STAGE0_DOP_STAGE0_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE0_DOP_STAGE0_TCAM_TCAM_MATCH},\ + {"IPARSER1_HME_STAGE0_DOP_STAGE0_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE0_DOP_STAGE0_SHIFT_AMOUNT},\ + {"IPARSER1_HME_STAGE0_DOP_STAGE0_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE0_DOP_STAGE0_PKT_DATA},\ + {"IPARSER1_HME_STAGE1_DOP_STAGE1_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE1_DOP_STAGE1_HFE_PROFILE_PTR},\ + {"IPARSER1_HME_STAGE1_DOP_STAGE1_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE1_DOP_STAGE1_TCAM_TCAM_MATCH},\ + {"IPARSER1_HME_STAGE1_DOP_STAGE1_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE1_DOP_STAGE1_SHIFT_AMOUNT},\ + {"IPARSER1_HME_STAGE1_DOP_STAGE1_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE1_DOP_STAGE1_PKT_DATA},\ + {"IPARSER1_HME_STAGE2_DOP_STAGE2_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE2_DOP_STAGE2_HFE_PROFILE_PTR},\ + {"IPARSER1_HME_STAGE2_DOP_STAGE2_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE2_DOP_STAGE2_TCAM_TCAM_MATCH},\ + {"IPARSER1_HME_STAGE2_DOP_STAGE2_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE2_DOP_STAGE2_SHIFT_AMOUNT},\ + {"IPARSER1_HME_STAGE2_DOP_STAGE2_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE2_DOP_STAGE2_PKT_DATA},\ + {"IPARSER1_HME_STAGE3_DOP_STAGE3_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE3_DOP_STAGE3_HFE_PROFILE_PTR},\ + {"IPARSER1_HME_STAGE3_DOP_STAGE3_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE3_DOP_STAGE3_TCAM_TCAM_MATCH},\ + {"IPARSER1_HME_STAGE3_DOP_STAGE3_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE3_DOP_STAGE3_SHIFT_AMOUNT},\ + {"IPARSER1_HME_STAGE3_DOP_STAGE3_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE3_DOP_STAGE3_PKT_DATA},\ + {"IPARSER1_HME_STAGE4_DOP_STAGE4_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE4_DOP_STAGE4_HFE_PROFILE_PTR},\ + {"IPARSER1_HME_STAGE4_DOP_STAGE4_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE4_DOP_STAGE4_TCAM_TCAM_MATCH},\ + {"IPARSER1_HME_STAGE4_DOP_STAGE4_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE4_DOP_STAGE4_SHIFT_AMOUNT},\ + {"IPARSER1_HME_STAGE4_DOP_STAGE4_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE4_DOP_STAGE4_PKT_DATA},\ + {"IPARSER1_HME_STAGE5_DOP_STAGE5_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE5_DOP_STAGE5_HFE_PROFILE_PTR},\ + {"IPARSER1_HME_STAGE5_DOP_STAGE5_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE5_DOP_STAGE5_TCAM_TCAM_MATCH},\ + {"IPARSER1_HME_STAGE5_DOP_STAGE5_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE5_DOP_STAGE5_SHIFT_AMOUNT},\ + {"IPARSER1_HME_STAGE5_DOP_STAGE5_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE5_DOP_STAGE5_PKT_DATA},\ + {"IFTA30_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA30_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH},\ + {"IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH},\ + {"IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"MEMDB_TCAM_IFTA30_MEM0_1_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_1_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_TCAM_IFTA30_MEM0_1_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_1_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA30_MEM0_3_KEY_DOP_MEM0_3_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_3_KEY_DOP_MEM0_3_KEY},\ + {"MEMDB_TCAM_IFTA30_MEM0_3_KEY_DOP_MEM0_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_3_KEY_DOP_MEM0_3_PKT_RD},\ + {"MEMDB_TCAM_IFTA30_MEM0_2_KEY_DOP_MEM0_2_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_2_KEY_DOP_MEM0_2_KEY},\ + {"MEMDB_TCAM_IFTA30_MEM0_2_KEY_DOP_MEM0_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_2_KEY_DOP_MEM0_2_PKT_RD},\ + {"MEMDB_TCAM_IFTA30_MEM0_0_KEY_DOP_MEM0_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_0_KEY_DOP_MEM0_0_KEY},\ + {"MEMDB_TCAM_IFTA30_MEM0_0_KEY_DOP_MEM0_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_0_KEY_DOP_MEM0_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH},\ + {"IPARSER2_HME_STAGE0_DOP_STAGE0_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE0_DOP_STAGE0_HFE_PROFILE_PTR},\ + {"IPARSER2_HME_STAGE0_DOP_STAGE0_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE0_DOP_STAGE0_TCAM_TCAM_MATCH},\ + {"IPARSER2_HME_STAGE0_DOP_STAGE0_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE0_DOP_STAGE0_SHIFT_AMOUNT},\ + {"IPARSER2_HME_STAGE0_DOP_STAGE0_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE0_DOP_STAGE0_PKT_DATA},\ + {"IPARSER2_HME_STAGE1_DOP_STAGE1_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE1_DOP_STAGE1_HFE_PROFILE_PTR},\ + {"IPARSER2_HME_STAGE1_DOP_STAGE1_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE1_DOP_STAGE1_TCAM_TCAM_MATCH},\ + {"IPARSER2_HME_STAGE1_DOP_STAGE1_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE1_DOP_STAGE1_SHIFT_AMOUNT},\ + {"IPARSER2_HME_STAGE1_DOP_STAGE1_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE1_DOP_STAGE1_PKT_DATA},\ + {"IPARSER2_HME_STAGE2_DOP_STAGE2_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE2_DOP_STAGE2_HFE_PROFILE_PTR},\ + {"IPARSER2_HME_STAGE2_DOP_STAGE2_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE2_DOP_STAGE2_TCAM_TCAM_MATCH},\ + {"IPARSER2_HME_STAGE2_DOP_STAGE2_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE2_DOP_STAGE2_SHIFT_AMOUNT},\ + {"IPARSER2_HME_STAGE2_DOP_STAGE2_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE2_DOP_STAGE2_PKT_DATA},\ + {"IPARSER2_HME_STAGE3_DOP_STAGE3_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE3_DOP_STAGE3_HFE_PROFILE_PTR},\ + {"IPARSER2_HME_STAGE3_DOP_STAGE3_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE3_DOP_STAGE3_TCAM_TCAM_MATCH},\ + {"IPARSER2_HME_STAGE3_DOP_STAGE3_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE3_DOP_STAGE3_SHIFT_AMOUNT},\ + {"IPARSER2_HME_STAGE3_DOP_STAGE3_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE3_DOP_STAGE3_PKT_DATA},\ + {"IPARSER2_HME_STAGE4_DOP_STAGE4_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE4_DOP_STAGE4_HFE_PROFILE_PTR},\ + {"IPARSER2_HME_STAGE4_DOP_STAGE4_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE4_DOP_STAGE4_TCAM_TCAM_MATCH},\ + {"IPARSER2_HME_STAGE4_DOP_STAGE4_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE4_DOP_STAGE4_SHIFT_AMOUNT},\ + {"IPARSER2_HME_STAGE4_DOP_STAGE4_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE4_DOP_STAGE4_PKT_DATA},\ + {"IFTA40_E2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA40_E2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA40_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA40_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA40_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA40_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA40_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA40_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA40_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA40_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA40_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA40_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY},\ + {"IFTA40_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA40_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY},\ + {"IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX},\ + {"IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX},\ + {"IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"IFTA40_T4T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA40_T4T_01_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY},\ + {"IFTA40_T4T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA40_T4T_01_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY},\ + {"IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX},\ + {"IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX},\ + {"IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"IFTA40_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA40_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"IFTA40_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA40_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"MEMDB_TCAM_IFTA40_MEM0_3_KEY_DOP_MEM0_3_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_3_KEY_DOP_MEM0_3_KEY},\ + {"MEMDB_TCAM_IFTA40_MEM0_3_KEY_DOP_MEM0_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_3_KEY_DOP_MEM0_3_PKT_RD},\ + {"MEMDB_TCAM_IFTA40_MEM1_2_KEY_DOP_MEM1_2_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_2_KEY_DOP_MEM1_2_KEY},\ + {"MEMDB_TCAM_IFTA40_MEM1_2_KEY_DOP_MEM1_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_2_KEY_DOP_MEM1_2_PKT_RD},\ + {"MEMDB_TCAM_IFTA40_MEM0_2_KEY_DOP_MEM0_2_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_2_KEY_DOP_MEM0_2_KEY},\ + {"MEMDB_TCAM_IFTA40_MEM0_2_KEY_DOP_MEM0_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_2_KEY_DOP_MEM0_2_PKT_RD},\ + {"MEMDB_TCAM_IFTA40_MEM0_0_KEY_DOP_MEM0_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_0_KEY_DOP_MEM0_0_KEY},\ + {"MEMDB_TCAM_IFTA40_MEM0_0_KEY_DOP_MEM0_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_0_KEY_DOP_MEM0_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA40_MEM1_0_KEY_DOP_MEM1_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_0_KEY_DOP_MEM1_0_KEY},\ + {"MEMDB_TCAM_IFTA40_MEM1_0_KEY_DOP_MEM1_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_0_KEY_DOP_MEM1_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA40_MEM1_1_KEY_DOP_MEM1_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_1_KEY_DOP_MEM1_1_KEY},\ + {"MEMDB_TCAM_IFTA40_MEM1_1_KEY_DOP_MEM1_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_1_KEY_DOP_MEM1_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA40_MEM0_1_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_1_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_TCAM_IFTA40_MEM0_1_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_1_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA40_MEM1_3_KEY_DOP_MEM1_3_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_3_KEY_DOP_MEM1_3_KEY},\ + {"MEMDB_TCAM_IFTA40_MEM1_3_KEY_DOP_MEM1_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_3_KEY_DOP_MEM1_3_PKT_RD},\ + {"MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_2_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_2_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_3_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP_MEM1_3_TCAM_MATCH},\ + {"IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"IFTA50_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA50_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY", BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY},\ + {"IFTA50_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA50_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY", BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY},\ + {"IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX},\ + {"IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX},\ + {"IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"IFTA50_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA50_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA50_I1T_00_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA50_I1T_00_INDEX_DOP_LKP0_LTPR_WIN},\ + {"IFTA50_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA50_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA50_I1T_01_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA50_I1T_01_INDEX_DOP_LKP0_LTPR_WIN},\ + {"MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_KEY_DOP_TCAM_ONLY_KEY", BCMPKT_TRACE_DOP_MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_KEY_DOP_TCAM_ONLY_KEY},\ + {"MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_HIT_AND_INDEX_DOP_TCAM_ONLY_MATCH_INDEX", BCMPKT_TRACE_DOP_MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_HIT_AND_INDEX_DOP_TCAM_ONLY_MATCH_INDEX},\ + {"MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_HIT_AND_INDEX_DOP_TCAM_ONLY_TCAM_MATCH", BCMPKT_TRACE_DOP_MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_HIT_AND_INDEX_DOP_TCAM_ONLY_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA50_MEM0_1_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_1_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_TCAM_IFTA50_MEM0_1_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_1_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA50_MEM0_3_KEY_DOP_MEM0_3_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_3_KEY_DOP_MEM0_3_KEY},\ + {"MEMDB_TCAM_IFTA50_MEM0_3_KEY_DOP_MEM0_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_3_KEY_DOP_MEM0_3_PKT_RD},\ + {"MEMDB_TCAM_IFTA50_MEM0_2_KEY_DOP_MEM0_2_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_2_KEY_DOP_MEM0_2_KEY},\ + {"MEMDB_TCAM_IFTA50_MEM0_2_KEY_DOP_MEM0_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_2_KEY_DOP_MEM0_2_PKT_RD},\ + {"MEMDB_TCAM_IFTA50_MEM0_0_KEY_DOP_MEM0_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_0_KEY_DOP_MEM0_0_KEY},\ + {"MEMDB_TCAM_IFTA50_MEM0_0_KEY_DOP_MEM0_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_0_KEY_DOP_MEM0_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH},\ + {"MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR},\ + {"MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM0_PKT_RD},\ + {"MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR},\ + {"MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM1_PKT_RD},\ + {"MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR},\ + {"MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM2_PKT_RD},\ + {"MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR},\ + {"MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA50_MY_DOP_INDEX_DOP_MEM3_PKT_RD},\ + {"MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR},\ + {"MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM0_PKT_RD},\ + {"MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR},\ + {"MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM1_PKT_RD},\ + {"MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR},\ + {"MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM2_PKT_RD},\ + {"MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR},\ + {"MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM3_PKT_RD},\ + {"MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR},\ + {"MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM4_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM4_PKT_RD},\ + {"MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR},\ + {"MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM5_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA60_MY_DOP_INDEX_DOP_MEM5_PKT_RD},\ + {"IFTA60_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA60_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA60_I1T_00_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA60_I1T_00_INDEX_DOP_LKP0_LTPR_WIN},\ + {"IFTA60_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA60_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA60_I1T_01_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA60_I1T_01_INDEX_DOP_LKP0_LTPR_WIN},\ + {"IFTA60_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA60_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA60_I1T_02_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA60_I1T_02_INDEX_DOP_LKP0_LTPR_WIN},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"IFTA60_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA60_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"MEMDB_TCAM_IFTA60_MEM0_1_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_1_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_TCAM_IFTA60_MEM0_1_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_1_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_0_TCAM_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_0_TCAM_INDEX},\ + {"MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_1_TCAM_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_1_TCAM_INDEX},\ + {"MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_2_TCAM_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_2_TCAM_INDEX},\ + {"MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_3_TCAM_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_3_TCAM_INDEX},\ + {"MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_3_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_3_KEY},\ + {"MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP_MEM0_3_PKT_RD},\ + {"MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_0_KEY},\ + {"MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP_MEM0_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_2_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_2_KEY},\ + {"MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP_MEM0_2_PKT_RD},\ + {"FLEX_DIGEST_LKUP_FD_NET_LAYER_KEY_DOP_NET_LAYER_TCAM_0_KEY", BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_KEY_DOP_NET_LAYER_TCAM_0_KEY},\ + {"FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_0_MATCH_INDEX},\ + {"FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_1_MATCH_INDEX},\ + {"FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_2_MATCH_INDEX},\ + {"FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_0_TCAM_MATCH},\ + {"FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_1_TCAM_MATCH},\ + {"FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP_NET_LAYER_TCAM_2_TCAM_MATCH},\ + {"FLEX_DIGEST_NORM_FD_NORM_DOP_OUT_FD_NORM_FLD_BUS", BCMPKT_TRACE_DOP_FLEX_DIGEST_NORM_FD_NORM_DOP_OUT_FD_NORM_FLD_BUS},\ + {"FLEX_DIGEST_HASH_FD_HASH_DOP_OUT_ING_HASH_BUS", BCMPKT_TRACE_DOP_FLEX_DIGEST_HASH_FD_HASH_DOP_OUT_ING_HASH_BUS},\ + {"MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR},\ + {"MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM0_PKT_RD},\ + {"MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR},\ + {"MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM1_PKT_RD},\ + {"MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR},\ + {"MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM2_PKT_RD},\ + {"MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR},\ + {"MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA70_MY_DOP_INDEX_DOP_MEM3_PKT_RD},\ + {"IFTA70_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA70_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA70_I1T_00_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA70_I1T_00_INDEX_DOP_LKP0_LTPR_WIN},\ + {"IFTA70_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA70_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA70_I1T_01_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA70_I1T_01_INDEX_DOP_LKP0_LTPR_WIN},\ + {"IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IFSL70_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"IFTA80_E2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA80_E2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA80_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA80_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA80_E2T_03_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA80_E2T_03_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA80_E2T_02_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA80_E2T_02_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA80_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA80_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA80_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA80_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA80_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA80_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA80_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA80_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA80_T2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA80_T2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA80_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA80_T2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA80_T2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA80_T2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA80_T2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA80_T2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"FLEX_QOS_PHB_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_FLEX_QOS_PHB_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_MATCH_INDEX},\ + {"FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH},\ + {"FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA", BCMPKT_TRACE_DOP_FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA},\ + {"FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX", BCMPKT_TRACE_DOP_FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX},\ + {"FLEX_QOS_PHB2_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_FLEX_QOS_PHB2_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH},\ + {"FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA", BCMPKT_TRACE_DOP_FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA},\ + {"FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX", BCMPKT_TRACE_DOP_FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM2_0_KEY_DOP_MEM2_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_0_KEY_DOP_MEM2_0_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM2_0_KEY_DOP_MEM2_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_0_KEY_DOP_MEM2_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM1_0_KEY_DOP_MEM1_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_0_KEY_DOP_MEM1_0_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM1_0_KEY_DOP_MEM1_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_0_KEY_DOP_MEM1_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM7_1_KEY_DOP_MEM7_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_1_KEY_DOP_MEM7_1_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM7_1_KEY_DOP_MEM7_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_1_KEY_DOP_MEM7_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM6_0_KEY_DOP_MEM6_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_0_KEY_DOP_MEM6_0_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM6_0_KEY_DOP_MEM6_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_0_KEY_DOP_MEM6_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM5_0_KEY_DOP_MEM5_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_0_KEY_DOP_MEM5_0_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM5_0_KEY_DOP_MEM5_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_0_KEY_DOP_MEM5_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM2_1_KEY_DOP_MEM2_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_1_KEY_DOP_MEM2_1_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM2_1_KEY_DOP_MEM2_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_1_KEY_DOP_MEM2_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM5_1_KEY_DOP_MEM5_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_1_KEY_DOP_MEM5_1_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM5_1_KEY_DOP_MEM5_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_1_KEY_DOP_MEM5_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM0_0_KEY_DOP_MEM0_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_0_KEY_DOP_MEM0_0_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM0_0_KEY_DOP_MEM0_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_0_KEY_DOP_MEM0_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM6_1_KEY_DOP_MEM6_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_1_KEY_DOP_MEM6_1_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM6_1_KEY_DOP_MEM6_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_1_KEY_DOP_MEM6_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM1_1_KEY_DOP_MEM1_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_1_KEY_DOP_MEM1_1_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM1_1_KEY_DOP_MEM1_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_1_KEY_DOP_MEM1_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM4_0_KEY_DOP_MEM4_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_0_KEY_DOP_MEM4_0_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM4_0_KEY_DOP_MEM4_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_0_KEY_DOP_MEM4_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM3_1_KEY_DOP_MEM3_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_1_KEY_DOP_MEM3_1_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM3_1_KEY_DOP_MEM3_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_1_KEY_DOP_MEM3_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM0_1_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_1_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM0_1_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_1_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM4_1_KEY_DOP_MEM4_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_1_KEY_DOP_MEM4_1_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM4_1_KEY_DOP_MEM4_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_1_KEY_DOP_MEM4_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM7_0_KEY_DOP_MEM7_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_0_KEY_DOP_MEM7_0_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM7_0_KEY_DOP_MEM7_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_0_KEY_DOP_MEM7_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM3_0_KEY_DOP_MEM3_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_0_KEY_DOP_MEM3_0_KEY},\ + {"MEMDB_TCAM_IFTA80_MEM3_0_KEY_DOP_MEM3_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_0_KEY_DOP_MEM3_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP_MEM6_1_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP_MEM4_1_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP_MEM3_1_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP_MEM7_1_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP_MEM5_1_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP_MEM2_1_TCAM_MATCH},\ + {"IFTA90_E2T_03_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA90_E2T_03_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA90_E2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA90_E2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA90_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA90_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA90_E2T_02_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA90_E2T_02_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA90_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA90_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA90_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA90_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA90_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA90_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA90_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA90_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"FLEX_CTR_ST_ING0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0},\ + {"FLEX_CTR_ST_ING0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1},\ + {"FLEX_CTR_ST_ING0_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID},\ + {"FLEX_CTR_ST_ING0_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID},\ + {"FLEX_CTR_ST_ING0_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID},\ + {"FLEX_CTR_ST_ING0_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID},\ + {"FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B0},\ + {"FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B1},\ + {"FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B2},\ + {"FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_COUNTER_B3},\ + {"FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B0},\ + {"FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B1},\ + {"FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B2},\ + {"FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_B_DOP_BUS_COUNTER_B3},\ + {"FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0},\ + {"FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1},\ + {"FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2},\ + {"FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3},\ + {"FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0},\ + {"FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1},\ + {"FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2},\ + {"FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3},\ + {"FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A0},\ + {"FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A1},\ + {"FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A2},\ + {"FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_COUNTER_A3},\ + {"FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A0},\ + {"FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A1},\ + {"FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A2},\ + {"FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING0_COUNTER_A_DOP_BUS_COUNTER_A3},\ + {"IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IFSL90_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IFSL91_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"IFTA100_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA100_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY},\ + {"IFTA100_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA100_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY},\ + {"IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX},\ + {"IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX},\ + {"IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"IFTA100_T4T_02_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA100_T4T_02_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY},\ + {"IFTA100_T4T_02_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA100_T4T_02_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY},\ + {"IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX},\ + {"IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX},\ + {"IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"IFTA100_T4T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA100_T4T_01_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY},\ + {"IFTA100_T4T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA100_T4T_01_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY},\ + {"IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX},\ + {"IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX},\ + {"IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"IFTA100_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA100_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"IFTA100_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA100_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"IFTA100_T4T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA100_T4T_02_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA100_T4T_03_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM1_2_KEY_DOP_MEM1_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_2_KEY_DOP_MEM1_2_KEY},\ + {"MEMDB_IFTA100_MEM1_2_KEY_DOP_MEM1_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_2_KEY_DOP_MEM1_2_PKT_RD},\ + {"MEMDB_IFTA100_MEM0_2_KEY_DOP_MEM0_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_2_KEY_DOP_MEM0_2_KEY},\ + {"MEMDB_IFTA100_MEM0_2_KEY_DOP_MEM0_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_2_KEY_DOP_MEM0_2_PKT_RD},\ + {"MEMDB_IFTA100_MEM7_2_KEY_DOP_MEM7_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_2_KEY_DOP_MEM7_2_KEY},\ + {"MEMDB_IFTA100_MEM7_2_KEY_DOP_MEM7_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_2_KEY_DOP_MEM7_2_PKT_RD},\ + {"MEMDB_IFTA100_MEM8_2_KEY_DOP_MEM8_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_2_KEY_DOP_MEM8_2_KEY},\ + {"MEMDB_IFTA100_MEM8_2_KEY_DOP_MEM8_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_2_KEY_DOP_MEM8_2_PKT_RD},\ + {"MEMDB_IFTA100_MEM9_0_KEY_DOP_MEM9_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_0_KEY_DOP_MEM9_0_KEY},\ + {"MEMDB_IFTA100_MEM9_0_KEY_DOP_MEM9_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_0_KEY_DOP_MEM9_0_PKT_RD},\ + {"MEMDB_IFTA100_MEM11_3_KEY_DOP_MEM11_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_3_KEY_DOP_MEM11_3_KEY},\ + {"MEMDB_IFTA100_MEM11_3_KEY_DOP_MEM11_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_3_KEY_DOP_MEM11_3_PKT_RD},\ + {"MEMDB_IFTA100_MEM7_3_KEY_DOP_MEM7_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_3_KEY_DOP_MEM7_3_KEY},\ + {"MEMDB_IFTA100_MEM7_3_KEY_DOP_MEM7_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_3_KEY_DOP_MEM7_3_PKT_RD},\ + {"MEMDB_IFTA100_MEM8_0_KEY_DOP_MEM8_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_0_KEY_DOP_MEM8_0_KEY},\ + {"MEMDB_IFTA100_MEM8_0_KEY_DOP_MEM8_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_0_KEY_DOP_MEM8_0_PKT_RD},\ + {"MEMDB_IFTA100_MEM10_2_KEY_DOP_MEM10_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_2_KEY_DOP_MEM10_2_KEY},\ + {"MEMDB_IFTA100_MEM10_2_KEY_DOP_MEM10_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_2_KEY_DOP_MEM10_2_PKT_RD},\ + {"MEMDB_IFTA100_MEM5_0_KEY_DOP_MEM5_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_0_KEY_DOP_MEM5_0_KEY},\ + {"MEMDB_IFTA100_MEM5_0_KEY_DOP_MEM5_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_0_KEY_DOP_MEM5_0_PKT_RD},\ + {"MEMDB_IFTA100_MEM3_2_KEY_DOP_MEM3_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_2_KEY_DOP_MEM3_2_KEY},\ + {"MEMDB_IFTA100_MEM3_2_KEY_DOP_MEM3_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_2_KEY_DOP_MEM3_2_PKT_RD},\ + {"MEMDB_IFTA100_MEM8_3_KEY_DOP_MEM8_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_3_KEY_DOP_MEM8_3_KEY},\ + {"MEMDB_IFTA100_MEM8_3_KEY_DOP_MEM8_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_3_KEY_DOP_MEM8_3_PKT_RD},\ + {"MEMDB_IFTA100_MEM11_0_KEY_DOP_MEM11_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_0_KEY_DOP_MEM11_0_KEY},\ + {"MEMDB_IFTA100_MEM11_0_KEY_DOP_MEM11_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_0_KEY_DOP_MEM11_0_PKT_RD},\ + {"MEMDB_IFTA100_MEM2_1_KEY_DOP_MEM2_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_1_KEY_DOP_MEM2_1_KEY},\ + {"MEMDB_IFTA100_MEM2_1_KEY_DOP_MEM2_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_1_KEY_DOP_MEM2_1_PKT_RD},\ + {"MEMDB_IFTA100_MEM4_3_KEY_DOP_MEM4_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_3_KEY_DOP_MEM4_3_KEY},\ + {"MEMDB_IFTA100_MEM4_3_KEY_DOP_MEM4_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_3_KEY_DOP_MEM4_3_PKT_RD},\ + {"MEMDB_IFTA100_MEM4_2_KEY_DOP_MEM4_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_2_KEY_DOP_MEM4_2_KEY},\ + {"MEMDB_IFTA100_MEM4_2_KEY_DOP_MEM4_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_2_KEY_DOP_MEM4_2_PKT_RD},\ + {"MEMDB_IFTA100_MEM5_3_KEY_DOP_MEM5_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_3_KEY_DOP_MEM5_3_KEY},\ + {"MEMDB_IFTA100_MEM5_3_KEY_DOP_MEM5_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_3_KEY_DOP_MEM5_3_PKT_RD},\ + {"MEMDB_IFTA100_MEM10_1_KEY_DOP_MEM10_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_1_KEY_DOP_MEM10_1_KEY},\ + {"MEMDB_IFTA100_MEM10_1_KEY_DOP_MEM10_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_1_KEY_DOP_MEM10_1_PKT_RD},\ + {"MEMDB_IFTA100_MEM6_1_KEY_DOP_MEM6_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_1_KEY_DOP_MEM6_1_KEY},\ + {"MEMDB_IFTA100_MEM6_1_KEY_DOP_MEM6_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_1_KEY_DOP_MEM6_1_PKT_RD},\ + {"MEMDB_IFTA100_MEM10_3_KEY_DOP_MEM10_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_3_KEY_DOP_MEM10_3_KEY},\ + {"MEMDB_IFTA100_MEM10_3_KEY_DOP_MEM10_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_3_KEY_DOP_MEM10_3_PKT_RD},\ + {"MEMDB_IFTA100_MEM4_1_KEY_DOP_MEM4_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_1_KEY_DOP_MEM4_1_KEY},\ + {"MEMDB_IFTA100_MEM4_1_KEY_DOP_MEM4_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_1_KEY_DOP_MEM4_1_PKT_RD},\ + {"MEMDB_IFTA100_MEM9_2_KEY_DOP_MEM9_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_2_KEY_DOP_MEM9_2_KEY},\ + {"MEMDB_IFTA100_MEM9_2_KEY_DOP_MEM9_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_2_KEY_DOP_MEM9_2_PKT_RD},\ + {"MEMDB_IFTA100_MEM3_0_KEY_DOP_MEM3_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_0_KEY_DOP_MEM3_0_KEY},\ + {"MEMDB_IFTA100_MEM3_0_KEY_DOP_MEM3_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_0_KEY_DOP_MEM3_0_PKT_RD},\ + {"MEMDB_IFTA100_MEM2_0_KEY_DOP_MEM2_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_0_KEY_DOP_MEM2_0_KEY},\ + {"MEMDB_IFTA100_MEM2_0_KEY_DOP_MEM2_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_0_KEY_DOP_MEM2_0_PKT_RD},\ + {"MEMDB_IFTA100_MEM1_0_KEY_DOP_MEM1_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_0_KEY_DOP_MEM1_0_KEY},\ + {"MEMDB_IFTA100_MEM1_0_KEY_DOP_MEM1_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_0_KEY_DOP_MEM1_0_PKT_RD},\ + {"MEMDB_IFTA100_MEM11_1_KEY_DOP_MEM11_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_1_KEY_DOP_MEM11_1_KEY},\ + {"MEMDB_IFTA100_MEM11_1_KEY_DOP_MEM11_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_1_KEY_DOP_MEM11_1_PKT_RD},\ + {"MEMDB_IFTA100_MEM2_2_KEY_DOP_MEM2_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_2_KEY_DOP_MEM2_2_KEY},\ + {"MEMDB_IFTA100_MEM2_2_KEY_DOP_MEM2_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_2_KEY_DOP_MEM2_2_PKT_RD},\ + {"MEMDB_IFTA100_MEM8_1_KEY_DOP_MEM8_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_1_KEY_DOP_MEM8_1_KEY},\ + {"MEMDB_IFTA100_MEM8_1_KEY_DOP_MEM8_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_1_KEY_DOP_MEM8_1_PKT_RD},\ + {"MEMDB_IFTA100_MEM7_1_KEY_DOP_MEM7_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_1_KEY_DOP_MEM7_1_KEY},\ + {"MEMDB_IFTA100_MEM7_1_KEY_DOP_MEM7_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_1_KEY_DOP_MEM7_1_PKT_RD},\ + {"MEMDB_IFTA100_MEM9_3_KEY_DOP_MEM9_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_3_KEY_DOP_MEM9_3_KEY},\ + {"MEMDB_IFTA100_MEM9_3_KEY_DOP_MEM9_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_3_KEY_DOP_MEM9_3_PKT_RD},\ + {"MEMDB_IFTA100_MEM6_0_KEY_DOP_MEM6_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_0_KEY_DOP_MEM6_0_KEY},\ + {"MEMDB_IFTA100_MEM6_0_KEY_DOP_MEM6_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_0_KEY_DOP_MEM6_0_PKT_RD},\ + {"MEMDB_IFTA100_MEM6_2_KEY_DOP_MEM6_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_2_KEY_DOP_MEM6_2_KEY},\ + {"MEMDB_IFTA100_MEM6_2_KEY_DOP_MEM6_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_2_KEY_DOP_MEM6_2_PKT_RD},\ + {"MEMDB_IFTA100_MEM9_1_KEY_DOP_MEM9_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_1_KEY_DOP_MEM9_1_KEY},\ + {"MEMDB_IFTA100_MEM9_1_KEY_DOP_MEM9_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_1_KEY_DOP_MEM9_1_PKT_RD},\ + {"MEMDB_IFTA100_MEM5_1_KEY_DOP_MEM5_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_1_KEY_DOP_MEM5_1_KEY},\ + {"MEMDB_IFTA100_MEM5_1_KEY_DOP_MEM5_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_1_KEY_DOP_MEM5_1_PKT_RD},\ + {"MEMDB_IFTA100_MEM0_3_KEY_DOP_MEM0_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_3_KEY_DOP_MEM0_3_KEY},\ + {"MEMDB_IFTA100_MEM0_3_KEY_DOP_MEM0_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_3_KEY_DOP_MEM0_3_PKT_RD},\ + {"MEMDB_IFTA100_MEM3_3_KEY_DOP_MEM3_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_3_KEY_DOP_MEM3_3_KEY},\ + {"MEMDB_IFTA100_MEM3_3_KEY_DOP_MEM3_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_3_KEY_DOP_MEM3_3_PKT_RD},\ + {"MEMDB_IFTA100_MEM0_0_KEY_DOP_MEM0_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_0_KEY_DOP_MEM0_0_KEY},\ + {"MEMDB_IFTA100_MEM0_0_KEY_DOP_MEM0_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_0_KEY_DOP_MEM0_0_PKT_RD},\ + {"MEMDB_IFTA100_MEM1_1_KEY_DOP_MEM1_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_1_KEY_DOP_MEM1_1_KEY},\ + {"MEMDB_IFTA100_MEM1_1_KEY_DOP_MEM1_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_1_KEY_DOP_MEM1_1_PKT_RD},\ + {"MEMDB_IFTA100_MEM4_0_KEY_DOP_MEM4_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_0_KEY_DOP_MEM4_0_KEY},\ + {"MEMDB_IFTA100_MEM4_0_KEY_DOP_MEM4_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_0_KEY_DOP_MEM4_0_PKT_RD},\ + {"MEMDB_IFTA100_MEM3_1_KEY_DOP_MEM3_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_1_KEY_DOP_MEM3_1_KEY},\ + {"MEMDB_IFTA100_MEM3_1_KEY_DOP_MEM3_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_1_KEY_DOP_MEM3_1_PKT_RD},\ + {"MEMDB_IFTA100_MEM2_3_KEY_DOP_MEM2_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_3_KEY_DOP_MEM2_3_KEY},\ + {"MEMDB_IFTA100_MEM2_3_KEY_DOP_MEM2_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_3_KEY_DOP_MEM2_3_PKT_RD},\ + {"MEMDB_IFTA100_MEM10_0_KEY_DOP_MEM10_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_0_KEY_DOP_MEM10_0_KEY},\ + {"MEMDB_IFTA100_MEM10_0_KEY_DOP_MEM10_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_0_KEY_DOP_MEM10_0_PKT_RD},\ + {"MEMDB_IFTA100_MEM6_3_KEY_DOP_MEM6_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_3_KEY_DOP_MEM6_3_KEY},\ + {"MEMDB_IFTA100_MEM6_3_KEY_DOP_MEM6_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_3_KEY_DOP_MEM6_3_PKT_RD},\ + {"MEMDB_IFTA100_MEM0_1_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_1_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_IFTA100_MEM0_1_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_1_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_IFTA100_MEM5_2_KEY_DOP_MEM5_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_2_KEY_DOP_MEM5_2_KEY},\ + {"MEMDB_IFTA100_MEM5_2_KEY_DOP_MEM5_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_2_KEY_DOP_MEM5_2_PKT_RD},\ + {"MEMDB_IFTA100_MEM7_0_KEY_DOP_MEM7_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_0_KEY_DOP_MEM7_0_KEY},\ + {"MEMDB_IFTA100_MEM7_0_KEY_DOP_MEM7_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_0_KEY_DOP_MEM7_0_PKT_RD},\ + {"MEMDB_IFTA100_MEM1_3_KEY_DOP_MEM1_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_3_KEY_DOP_MEM1_3_KEY},\ + {"MEMDB_IFTA100_MEM1_3_KEY_DOP_MEM1_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_3_KEY_DOP_MEM1_3_PKT_RD},\ + {"MEMDB_IFTA100_MEM11_2_KEY_DOP_MEM11_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_2_KEY_DOP_MEM11_2_KEY},\ + {"MEMDB_IFTA100_MEM11_2_KEY_DOP_MEM11_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_2_KEY_DOP_MEM11_2_PKT_RD},\ + {"MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_0_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_0_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_1_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_1_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_2_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_2_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_3_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM9_INDEX_DOP_MEM9_3_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_0_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_0_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_1_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_1_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_2_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_2_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_3_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM10_INDEX_DOP_MEM10_3_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_0_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_0_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_1_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_1_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_2_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_2_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_3_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM7_INDEX_DOP_MEM7_3_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_0_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_0_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_1_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_1_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_2_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_2_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_3_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM5_INDEX_DOP_MEM5_3_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_0_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_0_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_1_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_1_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_2_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_2_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_3_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM8_INDEX_DOP_MEM8_3_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_0_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_0_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_1_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_1_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_2_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_2_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_3_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM2_INDEX_DOP_MEM2_3_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_0_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_0_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_1_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_1_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_2_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_2_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_3_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM11_INDEX_DOP_MEM11_3_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_0_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_0_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_1_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_1_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_2_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_2_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_3_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM6_INDEX_DOP_MEM6_3_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_2_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_2_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_3_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM1_INDEX_DOP_MEM1_3_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_0_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_0_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_1_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_1_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_2_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_2_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_3_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM4_INDEX_DOP_MEM4_3_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_0_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_0_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_1_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_1_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_2_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_2_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_3_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM3_INDEX_DOP_MEM3_3_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH},\ + {"MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX},\ + {"MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA100_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH},\ + {"IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IFSL100_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"ECMP_GROUP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX", BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX},\ + {"ECMP_GROUP_LEVEL0_GROUP_TABLE_DATA_DOP_GROUP_TABLE_DATA", BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL0_GROUP_TABLE_DATA_DOP_GROUP_TABLE_DATA},\ + {"ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX", BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX},\ + {"ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP_HASH", BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP_HASH},\ + {"ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP_MODULO_OFFSET", BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP_MODULO_OFFSET},\ + {"MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR},\ + {"MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM0_PKT_RD},\ + {"MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR},\ + {"MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA110_MY_DOP_INDEX_DOP_MEM1_PKT_RD},\ + {"ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_B1", BCMPKT_TRACE_DOP_ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_B1},\ + {"ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_B0", BCMPKT_TRACE_DOP_ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_B0},\ + {"ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_A1", BCMPKT_TRACE_DOP_ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_A1},\ + {"ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_A0", BCMPKT_TRACE_DOP_ETRAP_ETR_HIT_RTAG_HASH_DOP_RTAG7_HASH_A0},\ + {"ETRAP_ETR_HIT_RTAG_HASH_DOP_ETR_HIT", BCMPKT_TRACE_DOP_ETRAP_ETR_HIT_RTAG_HASH_DOP_ETR_HIT},\ + {"ETRAP_ETR_OUT_DOP_FLW_OFMT_FLOW_TABLE_HIT", BCMPKT_TRACE_DOP_ETRAP_ETR_OUT_DOP_FLW_OFMT_FLOW_TABLE_HIT},\ + {"ETRAP_ETR_OUT_DOP_EOP_FLOW_TABLE_HIT_PM2", BCMPKT_TRACE_DOP_ETRAP_ETR_OUT_DOP_EOP_FLOW_TABLE_HIT_PM2},\ + {"ETRAP_ETR_OUT_DOP_ETR_CNG", BCMPKT_TRACE_DOP_ETRAP_ETR_OUT_DOP_ETR_CNG},\ + {"ETRAP_ETR_OUT_DOP_ETR_VALID", BCMPKT_TRACE_DOP_ETRAP_ETR_OUT_DOP_ETR_VALID},\ + {"DLB_ECMP_DLB_ECMP_CURRENT_TIME_DOP_CURRENT_TIME", BCMPKT_TRACE_DOP_DLB_ECMP_DLB_ECMP_CURRENT_TIME_DOP_CURRENT_TIME},\ + {"DLB_ECMP_DLB_ECMP_FLOWSET_INDEX_DOP_FLOWSET_INDEX", BCMPKT_TRACE_DOP_DLB_ECMP_DLB_ECMP_FLOWSET_INDEX_DOP_FLOWSET_INDEX},\ + {"ECMP_GROUP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX", BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX},\ + {"ECMP_GROUP_LEVEL1_GROUP_TABLE_DATA_DOP_GROUP_TABLE_DATA", BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL1_GROUP_TABLE_DATA_DOP_GROUP_TABLE_DATA},\ + {"ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX", BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX},\ + {"ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP_HASH", BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP_HASH},\ + {"ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP_MODULO_OFFSET", BCMPKT_TRACE_DOP_ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP_MODULO_OFFSET},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM0_PKT_RD},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM1_PKT_RD},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM2_PKT_RD},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM3_PKT_RD},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM4_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM4_PKT_RD},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM5_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM5_PKT_RD},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM6_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM6_PKT_RD},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM7_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA120_MY_DOP_INDEX_DOP_MEM7_PKT_RD},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM0_PKT_RD},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM1_PKT_RD},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM2_PKT_RD},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM3_PKT_RD},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM4_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM4_PKT_RD},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM5_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM5_PKT_RD},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM6_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM6_PKT_RD},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM7_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA130_MY_DOP_INDEX_DOP_MEM7_PKT_RD},\ + {"IFTA130_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA130_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA130_I1T_00_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA130_I1T_00_INDEX_DOP_LKP0_LTPR_WIN},\ + {"IFTA130_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA130_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA130_I1T_01_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA130_I1T_01_INDEX_DOP_LKP0_LTPR_WIN},\ + {"IFTA130_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA130_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA130_I1T_02_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA130_I1T_02_INDEX_DOP_LKP0_LTPR_WIN},\ + {"IFTA130_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA130_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA130_I1T_03_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA130_I1T_03_INDEX_DOP_LKP0_LTPR_WIN},\ + {"MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR},\ + {"MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM0_PKT_RD},\ + {"MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR},\ + {"MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA140_MY_DOP_INDEX_DOP_MEM1_PKT_RD},\ + {"IFTA140_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA140_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA140_I1T_00_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA140_I1T_00_INDEX_DOP_LKP0_LTPR_WIN},\ + {"IFTA140_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA140_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA140_I1T_01_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA140_I1T_01_INDEX_DOP_LKP0_LTPR_WIN},\ + {"FLEX_CTR_ST_ING1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0},\ + {"FLEX_CTR_ST_ING1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1},\ + {"FLEX_CTR_ST_ING1_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID},\ + {"FLEX_CTR_ST_ING1_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID},\ + {"FLEX_CTR_ST_ING1_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID},\ + {"FLEX_CTR_ST_ING1_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID},\ + {"FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B0},\ + {"FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B1},\ + {"FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B2},\ + {"FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_COUNTER_B3},\ + {"FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B0},\ + {"FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B1},\ + {"FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B2},\ + {"FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_B_DOP_BUS_COUNTER_B3},\ + {"FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0},\ + {"FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1},\ + {"FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2},\ + {"FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3},\ + {"FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0},\ + {"FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1},\ + {"FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2},\ + {"FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3},\ + {"FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A0},\ + {"FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A1},\ + {"FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A2},\ + {"FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_BUS_COUNTER_A3},\ + {"FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A0},\ + {"FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A1},\ + {"FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A2},\ + {"FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_ING1_COUNTER_A_DOP_COUNTER_A3},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"IFTA150_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA150_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"IFTA150_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY},\ + {"IFTA150_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"IFTA150_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY},\ + {"IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX},\ + {"IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX},\ + {"IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"MEMDB_IFTA150_MEM0_1_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_1_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_IFTA150_MEM0_1_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_1_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_IFTA150_MEM0_3_KEY_DOP_MEM0_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_3_KEY_DOP_MEM0_3_KEY},\ + {"MEMDB_IFTA150_MEM0_3_KEY_DOP_MEM0_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_3_KEY_DOP_MEM0_3_PKT_RD},\ + {"MEMDB_IFTA150_MEM0_2_KEY_DOP_MEM0_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_2_KEY_DOP_MEM0_2_KEY},\ + {"MEMDB_IFTA150_MEM0_2_KEY_DOP_MEM0_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_2_KEY_DOP_MEM0_2_PKT_RD},\ + {"MEMDB_IFTA150_MEM0_0_KEY_DOP_MEM0_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_0_KEY_DOP_MEM0_0_KEY},\ + {"MEMDB_IFTA150_MEM0_0_KEY_DOP_MEM0_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_0_KEY_DOP_MEM0_0_PKT_RD},\ + {"MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX},\ + {"MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH},\ + {"MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX},\ + {"MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH},\ + {"MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX},\ + {"MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH},\ + {"MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX},\ + {"MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA150_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH},\ + {"IPOST_DLB_LAG_DLB_LAG_CURRENT_TIME_DOP_CURRENT_TIME", BCMPKT_TRACE_DOP_IPOST_DLB_LAG_DLB_LAG_CURRENT_TIME_DOP_CURRENT_TIME},\ + {"IPOST_DLB_LAG_DLB_LAG_FLOWSET_INDEX_DOP_FLOWSET_INDEX", BCMPKT_TRACE_DOP_IPOST_DLB_LAG_DLB_LAG_FLOWSET_INDEX_DOP_FLOWSET_INDEX},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_BUS", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_BUS},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_0", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_0},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_1", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_1},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_2", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_2},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_3", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_3},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_4", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_4},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_5", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_5},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_6", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_6},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_7", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP_MIRROR_SESSION_7},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_0_RDATA", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_0_RDATA},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_1_RDATA", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_1_RDATA},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_2_RDATA", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_2_RDATA},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_3_RDATA", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_3_RDATA},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_4_RDATA", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_4_RDATA},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_5_RDATA", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_5_RDATA},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_6_RDATA", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_6_RDATA},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_7_RDATA", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP_FINAL_MIRROR_SESSION_7_RDATA},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_0_WINNER", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_0_WINNER},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_1_WINNER", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_1_WINNER},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_2_WINNER", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_2_WINNER},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_3_WINNER", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_3_WINNER},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_4_WINNER", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_4_WINNER},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_5_WINNER", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_5_WINNER},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_6_WINNER", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_6_WINNER},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_7_WINNER", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP_MIRROR_SESSION_7_WINNER},\ + {"IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_INDEX_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_INDEX_DOP_LTS_TCAM_MATCH_INDEX},\ + {"IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH},\ + {"IPOST_CPU_COS_CPU_COS_MAP_TCAM_KEY_DOP_CPU_COS_MAP_TCAM_KEY", BCMPKT_TRACE_DOP_IPOST_CPU_COS_CPU_COS_MAP_TCAM_KEY_DOP_CPU_COS_MAP_TCAM_KEY},\ + {"IPOST_CPU_COS_CPU_COS_MAP_TCAM_INDEX_DOP_CPU_COS_MAP_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_IPOST_CPU_COS_CPU_COS_MAP_TCAM_INDEX_DOP_CPU_COS_MAP_TCAM_MATCH_INDEX},\ + {"IPOST_CPU_COS_CPU_COS_MAP_TCAM_INDEX_DOP_CPU_COS_MAP_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPOST_CPU_COS_CPU_COS_MAP_TCAM_INDEX_DOP_CPU_COS_MAP_TCAM_TCAM_MATCH},\ + {"IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY", BCMPKT_TRACE_DOP_IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY},\ + {"IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_MATCH_INDEX},\ + {"IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_TCAM_MATCH},\ + {"IPOST_MPB_ENCODE_MPB_FLEX_BUS_DOP_OUT_MPB_FLEX_BUS", BCMPKT_TRACE_DOP_IPOST_MPB_ENCODE_MPB_FLEX_BUS_DOP_OUT_MPB_FLEX_BUS},\ + {"IPOST_MPB_CCBI_FIXED_CCBI_B_BUS_DOP_OUT_CCBI_B_BUS", BCMPKT_TRACE_DOP_IPOST_MPB_CCBI_FIXED_CCBI_B_BUS_DOP_OUT_CCBI_B_BUS},\ + {"IPOST_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP_OUT_MPB_FIXED_BUS", BCMPKT_TRACE_DOP_IPOST_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP_OUT_MPB_FIXED_BUS},\ + {"FLEX_CTR_ING_COUNTER_ACTION_VECTOR_DOP_ING_FLEX_CTR_BUS", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_ACTION_VECTOR_DOP_ING_FLEX_CTR_BUS},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_2_DOP_COUNTER_EOP_BUFFER_2_PKT_WDATA_COUNTER_EOP_BUFFER_2_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_2_DOP_COUNTER_EOP_BUFFER_2_PKT_WDATA_COUNTER_EOP_BUFFER_2_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_11_DOP_COUNTER_EOP_BUFFER_11_PKT_WDATA_COUNTER_EOP_BUFFER_11_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_11_DOP_COUNTER_EOP_BUFFER_11_PKT_WDATA_COUNTER_EOP_BUFFER_11_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_8_DOP_COUNTER_EOP_BUFFER_8_PKT_WDATA_COUNTER_EOP_BUFFER_8_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_8_DOP_COUNTER_EOP_BUFFER_8_PKT_WDATA_COUNTER_EOP_BUFFER_8_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_7_DOP_COUNTER_EOP_BUFFER_7_PKT_WDATA_COUNTER_EOP_BUFFER_7_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_7_DOP_COUNTER_EOP_BUFFER_7_PKT_WDATA_COUNTER_EOP_BUFFER_7_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_5_DOP_COUNTER_EOP_BUFFER_5_PKT_WDATA_COUNTER_EOP_BUFFER_5_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_5_DOP_COUNTER_EOP_BUFFER_5_PKT_WDATA_COUNTER_EOP_BUFFER_5_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_9_DOP_COUNTER_EOP_BUFFER_9_PKT_WDATA_COUNTER_EOP_BUFFER_9_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_9_DOP_COUNTER_EOP_BUFFER_9_PKT_WDATA_COUNTER_EOP_BUFFER_9_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_6_DOP_COUNTER_EOP_BUFFER_6_PKT_WDATA_COUNTER_EOP_BUFFER_6_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_6_DOP_COUNTER_EOP_BUFFER_6_PKT_WDATA_COUNTER_EOP_BUFFER_6_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_0_DOP_COUNTER_EOP_BUFFER_0_PKT_WDATA_COUNTER_EOP_BUFFER_0_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_0_DOP_COUNTER_EOP_BUFFER_0_PKT_WDATA_COUNTER_EOP_BUFFER_0_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_1_DOP_COUNTER_EOP_BUFFER_1_PKT_WDATA_COUNTER_EOP_BUFFER_1_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_1_DOP_COUNTER_EOP_BUFFER_1_PKT_WDATA_COUNTER_EOP_BUFFER_1_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_4_DOP_COUNTER_EOP_BUFFER_4_PKT_WDATA_COUNTER_EOP_BUFFER_4_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_4_DOP_COUNTER_EOP_BUFFER_4_PKT_WDATA_COUNTER_EOP_BUFFER_4_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_3_DOP_COUNTER_EOP_BUFFER_3_PKT_WDATA_COUNTER_EOP_BUFFER_3_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_3_DOP_COUNTER_EOP_BUFFER_3_PKT_WDATA_COUNTER_EOP_BUFFER_3_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_10_DOP_COUNTER_EOP_BUFFER_10_PKT_WDATA_COUNTER_EOP_BUFFER_10_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_10_DOP_COUNTER_EOP_BUFFER_10_PKT_WDATA_COUNTER_EOP_BUFFER_10_PKT_WR},\ + {"IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IFSL140_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_4_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_4_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_4_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_4_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_1_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_1_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_1_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_1_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_3_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_3_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_3_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_3_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_2_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_2_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_2_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_2_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_0_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_0_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_0_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_0_MATCH_ID_ATTRIBUTES_TABLE_PKT_ADDR},\ + {"EPRE_PARSER_ZONE_REMAP_EGR_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP_FIELD_EXTRACTION_PROFILE_CONTROL_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_EGR_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP_FIELD_EXTRACTION_PROFILE_CONTROL_PKT_ADDR},\ + {"EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER0_CTRL_DOP_OUT_EGR_SCR_EPRE2EPARSER0_BUS", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER0_CTRL_DOP_OUT_EGR_SCR_EPRE2EPARSER0_BUS},\ + {"EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER1_CTRL_DOP_OUT_EGR_SCR_EPRE2EPARSER1_BUS", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER1_CTRL_DOP_OUT_EGR_SCR_EPRE2EPARSER1_BUS},\ + {"EPRE_EDEV_CONFIG_EGR_INT_CN_UPDATE_INDEX_DOP_EGR_INT_CN_UPDATE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_EGR_INT_CN_UPDATE_INDEX_DOP_EGR_INT_CN_UPDATE_PKT_ADDR},\ + {"EPRE_EDEV_CONFIG_FORWARDING_TYPE_TABLE_INDEX_DOP_FORWARDING_TYPE_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_FORWARDING_TYPE_TABLE_INDEX_DOP_FORWARDING_TYPE_TABLE_PKT_ADDR},\ + {"EPRE_EDEV_CONFIG_MPB_FIXED_DOP_MPB_FIXED", BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_MPB_FIXED_DOP_MPB_FIXED},\ + {"EPRE_EDEV_CONFIG_CCBE_DOP_CCBE_BUS", BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_CCBE_DOP_CCBE_BUS},\ + {"EPRE_EDEV_CONFIG_EGR_TABLE_INDEX_UPDATE_PROFILE_INDEX_DOP_EGR_TABLE_INDEX_UPDATE_PROFILE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_EGR_TABLE_INDEX_UPDATE_PROFILE_INDEX_DOP_EGR_TABLE_INDEX_UPDATE_PROFILE_PKT_ADDR},\ + {"EPRE_EDEV_CONFIG_MIRROR_ATTRIBUTES_TABLE_INDEX_DOP_MIRROR_ATTRIBUTES_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_MIRROR_ATTRIBUTES_TABLE_INDEX_DOP_MIRROR_ATTRIBUTES_TABLE_PKT_ADDR},\ + {"EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP_PDD_PROFILE_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP_PDD_PROFILE_TABLE_PKT_ADDR},\ + {"EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP_MPB_FLEX", BCMPKT_TRACE_DOP_EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP_MPB_FLEX},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM0_PKT_RD},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM1_PKT_RD},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM2_PKT_RD},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM3_PKT_RD},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM4_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM4_PKT_RD},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM5_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM5_PKT_RD},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM6_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM6_PKT_RD},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM7_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA10_MY_DOP_INDEX_DOP_MEM7_PKT_RD},\ + {"EFTA10_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA10_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA10_I1T_00_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA10_I1T_00_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFTA10_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA10_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA10_I1T_01_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA10_I1T_01_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFTA10_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA10_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA10_I1T_02_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA10_I1T_02_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFTA10_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA10_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA10_I1T_03_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA10_I1T_03_INDEX_DOP_LKP0_LTPR_WIN},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_ADDR},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM0_PKT_RD},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_ADDR},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM1_PKT_RD},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM10_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM10_PKT_ADDR},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM10_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM10_PKT_RD},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM11_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM11_PKT_ADDR},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM11_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM11_PKT_RD},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM2_PKT_ADDR},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM2_PKT_RD},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM3_PKT_ADDR},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM3_PKT_RD},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM4_PKT_ADDR},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM4_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM4_PKT_RD},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM5_PKT_ADDR},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM5_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM5_PKT_RD},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM6_PKT_ADDR},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM6_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM6_PKT_RD},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM7_PKT_ADDR},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM7_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM7_PKT_RD},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM8_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM8_PKT_ADDR},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM8_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM8_PKT_RD},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM9_PKT_ADDR", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM9_PKT_ADDR},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM9_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_EFTA20_MY_DOP_INDEX_DOP_MEM9_PKT_RD},\ + {"EFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA20_I1T_00_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA20_I1T_00_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFTA20_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA20_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA20_I1T_01_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA20_I1T_01_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFTA20_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA20_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA20_I1T_02_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA20_I1T_02_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFTA20_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA20_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA20_I1T_03_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA20_I1T_03_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFTA20_I1T_04_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA20_I1T_04_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA20_I1T_04_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA20_I1T_04_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFTA20_I1T_05_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA20_I1T_05_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA20_I1T_05_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA20_I1T_05_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFTA20_I1T_06_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA20_I1T_06_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA20_I1T_06_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA20_I1T_06_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_EFSL20_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"EFTA30_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"EFTA30_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"EFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_EFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"EFTA30_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_EFTA30_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"EFTA30_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_1_KEY_DOP_LTS_TCAM_1_KEY},\ + {"EFTA30_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_3_KEY_DOP_LTS_TCAM_3_KEY},\ + {"EFTA30_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_0_KEY_DOP_LTS_TCAM_0_KEY},\ + {"EFTA30_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_2_KEY_DOP_LTS_TCAM_2_KEY},\ + {"EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_MATCH_INDEX},\ + {"EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_MATCH_INDEX},\ + {"EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_MATCH_INDEX},\ + {"EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_MATCH_INDEX},\ + {"EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_0_TCAM_MATCH},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_1_TCAM_MATCH},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_2_TCAM_MATCH},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP_LTS_TCAM_3_TCAM_MATCH},\ + {"EFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_EFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_EGR_TS_PROFILE_INDEX", BCMPKT_TRACE_DOP_EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_EGR_TS_PROFILE_INDEX},\ + {"EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_EGR_INGRESS_TIMESTAMP_BUS", BCMPKT_TRACE_DOP_EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_EGR_INGRESS_TIMESTAMP_BUS},\ + {"EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_TIMESTAMP_COUNT", BCMPKT_TRACE_DOP_EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_TIMESTAMP_COUNT},\ + {"EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_INGRESS_TIMESTAMP", BCMPKT_TRACE_DOP_EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP_INGRESS_TIMESTAMP},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBER_INDEX", BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBER_INDEX},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_PKT_ADDR},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_UNTAG_BITMAP_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_UNTAG_BITMAP_PKT_ADDR},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_STATE_PROFILE_LOWER_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_STATE_PROFILE_LOWER_PKT_ADDR},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBERSHIP_PROFILE_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBERSHIP_PROFILE_PKT_ADDR},\ + {"FLEX_CTR_ST_EGR_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0},\ + {"FLEX_CTR_ST_EGR_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1},\ + {"FLEX_CTR_ST_EGR_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID},\ + {"FLEX_CTR_ST_EGR_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID},\ + {"FLEX_CTR_ST_EGR_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID},\ + {"FLEX_CTR_ST_EGR_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID},\ + {"FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B0},\ + {"FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B1},\ + {"FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B2},\ + {"FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_B_DOP_COUNTER_B3},\ + {"FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0},\ + {"FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1},\ + {"FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2},\ + {"FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3},\ + {"FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A0},\ + {"FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A1},\ + {"FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A2},\ + {"FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR_COUNTER_A_DOP_COUNTER_A3},\ + {"FLEX_CTR_ST_EGR0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0},\ + {"FLEX_CTR_ST_EGR0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1},\ + {"FLEX_CTR_ST_EGR0_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID},\ + {"FLEX_CTR_ST_EGR0_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID},\ + {"FLEX_CTR_ST_EGR0_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID},\ + {"FLEX_CTR_ST_EGR0_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID},\ + {"FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B0},\ + {"FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B1},\ + {"FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B2},\ + {"FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_B_DOP_BUS_COUNTER_B3},\ + {"FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0},\ + {"FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1},\ + {"FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2},\ + {"FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3},\ + {"FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A0},\ + {"FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A1},\ + {"FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A2},\ + {"FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_COUNTER_A_DOP_BUS_COUNTER_A3},\ + {"FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0},\ + {"FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1},\ + {"FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2},\ + {"FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3},\ + {"FLEX_CTR_ST_EGR1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_0},\ + {"FLEX_CTR_ST_EGR1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_ACTION_VECTOR_DOP_FLEX_STATE_ACTION_CTRL_1},\ + {"FLEX_CTR_ST_EGR1_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_POOL_1_UPDATE_CMD_DOP_POOL1_COUNTER_UPDATE_CMDPOOL1_CMD_VALID},\ + {"FLEX_CTR_ST_EGR1_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_POOL_2_UPDATE_CMD_DOP_POOL2_COUNTER_UPDATE_CMDPOOL2_CMD_VALID},\ + {"FLEX_CTR_ST_EGR1_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_POOL_3_UPDATE_CMD_DOP_POOL3_COUNTER_UPDATE_CMDPOOL3_CMD_VALID},\ + {"FLEX_CTR_ST_EGR1_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_POOL_0_UPDATE_CMD_DOP_POOL0_COUNTER_UPDATE_CMDPOOL0_CMD_VALID},\ + {"FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B0},\ + {"FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B1},\ + {"FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B2},\ + {"FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_B_DOP_BUS_COUNTER_B3},\ + {"FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_0},\ + {"FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_1},\ + {"FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_2},\ + {"FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP_TRIGGER_STATE_CTRL_3},\ + {"FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A0},\ + {"FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A1},\ + {"FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A2},\ + {"FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_COUNTER_A_DOP_BUS_COUNTER_A3},\ + {"FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_0},\ + {"FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_1},\ + {"FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_2},\ + {"FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3", BCMPKT_TRACE_DOP_FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP_TRUTH_TABLE_OUTPUT_3},\ + {"MEMDB_TCAM_EFTA30_MEM0_1_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_1_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_TCAM_EFTA30_MEM0_1_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_1_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_TCAM_EFTA30_MEM0_3_KEY_DOP_MEM0_3_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_3_KEY_DOP_MEM0_3_KEY},\ + {"MEMDB_TCAM_EFTA30_MEM0_3_KEY_DOP_MEM0_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_3_KEY_DOP_MEM0_3_PKT_RD},\ + {"MEMDB_TCAM_EFTA30_MEM0_2_KEY_DOP_MEM0_2_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_2_KEY_DOP_MEM0_2_KEY},\ + {"MEMDB_TCAM_EFTA30_MEM0_2_KEY_DOP_MEM0_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_2_KEY_DOP_MEM0_2_PKT_RD},\ + {"MEMDB_TCAM_EFTA30_MEM0_0_KEY_DOP_MEM0_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_0_KEY_DOP_MEM0_0_KEY},\ + {"MEMDB_TCAM_EFTA30_MEM0_0_KEY_DOP_MEM0_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_0_KEY_DOP_MEM0_0_PKT_RD},\ + {"MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX},\ + {"MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH},\ + {"MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX},\ + {"MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH},\ + {"MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX},\ + {"MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH},\ + {"MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX},\ + {"MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH},\ + {"EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_EFSL30_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"EGR_MIRROR_MIRROR2EDIT_CTRL_BUS_DOP_OUT_EGR_SCR_MIRROR2EDIT_CTRL_BUS", BCMPKT_TRACE_DOP_EGR_MIRROR_MIRROR2EDIT_CTRL_BUS_DOP_OUT_EGR_SCR_MIRROR2EDIT_CTRL_BUS},\ + {"QOS_REMARKING_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_KEY", BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_KEY},\ + {"QOS_REMARKING_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_ONLY_MATCH_INDEX", BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_ONLY_MATCH_INDEX},\ + {"QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_ONLY_TCAM_MATCH", BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_ONLY_TCAM_MATCH},\ + {"QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_POLICY_DATA", BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_POLICY_DATA},\ + {"QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX", BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX},\ + {"QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_ONLY_TCAM_MATCH", BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_ONLY_TCAM_MATCH},\ + {"QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA", BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA},\ + {"QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX", BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX},\ + {"QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_QOS_REMARKING_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH},\ + {"QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_4_PKT_ADDR", BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_4_PKT_ADDR},\ + {"QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_3_PKT_ADDR", BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_3_PKT_ADDR},\ + {"QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_2_PKT_ADDR", BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_2_PKT_ADDR},\ + {"QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_1_PKT_ADDR", BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_1_PKT_ADDR},\ + {"QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_0_PKT_ADDR", BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_ECN_MAP_TABLE_0_PKT_ADDR},\ + {"QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_MPLS_QOS_MAP_TABLE_1_PKT_ADDR", BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_MPLS_QOS_MAP_TABLE_1_PKT_ADDR},\ + {"QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_MPLS_QOS_MAP_TABLE_0_PKT_ADDR", BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_MPLS_QOS_MAP_TABLE_0_PKT_ADDR},\ + {"QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_4_PKT_ADDR", BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_4_PKT_ADDR},\ + {"QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_3_PKT_ADDR", BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_3_PKT_ADDR},\ + {"QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_2_PKT_ADDR", BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_2_PKT_ADDR},\ + {"QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_1_PKT_ADDR", BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_1_PKT_ADDR},\ + {"QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_0_PKT_ADDR", BCMPKT_TRACE_DOP_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP_QOS_MAP_TABLE_0_PKT_ADDR},\ + {"EDIT_CTRL_ZONE_4_TCAM_KEY_DOP_TCAM_4_A_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_KEY_DOP_TCAM_4_A_KEY},\ + {"EDIT_CTRL_ZONE_3_TCAM_KEY_DOP_TCAM_3_A_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_KEY_DOP_TCAM_3_A_KEY},\ + {"EDIT_CTRL_ZONE_1_TCAM_KEY_DOP_TCAM_1_A_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_KEY_DOP_TCAM_1_A_KEY},\ + {"EDIT_CTRL_ZONE_2_TCAM_KEY_DOP_TCAM_2_A_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_KEY_DOP_TCAM_2_A_KEY},\ + {"EDIT_CTRL_ZONE_0_TCAM_KEY_DOP_TCAM_0_A_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_KEY_DOP_TCAM_0_A_KEY},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_TCAM_4_A_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_TCAM_4_A_KEY},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_TCAM_4_A_UPPER_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_TCAM_4_A_UPPER_KEY},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP_TCAM_3_A_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP_TCAM_3_A_KEY},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_TCAM_2_A_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_TCAM_2_A_KEY},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_TCAM_2_A_UPPER_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_TCAM_2_A_UPPER_KEY},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP_TCAM_1_A_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP_TCAM_1_A_KEY},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP_TCAM_0_A_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP_TCAM_0_A_KEY},\ + {"EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_C_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_C_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_C_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_C_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_B_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_B_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_B_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_B_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_A_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_A_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_A_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP_TCAM_0_A_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_C_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_C_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_C_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_C_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_B_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_B_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_B_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_B_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_A_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_A_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_A_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP_TCAM_4_A_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_C_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_C_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_C_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_C_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_B_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_B_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_B_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_B_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_A_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_A_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_A_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP_TCAM_3_A_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_C_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_C_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_C_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_C_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_B_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_B_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_B_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_B_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_A_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_A_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_A_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP_TCAM_2_A_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_C_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_C_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_C_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_C_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_B_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_B_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_B_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_B_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_A_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_A_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_A_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP_TCAM_1_A_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_C_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_C_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_C_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_C_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_B_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_B_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_B_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_B_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_A_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_A_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_A_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_A_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_C_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_C_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_C_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_C_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_B_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_B_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_B_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_B_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_A_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_A_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_A_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_A_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_C_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_C_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_C_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_C_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_B_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_B_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_B_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_B_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_A_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_A_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_A_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_A_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_C_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_C_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_C_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_C_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_B_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_B_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_B_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_B_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_A_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_A_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_A_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_A_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_C_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_C_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_C_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_C_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_B_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_B_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_B_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_B_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_A_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_A_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_A_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_A_MATCH_INDEX},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_2_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_2_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_2_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_2_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_RW_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_3_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_3_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_RW_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_0_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_2_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_2_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_1_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EGR_SEQUENCE_MIRROR_SEQUENCE_NUMBER_PROFILE_INDEX_DOP_MIRROR_SEQUENCE_NUMBER_PROFILE_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_SEQUENCE_MIRROR_SEQUENCE_NUMBER_PROFILE_INDEX_DOP_MIRROR_SEQUENCE_NUMBER_PROFILE_PKT_ADDR},\ + {"EGR_SEQUENCE_SEQUENCE_NUMBER_TABLE_INDEX_DOP_NUMBER_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_SEQUENCE_SEQUENCE_NUMBER_TABLE_INDEX_DOP_NUMBER_TABLE_PKT_ADDR},\ + {"EGR_SEQUENCE_SEQUENCE_PROFILE_INDEX_DOP_PROFILE_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_SEQUENCE_SEQUENCE_PROFILE_INDEX_DOP_PROFILE_PKT_ADDR},\ + {"EGR_SEQUENCE_NEW_SEQUENCE_NUM_DOP_NEW_SEQUENCE_NUM", BCMPKT_TRACE_DOP_EGR_SEQUENCE_NEW_SEQUENCE_NUM_DOP_NEW_SEQUENCE_NUM},\ + {"EGR_SEQUENCE_PKT_SEQUENCE_NUM_DOP_PKT_SEQUENCE_NUM", BCMPKT_TRACE_DOP_EGR_SEQUENCE_PKT_SEQUENCE_NUM_DOP_PKT_SEQUENCE_NUM},\ + {"FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_4", BCMPKT_TRACE_DOP_FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_4},\ + {"FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_3", BCMPKT_TRACE_DOP_FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_3},\ + {"FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_2", BCMPKT_TRACE_DOP_FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_2},\ + {"FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_1", BCMPKT_TRACE_DOP_FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_1},\ + {"FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_0", BCMPKT_TRACE_DOP_FLEX_EDITOR_MATCH_ID_DOP_MATCH_ID_0},\ + {"FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_3", BCMPKT_TRACE_DOP_FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_3},\ + {"FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_2", BCMPKT_TRACE_DOP_FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_2},\ + {"FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_1", BCMPKT_TRACE_DOP_FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_1},\ + {"FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_0", BCMPKT_TRACE_DOP_FLEX_EDITOR_VHLEN_DOP_EGR_VHLEN_FMT_0},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_4", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_4},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_3", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_3},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_2", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_2},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_1", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_1},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_0", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_RW_0},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_4", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_4},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_3", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_3},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_2", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_2},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_1", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_1},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_0", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_INS_0},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_4", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_4},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_3", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_3},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_2", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_2},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_1", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_1},\ + {"FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_0", BCMPKT_TRACE_DOP_FLEX_EDITOR_EDIT_ID_DOP_EDIT_ID_DEL_0},\ + {"FLEX_CTR_EGR_COUNTER_ACTION_VECTOR_DOP_EGR_FLEX_CTR_BUS", BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_ACTION_VECTOR_DOP_EGR_FLEX_CTR_BUS},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_2_DOP_COUNTER_EOP_BUFFER_2_PKT_WDATA_COUNTER_EOP_BUFFER_2_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_2_DOP_COUNTER_EOP_BUFFER_2_PKT_WDATA_COUNTER_EOP_BUFFER_2_PKT_WR},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_7_DOP_COUNTER_EOP_BUFFER_7_PKT_WDATA_COUNTER_EOP_BUFFER_7_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_7_DOP_COUNTER_EOP_BUFFER_7_PKT_WDATA_COUNTER_EOP_BUFFER_7_PKT_WR},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_5_DOP_COUNTER_EOP_BUFFER_5_PKT_WDATA_COUNTER_EOP_BUFFER_5_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_5_DOP_COUNTER_EOP_BUFFER_5_PKT_WDATA_COUNTER_EOP_BUFFER_5_PKT_WR},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_6_DOP_COUNTER_EOP_BUFFER_6_PKT_WDATA_COUNTER_EOP_BUFFER_6_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_6_DOP_COUNTER_EOP_BUFFER_6_PKT_WDATA_COUNTER_EOP_BUFFER_6_PKT_WR},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_0_DOP_COUNTER_EOP_BUFFER_0_PKT_WDATA_COUNTER_EOP_BUFFER_0_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_0_DOP_COUNTER_EOP_BUFFER_0_PKT_WDATA_COUNTER_EOP_BUFFER_0_PKT_WR},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_1_DOP_COUNTER_EOP_BUFFER_1_PKT_WDATA_COUNTER_EOP_BUFFER_1_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_1_DOP_COUNTER_EOP_BUFFER_1_PKT_WDATA_COUNTER_EOP_BUFFER_1_PKT_WR},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_4_DOP_COUNTER_EOP_BUFFER_4_PKT_WDATA_COUNTER_EOP_BUFFER_4_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_4_DOP_COUNTER_EOP_BUFFER_4_PKT_WDATA_COUNTER_EOP_BUFFER_4_PKT_WR},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_3_DOP_COUNTER_EOP_BUFFER_3_PKT_WDATA_COUNTER_EOP_BUFFER_3_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_3_DOP_COUNTER_EOP_BUFFER_3_PKT_WDATA_COUNTER_EOP_BUFFER_3_PKT_WR},\ + {"APU_EGR0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY", BCMPKT_TRACE_DOP_APU_EGR0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY},\ + {"APU_EGR1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY", BCMPKT_TRACE_DOP_APU_EGR1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY},\ + {"APU_ING0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY", BCMPKT_TRACE_DOP_APU_ING0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY},\ + {"APU_ING1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY", BCMPKT_TRACE_DOP_APU_ING1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP_TCAM_KEY_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0_FINAL_TCAM_POLICY},\ + {"ECMP_LEVEL0_GROUP_TABLE_DATA_DOP_GROUP_TABLE_DATA", BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_TABLE_DATA_DOP_GROUP_TABLE_DATA},\ + {"ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX", BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX},\ + {"ECMP_LEVEL0_MEMBER_INDEX_DOP_HASH", BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_HASH},\ + {"ECMP_LEVEL0_MEMBER_INDEX_DOP_MODULO_OFFSET", BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_MODULO_OFFSET},\ + {"ECMP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX", BCMPKT_TRACE_DOP_ECMP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX},\ + {"ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_DLB_NHI", BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_DLB_NHI},\ + {"ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_ALT_NHI", BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_ALT_NHI},\ + {"ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_ALT_HASH", BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_ALT_HASH},\ + {"ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_ALT_MODULO_OFFSET", BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP_ALT_MODULO_OFFSET},\ + {"ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX", BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_INDEX},\ + {"ECMP_LEVEL1_MEMBER_INDEX_DOP_PRIM_HASH", BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_PRIM_HASH},\ + {"ECMP_LEVEL1_MEMBER_INDEX_DOP_MODULO_OFFSET", BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_MODULO_OFFSET},\ + {"ECMP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX", BCMPKT_TRACE_DOP_ECMP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP_SHUFFLE_TABLE_INDEX},\ + {"EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY},\ + {"EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD},\ + {"EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY},\ + {"EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD},\ + {"EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY},\ + {"EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD},\ + {"EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY},\ + {"EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_PKT_RD},\ + {"EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_TCAM_MATCH},\ + {"EFTA40_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA40_I1T_00_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA40_I1T_00_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA40_I1T_00_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFTA40_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA40_I1T_01_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA40_I1T_01_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA40_I1T_01_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFTA40_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA40_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA40_I1T_02_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA40_I1T_02_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFTA40_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA40_I1T_03_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EFTA40_I1T_03_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA40_I1T_03_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_1_LOWER_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_1_LOWER_PKT_ADDR},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_UNTAG_BITMAP_LOWER_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_UNTAG_BITMAP_LOWER_PKT_ADDR},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_STATE_PROFILE_LOWER_0_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_STATE_PROFILE_LOWER_0_PKT_ADDR},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBERSHIP_PROFILE_LOWER_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBERSHIP_PROFILE_LOWER_PKT_ADDR},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_ADDR},\ + {"FLEX_EDITOR_ARC_ID_DOP_ARID_4", BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_ARID_4},\ + {"FLEX_EDITOR_ARC_ID_DOP_ARID_3", BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_ARID_3},\ + {"FLEX_EDITOR_ARC_ID_DOP_ARID_2", BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_ARID_2},\ + {"FLEX_EDITOR_ARC_ID_DOP_ARID_1", BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_ARID_1},\ + {"FLEX_EDITOR_ARC_ID_DOP_ARID_0", BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_ARID_0},\ + {"HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_7_PKT_ADDR", BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_7_PKT_ADDR},\ + {"HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_6_PKT_ADDR", BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_6_PKT_ADDR},\ + {"HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_5_PKT_ADDR", BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_5_PKT_ADDR},\ + {"HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_4_PKT_ADDR", BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_4_PKT_ADDR},\ + {"HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_3_PKT_ADDR", BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_3_PKT_ADDR},\ + {"HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_2_PKT_ADDR", BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_2_PKT_ADDR},\ + {"HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_1_PKT_ADDR", BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_1_PKT_ADDR},\ + {"HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_0_PKT_ADDR", BCMPKT_TRACE_DOP_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP_HDR_STACK_EDIT_BITMAP_MAP_TABLE_0_PKT_ADDR},\ + {"HDR_STACK_EGR_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX", BCMPKT_TRACE_DOP_HDR_STACK_EGR_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX},\ + {"HDR_STACK_EGR_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_HDR_STACK_EGR_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH},\ + {"HDR_STACK_EGR_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_HDR_STACK_EGR_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"HDR_STACK_ING_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX", BCMPKT_TRACE_DOP_HDR_STACK_ING_LTS_TCAM_INDEX_DOP_LTS_TCAM_POLICY_DATA_HIT_INDEX},\ + {"HDR_STACK_ING_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_HDR_STACK_ING_LTS_TCAM_INDEX_DOP_LTS_TCAM_TCAM_MATCH},\ + {"HDR_STACK_ING_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_HDR_STACK_ING_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA5_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA5_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IPARSER1_HME_STAGE6_DOP_STAGE6_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE6_DOP_STAGE6_HFE_PROFILE_PTR},\ + {"IPARSER1_HME_STAGE6_DOP_STAGE6_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE6_DOP_STAGE6_TCAM_TCAM_MATCH},\ + {"IPARSER1_HME_STAGE6_DOP_STAGE6_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE6_DOP_STAGE6_SHIFT_AMOUNT},\ + {"IPARSER1_HME_STAGE6_DOP_STAGE6_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE6_DOP_STAGE6_PKT_DATA},\ + {"IPARSER1_HME_STAGE7_DOP_STAGE7_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE7_DOP_STAGE7_HFE_PROFILE_PTR},\ + {"IPARSER1_HME_STAGE7_DOP_STAGE7_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE7_DOP_STAGE7_TCAM_TCAM_MATCH},\ + {"IPARSER1_HME_STAGE7_DOP_STAGE7_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE7_DOP_STAGE7_SHIFT_AMOUNT},\ + {"IPARSER1_HME_STAGE7_DOP_STAGE7_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER1_HME_STAGE7_DOP_STAGE7_PKT_DATA},\ + {"IPARSER2_HME_STAGE5_DOP_STAGE5_HFE_PROFILE_PTR", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE5_DOP_STAGE5_HFE_PROFILE_PTR},\ + {"IPARSER2_HME_STAGE5_DOP_STAGE5_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE5_DOP_STAGE5_TCAM_TCAM_MATCH},\ + {"IPARSER2_HME_STAGE5_DOP_STAGE5_SHIFT_AMOUNT", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE5_DOP_STAGE5_SHIFT_AMOUNT},\ + {"IPARSER2_HME_STAGE5_DOP_STAGE5_PKT_DATA", BCMPKT_TRACE_DOP_IPARSER2_HME_STAGE5_DOP_STAGE5_PKT_DATA},\ + {"MEMDB_TCAM_IFTA5_MEM0_0_KEY_DOP_MEM0_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_0_KEY_DOP_MEM0_0_KEY},\ + {"MEMDB_TCAM_IFTA5_MEM0_0_KEY_DOP_MEM0_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_0_KEY_DOP_MEM0_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA5_MEM0_1_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_1_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_TCAM_IFTA5_MEM0_1_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_1_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA5_MEM1_0_KEY_DOP_MEM1_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_0_KEY_DOP_MEM1_0_KEY},\ + {"MEMDB_TCAM_IFTA5_MEM1_0_KEY_DOP_MEM1_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_0_KEY_DOP_MEM1_0_PKT_RD},\ + {"MEMDB_TCAM_IFTA5_MEM1_1_KEY_DOP_MEM1_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_1_KEY_DOP_MEM1_1_KEY},\ + {"MEMDB_TCAM_IFTA5_MEM1_1_KEY_DOP_MEM1_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_1_KEY_DOP_MEM1_1_PKT_RD},\ + {"MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_0_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_0_TCAM_MATCH},\ + {"MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_1_MATCH_INDEX},\ + {"MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP_MEM1_1_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_C_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_C_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_B_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_B_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_A_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_TCAM_0_A_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_C_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_C_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_B_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_B_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_A_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_TCAM_1_A_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_C_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_C_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_B_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_B_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_A_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_TCAM_2_A_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_C_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_C_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_B_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_B_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_A_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_TCAM_3_A_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_C_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_C_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_B_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_B_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_A_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_TCAM_4_A_FINAL_TCAM_MATCH},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_1_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_1_PKT_ADDR},\ + {"APU_EGR0_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0", BCMPKT_TRACE_DOP_APU_EGR0_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0},\ + {"APU_EGR0_APU_TCAM_KEY_DOP_TCAM_KEY", BCMPKT_TRACE_DOP_APU_EGR0_APU_TCAM_KEY_DOP_TCAM_KEY},\ + {"APU_EGR0_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY", BCMPKT_TRACE_DOP_APU_EGR0_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY},\ + {"APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_APU_EGR0_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"APU_EGR1_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0", BCMPKT_TRACE_DOP_APU_EGR1_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0},\ + {"APU_EGR1_APU_TCAM_KEY_DOP_TCAM_KEY", BCMPKT_TRACE_DOP_APU_EGR1_APU_TCAM_KEY_DOP_TCAM_KEY},\ + {"APU_EGR1_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY", BCMPKT_TRACE_DOP_APU_EGR1_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY},\ + {"APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_APU_EGR1_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"APU_ING0_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0", BCMPKT_TRACE_DOP_APU_ING0_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0},\ + {"APU_ING0_APU_TCAM_KEY_DOP_TCAM_KEY", BCMPKT_TRACE_DOP_APU_ING0_APU_TCAM_KEY_DOP_TCAM_KEY},\ + {"APU_ING0_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY", BCMPKT_TRACE_DOP_APU_ING0_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY},\ + {"APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_APU_ING0_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"APU_ING1_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0", BCMPKT_TRACE_DOP_APU_ING1_APU_TCAM_HIT_VECTOR_DOP_HIT_VECTOR_3_HIT_VECTOR_2_HIT_VECTOR_1_HIT_VECTOR_0},\ + {"APU_ING1_APU_TCAM_KEY_DOP_TCAM_KEY", BCMPKT_TRACE_DOP_APU_ING1_APU_TCAM_KEY_DOP_TCAM_KEY},\ + {"APU_ING1_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY", BCMPKT_TRACE_DOP_APU_ING1_APU_TCAM_POLICY_DOP_FINAL_TCAM_POLICY},\ + {"APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_APU_ING1_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_CTRL_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_CTRL_PRE_SEL_MUX_OUT},\ + {"ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_SINGLE_POINTER_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_SINGLE_POINTER_TABLE_PKT_ADDR},\ + {"ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_ADDR},\ + {"ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_SHUFFLE_TABLE_INDEX", BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_SHUFFLE_TABLE_INDEX},\ + {"ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_SINGLE_PTR_TBL_RD", BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_SINGLE_PTR_TBL_RD},\ + {"ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_RD", BCMPKT_TRACE_DOP_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_RD},\ + {"ECMP_LEVEL0_MEMBER_INDEX_DOP_MEMBER_TBL_RD", BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_MEMBER_TBL_RD},\ + {"ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_OFFSET", BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_OFFSET},\ + {"ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_INDEX", BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_INDEX},\ + {"ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MODE", BCMPKT_TRACE_DOP_ECMP_LEVEL0_MEMBER_INDEX_DOP_ECMP_MODE},\ + {"ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_MODULO_OFFSET", BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_MODULO_OFFSET},\ + {"ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_HASH", BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_HASH},\ + {"ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_ECMP_MEMBER_TBL_INDEX", BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_ECMP_MEMBER_TBL_INDEX},\ + {"ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_MEMBER_TBL_RD", BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_MEMBER_TBL_RD},\ + {"ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_ECMP_MEMBER_TBL_OFFSET", BCMPKT_TRACE_DOP_ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP_ALT_ECMP_MEMBER_TBL_OFFSET},\ + {"ECMP_LEVEL1_DLB_NHI_DOP_DLB_NHI_VALID", BCMPKT_TRACE_DOP_ECMP_LEVEL1_DLB_NHI_DOP_DLB_NHI_VALID},\ + {"ECMP_LEVEL1_DLB_NHI_DOP_DLB_NHI", BCMPKT_TRACE_DOP_ECMP_LEVEL1_DLB_NHI_DOP_DLB_NHI},\ + {"ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_CTRL_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_CTRL_PRE_SEL_MUX_OUT},\ + {"ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_ADDR},\ + {"ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_SHUFFLE_TABLE_INDEX", BCMPKT_TRACE_DOP_ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_SHUFFLE_TABLE_INDEX},\ + {"ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_RD", BCMPKT_TRACE_DOP_ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP_GROUP_TABLE_PKT_RD},\ + {"ECMP_LEVEL1_MEMBER_INDEX_DOP_MEMBER_TBL_RD", BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_MEMBER_TBL_RD},\ + {"ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_OFFSET", BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_OFFSET},\ + {"ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_INDEX", BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MEMBER_TBL_INDEX},\ + {"ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MODE", BCMPKT_TRACE_DOP_ECMP_LEVEL1_MEMBER_INDEX_DOP_ECMP_MODE},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_0_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_0_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_0_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_1_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_2_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_1_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_1_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_2_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP_ZONE_0_LOGICAL_TCAM_2_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP_ZONE_0_PHYSICAL_TCAM_0_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP_ZONE_0_PHYSICAL_TCAM_0_KEY},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP_ZONE_0_PHYSICAL_TCAM_0_PKT_RD", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP_ZONE_0_PHYSICAL_TCAM_0_PKT_RD},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_0_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_0_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_2_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_2_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_0_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_1_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_1_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_1_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_2_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP_ZONE_1_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP_ZONE_1_PHYSICAL_TCAM_0_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP_ZONE_1_PHYSICAL_TCAM_0_KEY},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP_ZONE_1_PHYSICAL_TCAM_0_PKT_RD", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP_ZONE_1_PHYSICAL_TCAM_0_PKT_RD},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_1_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_1_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_2_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_0_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_2_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_2_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_1_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_0_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP_ZONE_2_LOGICAL_TCAM_0_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_ZONE_2_PHYSICAL_TCAM_0_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_ZONE_2_PHYSICAL_TCAM_0_KEY},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_ZONE_2_PHYSICAL_TCAM_0_PKT_RD", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP_ZONE_2_PHYSICAL_TCAM_0_PKT_RD},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_0_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_0_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_2_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_0_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_2_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_2_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_1_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_1_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP_ZONE_3_LOGICAL_TCAM_1_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP_ZONE_3_PHYSICAL_TCAM_0_PKT_RD", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP_ZONE_3_PHYSICAL_TCAM_0_PKT_RD},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP_ZONE_3_PHYSICAL_TCAM_0_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP_ZONE_3_PHYSICAL_TCAM_0_KEY},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_1_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_1_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_0_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_0_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_2_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_2_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_2_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_0_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_1_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_1_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_1_MATCH_PHYSICAL_TCAM_ID},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_2_FINAL_TCAM_MATCH", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_2_FINAL_TCAM_MATCH},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_0_MATCH_INDEX", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP_ZONE_4_LOGICAL_TCAM_0_MATCH_INDEX},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_ZONE_4_PHYSICAL_TCAM_0_KEY", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_ZONE_4_PHYSICAL_TCAM_0_KEY},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_ZONE_4_PHYSICAL_TCAM_0_PKT_RD", BCMPKT_TRACE_DOP_EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP_ZONE_4_PHYSICAL_TCAM_0_PKT_RD},\ + {"EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_EFSL40_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY", BCMPKT_TRACE_DOP_EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_KEY},\ + {"EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_TCAM_MATCH},\ + {"EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_EFSL41_LTS_TCAM_KEY_DOP_LTS_TCAM_MATCH_INDEX},\ + {"EFTA10_I1T_04_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_EFTA10_I1T_04_INDEX_DOP_LKP0_LTPR_WIN},\ + {"EFTA10_I1T_04_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_EFTA10_I1T_04_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_PROFILE_PTR_3", BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_PROFILE_PTR_3},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_PROFILE_PTR_1", BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_FIELD_BITMAP_PROFILE_PTR_1},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBERSHIP_PROFILE_PKT_RD", BCMPKT_TRACE_DOP_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP_MEMBERSHIP_PROFILE_PKT_RD},\ + {"EGR_MIRROR_ENCAP_1_TABLE_INDEX_DOP_ENCAP_1_TABLE_PKT_RD", BCMPKT_TRACE_DOP_EGR_MIRROR_ENCAP_1_TABLE_INDEX_DOP_ENCAP_1_TABLE_PKT_RD},\ + {"EGR_MIRROR_ENCAP_1_TABLE_INDEX_DOP_ENCAP_1_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_MIRROR_ENCAP_1_TABLE_INDEX_DOP_ENCAP_1_TABLE_PKT_ADDR},\ + {"EGR_MIRROR_ENCAP_TABLE_INDEX_DOP_ENCAP_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_MIRROR_ENCAP_TABLE_INDEX_DOP_ENCAP_TABLE_PKT_ADDR},\ + {"EGR_MIRROR_ENCAP_TABLE_INDEX_DOP_ENCAP_TABLE_PKT_RD", BCMPKT_TRACE_DOP_EGR_MIRROR_ENCAP_TABLE_INDEX_DOP_ENCAP_TABLE_PKT_RD},\ + {"EGR_MIRROR_MIRROR2EDITOR2_BUS_DOP_OUT_EGR_SCR_MIRROR2EDITOR2_BUS", BCMPKT_TRACE_DOP_EGR_MIRROR_MIRROR2EDITOR2_BUS_DOP_OUT_EGR_SCR_MIRROR2EDITOR2_BUS},\ + {"EGR_MIRROR_MIRROR2EDITOR_BUS_DOP_OUT_EGR_SCR_MIRROR2EDITOR_BUS", BCMPKT_TRACE_DOP_EGR_MIRROR_MIRROR2EDITOR_BUS_DOP_OUT_EGR_SCR_MIRROR2EDITOR_BUS},\ + {"EGR_MIRROR_SESSION_CONTROL_TABLE_INDEX_DOP_SESSION_CONTROL_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_MIRROR_SESSION_CONTROL_TABLE_INDEX_DOP_SESSION_CONTROL_TABLE_PKT_ADDR},\ + {"EGR_MIRROR_SESSION_CONTROL_TABLE_INDEX_DOP_SESSION_CONTROL_TABLE_PKT_RD", BCMPKT_TRACE_DOP_EGR_MIRROR_SESSION_CONTROL_TABLE_INDEX_DOP_SESSION_CONTROL_TABLE_PKT_RD},\ + {"EGR_SEQUENCE_MIRROR_SEQUENCE_NUMBER_PROFILE_INDEX_DOP_MIRROR_SEQUENCE_NUMBER_PROFILE_PKT_RD", BCMPKT_TRACE_DOP_EGR_SEQUENCE_MIRROR_SEQUENCE_NUMBER_PROFILE_INDEX_DOP_MIRROR_SEQUENCE_NUMBER_PROFILE_PKT_RD},\ + {"EGR_SEQUENCE_NUMBER_TABLE_INDEX_DOP_NUMBER_TABLE_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_SEQUENCE_NUMBER_TABLE_INDEX_DOP_NUMBER_TABLE_PKT_ADDR},\ + {"EGR_SEQUENCE_NUMBER_TABLE_INDEX_DOP_NUMBER_TABLE_PKT_RD", BCMPKT_TRACE_DOP_EGR_SEQUENCE_NUMBER_TABLE_INDEX_DOP_NUMBER_TABLE_PKT_RD},\ + {"EGR_SEQUENCE_PROFILE_INDEX_DOP_PROFILE_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_SEQUENCE_PROFILE_INDEX_DOP_PROFILE_PKT_ADDR},\ + {"EGR_SEQUENCE_PROFILE_INDEX_DOP_PROFILE_PKT_RD", BCMPKT_TRACE_DOP_EGR_SEQUENCE_PROFILE_INDEX_DOP_PROFILE_PKT_RD},\ + {"EPOST_EPOST_DROP_TRACE_DOP_EGR_TRACE_BUS", BCMPKT_TRACE_DOP_EPOST_EPOST_DROP_TRACE_DOP_EGR_TRACE_BUS},\ + {"EPOST_EPOST_DROP_TRACE_DOP_EGR_DROP_BUS", BCMPKT_TRACE_DOP_EPOST_EPOST_DROP_TRACE_DOP_EGR_DROP_BUS},\ + {"EPRE_EDEV_CONFIG_CPU_DMA_FLEX_WORD_MUX_PROFILE_INDEX_DOP_CPU_DMA_FLEX_WORD_MUX_PROFILE_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_CPU_DMA_FLEX_WORD_MUX_PROFILE_INDEX_DOP_CPU_DMA_FLEX_WORD_MUX_PROFILE_PKT_ADDR},\ + {"EPRE_EDEV_CONFIG_CPU_DMA_FLEX_WORD_MUX_PROFILE_INDEX_DOP_CPU_DMA_FLEX_WORD_MUX_PROFILE_PKT_RD", BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_CPU_DMA_FLEX_WORD_MUX_PROFILE_INDEX_DOP_CPU_DMA_FLEX_WORD_MUX_PROFILE_PKT_RD},\ + {"EPRE_EDEV_CONFIG_EGR_TABLE_INDEX_UPDATE_PROFILE_INDEX_DOP_EGR_TABLE_INDEX_UPDATE_PROFILE_PKT_RD", BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_EGR_TABLE_INDEX_UPDATE_PROFILE_INDEX_DOP_EGR_TABLE_INDEX_UPDATE_PROFILE_PKT_RD},\ + {"EPRE_EDEV_CONFIG_MIRROR_ATTRIBUTES_TABLE_INDEX_DOP_MIRROR_ATTRIBUTES_TABLE_PKT_RD", BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_MIRROR_ATTRIBUTES_TABLE_INDEX_DOP_MIRROR_ATTRIBUTES_TABLE_PKT_RD},\ + {"EPRE_PARSER_ZONE_REMAP_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP_FIELD_EXTRACTION_PROFILE_CONTROL_PKT_RD", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP_FIELD_EXTRACTION_PROFILE_CONTROL_PKT_RD},\ + {"EPRE_PARSER_ZONE_REMAP_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP_FIELD_EXTRACTION_PROFILE_CONTROL_PKT_ADDR", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP_FIELD_EXTRACTION_PROFILE_CONTROL_PKT_ADDR},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD", BCMPKT_TRACE_DOP_EPRE_PARSER_ZONE_REMAP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_PKT_RD},\ + {"FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_KEY", BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_KEY},\ + {"FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_MATCH_INDEX},\ + {"FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_PKT_RD", BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_PKT_RD},\ + {"FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_TCAM_MATCH},\ + {"FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_KEY", BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_KEY},\ + {"FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_MATCH_INDEX},\ + {"FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_PKT_RD", BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_PKT_RD},\ + {"FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP_L3_TYPE_TCAM_TCAM_MATCH},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_8_DOP_COUNTER_EOP_BUFFER_8_PKT_WDATA_COUNTER_EOP_BUFFER_8_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_8_DOP_COUNTER_EOP_BUFFER_8_PKT_WDATA_COUNTER_EOP_BUFFER_8_PKT_WR},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_9_DOP_COUNTER_EOP_BUFFER_9_PKT_WDATA_COUNTER_EOP_BUFFER_9_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_9_DOP_COUNTER_EOP_BUFFER_9_PKT_WDATA_COUNTER_EOP_BUFFER_9_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_12_DOP_COUNTER_EOP_BUFFER_12_PKT_WDATA_COUNTER_EOP_BUFFER_12_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_12_DOP_COUNTER_EOP_BUFFER_12_PKT_WDATA_COUNTER_EOP_BUFFER_12_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_13_DOP_COUNTER_EOP_BUFFER_13_PKT_WDATA_COUNTER_EOP_BUFFER_13_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_13_DOP_COUNTER_EOP_BUFFER_13_PKT_WDATA_COUNTER_EOP_BUFFER_13_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_14_DOP_COUNTER_EOP_BUFFER_14_PKT_WDATA_COUNTER_EOP_BUFFER_14_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_14_DOP_COUNTER_EOP_BUFFER_14_PKT_WDATA_COUNTER_EOP_BUFFER_14_PKT_WR},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_15_DOP_COUNTER_EOP_BUFFER_15_PKT_WDATA_COUNTER_EOP_BUFFER_15_PKT_WR", BCMPKT_TRACE_DOP_FLEX_CTR_ING_COUNTER_EOP_BUFFER_15_DOP_COUNTER_EOP_BUFFER_15_PKT_WDATA_COUNTER_EOP_BUFFER_15_PKT_WR},\ + {"FLEX_EDITOR_ARC_ID_DOP_MIRROR_0_PROFILE_PTR", BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_MIRROR_0_PROFILE_PTR},\ + {"FLEX_EDITOR_ARC_ID_DOP_TRUNCATE_PROFILE_PTR", BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_TRUNCATE_PROFILE_PTR},\ + {"FLEX_EDITOR_ARC_ID_DOP_SOP", BCMPKT_TRACE_DOP_FLEX_EDITOR_ARC_ID_DOP_SOP},\ + {"IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_MATCH},\ + {"IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_MATCH},\ + {"IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP3_LTS_TCAM_MATCH},\ + {"IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE", BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP0_LTS_TCAM_DATA_KEY_TYPE},\ + {"IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID", BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP2_LTS_TCAM_DATA_LOGICAL_TABLE_ID},\ + {"IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH", BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP_LKP1_LTS_TCAM_MATCH},\ + {"IFTA105_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT", BCMPKT_TRACE_DOP_IFTA105_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP_LTS_PRE_SEL_MUX_OUT},\ + {"IFTA130_I1T_04_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA130_I1T_04_INDEX_DOP_LKP0_LTPR_WIN},\ + {"IFTA130_I1T_04_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA130_I1T_04_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IFTA70_I1T_02_INDEX_DOP_LKP0_LTPR_WIN", BCMPKT_TRACE_DOP_IFTA70_I1T_02_INDEX_DOP_LKP0_LTPR_WIN},\ + {"IFTA70_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT", BCMPKT_TRACE_DOP_IFTA70_I1T_02_INDEX_DOP_LKP0_TILE_KEY_COMPRESSION_MUX_OUT},\ + {"IPOST_CPU_COS_CPU_COS_MAP_TCAM_KEY_DOP_CPU_COS_MAP_TCAM_PKT_RD", BCMPKT_TRACE_DOP_IPOST_CPU_COS_CPU_COS_MAP_TCAM_KEY_DOP_CPU_COS_MAP_TCAM_PKT_RD},\ + {"IPOST_LAG_L2OIF_INDEX_DOP_L2OIF_PKT_RD", BCMPKT_TRACE_DOP_IPOST_LAG_L2OIF_INDEX_DOP_L2OIF_PKT_RD},\ + {"IPOST_LAG_L2OIF_INDEX_DOP_L2OIF_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_LAG_L2OIF_INDEX_DOP_L2OIF_PKT_ADDR},\ + {"IPOST_LAG_LAG_GROUP_INDEX_DOP_LAG_GROUP_PKT_RD", BCMPKT_TRACE_DOP_IPOST_LAG_LAG_GROUP_INDEX_DOP_LAG_GROUP_PKT_RD},\ + {"IPOST_LAG_LAG_GROUP_INDEX_DOP_LAG_GROUP_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_LAG_LAG_GROUP_INDEX_DOP_LAG_GROUP_PKT_ADDR},\ + {"IPOST_LAG_LAG_MEMBER_INDEX_DOP_LAG_MEMBER_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_LAG_LAG_MEMBER_INDEX_DOP_LAG_MEMBER_PKT_ADDR},\ + {"IPOST_LAG_LAG_MEMBER_INDEX_DOP_LAG_MEMBER_PKT_RD", BCMPKT_TRACE_DOP_IPOST_LAG_LAG_MEMBER_INDEX_DOP_LAG_MEMBER_PKT_RD},\ + {"IPOST_LAG_NONUCAST_LAG_BLOCK_MASK_INDEX_DOP_NONUCAST_LAG_BLOCK_MASK_PKT_RD", BCMPKT_TRACE_DOP_IPOST_LAG_NONUCAST_LAG_BLOCK_MASK_INDEX_DOP_NONUCAST_LAG_BLOCK_MASK_PKT_RD},\ + {"IPOST_LAG_NONUCAST_LAG_BLOCK_MASK_INDEX_DOP_NONUCAST_LAG_BLOCK_MASK_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_LAG_NONUCAST_LAG_BLOCK_MASK_INDEX_DOP_NONUCAST_LAG_BLOCK_MASK_PKT_ADDR},\ + {"IPOST_LAG_SYSTEM_LAG_GROUP_ID_BMAP_DOP_SYSTEM_LAG_GROUP_ID_BMAP", BCMPKT_TRACE_DOP_IPOST_LAG_SYSTEM_LAG_GROUP_ID_BMAP_DOP_SYSTEM_LAG_GROUP_ID_BMAP},\ + {"IPOST_LAG_SYSTEM_LAG_MEMBER_INDEX_DOP_SYSTEM_LAG_MEMBER_INDEX", BCMPKT_TRACE_DOP_IPOST_LAG_SYSTEM_LAG_MEMBER_INDEX_DOP_SYSTEM_LAG_MEMBER_INDEX},\ + {"IPOST_LAG_SYSTEM_PORT_INDEX_DOP_SYSTEM_PORT_PKT_RD", BCMPKT_TRACE_DOP_IPOST_LAG_SYSTEM_PORT_INDEX_DOP_SYSTEM_PORT_PKT_RD},\ + {"IPOST_LAG_SYSTEM_PORT_INDEX_DOP_SYSTEM_PORT_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_LAG_SYSTEM_PORT_INDEX_DOP_SYSTEM_PORT_PKT_ADDR},\ + {"IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_CHECK_BITMAP_INDEX_DOP_MEMBERSHIP_CHECK_BITMAP_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_CHECK_BITMAP_INDEX_DOP_MEMBERSHIP_CHECK_BITMAP_PKT_RD},\ + {"IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_CHECK_BITMAP_INDEX_DOP_MEMBERSHIP_CHECK_BITMAP_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_CHECK_BITMAP_INDEX_DOP_MEMBERSHIP_CHECK_BITMAP_PKT_ADDR},\ + {"IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_LOWER_INDEX_DOP_MEMBERSHIP_STATE_LOWER_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_LOWER_INDEX_DOP_MEMBERSHIP_STATE_LOWER_PKT_RD},\ + {"IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_LOWER_INDEX_DOP_MEMBERSHIP_STATE_LOWER_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_LOWER_INDEX_DOP_MEMBERSHIP_STATE_LOWER_PKT_ADDR},\ + {"IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_UPPER_INDEX_DOP_MEMBERSHIP_STATE_UPPER_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_UPPER_INDEX_DOP_MEMBERSHIP_STATE_UPPER_PKT_ADDR},\ + {"IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_UPPER_INDEX_DOP_MEMBERSHIP_STATE_UPPER_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_UPPER_INDEX_DOP_MEMBERSHIP_STATE_UPPER_PKT_RD},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_6_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_6_PKT_RD},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_3_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_3_PKT_ADDR},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_5_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_5_PKT_RD},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_2_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_2_PKT_RD},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_3_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_3_PKT_RD},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_1_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_1_PKT_ADDR},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_6_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_6_PKT_ADDR},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_4_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_4_PKT_RD},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_7_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_7_PKT_RD},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_0_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_0_PKT_ADDR},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_1_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_1_PKT_RD},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_2_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_2_PKT_ADDR},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_0_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_0_PKT_RD},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_5_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_5_PKT_ADDR},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_4_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_4_PKT_ADDR},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_7_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP_MIRROR_SESSION_7_PKT_ADDR},\ + {"IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_0_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_0_PKT_ADDR},\ + {"IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_3_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_3_PKT_ADDR},\ + {"IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_2_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_2_PKT_ADDR},\ + {"IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_0_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_0_PKT_RD},\ + {"IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_1_PKT_ADDR", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_1_PKT_ADDR},\ + {"IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_2_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_2_PKT_RD},\ + {"IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_1_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_1_PKT_RD},\ + {"IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_3_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP_SAMPLER_POOL_3_PKT_RD},\ + {"IPOST_M_MPB_CCBI_FIXED_CCBI_B_BUS_DOP_OUT_CCBI_B_BUS", BCMPKT_TRACE_DOP_IPOST_M_MPB_CCBI_FIXED_CCBI_B_BUS_DOP_OUT_CCBI_B_BUS},\ + {"IPOST_M_MPB_CCBI_FIXED_CCBI_MC_BUS_DOP_OUT_CCBI_MBUS", BCMPKT_TRACE_DOP_IPOST_M_MPB_CCBI_FIXED_CCBI_MC_BUS_DOP_OUT_CCBI_MBUS},\ + {"IPOST_M_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP_OUT_MPB_FIXED_BUS", BCMPKT_TRACE_DOP_IPOST_M_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP_OUT_MPB_FIXED_BUS},\ + {"IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_TCAM_MATCH},\ + {"IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_MATCH_INDEX},\ + {"IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY", BCMPKT_TRACE_DOP_IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY},\ + {"IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_PKT_RD", BCMPKT_TRACE_DOP_IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_PKT_RD},\ + {"IPOST_M_MPB_ENCODE_MPB_FLEX_BUS_DOP_OUT_MPB_FLEX_BUS", BCMPKT_TRACE_DOP_IPOST_M_MPB_ENCODE_MPB_FLEX_BUS_DOP_OUT_MPB_FLEX_BUS},\ + {"IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD", BCMPKT_TRACE_DOP_IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_KEY_DOP_LTS_TCAM_PKT_RD},\ + {"IPOST_TRACE_DROP_EVENT_ING_DROP_BUS_DOP_ING_DROP_BUS", BCMPKT_TRACE_DOP_IPOST_TRACE_DROP_EVENT_ING_DROP_BUS_DOP_ING_DROP_BUS},\ + {"IPOST_TRACE_DROP_EVENT_ING_TRACE_BUS_DOP_ING_TRACE_BUS", BCMPKT_TRACE_DOP_IPOST_TRACE_DROP_EVENT_ING_TRACE_BUS_DOP_ING_TRACE_BUS},\ + {"MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_BITMAP_PKT_ADDR", BCMPKT_TRACE_DOP_MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_BITMAP_PKT_ADDR},\ + {"MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_MEMBER_INDEX", BCMPKT_TRACE_DOP_MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_MEMBER_INDEX},\ + {"MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_STATE_PROFILE_LOWER_PKT_RD", BCMPKT_TRACE_DOP_MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_STATE_PROFILE_LOWER_PKT_RD},\ + {"MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_STATE_PROFILE_LOWER_PKT_ADDR", BCMPKT_TRACE_DOP_MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP_STATE_PROFILE_LOWER_PKT_ADDR},\ + {"MEMDB_IFTA105_MEM0_0_KEY_DOP_MEM0_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_0_KEY_DOP_MEM0_0_PKT_RD},\ + {"MEMDB_IFTA105_MEM0_0_KEY_DOP_MEM0_0_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_0_KEY_DOP_MEM0_0_KEY},\ + {"MEMDB_IFTA105_MEM0_1_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_1_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_IFTA105_MEM0_1_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_1_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_IFTA105_MEM0_2_KEY_DOP_MEM0_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_2_KEY_DOP_MEM0_2_PKT_RD},\ + {"MEMDB_IFTA105_MEM0_2_KEY_DOP_MEM0_2_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_2_KEY_DOP_MEM0_2_KEY},\ + {"MEMDB_IFTA105_MEM0_3_KEY_DOP_MEM0_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_3_KEY_DOP_MEM0_3_PKT_RD},\ + {"MEMDB_IFTA105_MEM0_3_KEY_DOP_MEM0_3_KEY", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_3_KEY_DOP_MEM0_3_KEY},\ + {"MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX},\ + {"MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX},\ + {"MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH},\ + {"MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX},\ + {"MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH},\ + {"MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH},\ + {"MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH},\ + {"MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_IFTA105_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX},\ + {"MINTERM_AGG_MINTERM_AGG2EDIT_CTRL_BUS_DOP_OUT_EGR_SCR_MINTERM_AGG2EDIT_CTRL_BUS", BCMPKT_TRACE_DOP_MINTERM_AGG_MINTERM_AGG2EDIT_CTRL_BUS_DOP_OUT_EGR_SCR_MINTERM_AGG2EDIT_CTRL_BUS},\ + {"RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_0_PKT_RD", BCMPKT_TRACE_DOP_RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_0_PKT_RD},\ + {"RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_1_PKT_ADDR", BCMPKT_TRACE_DOP_RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_1_PKT_ADDR},\ + {"RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_1_PKT_RD", BCMPKT_TRACE_DOP_RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_1_PKT_RD},\ + {"RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_0_PKT_ADDR", BCMPKT_TRACE_DOP_RANGE_MAP_PROFILE_INDEX_DOP_PROFILE_0_PKT_ADDR},\ + {"SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_TCAM_MATCH", BCMPKT_TRACE_DOP_SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_TCAM_MATCH},\ + {"SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_MATCH_INDEX", BCMPKT_TRACE_DOP_SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_MATCH_INDEX},\ + {"SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_PKT_RD", BCMPKT_TRACE_DOP_SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_PKT_RD},\ + {"SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_KEY", BCMPKT_TRACE_DOP_SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP_LTS_TCAM_ONLY_KEY},\ + {"SIMPLE_MATCH_TABLE_INDEX_DOP_TABLE_MATCH_INDEX", BCMPKT_TRACE_DOP_SIMPLE_MATCH_TABLE_INDEX_DOP_TABLE_MATCH_INDEX},\ + {"SIMPLE_MATCH_TABLE_INDEX_DOP_TABLE_TCAM_MATCH", BCMPKT_TRACE_DOP_SIMPLE_MATCH_TABLE_INDEX_DOP_TABLE_TCAM_MATCH},\ + {"SIMPLE_MATCH_TABLE_KEY_DOP_TABLE_KEY", BCMPKT_TRACE_DOP_SIMPLE_MATCH_TABLE_KEY_DOP_TABLE_KEY},\ + {"IPOST_CPU_COS_MAP_TCAM_INDEX_DOP_MAP_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_IPOST_CPU_COS_MAP_TCAM_INDEX_DOP_MAP_TCAM_MATCH_INDEX},\ + {"IPOST_CPU_COS_MAP_TCAM_INDEX_DOP_MAP_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_IPOST_CPU_COS_MAP_TCAM_INDEX_DOP_MAP_TCAM_TCAM_MATCH},\ + {"IPOST_CPU_COS_MAP_TCAM_KEY_DOP_MAP_TCAM_KEY", BCMPKT_TRACE_DOP_IPOST_CPU_COS_MAP_TCAM_KEY_DOP_MAP_TCAM_KEY},\ + {"IPOST_CPU_COS_MAP_TCAM_KEY_DOP_MAP_TCAM_PKT_RD", BCMPKT_TRACE_DOP_IPOST_CPU_COS_MAP_TCAM_KEY_DOP_MAP_TCAM_PKT_RD},\ + {"IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_PKT_RD", BCMPKT_TRACE_DOP_IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP_ING_MPB_FLEX_DATA_SELECT_TCAM_PKT_RD},\ + {"EFTA10_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT", BCMPKT_TRACE_DOP_EFTA10_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT},\ + {"EFTA10_I1T_01_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT", BCMPKT_TRACE_DOP_EFTA10_I1T_01_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT},\ + {"EFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT", BCMPKT_TRACE_DOP_EFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT},\ + {"EFTA20_I1T_01_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT", BCMPKT_TRACE_DOP_EFTA20_I1T_01_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT},\ + {"IFTA130_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT", BCMPKT_TRACE_DOP_IFTA130_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT},\ + {"IFTA50_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT", BCMPKT_TRACE_DOP_IFTA50_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT},\ + {"IFTA70_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT", BCMPKT_TRACE_DOP_IFTA70_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT},\ + {"IFTA70_I1T_01_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT", BCMPKT_TRACE_DOP_IFTA70_I1T_01_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"IDEV_CONFIG_DEBUG_CAPTURE_DATA_DOP_DEBUG_CAPTURE_PKT_WDATA", BCMPKT_TRACE_DOP_IDEV_CONFIG_DEBUG_CAPTURE_DATA_DOP_DEBUG_CAPTURE_PKT_WDATA},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"HDR_STACK_LITE_DEBUG_CAPTURE_DATA_DOP_DEBUG_CAPTURE_PKT_WDATA", BCMPKT_TRACE_DOP_HDR_STACK_LITE_DEBUG_CAPTURE_DATA_DOP_DEBUG_CAPTURE_PKT_WDATA},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_3_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_2", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_2},\ + {"VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_1", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_1},\ + {"VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_1", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_1},\ + {"VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_1", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_1},\ + {"VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_3", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_3},\ + {"VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_3", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_3},\ + {"VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_0", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_0},\ + {"VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_0", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_0},\ + {"VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_0", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_0},\ + {"VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_2", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_TABLE_ID_2},\ + {"VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_2", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_KEY_2},\ + {"VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_3", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_KEY_DOP_FINAL_VALID_3},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP_MPB_FLEX_BUS", BCMPKT_TRACE_DOP_EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP_MPB_FLEX_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_1_KEY_PROFILE_PKT_ADDR", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_1_KEY_PROFILE_PKT_ADDR},\ + {"VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_2_KEY_PROFILE_PKT_RD", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_2_KEY_PROFILE_PKT_RD},\ + {"VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_3_KEY_PROFILE_PKT_ADDR", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_3_KEY_PROFILE_PKT_ADDR},\ + {"VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_3_KEY_PROFILE_PKT_RD", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_3_KEY_PROFILE_PKT_RD},\ + {"VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_2_KEY_PROFILE_PKT_ADDR", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_2_KEY_PROFILE_PKT_ADDR},\ + {"VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_0_KEY_PROFILE_PKT_ADDR", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_0_KEY_PROFILE_PKT_ADDR},\ + {"VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_0_KEY_PROFILE_PKT_RD", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_0_KEY_PROFILE_PKT_RD},\ + {"VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_1_KEY_PROFILE_PKT_RD", BCMPKT_TRACE_DOP_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP_VCA_READ_1_KEY_PROFILE_PKT_RD},\ + {"VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_0", BCMPKT_TRACE_DOP_VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_0},\ + {"VCA_IF_RESPONSE_VCA_DATA_DOP_BITP_MUX_OUT", BCMPKT_TRACE_DOP_VCA_IF_RESPONSE_VCA_DATA_DOP_BITP_MUX_OUT},\ + {"VCA_IF_RESPONSE_VCA_DATA_DOP_BOTP_MUX_IN", BCMPKT_TRACE_DOP_VCA_IF_RESPONSE_VCA_DATA_DOP_BOTP_MUX_IN},\ + {"VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_2", BCMPKT_TRACE_DOP_VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_2},\ + {"VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_1", BCMPKT_TRACE_DOP_VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_1},\ + {"VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_3", BCMPKT_TRACE_DOP_VCA_IF_RESPONSE_VCA_DATA_DOP_VCA_ERROR_3},\ + {"EGR_MIRROR_SEQUENCE_NUMBER_INDEX_DOP_SEQUENCE_NUMBER_PKT_RD", BCMPKT_TRACE_DOP_EGR_MIRROR_SEQUENCE_NUMBER_INDEX_DOP_SEQUENCE_NUMBER_PKT_RD},\ + {"EGR_MIRROR_SEQUENCE_NUMBER_INDEX_DOP_SEQUENCE_NUMBER_PKT_ADDR", BCMPKT_TRACE_DOP_EGR_MIRROR_SEQUENCE_NUMBER_INDEX_DOP_SEQUENCE_NUMBER_PKT_ADDR},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_0_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"IFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT", BCMPKT_TRACE_DOP_IFTA20_I1T_00_INDEX_DOP_LKP0_TILE_KEY_MUX_OUT},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_1_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EPRE_EDEV_CONFIG_MPB_FIXED_DOP_MPB_FIXED_BUS", BCMPKT_TRACE_DOP_EPRE_EDEV_CONFIG_MPB_FIXED_DOP_MPB_FIXED_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_2_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_TRUNCATE_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS", BCMPKT_TRACE_DOP_EDIT_CTRL_EDIT_CTRL2EDITOR_TRUNCATE_PROFILE_PTR_DOP_OUT_EGR_SCR_EDIT_CTRL2EDITOR_BUS},\ + {"C7_DOP_VFI_2INDEX", BCMPKT_TRACE_DOP_C7_DOP_VFI_2INDEX},\ + {"EFPMOD_MISC_DOP_CHANGE_DSCP", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_DSCP},\ + {"EFPMOD_MISC_DOP_LOOPBACK_PROFILE_HIGH_STR_INDEX", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_LOOPBACK_PROFILE_HIGH_STR_INDEX},\ + {"EFPMOD_MISC_DOP_ADD_EGRESS_TAIL_TS", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_ADD_EGRESS_TAIL_TS},\ + {"EFPMOD_MISC_DOP_LOOPBACK_PROFILE_NEXT_STR_INDEX", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_LOOPBACK_PROFILE_NEXT_STR_INDEX},\ + {"EFPMOD_MISC_DOP_CHANGE_MPLS_EXP", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_MPLS_EXP},\ + {"EFPMOD_MISC_DOP_CHANGE_VXLAN_FILEDS", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_VXLAN_FILEDS},\ + {"EFPMOD_MISC_DOP_CHANGE_OUTER_TPID", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_OUTER_TPID},\ + {"EFPMOD_MISC_DOP_CHANGE_OUTER_VLAN_TAG", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_OUTER_VLAN_TAG},\ + {"EFPMOD_MISC_DOP_ADD_INGRESS_TAIL_TS", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_ADD_INGRESS_TAIL_TS},\ + {"EFPMOD_MISC_DOP_UPDATE_CPU_DMA", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_UPDATE_CPU_DMA},\ + {"EFPMOD_MISC_DOP_REPLACE_SRV6_FIELDS", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_REPLACE_SRV6_FIELDS},\ + {"EFPMOD_MISC_DOP_CHANGE_NTP_TC", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_NTP_TC},\ + {"EFPMOD_MISC_DOP_CHNAGE_LOOPBACK_FILEDS", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHNAGE_LOOPBACK_FILEDS},\ + {"EFPMOD_MISC_DOP_RECALCULATE_IP_CHECKSUM", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_RECALCULATE_IP_CHECKSUM},\ + {"EFPMOD_MISC_DOP_EPRC_COPY_TYPE_1", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_EPRC_COPY_TYPE_1},\ + {"EFPMOD_MISC_DOP_EPRC_COPY_VALID_1", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_EPRC_COPY_VALID_1},\ + {"EFPMOD_MISC_DOP_EPRC_COPY_VALID_0", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_EPRC_COPY_VALID_0},\ + {"EFPMOD_MISC_DOP_CHANGE_GSH_FILEDS", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_GSH_FILEDS},\ + {"EFPMOD_MISC_DOP_EP_POWER_ACTIVITY_MONITOR_FLOW_INDEX", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_EP_POWER_ACTIVITY_MONITOR_FLOW_INDEX},\ + {"EFPMOD_MISC_DOP_CHANGE_1588_CORRECTION_FIELD", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_CHANGE_1588_CORRECTION_FIELD},\ + {"EFPMOD_MISC_DOP_EPRC_COPY_TYPE_0", BCMPKT_TRACE_DOP_EFPMOD_MISC_DOP_EPRC_COPY_TYPE_0},\ + {"EFPPARS_EFP_RANGE_CHECK_DOPS_EFP_RANGE_CHECK_BM", BCMPKT_TRACE_DOP_EFPPARS_EFP_RANGE_CHECK_DOPS_EFP_RANGE_CHECK_BM},\ + {"EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_1", BCMPKT_TRACE_DOP_EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_1},\ + {"EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_3", BCMPKT_TRACE_DOP_EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_3},\ + {"EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_2", BCMPKT_TRACE_DOP_EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_2},\ + {"EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_0", BCMPKT_TRACE_DOP_EFP_KEY_LOOKUP_DOP_EFP_KEY_LOOKUP_0},\ + {"EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_2", BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_2},\ + {"EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_3", BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_3},\ + {"EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_0", BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_0},\ + {"EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_1", BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_POLICY_INDEX_LOOKUP_1},\ + {"EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_1", BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_1},\ + {"EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_0", BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_0},\ + {"EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_3", BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_3},\ + {"EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_2", BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_PHYSICAL_SLICE_FOR_VIRTUAL_LOOKUP_2},\ + {"EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_0", BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_0},\ + {"EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_1", BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_1},\ + {"EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_2", BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_2},\ + {"EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_3", BCMPKT_TRACE_DOP_EFP_VIRTUAL_SLICE_LOOKUP_DOP_EFP_VIRTUAL_SLICE_HIT_3},\ + {"EPARS_GROUP_4_DOPS_UNDERLAY_L3_OIF", BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_UNDERLAY_L3_OIF},\ + {"EPARS_GROUP_4_DOPS_OVERLAY_NHI_VALID", BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_OVERLAY_NHI_VALID},\ + {"EPARS_GROUP_4_DOPS_UNDERLAY_NHI_VALID", BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_UNDERLAY_NHI_VALID},\ + {"EPARS_GROUP_4_DOPS_OVERLAY_NHI", BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_OVERLAY_NHI},\ + {"EPARS_GROUP_4_DOPS_DVP", BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_DVP},\ + {"EPARS_GROUP_4_DOPS_OVERLAY_L3_OIF_VALID", BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_OVERLAY_L3_OIF_VALID},\ + {"EPARS_GROUP_4_DOPS_UNDERLAY_NHI", BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_UNDERLAY_NHI},\ + {"EPARS_GROUP_4_DOPS_OVERLAY_L3_OIF", BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_OVERLAY_L3_OIF},\ + {"EPARS_GROUP_4_DOPS_UNDERLAY_L3_OIF_VALID", BCMPKT_TRACE_DOP_EPARS_GROUP_4_DOPS_UNDERLAY_L3_OIF_VALID},\ + {"EPARS_GROUP_9_1_DOPS_OVERLAY_EGR_VFI", BCMPKT_TRACE_DOP_EPARS_GROUP_9_1_DOPS_OVERLAY_EGR_VFI},\ + {"EPARS_GROUP_9_1_DOPS_UNDERLAY_EGR_VFI", BCMPKT_TRACE_DOP_EPARS_GROUP_9_1_DOPS_UNDERLAY_EGR_VFI},\ + {"EPARS_GROUP_9_2_DOPS_PCBE_EGRESS_PORT", BCMPKT_TRACE_DOP_EPARS_GROUP_9_2_DOPS_PCBE_EGRESS_PORT},\ + {"EPARS_GROUP_9_2_DOPS_MPLS_PSN_INDEX", BCMPKT_TRACE_DOP_EPARS_GROUP_9_2_DOPS_MPLS_PSN_INDEX},\ + {"EPARS_GROUP_9_2_DOPS_L3_TUNNEL_INDEX", BCMPKT_TRACE_DOP_EPARS_GROUP_9_2_DOPS_L3_TUNNEL_INDEX},\ + {"EPARS_GROUP_EGR_ADAPT_1_DOPS_EGR_ADAPT_LOOKUP_DONE", BCMPKT_TRACE_DOP_EPARS_GROUP_EGR_ADAPT_1_DOPS_EGR_ADAPT_LOOKUP_DONE},\ + {"EPARS_GROUP_EGR_ADAPT_1_DOPS_EGR_ADAPT_KEY", BCMPKT_TRACE_DOP_EPARS_GROUP_EGR_ADAPT_1_DOPS_EGR_ADAPT_KEY},\ + {"EPARS_GROUP_EGR_ADAPT_2_DOPS_EGR_ADAPT_HIT", BCMPKT_TRACE_DOP_EPARS_GROUP_EGR_ADAPT_2_DOPS_EGR_ADAPT_HIT},\ + {"EPARS_GROUP_EGR_ADAPT_2_DOPS_EGR_ADAPT_INDEX", BCMPKT_TRACE_DOP_EPARS_GROUP_EGR_ADAPT_2_DOPS_EGR_ADAPT_INDEX},\ + {"EPMOD_MISC_DOP_SRV6_PATH_TRACE", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_SRV6_PATH_TRACE},\ + {"EPMOD_MISC_DOP_REPLACE_OUTER_VLAN", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REPLACE_OUTER_VLAN},\ + {"EPMOD_MISC_DOP_ADD_L3_INSTR_HDR", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_L3_INSTR_HDR},\ + {"EPMOD_MISC_DOP_INHERIT_ROCEV2_DCN_HEADER_FROM_PAYLOAD", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_INHERIT_ROCEV2_DCN_HEADER_FROM_PAYLOAD},\ + {"EPMOD_MISC_DOP_GEN_ROCEV2_CNP", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_GEN_ROCEV2_CNP},\ + {"EPMOD_MISC_DOP_ADD_ROCEV2_DCN_HEADER", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_ROCEV2_DCN_HEADER},\ + {"EPMOD_MISC_DOP_REMOVE_OPAQUE_TAG", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REMOVE_OPAQUE_TAG},\ + {"EPMOD_MISC_DOP_INSERT_INT_MD_HDR", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_INSERT_INT_MD_HDR},\ + {"EPMOD_MISC_DOP_L3_TUNNEL_ENCAP", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_L3_TUNNEL_ENCAP},\ + {"EPMOD_MISC_DOP_IFA_DEFERRED_INSERT", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_IFA_DEFERRED_INSERT},\ + {"EPMOD_MISC_DOP_SRH_DECAP", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_SRH_DECAP},\ + {"EPMOD_MISC_DOP_REMOVE_L3_INSTR_HDR", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REMOVE_L3_INSTR_HDR},\ + {"EPMOD_MISC_DOP_RECALCULATE_IP_CHECKSUM", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_RECALCULATE_IP_CHECKSUM},\ + {"EPMOD_MISC_DOP_ADD_MIRROR_ENCAP", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_MIRROR_ENCAP},\ + {"EPMOD_MISC_DOP_ADD_SVTAG", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_SVTAG},\ + {"EPMOD_MISC_DOP_REMOVE_IFA_HDR", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REMOVE_IFA_HDR},\ + {"EPMOD_MISC_DOP_ADD_DMA", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_DMA},\ + {"EPMOD_MISC_DOP_REMOVE_ROCE_DCN_HEADER", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REMOVE_ROCE_DCN_HEADER},\ + {"EPMOD_MISC_DOP_INSERT_INT_BASE_HDR", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_INSERT_INT_BASE_HDR},\ + {"EPMOD_MISC_DOP_REPLACE_TOP_LEVEL_MPLS_EXP", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REPLACE_TOP_LEVEL_MPLS_EXP},\ + {"EPMOD_MISC_DOP_L2_TUNNEL_DECAP", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_L2_TUNNEL_DECAP},\ + {"EPMOD_MISC_DOP_L3_TUNNEL_DECAP", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_L3_TUNNEL_DECAP},\ + {"EPMOD_MISC_DOP_PKT_PADDING", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_PKT_PADDING},\ + {"EPMOD_MISC_DOP_ADD_OPAQUE_TAG", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_OPAQUE_TAG},\ + {"EPMOD_MISC_DOP_REMOVE_SVTAG", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REMOVE_SVTAG},\ + {"EPMOD_MISC_DOP_ADD_OUTER_VLAN", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_OUTER_VLAN},\ + {"EPMOD_MISC_DOP_ADD_RSPAN_TAG", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_ADD_RSPAN_TAG},\ + {"EPMOD_MISC_DOP_REMOVE_L2_INSTR_TAG", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REMOVE_L2_INSTR_TAG},\ + {"EPMOD_MISC_DOP_REPLACE_TOP_LEVEL_MPLS_TTL", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_REPLACE_TOP_LEVEL_MPLS_TTL},\ + {"EPMOD_MISC_DOP_DELETE_OUTER_VLAN", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_DELETE_OUTER_VLAN},\ + {"EPMOD_MISC_DOP_PREPEND_HEADERS_TO_PACKET", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_PREPEND_HEADERS_TO_PACKET},\ + {"EPMOD_MISC_DOP_L2_TUNNEL_ENCAP", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_L2_TUNNEL_ENCAP},\ + {"EPMOD_MISC_DOP_INHERIT_ROCEV2_DCN_HEADER_FROM_TUNNEL", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_INHERIT_ROCEV2_DCN_HEADER_FROM_TUNNEL},\ + {"EPMOD_MISC_DOP_MODIFY_DELETE_GSH", BCMPKT_TRACE_DOP_EPMOD_MISC_DOP_MODIFY_DELETE_GSH},\ + {"ESW_GROUP_1_DOPS_INPLACE_MACDA_CHANGED", BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_MACDA_CHANGED},\ + {"ESW_GROUP_1_DOPS_INT_ACTION_PROFILE", BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INT_ACTION_PROFILE},\ + {"ESW_GROUP_1_DOPS_INPLACE_TTL_CHANGED", BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_TTL_CHANGED},\ + {"ESW_GROUP_1_DOPS_INPLACE_SRH_CHANGED", BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_SRH_CHANGED},\ + {"ESW_GROUP_1_DOPS_INPLACE_DIP_CHANGED", BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_DIP_CHANGED},\ + {"ESW_GROUP_1_DOPS_INPLACE_PAYLOAD_LENGTH_CHANGED", BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_PAYLOAD_LENGTH_CHANGED},\ + {"ESW_GROUP_1_DOPS_INT_OPERATION", BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INT_OPERATION},\ + {"ESW_GROUP_1_DOPS_INPLACE_MACSA_CHANGED", BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_MACSA_CHANGED},\ + {"ESW_GROUP_1_DOPS_INPLACE_TOS_CHANGED", BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_TOS_CHANGED},\ + {"ESW_GROUP_1_DOPS_INPLACE_ETYPE_CHANGED", BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_ETYPE_CHANGED},\ + {"ESW_GROUP_1_DOPS_INPLACE_DCN_CHANGED", BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_DCN_CHANGED},\ + {"ESW_GROUP_1_DOPS_INPLACE_NEXT_HDR_CHANGED", BCMPKT_TRACE_DOP_ESW_GROUP_1_DOPS_INPLACE_NEXT_HDR_CHANGED},\ + {"FP_GROUP2_DOP_THIRD_LKUP_KEY_7", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_7},\ + {"FP_GROUP2_DOP_THIRD_LKUP_KEY_6", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_6},\ + {"FP_GROUP2_DOP_THIRD_LKUP_KEY_5", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_5},\ + {"FP_GROUP2_DOP_THIRD_LKUP_KEY_4", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_4},\ + {"FP_GROUP2_DOP_THIRD_LKUP_KEY_3", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_3},\ + {"FP_GROUP2_DOP_THIRD_LKUP_KEY_2", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_2},\ + {"FP_GROUP2_DOP_THIRD_LKUP_KEY_1", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_1},\ + {"FP_GROUP2_DOP_THIRD_LKUP_KEY_0", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_0},\ + {"FP_GROUP2_DOP_THIRD_LKUP_KEY_8", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_THIRD_LKUP_KEY_8},\ + {"FP_GROUP2_DOP_SECOND_LKUP_KEY_8", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_8},\ + {"FP_GROUP2_DOP_SECOND_LKUP_KEY_3", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_3},\ + {"FP_GROUP2_DOP_SECOND_LKUP_KEY_2", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_2},\ + {"FP_GROUP2_DOP_SECOND_LKUP_KEY_1", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_1},\ + {"FP_GROUP2_DOP_SECOND_LKUP_KEY_0", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_0},\ + {"FP_GROUP2_DOP_SECOND_LKUP_KEY_7", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_7},\ + {"FP_GROUP2_DOP_SECOND_LKUP_KEY_6", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_6},\ + {"FP_GROUP2_DOP_SECOND_LKUP_KEY_5", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_5},\ + {"FP_GROUP2_DOP_SECOND_LKUP_KEY_4", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_SECOND_LKUP_KEY_4},\ + {"FP_GROUP2_DOP_FIRST_LKUP_KEY_0", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_0},\ + {"FP_GROUP2_DOP_FIRST_LKUP_KEY_1", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_1},\ + {"FP_GROUP2_DOP_FIRST_LKUP_KEY_2", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_2},\ + {"FP_GROUP2_DOP_FIRST_LKUP_KEY_3", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_3},\ + {"FP_GROUP2_DOP_FIRST_LKUP_KEY_4", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_4},\ + {"FP_GROUP2_DOP_FIRST_LKUP_KEY_5", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_5},\ + {"FP_GROUP2_DOP_FIRST_LKUP_KEY_6", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_6},\ + {"FP_GROUP2_DOP_FIRST_LKUP_KEY_7", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_7},\ + {"FP_GROUP2_DOP_FIRST_LKUP_KEY_8", BCMPKT_TRACE_DOP_FP_GROUP2_DOP_FIRST_LKUP_KEY_8},\ + {"FP_GROUP8_DOP_LKUP_HIT3", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT3},\ + {"FP_GROUP8_DOP_LKUP_HIT2", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT2},\ + {"FP_GROUP8_DOP_LKUP_HIT_INDEX8", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX8},\ + {"FP_GROUP8_DOP_LKUP_HIT0", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT0},\ + {"FP_GROUP8_DOP_LKUP_HIT6", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT6},\ + {"FP_GROUP8_DOP_LKUP_HIT5", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT5},\ + {"FP_GROUP8_DOP_LKUP_HIT4", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT4},\ + {"FP_GROUP8_DOP_LKUP_HIT_INDEX2", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX2},\ + {"FP_GROUP8_DOP_LKUP_HIT_INDEX0", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX0},\ + {"FP_GROUP8_DOP_LKUP_HIT_INDEX1", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX1},\ + {"FP_GROUP8_DOP_LKUP_HIT_INDEX6", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX6},\ + {"FP_GROUP8_DOP_LKUP_HIT1", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT1},\ + {"FP_GROUP8_DOP_LKUP_HIT_INDEX4", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX4},\ + {"FP_GROUP8_DOP_LKUP_HIT_INDEX7", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX7},\ + {"FP_GROUP8_DOP_LKUP_HIT_INDEX3", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX3},\ + {"FP_GROUP8_DOP_LKUP_HIT7", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT7},\ + {"FP_GROUP8_DOP_LKUP_HIT_INDEX5", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT_INDEX5},\ + {"FP_GROUP8_DOP_LKUP_HIT8", BCMPKT_TRACE_DOP_FP_GROUP8_DOP_LKUP_HIT8},\ + {"IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOPKUP_IS_IPM", BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOPKUP_IS_IPM},\ + {"IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOPKUP_IS_KICKED_OFF", BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOPKUP_IS_KICKED_OFF},\ + {"IFWD1_GROUP_A_1_DOPS_LPM_SRC_LOOKUP_KEY", BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_SRC_LOOKUP_KEY},\ + {"IFWD1_GROUP_A_1_DOPS_LPM_SRC_LOOPKUP_IS_V6", BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_SRC_LOOPKUP_IS_V6},\ + {"IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOKUP_KEY", BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOKUP_KEY},\ + {"IFWD1_GROUP_A_1_DOPS_LPM_SRC_LOOPKUP_IS_KICKED_OFF", BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_SRC_LOOPKUP_IS_KICKED_OFF},\ + {"IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOPKUP_IS_V6", BCMPKT_TRACE_DOP_IFWD1_GROUP_A_1_DOPS_LPM_DST_LOOPKUP_IS_V6},\ + {"IFWD1_GROUP_A_2_DOPS_COMP_DST_LOOKUP_KEY", BCMPKT_TRACE_DOP_IFWD1_GROUP_A_2_DOPS_COMP_DST_LOOKUP_KEY},\ + {"IFWD1_GROUP_A_2_DOPS_COMP_DST_LOOPKUP_IS_V6", BCMPKT_TRACE_DOP_IFWD1_GROUP_A_2_DOPS_COMP_DST_LOOPKUP_IS_V6},\ + {"IFWD1_GROUP_A_2_DOPS_COMP_DST_LOOPKUP_IS_KICKED_OFF", BCMPKT_TRACE_DOP_IFWD1_GROUP_A_2_DOPS_COMP_DST_LOOPKUP_IS_KICKED_OFF},\ + {"IFWD1_GROUP_A_2_DOPS_COMP_SRC_LOOKUP_KEY", BCMPKT_TRACE_DOP_IFWD1_GROUP_A_2_DOPS_COMP_SRC_LOOKUP_KEY},\ + {"IFWD1_GROUP_A_2_DOPS_COMP_SRC_LOOPKUP_IS_KICKED_OFF", BCMPKT_TRACE_DOP_IFWD1_GROUP_A_2_DOPS_COMP_SRC_LOOPKUP_IS_KICKED_OFF},\ + {"IFWD1_GROUP_A_2_DOPS_COMP_SRC_LOOPKUP_IS_V6", BCMPKT_TRACE_DOP_IFWD1_GROUP_A_2_DOPS_COMP_SRC_LOOPKUP_IS_V6},\ + {"IFWD1_GROUP_B_DOPS_L2_USER_ENTRY_LOOKUP_DONE", BCMPKT_TRACE_DOP_IFWD1_GROUP_B_DOPS_L2_USER_ENTRY_LOOKUP_DONE},\ + {"IFWD1_GROUP_B_DOPS_L2_SRC_LOOKUP_DONE", BCMPKT_TRACE_DOP_IFWD1_GROUP_B_DOPS_L2_SRC_LOOKUP_DONE},\ + {"IFWD1_GROUP_B_DOPS_L2_USER_ENTRY_KEY", BCMPKT_TRACE_DOP_IFWD1_GROUP_B_DOPS_L2_USER_ENTRY_KEY},\ + {"IFWD1_GROUP_B_DOPS_L2_DST_LOOKUP_DONE", BCMPKT_TRACE_DOP_IFWD1_GROUP_B_DOPS_L2_DST_LOOKUP_DONE},\ + {"IFWD1_GROUP_B_DOPS_L2_SRC_LOOKUP_KEY", BCMPKT_TRACE_DOP_IFWD1_GROUP_B_DOPS_L2_SRC_LOOKUP_KEY},\ + {"IFWD1_GROUP_B_DOPS_L2_DST_LOOKUP_KEY", BCMPKT_TRACE_DOP_IFWD1_GROUP_B_DOPS_L2_DST_LOOKUP_KEY},\ + {"IFWD1_GROUP_C_DOPS_EM_LOOKUP_KEY", BCMPKT_TRACE_DOP_IFWD1_GROUP_C_DOPS_EM_LOOKUP_KEY},\ + {"IFWD1_GROUP_C_DOPS_EM_LOOKUP_DONE", BCMPKT_TRACE_DOP_IFWD1_GROUP_C_DOPS_EM_LOOKUP_DONE},\ + {"IFWD1_GROUP_D_DOPS_EM_LTS_TCAM_LOOKUP_KEY", BCMPKT_TRACE_DOP_IFWD1_GROUP_D_DOPS_EM_LTS_TCAM_LOOKUP_KEY},\ + {"IFWD1_GROUP_D_DOPS_EM_LTS_TCAM_HIT_INDEX", BCMPKT_TRACE_DOP_IFWD1_GROUP_D_DOPS_EM_LTS_TCAM_HIT_INDEX},\ + {"IFWD1_GROUP_D_DOPS_EM_LTS_TCAM_HIT", BCMPKT_TRACE_DOP_IFWD1_GROUP_D_DOPS_EM_LTS_TCAM_HIT},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_8", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_8},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_3", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_3},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_LOOKUP_KEY_0", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_LOOKUP_KEY_0},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_0", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_0},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_7", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_7},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_6", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_6},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_5", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_5},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_4", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_4},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_8", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_8},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_1", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_1},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_2", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_INDEX_2},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_0", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_0},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_1", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_1},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_2", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_2},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_3", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_3},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_4", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_4},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_5", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_5},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_6", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_6},\ + {"IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_7", BCMPKT_TRACE_DOP_IFWD1_GROUP_E_DOPS_IFP_LTS_TCAM_HIT_7},\ + {"IFWD1_GROUP_G_1_DOPS_LPM_SRC_HIT_TBL", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_1_DOPS_LPM_SRC_HIT_TBL},\ + {"IFWD1_GROUP_G_1_DOPS_LPM_SRC_HIT", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_1_DOPS_LPM_SRC_HIT},\ + {"IFWD1_GROUP_G_1_DOPS_LPM_DST_HIT", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_1_DOPS_LPM_DST_HIT},\ + {"IFWD1_GROUP_G_1_DOPS_LPM_SRC_HIT_INDEX", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_1_DOPS_LPM_SRC_HIT_INDEX},\ + {"IFWD1_GROUP_G_1_DOPS_LPM_DST_HIT_INDEX", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_1_DOPS_LPM_DST_HIT_INDEX},\ + {"IFWD1_GROUP_G_1_DOPS_LPM_DST_HIT_TBL", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_1_DOPS_LPM_DST_HIT_TBL},\ + {"IFWD1_GROUP_G_2_DOPS_LPM_SRC_HIT_TBL", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_2_DOPS_LPM_SRC_HIT_TBL},\ + {"IFWD1_GROUP_G_2_DOPS_LPM_SRC_HIT", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_2_DOPS_LPM_SRC_HIT},\ + {"IFWD1_GROUP_G_2_DOPS_LPM_DST_HIT", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_2_DOPS_LPM_DST_HIT},\ + {"IFWD1_GROUP_G_2_DOPS_LPM_SRC_HIT_INDEX", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_2_DOPS_LPM_SRC_HIT_INDEX},\ + {"IFWD1_GROUP_G_2_DOPS_LPM_DST_HIT_INDEX", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_2_DOPS_LPM_DST_HIT_INDEX},\ + {"IFWD1_GROUP_G_2_DOPS_LPM_DST_HIT_TBL", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_2_DOPS_LPM_DST_HIT_TBL},\ + {"IFWD1_GROUP_G_3_DOPS_L2_SRC_HIT", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_3_DOPS_L2_SRC_HIT},\ + {"IFWD1_GROUP_G_3_DOPS_L2_USER_ENTRY_HIT", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_3_DOPS_L2_USER_ENTRY_HIT},\ + {"IFWD1_GROUP_G_3_DOPS_L2_DST_HIT", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_3_DOPS_L2_DST_HIT},\ + {"IFWD1_GROUP_G_3_DOPS_L2_USER_ENTRY_HIT_INDEX", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_3_DOPS_L2_USER_ENTRY_HIT_INDEX},\ + {"IFWD1_GROUP_G_3_DOPS_L2_SRC_HIT_INDEX", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_3_DOPS_L2_SRC_HIT_INDEX},\ + {"IFWD1_GROUP_G_3_DOPS_L2_DST_HIT_INDEX", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_3_DOPS_L2_DST_HIT_INDEX},\ + {"IFWD1_GROUP_G_4_DOPS_EM_HIT_INDEX", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_4_DOPS_EM_HIT_INDEX},\ + {"IFWD1_GROUP_G_4_DOPS_EM_HIT", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_4_DOPS_EM_HIT},\ + {"IFWD1_GROUP_G_4_DOPS_EM_HIT_TBL", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_4_DOPS_EM_HIT_TBL},\ + {"IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_B0", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_B0},\ + {"IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_B1", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_B1},\ + {"IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_A1", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_A1},\ + {"IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_A0", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_5_DOPS_RTAG7_HASH_VALUE_A0},\ + {"IFWD1_GROUP_G_5_DOPS_DISABLE_VLAN_CHECKS", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_5_DOPS_DISABLE_VLAN_CHECKS},\ + {"IFWD1_GROUP_G_5_DOPS_LOOKUP_STATUS_VECTOR", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_5_DOPS_LOOKUP_STATUS_VECTOR},\ + {"IFWD1_GROUP_G_6_DOPS_REMAP_DOT1P_INDEX", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_6_DOPS_REMAP_DOT1P_INDEX},\ + {"IFWD1_GROUP_G_6_DOPS_REMAP_PAYLOAD_DOT1P", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_6_DOPS_REMAP_PAYLOAD_DOT1P},\ + {"IFWD1_GROUP_G_6_DOPS_REMAP_OUTER_DOT1P", BCMPKT_TRACE_DOP_IFWD1_GROUP_G_6_DOPS_REMAP_OUTER_DOT1P},\ + {"IPARS_HASH_TABLE_DOP_L3_TUNNEL_LOOKUP_SEARCH_KEY", BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_L3_TUNNEL_LOOKUP_SEARCH_KEY},\ + {"IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_1_HIT", BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_1_HIT},\ + {"IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_2_SEARCH_KEY", BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_2_SEARCH_KEY},\ + {"IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_1_SEARCH_KEY", BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_1_SEARCH_KEY},\ + {"IPARS_HASH_TABLE_DOP_L3_TUNNEL_LOOKUP_HIT_INDEX", BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_L3_TUNNEL_LOOKUP_HIT_INDEX},\ + {"IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_2_HIT", BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_2_HIT},\ + {"IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_2_HIT_INDEX", BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_2_HIT_INDEX},\ + {"IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_1_HIT_INDEX", BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_MPLS_LOOKUP_1_HIT_INDEX},\ + {"IPARS_HASH_TABLE_DOP_L3_TUNNEL_LOOKUP_HIT", BCMPKT_TRACE_DOP_IPARS_HASH_TABLE_DOP_L3_TUNNEL_LOOKUP_HIT},\ + {"IPARS_L3_TUNNEL_TCAM_DOP_SEARCH_KEY_1", BCMPKT_TRACE_DOP_IPARS_L3_TUNNEL_TCAM_DOP_SEARCH_KEY_1},\ + {"IPARS_L3_TUNNEL_TCAM_DOP_SEARCH_KEY_0", BCMPKT_TRACE_DOP_IPARS_L3_TUNNEL_TCAM_DOP_SEARCH_KEY_0},\ + {"IPARS_L3_TUNNEL_TCAM_DOP_TCAM_HIT", BCMPKT_TRACE_DOP_IPARS_L3_TUNNEL_TCAM_DOP_TCAM_HIT},\ + {"IPARS_L3_TUNNEL_TCAM_DOP_TUNNEL_OR_HIT_INDEX", BCMPKT_TRACE_DOP_IPARS_L3_TUNNEL_TCAM_DOP_TUNNEL_OR_HIT_INDEX},\ + {"IPARS_MISC_DOP_IPAD_BUS", BCMPKT_TRACE_DOP_IPARS_MISC_DOP_IPAD_BUS},\ + {"IPARS_MY_PREFIX_TCAM_DOP_MY_PREFIX_TCAM_HIT", BCMPKT_TRACE_DOP_IPARS_MY_PREFIX_TCAM_DOP_MY_PREFIX_TCAM_HIT},\ + {"IPARS_MY_PREFIX_TCAM_DOP_MY_PREFIX_TCAM_HIT_INDEX", BCMPKT_TRACE_DOP_IPARS_MY_PREFIX_TCAM_DOP_MY_PREFIX_TCAM_HIT_INDEX},\ + {"IPARS_MY_PREFIX_TCAM_DOP_MY_PREFIX_TCAM_LOOKUP_KEY", BCMPKT_TRACE_DOP_IPARS_MY_PREFIX_TCAM_DOP_MY_PREFIX_TCAM_LOOKUP_KEY},\ + {"IPARS_UDF_TCAM_DOP_UDF_TCAM_HIT", BCMPKT_TRACE_DOP_IPARS_UDF_TCAM_DOP_UDF_TCAM_HIT},\ + {"IPARS_UDF_TCAM_DOP_UDF_TCAM_LOOKUP_KEY", BCMPKT_TRACE_DOP_IPARS_UDF_TCAM_DOP_UDF_TCAM_LOOKUP_KEY},\ + {"IPARS_UDF_TCAM_DOP_UDF_TCAM_HIT_INDEX", BCMPKT_TRACE_DOP_IPARS_UDF_TCAM_DOP_UDF_TCAM_HIT_INDEX},\ + {"MISC_DOP_DO_IPMC_LOOKUP", BCMPKT_TRACE_DOP_MISC_DOP_DO_IPMC_LOOKUP},\ + {"MISC_DOP_ELIGIBLE_FOR_L3_LOOKUP", BCMPKT_TRACE_DOP_MISC_DOP_ELIGIBLE_FOR_L3_LOOKUP},\ + {"MY_STATION_2_TCAM_DOP_MY_STATION_2_TCAM_KEY", BCMPKT_TRACE_DOP_MY_STATION_2_TCAM_DOP_MY_STATION_2_TCAM_KEY},\ + {"MY_STATION_2_TCAM_DOP_MY_STATION_2_TCAM_HIT_INDEX", BCMPKT_TRACE_DOP_MY_STATION_2_TCAM_DOP_MY_STATION_2_TCAM_HIT_INDEX},\ + {"MY_STATION_2_TCAM_DOP_MY_STATION_2_TCAM_HIT", BCMPKT_TRACE_DOP_MY_STATION_2_TCAM_DOP_MY_STATION_2_TCAM_HIT},\ + {"MY_STATION_TCAM_DOP_MY_STATION_TCAM_KEY", BCMPKT_TRACE_DOP_MY_STATION_TCAM_DOP_MY_STATION_TCAM_KEY},\ + {"MY_STATION_TCAM_DOP_MY_STATION_TCAM_HIT", BCMPKT_TRACE_DOP_MY_STATION_TCAM_DOP_MY_STATION_TCAM_HIT},\ + {"MY_STATION_TCAM_DOP_MY_STATION_TCAM_HIT_INDEX", BCMPKT_TRACE_DOP_MY_STATION_TCAM_DOP_MY_STATION_TCAM_HIT_INDEX},\ + {"RSEL_GROUP1_DOP_OL_WCMP_BUCKET_HASH_VALUE", BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_WCMP_BUCKET_HASH_VALUE},\ + {"RSEL_GROUP1_DOP_OL_MEMBER_INDEX", BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_MEMBER_INDEX},\ + {"RSEL_GROUP1_DOP_OL_L3_ECMP_HASH_VALUE", BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_L3_ECMP_HASH_VALUE},\ + {"RSEL_GROUP1_DOP_OL_RESOLUTION_DONE", BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_RESOLUTION_DONE},\ + {"RSEL_GROUP1_DOP_OL_GROUP_PTR", BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_GROUP_PTR},\ + {"RSEL_GROUP1_DOP_OL_WCMP_WEIGHT_HASH_VALUE", BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_WCMP_WEIGHT_HASH_VALUE},\ + {"RSEL_GROUP1_DOP_OL_NHI", BCMPKT_TRACE_DOP_RSEL_GROUP1_DOP_OL_NHI},\ + {"RSEL_GROUP2_1_DOP_UL_GROUP_PTR", BCMPKT_TRACE_DOP_RSEL_GROUP2_1_DOP_UL_GROUP_PTR},\ + {"RSEL_GROUP2_2_DOP_PRIMARY_RH_FLOW_SET_INDEX", BCMPKT_TRACE_DOP_RSEL_GROUP2_2_DOP_PRIMARY_RH_FLOW_SET_INDEX},\ + {"RSEL_GROUP2_2_DOP_PRIMARY_RH_ECMP_HASH", BCMPKT_TRACE_DOP_RSEL_GROUP2_2_DOP_PRIMARY_RH_ECMP_HASH},\ + {"RSEL_GROUP2_3_DOP_SECONDARY_RH_ECMP_HASH", BCMPKT_TRACE_DOP_RSEL_GROUP2_3_DOP_SECONDARY_RH_ECMP_HASH},\ + {"RSEL_GROUP2_3_DOP_SECONDARY_RH_FLOW_SET_INDEX", BCMPKT_TRACE_DOP_RSEL_GROUP2_3_DOP_SECONDARY_RH_FLOW_SET_INDEX},\ + {"RSEL_GROUP3_1_DOP_PRIMARY_UL_NHI", BCMPKT_TRACE_DOP_RSEL_GROUP3_1_DOP_PRIMARY_UL_NHI},\ + {"RSEL_GROUP3_1_DOP_PRIMARY_MEMBER_INDEX", BCMPKT_TRACE_DOP_RSEL_GROUP3_1_DOP_PRIMARY_MEMBER_INDEX},\ + {"RSEL_GROUP3_1_DOP_PRIMARY_ECMP_L3_HASH_VALUE", BCMPKT_TRACE_DOP_RSEL_GROUP3_1_DOP_PRIMARY_ECMP_L3_HASH_VALUE},\ + {"RSEL_GROUP3_2_DOP_SECONDARY_MEMBER_INDEX", BCMPKT_TRACE_DOP_RSEL_GROUP3_2_DOP_SECONDARY_MEMBER_INDEX},\ + {"RSEL_GROUP3_2_DOP_SECONDARY_ECMP_L3_HASH_VALUE", BCMPKT_TRACE_DOP_RSEL_GROUP3_2_DOP_SECONDARY_ECMP_L3_HASH_VALUE},\ + {"RSEL_GROUP3_2_DOP_SECONDARY_UL_NHI", BCMPKT_TRACE_DOP_RSEL_GROUP3_2_DOP_SECONDARY_UL_NHI},\ + {"RSEL_GROUP3_3_DOP_PRIMARY_WCMP_BUCKET_HASH_VALUE", BCMPKT_TRACE_DOP_RSEL_GROUP3_3_DOP_PRIMARY_WCMP_BUCKET_HASH_VALUE},\ + {"RSEL_GROUP3_3_DOP_SECONDARY_WCMP_BUCKET_HASH_VALUE", BCMPKT_TRACE_DOP_RSEL_GROUP3_3_DOP_SECONDARY_WCMP_BUCKET_HASH_VALUE},\ + {"RSEL_GROUP3_4_DOP_TERTIARY_UL_NHI", BCMPKT_TRACE_DOP_RSEL_GROUP3_4_DOP_TERTIARY_UL_NHI},\ + {"RSEL_GROUP3_5_DOP_PRIMARY_PATH", BCMPKT_TRACE_DOP_RSEL_GROUP3_5_DOP_PRIMARY_PATH},\ + {"RSEL_GROUP3_5_DOP_PROTECTION_PATH_ACTIVE", BCMPKT_TRACE_DOP_RSEL_GROUP3_5_DOP_PROTECTION_PATH_ACTIVE},\ + {"RSEL_GROUP3_5_DOP_TERTIARY_PATH", BCMPKT_TRACE_DOP_RSEL_GROUP3_5_DOP_TERTIARY_PATH},\ + {"RSEL_GROUP3_5_DOP_SECONDARY_PATH", BCMPKT_TRACE_DOP_RSEL_GROUP3_5_DOP_SECONDARY_PATH},\ + {"SW_GROUP1_1_DOP_ING_VFI", BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_ING_VFI},\ + {"SW_GROUP1_1_DOP_VRF", BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_VRF},\ + {"SW_GROUP1_1_DOP_L3_IIF", BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_L3_IIF},\ + {"SW_GROUP1_1_DOP_FORWARDING_FIELD", BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_FORWARDING_FIELD},\ + {"SW_GROUP1_1_DOP_FORWARDING_TYPE", BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_FORWARDING_TYPE},\ + {"SW_GROUP1_1_DOP_DVP", BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_DVP},\ + {"SW_GROUP1_1_DOP_SVP", BCMPKT_TRACE_DOP_SW_GROUP1_1_DOP_SVP},\ + {"SW_GROUP1_2_DOP_INT_CN", BCMPKT_TRACE_DOP_SW_GROUP1_2_DOP_INT_CN},\ + {"SW_GROUP1_3_DOP_L2MC_INDEX", BCMPKT_TRACE_DOP_SW_GROUP1_3_DOP_L2MC_INDEX},\ + {"SW_GROUP1_4_DOP_MC_INDEX", BCMPKT_TRACE_DOP_SW_GROUP1_4_DOP_MC_INDEX},\ + {"SW_GROUP1_5_DOP_LAG_ID", BCMPKT_TRACE_DOP_SW_GROUP1_5_DOP_LAG_ID},\ + {"SW_GROUP1_5_DOP_HASH_VALUE_LAG", BCMPKT_TRACE_DOP_SW_GROUP1_5_DOP_HASH_VALUE_LAG},\ + {"SW_GROUP1_6_DOP_IP_POWER_ACTIVITY_MONITOR_NUM_OF_ACTIVE_IFP_SLICES", BCMPKT_TRACE_DOP_SW_GROUP1_6_DOP_IP_POWER_ACTIVITY_MONITOR_NUM_OF_ACTIVE_IFP_SLICES},\ + {"SW_GROUP1_6_DOP_IP_POWER_ACTIVITY_MONITOR_NUM_OF_ACTIVE_UFT_BANKS", BCMPKT_TRACE_DOP_SW_GROUP1_6_DOP_IP_POWER_ACTIVITY_MONITOR_NUM_OF_ACTIVE_UFT_BANKS},\ + {"SW_GROUP1_7_DOP_CHANGE_DSCP", BCMPKT_TRACE_DOP_SW_GROUP1_7_DOP_CHANGE_DSCP},\ + {"SW_GROUP1_7_DOP_PRESERVE_DSCP", BCMPKT_TRACE_DOP_SW_GROUP1_7_DOP_PRESERVE_DSCP},\ + {"SW_GROUP1_7_DOP_DSCP", BCMPKT_TRACE_DOP_SW_GROUP1_7_DOP_DSCP},\ + {"SW_GROUP2_1_DOP_L2MC_PBM", BCMPKT_TRACE_DOP_SW_GROUP2_1_DOP_L2MC_PBM},\ + {"SW_GROUP2_2_DOP_OR_PBM", BCMPKT_TRACE_DOP_SW_GROUP2_2_DOP_OR_PBM},\ + {"SW_GROUP2_3_DOP_LAG_OFFSET", BCMPKT_TRACE_DOP_SW_GROUP2_3_DOP_LAG_OFFSET},\ + {"SW_GROUP2_4_DOP_FLOW_INDEX", BCMPKT_TRACE_DOP_SW_GROUP2_4_DOP_FLOW_INDEX},\ + {"SW_GROUP3_DOP_AND_PBM", BCMPKT_TRACE_DOP_SW_GROUP3_DOP_AND_PBM},\ + {"SW_GROUP4_DOP_CPU_COS_MAP_TCAM_KEY", BCMPKT_TRACE_DOP_SW_GROUP4_DOP_CPU_COS_MAP_TCAM_KEY},\ + {"SW_GROUP5_1_DOP_CPU_COS_MAP_TCAM_HIT", BCMPKT_TRACE_DOP_SW_GROUP5_1_DOP_CPU_COS_MAP_TCAM_HIT},\ + {"SW_GROUP5_1_DOP_CPU_COS_MAP_TCAM_HIT_INDEX", BCMPKT_TRACE_DOP_SW_GROUP5_1_DOP_CPU_COS_MAP_TCAM_HIT_INDEX},\ + {"SW_GROUP5_2_DOP_ING_COUNTER_UPDATE_VECTOR", BCMPKT_TRACE_DOP_SW_GROUP5_2_DOP_ING_COUNTER_UPDATE_VECTOR},\ + {"SW_GROUP5_3_DOP_CNG", BCMPKT_TRACE_DOP_SW_GROUP5_3_DOP_CNG},\ + {"SW_GROUP5_3_DOP_COPY_TO_CPU", BCMPKT_TRACE_DOP_SW_GROUP5_3_DOP_COPY_TO_CPU},\ + {"SW_GROUP5_3_DOP_TUNNEL_DECAP_TYPE", BCMPKT_TRACE_DOP_SW_GROUP5_3_DOP_TUNNEL_DECAP_TYPE},\ + {"SW_GROUP5_3_DOP_INT_PRI", BCMPKT_TRACE_DOP_SW_GROUP5_3_DOP_INT_PRI},\ + {"SW_GROUP5_3_DOP_PRESERVE_DOT1P", BCMPKT_TRACE_DOP_SW_GROUP5_3_DOP_PRESERVE_DOT1P},\ + {"SW_GROUP5_3_DOP_DEST_PORT", BCMPKT_TRACE_DOP_SW_GROUP5_3_DOP_DEST_PORT},\ + {"SW_GROUP6_1_DOP_L3_PBM", BCMPKT_TRACE_DOP_SW_GROUP6_1_DOP_L3_PBM},\ + {"SW_GROUP6_1_DOP_L2_PBM", BCMPKT_TRACE_DOP_SW_GROUP6_1_DOP_L2_PBM},\ + {"SW_GROUP6_2_DOP_CHANGE_ECN", BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_CHANGE_ECN},\ + {"SW_GROUP6_2_DOP_EMIRROR", BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_EMIRROR},\ + {"SW_GROUP6_2_DOP_MIRROR", BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_MIRROR},\ + {"SW_GROUP6_2_DOP_UC_QUEUE_VALID", BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_UC_QUEUE_VALID},\ + {"SW_GROUP6_2_DOP_ING_OTAG_ACTION", BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_ING_OTAG_ACTION},\ + {"SW_GROUP6_2_DOP_ECN", BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_ECN},\ + {"SW_GROUP6_2_DOP_ENTROPY", BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_ENTROPY},\ + {"SW_GROUP6_2_DOP_MIRR3", BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_MIRR3},\ + {"SW_GROUP6_2_DOP_MIRR2", BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_MIRR2},\ + {"SW_GROUP6_2_DOP_MIRR1", BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_MIRR1},\ + {"SW_GROUP6_2_DOP_MIRR0", BCMPKT_TRACE_DOP_SW_GROUP6_2_DOP_MIRR0},\ + {"UDF_COND_TCAM_DOP_UDF_COND_TCAM_HIT_INDEX", BCMPKT_TRACE_DOP_UDF_COND_TCAM_DOP_UDF_COND_TCAM_HIT_INDEX},\ + {"UDF_COND_TCAM_DOP_UDF_COND_TCAM_KEY", BCMPKT_TRACE_DOP_UDF_COND_TCAM_DOP_UDF_COND_TCAM_KEY},\ + {"UDF_COND_TCAM_DOP_UDF_COND_TCAM_HIT", BCMPKT_TRACE_DOP_UDF_COND_TCAM_DOP_UDF_COND_TCAM_HIT},\ + {"VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_0_B", BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_0_B},\ + {"VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_0_A", BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_0_A},\ + {"VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_2_A", BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_2_A},\ + {"VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_2_B", BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_2_B},\ + {"VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_1_B", BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_1_B},\ + {"VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_1_A", BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_1_A},\ + {"VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_3_A", BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_3_A},\ + {"VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_3_B", BCMPKT_TRACE_DOP_VFP_TCAM_KEY_DOP_VFP_TCAM_KEY_SLICE_3_B},\ + {"VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_0", BCMPKT_TRACE_DOP_VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_0},\ + {"VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_1", BCMPKT_TRACE_DOP_VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_1},\ + {"VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_2", BCMPKT_TRACE_DOP_VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_2},\ + {"VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_0", BCMPKT_TRACE_DOP_VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_0},\ + {"VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_3", BCMPKT_TRACE_DOP_VFP_TCAM_RESULT_DOP_VFP_VIRTUAL_SLICE_HIT_INDEX_3},\ + {"LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP_EGR_INCA_OPCODE_MAP_TCAM_KEY", BCMPKT_TRACE_DOP_LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP_EGR_INCA_OPCODE_MAP_TCAM_KEY},\ + {"LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP_EGR_INCA_OPCODE_MAP_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP_EGR_INCA_OPCODE_MAP_TCAM_MATCH_INDEX},\ + {"LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP_EGR_INCA_OPCODE_MAP_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP_EGR_INCA_OPCODE_MAP_TCAM_TCAM_MATCH},\ + {"LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_KEY", BCMPKT_TRACE_DOP_LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_KEY},\ + {"LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_MATCH_INDEX},\ + {"LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_TCAM_MATCH},\ + {"LPP_EPARS_EGR_PP_PORT_DOP_EGR_PP_PORT_NUM_SOP", BCMPKT_TRACE_DOP_LPP_EPARS_EGR_PP_PORT_DOP_EGR_PP_PORT_NUM_SOP},\ + {"LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_DQP", BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_DQP},\ + {"LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_INTERNAL_QP_ID", BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_INTERNAL_QP_ID},\ + {"LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_OPCODE", BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_OPCODE},\ + {"LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_PSN", BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_INCA_DOP_INCA_OUTGOING_PSN},\ + {"LPP_EPARS_EPARS_INCA_DOP_INCA_PSN_UPDATE_ENABLE", BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_INCA_DOP_INCA_PSN_UPDATE_ENABLE},\ + {"LPP_EPARS_EPARS_INCA_DOP_INCA_UPDATE_OPCODE_ENABLE", BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_INCA_DOP_INCA_UPDATE_OPCODE_ENABLE},\ + {"LPP_EPARS_EPARS_MATCH_ID_DOP_EPARS_MATCH_ID", BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_MATCH_ID_DOP_EPARS_MATCH_ID},\ + {"LPP_EPARS_EPARS_TS_1588_DOP_EPARS_MSG_TYPE_1588", BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_TS_1588_DOP_EPARS_MSG_TYPE_1588},\ + {"LPP_EPARS_EPARS_TS_1588_DOP_EPARS_TS_1588_PKT", BCMPKT_TRACE_DOP_LPP_EPARS_EPARS_TS_1588_DOP_EPARS_TS_1588_PKT},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_ADD_OUTER_VLAN", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_ADD_OUTER_VLAN},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_ADD_RX_MD_HDR", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_ADD_RX_MD_HDR},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_CORRECTION_FIELD_UPDATED_1588", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_CORRECTION_FIELD_UPDATED_1588},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_DELETE_OUTER_VLAN", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_DELETE_OUTER_VLAN},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_EDITED_PKT_LENGTH", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_EDITED_PKT_LENGTH},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_IFA_ACTION", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_IFA_ACTION},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_IFA_MD_HDR_INSERTED", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_IFA_MD_HDR_INSERTED},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_INCA_INSERT_ROCEV2_RETH_HDR", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INCA_INSERT_ROCEV2_RETH_HDR},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_INCA_ROCEV2_HDR_DELETED", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INCA_ROCEV2_HDR_DELETED},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_INCA_UPDATE_ROCEV2_RETH_HDR", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INCA_UPDATE_ROCEV2_RETH_HDR},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_DCN_METADATA_UPDATED", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_DCN_METADATA_UPDATED},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_DIP_CHANGED", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_DIP_CHANGED},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_MACDA_CHANGED", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_MACDA_CHANGED},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_MACSA_CHANGED", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_MACSA_CHANGED},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_PAYLOAD_LENGTH_CHANGED", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_PAYLOAD_LENGTH_CHANGED},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_SIP_CHANGED", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_SIP_CHANGED},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_TOS_CHANGED", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_TOS_CHANGED},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_TTL_CHANGED", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_INPLACE_TTL_CHANGED},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_L2_INSTR_LOCATOR_METADATA_UPDATED", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_L2_INSTR_LOCATOR_METADATA_UPDATED},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_L2_INSTR_PERFORMANCE_METRICS_UPDATED", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_L2_INSTR_PERFORMANCE_METRICS_UPDATED},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_L2_INSTR_PKT_EDIT_ACTION", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_L2_INSTR_PKT_EDIT_ACTION},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_REPLACE_OUTER_VLAN", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_REPLACE_OUTER_VLAN},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP_UDP_CHECKSUM_UPDATED", BCMPKT_TRACE_DOP_LPP_EPMOD_EDIT_ACTION_DOP_DOP_UDP_CHECKSUM_UPDATED},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP_EGR_SOBMH_COUNTER", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_EGR_SOBMH_COUNTER},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP_PRIORITY_VAL", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_PRIORITY_VAL},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP_TDBGC", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TDBGC},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP_TX_PARITY_ERROR_DROP", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_PARITY_ERROR_DROP},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_IPV4", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_IPV4},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_IPV6", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_IPV6},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE_ECN_MARKED", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE_ECN_MARKED},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE_RED", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE_RED},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE_YELLOW", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_PER_QUEUE_YELLOW},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_RED", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_RED},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_YELLOW", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_COUNTERS_DOP_TX_STATS_YELLOW},\ + {"LPP_EPMOD_EGR_EVENT_VECTOR_DOP_EGR_EVENT_VECTOR", BCMPKT_TRACE_DOP_LPP_EPMOD_EGR_EVENT_VECTOR_DOP_EGR_EVENT_VECTOR},\ + {"LPP_IFWD_ALPM_FXT_HASH_OUT_GEN_DOP_HASH_VAL", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_FXT_HASH_OUT_GEN_DOP_HASH_VAL},\ + {"LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY},\ + {"LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_PKT_RD", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_PKT_RD},\ + {"LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_MATCH_INDEX", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_MATCH_INDEX},\ + {"LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_TCAM_MATCH},\ + {"LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY},\ + {"LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_PKT_RD", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_PKT_RD},\ + {"LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_MATCH_INDEX", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_MATCH_INDEX},\ + {"LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_INDEX_DOP_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_TCAM_MATCH},\ + {"LPP_IFWD_ALPM_LEVEL2_HIT_INFO_DOP_HIT_0", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_LEVEL2_HIT_INFO_DOP_HIT_0},\ + {"LPP_IFWD_ALPM_LEVEL2_HIT_INFO_DOP_HIT_0_INDEX", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_LEVEL2_HIT_INFO_DOP_HIT_0_INDEX},\ + {"LPP_IFWD_ALPM_LPM_KEY_GEN_CONTROLS_DOP_ELIGIBLE_FOR_L3_LOOKUP", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_LPM_KEY_GEN_CONTROLS_DOP_ELIGIBLE_FOR_L3_LOOKUP},\ + {"LPP_IFWD_ALPM_LPM_KEY_GEN_CONTROLS_DOP_VRF", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_LPM_KEY_GEN_CONTROLS_DOP_VRF},\ + {"LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_FORWARDING_PROFILE", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_FORWARDING_PROFILE},\ + {"LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_OUTGOING_VLAN_PROFILE", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_OUTGOING_VLAN_PROFILE},\ + {"LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_AR_DESTINATION", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_AR_DESTINATION},\ + {"LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_AR_DESTINATION_VALID", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_AR_DESTINATION_VALID},\ + {"LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_DEFAULT_DESTINATION", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_DEFAULT_DESTINATION},\ + {"LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_DEFAULT_DESTINATION_TYPE", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_DEFAULT_DESTINATION_TYPE},\ + {"LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_DEFAULT_DESTINATION_VALID", BCMPKT_TRACE_DOP_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP_RESOLVED_DEFAULT_DESTINATION_VALID},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_KEY", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_KEY},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_MATCH_INDEX", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_MATCH_INDEX},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_PKT_RD", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_PKT_RD},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP_IFP_LTS_TCAM_ONLY_0_TCAM_MATCH},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_KEY", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_KEY},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_MATCH_INDEX", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_MATCH_INDEX},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_PKT_RD", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_PKT_RD},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP_IFP_LTS_TCAM_ONLY_1_TCAM_MATCH},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_KEY", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_KEY},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_MATCH_INDEX", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_MATCH_INDEX},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_PKT_RD", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_PKT_RD},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP_IFP_LTS_TCAM_ONLY_2_TCAM_MATCH},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_KEY", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_KEY},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_MATCH_INDEX", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_MATCH_INDEX},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_PKT_RD", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_PKT_RD},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP_IFP_LTS_TCAM_ONLY_3_TCAM_MATCH},\ + {"LPP_IPARS_FINAL_VRF_DOP_FINAL_VRF", BCMPKT_TRACE_DOP_LPP_IPARS_FINAL_VRF_DOP_FINAL_VRF},\ + {"LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP_ING_LOCAL_INCA_COLLECTIVE_MAP_TCAM_KEY", BCMPKT_TRACE_DOP_LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP_ING_LOCAL_INCA_COLLECTIVE_MAP_TCAM_KEY},\ + {"LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP_ING_LOCAL_INCA_COLLECTIVE_MAP_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP_ING_LOCAL_INCA_COLLECTIVE_MAP_TCAM_MATCH_INDEX},\ + {"LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP_ING_LOCAL_INCA_COLLECTIVE_MAP_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP_ING_LOCAL_INCA_COLLECTIVE_MAP_TCAM_TCAM_MATCH},\ + {"LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP_ING_INCA_OPCODE_MAP_TCAM_KEY", BCMPKT_TRACE_DOP_LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP_ING_INCA_OPCODE_MAP_TCAM_KEY},\ + {"LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP_ING_INCA_OPCODE_MAP_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP_ING_INCA_OPCODE_MAP_TCAM_MATCH_INDEX},\ + {"LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP_ING_INCA_OPCODE_MAP_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP_ING_INCA_OPCODE_MAP_TCAM_TCAM_MATCH},\ + {"LPP_IPARS_IPARS_MAPPED_DSCP_DOP_IPARS_MAPPED_DSCP", BCMPKT_TRACE_DOP_LPP_IPARS_IPARS_MAPPED_DSCP_DOP_IPARS_MAPPED_DSCP},\ + {"LPP_IPARS_LPP_IPAD_BUS_DOP_LPP_IPAD_BUS", BCMPKT_TRACE_DOP_LPP_IPARS_LPP_IPAD_BUS_DOP_LPP_IPAD_BUS},\ + {"LPP_IPARS_MATCH_ID_DOP_BUS_MATCH_ID", BCMPKT_TRACE_DOP_LPP_IPARS_MATCH_ID_DOP_BUS_MATCH_ID},\ + {"LPP_IPARS_MY_STATION_HIT_DOP_MY_STATION_HIT", BCMPKT_TRACE_DOP_LPP_IPARS_MY_STATION_HIT_DOP_MY_STATION_HIT},\ + {"LPP_IPARS_UDF_TCAM_DOP_UDF_TCAM_TCAM_HIT_INDEX", BCMPKT_TRACE_DOP_LPP_IPARS_UDF_TCAM_DOP_UDF_TCAM_TCAM_HIT_INDEX},\ + {"LPP_IPARS_UDF_TCAM_DOP_UDF_TCAM_TCAM_KEY", BCMPKT_TRACE_DOP_LPP_IPARS_UDF_TCAM_DOP_UDF_TCAM_TCAM_KEY},\ + {"LPP_IPARS_UDF_TCAM_DOP_UDF_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_IPARS_UDF_TCAM_DOP_UDF_TCAM_TCAM_MATCH},\ + {"LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP_VLAN_TO_VRF_MAPPING_TCAM_KEY", BCMPKT_TRACE_DOP_LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP_VLAN_TO_VRF_MAPPING_TCAM_KEY},\ + {"LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP_VLAN_TO_VRF_MAPPING_TCAM_MATCH_INDEX", BCMPKT_TRACE_DOP_LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP_VLAN_TO_VRF_MAPPING_TCAM_MATCH_INDEX},\ + {"LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP_VLAN_TO_VRF_MAPPING_TCAM_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP_VLAN_TO_VRF_MAPPING_TCAM_TCAM_MATCH},\ + {"LPP_IRSEL_AR_AR_INFO_DOP_AR_GROUP", BCMPKT_TRACE_DOP_LPP_IRSEL_AR_AR_INFO_DOP_AR_GROUP},\ + {"LPP_IRSEL_AR_AR_INFO_DOP_AR_RESOLUTION_INDEX", BCMPKT_TRACE_DOP_LPP_IRSEL_AR_AR_INFO_DOP_AR_RESOLUTION_INDEX},\ + {"LPP_IRSEL_AR_AR_INFO_DOP_FLOWSET_INDEX", BCMPKT_TRACE_DOP_LPP_IRSEL_AR_AR_INFO_DOP_FLOWSET_INDEX},\ + {"LPP_IRSEL_AR_AR_INFO_DOP_INGRESS_VC", BCMPKT_TRACE_DOP_LPP_IRSEL_AR_AR_INFO_DOP_INGRESS_VC},\ + {"LPP_IRSEL_AR_AR_INFO_DOP_TIMESTAMP", BCMPKT_TRACE_DOP_LPP_IRSEL_AR_AR_INFO_DOP_TIMESTAMP},\ + {"LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_AR_DR_FLAG", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_AR_DR_FLAG},\ + {"LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_ASSIGNED_MIRROR", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_ASSIGNED_MIRROR},\ + {"LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_CHOICE_TYPE", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_CHOICE_TYPE},\ + {"LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_COPY_TO_CPU", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_COPY_TO_CPU},\ + {"LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_DROP", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_DROP},\ + {"LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_DR_SELECTION", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_DR_SELECTION},\ + {"LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_DR_VSELECT", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_DR_VSELECT},\ + {"LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_EGRESS_PORT", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_EGRESS_PORT},\ + {"LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_EGRESS_PORT_VALID", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_EGRESS_PORT_VALID},\ + {"LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_EGRESS_VC", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_EGRESS_VC},\ + {"LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_MIRROR", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_MIRROR},\ + {"LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_VMAP_PRI_VC", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP_AR_RESULT_VMAP_PRI_VC},\ + {"LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_PORT", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_PORT},\ + {"LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_PORT_VALID", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_PORT_VALID},\ + {"LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_TGID", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_TGID},\ + {"LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_TGID_VALID", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DEST_INFO_DOP_DEST_TGID_VALID},\ + {"LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_DR_PORT_LINK_DOWN", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_DR_PORT_LINK_DOWN},\ + {"LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_DR_SAME_PORT_CHECK_FAIL", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_DR_SAME_PORT_CHECK_FAIL},\ + {"LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_PORT_PROTECTION_ENABLE", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_PORT_PROTECTION_ENABLE},\ + {"LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_SAME_PORT_PROT_ENABLE", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_DR_PORT_INFO_DOP_SAME_PORT_PROT_ENABLE},\ + {"LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP_DR_NEXT_HOP", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP_DR_NEXT_HOP},\ + {"LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP_DR_NEXT_HOP_VALID", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP_DR_NEXT_HOP_VALID},\ + {"LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP_ECMP_MEMBER_INDEX", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP_ECMP_MEMBER_INDEX},\ + {"LPP_IRSEL_RSEL_EGRESS_PORT_INFO_DOP_AR_PATH_CHOICE", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_EGRESS_PORT_INFO_DOP_AR_PATH_CHOICE},\ + {"LPP_IRSEL_RSEL_EGRESS_PORT_INFO_DOP_EGRESS_VC", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_EGRESS_PORT_INFO_DOP_EGRESS_VC},\ + {"LPP_IRSEL_RSEL_METER_INFO_DOP_METER_INDEX", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_METER_INFO_DOP_METER_INDEX},\ + {"LPP_IRSEL_RSEL_METER_INFO_DOP_METER_UPDATE_BITMAP", BCMPKT_TRACE_DOP_LPP_IRSEL_RSEL_METER_INFO_DOP_METER_UPDATE_BITMAP},\ + {"LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP_AUX_COPY_COS_PORT_MAP_KEY", BCMPKT_TRACE_DOP_LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP_AUX_COPY_COS_PORT_MAP_KEY},\ + {"LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP_AUX_COPY_COS_PORT_MAP_MATCH_OUT", BCMPKT_TRACE_DOP_LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP_AUX_COPY_COS_PORT_MAP_MATCH_OUT},\ + {"LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP_AUX_COPY_COS_PORT_MAP_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP_AUX_COPY_COS_PORT_MAP_TCAM_MATCH},\ + {"LPP_ISW_IFA_MIRROR_DOP_CBFCPKT", BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_CBFCPKT},\ + {"LPP_ISW_IFA_MIRROR_DOP_IFA_ACTION", BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_IFA_ACTION},\ + {"LPP_ISW_IFA_MIRROR_DOP_IFA_MD_FORMAT", BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_IFA_MD_FORMAT},\ + {"LPP_ISW_IFA_MIRROR_DOP_LLR_LOSSLESS_PKT", BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_LLR_LOSSLESS_PKT},\ + {"LPP_ISW_IFA_MIRROR_DOP_PORT_IS_AUX", BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_PORT_IS_AUX},\ + {"LPP_ISW_IFA_MIRROR_DOP_SFLOW_ING_FLEX_MIRROR_ENABLE", BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_SFLOW_ING_FLEX_MIRROR_ENABLE},\ + {"LPP_ISW_IFA_MIRROR_DOP_SFLOW_ING_MIRROR_ENABLE", BCMPKT_TRACE_DOP_LPP_ISW_IFA_MIRROR_DOP_SFLOW_ING_MIRROR_ENABLE},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_FP_COUNTER", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_FP_COUNTER},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_INCA_ICRCTR", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_INCA_ICRCTR},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_INCA_MSG_CTR", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_INCA_MSG_CTR},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_ING_VLAN_FILTER_DROP", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_ING_VLAN_FILTER_DROP},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_PARITY_ERROR_DROP", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_PARITY_ERROR_DROP},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_PORT_STATS_IN", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_PORT_STATS_IN},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_PRIORITY_VAL", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_PRIORITY_VAL},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_RDBGC", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RDBGC},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_DISCARD", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_DISCARD},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_DISCARD_IPV4", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_DISCARD_IPV4},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_DISCARD_IPV6", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_DISCARD_IPV6},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_INT_PRI_OR_COS_DISCARD", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_INT_PRI_OR_COS_DISCARD},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_IN_IPV4", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_IN_IPV4},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_IN_IPV6", BCMPKT_TRACE_DOP_LPP_ISW_ING_COUNTER_INCR_DOP_RX_STATS_IN_IPV6},\ + {"LPP_ISW_MISC_2_DOP_CHANGE_DSCP", BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_CHANGE_DSCP},\ + {"LPP_ISW_MISC_2_DOP_CNG", BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_CNG},\ + {"LPP_ISW_MISC_2_DOP_CNP_ELIGIBLE", BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_CNP_ELIGIBLE},\ + {"LPP_ISW_MISC_2_DOP_DCN_ELIGIBLE", BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_DCN_ELIGIBLE},\ + {"LPP_ISW_MISC_2_DOP_FINAL_OUTGOING_DSCP", BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_FINAL_OUTGOING_DSCP},\ + {"LPP_ISW_MISC_2_DOP_FP_CHANGE_ECN", BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_FP_CHANGE_ECN},\ + {"LPP_ISW_MISC_2_DOP_FP_NEW_ECN", BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_FP_NEW_ECN},\ + {"LPP_ISW_MISC_2_DOP_HIGHEST_PRIORITY_DROP_REASON", BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_HIGHEST_PRIORITY_DROP_REASON},\ + {"LPP_ISW_MISC_2_DOP_ING_EVENT_VECTOR", BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_ING_EVENT_VECTOR},\ + {"LPP_ISW_MISC_2_DOP_INT_CN", BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_INT_CN},\ + {"LPP_ISW_MISC_2_DOP_INT_PRI", BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_INT_PRI},\ + {"LPP_ISW_MISC_2_DOP_PRESERVE_DSCP", BCMPKT_TRACE_DOP_LPP_ISW_MISC_2_DOP_PRESERVE_DSCP},\ + {"LPP_ISW_MISC_DOP_COPY_TO_CPU_OPCODE", BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_COPY_TO_CPU_OPCODE},\ + {"LPP_ISW_MISC_DOP_ENTROPY_HASH", BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_ENTROPY_HASH},\ + {"LPP_ISW_MISC_DOP_FORWARDING_PROFILE", BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_FORWARDING_PROFILE},\ + {"LPP_ISW_MISC_DOP_MIRROR", BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_MIRROR},\ + {"LPP_ISW_MISC_DOP_OUTGOING_VLAN_PROFILE", BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_OUTGOING_VLAN_PROFILE},\ + {"LPP_ISW_MISC_DOP_TRUNK_INDEX", BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_TRUNK_INDEX},\ + {"LPP_ISW_MISC_DOP_VPP_AUX_COPY_BITMAP", BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_VPP_AUX_COPY_BITMAP},\ + {"LPP_ISW_MISC_DOP_VPP_SW_COPY_REASON_CODE", BCMPKT_TRACE_DOP_LPP_ISW_MISC_DOP_VPP_SW_COPY_REASON_CODE},\ + {"LPP_ISW_NEXT_HOP_DOP_AR_PORT_TO_NHOP_INDEX", BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_AR_PORT_TO_NHOP_INDEX},\ + {"LPP_ISW_NEXT_HOP_DOP_FINAL_NEXT_HOP", BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_FINAL_NEXT_HOP},\ + {"LPP_ISW_NEXT_HOP_DOP_FINAL_NEXT_HOP_VALID", BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_FINAL_NEXT_HOP_VALID},\ + {"LPP_ISW_NEXT_HOP_DOP_INCA_FLOW_TYPE", BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_INCA_FLOW_TYPE},\ + {"LPP_ISW_NEXT_HOP_DOP_L2_INSTR_RESOLVED_ACTION_PROFILE", BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_L2_INSTR_RESOLVED_ACTION_PROFILE},\ + {"LPP_ISW_NEXT_HOP_DOP_MOD_MMU_ELIGIBLE", BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_MOD_MMU_ELIGIBLE},\ + {"LPP_ISW_NEXT_HOP_DOP_MOD_MMU_PROFILE", BCMPKT_TRACE_DOP_LPP_ISW_NEXT_HOP_DOP_MOD_MMU_PROFILE},\ + {"LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_DEST_PORT", BCMPKT_TRACE_DOP_LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_DEST_PORT},\ + {"LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_PROFILE", BCMPKT_TRACE_DOP_LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_PROFILE},\ + {"LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_QUEUE_NUM", BCMPKT_TRACE_DOP_LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_QUEUE_NUM},\ + {"LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_TRUNCATE_ENABLE", BCMPKT_TRACE_DOP_LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_TRUNCATE_ENABLE},\ + {"LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_VALID", BCMPKT_TRACE_DOP_LPP_ISW_NONSW_COPY_DOP_NONSW_COPY_VALID},\ + {"LPP_ISW_PROTOCOL_TCAM_DOP_PROTOCOL_TCAM_HIT_INDEX", BCMPKT_TRACE_DOP_LPP_ISW_PROTOCOL_TCAM_DOP_PROTOCOL_TCAM_HIT_INDEX},\ + {"LPP_ISW_PROTOCOL_TCAM_DOP_PROTOCOL_TCAM_KEY_INT", BCMPKT_TRACE_DOP_LPP_ISW_PROTOCOL_TCAM_DOP_PROTOCOL_TCAM_KEY_INT},\ + {"LPP_ISW_PROTOCOL_TCAM_DOP_PROTOCOL_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_ISW_PROTOCOL_TCAM_DOP_PROTOCOL_TCAM_MATCH},\ + {"LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP_SW_COPY_COS_PORT_MAP_KEY", BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP_SW_COPY_COS_PORT_MAP_KEY},\ + {"LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP_SW_COPY_COS_PORT_MAP_MATCH_OUT", BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP_SW_COPY_COS_PORT_MAP_MATCH_OUT},\ + {"LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP_SW_COPY_COS_PORT_MAP_TCAM_MATCH", BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP_SW_COPY_COS_PORT_MAP_TCAM_MATCH},\ + {"LPP_ISW_SW_COPY_DOP_SW_COPY_DEST_PORT", BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_DOP_SW_COPY_DEST_PORT},\ + {"LPP_ISW_SW_COPY_DOP_SW_COPY_QUEUE_NUM", BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_DOP_SW_COPY_QUEUE_NUM},\ + {"LPP_ISW_SW_COPY_DOP_SW_COPY_TYPE", BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_DOP_SW_COPY_TYPE},\ + {"LPP_ISW_SW_COPY_DOP_SW_COPY_VALID", BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_DOP_SW_COPY_VALID},\ + {"LPP_ISW_SW_COPY_DOP_UNMOD_PKT_TYPE", BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_DOP_UNMOD_PKT_TYPE},\ + {"LPP_ISW_SW_COPY_DOP_UNMOD_PKT_VALID", BCMPKT_TRACE_DOP_LPP_ISW_SW_COPY_DOP_UNMOD_PKT_VALID},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_0_KEY_DOP_MEM0_0_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_0_KEY_DOP_MEM0_0_KEY},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_0_KEY_DOP_MEM0_0_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_0_KEY_DOP_MEM0_0_PKT_RD},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_1_KEY_DOP_MEM0_1_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_1_KEY_DOP_MEM0_1_KEY},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_1_KEY_DOP_MEM0_1_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_1_KEY_DOP_MEM0_1_PKT_RD},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_2_KEY_DOP_MEM0_2_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_2_KEY_DOP_MEM0_2_KEY},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_2_KEY_DOP_MEM0_2_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_2_KEY_DOP_MEM0_2_PKT_RD},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_3_KEY_DOP_MEM0_3_KEY", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_3_KEY_DOP_MEM0_3_KEY},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_3_KEY_DOP_MEM0_3_PKT_RD", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_3_KEY_DOP_MEM0_3_PKT_RD},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_0_MATCH_INDEX},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_0_TCAM_MATCH},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_1_MATCH_INDEX},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_1_TCAM_MATCH},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_2_MATCH_INDEX},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_2_TCAM_MATCH},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_3_MATCH_INDEX},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH", BCMPKT_TRACE_DOP_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP_MEM0_3_TCAM_MATCH},\ + {"fid count", BCMPKT_TRACE_DOP_FID_COUNT} + +/*! + * \name TRACE DOP IDs. + * \anchor BCMPKT_TRACE_DOP_IDXXX + * \format BCMPKT_TRACE_DOP_ID_ + */ +/*! \{ */ +/*! Invalid BCMPKT_TRACE_DOP_ID FID indicator */ +#define BCMPKT_TRACE_DOP_ID_FID_INVALID -1 +/*! IPARSER0_HME_STAGE0_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER0_HME_STAGE0_DOP 0 +/*! MEMDB_IFTA10_MY_DOP_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA10_MY_DOP_INDEX_DOP 1 +/*! IFTA10_I1T_00_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA10_I1T_00_INDEX_DOP 2 +/*! MEMDB_IFTA20_MY_DOP_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA20_MY_DOP_INDEX_DOP 3 +/*! IFTA20_I1T_00_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA20_I1T_00_INDEX_DOP 4 +/*! IPARSER1_HME_STAGE0_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE0_DOP 5 +/*! IPARSER1_HME_STAGE1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE1_DOP 6 +/*! IPARSER1_HME_STAGE2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE2_DOP 7 +/*! IPARSER1_HME_STAGE3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE3_DOP 8 +/*! IPARSER1_HME_STAGE4_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE4_DOP 9 +/*! IPARSER1_HME_STAGE5_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE5_DOP 10 +/*! IFTA30_E2T_00_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA30_E2T_00_LTS_TCAM_1_KEY_DOP 11 +/*! IFTA30_E2T_00_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA30_E2T_00_LTS_TCAM_0_KEY_DOP 12 +/*! IFTA30_E2T_00_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA30_E2T_00_LTS_TCAM_INDEX_DOP 13 +/*! IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP 14 +/*! IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP 15 +/*! IFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP 16 +/*! IFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP 17 +/*! MEMDB_TCAM_IFTA30_MEM0_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA30_MEM0_1_KEY_DOP 18 +/*! MEMDB_TCAM_IFTA30_MEM0_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA30_MEM0_3_KEY_DOP 19 +/*! MEMDB_TCAM_IFTA30_MEM0_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA30_MEM0_2_KEY_DOP 20 +/*! MEMDB_TCAM_IFTA30_MEM0_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA30_MEM0_0_KEY_DOP 21 +/*! MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP 22 +/*! IPARSER2_HME_STAGE0_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER2_HME_STAGE0_DOP 23 +/*! IPARSER2_HME_STAGE1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER2_HME_STAGE1_DOP 24 +/*! IPARSER2_HME_STAGE2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER2_HME_STAGE2_DOP 25 +/*! IPARSER2_HME_STAGE3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER2_HME_STAGE3_DOP 26 +/*! IPARSER2_HME_STAGE4_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER2_HME_STAGE4_DOP 27 +/*! IFTA40_E2T_01_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_E2T_01_LTS_TCAM_1_KEY_DOP 28 +/*! IFTA40_E2T_01_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_E2T_01_LTS_TCAM_0_KEY_DOP 29 +/*! IFTA40_E2T_01_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_E2T_01_LTS_TCAM_INDEX_DOP 30 +/*! IFTA40_E2T_00_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_E2T_00_LTS_TCAM_1_KEY_DOP 31 +/*! IFTA40_E2T_00_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_E2T_00_LTS_TCAM_0_KEY_DOP 32 +/*! IFTA40_E2T_00_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_E2T_00_LTS_TCAM_INDEX_DOP 33 +/*! IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP 34 +/*! IFTA40_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP 35 +/*! IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP 36 +/*! IFTA40_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP 37 +/*! IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP 38 +/*! IFTA40_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP 39 +/*! IFTA40_T4T_00_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_TCAM_1_KEY_DOP 40 +/*! IFTA40_T4T_00_LTS_TCAM_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_TCAM_3_KEY_DOP 41 +/*! IFTA40_T4T_00_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_TCAM_0_KEY_DOP 42 +/*! IFTA40_T4T_00_LTS_TCAM_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_TCAM_2_KEY_DOP 43 +/*! IFTA40_T4T_00_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP 44 +/*! IFTA40_T4T_01_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_TCAM_1_KEY_DOP 45 +/*! IFTA40_T4T_01_LTS_TCAM_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_TCAM_3_KEY_DOP 46 +/*! IFTA40_T4T_01_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_TCAM_0_KEY_DOP 47 +/*! IFTA40_T4T_01_LTS_TCAM_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_TCAM_2_KEY_DOP 48 +/*! IFTA40_T4T_01_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP 49 +/*! IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP 50 +/*! IFTA40_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP 51 +/*! IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP 52 +/*! IFTA40_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP 53 +/*! MEMDB_TCAM_IFTA40_MEM0_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM0_3_KEY_DOP 54 +/*! MEMDB_TCAM_IFTA40_MEM1_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM1_2_KEY_DOP 55 +/*! MEMDB_TCAM_IFTA40_MEM0_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM0_2_KEY_DOP 56 +/*! MEMDB_TCAM_IFTA40_MEM0_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM0_0_KEY_DOP 57 +/*! MEMDB_TCAM_IFTA40_MEM1_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM1_0_KEY_DOP 58 +/*! MEMDB_TCAM_IFTA40_MEM1_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM1_1_KEY_DOP 59 +/*! MEMDB_TCAM_IFTA40_MEM0_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM0_1_KEY_DOP 60 +/*! MEMDB_TCAM_IFTA40_MEM1_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM1_3_KEY_DOP 61 +/*! MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP 62 +/*! MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP 63 +/*! IFSL40_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFSL40_LTS_TCAM_KEY_DOP 64 +/*! IFSL41_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFSL41_LTS_TCAM_KEY_DOP 65 +/*! IFTA50_T4T_00_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA50_T4T_00_LTS_TCAM_1_KEY_DOP 66 +/*! IFTA50_T4T_00_LTS_TCAM_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA50_T4T_00_LTS_TCAM_3_KEY_DOP 67 +/*! IFTA50_T4T_00_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA50_T4T_00_LTS_TCAM_0_KEY_DOP 68 +/*! IFTA50_T4T_00_LTS_TCAM_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA50_T4T_00_LTS_TCAM_2_KEY_DOP 69 +/*! IFTA50_T4T_00_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP 70 +/*! IFTA50_I1T_00_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA50_I1T_00_INDEX_DOP 71 +/*! IFTA50_I1T_01_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA50_I1T_01_INDEX_DOP 72 +/*! MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_KEY_DOP 73 +/*! MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_HIT_AND_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_HIT_AND_INDEX_DOP 74 +/*! MEMDB_TCAM_IFTA50_MEM0_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA50_MEM0_1_KEY_DOP 75 +/*! MEMDB_TCAM_IFTA50_MEM0_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA50_MEM0_3_KEY_DOP 76 +/*! MEMDB_TCAM_IFTA50_MEM0_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA50_MEM0_2_KEY_DOP 77 +/*! MEMDB_TCAM_IFTA50_MEM0_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA50_MEM0_0_KEY_DOP 78 +/*! MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP 79 +/*! MEMDB_IFTA50_MY_DOP_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA50_MY_DOP_INDEX_DOP 80 +/*! MEMDB_IFTA60_MY_DOP_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA60_MY_DOP_INDEX_DOP 81 +/*! IFTA60_I1T_00_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA60_I1T_00_INDEX_DOP 82 +/*! IFTA60_I1T_01_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA60_I1T_01_INDEX_DOP 83 +/*! IFTA60_I1T_02_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA60_I1T_02_INDEX_DOP 84 +/*! IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP 85 +/*! IFTA60_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA60_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP 86 +/*! MEMDB_TCAM_IFTA60_MEM0_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA60_MEM0_1_KEY_DOP 87 +/*! MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP 88 +/*! MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP 89 +/*! MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP 90 +/*! MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP 91 +/*! FLEX_DIGEST_LKUP_FD_NET_LAYER_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_DIGEST_LKUP_FD_NET_LAYER_KEY_DOP 92 +/*! FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP 93 +/*! FLEX_DIGEST_NORM_FD_NORM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_DIGEST_NORM_FD_NORM_DOP 94 +/*! FLEX_DIGEST_HASH_FD_HASH_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_DIGEST_HASH_FD_HASH_DOP 95 +/*! MEMDB_IFTA70_MY_DOP_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA70_MY_DOP_INDEX_DOP 96 +/*! IFTA70_I1T_00_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA70_I1T_00_INDEX_DOP 97 +/*! IFTA70_I1T_01_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA70_I1T_01_INDEX_DOP 98 +/*! IFSL70_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFSL70_LTS_TCAM_KEY_DOP 99 +/*! IFTA80_E2T_01_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_01_LTS_TCAM_1_KEY_DOP 100 +/*! IFTA80_E2T_01_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_01_LTS_TCAM_0_KEY_DOP 101 +/*! IFTA80_E2T_01_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_01_LTS_TCAM_INDEX_DOP 102 +/*! IFTA80_E2T_00_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_00_LTS_TCAM_1_KEY_DOP 103 +/*! IFTA80_E2T_00_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_00_LTS_TCAM_0_KEY_DOP 104 +/*! IFTA80_E2T_00_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_00_LTS_TCAM_INDEX_DOP 105 +/*! IFTA80_E2T_03_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_03_LTS_TCAM_1_KEY_DOP 106 +/*! IFTA80_E2T_03_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_03_LTS_TCAM_0_KEY_DOP 107 +/*! IFTA80_E2T_03_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_03_LTS_TCAM_INDEX_DOP 108 +/*! IFTA80_E2T_02_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_02_LTS_TCAM_1_KEY_DOP 109 +/*! IFTA80_E2T_02_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_02_LTS_TCAM_0_KEY_DOP 110 +/*! IFTA80_E2T_02_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_02_LTS_TCAM_INDEX_DOP 111 +/*! IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP 112 +/*! IFTA80_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP 113 +/*! IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP 114 +/*! IFTA80_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP 115 +/*! IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP 116 +/*! IFTA80_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP 117 +/*! IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP 118 +/*! IFTA80_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP 119 +/*! IFTA80_T2T_01_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_T2T_01_LTS_TCAM_1_KEY_DOP 120 +/*! IFTA80_T2T_01_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_T2T_01_LTS_TCAM_0_KEY_DOP 121 +/*! IFTA80_T2T_01_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_T2T_01_LTS_TCAM_INDEX_DOP 122 +/*! IFTA80_T2T_00_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_T2T_00_LTS_TCAM_1_KEY_DOP 123 +/*! IFTA80_T2T_00_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_T2T_00_LTS_TCAM_0_KEY_DOP 124 +/*! IFTA80_T2T_00_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_T2T_00_LTS_TCAM_INDEX_DOP 125 +/*! IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP 126 +/*! IFTA80_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP 127 +/*! IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP 128 +/*! IFTA80_T2T_01_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA80_T2T_01_LTS_PRE_SEL_MUX_OUT_DOP 129 +/*! FLEX_QOS_PHB_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_QOS_PHB_LTS_TCAM_KEY_DOP 130 +/*! FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP 131 +/*! FLEX_QOS_PHB2_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_QOS_PHB2_LTS_TCAM_KEY_DOP 132 +/*! FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP 133 +/*! MEMDB_TCAM_IFTA80_MEM2_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM2_0_KEY_DOP 134 +/*! MEMDB_TCAM_IFTA80_MEM1_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM1_0_KEY_DOP 135 +/*! MEMDB_TCAM_IFTA80_MEM7_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM7_1_KEY_DOP 136 +/*! MEMDB_TCAM_IFTA80_MEM6_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM6_0_KEY_DOP 137 +/*! MEMDB_TCAM_IFTA80_MEM5_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM5_0_KEY_DOP 138 +/*! MEMDB_TCAM_IFTA80_MEM2_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM2_1_KEY_DOP 139 +/*! MEMDB_TCAM_IFTA80_MEM5_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM5_1_KEY_DOP 140 +/*! MEMDB_TCAM_IFTA80_MEM0_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM0_0_KEY_DOP 141 +/*! MEMDB_TCAM_IFTA80_MEM6_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM6_1_KEY_DOP 142 +/*! MEMDB_TCAM_IFTA80_MEM1_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM1_1_KEY_DOP 143 +/*! MEMDB_TCAM_IFTA80_MEM4_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM4_0_KEY_DOP 144 +/*! MEMDB_TCAM_IFTA80_MEM3_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM3_1_KEY_DOP 145 +/*! MEMDB_TCAM_IFTA80_MEM0_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM0_1_KEY_DOP 146 +/*! MEMDB_TCAM_IFTA80_MEM4_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM4_1_KEY_DOP 147 +/*! MEMDB_TCAM_IFTA80_MEM7_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM7_0_KEY_DOP 148 +/*! MEMDB_TCAM_IFTA80_MEM3_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM3_0_KEY_DOP 149 +/*! MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP 150 +/*! MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP 151 +/*! MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP 152 +/*! MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP 153 +/*! MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP 154 +/*! MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP 155 +/*! MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP 156 +/*! MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP 157 +/*! IFTA90_E2T_03_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_03_LTS_TCAM_1_KEY_DOP 158 +/*! IFTA90_E2T_03_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_03_LTS_TCAM_0_KEY_DOP 159 +/*! IFTA90_E2T_03_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_03_LTS_TCAM_INDEX_DOP 160 +/*! IFTA90_E2T_01_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_01_LTS_TCAM_1_KEY_DOP 161 +/*! IFTA90_E2T_01_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_01_LTS_TCAM_0_KEY_DOP 162 +/*! IFTA90_E2T_01_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_01_LTS_TCAM_INDEX_DOP 163 +/*! IFTA90_E2T_00_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_00_LTS_TCAM_1_KEY_DOP 164 +/*! IFTA90_E2T_00_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_00_LTS_TCAM_0_KEY_DOP 165 +/*! IFTA90_E2T_00_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_00_LTS_TCAM_INDEX_DOP 166 +/*! IFTA90_E2T_02_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_02_LTS_TCAM_1_KEY_DOP 167 +/*! IFTA90_E2T_02_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_02_LTS_TCAM_0_KEY_DOP 168 +/*! IFTA90_E2T_02_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_02_LTS_TCAM_INDEX_DOP 169 +/*! IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP 170 +/*! IFTA90_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP 171 +/*! IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP 172 +/*! IFTA90_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP 173 +/*! IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP 174 +/*! IFTA90_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP 175 +/*! IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP 176 +/*! IFTA90_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA90_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP 177 +/*! FLEX_CTR_ST_ING0_COUNTER_ACTION_VECTOR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_ACTION_VECTOR_DOP 178 +/*! FLEX_CTR_ST_ING0_COUNTER_POOL_1_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_POOL_1_UPDATE_CMD_DOP 179 +/*! FLEX_CTR_ST_ING0_COUNTER_POOL_2_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_POOL_2_UPDATE_CMD_DOP 180 +/*! FLEX_CTR_ST_ING0_COUNTER_POOL_3_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_POOL_3_UPDATE_CMD_DOP 181 +/*! FLEX_CTR_ST_ING0_COUNTER_POOL_0_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_POOL_0_UPDATE_CMD_DOP 182 +/*! FLEX_CTR_ST_ING0_COUNTER_B_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_B_DOP 183 +/*! FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP 184 +/*! FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP 185 +/*! FLEX_CTR_ST_ING0_COUNTER_A_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_A_DOP 186 +/*! IFSL90_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFSL90_LTS_TCAM_KEY_DOP 187 +/*! IFSL91_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFSL91_LTS_TCAM_KEY_DOP 188 +/*! IFTA100_T4T_00_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_TCAM_1_KEY_DOP 189 +/*! IFTA100_T4T_00_LTS_TCAM_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_TCAM_3_KEY_DOP 190 +/*! IFTA100_T4T_00_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_TCAM_0_KEY_DOP 191 +/*! IFTA100_T4T_00_LTS_TCAM_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_TCAM_2_KEY_DOP 192 +/*! IFTA100_T4T_00_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP 193 +/*! IFTA100_T4T_02_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_TCAM_1_KEY_DOP 194 +/*! IFTA100_T4T_02_LTS_TCAM_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_TCAM_3_KEY_DOP 195 +/*! IFTA100_T4T_02_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_TCAM_0_KEY_DOP 196 +/*! IFTA100_T4T_02_LTS_TCAM_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_TCAM_2_KEY_DOP 197 +/*! IFTA100_T4T_02_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP 198 +/*! IFTA100_T4T_01_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_TCAM_1_KEY_DOP 199 +/*! IFTA100_T4T_01_LTS_TCAM_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_TCAM_3_KEY_DOP 200 +/*! IFTA100_T4T_01_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_TCAM_0_KEY_DOP 201 +/*! IFTA100_T4T_01_LTS_TCAM_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_TCAM_2_KEY_DOP 202 +/*! IFTA100_T4T_01_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP 203 +/*! IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP 204 +/*! IFTA100_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP 205 +/*! IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP 206 +/*! IFTA100_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP 207 +/*! IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP 208 +/*! IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP 209 +/*! IFTA100_T4T_02_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_PRE_SEL_MUX_OUT_DOP 210 +/*! IFTA100_T4T_03_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA100_T4T_03_LTS_PRE_SEL_MUX_OUT_DOP 211 +/*! MEMDB_IFTA100_MEM1_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM1_2_KEY_DOP 212 +/*! MEMDB_IFTA100_MEM0_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM0_2_KEY_DOP 213 +/*! MEMDB_IFTA100_MEM7_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM7_2_KEY_DOP 214 +/*! MEMDB_IFTA100_MEM8_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM8_2_KEY_DOP 215 +/*! MEMDB_IFTA100_MEM9_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM9_0_KEY_DOP 216 +/*! MEMDB_IFTA100_MEM11_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM11_3_KEY_DOP 217 +/*! MEMDB_IFTA100_MEM7_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM7_3_KEY_DOP 218 +/*! MEMDB_IFTA100_MEM8_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM8_0_KEY_DOP 219 +/*! MEMDB_IFTA100_MEM10_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM10_2_KEY_DOP 220 +/*! MEMDB_IFTA100_MEM5_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM5_0_KEY_DOP 221 +/*! MEMDB_IFTA100_MEM3_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM3_2_KEY_DOP 222 +/*! MEMDB_IFTA100_MEM8_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM8_3_KEY_DOP 223 +/*! MEMDB_IFTA100_MEM11_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM11_0_KEY_DOP 224 +/*! MEMDB_IFTA100_MEM2_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM2_1_KEY_DOP 225 +/*! MEMDB_IFTA100_MEM4_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM4_3_KEY_DOP 226 +/*! MEMDB_IFTA100_MEM4_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM4_2_KEY_DOP 227 +/*! MEMDB_IFTA100_MEM5_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM5_3_KEY_DOP 228 +/*! MEMDB_IFTA100_MEM10_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM10_1_KEY_DOP 229 +/*! MEMDB_IFTA100_MEM6_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM6_1_KEY_DOP 230 +/*! MEMDB_IFTA100_MEM10_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM10_3_KEY_DOP 231 +/*! MEMDB_IFTA100_MEM4_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM4_1_KEY_DOP 232 +/*! MEMDB_IFTA100_MEM9_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM9_2_KEY_DOP 233 +/*! MEMDB_IFTA100_MEM3_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM3_0_KEY_DOP 234 +/*! MEMDB_IFTA100_MEM2_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM2_0_KEY_DOP 235 +/*! MEMDB_IFTA100_MEM1_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM1_0_KEY_DOP 236 +/*! MEMDB_IFTA100_MEM11_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM11_1_KEY_DOP 237 +/*! MEMDB_IFTA100_MEM2_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM2_2_KEY_DOP 238 +/*! MEMDB_IFTA100_MEM8_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM8_1_KEY_DOP 239 +/*! MEMDB_IFTA100_MEM7_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM7_1_KEY_DOP 240 +/*! MEMDB_IFTA100_MEM9_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM9_3_KEY_DOP 241 +/*! MEMDB_IFTA100_MEM6_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM6_0_KEY_DOP 242 +/*! MEMDB_IFTA100_MEM6_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM6_2_KEY_DOP 243 +/*! MEMDB_IFTA100_MEM9_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM9_1_KEY_DOP 244 +/*! MEMDB_IFTA100_MEM5_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM5_1_KEY_DOP 245 +/*! MEMDB_IFTA100_MEM0_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM0_3_KEY_DOP 246 +/*! MEMDB_IFTA100_MEM3_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM3_3_KEY_DOP 247 +/*! MEMDB_IFTA100_MEM0_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM0_0_KEY_DOP 248 +/*! MEMDB_IFTA100_MEM1_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM1_1_KEY_DOP 249 +/*! MEMDB_IFTA100_MEM4_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM4_0_KEY_DOP 250 +/*! MEMDB_IFTA100_MEM3_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM3_1_KEY_DOP 251 +/*! MEMDB_IFTA100_MEM2_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM2_3_KEY_DOP 252 +/*! MEMDB_IFTA100_MEM10_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM10_0_KEY_DOP 253 +/*! MEMDB_IFTA100_MEM6_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM6_3_KEY_DOP 254 +/*! MEMDB_IFTA100_MEM0_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM0_1_KEY_DOP 255 +/*! MEMDB_IFTA100_MEM5_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM5_2_KEY_DOP 256 +/*! MEMDB_IFTA100_MEM7_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM7_0_KEY_DOP 257 +/*! MEMDB_IFTA100_MEM1_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM1_3_KEY_DOP 258 +/*! MEMDB_IFTA100_MEM11_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM11_2_KEY_DOP 259 +/*! MEMDB_IFTA100_MEM9_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM9_INDEX_DOP 260 +/*! MEMDB_IFTA100_MEM10_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM10_INDEX_DOP 261 +/*! MEMDB_IFTA100_MEM7_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM7_INDEX_DOP 262 +/*! MEMDB_IFTA100_MEM5_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM5_INDEX_DOP 263 +/*! MEMDB_IFTA100_MEM8_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM8_INDEX_DOP 264 +/*! MEMDB_IFTA100_MEM2_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM2_INDEX_DOP 265 +/*! MEMDB_IFTA100_MEM11_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM11_INDEX_DOP 266 +/*! MEMDB_IFTA100_MEM6_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM6_INDEX_DOP 267 +/*! MEMDB_IFTA100_MEM1_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM1_INDEX_DOP 268 +/*! MEMDB_IFTA100_MEM4_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM4_INDEX_DOP 269 +/*! MEMDB_IFTA100_MEM3_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM3_INDEX_DOP 270 +/*! MEMDB_IFTA100_MEM0_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM0_INDEX_DOP 271 +/*! IFSL100_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFSL100_LTS_TCAM_KEY_DOP 272 +/*! ECMP_GROUP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_GROUP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP 273 +/*! ECMP_GROUP_LEVEL0_GROUP_TABLE_DATA_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_GROUP_LEVEL0_GROUP_TABLE_DATA_DOP 274 +/*! ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP 275 +/*! MEMDB_IFTA110_MY_DOP_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA110_MY_DOP_INDEX_DOP 276 +/*! ETRAP_ETR_HIT_RTAG_HASH_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ETRAP_ETR_HIT_RTAG_HASH_DOP 277 +/*! ETRAP_ETR_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ETRAP_ETR_OUT_DOP 278 +/*! DLB_ECMP_DLB_ECMP_CURRENT_TIME_DOP. */ +#define BCMPKT_TRACE_DOP_ID_DLB_ECMP_DLB_ECMP_CURRENT_TIME_DOP 279 +/*! DLB_ECMP_DLB_ECMP_FLOWSET_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_DLB_ECMP_DLB_ECMP_FLOWSET_INDEX_DOP 280 +/*! ECMP_GROUP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_GROUP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP 281 +/*! ECMP_GROUP_LEVEL1_GROUP_TABLE_DATA_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_GROUP_LEVEL1_GROUP_TABLE_DATA_DOP 282 +/*! ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP 283 +/*! MEMDB_IFTA120_MY_DOP_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA120_MY_DOP_INDEX_DOP 284 +/*! MEMDB_IFTA130_MY_DOP_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA130_MY_DOP_INDEX_DOP 285 +/*! IFTA130_I1T_00_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA130_I1T_00_INDEX_DOP 286 +/*! IFTA130_I1T_01_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA130_I1T_01_INDEX_DOP 287 +/*! IFTA130_I1T_02_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA130_I1T_02_INDEX_DOP 288 +/*! IFTA130_I1T_03_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA130_I1T_03_INDEX_DOP 289 +/*! MEMDB_IFTA140_MY_DOP_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA140_MY_DOP_INDEX_DOP 290 +/*! IFTA140_I1T_00_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA140_I1T_00_INDEX_DOP 291 +/*! IFTA140_I1T_01_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA140_I1T_01_INDEX_DOP 292 +/*! FLEX_CTR_ST_ING1_COUNTER_ACTION_VECTOR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_ACTION_VECTOR_DOP 293 +/*! FLEX_CTR_ST_ING1_COUNTER_POOL_1_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_POOL_1_UPDATE_CMD_DOP 294 +/*! FLEX_CTR_ST_ING1_COUNTER_POOL_2_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_POOL_2_UPDATE_CMD_DOP 295 +/*! FLEX_CTR_ST_ING1_COUNTER_POOL_3_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_POOL_3_UPDATE_CMD_DOP 296 +/*! FLEX_CTR_ST_ING1_COUNTER_POOL_0_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_POOL_0_UPDATE_CMD_DOP 297 +/*! FLEX_CTR_ST_ING1_COUNTER_B_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_B_DOP 298 +/*! FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP 299 +/*! FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP 300 +/*! FLEX_CTR_ST_ING1_COUNTER_A_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_A_DOP 301 +/*! IFTA150_T4T_00_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_TCAM_1_KEY_DOP 302 +/*! IFTA150_T4T_00_LTS_TCAM_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_TCAM_3_KEY_DOP 303 +/*! IFTA150_T4T_00_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_TCAM_0_KEY_DOP 304 +/*! IFTA150_T4T_00_LTS_TCAM_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_TCAM_2_KEY_DOP 305 +/*! IFTA150_T4T_00_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP 306 +/*! IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP 307 +/*! IFTA150_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP 308 +/*! MEMDB_IFTA150_MEM0_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA150_MEM0_1_KEY_DOP 309 +/*! MEMDB_IFTA150_MEM0_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA150_MEM0_3_KEY_DOP 310 +/*! MEMDB_IFTA150_MEM0_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA150_MEM0_2_KEY_DOP 311 +/*! MEMDB_IFTA150_MEM0_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA150_MEM0_0_KEY_DOP 312 +/*! MEMDB_IFTA150_MEM0_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA150_MEM0_INDEX_DOP 313 +/*! IPOST_DLB_LAG_DLB_LAG_CURRENT_TIME_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_DLB_LAG_DLB_LAG_CURRENT_TIME_DOP 314 +/*! IPOST_DLB_LAG_DLB_LAG_FLOWSET_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_DLB_LAG_DLB_LAG_FLOWSET_INDEX_DOP 315 +/*! IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP 316 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP 317 +/*! IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP 318 +/*! IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_KEY_DOP 319 +/*! IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_INDEX_DOP 320 +/*! IPOST_CPU_COS_CPU_COS_MAP_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_CPU_COS_CPU_COS_MAP_TCAM_KEY_DOP 321 +/*! IPOST_CPU_COS_CPU_COS_MAP_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_CPU_COS_CPU_COS_MAP_TCAM_INDEX_DOP 322 +/*! IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP 323 +/*! IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP 324 +/*! IPOST_MPB_ENCODE_MPB_FLEX_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_MPB_ENCODE_MPB_FLEX_BUS_DOP 325 +/*! IPOST_MPB_CCBI_FIXED_CCBI_B_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_MPB_CCBI_FIXED_CCBI_B_BUS_DOP 326 +/*! IPOST_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP 327 +/*! FLEX_CTR_ING_COUNTER_ACTION_VECTOR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_ACTION_VECTOR_DOP 328 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_2_DOP 329 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_11_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_11_DOP 330 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_8_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_8_DOP 331 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_7_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_7_DOP 332 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_5_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_5_DOP 333 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_9_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_9_DOP 334 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_6_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_6_DOP 335 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_0_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_0_DOP 336 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_1_DOP 337 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_4_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_4_DOP 338 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_3_DOP 339 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_10_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_10_DOP 340 +/*! IFSL140_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFSL140_LTS_TCAM_KEY_DOP 341 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_4_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_4_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP 342 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_1_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_1_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP 343 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_3_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_3_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP 344 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_2_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_2_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP 345 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_0_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_0_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP 346 +/*! EPRE_PARSER_ZONE_REMAP_EGR_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_EGR_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP 347 +/*! EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER0_CTRL_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER0_CTRL_DOP 348 +/*! EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER1_CTRL_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER1_CTRL_DOP 349 +/*! EPRE_EDEV_CONFIG_EGR_INT_CN_UPDATE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_EGR_INT_CN_UPDATE_INDEX_DOP 350 +/*! EPRE_EDEV_CONFIG_FORWARDING_TYPE_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_FORWARDING_TYPE_TABLE_INDEX_DOP 351 +/*! EPRE_EDEV_CONFIG_MPB_FIXED_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_MPB_FIXED_DOP 352 +/*! EPRE_EDEV_CONFIG_CCBE_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_CCBE_DOP 353 +/*! EPRE_EDEV_CONFIG_EGR_TABLE_INDEX_UPDATE_PROFILE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_EGR_TABLE_INDEX_UPDATE_PROFILE_INDEX_DOP 354 +/*! EPRE_EDEV_CONFIG_MIRROR_ATTRIBUTES_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_MIRROR_ATTRIBUTES_TABLE_INDEX_DOP 355 +/*! EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP 356 +/*! MEMDB_EFTA10_MY_DOP_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_EFTA10_MY_DOP_INDEX_DOP 357 +/*! EFTA10_I1T_00_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA10_I1T_00_INDEX_DOP 358 +/*! EFTA10_I1T_01_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA10_I1T_01_INDEX_DOP 359 +/*! EFTA10_I1T_02_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA10_I1T_02_INDEX_DOP 360 +/*! EFTA10_I1T_03_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA10_I1T_03_INDEX_DOP 361 +/*! MEMDB_EFTA20_MY_DOP_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_EFTA20_MY_DOP_INDEX_DOP 362 +/*! EFTA20_I1T_00_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA20_I1T_00_INDEX_DOP 363 +/*! EFTA20_I1T_01_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA20_I1T_01_INDEX_DOP 364 +/*! EFTA20_I1T_02_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA20_I1T_02_INDEX_DOP 365 +/*! EFTA20_I1T_03_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA20_I1T_03_INDEX_DOP 366 +/*! EFTA20_I1T_04_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA20_I1T_04_INDEX_DOP 367 +/*! EFTA20_I1T_05_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA20_I1T_05_INDEX_DOP 368 +/*! EFTA20_I1T_06_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA20_I1T_06_INDEX_DOP 369 +/*! EFSL20_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFSL20_LTS_TCAM_KEY_DOP 370 +/*! EFTA30_E2T_00_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_E2T_00_LTS_TCAM_1_KEY_DOP 371 +/*! EFTA30_E2T_00_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_E2T_00_LTS_TCAM_0_KEY_DOP 372 +/*! EFTA30_E2T_00_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_E2T_00_LTS_TCAM_INDEX_DOP 373 +/*! EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP 374 +/*! EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP 375 +/*! EFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP 376 +/*! EFTA30_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP 377 +/*! EFTA30_T4T_00_LTS_TCAM_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_TCAM_1_KEY_DOP 378 +/*! EFTA30_T4T_00_LTS_TCAM_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_TCAM_3_KEY_DOP 379 +/*! EFTA30_T4T_00_LTS_TCAM_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_TCAM_0_KEY_DOP 380 +/*! EFTA30_T4T_00_LTS_TCAM_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_TCAM_2_KEY_DOP 381 +/*! EFTA30_T4T_00_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP 382 +/*! EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP 383 +/*! EFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP 384 +/*! EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP 385 +/*! EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP 386 +/*! FLEX_CTR_ST_EGR_COUNTER_ACTION_VECTOR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_ACTION_VECTOR_DOP 387 +/*! FLEX_CTR_ST_EGR_COUNTER_POOL_1_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_POOL_1_UPDATE_CMD_DOP 388 +/*! FLEX_CTR_ST_EGR_COUNTER_POOL_2_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_POOL_2_UPDATE_CMD_DOP 389 +/*! FLEX_CTR_ST_EGR_COUNTER_POOL_3_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_POOL_3_UPDATE_CMD_DOP 390 +/*! FLEX_CTR_ST_EGR_COUNTER_POOL_0_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_POOL_0_UPDATE_CMD_DOP 391 +/*! FLEX_CTR_ST_EGR_COUNTER_B_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_B_DOP 392 +/*! FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP 393 +/*! FLEX_CTR_ST_EGR_COUNTER_A_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_A_DOP 394 +/*! FLEX_CTR_ST_EGR0_COUNTER_ACTION_VECTOR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_ACTION_VECTOR_DOP 395 +/*! FLEX_CTR_ST_EGR0_COUNTER_POOL_1_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_POOL_1_UPDATE_CMD_DOP 396 +/*! FLEX_CTR_ST_EGR0_COUNTER_POOL_2_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_POOL_2_UPDATE_CMD_DOP 397 +/*! FLEX_CTR_ST_EGR0_COUNTER_POOL_3_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_POOL_3_UPDATE_CMD_DOP 398 +/*! FLEX_CTR_ST_EGR0_COUNTER_POOL_0_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_POOL_0_UPDATE_CMD_DOP 399 +/*! FLEX_CTR_ST_EGR0_COUNTER_B_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_B_DOP 400 +/*! FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP 401 +/*! FLEX_CTR_ST_EGR0_COUNTER_A_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_A_DOP 402 +/*! FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP 403 +/*! FLEX_CTR_ST_EGR1_COUNTER_ACTION_VECTOR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_ACTION_VECTOR_DOP 404 +/*! FLEX_CTR_ST_EGR1_COUNTER_POOL_1_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_POOL_1_UPDATE_CMD_DOP 405 +/*! FLEX_CTR_ST_EGR1_COUNTER_POOL_2_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_POOL_2_UPDATE_CMD_DOP 406 +/*! FLEX_CTR_ST_EGR1_COUNTER_POOL_3_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_POOL_3_UPDATE_CMD_DOP 407 +/*! FLEX_CTR_ST_EGR1_COUNTER_POOL_0_UPDATE_CMD_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_POOL_0_UPDATE_CMD_DOP 408 +/*! FLEX_CTR_ST_EGR1_COUNTER_B_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_B_DOP 409 +/*! FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP 410 +/*! FLEX_CTR_ST_EGR1_COUNTER_A_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_A_DOP 411 +/*! FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP 412 +/*! MEMDB_TCAM_EFTA30_MEM0_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_EFTA30_MEM0_1_KEY_DOP 413 +/*! MEMDB_TCAM_EFTA30_MEM0_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_EFTA30_MEM0_3_KEY_DOP 414 +/*! MEMDB_TCAM_EFTA30_MEM0_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_EFTA30_MEM0_2_KEY_DOP 415 +/*! MEMDB_TCAM_EFTA30_MEM0_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_EFTA30_MEM0_0_KEY_DOP 416 +/*! MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP 417 +/*! EFSL30_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFSL30_LTS_TCAM_KEY_DOP 418 +/*! EGR_MIRROR_MIRROR2EDIT_CTRL_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_MIRROR_MIRROR2EDIT_CTRL_BUS_DOP 419 +/*! QOS_REMARKING_LTS_TCAM_ONLY_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_QOS_REMARKING_LTS_TCAM_ONLY_KEY_DOP 420 +/*! QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP 421 +/*! QOS_REMARKING_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_QOS_REMARKING_LTS_TCAM_KEY_DOP 422 +/*! QOS_REMARKING_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_QOS_REMARKING_LTS_TCAM_INDEX_DOP 423 +/*! QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP 424 +/*! EDIT_CTRL_ZONE_4_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_4_TCAM_KEY_DOP 425 +/*! EDIT_CTRL_ZONE_3_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_3_TCAM_KEY_DOP 426 +/*! EDIT_CTRL_ZONE_1_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_1_TCAM_KEY_DOP 427 +/*! EDIT_CTRL_ZONE_2_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_2_TCAM_KEY_DOP 428 +/*! EDIT_CTRL_ZONE_0_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_0_TCAM_KEY_DOP 429 +/*! EDIT_CTRL_ZONE_0_TCAM_HIT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP 430 +/*! EDIT_CTRL_ZONE_4_TCAM_HIT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP 431 +/*! EDIT_CTRL_ZONE_3_TCAM_HIT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP 432 +/*! EDIT_CTRL_ZONE_2_TCAM_HIT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP 433 +/*! EDIT_CTRL_ZONE_1_TCAM_HIT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP 434 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP 435 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP 436 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP 437 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP 438 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP 439 +/*! EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP 440 +/*! EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP 441 +/*! EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP 442 +/*! EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP 443 +/*! EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP 444 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_2_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_2_PROFILE_PTR_DOP 445 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_2_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_2_PROFILE_PTR_DOP 446 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_RW_1_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_1_PROFILE_PTR_DOP 447 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_1_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_1_PROFILE_PTR_DOP 448 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_1_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_1_PROFILE_PTR_DOP 449 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_0_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_0_PROFILE_PTR_DOP 450 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_3_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_3_PROFILE_PTR_DOP 451 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_RW_0_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_0_PROFILE_PTR_DOP 452 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_0_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_0_PROFILE_PTR_DOP 453 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_0_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_0_PROFILE_PTR_DOP 454 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_0_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_0_PROFILE_PTR_DOP 455 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_2_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_2_PROFILE_PTR_DOP 456 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_1_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_1_PROFILE_PTR_DOP 457 +/*! EGR_SEQUENCE_MIRROR_SEQUENCE_NUMBER_PROFILE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_MIRROR_SEQUENCE_NUMBER_PROFILE_INDEX_DOP 458 +/*! EGR_SEQUENCE_SEQUENCE_NUMBER_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_SEQUENCE_NUMBER_TABLE_INDEX_DOP 459 +/*! EGR_SEQUENCE_SEQUENCE_PROFILE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_SEQUENCE_PROFILE_INDEX_DOP 460 +/*! EGR_SEQUENCE_NEW_SEQUENCE_NUM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_NEW_SEQUENCE_NUM_DOP 461 +/*! EGR_SEQUENCE_PKT_SEQUENCE_NUM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_PKT_SEQUENCE_NUM_DOP 462 +/*! FLEX_EDITOR_MATCH_ID_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_EDITOR_MATCH_ID_DOP 463 +/*! FLEX_EDITOR_VHLEN_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_EDITOR_VHLEN_DOP 464 +/*! FLEX_EDITOR_EDIT_ID_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_EDITOR_EDIT_ID_DOP 465 +/*! FLEX_CTR_EGR_COUNTER_ACTION_VECTOR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_ACTION_VECTOR_DOP 466 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_2_DOP 467 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_7_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_7_DOP 468 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_5_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_5_DOP 469 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_6_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_6_DOP 470 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_0_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_0_DOP 471 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_1_DOP 472 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_4_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_4_DOP 473 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_3_DOP 474 +/*! APU_EGR0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_EGR0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP 475 +/*! APU_EGR1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_EGR1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP 476 +/*! APU_ING0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_ING0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP 477 +/*! APU_ING1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_ING1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP 478 +/*! ECMP_LEVEL0_GROUP_TABLE_DATA_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_LEVEL0_GROUP_TABLE_DATA_DOP 479 +/*! ECMP_LEVEL0_MEMBER_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_LEVEL0_MEMBER_INDEX_DOP 480 +/*! ECMP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP 481 +/*! ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP 482 +/*! ECMP_LEVEL1_MEMBER_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_LEVEL1_MEMBER_INDEX_DOP 483 +/*! ECMP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP 484 +/*! EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP 485 +/*! EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP 486 +/*! EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP 487 +/*! EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP 488 +/*! EFTA40_I1T_00_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA40_I1T_00_INDEX_DOP 489 +/*! EFTA40_I1T_01_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA40_I1T_01_INDEX_DOP 490 +/*! EFTA40_I1T_02_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA40_I1T_02_INDEX_DOP 491 +/*! EFTA40_I1T_03_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA40_I1T_03_INDEX_DOP 492 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP 493 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP 494 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP 495 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP 496 +/*! EPRE_PARSER_ZONE_REMAP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP 497 +/*! FLEX_EDITOR_ARC_ID_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_EDITOR_ARC_ID_DOP 498 +/*! HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP 499 +/*! HDR_STACK_EGR_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_HDR_STACK_EGR_LTS_TCAM_INDEX_DOP 500 +/*! HDR_STACK_EGR_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_HDR_STACK_EGR_LTS_TCAM_KEY_DOP 501 +/*! HDR_STACK_ING_LTS_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_HDR_STACK_ING_LTS_TCAM_INDEX_DOP 502 +/*! HDR_STACK_ING_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_HDR_STACK_ING_LTS_TCAM_KEY_DOP 503 +/*! IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP 504 +/*! IFTA5_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA5_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP 505 +/*! IPARSER1_HME_STAGE6_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE6_DOP 506 +/*! IPARSER1_HME_STAGE7_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE7_DOP 507 +/*! IPARSER2_HME_STAGE5_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARSER2_HME_STAGE5_DOP 508 +/*! MEMDB_TCAM_IFTA5_MEM0_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA5_MEM0_0_KEY_DOP 509 +/*! MEMDB_TCAM_IFTA5_MEM0_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA5_MEM0_1_KEY_DOP 510 +/*! MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP 511 +/*! MEMDB_TCAM_IFTA5_MEM1_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA5_MEM1_0_KEY_DOP 512 +/*! MEMDB_TCAM_IFTA5_MEM1_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA5_MEM1_1_KEY_DOP 513 +/*! MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP 514 +/*! APU_EGR0_APU_TCAM_HIT_VECTOR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_EGR0_APU_TCAM_HIT_VECTOR_DOP 515 +/*! APU_EGR0_APU_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_EGR0_APU_TCAM_KEY_DOP 516 +/*! APU_EGR0_APU_TCAM_POLICY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_EGR0_APU_TCAM_POLICY_DOP 517 +/*! APU_EGR0_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_EGR0_LTS_TCAM_KEY_DOP 518 +/*! APU_EGR1_APU_TCAM_HIT_VECTOR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_EGR1_APU_TCAM_HIT_VECTOR_DOP 519 +/*! APU_EGR1_APU_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_EGR1_APU_TCAM_KEY_DOP 520 +/*! APU_EGR1_APU_TCAM_POLICY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_EGR1_APU_TCAM_POLICY_DOP 521 +/*! APU_EGR1_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_EGR1_LTS_TCAM_KEY_DOP 522 +/*! APU_ING0_APU_TCAM_HIT_VECTOR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_ING0_APU_TCAM_HIT_VECTOR_DOP 523 +/*! APU_ING0_APU_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_ING0_APU_TCAM_KEY_DOP 524 +/*! APU_ING0_APU_TCAM_POLICY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_ING0_APU_TCAM_POLICY_DOP 525 +/*! APU_ING0_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_ING0_LTS_TCAM_KEY_DOP 526 +/*! APU_ING1_APU_TCAM_HIT_VECTOR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_ING1_APU_TCAM_HIT_VECTOR_DOP 527 +/*! APU_ING1_APU_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_ING1_APU_TCAM_KEY_DOP 528 +/*! APU_ING1_APU_TCAM_POLICY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_ING1_APU_TCAM_POLICY_DOP 529 +/*! APU_ING1_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_APU_ING1_LTS_TCAM_KEY_DOP 530 +/*! ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP 531 +/*! ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP 532 +/*! ECMP_LEVEL1_DLB_NHI_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_LEVEL1_DLB_NHI_DOP 533 +/*! ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP 534 +/*! EFSL40_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFSL40_LTS_TCAM_KEY_DOP 535 +/*! EFSL41_LTS_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFSL41_LTS_TCAM_KEY_DOP 536 +/*! EFTA10_I1T_04_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFTA10_I1T_04_INDEX_DOP 537 +/*! EGR_MIRROR_ENCAP_1_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_MIRROR_ENCAP_1_TABLE_INDEX_DOP 538 +/*! EGR_MIRROR_ENCAP_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_MIRROR_ENCAP_TABLE_INDEX_DOP 539 +/*! EGR_MIRROR_MIRROR2EDITOR2_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_MIRROR_MIRROR2EDITOR2_BUS_DOP 540 +/*! EGR_MIRROR_MIRROR2EDITOR_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_MIRROR_MIRROR2EDITOR_BUS_DOP 541 +/*! EGR_MIRROR_SESSION_CONTROL_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_MIRROR_SESSION_CONTROL_TABLE_INDEX_DOP 542 +/*! EGR_SEQUENCE_NUMBER_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_NUMBER_TABLE_INDEX_DOP 543 +/*! EGR_SEQUENCE_PROFILE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_PROFILE_INDEX_DOP 544 +/*! EPOST_EPOST_DROP_TRACE_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPOST_EPOST_DROP_TRACE_DOP 545 +/*! EPRE_EDEV_CONFIG_CPU_DMA_FLEX_WORD_MUX_PROFILE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_CPU_DMA_FLEX_WORD_MUX_PROFILE_INDEX_DOP 546 +/*! EPRE_PARSER_ZONE_REMAP_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP 547 +/*! FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP 548 +/*! FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP 549 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_8_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_8_DOP 550 +/*! FLEX_CTR_EGR_COUNTER_EOP_BUFFER_9_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_9_DOP 551 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_12_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_12_DOP 552 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_13_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_13_DOP 553 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_14_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_14_DOP 554 +/*! FLEX_CTR_ING_COUNTER_EOP_BUFFER_15_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_15_DOP 555 +/*! IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP 556 +/*! IFTA105_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA105_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP 557 +/*! IFTA130_I1T_04_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA130_I1T_04_INDEX_DOP 558 +/*! IFTA70_I1T_02_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IFTA70_I1T_02_INDEX_DOP 559 +/*! IPOST_LAG_L2OIF_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_LAG_L2OIF_INDEX_DOP 560 +/*! IPOST_LAG_LAG_GROUP_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_LAG_LAG_GROUP_INDEX_DOP 561 +/*! IPOST_LAG_LAG_MEMBER_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_LAG_LAG_MEMBER_INDEX_DOP 562 +/*! IPOST_LAG_NONUCAST_LAG_BLOCK_MASK_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_LAG_NONUCAST_LAG_BLOCK_MASK_INDEX_DOP 563 +/*! IPOST_LAG_SYSTEM_LAG_GROUP_ID_BMAP_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_LAG_SYSTEM_LAG_GROUP_ID_BMAP_DOP 564 +/*! IPOST_LAG_SYSTEM_LAG_MEMBER_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_LAG_SYSTEM_LAG_MEMBER_INDEX_DOP 565 +/*! IPOST_LAG_SYSTEM_PORT_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_LAG_SYSTEM_PORT_INDEX_DOP 566 +/*! IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_CHECK_BITMAP_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_CHECK_BITMAP_INDEX_DOP 567 +/*! IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_LOWER_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_LOWER_INDEX_DOP 568 +/*! IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_UPPER_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_UPPER_INDEX_DOP 569 +/*! IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP 570 +/*! IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP 571 +/*! IPOST_M_MPB_CCBI_FIXED_CCBI_B_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_M_MPB_CCBI_FIXED_CCBI_B_BUS_DOP 572 +/*! IPOST_M_MPB_CCBI_FIXED_CCBI_MC_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_M_MPB_CCBI_FIXED_CCBI_MC_BUS_DOP 573 +/*! IPOST_M_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_M_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP 574 +/*! IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP 575 +/*! IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP 576 +/*! IPOST_M_MPB_ENCODE_MPB_FLEX_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_M_MPB_ENCODE_MPB_FLEX_BUS_DOP 577 +/*! IPOST_TRACE_DROP_EVENT_ING_DROP_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_TRACE_DROP_EVENT_ING_DROP_BUS_DOP 578 +/*! IPOST_TRACE_DROP_EVENT_ING_TRACE_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_TRACE_DROP_EVENT_ING_TRACE_BUS_DOP 579 +/*! MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP 580 +/*! MEMDB_IFTA105_MEM0_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA105_MEM0_0_KEY_DOP 581 +/*! MEMDB_IFTA105_MEM0_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA105_MEM0_1_KEY_DOP 582 +/*! MEMDB_IFTA105_MEM0_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA105_MEM0_2_KEY_DOP 583 +/*! MEMDB_IFTA105_MEM0_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA105_MEM0_3_KEY_DOP 584 +/*! MEMDB_IFTA105_MEM0_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_IFTA105_MEM0_INDEX_DOP 585 +/*! MINTERM_AGG_MINTERM_AGG2EDIT_CTRL_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MINTERM_AGG_MINTERM_AGG2EDIT_CTRL_BUS_DOP 586 +/*! RANGE_MAP_PROFILE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_RANGE_MAP_PROFILE_INDEX_DOP 587 +/*! SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP 588 +/*! SIMPLE_MATCH_TABLE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SIMPLE_MATCH_TABLE_INDEX_DOP 589 +/*! SIMPLE_MATCH_TABLE_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SIMPLE_MATCH_TABLE_KEY_DOP 590 +/*! IPOST_CPU_COS_MAP_TCAM_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_CPU_COS_MAP_TCAM_INDEX_DOP 591 +/*! IPOST_CPU_COS_MAP_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPOST_CPU_COS_MAP_TCAM_KEY_DOP 592 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_0_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_0_DOP 593 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_PROFILE_PTR_0_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_PROFILE_PTR_0_DOP 594 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_0_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_0_DOP 595 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_2_DOP 596 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_0_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_0_DOP 597 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_0_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_0_DOP 598 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_3_DOP 599 +/*! HDR_STACK_LITE_DEBUG_CAPTURE_DATA_DOP. */ +#define BCMPKT_TRACE_DOP_ID_HDR_STACK_LITE_DEBUG_CAPTURE_DATA_DOP 600 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_3_DOP 601 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_1_DOP 602 +/*! VCA_IF_REQUEST_VCA_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_VCA_IF_REQUEST_VCA_KEY_DOP 603 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_2_DOP 604 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_1_DOP 605 +/*! VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP 606 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_3_DOP 607 +/*! VCA_IF_RESPONSE_VCA_DATA_DOP. */ +#define BCMPKT_TRACE_DOP_ID_VCA_IF_RESPONSE_VCA_DATA_DOP 608 +/*! EGR_MIRROR_SEQUENCE_NUMBER_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EGR_MIRROR_SEQUENCE_NUMBER_INDEX_DOP 609 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_2_DOP 610 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_0_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_0_DOP 611 +/*! IDEV_CONFIG_DEBUG_CAPTURE_DATA_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IDEV_CONFIG_DEBUG_CAPTURE_DATA_DOP 612 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_2_DOP 613 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_1_DOP 614 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_1_DOP 615 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_2_DOP 616 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_1_DOP 617 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_3_DOP 618 +/*! EDIT_CTRL_EDIT_CTRL2EDITOR_TRUNCATE_PROFILE_PTR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_TRUNCATE_PROFILE_PTR_DOP 619 +/*! C7_DOP. */ +#define BCMPKT_TRACE_DOP_ID_C7_DOP 620 +/*! EFPMOD_MISC_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFPMOD_MISC_DOP 621 +/*! EFPPARS_EFP_RANGE_CHECK_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_EFPPARS_EFP_RANGE_CHECK_DOPS 622 +/*! EFP_KEY_LOOKUP_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFP_KEY_LOOKUP_DOP 623 +/*! EFP_VIRTUAL_SLICE_LOOKUP_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EFP_VIRTUAL_SLICE_LOOKUP_DOP 624 +/*! EPARS_GROUP_4_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_EPARS_GROUP_4_DOPS 625 +/*! EPARS_GROUP_9_1_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_EPARS_GROUP_9_1_DOPS 626 +/*! EPARS_GROUP_9_2_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_EPARS_GROUP_9_2_DOPS 627 +/*! EPARS_GROUP_EGR_ADAPT_1_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_EPARS_GROUP_EGR_ADAPT_1_DOPS 628 +/*! EPARS_GROUP_EGR_ADAPT_2_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_EPARS_GROUP_EGR_ADAPT_2_DOPS 629 +/*! EPMOD_MISC_DOP. */ +#define BCMPKT_TRACE_DOP_ID_EPMOD_MISC_DOP 630 +/*! ESW_GROUP_1_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_ESW_GROUP_1_DOPS 631 +/*! FP_GROUP2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FP_GROUP2_DOP 632 +/*! FP_GROUP8_DOP. */ +#define BCMPKT_TRACE_DOP_ID_FP_GROUP8_DOP 633 +/*! IFWD1_GROUP_A_1_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_A_1_DOPS 634 +/*! IFWD1_GROUP_A_2_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_A_2_DOPS 635 +/*! IFWD1_GROUP_B_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_B_DOPS 636 +/*! IFWD1_GROUP_C_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_C_DOPS 637 +/*! IFWD1_GROUP_D_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_D_DOPS 638 +/*! IFWD1_GROUP_E_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_E_DOPS 639 +/*! IFWD1_GROUP_G_1_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_G_1_DOPS 640 +/*! IFWD1_GROUP_G_2_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_G_2_DOPS 641 +/*! IFWD1_GROUP_G_3_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_G_3_DOPS 642 +/*! IFWD1_GROUP_G_4_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_G_4_DOPS 643 +/*! IFWD1_GROUP_G_5_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_G_5_DOPS 644 +/*! IFWD1_GROUP_G_6_DOPS. */ +#define BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_G_6_DOPS 645 +/*! IPARS_HASH_TABLE_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARS_HASH_TABLE_DOP 646 +/*! IPARS_L3_TUNNEL_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARS_L3_TUNNEL_TCAM_DOP 647 +/*! IPARS_MISC_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARS_MISC_DOP 648 +/*! IPARS_MY_PREFIX_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARS_MY_PREFIX_TCAM_DOP 649 +/*! IPARS_UDF_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_IPARS_UDF_TCAM_DOP 650 +/*! MISC_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MISC_DOP 651 +/*! MY_STATION_2_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MY_STATION_2_TCAM_DOP 652 +/*! MY_STATION_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MY_STATION_TCAM_DOP 653 +/*! RSEL_GROUP1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_RSEL_GROUP1_DOP 654 +/*! RSEL_GROUP2_1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_RSEL_GROUP2_1_DOP 655 +/*! RSEL_GROUP2_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_RSEL_GROUP2_2_DOP 656 +/*! RSEL_GROUP2_3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_RSEL_GROUP2_3_DOP 657 +/*! RSEL_GROUP3_1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_RSEL_GROUP3_1_DOP 658 +/*! RSEL_GROUP3_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_RSEL_GROUP3_2_DOP 659 +/*! RSEL_GROUP3_3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_RSEL_GROUP3_3_DOP 660 +/*! RSEL_GROUP3_4_DOP. */ +#define BCMPKT_TRACE_DOP_ID_RSEL_GROUP3_4_DOP 661 +/*! RSEL_GROUP3_5_DOP. */ +#define BCMPKT_TRACE_DOP_ID_RSEL_GROUP3_5_DOP 662 +/*! SW_GROUP1_1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP1_1_DOP 663 +/*! SW_GROUP1_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP1_2_DOP 664 +/*! SW_GROUP1_3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP1_3_DOP 665 +/*! SW_GROUP1_4_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP1_4_DOP 666 +/*! SW_GROUP1_5_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP1_5_DOP 667 +/*! SW_GROUP1_6_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP1_6_DOP 668 +/*! SW_GROUP1_7_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP1_7_DOP 669 +/*! SW_GROUP2_1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP2_1_DOP 670 +/*! SW_GROUP2_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP2_2_DOP 671 +/*! SW_GROUP2_3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP2_3_DOP 672 +/*! SW_GROUP2_4_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP2_4_DOP 673 +/*! SW_GROUP3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP3_DOP 674 +/*! SW_GROUP4_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP4_DOP 675 +/*! SW_GROUP5_1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP5_1_DOP 676 +/*! SW_GROUP5_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP5_2_DOP 677 +/*! SW_GROUP5_3_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP5_3_DOP 678 +/*! SW_GROUP6_1_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP6_1_DOP 679 +/*! SW_GROUP6_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_SW_GROUP6_2_DOP 680 +/*! UDF_COND_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_UDF_COND_TCAM_DOP 681 +/*! VFP_TCAM_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_VFP_TCAM_KEY_DOP 682 +/*! VFP_TCAM_RESULT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_VFP_TCAM_RESULT_DOP 683 +/*! LPP_IPARS_MATCH_ID_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IPARS_MATCH_ID_DOP 684 +/*! MEMDB_TCAM_LPP_IFP_MEM0_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_LPP_IFP_MEM0_0_KEY_DOP 685 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP 686 +/*! LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP 687 +/*! LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP 688 +/*! LPP_IPARS_LPP_IPAD_BUS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IPARS_LPP_IPAD_BUS_DOP 689 +/*! LPP_IFWD_ALPM_LPM_KEY_GEN_CONTROLS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_LPM_KEY_GEN_CONTROLS_DOP 690 +/*! MEMDB_TCAM_LPP_IFP_MEM0_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_LPP_IFP_MEM0_2_KEY_DOP 691 +/*! LPP_IRSEL_AR_AR_INFO_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IRSEL_AR_AR_INFO_DOP 692 +/*! LPP_EPMOD_EGR_COUNTERS_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_EPMOD_EGR_COUNTERS_DOP 693 +/*! LPP_IPARS_FINAL_VRF_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IPARS_FINAL_VRF_DOP 694 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP 695 +/*! LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY_DOP 696 +/*! LPP_ISW_SW_COPY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_ISW_SW_COPY_DOP 697 +/*! MEMDB_TCAM_LPP_IFP_MEM0_3_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_LPP_IFP_MEM0_3_KEY_DOP 698 +/*! LPP_IFWD_ALPM_FXT_HASH_OUT_GEN_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_FXT_HASH_OUT_GEN_DOP 699 +/*! LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_INDEX_DOP 700 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP 701 +/*! LPP_EPARS_EPARS_MATCH_ID_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_EPARS_EPARS_MATCH_ID_DOP 702 +/*! LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP 703 +/*! LPP_ISW_NONSW_COPY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_ISW_NONSW_COPY_DOP 704 +/*! MEMDB_TCAM_LPP_IFP_MEM0_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_LPP_IFP_MEM0_1_KEY_DOP 705 +/*! LPP_ISW_IFA_MIRROR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_ISW_IFA_MIRROR_DOP 706 +/*! LPP_EPARS_EGR_PP_PORT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_EPARS_EGR_PP_PORT_DOP 707 +/*! LPP_IRSEL_RSEL_DR_PORT_INFO_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IRSEL_RSEL_DR_PORT_INFO_DOP 708 +/*! LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP 709 +/*! LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP 710 +/*! LPP_ISW_NEXT_HOP_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_ISW_NEXT_HOP_DOP 711 +/*! LPP_IRSEL_RSEL_EGRESS_PORT_INFO_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IRSEL_RSEL_EGRESS_PORT_INFO_DOP 712 +/*! LPP_ISW_MISC_2_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_ISW_MISC_2_DOP 713 +/*! LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP 714 +/*! LPP_ISW_ING_COUNTER_INCR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_ISW_ING_COUNTER_INCR_DOP 715 +/*! LPP_IPARS_MY_STATION_HIT_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IPARS_MY_STATION_HIT_DOP 716 +/*! LPP_IFWD_ALPM_LEVEL2_HIT_INFO_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_LEVEL2_HIT_INFO_DOP 717 +/*! LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP 718 +/*! MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP 719 +/*! LPP_EPARS_EPARS_INCA_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_EPARS_EPARS_INCA_DOP 720 +/*! LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY_DOP 721 +/*! LPP_IRSEL_RSEL_DEST_INFO_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IRSEL_RSEL_DEST_INFO_DOP 722 +/*! LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP 723 +/*! LPP_EPMOD_EGR_EVENT_VECTOR_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_EPMOD_EGR_EVENT_VECTOR_DOP 724 +/*! LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP 725 +/*! LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP 726 +/*! LPP_ISW_MISC_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_ISW_MISC_DOP 727 +/*! LPP_ISW_PROTOCOL_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_ISW_PROTOCOL_TCAM_DOP 728 +/*! LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP 729 +/*! LPP_IPARS_IPARS_MAPPED_DSCP_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IPARS_IPARS_MAPPED_DSCP_DOP 730 +/*! LPP_EPMOD_EDIT_ACTION_DOP_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_EPMOD_EDIT_ACTION_DOP_DOP 731 +/*! LPP_IPARS_UDF_TCAM_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IPARS_UDF_TCAM_DOP 732 +/*! LPP_IRSEL_RSEL_METER_INFO_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IRSEL_RSEL_METER_INFO_DOP 733 +/*! LPP_EPARS_EPARS_TS_1588_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_EPARS_EPARS_TS_1588_DOP 734 +/*! LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_INDEX_DOP. */ +#define BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_INDEX_DOP 735 +/*! TRACE_DOP_ID FIELD ID NUMBER */ +#define BCMPKT_TRACE_DOP_ID_COUNT 736 +/*! \} */ + +/*! TRACE_DOP_ID name strings for debugging. */ +#define BCMPKT_TRACE_DOP_ID_NAME_MAP_INIT \ + {"IPARSER0_HME_STAGE0_DOP", BCMPKT_TRACE_DOP_ID_IPARSER0_HME_STAGE0_DOP},\ + {"MEMDB_IFTA10_MY_DOP_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA10_MY_DOP_INDEX_DOP},\ + {"IFTA10_I1T_00_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA10_I1T_00_INDEX_DOP},\ + {"MEMDB_IFTA20_MY_DOP_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA20_MY_DOP_INDEX_DOP},\ + {"IFTA20_I1T_00_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA20_I1T_00_INDEX_DOP},\ + {"IPARSER1_HME_STAGE0_DOP", BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE0_DOP},\ + {"IPARSER1_HME_STAGE1_DOP", BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE1_DOP},\ + {"IPARSER1_HME_STAGE2_DOP", BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE2_DOP},\ + {"IPARSER1_HME_STAGE3_DOP", BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE3_DOP},\ + {"IPARSER1_HME_STAGE4_DOP", BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE4_DOP},\ + {"IPARSER1_HME_STAGE5_DOP", BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE5_DOP},\ + {"IFTA30_E2T_00_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA30_E2T_00_LTS_TCAM_1_KEY_DOP},\ + {"IFTA30_E2T_00_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA30_E2T_00_LTS_TCAM_0_KEY_DOP},\ + {"IFTA30_E2T_00_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA30_E2T_00_LTS_TCAM_INDEX_DOP},\ + {"IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA30_E2T_00_LTS_HIT_CONTEXT_DOP},\ + {"IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA30_T4T_00_LTS_HIT_CONTEXT_DOP},\ + {"IFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"MEMDB_TCAM_IFTA30_MEM0_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA30_MEM0_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA30_MEM0_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA30_MEM0_3_KEY_DOP},\ + {"MEMDB_TCAM_IFTA30_MEM0_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA30_MEM0_2_KEY_DOP},\ + {"MEMDB_TCAM_IFTA30_MEM0_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA30_MEM0_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA30_MEM0_INDEX_DOP},\ + {"IPARSER2_HME_STAGE0_DOP", BCMPKT_TRACE_DOP_ID_IPARSER2_HME_STAGE0_DOP},\ + {"IPARSER2_HME_STAGE1_DOP", BCMPKT_TRACE_DOP_ID_IPARSER2_HME_STAGE1_DOP},\ + {"IPARSER2_HME_STAGE2_DOP", BCMPKT_TRACE_DOP_ID_IPARSER2_HME_STAGE2_DOP},\ + {"IPARSER2_HME_STAGE3_DOP", BCMPKT_TRACE_DOP_ID_IPARSER2_HME_STAGE3_DOP},\ + {"IPARSER2_HME_STAGE4_DOP", BCMPKT_TRACE_DOP_ID_IPARSER2_HME_STAGE4_DOP},\ + {"IFTA40_E2T_01_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_E2T_01_LTS_TCAM_1_KEY_DOP},\ + {"IFTA40_E2T_01_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_E2T_01_LTS_TCAM_0_KEY_DOP},\ + {"IFTA40_E2T_01_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_E2T_01_LTS_TCAM_INDEX_DOP},\ + {"IFTA40_E2T_00_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_E2T_00_LTS_TCAM_1_KEY_DOP},\ + {"IFTA40_E2T_00_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_E2T_00_LTS_TCAM_0_KEY_DOP},\ + {"IFTA40_E2T_00_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_E2T_00_LTS_TCAM_INDEX_DOP},\ + {"IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_E2T_00_LTS_HIT_CONTEXT_DOP},\ + {"IFTA40_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_E2T_01_LTS_HIT_CONTEXT_DOP},\ + {"IFTA40_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_E2T_02_LTS_HIT_CONTEXT_DOP},\ + {"IFTA40_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA40_T4T_00_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_TCAM_1_KEY_DOP},\ + {"IFTA40_T4T_00_LTS_TCAM_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_TCAM_3_KEY_DOP},\ + {"IFTA40_T4T_00_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_TCAM_0_KEY_DOP},\ + {"IFTA40_T4T_00_LTS_TCAM_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_TCAM_2_KEY_DOP},\ + {"IFTA40_T4T_00_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_TCAM_INDEX_DOP},\ + {"IFTA40_T4T_01_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_TCAM_1_KEY_DOP},\ + {"IFTA40_T4T_01_LTS_TCAM_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_TCAM_3_KEY_DOP},\ + {"IFTA40_T4T_01_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_TCAM_0_KEY_DOP},\ + {"IFTA40_T4T_01_LTS_TCAM_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_TCAM_2_KEY_DOP},\ + {"IFTA40_T4T_01_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_TCAM_INDEX_DOP},\ + {"IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_HIT_CONTEXT_DOP},\ + {"IFTA40_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_HIT_CONTEXT_DOP},\ + {"IFTA40_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA40_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"MEMDB_TCAM_IFTA40_MEM0_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM0_3_KEY_DOP},\ + {"MEMDB_TCAM_IFTA40_MEM1_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM1_2_KEY_DOP},\ + {"MEMDB_TCAM_IFTA40_MEM0_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM0_2_KEY_DOP},\ + {"MEMDB_TCAM_IFTA40_MEM0_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM0_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA40_MEM1_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM1_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA40_MEM1_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM1_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA40_MEM0_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM0_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA40_MEM1_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM1_3_KEY_DOP},\ + {"MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM0_INDEX_DOP},\ + {"MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA40_MEM1_INDEX_DOP},\ + {"IFSL40_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFSL40_LTS_TCAM_KEY_DOP},\ + {"IFSL41_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFSL41_LTS_TCAM_KEY_DOP},\ + {"IFTA50_T4T_00_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA50_T4T_00_LTS_TCAM_1_KEY_DOP},\ + {"IFTA50_T4T_00_LTS_TCAM_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA50_T4T_00_LTS_TCAM_3_KEY_DOP},\ + {"IFTA50_T4T_00_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA50_T4T_00_LTS_TCAM_0_KEY_DOP},\ + {"IFTA50_T4T_00_LTS_TCAM_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA50_T4T_00_LTS_TCAM_2_KEY_DOP},\ + {"IFTA50_T4T_00_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA50_T4T_00_LTS_TCAM_INDEX_DOP},\ + {"IFTA50_I1T_00_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA50_I1T_00_INDEX_DOP},\ + {"IFTA50_I1T_01_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA50_I1T_01_INDEX_DOP},\ + {"MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_KEY_DOP},\ + {"MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_HIT_AND_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MPLS_CTRL_PKT_PROC_MPLS_CTRL_TCAM_HIT_AND_INDEX_DOP},\ + {"MEMDB_TCAM_IFTA50_MEM0_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA50_MEM0_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA50_MEM0_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA50_MEM0_3_KEY_DOP},\ + {"MEMDB_TCAM_IFTA50_MEM0_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA50_MEM0_2_KEY_DOP},\ + {"MEMDB_TCAM_IFTA50_MEM0_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA50_MEM0_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA50_MEM0_INDEX_DOP},\ + {"MEMDB_IFTA50_MY_DOP_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA50_MY_DOP_INDEX_DOP},\ + {"MEMDB_IFTA60_MY_DOP_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA60_MY_DOP_INDEX_DOP},\ + {"IFTA60_I1T_00_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA60_I1T_00_INDEX_DOP},\ + {"IFTA60_I1T_01_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA60_I1T_01_INDEX_DOP},\ + {"IFTA60_I1T_02_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA60_I1T_02_INDEX_DOP},\ + {"IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA60_T4T_00_LTS_HIT_CONTEXT_DOP},\ + {"IFTA60_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA60_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"MEMDB_TCAM_IFTA60_MEM0_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA60_MEM0_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA60_MEM0_3_KEY_DOP},\ + {"MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA60_MEM0_2_KEY_DOP},\ + {"MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA60_MEM0_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA60_MEM0_INDEX_DOP},\ + {"FLEX_DIGEST_LKUP_FD_NET_LAYER_KEY_DOP", BCMPKT_TRACE_DOP_ID_FLEX_DIGEST_LKUP_FD_NET_LAYER_KEY_DOP},\ + {"FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP", BCMPKT_TRACE_DOP_ID_FLEX_DIGEST_LKUP_FD_NET_LAYER_HIT_DOP},\ + {"FLEX_DIGEST_NORM_FD_NORM_DOP", BCMPKT_TRACE_DOP_ID_FLEX_DIGEST_NORM_FD_NORM_DOP},\ + {"FLEX_DIGEST_HASH_FD_HASH_DOP", BCMPKT_TRACE_DOP_ID_FLEX_DIGEST_HASH_FD_HASH_DOP},\ + {"MEMDB_IFTA70_MY_DOP_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA70_MY_DOP_INDEX_DOP},\ + {"IFTA70_I1T_00_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA70_I1T_00_INDEX_DOP},\ + {"IFTA70_I1T_01_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA70_I1T_01_INDEX_DOP},\ + {"IFSL70_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFSL70_LTS_TCAM_KEY_DOP},\ + {"IFTA80_E2T_01_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_01_LTS_TCAM_1_KEY_DOP},\ + {"IFTA80_E2T_01_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_01_LTS_TCAM_0_KEY_DOP},\ + {"IFTA80_E2T_01_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_01_LTS_TCAM_INDEX_DOP},\ + {"IFTA80_E2T_00_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_00_LTS_TCAM_1_KEY_DOP},\ + {"IFTA80_E2T_00_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_00_LTS_TCAM_0_KEY_DOP},\ + {"IFTA80_E2T_00_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_00_LTS_TCAM_INDEX_DOP},\ + {"IFTA80_E2T_03_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_03_LTS_TCAM_1_KEY_DOP},\ + {"IFTA80_E2T_03_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_03_LTS_TCAM_0_KEY_DOP},\ + {"IFTA80_E2T_03_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_03_LTS_TCAM_INDEX_DOP},\ + {"IFTA80_E2T_02_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_02_LTS_TCAM_1_KEY_DOP},\ + {"IFTA80_E2T_02_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_02_LTS_TCAM_0_KEY_DOP},\ + {"IFTA80_E2T_02_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_02_LTS_TCAM_INDEX_DOP},\ + {"IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_00_LTS_HIT_CONTEXT_DOP},\ + {"IFTA80_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_01_LTS_HIT_CONTEXT_DOP},\ + {"IFTA80_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_02_LTS_HIT_CONTEXT_DOP},\ + {"IFTA80_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_03_LTS_HIT_CONTEXT_DOP},\ + {"IFTA80_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA80_T2T_01_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_T2T_01_LTS_TCAM_1_KEY_DOP},\ + {"IFTA80_T2T_01_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_T2T_01_LTS_TCAM_0_KEY_DOP},\ + {"IFTA80_T2T_01_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_T2T_01_LTS_TCAM_INDEX_DOP},\ + {"IFTA80_T2T_00_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_T2T_00_LTS_TCAM_1_KEY_DOP},\ + {"IFTA80_T2T_00_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_T2T_00_LTS_TCAM_0_KEY_DOP},\ + {"IFTA80_T2T_00_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_T2T_00_LTS_TCAM_INDEX_DOP},\ + {"IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_T2T_00_LTS_HIT_CONTEXT_DOP},\ + {"IFTA80_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_T2T_01_LTS_HIT_CONTEXT_DOP},\ + {"IFTA80_T2T_01_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA80_T2T_01_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"FLEX_QOS_PHB_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_FLEX_QOS_PHB_LTS_TCAM_KEY_DOP},\ + {"FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_FLEX_QOS_PHB_LTS_TCAM_INDEX_DOP},\ + {"FLEX_QOS_PHB2_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_FLEX_QOS_PHB2_LTS_TCAM_KEY_DOP},\ + {"FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_FLEX_QOS_PHB2_LTS_TCAM_INDEX_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM2_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM2_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM1_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM1_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM7_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM7_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM6_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM6_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM5_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM5_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM2_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM2_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM5_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM5_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM0_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM0_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM6_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM6_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM1_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM1_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM4_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM4_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM3_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM3_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM0_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM0_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM4_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM4_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM7_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM7_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM3_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM3_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM6_INDEX_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM1_INDEX_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM4_INDEX_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM3_INDEX_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM7_INDEX_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM5_INDEX_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM0_INDEX_DOP},\ + {"MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA80_MEM2_INDEX_DOP},\ + {"IFTA90_E2T_03_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_03_LTS_TCAM_1_KEY_DOP},\ + {"IFTA90_E2T_03_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_03_LTS_TCAM_0_KEY_DOP},\ + {"IFTA90_E2T_03_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_03_LTS_TCAM_INDEX_DOP},\ + {"IFTA90_E2T_01_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_01_LTS_TCAM_1_KEY_DOP},\ + {"IFTA90_E2T_01_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_01_LTS_TCAM_0_KEY_DOP},\ + {"IFTA90_E2T_01_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_01_LTS_TCAM_INDEX_DOP},\ + {"IFTA90_E2T_00_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_00_LTS_TCAM_1_KEY_DOP},\ + {"IFTA90_E2T_00_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_00_LTS_TCAM_0_KEY_DOP},\ + {"IFTA90_E2T_00_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_00_LTS_TCAM_INDEX_DOP},\ + {"IFTA90_E2T_02_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_02_LTS_TCAM_1_KEY_DOP},\ + {"IFTA90_E2T_02_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_02_LTS_TCAM_0_KEY_DOP},\ + {"IFTA90_E2T_02_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_02_LTS_TCAM_INDEX_DOP},\ + {"IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_00_LTS_HIT_CONTEXT_DOP},\ + {"IFTA90_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_01_LTS_HIT_CONTEXT_DOP},\ + {"IFTA90_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_02_LTS_HIT_CONTEXT_DOP},\ + {"IFTA90_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_02_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_03_LTS_HIT_CONTEXT_DOP},\ + {"IFTA90_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA90_E2T_03_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"FLEX_CTR_ST_ING0_COUNTER_ACTION_VECTOR_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_ACTION_VECTOR_DOP},\ + {"FLEX_CTR_ST_ING0_COUNTER_POOL_1_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_POOL_1_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_ING0_COUNTER_POOL_2_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_POOL_2_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_ING0_COUNTER_POOL_3_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_POOL_3_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_ING0_COUNTER_POOL_0_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_POOL_0_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_ING0_COUNTER_B_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_B_DOP},\ + {"FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_TRIGGER_STATE_CTRL_DOP},\ + {"FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_TRUTH_TABLE_CMD_OUTPUT_DOP},\ + {"FLEX_CTR_ST_ING0_COUNTER_A_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING0_COUNTER_A_DOP},\ + {"IFSL90_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFSL90_LTS_TCAM_KEY_DOP},\ + {"IFSL91_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFSL91_LTS_TCAM_KEY_DOP},\ + {"IFTA100_T4T_00_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_TCAM_1_KEY_DOP},\ + {"IFTA100_T4T_00_LTS_TCAM_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_TCAM_3_KEY_DOP},\ + {"IFTA100_T4T_00_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_TCAM_0_KEY_DOP},\ + {"IFTA100_T4T_00_LTS_TCAM_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_TCAM_2_KEY_DOP},\ + {"IFTA100_T4T_00_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_TCAM_INDEX_DOP},\ + {"IFTA100_T4T_02_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_TCAM_1_KEY_DOP},\ + {"IFTA100_T4T_02_LTS_TCAM_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_TCAM_3_KEY_DOP},\ + {"IFTA100_T4T_02_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_TCAM_0_KEY_DOP},\ + {"IFTA100_T4T_02_LTS_TCAM_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_TCAM_2_KEY_DOP},\ + {"IFTA100_T4T_02_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_TCAM_INDEX_DOP},\ + {"IFTA100_T4T_01_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_TCAM_1_KEY_DOP},\ + {"IFTA100_T4T_01_LTS_TCAM_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_TCAM_3_KEY_DOP},\ + {"IFTA100_T4T_01_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_TCAM_0_KEY_DOP},\ + {"IFTA100_T4T_01_LTS_TCAM_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_TCAM_2_KEY_DOP},\ + {"IFTA100_T4T_01_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_TCAM_INDEX_DOP},\ + {"IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_HIT_CONTEXT_DOP},\ + {"IFTA100_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_HIT_CONTEXT_DOP},\ + {"IFTA100_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_01_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_HIT_CONTEXT_DOP},\ + {"IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_03_LTS_HIT_CONTEXT_DOP},\ + {"IFTA100_T4T_02_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_02_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA100_T4T_03_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA100_T4T_03_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"MEMDB_IFTA100_MEM1_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM1_2_KEY_DOP},\ + {"MEMDB_IFTA100_MEM0_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM0_2_KEY_DOP},\ + {"MEMDB_IFTA100_MEM7_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM7_2_KEY_DOP},\ + {"MEMDB_IFTA100_MEM8_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM8_2_KEY_DOP},\ + {"MEMDB_IFTA100_MEM9_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM9_0_KEY_DOP},\ + {"MEMDB_IFTA100_MEM11_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM11_3_KEY_DOP},\ + {"MEMDB_IFTA100_MEM7_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM7_3_KEY_DOP},\ + {"MEMDB_IFTA100_MEM8_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM8_0_KEY_DOP},\ + {"MEMDB_IFTA100_MEM10_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM10_2_KEY_DOP},\ + {"MEMDB_IFTA100_MEM5_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM5_0_KEY_DOP},\ + {"MEMDB_IFTA100_MEM3_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM3_2_KEY_DOP},\ + {"MEMDB_IFTA100_MEM8_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM8_3_KEY_DOP},\ + {"MEMDB_IFTA100_MEM11_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM11_0_KEY_DOP},\ + {"MEMDB_IFTA100_MEM2_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM2_1_KEY_DOP},\ + {"MEMDB_IFTA100_MEM4_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM4_3_KEY_DOP},\ + {"MEMDB_IFTA100_MEM4_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM4_2_KEY_DOP},\ + {"MEMDB_IFTA100_MEM5_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM5_3_KEY_DOP},\ + {"MEMDB_IFTA100_MEM10_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM10_1_KEY_DOP},\ + {"MEMDB_IFTA100_MEM6_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM6_1_KEY_DOP},\ + {"MEMDB_IFTA100_MEM10_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM10_3_KEY_DOP},\ + {"MEMDB_IFTA100_MEM4_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM4_1_KEY_DOP},\ + {"MEMDB_IFTA100_MEM9_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM9_2_KEY_DOP},\ + {"MEMDB_IFTA100_MEM3_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM3_0_KEY_DOP},\ + {"MEMDB_IFTA100_MEM2_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM2_0_KEY_DOP},\ + {"MEMDB_IFTA100_MEM1_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM1_0_KEY_DOP},\ + {"MEMDB_IFTA100_MEM11_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM11_1_KEY_DOP},\ + {"MEMDB_IFTA100_MEM2_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM2_2_KEY_DOP},\ + {"MEMDB_IFTA100_MEM8_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM8_1_KEY_DOP},\ + {"MEMDB_IFTA100_MEM7_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM7_1_KEY_DOP},\ + {"MEMDB_IFTA100_MEM9_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM9_3_KEY_DOP},\ + {"MEMDB_IFTA100_MEM6_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM6_0_KEY_DOP},\ + {"MEMDB_IFTA100_MEM6_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM6_2_KEY_DOP},\ + {"MEMDB_IFTA100_MEM9_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM9_1_KEY_DOP},\ + {"MEMDB_IFTA100_MEM5_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM5_1_KEY_DOP},\ + {"MEMDB_IFTA100_MEM0_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM0_3_KEY_DOP},\ + {"MEMDB_IFTA100_MEM3_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM3_3_KEY_DOP},\ + {"MEMDB_IFTA100_MEM0_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM0_0_KEY_DOP},\ + {"MEMDB_IFTA100_MEM1_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM1_1_KEY_DOP},\ + {"MEMDB_IFTA100_MEM4_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM4_0_KEY_DOP},\ + {"MEMDB_IFTA100_MEM3_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM3_1_KEY_DOP},\ + {"MEMDB_IFTA100_MEM2_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM2_3_KEY_DOP},\ + {"MEMDB_IFTA100_MEM10_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM10_0_KEY_DOP},\ + {"MEMDB_IFTA100_MEM6_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM6_3_KEY_DOP},\ + {"MEMDB_IFTA100_MEM0_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM0_1_KEY_DOP},\ + {"MEMDB_IFTA100_MEM5_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM5_2_KEY_DOP},\ + {"MEMDB_IFTA100_MEM7_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM7_0_KEY_DOP},\ + {"MEMDB_IFTA100_MEM1_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM1_3_KEY_DOP},\ + {"MEMDB_IFTA100_MEM11_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM11_2_KEY_DOP},\ + {"MEMDB_IFTA100_MEM9_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM9_INDEX_DOP},\ + {"MEMDB_IFTA100_MEM10_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM10_INDEX_DOP},\ + {"MEMDB_IFTA100_MEM7_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM7_INDEX_DOP},\ + {"MEMDB_IFTA100_MEM5_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM5_INDEX_DOP},\ + {"MEMDB_IFTA100_MEM8_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM8_INDEX_DOP},\ + {"MEMDB_IFTA100_MEM2_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM2_INDEX_DOP},\ + {"MEMDB_IFTA100_MEM11_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM11_INDEX_DOP},\ + {"MEMDB_IFTA100_MEM6_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM6_INDEX_DOP},\ + {"MEMDB_IFTA100_MEM1_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM1_INDEX_DOP},\ + {"MEMDB_IFTA100_MEM4_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM4_INDEX_DOP},\ + {"MEMDB_IFTA100_MEM3_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM3_INDEX_DOP},\ + {"MEMDB_IFTA100_MEM0_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA100_MEM0_INDEX_DOP},\ + {"IFSL100_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFSL100_LTS_TCAM_KEY_DOP},\ + {"ECMP_GROUP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_ECMP_GROUP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP},\ + {"ECMP_GROUP_LEVEL0_GROUP_TABLE_DATA_DOP", BCMPKT_TRACE_DOP_ID_ECMP_GROUP_LEVEL0_GROUP_TABLE_DATA_DOP},\ + {"ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP", BCMPKT_TRACE_DOP_ID_ECMP_GROUP_LEVEL0_MEMBER_INDEX_DOP},\ + {"MEMDB_IFTA110_MY_DOP_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA110_MY_DOP_INDEX_DOP},\ + {"ETRAP_ETR_HIT_RTAG_HASH_DOP", BCMPKT_TRACE_DOP_ID_ETRAP_ETR_HIT_RTAG_HASH_DOP},\ + {"ETRAP_ETR_OUT_DOP", BCMPKT_TRACE_DOP_ID_ETRAP_ETR_OUT_DOP},\ + {"DLB_ECMP_DLB_ECMP_CURRENT_TIME_DOP", BCMPKT_TRACE_DOP_ID_DLB_ECMP_DLB_ECMP_CURRENT_TIME_DOP},\ + {"DLB_ECMP_DLB_ECMP_FLOWSET_INDEX_DOP", BCMPKT_TRACE_DOP_ID_DLB_ECMP_DLB_ECMP_FLOWSET_INDEX_DOP},\ + {"ECMP_GROUP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_ECMP_GROUP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP},\ + {"ECMP_GROUP_LEVEL1_GROUP_TABLE_DATA_DOP", BCMPKT_TRACE_DOP_ID_ECMP_GROUP_LEVEL1_GROUP_TABLE_DATA_DOP},\ + {"ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP", BCMPKT_TRACE_DOP_ID_ECMP_GROUP_LEVEL1_MEMBER_INDEX_DOP},\ + {"MEMDB_IFTA120_MY_DOP_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA120_MY_DOP_INDEX_DOP},\ + {"MEMDB_IFTA130_MY_DOP_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA130_MY_DOP_INDEX_DOP},\ + {"IFTA130_I1T_00_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA130_I1T_00_INDEX_DOP},\ + {"IFTA130_I1T_01_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA130_I1T_01_INDEX_DOP},\ + {"IFTA130_I1T_02_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA130_I1T_02_INDEX_DOP},\ + {"IFTA130_I1T_03_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA130_I1T_03_INDEX_DOP},\ + {"MEMDB_IFTA140_MY_DOP_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA140_MY_DOP_INDEX_DOP},\ + {"IFTA140_I1T_00_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA140_I1T_00_INDEX_DOP},\ + {"IFTA140_I1T_01_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA140_I1T_01_INDEX_DOP},\ + {"FLEX_CTR_ST_ING1_COUNTER_ACTION_VECTOR_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_ACTION_VECTOR_DOP},\ + {"FLEX_CTR_ST_ING1_COUNTER_POOL_1_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_POOL_1_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_ING1_COUNTER_POOL_2_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_POOL_2_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_ING1_COUNTER_POOL_3_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_POOL_3_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_ING1_COUNTER_POOL_0_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_POOL_0_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_ING1_COUNTER_B_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_B_DOP},\ + {"FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_TRIGGER_STATE_CTRL_DOP},\ + {"FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_TRUTH_TABLE_CMD_OUTPUT_DOP},\ + {"FLEX_CTR_ST_ING1_COUNTER_A_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_ING1_COUNTER_A_DOP},\ + {"IFTA150_T4T_00_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_TCAM_1_KEY_DOP},\ + {"IFTA150_T4T_00_LTS_TCAM_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_TCAM_3_KEY_DOP},\ + {"IFTA150_T4T_00_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_TCAM_0_KEY_DOP},\ + {"IFTA150_T4T_00_LTS_TCAM_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_TCAM_2_KEY_DOP},\ + {"IFTA150_T4T_00_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_TCAM_INDEX_DOP},\ + {"IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_HIT_CONTEXT_DOP},\ + {"IFTA150_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA150_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"MEMDB_IFTA150_MEM0_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA150_MEM0_1_KEY_DOP},\ + {"MEMDB_IFTA150_MEM0_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA150_MEM0_3_KEY_DOP},\ + {"MEMDB_IFTA150_MEM0_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA150_MEM0_2_KEY_DOP},\ + {"MEMDB_IFTA150_MEM0_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA150_MEM0_0_KEY_DOP},\ + {"MEMDB_IFTA150_MEM0_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA150_MEM0_INDEX_DOP},\ + {"IPOST_DLB_LAG_DLB_LAG_CURRENT_TIME_DOP", BCMPKT_TRACE_DOP_ID_IPOST_DLB_LAG_DLB_LAG_CURRENT_TIME_DOP},\ + {"IPOST_DLB_LAG_DLB_LAG_FLOWSET_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_DLB_LAG_DLB_LAG_FLOWSET_INDEX_DOP},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP", BCMPKT_TRACE_DOP_ID_IPOST_MIRROR_SAMPLER_MIRROR_BUS_DOP},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP", BCMPKT_TRACE_DOP_ID_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_PRE_DOP},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP", BCMPKT_TRACE_DOP_ID_IPOST_MIRROR_SAMPLER_MIRROR_RESOLUTION_POST_DOP},\ + {"IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_KEY_DOP},\ + {"IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_QUEUE_ASSIGNMENT_LTS_TCAM_INDEX_DOP},\ + {"IPOST_CPU_COS_CPU_COS_MAP_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_IPOST_CPU_COS_CPU_COS_MAP_TCAM_KEY_DOP},\ + {"IPOST_CPU_COS_CPU_COS_MAP_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_CPU_COS_CPU_COS_MAP_TCAM_INDEX_DOP},\ + {"IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP},\ + {"IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP},\ + {"IPOST_MPB_ENCODE_MPB_FLEX_BUS_DOP", BCMPKT_TRACE_DOP_ID_IPOST_MPB_ENCODE_MPB_FLEX_BUS_DOP},\ + {"IPOST_MPB_CCBI_FIXED_CCBI_B_BUS_DOP", BCMPKT_TRACE_DOP_ID_IPOST_MPB_CCBI_FIXED_CCBI_B_BUS_DOP},\ + {"IPOST_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP", BCMPKT_TRACE_DOP_ID_IPOST_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP},\ + {"FLEX_CTR_ING_COUNTER_ACTION_VECTOR_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_ACTION_VECTOR_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_2_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_2_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_11_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_11_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_8_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_8_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_7_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_7_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_5_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_5_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_9_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_9_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_6_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_6_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_0_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_0_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_1_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_1_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_4_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_4_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_3_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_3_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_10_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_10_DOP},\ + {"IFSL140_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_IFSL140_LTS_TCAM_KEY_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_4_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_4_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_1_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_1_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_3_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_3_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_2_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_2_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_0_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_0_MATCH_ID_ATTRIBUTES_TABLE_INDEX_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_EGR_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_EGR_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER0_CTRL_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER0_CTRL_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER1_CTRL_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_EPRE2EPARSER1_CTRL_DOP},\ + {"EPRE_EDEV_CONFIG_EGR_INT_CN_UPDATE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_EGR_INT_CN_UPDATE_INDEX_DOP},\ + {"EPRE_EDEV_CONFIG_FORWARDING_TYPE_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_FORWARDING_TYPE_TABLE_INDEX_DOP},\ + {"EPRE_EDEV_CONFIG_MPB_FIXED_DOP", BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_MPB_FIXED_DOP},\ + {"EPRE_EDEV_CONFIG_CCBE_DOP", BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_CCBE_DOP},\ + {"EPRE_EDEV_CONFIG_EGR_TABLE_INDEX_UPDATE_PROFILE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_EGR_TABLE_INDEX_UPDATE_PROFILE_INDEX_DOP},\ + {"EPRE_EDEV_CONFIG_MIRROR_ATTRIBUTES_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_MIRROR_ATTRIBUTES_TABLE_INDEX_DOP},\ + {"EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_MPB_DECODE_MPB_FLEX_MPB_PDD_PROFILE_INDEX_DOP},\ + {"MEMDB_EFTA10_MY_DOP_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_EFTA10_MY_DOP_INDEX_DOP},\ + {"EFTA10_I1T_00_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA10_I1T_00_INDEX_DOP},\ + {"EFTA10_I1T_01_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA10_I1T_01_INDEX_DOP},\ + {"EFTA10_I1T_02_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA10_I1T_02_INDEX_DOP},\ + {"EFTA10_I1T_03_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA10_I1T_03_INDEX_DOP},\ + {"MEMDB_EFTA20_MY_DOP_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_EFTA20_MY_DOP_INDEX_DOP},\ + {"EFTA20_I1T_00_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA20_I1T_00_INDEX_DOP},\ + {"EFTA20_I1T_01_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA20_I1T_01_INDEX_DOP},\ + {"EFTA20_I1T_02_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA20_I1T_02_INDEX_DOP},\ + {"EFTA20_I1T_03_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA20_I1T_03_INDEX_DOP},\ + {"EFTA20_I1T_04_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA20_I1T_04_INDEX_DOP},\ + {"EFTA20_I1T_05_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA20_I1T_05_INDEX_DOP},\ + {"EFTA20_I1T_06_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA20_I1T_06_INDEX_DOP},\ + {"EFSL20_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EFSL20_LTS_TCAM_KEY_DOP},\ + {"EFTA30_E2T_00_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_E2T_00_LTS_TCAM_1_KEY_DOP},\ + {"EFTA30_E2T_00_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_E2T_00_LTS_TCAM_0_KEY_DOP},\ + {"EFTA30_E2T_00_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_E2T_00_LTS_TCAM_INDEX_DOP},\ + {"EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_E2T_00_LTS_HIT_CONTEXT_DOP},\ + {"EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_E2T_01_LTS_HIT_CONTEXT_DOP},\ + {"EFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_E2T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"EFTA30_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_E2T_01_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"EFTA30_T4T_00_LTS_TCAM_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_TCAM_1_KEY_DOP},\ + {"EFTA30_T4T_00_LTS_TCAM_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_TCAM_3_KEY_DOP},\ + {"EFTA30_T4T_00_LTS_TCAM_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_TCAM_0_KEY_DOP},\ + {"EFTA30_T4T_00_LTS_TCAM_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_TCAM_2_KEY_DOP},\ + {"EFTA30_T4T_00_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_TCAM_INDEX_DOP},\ + {"EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_HIT_CONTEXT_DOP},\ + {"EFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_EFTA30_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP", BCMPKT_TRACE_DOP_ID_EGR_TIMESTAMP_TIMESTAMP_COUNT_DOP},\ + {"EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP", BCMPKT_TRACE_DOP_ID_EGR_MEMBERSHIP_MEMBERSHIP_PTR_DOP},\ + {"FLEX_CTR_ST_EGR_COUNTER_ACTION_VECTOR_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_ACTION_VECTOR_DOP},\ + {"FLEX_CTR_ST_EGR_COUNTER_POOL_1_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_POOL_1_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_EGR_COUNTER_POOL_2_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_POOL_2_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_EGR_COUNTER_POOL_3_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_POOL_3_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_EGR_COUNTER_POOL_0_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_POOL_0_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_EGR_COUNTER_B_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_B_DOP},\ + {"FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_TRIGGER_STATE_CTRL_DOP},\ + {"FLEX_CTR_ST_EGR_COUNTER_A_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR_COUNTER_A_DOP},\ + {"FLEX_CTR_ST_EGR0_COUNTER_ACTION_VECTOR_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_ACTION_VECTOR_DOP},\ + {"FLEX_CTR_ST_EGR0_COUNTER_POOL_1_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_POOL_1_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_EGR0_COUNTER_POOL_2_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_POOL_2_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_EGR0_COUNTER_POOL_3_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_POOL_3_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_EGR0_COUNTER_POOL_0_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_POOL_0_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_EGR0_COUNTER_B_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_B_DOP},\ + {"FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_TRIGGER_STATE_CTRL_DOP},\ + {"FLEX_CTR_ST_EGR0_COUNTER_A_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_COUNTER_A_DOP},\ + {"FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR0_TRUTH_TABLE_CMD_OUTPUT_DOP},\ + {"FLEX_CTR_ST_EGR1_COUNTER_ACTION_VECTOR_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_ACTION_VECTOR_DOP},\ + {"FLEX_CTR_ST_EGR1_COUNTER_POOL_1_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_POOL_1_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_EGR1_COUNTER_POOL_2_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_POOL_2_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_EGR1_COUNTER_POOL_3_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_POOL_3_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_EGR1_COUNTER_POOL_0_UPDATE_CMD_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_POOL_0_UPDATE_CMD_DOP},\ + {"FLEX_CTR_ST_EGR1_COUNTER_B_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_B_DOP},\ + {"FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_TRIGGER_STATE_CTRL_DOP},\ + {"FLEX_CTR_ST_EGR1_COUNTER_A_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_COUNTER_A_DOP},\ + {"FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ST_EGR1_TRUTH_TABLE_CMD_OUTPUT_DOP},\ + {"MEMDB_TCAM_EFTA30_MEM0_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_EFTA30_MEM0_1_KEY_DOP},\ + {"MEMDB_TCAM_EFTA30_MEM0_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_EFTA30_MEM0_3_KEY_DOP},\ + {"MEMDB_TCAM_EFTA30_MEM0_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_EFTA30_MEM0_2_KEY_DOP},\ + {"MEMDB_TCAM_EFTA30_MEM0_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_EFTA30_MEM0_0_KEY_DOP},\ + {"MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_EFTA30_MEM0_INDEX_DOP},\ + {"EFSL30_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EFSL30_LTS_TCAM_KEY_DOP},\ + {"EGR_MIRROR_MIRROR2EDIT_CTRL_BUS_DOP", BCMPKT_TRACE_DOP_ID_EGR_MIRROR_MIRROR2EDIT_CTRL_BUS_DOP},\ + {"QOS_REMARKING_LTS_TCAM_ONLY_KEY_DOP", BCMPKT_TRACE_DOP_ID_QOS_REMARKING_LTS_TCAM_ONLY_KEY_DOP},\ + {"QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP", BCMPKT_TRACE_DOP_ID_QOS_REMARKING_LTS_TCAM_HIT_AND_INDEX_DOP},\ + {"QOS_REMARKING_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_QOS_REMARKING_LTS_TCAM_KEY_DOP},\ + {"QOS_REMARKING_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_QOS_REMARKING_LTS_TCAM_INDEX_DOP},\ + {"QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_QOS_REMARKING_QOS_MAP_TABLE_INDEX_DOP},\ + {"EDIT_CTRL_ZONE_4_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_4_TCAM_KEY_DOP},\ + {"EDIT_CTRL_ZONE_3_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_3_TCAM_KEY_DOP},\ + {"EDIT_CTRL_ZONE_1_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_1_TCAM_KEY_DOP},\ + {"EDIT_CTRL_ZONE_2_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_2_TCAM_KEY_DOP},\ + {"EDIT_CTRL_ZONE_0_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_0_TCAM_KEY_DOP},\ + {"EDIT_CTRL_ZONE_0_TCAM_HIT_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_0_TCAM_HIT_DOP},\ + {"EDIT_CTRL_ZONE_4_TCAM_HIT_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_4_TCAM_HIT_DOP},\ + {"EDIT_CTRL_ZONE_3_TCAM_HIT_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_3_TCAM_HIT_DOP},\ + {"EDIT_CTRL_ZONE_2_TCAM_HIT_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_2_TCAM_HIT_DOP},\ + {"EDIT_CTRL_ZONE_1_TCAM_HIT_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_1_TCAM_HIT_DOP},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_4_LTS_TCAM_KEY_DOP},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_3_LTS_TCAM_KEY_DOP},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_2_LTS_TCAM_KEY_DOP},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_1_LTS_TCAM_KEY_DOP},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_0_LTS_TCAM_KEY_DOP},\ + {"EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_0_LTS_TCAM_INDEX_DOP},\ + {"EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_1_LTS_TCAM_INDEX_DOP},\ + {"EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_2_LTS_TCAM_INDEX_DOP},\ + {"EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_3_LTS_TCAM_INDEX_DOP},\ + {"EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_4_LTS_TCAM_INDEX_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_2_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_2_PROFILE_PTR_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_2_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_2_PROFILE_PTR_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_RW_1_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_1_PROFILE_PTR_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_1_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_1_PROFILE_PTR_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_1_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_1_PROFILE_PTR_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_0_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_0_PROFILE_PTR_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_3_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_3_PROFILE_PTR_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_RW_0_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_0_PROFILE_PTR_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_0_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_0_PROFILE_PTR_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_0_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_0_PROFILE_PTR_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_0_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_0_PROFILE_PTR_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_2_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_2_PROFILE_PTR_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_1_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_1_PROFILE_PTR_DOP},\ + {"EGR_SEQUENCE_MIRROR_SEQUENCE_NUMBER_PROFILE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_MIRROR_SEQUENCE_NUMBER_PROFILE_INDEX_DOP},\ + {"EGR_SEQUENCE_SEQUENCE_NUMBER_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_SEQUENCE_NUMBER_TABLE_INDEX_DOP},\ + {"EGR_SEQUENCE_SEQUENCE_PROFILE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_SEQUENCE_PROFILE_INDEX_DOP},\ + {"EGR_SEQUENCE_NEW_SEQUENCE_NUM_DOP", BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_NEW_SEQUENCE_NUM_DOP},\ + {"EGR_SEQUENCE_PKT_SEQUENCE_NUM_DOP", BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_PKT_SEQUENCE_NUM_DOP},\ + {"FLEX_EDITOR_MATCH_ID_DOP", BCMPKT_TRACE_DOP_ID_FLEX_EDITOR_MATCH_ID_DOP},\ + {"FLEX_EDITOR_VHLEN_DOP", BCMPKT_TRACE_DOP_ID_FLEX_EDITOR_VHLEN_DOP},\ + {"FLEX_EDITOR_EDIT_ID_DOP", BCMPKT_TRACE_DOP_ID_FLEX_EDITOR_EDIT_ID_DOP},\ + {"FLEX_CTR_EGR_COUNTER_ACTION_VECTOR_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_ACTION_VECTOR_DOP},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_2_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_2_DOP},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_7_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_7_DOP},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_5_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_5_DOP},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_6_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_6_DOP},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_0_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_0_DOP},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_1_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_1_DOP},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_4_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_4_DOP},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_3_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_3_DOP},\ + {"APU_EGR0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP", BCMPKT_TRACE_DOP_ID_APU_EGR0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP},\ + {"APU_EGR1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP", BCMPKT_TRACE_DOP_ID_APU_EGR1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP},\ + {"APU_ING0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP", BCMPKT_TRACE_DOP_ID_APU_ING0_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP},\ + {"APU_ING1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP", BCMPKT_TRACE_DOP_ID_APU_ING1_APU_TCAM_KEY_HIT_VECTOR_POLICY_DOP},\ + {"ECMP_LEVEL0_GROUP_TABLE_DATA_DOP", BCMPKT_TRACE_DOP_ID_ECMP_LEVEL0_GROUP_TABLE_DATA_DOP},\ + {"ECMP_LEVEL0_MEMBER_INDEX_DOP", BCMPKT_TRACE_DOP_ID_ECMP_LEVEL0_MEMBER_INDEX_DOP},\ + {"ECMP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_ECMP_LEVEL0_SHUFFLE_TABLE_INDEX_DOP},\ + {"ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP", BCMPKT_TRACE_DOP_ID_ECMP_LEVEL1_ALT_PROTECTION_INDEX_DOP},\ + {"ECMP_LEVEL1_MEMBER_INDEX_DOP", BCMPKT_TRACE_DOP_ID_ECMP_LEVEL1_MEMBER_INDEX_DOP},\ + {"ECMP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_ECMP_LEVEL1_SHUFFLE_TABLE_INDEX_DOP},\ + {"EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_1_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP},\ + {"EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_2_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP},\ + {"EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_3_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP},\ + {"EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_ZONE_4_MHC_0_PROFILE_INDEX_MERGE_TCAM_KEY_DOP},\ + {"EFTA40_I1T_00_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA40_I1T_00_INDEX_DOP},\ + {"EFTA40_I1T_01_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA40_I1T_01_INDEX_DOP},\ + {"EFTA40_I1T_02_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA40_I1T_02_INDEX_DOP},\ + {"EFTA40_I1T_03_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA40_I1T_03_INDEX_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_0_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_1_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_2_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_3_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_ZONE_4_PARSE_ARC_ID_ATTRIBUTES_TABLE_INDEX_DOP},\ + {"FLEX_EDITOR_ARC_ID_DOP", BCMPKT_TRACE_DOP_ID_FLEX_EDITOR_ARC_ID_DOP},\ + {"HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_HDR_STACK_EGR_EDIT_BITMAP_MAP_TABLE_INDEX_DOP},\ + {"HDR_STACK_EGR_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_HDR_STACK_EGR_LTS_TCAM_INDEX_DOP},\ + {"HDR_STACK_EGR_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_HDR_STACK_EGR_LTS_TCAM_KEY_DOP},\ + {"HDR_STACK_ING_LTS_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_HDR_STACK_ING_LTS_TCAM_INDEX_DOP},\ + {"HDR_STACK_ING_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_HDR_STACK_ING_LTS_TCAM_KEY_DOP},\ + {"IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA5_T2T_00_LTS_HIT_CONTEXT_DOP},\ + {"IFTA5_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA5_T2T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IPARSER1_HME_STAGE6_DOP", BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE6_DOP},\ + {"IPARSER1_HME_STAGE7_DOP", BCMPKT_TRACE_DOP_ID_IPARSER1_HME_STAGE7_DOP},\ + {"IPARSER2_HME_STAGE5_DOP", BCMPKT_TRACE_DOP_ID_IPARSER2_HME_STAGE5_DOP},\ + {"MEMDB_TCAM_IFTA5_MEM0_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA5_MEM0_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA5_MEM0_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA5_MEM0_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA5_MEM0_INDEX_DOP},\ + {"MEMDB_TCAM_IFTA5_MEM1_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA5_MEM1_0_KEY_DOP},\ + {"MEMDB_TCAM_IFTA5_MEM1_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA5_MEM1_1_KEY_DOP},\ + {"MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_IFTA5_MEM1_INDEX_DOP},\ + {"APU_EGR0_APU_TCAM_HIT_VECTOR_DOP", BCMPKT_TRACE_DOP_ID_APU_EGR0_APU_TCAM_HIT_VECTOR_DOP},\ + {"APU_EGR0_APU_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_APU_EGR0_APU_TCAM_KEY_DOP},\ + {"APU_EGR0_APU_TCAM_POLICY_DOP", BCMPKT_TRACE_DOP_ID_APU_EGR0_APU_TCAM_POLICY_DOP},\ + {"APU_EGR0_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_APU_EGR0_LTS_TCAM_KEY_DOP},\ + {"APU_EGR1_APU_TCAM_HIT_VECTOR_DOP", BCMPKT_TRACE_DOP_ID_APU_EGR1_APU_TCAM_HIT_VECTOR_DOP},\ + {"APU_EGR1_APU_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_APU_EGR1_APU_TCAM_KEY_DOP},\ + {"APU_EGR1_APU_TCAM_POLICY_DOP", BCMPKT_TRACE_DOP_ID_APU_EGR1_APU_TCAM_POLICY_DOP},\ + {"APU_EGR1_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_APU_EGR1_LTS_TCAM_KEY_DOP},\ + {"APU_ING0_APU_TCAM_HIT_VECTOR_DOP", BCMPKT_TRACE_DOP_ID_APU_ING0_APU_TCAM_HIT_VECTOR_DOP},\ + {"APU_ING0_APU_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_APU_ING0_APU_TCAM_KEY_DOP},\ + {"APU_ING0_APU_TCAM_POLICY_DOP", BCMPKT_TRACE_DOP_ID_APU_ING0_APU_TCAM_POLICY_DOP},\ + {"APU_ING0_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_APU_ING0_LTS_TCAM_KEY_DOP},\ + {"APU_ING1_APU_TCAM_HIT_VECTOR_DOP", BCMPKT_TRACE_DOP_ID_APU_ING1_APU_TCAM_HIT_VECTOR_DOP},\ + {"APU_ING1_APU_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_APU_ING1_APU_TCAM_KEY_DOP},\ + {"APU_ING1_APU_TCAM_POLICY_DOP", BCMPKT_TRACE_DOP_ID_APU_ING1_APU_TCAM_POLICY_DOP},\ + {"APU_ING1_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_APU_ING1_LTS_TCAM_KEY_DOP},\ + {"ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_ECMP_LEVEL0_GROUP_SHUFFLE_INDEX_DOP},\ + {"ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP", BCMPKT_TRACE_DOP_ID_ECMP_LEVEL1_ALT_MEMBER_INDEX_DOP},\ + {"ECMP_LEVEL1_DLB_NHI_DOP", BCMPKT_TRACE_DOP_ID_ECMP_LEVEL1_DLB_NHI_DOP},\ + {"ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_ECMP_LEVEL1_GROUP_SHUFFLE_INDEX_DOP},\ + {"EFSL40_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EFSL40_LTS_TCAM_KEY_DOP},\ + {"EFSL41_LTS_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_EFSL41_LTS_TCAM_KEY_DOP},\ + {"EFTA10_I1T_04_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EFTA10_I1T_04_INDEX_DOP},\ + {"EGR_MIRROR_ENCAP_1_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EGR_MIRROR_ENCAP_1_TABLE_INDEX_DOP},\ + {"EGR_MIRROR_ENCAP_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EGR_MIRROR_ENCAP_TABLE_INDEX_DOP},\ + {"EGR_MIRROR_MIRROR2EDITOR2_BUS_DOP", BCMPKT_TRACE_DOP_ID_EGR_MIRROR_MIRROR2EDITOR2_BUS_DOP},\ + {"EGR_MIRROR_MIRROR2EDITOR_BUS_DOP", BCMPKT_TRACE_DOP_ID_EGR_MIRROR_MIRROR2EDITOR_BUS_DOP},\ + {"EGR_MIRROR_SESSION_CONTROL_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EGR_MIRROR_SESSION_CONTROL_TABLE_INDEX_DOP},\ + {"EGR_SEQUENCE_NUMBER_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_NUMBER_TABLE_INDEX_DOP},\ + {"EGR_SEQUENCE_PROFILE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EGR_SEQUENCE_PROFILE_INDEX_DOP},\ + {"EPOST_EPOST_DROP_TRACE_DOP", BCMPKT_TRACE_DOP_ID_EPOST_EPOST_DROP_TRACE_DOP},\ + {"EPRE_EDEV_CONFIG_CPU_DMA_FLEX_WORD_MUX_PROFILE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_EDEV_CONFIG_CPU_DMA_FLEX_WORD_MUX_PROFILE_INDEX_DOP},\ + {"EPRE_PARSER_ZONE_REMAP_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EPRE_PARSER_ZONE_REMAP_FIELD_EXTRACTION_PROFILE_CONTROL_INDEX_DOP},\ + {"FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_FIELD_COMPRESSION_ENGINE_EFP_L3_TYPE_TCAM_KEY_DOP},\ + {"FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_FIELD_COMPRESSION_ENGINE_IFP_L3_TYPE_TCAM_KEY_DOP},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_8_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_8_DOP},\ + {"FLEX_CTR_EGR_COUNTER_EOP_BUFFER_9_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_EGR_COUNTER_EOP_BUFFER_9_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_12_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_12_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_13_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_13_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_14_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_14_DOP},\ + {"FLEX_CTR_ING_COUNTER_EOP_BUFFER_15_DOP", BCMPKT_TRACE_DOP_ID_FLEX_CTR_ING_COUNTER_EOP_BUFFER_15_DOP},\ + {"IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP", BCMPKT_TRACE_DOP_ID_IFTA105_T4T_00_LTS_HIT_CONTEXT_DOP},\ + {"IFTA105_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP", BCMPKT_TRACE_DOP_ID_IFTA105_T4T_00_LTS_PRE_SEL_MUX_OUT_DOP},\ + {"IFTA130_I1T_04_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA130_I1T_04_INDEX_DOP},\ + {"IFTA70_I1T_02_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IFTA70_I1T_02_INDEX_DOP},\ + {"IPOST_LAG_L2OIF_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_LAG_L2OIF_INDEX_DOP},\ + {"IPOST_LAG_LAG_GROUP_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_LAG_LAG_GROUP_INDEX_DOP},\ + {"IPOST_LAG_LAG_MEMBER_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_LAG_LAG_MEMBER_INDEX_DOP},\ + {"IPOST_LAG_NONUCAST_LAG_BLOCK_MASK_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_LAG_NONUCAST_LAG_BLOCK_MASK_INDEX_DOP},\ + {"IPOST_LAG_SYSTEM_LAG_GROUP_ID_BMAP_DOP", BCMPKT_TRACE_DOP_ID_IPOST_LAG_SYSTEM_LAG_GROUP_ID_BMAP_DOP},\ + {"IPOST_LAG_SYSTEM_LAG_MEMBER_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_LAG_SYSTEM_LAG_MEMBER_INDEX_DOP},\ + {"IPOST_LAG_SYSTEM_PORT_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_LAG_SYSTEM_PORT_INDEX_DOP},\ + {"IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_CHECK_BITMAP_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_CHECK_BITMAP_INDEX_DOP},\ + {"IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_LOWER_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_LOWER_INDEX_DOP},\ + {"IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_UPPER_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_MEMBERSHIP_CHECK_BLOCK_MASK_MEMBERSHIP_STATE_UPPER_INDEX_DOP},\ + {"IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_MIRROR_SAMPLER_MIRROR_SESSION_INDEX_DOP},\ + {"IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_MIRROR_SAMPLER_SAMPLER_POOL_INDEX_DOP},\ + {"IPOST_M_MPB_CCBI_FIXED_CCBI_B_BUS_DOP", BCMPKT_TRACE_DOP_ID_IPOST_M_MPB_CCBI_FIXED_CCBI_B_BUS_DOP},\ + {"IPOST_M_MPB_CCBI_FIXED_CCBI_MC_BUS_DOP", BCMPKT_TRACE_DOP_ID_IPOST_M_MPB_CCBI_FIXED_CCBI_MC_BUS_DOP},\ + {"IPOST_M_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP", BCMPKT_TRACE_DOP_ID_IPOST_M_MPB_CCBI_FIXED_MPB_FIXED_BUS_DOP},\ + {"IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_INDEX_DOP},\ + {"IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_IPOST_M_MPB_ENCODE_ING_MPB_FLEX_DATA_SELECT_TCAM_KEY_DOP},\ + {"IPOST_M_MPB_ENCODE_MPB_FLEX_BUS_DOP", BCMPKT_TRACE_DOP_ID_IPOST_M_MPB_ENCODE_MPB_FLEX_BUS_DOP},\ + {"IPOST_TRACE_DROP_EVENT_ING_DROP_BUS_DOP", BCMPKT_TRACE_DOP_ID_IPOST_TRACE_DROP_EVENT_ING_DROP_BUS_DOP},\ + {"IPOST_TRACE_DROP_EVENT_ING_TRACE_BUS_DOP", BCMPKT_TRACE_DOP_ID_IPOST_TRACE_DROP_EVENT_ING_TRACE_BUS_DOP},\ + {"MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP", BCMPKT_TRACE_DOP_ID_MEMBERSHIP_CHECK_ING0_MEMBERSHIP_ING_PTR_DOP},\ + {"MEMDB_IFTA105_MEM0_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA105_MEM0_0_KEY_DOP},\ + {"MEMDB_IFTA105_MEM0_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA105_MEM0_1_KEY_DOP},\ + {"MEMDB_IFTA105_MEM0_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA105_MEM0_2_KEY_DOP},\ + {"MEMDB_IFTA105_MEM0_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA105_MEM0_3_KEY_DOP},\ + {"MEMDB_IFTA105_MEM0_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_IFTA105_MEM0_INDEX_DOP},\ + {"MINTERM_AGG_MINTERM_AGG2EDIT_CTRL_BUS_DOP", BCMPKT_TRACE_DOP_ID_MINTERM_AGG_MINTERM_AGG2EDIT_CTRL_BUS_DOP},\ + {"RANGE_MAP_PROFILE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_RANGE_MAP_PROFILE_INDEX_DOP},\ + {"SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP", BCMPKT_TRACE_DOP_ID_SIMPLE_MATCH_LTS_TCAM_ONLY_KEY_DOP},\ + {"SIMPLE_MATCH_TABLE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_SIMPLE_MATCH_TABLE_INDEX_DOP},\ + {"SIMPLE_MATCH_TABLE_KEY_DOP", BCMPKT_TRACE_DOP_ID_SIMPLE_MATCH_TABLE_KEY_DOP},\ + {"IPOST_CPU_COS_MAP_TCAM_INDEX_DOP", BCMPKT_TRACE_DOP_ID_IPOST_CPU_COS_MAP_TCAM_INDEX_DOP},\ + {"IPOST_CPU_COS_MAP_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_IPOST_CPU_COS_MAP_TCAM_KEY_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_0_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_0_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_PROFILE_PTR_0_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MIRROR_PROFILE_PTR_0_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_0_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_0_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_2_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_2_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_0_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_0_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_0_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_0_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_3_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_3_DOP},\ + {"HDR_STACK_LITE_DEBUG_CAPTURE_DATA_DOP", BCMPKT_TRACE_DOP_ID_HDR_STACK_LITE_DEBUG_CAPTURE_DATA_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_3_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_3_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_1_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_1_DOP},\ + {"VCA_IF_REQUEST_VCA_KEY_DOP", BCMPKT_TRACE_DOP_ID_VCA_IF_REQUEST_VCA_KEY_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_2_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_2_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_1_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_1_DOP},\ + {"VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP", BCMPKT_TRACE_DOP_ID_VCA_IF_REQUEST_VCA_PROFILE_INDEX_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_3_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_3_DOP},\ + {"VCA_IF_RESPONSE_VCA_DATA_DOP", BCMPKT_TRACE_DOP_ID_VCA_IF_RESPONSE_VCA_DATA_DOP},\ + {"EGR_MIRROR_SEQUENCE_NUMBER_INDEX_DOP", BCMPKT_TRACE_DOP_ID_EGR_MIRROR_SEQUENCE_NUMBER_INDEX_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_2_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_MHC_CHECKSUM_PROFILE_PTR_2_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_0_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_0_DOP},\ + {"IDEV_CONFIG_DEBUG_CAPTURE_DATA_DOP", BCMPKT_TRACE_DOP_ID_IDEV_CONFIG_DEBUG_CAPTURE_DATA_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_2_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_RW_PROFILE_PTR_2_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_1_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_SMALL_FLEX_HDR_PROFILE_PTR_1_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_1_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_1_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_2_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_HEADER_SUM_PROFILE_PTR_2_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_1_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_1_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_3_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_LARGE_FLEX_HDR_PROFILE_PTR_3_DOP},\ + {"EDIT_CTRL_EDIT_CTRL2EDITOR_TRUNCATE_PROFILE_PTR_DOP", BCMPKT_TRACE_DOP_ID_EDIT_CTRL_EDIT_CTRL2EDITOR_TRUNCATE_PROFILE_PTR_DOP},\ + {"C7_DOP", BCMPKT_TRACE_DOP_ID_C7_DOP},\ + {"EFPMOD_MISC_DOP", BCMPKT_TRACE_DOP_ID_EFPMOD_MISC_DOP},\ + {"EFPPARS_EFP_RANGE_CHECK_DOPS", BCMPKT_TRACE_DOP_ID_EFPPARS_EFP_RANGE_CHECK_DOPS},\ + {"EFP_KEY_LOOKUP_DOP", BCMPKT_TRACE_DOP_ID_EFP_KEY_LOOKUP_DOP},\ + {"EFP_VIRTUAL_SLICE_LOOKUP_DOP", BCMPKT_TRACE_DOP_ID_EFP_VIRTUAL_SLICE_LOOKUP_DOP},\ + {"EPARS_GROUP_4_DOPS", BCMPKT_TRACE_DOP_ID_EPARS_GROUP_4_DOPS},\ + {"EPARS_GROUP_9_1_DOPS", BCMPKT_TRACE_DOP_ID_EPARS_GROUP_9_1_DOPS},\ + {"EPARS_GROUP_9_2_DOPS", BCMPKT_TRACE_DOP_ID_EPARS_GROUP_9_2_DOPS},\ + {"EPARS_GROUP_EGR_ADAPT_1_DOPS", BCMPKT_TRACE_DOP_ID_EPARS_GROUP_EGR_ADAPT_1_DOPS},\ + {"EPARS_GROUP_EGR_ADAPT_2_DOPS", BCMPKT_TRACE_DOP_ID_EPARS_GROUP_EGR_ADAPT_2_DOPS},\ + {"EPMOD_MISC_DOP", BCMPKT_TRACE_DOP_ID_EPMOD_MISC_DOP},\ + {"ESW_GROUP_1_DOPS", BCMPKT_TRACE_DOP_ID_ESW_GROUP_1_DOPS},\ + {"FP_GROUP2_DOP", BCMPKT_TRACE_DOP_ID_FP_GROUP2_DOP},\ + {"FP_GROUP8_DOP", BCMPKT_TRACE_DOP_ID_FP_GROUP8_DOP},\ + {"IFWD1_GROUP_A_1_DOPS", BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_A_1_DOPS},\ + {"IFWD1_GROUP_A_2_DOPS", BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_A_2_DOPS},\ + {"IFWD1_GROUP_B_DOPS", BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_B_DOPS},\ + {"IFWD1_GROUP_C_DOPS", BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_C_DOPS},\ + {"IFWD1_GROUP_D_DOPS", BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_D_DOPS},\ + {"IFWD1_GROUP_E_DOPS", BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_E_DOPS},\ + {"IFWD1_GROUP_G_1_DOPS", BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_G_1_DOPS},\ + {"IFWD1_GROUP_G_2_DOPS", BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_G_2_DOPS},\ + {"IFWD1_GROUP_G_3_DOPS", BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_G_3_DOPS},\ + {"IFWD1_GROUP_G_4_DOPS", BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_G_4_DOPS},\ + {"IFWD1_GROUP_G_5_DOPS", BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_G_5_DOPS},\ + {"IFWD1_GROUP_G_6_DOPS", BCMPKT_TRACE_DOP_ID_IFWD1_GROUP_G_6_DOPS},\ + {"IPARS_HASH_TABLE_DOP", BCMPKT_TRACE_DOP_ID_IPARS_HASH_TABLE_DOP},\ + {"IPARS_L3_TUNNEL_TCAM_DOP", BCMPKT_TRACE_DOP_ID_IPARS_L3_TUNNEL_TCAM_DOP},\ + {"IPARS_MISC_DOP", BCMPKT_TRACE_DOP_ID_IPARS_MISC_DOP},\ + {"IPARS_MY_PREFIX_TCAM_DOP", BCMPKT_TRACE_DOP_ID_IPARS_MY_PREFIX_TCAM_DOP},\ + {"IPARS_UDF_TCAM_DOP", BCMPKT_TRACE_DOP_ID_IPARS_UDF_TCAM_DOP},\ + {"MISC_DOP", BCMPKT_TRACE_DOP_ID_MISC_DOP},\ + {"MY_STATION_2_TCAM_DOP", BCMPKT_TRACE_DOP_ID_MY_STATION_2_TCAM_DOP},\ + {"MY_STATION_TCAM_DOP", BCMPKT_TRACE_DOP_ID_MY_STATION_TCAM_DOP},\ + {"RSEL_GROUP1_DOP", BCMPKT_TRACE_DOP_ID_RSEL_GROUP1_DOP},\ + {"RSEL_GROUP2_1_DOP", BCMPKT_TRACE_DOP_ID_RSEL_GROUP2_1_DOP},\ + {"RSEL_GROUP2_2_DOP", BCMPKT_TRACE_DOP_ID_RSEL_GROUP2_2_DOP},\ + {"RSEL_GROUP2_3_DOP", BCMPKT_TRACE_DOP_ID_RSEL_GROUP2_3_DOP},\ + {"RSEL_GROUP3_1_DOP", BCMPKT_TRACE_DOP_ID_RSEL_GROUP3_1_DOP},\ + {"RSEL_GROUP3_2_DOP", BCMPKT_TRACE_DOP_ID_RSEL_GROUP3_2_DOP},\ + {"RSEL_GROUP3_3_DOP", BCMPKT_TRACE_DOP_ID_RSEL_GROUP3_3_DOP},\ + {"RSEL_GROUP3_4_DOP", BCMPKT_TRACE_DOP_ID_RSEL_GROUP3_4_DOP},\ + {"RSEL_GROUP3_5_DOP", BCMPKT_TRACE_DOP_ID_RSEL_GROUP3_5_DOP},\ + {"SW_GROUP1_1_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP1_1_DOP},\ + {"SW_GROUP1_2_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP1_2_DOP},\ + {"SW_GROUP1_3_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP1_3_DOP},\ + {"SW_GROUP1_4_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP1_4_DOP},\ + {"SW_GROUP1_5_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP1_5_DOP},\ + {"SW_GROUP1_6_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP1_6_DOP},\ + {"SW_GROUP1_7_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP1_7_DOP},\ + {"SW_GROUP2_1_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP2_1_DOP},\ + {"SW_GROUP2_2_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP2_2_DOP},\ + {"SW_GROUP2_3_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP2_3_DOP},\ + {"SW_GROUP2_4_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP2_4_DOP},\ + {"SW_GROUP3_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP3_DOP},\ + {"SW_GROUP4_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP4_DOP},\ + {"SW_GROUP5_1_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP5_1_DOP},\ + {"SW_GROUP5_2_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP5_2_DOP},\ + {"SW_GROUP5_3_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP5_3_DOP},\ + {"SW_GROUP6_1_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP6_1_DOP},\ + {"SW_GROUP6_2_DOP", BCMPKT_TRACE_DOP_ID_SW_GROUP6_2_DOP},\ + {"UDF_COND_TCAM_DOP", BCMPKT_TRACE_DOP_ID_UDF_COND_TCAM_DOP},\ + {"VFP_TCAM_KEY_DOP", BCMPKT_TRACE_DOP_ID_VFP_TCAM_KEY_DOP},\ + {"VFP_TCAM_RESULT_DOP", BCMPKT_TRACE_DOP_ID_VFP_TCAM_RESULT_DOP},\ + {"LPP_IPARS_MATCH_ID_DOP", BCMPKT_TRACE_DOP_ID_LPP_IPARS_MATCH_ID_DOP},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_LPP_IFP_MEM0_0_KEY_DOP},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_0_KEY_DOP},\ + {"LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP", BCMPKT_TRACE_DOP_ID_LPP_ISW_AUX_COPY_COS_PORT_TCAM_DOP},\ + {"LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP", BCMPKT_TRACE_DOP_ID_LPP_EPARS_EGR_LOCAL_INCA_COLLECTIVE_2_TCAM_DOP},\ + {"LPP_IPARS_LPP_IPAD_BUS_DOP", BCMPKT_TRACE_DOP_ID_LPP_IPARS_LPP_IPAD_BUS_DOP},\ + {"LPP_IFWD_ALPM_LPM_KEY_GEN_CONTROLS_DOP", BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_LPM_KEY_GEN_CONTROLS_DOP},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_LPP_IFP_MEM0_2_KEY_DOP},\ + {"LPP_IRSEL_AR_AR_INFO_DOP", BCMPKT_TRACE_DOP_ID_LPP_IRSEL_AR_AR_INFO_DOP},\ + {"LPP_EPMOD_EGR_COUNTERS_DOP", BCMPKT_TRACE_DOP_ID_LPP_EPMOD_EGR_COUNTERS_DOP},\ + {"LPP_IPARS_FINAL_VRF_DOP", BCMPKT_TRACE_DOP_ID_LPP_IPARS_FINAL_VRF_DOP},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_3_KEY_DOP},\ + {"LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_0_KEY_DOP},\ + {"LPP_ISW_SW_COPY_DOP", BCMPKT_TRACE_DOP_ID_LPP_ISW_SW_COPY_DOP},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_3_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_LPP_IFP_MEM0_3_KEY_DOP},\ + {"LPP_IFWD_ALPM_FXT_HASH_OUT_GEN_DOP", BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_FXT_HASH_OUT_GEN_DOP},\ + {"LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_INDEX_DOP", BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_INDEX_DOP},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP", BCMPKT_TRACE_DOP_ID_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_2_KEY_DOP},\ + {"LPP_EPARS_EPARS_MATCH_ID_DOP", BCMPKT_TRACE_DOP_ID_LPP_EPARS_EPARS_MATCH_ID_DOP},\ + {"LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP", BCMPKT_TRACE_DOP_ID_LPP_EPARS_EGR_INCA_OPCODE_MAP_TCAM_DOP},\ + {"LPP_ISW_NONSW_COPY_DOP", BCMPKT_TRACE_DOP_ID_LPP_ISW_NONSW_COPY_DOP},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_LPP_IFP_MEM0_1_KEY_DOP},\ + {"LPP_ISW_IFA_MIRROR_DOP", BCMPKT_TRACE_DOP_ID_LPP_ISW_IFA_MIRROR_DOP},\ + {"LPP_EPARS_EGR_PP_PORT_DOP", BCMPKT_TRACE_DOP_ID_LPP_EPARS_EGR_PP_PORT_DOP},\ + {"LPP_IRSEL_RSEL_DR_PORT_INFO_DOP", BCMPKT_TRACE_DOP_ID_LPP_IRSEL_RSEL_DR_PORT_INFO_DOP},\ + {"LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP", BCMPKT_TRACE_DOP_ID_LPP_IPARS_INCA_OPCODE_MAP_TCAM_DOP},\ + {"LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP", BCMPKT_TRACE_DOP_ID_LPP_ISW_SW_COPY_COS_PORT_TCAM_DOP},\ + {"LPP_ISW_NEXT_HOP_DOP", BCMPKT_TRACE_DOP_ID_LPP_ISW_NEXT_HOP_DOP},\ + {"LPP_IRSEL_RSEL_EGRESS_PORT_INFO_DOP", BCMPKT_TRACE_DOP_ID_LPP_IRSEL_RSEL_EGRESS_PORT_INFO_DOP},\ + {"LPP_ISW_MISC_2_DOP", BCMPKT_TRACE_DOP_ID_LPP_ISW_MISC_2_DOP},\ + {"LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP", BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_RESOLVED_FORWARDING_ACTIONS_GEN_DOP},\ + {"LPP_ISW_ING_COUNTER_INCR_DOP", BCMPKT_TRACE_DOP_ID_LPP_ISW_ING_COUNTER_INCR_DOP},\ + {"LPP_IPARS_MY_STATION_HIT_DOP", BCMPKT_TRACE_DOP_ID_LPP_IPARS_MY_STATION_HIT_DOP},\ + {"LPP_IFWD_ALPM_LEVEL2_HIT_INFO_DOP", BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_LEVEL2_HIT_INFO_DOP},\ + {"LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP", BCMPKT_TRACE_DOP_ID_LPP_IRSEL_RSEL_AR_RESULT_INFO_DOP},\ + {"MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP", BCMPKT_TRACE_DOP_ID_MEMDB_TCAM_LPP_IFP_MEM0_INDEX_DOP},\ + {"LPP_EPARS_EPARS_INCA_DOP", BCMPKT_TRACE_DOP_ID_LPP_EPARS_EPARS_INCA_DOP},\ + {"LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY_DOP", BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_LWR_256_0_KEY_DOP},\ + {"LPP_IRSEL_RSEL_DEST_INFO_DOP", BCMPKT_TRACE_DOP_ID_LPP_IRSEL_RSEL_DEST_INFO_DOP},\ + {"LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP", BCMPKT_TRACE_DOP_ID_LPP_IPARS_VLAN_TO_VRF_MAPPING_TCAM_DOP},\ + {"LPP_EPMOD_EGR_EVENT_VECTOR_DOP", BCMPKT_TRACE_DOP_ID_LPP_EPMOD_EGR_EVENT_VECTOR_DOP},\ + {"LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP", BCMPKT_TRACE_DOP_ID_LPP_IRSEL_RSEL_ECMP_DR_INFO_DOP},\ + {"LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP", BCMPKT_TRACE_DOP_ID_LPP_IPARS_INCA_COLLECTIVE_MAP_TCAM_DOP},\ + {"LPP_ISW_MISC_DOP", BCMPKT_TRACE_DOP_ID_LPP_ISW_MISC_DOP},\ + {"LPP_ISW_PROTOCOL_TCAM_DOP", BCMPKT_TRACE_DOP_ID_LPP_ISW_PROTOCOL_TCAM_DOP},\ + {"LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP", BCMPKT_TRACE_DOP_ID_LPP_IFWD_IFP_IFP_LTS_TCAM_ONLY_1_KEY_DOP},\ + {"LPP_IPARS_IPARS_MAPPED_DSCP_DOP", BCMPKT_TRACE_DOP_ID_LPP_IPARS_IPARS_MAPPED_DSCP_DOP},\ + {"LPP_EPMOD_EDIT_ACTION_DOP_DOP", BCMPKT_TRACE_DOP_ID_LPP_EPMOD_EDIT_ACTION_DOP_DOP},\ + {"LPP_IPARS_UDF_TCAM_DOP", BCMPKT_TRACE_DOP_ID_LPP_IPARS_UDF_TCAM_DOP},\ + {"LPP_IRSEL_RSEL_METER_INFO_DOP", BCMPKT_TRACE_DOP_ID_LPP_IRSEL_RSEL_METER_INFO_DOP},\ + {"LPP_EPARS_EPARS_TS_1588_DOP", BCMPKT_TRACE_DOP_ID_LPP_EPARS_EPARS_TS_1588_DOP},\ + {"LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_INDEX_DOP", BCMPKT_TRACE_DOP_ID_LPP_IFWD_ALPM_L3_DEFIP_ALPM_LEVEL1_UPR_256_INDEX_DOP},\ + {"fid count", BCMPKT_TRACE_DOP_ID_COUNT} + +/*! + * \name TRACE DOP Internal usage field IDs. + * \anchor BCMPKT_TRACE_DOP_I_XXX + */ +/*! \{ */ +/*! Invalid BCMPKT_TRACE_DOP_I FID indicator */ +#define BCMPKT_TRACE_DOP_I_FID_INVALID -1 +/*! Ingress DOP count. */ +#define BCMPKT_TRACE_DOP_I_ING_DOP_COUNT 0 +/*! Egress DOP count. */ +#define BCMPKT_TRACE_DOP_I_EGR_DOP_COUNT 1 +/*! Max DOP size in word count. */ +#define BCMPKT_TRACE_DOP_I_MAX_DOP_PHASE 2 +/*! Max DOP field count. */ +#define BCMPKT_TRACE_DOP_I_MAX_DOP_FIELD_COUNT 3 +/*! TRACE_DOP_I FIELD ID NUMBER */ +#define BCMPKT_TRACE_DOP_I_FID_COUNT 4 +/*! \} */ + +/*! TRACE_DOP_I field name strings for debugging. */ +#define BCMPKT_TRACE_DOP_I_FIELD_NAME_MAP_INIT \ + {"ING_DOP_COUNT", BCMPKT_TRACE_DOP_I_ING_DOP_COUNT},\ + {"EGR_DOP_COUNT", BCMPKT_TRACE_DOP_I_EGR_DOP_COUNT},\ + {"MAX_DOP_PHASE", BCMPKT_TRACE_DOP_I_MAX_DOP_PHASE},\ + {"MAX_DOP_FIELD_COUNT", BCMPKT_TRACE_DOP_I_MAX_DOP_FIELD_COUNT},\ + {"fid count", BCMPKT_TRACE_DOP_I_FID_COUNT} + +/*! BFD terminated drop. */ +#define BCMPKT_TRACE_DROP_REASON_BFD_TERMINATED_DROP 0 +/*! Drop due to BPDU. */ +#define BCMPKT_TRACE_DROP_REASON_BPDU 1 +/*! Packets dropped due to CFI or L3 disable. */ +#define BCMPKT_TRACE_DROP_REASON_CFI_OR_L3DISABLE 2 +/*! Drop due to CML. */ +#define BCMPKT_TRACE_DROP_REASON_CML 3 +/*! Drop due to parity/ecc errors. */ +#define BCMPKT_TRACE_DROP_REASON_COMPOSITE_ERROR 4 +/*! Packet dropped due to CONTROL_FRAME. */ +#define BCMPKT_TRACE_DROP_REASON_CONTROL_FRAME 5 +/*! Packet dropped due to IPV4 protocol error. */ +#define BCMPKT_TRACE_DROP_REASON_IPV4_PROTOCOL_ERROR 6 +/*! Packet dropped due to IPV6 protocol error. */ +#define BCMPKT_TRACE_DROP_REASON_IPV6_PROTOCOL_ERROR 7 +/*! Packet dropped due to L3_DOS_ATTACK. */ +#define BCMPKT_TRACE_DROP_REASON_L3_DOS_ATTACK 8 +/*! Packet dropped due to L4_DOS_ATTACK. */ +#define BCMPKT_TRACE_DROP_REASON_L4_DOS_ATTACK 9 +/*! Packet dropped due to LAG_FAIL_LOOPBACK. */ +#define BCMPKT_TRACE_DROP_REASON_LAG_FAIL_LOOPBACK 10 +/*! Packet dropped due to MACSA_EQUALS_DA. */ +#define BCMPKT_TRACE_DROP_REASON_MACSA_EQUALS_DA 11 +/*! IPMC header error drop. */ +#define BCMPKT_TRACE_DROP_REASON_IPMC_PROC 12 +/*! Packets dropped due to L2 destination discard. */ +#define BCMPKT_TRACE_DROP_REASON_L2DST_DISCARD 13 +/*! Packets dropped due to L2 source discard. */ +#define BCMPKT_TRACE_DROP_REASON_L2SRC_DISCARD 14 +/*! L2 source static move drop. */ +#define BCMPKT_TRACE_DROP_REASON_L2SRC_STATIC_MOVE 15 +/*! L3 destination discard drop. */ +#define BCMPKT_TRACE_DROP_REASON_L3DST_DISCARD 16 +/*! L3 source discard drop. */ +#define BCMPKT_TRACE_DROP_REASON_L3SRC_DISCARD 17 +/*! L3 destination lookup miss drop. */ +#define BCMPKT_TRACE_DROP_REASON_L3_DST_LOOKUP_MISS 18 +/*! L3 header error drop. */ +#define BCMPKT_TRACE_DROP_REASON_L3_HDR_ERROR 19 +/*! L3 TTL error drop. */ +#define BCMPKT_TRACE_DROP_REASON_L3_TTL_ERROR 20 +/*! MACSA is zero. */ +#define BCMPKT_TRACE_DROP_REASON_MACSA0 21 +/*! MPLS stage drop. */ +#define BCMPKT_TRACE_DROP_REASON_MPLS_STAGE 22 +/*! Drop due to multicast index error. */ +#define BCMPKT_TRACE_DROP_REASON_MULTICAST_INDEX_ERROR 23 +/*! Drop due to my station lookup miss. */ +#define BCMPKT_TRACE_DROP_REASON_MY_STATION 24 +/*! Port filtering mode drop. */ +#define BCMPKT_TRACE_DROP_REASON_PFM 25 +/*! Drop due to protocol packets. */ +#define BCMPKT_TRACE_DROP_REASON_PROTCOL_PKT 26 +/*! Private vlan VP filter drop. */ +#define BCMPKT_TRACE_DROP_REASON_PVLAN_VP_EFILTER 27 +/*! Packet dropped due to ECMP resolution error. */ +#define BCMPKT_TRACE_DROP_REASON_ECMP_RESOLUTION_ERROR 28 +/*! Packet dropped due to FP change l2 fields no redirect. */ +#define BCMPKT_TRACE_DROP_REASON_FP_CHANGE_L2_FIELDS_NO_REDIRECT_DROP 29 +/*! Packet dropped due to IFP drop. */ +#define BCMPKT_TRACE_DROP_REASON_IFP_DROP 30 +/*! Packet dropped due to next hop indication. */ +#define BCMPKT_TRACE_DROP_REASON_NEXT_HOP_DROP 31 +/*! Packet dropped due to protection. */ +#define BCMPKT_TRACE_DROP_REASON_PROTECTION_DATA_DROP 32 +/*! Packet dropped due to tunnel errors. */ +#define BCMPKT_TRACE_DROP_REASON_TUNNEL_ERROR 33 +/*! Drop due to spanning tree. */ +#define BCMPKT_TRACE_DROP_REASON_SPANNING_TREE_STATE 34 +/*! Drop due to source route. */ +#define BCMPKT_TRACE_DROP_REASON_SRC_ROUTE 35 +/*! Packets dropped due to LPORT.PORT_DIS_UNTAG or LPORT.PORT_DIS_TAG. */ +#define BCMPKT_TRACE_DROP_REASON_TAG_UNTAG_DISCARD 36 +/*! Time sync packet drop. */ +#define BCMPKT_TRACE_DROP_REASON_TIME_SYNC_PKT 37 +/*! Tunnel decap ECN error drop. */ +#define BCMPKT_TRACE_DROP_REASON_TUNNEL_DECAP_ECN 38 +/*! Packet dropped due to MPLS Generic Label lookup miss. */ +#define BCMPKT_TRACE_DROP_REASON_MPLS_GAL_LABEL 39 +/*! Packet dropped due to MPLS invalid action. */ +#define BCMPKT_TRACE_DROP_REASON_MPLS_INVALID_ACTION 40 +/*! Packet dropped due to MPLS invalid control word. */ +#define BCMPKT_TRACE_DROP_REASON_MPLS_INVALID_CW 41 +/*! Packet dropped due to MPLS invalid payload. */ +#define BCMPKT_TRACE_DROP_REASON_MPLS_INVALID_PAYLOAD 42 +/*! Packet dropped due to MPLS label lookup miss. */ +#define BCMPKT_TRACE_DROP_REASON_MPLS_LABEL_MISS 43 +/*! Packet dropped due to MPLS TTL check fail. */ +#define BCMPKT_TRACE_DROP_REASON_MPLS_TTL_CHECK_FAIL 44 +/*! Packet dropped by VFP. */ +#define BCMPKT_TRACE_DROP_REASON_VFP 45 +/*! Vlan cross-connect drop. */ +#define BCMPKT_TRACE_DROP_REASON_VLAN_CC_OR_PBT 46 +/*! Packet dropped due to ingress port not in VLAN membership. */ +#define BCMPKT_TRACE_DROP_REASON_ENIFILTER 47 +/*! Packet dropped due to TPID mismatch. */ +#define BCMPKT_TRACE_DROP_REASON_INVALID_TPID 48 +/*! Packet dropped due to VLAN not valid. */ +#define BCMPKT_TRACE_DROP_REASON_INVALID_VLAN 49 +/*! Packet dropped due to PVLAN VID mismatch. */ +#define BCMPKT_TRACE_DROP_REASON_PVLAN_VID_MISMATCH 50 +/*! VXLT miss drop condition. */ +#define BCMPKT_TRACE_DROP_REASON_VXLT_MISS 51 +/*! HiGig module header type 1 drop. */ +#define BCMPKT_TRACE_DROP_REASON_HIGIG_MH_TYPE1 52 +/*! HiGig discard drop. */ +#define BCMPKT_TRACE_DROP_REASON_DISC_STAGE 53 +/*! HiGig invalid VLAN drop. */ +#define BCMPKT_TRACE_DROP_REASON_SW1_INVALID_VLAN 54 +/*! HiGig Header error drop. */ +#define BCMPKT_TRACE_DROP_REASON_HIGIG_HDR_ERROR 55 +/*! This is looped back packet. */ +#define BCMPKT_TRACE_DROP_REASON_LAG_FAILOVER 56 +/*! Class based learning drop. */ +#define BCMPKT_TRACE_DROP_REASON_CLASS_BASED_SM 57 +/*! Bad udp checksum drop. */ +#define BCMPKT_TRACE_DROP_REASON_BAD_UDP_CHECKSUM 58 +/*! NIV Forwarding drop. */ +#define BCMPKT_TRACE_DROP_REASON_NIV_FORWARDING 59 +/*! NIV RPF check fail drop. */ +#define BCMPKT_TRACE_DROP_REASON_NIV_RPF_CHECK_FAIL 60 +/*! Trill Header Version Nonzero drop. */ +#define BCMPKT_TRACE_DROP_REASON_TRILL_HEADER_VERSION_NONZERO 61 +/*! Trill Adjacency Check Fail drop. */ +#define BCMPKT_TRACE_DROP_REASON_TRILL_ADJACENCY_CHECK_FAIL 62 +/*! Trill RBridge Lookup Miss drop. */ +#define BCMPKT_TRACE_DROP_REASON_TRILL_RBRIDGE_LOOKUP_MISS 63 +/*! Trill UC HDR MC MACDA drop. */ +#define BCMPKT_TRACE_DROP_REASON_TRILL_UC_HDR_MC_MACDA 64 +/*! Trill Slowpath drop. */ +#define BCMPKT_TRACE_DROP_REASON_TRILL_SLOWPATH 65 +/*! Core IS-IS Packet drop. */ +#define BCMPKT_TRACE_DROP_REASON_CORE_IS_IS_PKT 66 +/*! Trill RPF Check Fail drop. */ +#define BCMPKT_TRACE_DROP_REASON_TRILL_RPF_CHECK_FAIL 67 +/*! Trill Packet with SNAP Encap drop. */ +#define BCMPKT_TRACE_DROP_REASON_TRILL_PKT_WITH_SNAP_ENCAP 68 +/*! Trill Packet with Ingress RBridge equal to Egress RBridge drop. */ +#define BCMPKT_TRACE_DROP_REASON_TRILL_ING_RBRIDGE_EQ_EGR_RBRIDGE 69 +/*! Trill Hop Count check fail drop. */ +#define BCMPKT_TRACE_DROP_REASON_TRILL_HOPCOUNT_CHECK_FAIL 70 +/*! INT dataplane probe */ +#define BCMPKT_TRACE_DROP_REASON_INT_DATAPLANE_PROBE 71 +/*! INT packet error */ +#define BCMPKT_TRACE_DROP_REASON_INT_ERROR 72 +/*! Invalid GSH packet dropped */ +#define BCMPKT_TRACE_DROP_REASON_INVALID_GSH_DROP 73 +/*! Invalid non-GSH packet dropped */ +#define BCMPKT_TRACE_DROP_REASON_INVALID_NON_GSH_DROP 74 +/*! Drop due to parity/ecc errors */ +#define BCMPKT_TRACE_DROP_REASON_SER_DROP 75 +/*! Packet dropped due to SRV6 process error. */ +#define BCMPKT_TRACE_DROP_REASON_SRV6_PROC_DROP 76 +/*! Packet dropped due to SRV6 validation error. */ +#define BCMPKT_TRACE_DROP_REASON_SRV6_VALIDATION_DROP 77 +/*! Packet dropped due to VXLAN Tunnel Error. */ +#define BCMPKT_TRACE_DROP_REASON_VXLAN_TUNNEL_ERROR_DROP 78 +/*! Packet dropped due VXLAN VN_ID lookup miss. */ +#define BCMPKT_TRACE_DROP_REASON_VXLAN_VN_ID_LOOKUP_MISS 79 +/*! + * Packet dropped due to unknown routing type in SRV6 packet with nonzero + * SegmentLeft field. + */ +#define BCMPKT_TRACE_DROP_REASON_UNKNOWN_RH_WITH_NONZERO_SL_DROP 80 +/*! Adapt miss drop */ +#define BCMPKT_TRACE_DROP_REASON_ADAPT_MISS_DROP 81 +/*! + * Both O_NH/INTF and U_NH_INTF are valid, and each of these indices do NOT comply + * with configured bank allocation bitmap + */ +#define BCMPKT_TRACE_DROP_REASON_OVERLAY_UNDERLAY_RANGE_ERROR 82 +/*! VXLAN SIP lookup miss drop */ +#define BCMPKT_TRACE_DROP_REASON_VXLAN_SIP_LOOKUP_MISS_DROP 83 +/*! Packet dropped due to SVTAG lookup miss */ +#define BCMPKT_TRACE_DROP_REASON_SVTAG_LOOKUP_MISS 84 +/*! VXLAN/SRv6_L2 SIP lookup miss drop */ +#define BCMPKT_TRACE_DROP_REASON_L2_TUNNEL_SIP_LOOKUP_MISS_DROP 85 +/*! Invalid */ +#define BCMPKT_TRACE_DROP_REASON_INVALID 86 +/*! BCMPKT_TRACE_DROP_REASON TYPE NUMBER */ +#define BCMPKT_TRACE_DROP_REASON_COUNT 87 +/*! \} */ + +/*! TRACE DROP reason name strings for debugging. */ +#define BCMPKT_TRACE_DROP_REASON_NAME_MAP_INIT \ + {"BFD_TERMINATED_DROP", BCMPKT_TRACE_DROP_REASON_BFD_TERMINATED_DROP},\ + {"BPDU", BCMPKT_TRACE_DROP_REASON_BPDU},\ + {"CFI_OR_L3DISABLE", BCMPKT_TRACE_DROP_REASON_CFI_OR_L3DISABLE},\ + {"CML", BCMPKT_TRACE_DROP_REASON_CML},\ + {"COMPOSITE_ERROR", BCMPKT_TRACE_DROP_REASON_COMPOSITE_ERROR},\ + {"CONTROL_FRAME", BCMPKT_TRACE_DROP_REASON_CONTROL_FRAME},\ + {"IPV4_PROTOCOL_ERROR", BCMPKT_TRACE_DROP_REASON_IPV4_PROTOCOL_ERROR},\ + {"IPV6_PROTOCOL_ERROR", BCMPKT_TRACE_DROP_REASON_IPV6_PROTOCOL_ERROR},\ + {"L3_DOS_ATTACK", BCMPKT_TRACE_DROP_REASON_L3_DOS_ATTACK},\ + {"L4_DOS_ATTACK", BCMPKT_TRACE_DROP_REASON_L4_DOS_ATTACK},\ + {"LAG_FAIL_LOOPBACK", BCMPKT_TRACE_DROP_REASON_LAG_FAIL_LOOPBACK},\ + {"MACSA_EQUALS_DA", BCMPKT_TRACE_DROP_REASON_MACSA_EQUALS_DA},\ + {"IPMC_PROC", BCMPKT_TRACE_DROP_REASON_IPMC_PROC},\ + {"L2DST_DISCARD", BCMPKT_TRACE_DROP_REASON_L2DST_DISCARD},\ + {"L2SRC_DISCARD", BCMPKT_TRACE_DROP_REASON_L2SRC_DISCARD},\ + {"L2SRC_STATIC_MOVE", BCMPKT_TRACE_DROP_REASON_L2SRC_STATIC_MOVE},\ + {"L3DST_DISCARD", BCMPKT_TRACE_DROP_REASON_L3DST_DISCARD},\ + {"L3SRC_DISCARD", BCMPKT_TRACE_DROP_REASON_L3SRC_DISCARD},\ + {"L3_DST_LOOKUP_MISS", BCMPKT_TRACE_DROP_REASON_L3_DST_LOOKUP_MISS},\ + {"L3_HDR_ERROR", BCMPKT_TRACE_DROP_REASON_L3_HDR_ERROR},\ + {"L3_TTL_ERROR", BCMPKT_TRACE_DROP_REASON_L3_TTL_ERROR},\ + {"MACSA0", BCMPKT_TRACE_DROP_REASON_MACSA0},\ + {"MPLS_STAGE", BCMPKT_TRACE_DROP_REASON_MPLS_STAGE},\ + {"MULTICAST_INDEX_ERROR", BCMPKT_TRACE_DROP_REASON_MULTICAST_INDEX_ERROR},\ + {"MY_STATION", BCMPKT_TRACE_DROP_REASON_MY_STATION},\ + {"PFM", BCMPKT_TRACE_DROP_REASON_PFM},\ + {"PROTCOL_PKT", BCMPKT_TRACE_DROP_REASON_PROTCOL_PKT},\ + {"PVLAN_VP_EFILTER", BCMPKT_TRACE_DROP_REASON_PVLAN_VP_EFILTER},\ + {"ECMP_RESOLUTION_ERROR", BCMPKT_TRACE_DROP_REASON_ECMP_RESOLUTION_ERROR},\ + {"FP_CHANGE_L2_FIELDS_NO_REDIRECT_DROP", BCMPKT_TRACE_DROP_REASON_FP_CHANGE_L2_FIELDS_NO_REDIRECT_DROP},\ + {"IFP_DROP", BCMPKT_TRACE_DROP_REASON_IFP_DROP},\ + {"NEXT_HOP_DROP", BCMPKT_TRACE_DROP_REASON_NEXT_HOP_DROP},\ + {"PROTECTION_DATA_DROP", BCMPKT_TRACE_DROP_REASON_PROTECTION_DATA_DROP},\ + {"TUNNEL_ERROR", BCMPKT_TRACE_DROP_REASON_TUNNEL_ERROR},\ + {"SPANNING_TREE_STATE", BCMPKT_TRACE_DROP_REASON_SPANNING_TREE_STATE},\ + {"SRC_ROUTE", BCMPKT_TRACE_DROP_REASON_SRC_ROUTE},\ + {"TAG_UNTAG_DISCARD", BCMPKT_TRACE_DROP_REASON_TAG_UNTAG_DISCARD},\ + {"TIME_SYNC_PKT", BCMPKT_TRACE_DROP_REASON_TIME_SYNC_PKT},\ + {"TUNNEL_DECAP_ECN", BCMPKT_TRACE_DROP_REASON_TUNNEL_DECAP_ECN},\ + {"MPLS_GAL_LABEL", BCMPKT_TRACE_DROP_REASON_MPLS_GAL_LABEL},\ + {"MPLS_INVALID_ACTION", BCMPKT_TRACE_DROP_REASON_MPLS_INVALID_ACTION},\ + {"MPLS_INVALID_CW", BCMPKT_TRACE_DROP_REASON_MPLS_INVALID_CW},\ + {"MPLS_INVALID_PAYLOAD", BCMPKT_TRACE_DROP_REASON_MPLS_INVALID_PAYLOAD},\ + {"MPLS_LABEL_MISS", BCMPKT_TRACE_DROP_REASON_MPLS_LABEL_MISS},\ + {"MPLS_TTL_CHECK_FAIL", BCMPKT_TRACE_DROP_REASON_MPLS_TTL_CHECK_FAIL},\ + {"VFP", BCMPKT_TRACE_DROP_REASON_VFP},\ + {"VLAN_CC_OR_PBT", BCMPKT_TRACE_DROP_REASON_VLAN_CC_OR_PBT},\ + {"ENIFILTER", BCMPKT_TRACE_DROP_REASON_ENIFILTER},\ + {"INVALID_TPID", BCMPKT_TRACE_DROP_REASON_INVALID_TPID},\ + {"INVALID_VLAN", BCMPKT_TRACE_DROP_REASON_INVALID_VLAN},\ + {"PVLAN_VID_MISMATCH", BCMPKT_TRACE_DROP_REASON_PVLAN_VID_MISMATCH},\ + {"VXLT_MISS", BCMPKT_TRACE_DROP_REASON_VXLT_MISS},\ + {"HIGIG_MH_TYPE1", BCMPKT_TRACE_DROP_REASON_HIGIG_MH_TYPE1},\ + {"DISC_STAGE", BCMPKT_TRACE_DROP_REASON_DISC_STAGE},\ + {"SW1_INVALID_VLAN", BCMPKT_TRACE_DROP_REASON_SW1_INVALID_VLAN},\ + {"HIGIG_HDR_ERROR", BCMPKT_TRACE_DROP_REASON_HIGIG_HDR_ERROR},\ + {"LAG_FAILOVER", BCMPKT_TRACE_DROP_REASON_LAG_FAILOVER},\ + {"CLASS_BASED_SM", BCMPKT_TRACE_DROP_REASON_CLASS_BASED_SM},\ + {"BAD_UDP_CHECKSUM", BCMPKT_TRACE_DROP_REASON_BAD_UDP_CHECKSUM},\ + {"NIV_FORWARDING", BCMPKT_TRACE_DROP_REASON_NIV_FORWARDING},\ + {"NIV_RPF_CHECK_FAIL", BCMPKT_TRACE_DROP_REASON_NIV_RPF_CHECK_FAIL},\ + {"TRILL_HEADER_VERSION_NONZERO", BCMPKT_TRACE_DROP_REASON_TRILL_HEADER_VERSION_NONZERO},\ + {"TRILL_ADJACENCY_CHECK_FAIL", BCMPKT_TRACE_DROP_REASON_TRILL_ADJACENCY_CHECK_FAIL},\ + {"TRILL_RBRIDGE_LOOKUP_MISS", BCMPKT_TRACE_DROP_REASON_TRILL_RBRIDGE_LOOKUP_MISS},\ + {"TRILL_UC_HDR_MC_MACDA", BCMPKT_TRACE_DROP_REASON_TRILL_UC_HDR_MC_MACDA},\ + {"TRILL_SLOWPATH", BCMPKT_TRACE_DROP_REASON_TRILL_SLOWPATH},\ + {"CORE_IS_IS_PKT", BCMPKT_TRACE_DROP_REASON_CORE_IS_IS_PKT},\ + {"TRILL_RPF_CHECK_FAIL", BCMPKT_TRACE_DROP_REASON_TRILL_RPF_CHECK_FAIL},\ + {"TRILL_PKT_WITH_SNAP_ENCAP", BCMPKT_TRACE_DROP_REASON_TRILL_PKT_WITH_SNAP_ENCAP},\ + {"TRILL_ING_RBRIDGE_EQ_EGR_RBRIDGE", BCMPKT_TRACE_DROP_REASON_TRILL_ING_RBRIDGE_EQ_EGR_RBRIDGE},\ + {"TRILL_HOPCOUNT_CHECK_FAIL", BCMPKT_TRACE_DROP_REASON_TRILL_HOPCOUNT_CHECK_FAIL},\ + {"INT_DATAPLANE_PROBE", BCMPKT_TRACE_DROP_REASON_INT_DATAPLANE_PROBE},\ + {"INT_ERROR", BCMPKT_TRACE_DROP_REASON_INT_ERROR},\ + {"INVALID_GSH_DROP", BCMPKT_TRACE_DROP_REASON_INVALID_GSH_DROP},\ + {"INVALID_NON_GSH_DROP", BCMPKT_TRACE_DROP_REASON_INVALID_NON_GSH_DROP},\ + {"SER_DROP", BCMPKT_TRACE_DROP_REASON_SER_DROP},\ + {"SRV6_PROC_DROP", BCMPKT_TRACE_DROP_REASON_SRV6_PROC_DROP},\ + {"SRV6_VALIDATION_DROP", BCMPKT_TRACE_DROP_REASON_SRV6_VALIDATION_DROP},\ + {"VXLAN_TUNNEL_ERROR_DROP", BCMPKT_TRACE_DROP_REASON_VXLAN_TUNNEL_ERROR_DROP},\ + {"VXLAN_VN_ID_LOOKUP_MISS", BCMPKT_TRACE_DROP_REASON_VXLAN_VN_ID_LOOKUP_MISS},\ + {"UNKNOWN_RH_WITH_NONZERO_SL_DROP", BCMPKT_TRACE_DROP_REASON_UNKNOWN_RH_WITH_NONZERO_SL_DROP},\ + {"ADAPT_MISS_DROP", BCMPKT_TRACE_DROP_REASON_ADAPT_MISS_DROP},\ + {"OVERLAY_UNDERLAY_RANGE_ERROR", BCMPKT_TRACE_DROP_REASON_OVERLAY_UNDERLAY_RANGE_ERROR},\ + {"VXLAN_SIP_LOOKUP_MISS_DROP", BCMPKT_TRACE_DROP_REASON_VXLAN_SIP_LOOKUP_MISS_DROP},\ + {"SVTAG_LOOKUP_MISS", BCMPKT_TRACE_DROP_REASON_SVTAG_LOOKUP_MISS},\ + {"L2_TUNNEL_SIP_LOOKUP_MISS_DROP", BCMPKT_TRACE_DROP_REASON_L2_TUNNEL_SIP_LOOKUP_MISS_DROP},\ + {"INVALID", BCMPKT_TRACE_DROP_REASON_INVALID},\ + {"trace drop reason count", BCMPKT_TRACE_DROP_REASON_COUNT} + /*! BCMPKT_TRACE_DROP_REASON_DEFS_H */ + +/*! + * \name Packet TRACE COUNTER Types. + * \anchor BCMPKT_TRACE_COUNTER_XXX + */ +/*! \{ */ +/*! L3 pkt discarded due to resource. */ +#define BCMPKT_TRACE_COUNTER_RIPD4 0 +/*! Forwarded IPv4 packets. */ +#define BCMPKT_TRACE_COUNTER_RIPC4 1 +/*! IP Header Error packets. */ +#define BCMPKT_TRACE_COUNTER_RIPHE4 2 +/*! Routed IPv4 Muliticast packets. */ +#define BCMPKT_TRACE_COUNTER_IMRP4 3 +/*! L3 pkt discarded due to resource. */ +#define BCMPKT_TRACE_COUNTER_RIPD6 4 +/*! Forwarded IPv6 packets. */ +#define BCMPKT_TRACE_COUNTER_RIPC6 5 +/*! IP Header Error packets. */ +#define BCMPKT_TRACE_COUNTER_RIPHE6 6 +/*! Routed IPv6 Muliticast packets. */ +#define BCMPKT_TRACE_COUNTER_IMRP6 7 +/*! BFD Version number of ACH header is not zero or ACH channel type is unknown. */ +#define BCMPKT_TRACE_COUNTER_BFD_UNKNOWN_ACH_ERROR 8 +/*! + * Unrecognized control packet received from control channel, which can be PW VCCV + * type 1/2/3, MPLS-TP control channel, etc. + */ +#define BCMPKT_TRACE_COUNTER_BFD_UNKNOWN_CONTROL_PACKET 9 +/*! BFD Unknown version or discard dropped. */ +#define BCMPKT_TRACE_COUNTER_BFD_UNKNOWN_VER_OR_DISCR 10 +/*! Drop due to block masks. */ +#define BCMPKT_TRACE_COUNTER_BLOCK_MASK_DROP 11 +/*! DOS fragment error packets. */ +#define BCMPKT_TRACE_COUNTER_DSFRAG 12 +/*! DOS ICMP error packets. */ +#define BCMPKT_TRACE_COUNTER_DSICMP 13 +/*! Dos Attack L2 Packets. */ +#define BCMPKT_TRACE_COUNTER_DSL2HE 14 +/*! Bridged Multicast pkts. */ +#define BCMPKT_TRACE_COUNTER_IMBP 15 +/*! LAG failover loopback pkt. */ +#define BCMPKT_TRACE_COUNTER_LAGLUP 16 +/*! LAG failover loopback pkt discarded. */ +#define BCMPKT_TRACE_COUNTER_LAGLUPD 17 +/*! Pkts dropped due to MTU check fail. */ +#define BCMPKT_TRACE_COUNTER_MTU_CHECK_FAIL 18 +/*! Pkts dropped due to parity error. */ +#define BCMPKT_TRACE_COUNTER_PARITYD 19 +/*! Non-IP packet discard dropped. */ +#define BCMPKT_TRACE_COUNTER_PDISC 20 +/*! Portbitmap zero drop condition. */ +#define BCMPKT_TRACE_COUNTER_RDROP 21 +/*! Multicast (L2+L3) packets that are dropped. */ +#define BCMPKT_TRACE_COUNTER_RIMDR 22 +/*! Pkts dropped as ingress port's SP state is not forwarding. */ +#define BCMPKT_TRACE_COUNTER_RPORTD 23 +/*! Good Tunnel terminated packets. */ +#define BCMPKT_TRACE_COUNTER_RTUN 24 +/*! Receive tunnel error packets. */ +#define BCMPKT_TRACE_COUNTER_RTUNE 25 +/*! Good Unicast Packets. */ +#define BCMPKT_TRACE_COUNTER_RUC 26 +/*! Drop due to source port knockout. */ +#define BCMPKT_TRACE_COUNTER_SRC_PORT_KNOCKOUT_DROP 27 +/*! IBP discard and CBP full. */ +#define BCMPKT_TRACE_COUNTER_RDISC 28 +/*! Packets dropped by FP. */ +#define BCMPKT_TRACE_COUNTER_RFILDR 29 +/*! HiGig IPIC pause receive counter. */ +#define BCMPKT_TRACE_COUNTER_IRPSE 30 +/*! HiGig End-to-End HOL receive packet counter. */ +#define BCMPKT_TRACE_COUNTER_IRHOL 31 +/*! HiGig End-to-End IBP receive packet counter. */ +#define BCMPKT_TRACE_COUNTER_IRIBP 32 +/*! DOS L3 header error packets (only applicable to packet from 10GE port). */ +#define BCMPKT_TRACE_COUNTER_DSL3HE 33 +/*! Unknown HiGig header type packet (only applicable to packet from HiGig port). */ +#define BCMPKT_TRACE_COUNTER_IUNKHDR 34 +/*! DOS L4 header error packets (only applicable to packet from 10GE port). */ +#define BCMPKT_TRACE_COUNTER_DSL4HE 35 +/*! HiGig mirror packet (only applicable to packet from HiGig port). */ +#define BCMPKT_TRACE_COUNTER_IMIRROR 36 +/*! Packets trapped to CPU due to egress L3 MTU violation. */ +#define BCMPKT_TRACE_COUNTER_MTUERR 37 +/*! Receive VLAN drop cases. */ +#define BCMPKT_TRACE_COUNTER_VLANDR 38 +/*! HiGig Header error packets. */ +#define BCMPKT_TRACE_COUNTER_HGHDRE 39 +/*! Multicast Index error packets. */ +#define BCMPKT_TRACE_COUNTER_MCIDXE 40 +/*! Receive HiGig Unicast packet. */ +#define BCMPKT_TRACE_COUNTER_RHGUC 41 +/*! Receive HiGig non-Unicast packet. */ +#define BCMPKT_TRACE_COUNTER_RHGMC 42 +/*! Unicast Reverse Path Forwarding. */ +#define BCMPKT_TRACE_COUNTER_URPF 43 +/*! VLAN FP drop case. */ +#define BCMPKT_TRACE_COUNTER_VFPDR 44 +/*! L2/L3 lookup DST_DISCARD drop. */ +#define BCMPKT_TRACE_COUNTER_DSTDISC 45 +/*! Class based learning drop. */ +#define BCMPKT_TRACE_COUNTER_CBLDROP 46 +/*! MAC limit exceeded and packet not dropped. */ +#define BCMPKT_TRACE_COUNTER_MACLMT_NODROP 47 +/*! MAC limit exceeded and packet dropped. */ +#define BCMPKT_TRACE_COUNTER_MACLMT_DROP 48 +/*! VNTAG Error packet dropped. */ +#define BCMPKT_TRACE_COUNTER_VNTAG_ERROR 49 +/*! NIV Forwarding Error dropped. */ +#define BCMPKT_TRACE_COUNTER_NIV_FORWARDING_DROP 50 +/*! Non-Trill Frame on Network Port dropped. */ +#define BCMPKT_TRACE_COUNTER_OFFSET_NONTRILL_FRAME_ON_NW_PORT_DROP 51 +/*! Trill Frame on Access Port dropped. */ +#define BCMPKT_TRACE_COUNTER_OFFSET_TRILL_FRAME_ON_ACCESS_PORT_DROP 52 +/*! Trill errors dropped. */ +#define BCMPKT_TRACE_COUNTER_OFFSET_TRILL_ERRORS_DROP 53 +/*! Trill RBridge Lookup Miss dropped. */ +#define BCMPKT_TRACE_COUNTER_OFFSET_TRILL_RBRIDGE_LOOKUP_MISS_DROP 54 +/*! Trill HopCount check fail dropped. */ +#define BCMPKT_TRACE_COUNTER_OFFSET_TRILL_HOPCOUNT_CHECK_FAIL 55 +/*! Trill RPF Check Fail dropped. */ +#define BCMPKT_TRACE_COUNTER_OFFSET_TRILL_RPF_CHECK_FAIL_DROP 56 +/*! Virtual-Output-Queue-based Flow-Control-Message receive packet counter. */ +#define BCMPKT_TRACE_COUNTER_IRVOQFC 57 +/*! ECMP not resolved. */ +#define BCMPKT_TRACE_COUNTER_ECMP_NOT_RESOLVED 58 +/*! PKT dropped for PT flow sink node. */ +#define BCMPKT_TRACE_COUNTER_PT_SINK_DROP 59 +/*! BCMPKT_TRACE_COUNTER TYPE NUMBER */ +#define BCMPKT_TRACE_COUNTER_COUNT 60 +/*! \} */ + +/*! TRACE COUNTER name strings for debugging. */ +#define BCMPKT_TRACE_COUNTER_NAME_MAP_INIT \ + {"RIPD4", BCMPKT_TRACE_COUNTER_RIPD4},\ + {"RIPC4", BCMPKT_TRACE_COUNTER_RIPC4},\ + {"RIPHE4", BCMPKT_TRACE_COUNTER_RIPHE4},\ + {"IMRP4", BCMPKT_TRACE_COUNTER_IMRP4},\ + {"RIPD6", BCMPKT_TRACE_COUNTER_RIPD6},\ + {"RIPC6", BCMPKT_TRACE_COUNTER_RIPC6},\ + {"RIPHE6", BCMPKT_TRACE_COUNTER_RIPHE6},\ + {"IMRP6", BCMPKT_TRACE_COUNTER_IMRP6},\ + {"BFD_UNKNOWN_ACH_ERROR", BCMPKT_TRACE_COUNTER_BFD_UNKNOWN_ACH_ERROR},\ + {"BFD_UNKNOWN_CONTROL_PACKET", BCMPKT_TRACE_COUNTER_BFD_UNKNOWN_CONTROL_PACKET},\ + {"BFD_UNKNOWN_VER_OR_DISCR", BCMPKT_TRACE_COUNTER_BFD_UNKNOWN_VER_OR_DISCR},\ + {"BLOCK_MASK_DROP", BCMPKT_TRACE_COUNTER_BLOCK_MASK_DROP},\ + {"DSFRAG", BCMPKT_TRACE_COUNTER_DSFRAG},\ + {"DSICMP", BCMPKT_TRACE_COUNTER_DSICMP},\ + {"DSL2HE", BCMPKT_TRACE_COUNTER_DSL2HE},\ + {"IMBP", BCMPKT_TRACE_COUNTER_IMBP},\ + {"LAGLUP", BCMPKT_TRACE_COUNTER_LAGLUP},\ + {"LAGLUPD", BCMPKT_TRACE_COUNTER_LAGLUPD},\ + {"MTU_CHECK_FAIL", BCMPKT_TRACE_COUNTER_MTU_CHECK_FAIL},\ + {"PARITYD", BCMPKT_TRACE_COUNTER_PARITYD},\ + {"PDISC", BCMPKT_TRACE_COUNTER_PDISC},\ + {"RDROP", BCMPKT_TRACE_COUNTER_RDROP},\ + {"RIMDR", BCMPKT_TRACE_COUNTER_RIMDR},\ + {"RPORTD", BCMPKT_TRACE_COUNTER_RPORTD},\ + {"RTUN", BCMPKT_TRACE_COUNTER_RTUN},\ + {"RTUNE", BCMPKT_TRACE_COUNTER_RTUNE},\ + {"RUC", BCMPKT_TRACE_COUNTER_RUC},\ + {"SRC_PORT_KNOCKOUT_DROP", BCMPKT_TRACE_COUNTER_SRC_PORT_KNOCKOUT_DROP},\ + {"RDISC", BCMPKT_TRACE_COUNTER_RDISC},\ + {"RFILDR", BCMPKT_TRACE_COUNTER_RFILDR},\ + {"IRPSE", BCMPKT_TRACE_COUNTER_IRPSE},\ + {"IRHOL", BCMPKT_TRACE_COUNTER_IRHOL},\ + {"IRIBP", BCMPKT_TRACE_COUNTER_IRIBP},\ + {"DSL3HE", BCMPKT_TRACE_COUNTER_DSL3HE},\ + {"IUNKHDR", BCMPKT_TRACE_COUNTER_IUNKHDR},\ + {"DSL4HE", BCMPKT_TRACE_COUNTER_DSL4HE},\ + {"IMIRROR", BCMPKT_TRACE_COUNTER_IMIRROR},\ + {"MTUERR", BCMPKT_TRACE_COUNTER_MTUERR},\ + {"VLANDR", BCMPKT_TRACE_COUNTER_VLANDR},\ + {"HGHDRE", BCMPKT_TRACE_COUNTER_HGHDRE},\ + {"MCIDXE", BCMPKT_TRACE_COUNTER_MCIDXE},\ + {"RHGUC", BCMPKT_TRACE_COUNTER_RHGUC},\ + {"RHGMC", BCMPKT_TRACE_COUNTER_RHGMC},\ + {"URPF", BCMPKT_TRACE_COUNTER_URPF},\ + {"VFPDR", BCMPKT_TRACE_COUNTER_VFPDR},\ + {"DSTDISC", BCMPKT_TRACE_COUNTER_DSTDISC},\ + {"CBLDROP", BCMPKT_TRACE_COUNTER_CBLDROP},\ + {"MACLMT_NODROP", BCMPKT_TRACE_COUNTER_MACLMT_NODROP},\ + {"MACLMT_DROP", BCMPKT_TRACE_COUNTER_MACLMT_DROP},\ + {"VNTAG_ERROR", BCMPKT_TRACE_COUNTER_VNTAG_ERROR},\ + {"NIV_FORWARDING_DROP", BCMPKT_TRACE_COUNTER_NIV_FORWARDING_DROP},\ + {"OFFSET_NONTRILL_FRAME_ON_NW_PORT_DROP", BCMPKT_TRACE_COUNTER_OFFSET_NONTRILL_FRAME_ON_NW_PORT_DROP},\ + {"OFFSET_TRILL_FRAME_ON_ACCESS_PORT_DROP", BCMPKT_TRACE_COUNTER_OFFSET_TRILL_FRAME_ON_ACCESS_PORT_DROP},\ + {"OFFSET_TRILL_ERRORS_DROP", BCMPKT_TRACE_COUNTER_OFFSET_TRILL_ERRORS_DROP},\ + {"OFFSET_TRILL_RBRIDGE_LOOKUP_MISS_DROP", BCMPKT_TRACE_COUNTER_OFFSET_TRILL_RBRIDGE_LOOKUP_MISS_DROP},\ + {"OFFSET_TRILL_HOPCOUNT_CHECK_FAIL", BCMPKT_TRACE_COUNTER_OFFSET_TRILL_HOPCOUNT_CHECK_FAIL},\ + {"OFFSET_TRILL_RPF_CHECK_FAIL_DROP", BCMPKT_TRACE_COUNTER_OFFSET_TRILL_RPF_CHECK_FAIL_DROP},\ + {"IRVOQFC", BCMPKT_TRACE_COUNTER_IRVOQFC},\ + {"ECMP_NOT_RESOLVED", BCMPKT_TRACE_COUNTER_ECMP_NOT_RESOLVED},\ + {"PT_SINK_DROP", BCMPKT_TRACE_COUNTER_PT_SINK_DROP},\ + {"trace counter count", BCMPKT_TRACE_COUNTER_COUNT} + +#endif /*! BCMPKT_TRACE_COUNTER_DEFS_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd.h new file mode 100644 index 0000000..fd61bf8 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd.h @@ -0,0 +1,174 @@ +/*! \file bcmpkt_txpmd.h + * + * TX Packet MetaData (TXPMD, called SOBMH in hardware) access interface. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_TXPMD_H +#define BCMPKT_TXPMD_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#include +#endif +#include +#include +#include + +/*! TX Packet MetaData size (bytes). */ +#define BCMPKT_TXPMD_SIZE_BYTES 16 +/*! TX Packet MetaData size (words). */ +#define BCMPKT_TXPMD_SIZE_WORDS 4 + +/*! + * \name TXPMD Dump flags. (deprecated by BCMPKT_DUMP_F_XXX) + * \anchor BCMPKT_TXPMD_DUMP_F_XXX + */ +/*! \{ */ +/*! + * Dump all fields contents. + */ +#define BCMPKT_TXPMD_DUMP_F_ALL 0 +/*! + * Dump non-zero field content only. + */ +#define BCMPKT_TXPMD_DUMP_F_NONE_ZERO 1 +/*! \} */ + +/*! \brief TXPMD field ID supported bit array. + * Array of bits indicating whether a TXPMD field ID is supported by a given + * device type. + */ +typedef struct bcmpkt_txpmd_fid_support_s { + /*! Field ID bitmap container */ + SHR_BITDCLNAME(fbits, BCMPKT_TXPMD_FID_COUNT); +} bcmpkt_txpmd_fid_support_t; + +/*! + * \name Utility macros for \ref bcmpkt_txpmd_fid_support_t. + * \anchor BCMPKT_TXPMD_SUPPORT_OPS + */ +/*! \{ */ +/*! + * Macro to get a field ID's supported status. + * + * \retval zero Not supported + * \retval non-zero Supported + */ +#define BCMPKT_TXPMD_FID_SUPPORT_GET(_support, _fid) \ + SHR_BITGET(((_support).fbits), (_fid)) + +/*! + * Iterate over all supported TXPMD field IDs in the \c _support. + */ +#define BCMPKT_TXPMD_FID_SUPPORT_ITER(_support, _fid) \ + for(_fid = 0; _fid < BCMPKT_TXPMD_FID_COUNT; _fid++) \ + if(BCMPKT_TXPMD_FID_SUPPORT_GET(_support, _fid)) +/*! \} */ + +/*! + * \brief Get TXPMD's size for a given device type. + * + * \param [in] dev_type Device type. + * \param [out] len Bytes of TXPMD length. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Unsupported device type or bad \c len pointer. + * \retval SHR_E_UNAVAIL Not support TXPMD get function. + */ +extern int +bcmpkt_txpmd_len_get(bcmdrd_dev_type_t dev_type, uint32_t *len); + +/*! + * \brief Get field name for a given TXPMD field ID. + * + * \param [in] fid TXPMD field ID, refer to \ref BCMPKT_TXPMD_XXX. + * \param [out] name TXPMD field name string. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + */ +extern int +bcmpkt_txpmd_field_name_get(int fid, char **name); + +/*! + * \brief Get field ID for a given TXPMD field name. + * + * \param [in] name TXPMD name string. + * \param [out] fid TXPMD Field ID. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_NOT_FOUND Not found the name. + */ +extern int +bcmpkt_txpmd_field_id_get(char* name, int *fid); + +/*! + * \brief Get supported TXPMD field IDs for a given device type. + * + * This function returns a structure with information about the TXPMD field IDs + * a given device type supports. + * + * Use \ref BCMPKT_TXPMD_FID_SUPPORT_GET on the returned structure to get the + * supported status of a specific field ID. + * + * \param [in] dev_type Device type. + * \param [out] support Field ID supported status bitmap. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_INTERNAL API internal error. + */ +extern int +bcmpkt_txpmd_fid_support_get(bcmdrd_dev_type_t dev_type, + bcmpkt_txpmd_fid_support_t *support); + +/*! + * \brief Get view info for a given TXPMD field ID for a given device type. + * + * \param [in] dev_type Device type. + * \param [in] fid TXPMD field ID, refer to \ref BCMPKT_TXPMD_XXX. + * \param [out] view TXPMD view info. -2 for unsupported, -1 for global, + * others for view's value of \ref BCMPKT_TXPMD_HEADER_TYPE_XXX. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_INTERNAL API internal error. + */ +extern int +bcmpkt_txpmd_fid_view_get(bcmdrd_dev_type_t dev_type, + int fid, int *view); + +#endif /* BCMPKT_TXPMD_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd_defs.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd_defs.h new file mode 100644 index 0000000..4680523 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd_defs.h @@ -0,0 +1,823 @@ +#ifndef BCMPKT_TXPMD_DEFS_H +#define BCMPKT_TXPMD_DEFS_H +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * Tool: INTERNAL/regs/xgs/generate-pmd.pl + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides field macros for the TX Packet MetaData (TXPMD, called + * SOBMH in hardware.) access. + * + ******************************************************************************/ + +/*! + * \name TX packet metadata field IDs. + * \anchor BCMPKT_TXPMD_XXX + */ +/*! \{ */ +/*! Invalid BCMPKT_TXPMD FID indicator */ +#define BCMPKT_TXPMD_FID_INVALID -1 +/*! Start of frame indicator. */ +#define BCMPKT_TXPMD_START 0 +/*! + * 64 Header Types Supported. 1 means Packets from CPU with SOBMH header format + * to Passthru NLF + */ +#define BCMPKT_TXPMD_HEADER_TYPE 1 +/*! PKT_LENGTH (set by hardware - in Iarb). */ +#define BCMPKT_TXPMD_PKT_LENGTH 2 +/*! Pointer to cell buffer of this SOBMH cell. (Set by hardware) */ +#define BCMPKT_TXPMD_IPCF_PTR 3 +/*! SOP indicator (set by hardware - in Iarb). */ +#define BCMPKT_TXPMD_SOP 4 +/*! EOP indicator (set by hardware - in Iarb). */ +#define BCMPKT_TXPMD_EOP 5 +/*! CELL_LENGTH (set by hardware - in Iarb). */ +#define BCMPKT_TXPMD_CELL_LENGTH 6 +/*! CELL_ERROR or PURGE */ +#define BCMPKT_TXPMD_CELL_ERROR 7 +/*! Indicates the local port to send a SOBMH packet out. */ +#define BCMPKT_TXPMD_LOCAL_DEST_PORT 8 +/*! Source module ID, must be programmed to MY_MODID. */ +#define BCMPKT_TXPMD_SRC_MODID 9 +/*! + * Class of service for MMU queueing for this packet - sets COS values, + * PBI.UC_COS, PBI.MC_COS1, and PBI.MC_COS2. + */ +#define BCMPKT_TXPMD_COS 10 +/*! Traffic priority to be applied to MMU via PBI.INPUT_PRIORITY. */ +#define BCMPKT_TXPMD_INPUT_PRI 11 +/*! Indicates that PBI.UNICAST should be set to queue as unicast packet. */ +#define BCMPKT_TXPMD_UNICAST 12 +/*! Value for CCBI.RSQ_Q_NUM. */ +#define BCMPKT_TXPMD_RQE_Q_NUM 13 +/*! Indicates that PBI.L2_BITMAP should be set (to queue as L2MC packet). */ +#define BCMPKT_TXPMD_SET_L2BM 14 +/*! ONE STEP TIME STAMPING ENABLE */ +#define BCMPKT_TXPMD_IEEE1588_ONE_STEP_ENABLE 15 +/*! Regenerate UDP Checksum */ +#define BCMPKT_TXPMD_IEEE1588_REGEN_UDP_CHECKSUM 16 +/*! ITS_SIGN bit */ +#define BCMPKT_TXPMD_IEEE1588_INGRESS_TIMESTAMP_SIGN 17 +/*! HDR_OFFSET */ +#define BCMPKT_TXPMD_IEEE1588_TIMESTAMP_HDR_OFFSET 18 +/*! + * Indicates for TS packet transmitted from CPU into IP that the outgoing packet + * needs to have its transmit timestamp captured by the port. + */ +#define BCMPKT_TXPMD_TX_TS 19 +/*! For PBI.SPID_Override */ +#define BCMPKT_TXPMD_SPID_OVERRIDE 20 +/*! For PBI.SPID - Service Pool ID */ +#define BCMPKT_TXPMD_SPID 21 +/*! For PBI.SPAP - Service Pool Priority (color) */ +#define BCMPKT_TXPMD_SPAP 22 +/*! Will set CCBI_B.UNICAST_PKT */ +#define BCMPKT_TXPMD_UNICAST_PKT 23 +/*! Timestamp action LSB. */ +#define BCMPKT_TXPMD_TS_ACTION_LSB 24 +/*! Timestamp action MSB. */ +#define BCMPKT_TXPMD_TS_ACTION_MSB 25 +/*! Time statmp type. Encodings are 0-NTP TOD(64 bit), 1-PTP TOD(64bit) */ +#define BCMPKT_TXPMD_TS_TYPE 26 +/*! Destination subport number */ +#define BCMPKT_TXPMD_DST_SUBPORT_NUM 27 +/*! Enable UDP incremental checksum */ +#define BCMPKT_TXPMD_UDP_CHECKSUM_UPDATE_ENABLE 28 +/*! Offset to UDP checksum field from start of MACS-SA. */ +#define BCMPKT_TXPMD_UDP_CHECKSUM_OFFSET 29 +/*! CNG Field. */ +#define BCMPKT_TXPMD_CNG 30 +/*! DESTINATION Field. */ +#define BCMPKT_TXPMD_DESTINATION 31 +/*! Destination Field Type. */ +#define BCMPKT_TXPMD_DESTINATION_TYPE 32 +/*! WRED Mark Eligible field. */ +#define BCMPKT_TXPMD_WRED_MARK_ELIGIBLE 33 +/*! WRED Response Field. */ +#define BCMPKT_TXPMD_WRED_RESPONSE 34 +/*! Allows software to select load balancing bitmap for non-unicast packets. */ +#define BCMPKT_TXPMD_CPU_TX_MCAST_LB_INDEX 35 +/*! ECMP member ID for case where DESTINATION_TYPE=ECMP_MEMBER. Only valid for single level ECMP */ +#define BCMPKT_TXPMD_CPU_TX_ECMP_MEMBER_ID 36 +/*! Destination Field. */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION 37 +/*! Destination Field Type. */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_TYPE 38 +/*! Drop Precedence. */ +#define BCMPKT_TXPMD_CPU_TX_DP 39 +/*! Traffic priority to be applied to MMU via PBI.INPUT_PRIORITY. */ +#define BCMPKT_TXPMD_CPU_TX_INPUT_PRI 40 +/*! Internal congestion. */ +#define BCMPKT_TXPMD_CPU_TX_INT_CN 41 +/*! Internal priority */ +#define BCMPKT_TXPMD_CPU_TX_INT_PRI 42 +/*! Load balancing bitmap is valid indication. */ +#define BCMPKT_TXPMD_CPU_TX_MCAST_LB_INDEX_VLD 43 +/*! Pointer to CPU_PACKET_PROFILE_1/2 registers. */ +#define BCMPKT_TXPMD_CPU_TX_PKT_PROFILE 44 +/*! QoS fields (INT_PRI, DP, INT_CN) valid indication. */ +#define BCMPKT_TXPMD_CPU_TX_QOS_FIELDS_VLD 45 +/*! If set packet marked as Layer 3 routed. */ +#define BCMPKT_TXPMD_CPU_TX_ROUTED_PKT 46 +/*! Indicates that PBI.UNICAST should be set to queue as unicast packet. */ +#define BCMPKT_TXPMD_CPU_TX_UNICAST 47 +/*! SOP indication. */ +#define BCMPKT_TXPMD_CPU_TX_SOP 48 +/*! VRF ID. */ +#define BCMPKT_TXPMD_CPU_TX_VRF 49 +/*! VRF ID is valid. */ +#define BCMPKT_TXPMD_CPU_TX_VRF_VALID 50 +/*! WCMP Selection. */ +#define BCMPKT_TXPMD_CPU_TX_WCMP_SEL 51 +/*! Cell error. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_CELL_ERROR 52 +/*! Cell length. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_CELL_LENGTH 53 +/*! Class of service. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_COS 54 +/*! Destination. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_DESTINATION 55 +/*! Destination type. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_DESTINATION_TYPE 56 +/*! EOP indicator. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_EOP 57 +/*! Input priority. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_INPUT_PRI 58 +/*! LM counter action. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION 59 +/*! LM counter ID. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ID 60 +/*! OAM replacement offset. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_OAM_REPLACEMENT_OFFSET 61 +/*! Packet length. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_PKT_LENGTH 62 +/*! RQE Queue Number. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_RQE_Q_NUM 63 +/*! SOP indicator. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_SOP 64 +/*! Service Pool Allocation Precedence. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_SPAP 65 +/*! Service Pool ID. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_SPID 66 +/*! For Service Pool ID override. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_SPID_OVERRIDE 67 +/*! Source module ID. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_SRC_MODID 68 +/*! Timestamp action. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_TIMESTAMP_ACTION 69 +/*! Unicast packet. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_UNICAST 70 +/*! Indicates a copy should be sent to the the CPU port mapped to R5. */ +#define BCMPKT_TXPMD_COPY_TO_DEBUG 71 +/*! Copy-to-CPU packet. */ +#define BCMPKT_TXPMD_COPY_TO_CPU 72 +/*! Used to set PBI.WRED_RESPONSIVE */ +#define BCMPKT_TXPMD_WRED_RESPONSIVE 73 +/*! Cookie correspoding to 1588 2-step */ +#define BCMPKT_TXPMD_CPU_TX_COOKIE 74 +/*! Validates Cookie field */ +#define BCMPKT_TXPMD_CPU_TX_COOKIE_VALID 75 +/*! The 8 LSB bits of Cookie corresponding to 1588 2-Step */ +#define BCMPKT_TXPMD_COOKIE_7_0 76 +/*! The MSB of Cookie corresponding to 1588 2-Step */ +#define BCMPKT_TXPMD_COOKIE_8 77 +/*! Unicast packet type. */ +#define BCMPKT_TXPMD_AUX_SOBMH_UNICAST_PKT 78 +/*! vpp_port to send a SOBMH packet out. */ +#define BCMPKT_TXPMD_AUX_SOBMH_TX_VPP_PORT 79 +/*! Destination chip_port number. */ +#define BCMPKT_TXPMD_AUX_SOBMH_TX_CHIP_PORT 80 +/*! RX chip port. */ +#define BCMPKT_TXPMD_AUX_SOBMH_RX_CHIP_PORT 81 +/*! SVP */ +#define BCMPKT_TXPMD_CPU_TX_SVP 82 +/*! Switch packet copy is accepted. */ +#define BCMPKT_TXPMD_SWITCH_COPY 83 +/*! Switch packet copy type. */ +#define BCMPKT_TXPMD_SWITCH_COPY_TYPE 84 +/*! Destination port of switch packet copy. */ +#define BCMPKT_TXPMD_SWITCH_COPY_DEST_PORT 85 +/*! Queue number of the switch packet copy. */ +#define BCMPKT_TXPMD_SWITCH_COPY_COS 86 +/*! Adaptive routing group. */ +#define BCMPKT_TXPMD_CPU_TX_AR_GROUP 87 +/*! INCA group ID. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_GROUP_ID 88 +/*! INCA collective ID. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_COLLECTIVE_ID 89 +/*! INCA internal QP ID. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_INTERNAL_QP_ID 90 +/*! INCA source host profile. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_SRC_HOST_PROFILE 91 +/*! INCA flow type. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_FLOW_TYPE 92 +/*! INCA Reduction required: 0 : Reduction not required (Broadcast), 1 : Reduction required (AllReduce/Reduce) */ +#define BCMPKT_TXPMD_CPU_TX_INCA_REDN_REQD 93 +/*! INCA Replication required: 0 : Replication not required (Reduce), 1 : Replication required (AllReduce/Broadcast) */ +#define BCMPKT_TXPMD_CPU_TX_INCA_REPL_REQD 94 +/*! INCA Second pass destination. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_SECOND_PASS_DEST 95 +/*! + * Operation type. 0-Sum, 1-Sum and Scale, 2-15 - Reserved. + * Valid only when the INCA_REDN_REQD==1 where INCA reduction is required. + * This field is consumed by ICE and not carried beyond to second pass. + */ +#define BCMPKT_TXPMD_CPU_TX_INCA_ICE_OPER_TYPE 96 +/*! Vlan profile. */ +#define BCMPKT_TXPMD_CPU_TX_VLAN_PROFILE 97 +/*! Forwarding profile. */ +#define BCMPKT_TXPMD_CPU_TX_FWD_PROFILE 98 +/*! Data format. Valid only when INCA_REDN_REQD==1 where INCA reduction is required. This field is consumed by ICE and not carried beyond to second pass. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT 99 +/*! Indicates the offset at 2B granularity from beginning of the pkt to the start of INCA DATA for reduction.Valid only when INCA_REDN_REQD==1 where INCA reduction is required. This is consumed by IDN and not carried beyond to second pass. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_OFFSET 100 +/*! CNG field. */ +#define BCMPKT_TXPMD_CPU_TX_CNG 101 +/*! Packet Entropy. */ +#define BCMPKT_TXPMD_CPU_TX_PACKET_ENTROPY 102 +/*! Source port number. */ +#define BCMPKT_TXPMD_CPU_TX_SRC_PORT_NUM 103 +/*! Packet control profile. */ +#define BCMPKT_TXPMD_CPU_TX_PKT_CTRL_PROFILE 104 +/*! Queue number. */ +#define BCMPKT_TXPMD_CPU_TX_COS 105 +/*! Internal priority valid. */ +#define BCMPKT_TXPMD_CPU_TX_INT_PRI_VALID 106 +/*! CNG vaild. */ +#define BCMPKT_TXPMD_CPU_TX_CNG_VALID 107 +/*! Internal congestion valid. */ +#define BCMPKT_TXPMD_CPU_TX_INT_CN_VALID 108 +/*! Input priority valid. */ +#define BCMPKT_TXPMD_CPU_TX_INPUT_PRI_VALID 109 +/*! COS valid. */ +#define BCMPKT_TXPMD_CPU_TX_COS_VALID 110 +/*! CPU Tx Type. */ +#define BCMPKT_TXPMD_CPU_TX_CPU_TX_TYPE 111 +/*! DOP Trigger. */ +#define BCMPKT_TXPMD_CPU_TX_DOP_TRIGGER 112 +/*! Aux to LPP class ID. */ +#define BCMPKT_TXPMD_CPU_TX_VPP_TO_LPP_CLASS_ID 113 +/*! Cell length */ +#define BCMPKT_TXPMD_AUX_SOBMH_CELL_LENGTH 114 +/*! End of Packet indication. */ +#define BCMPKT_TXPMD_AUX_SOBMH_EOP 115 +/*! Start of packet indication. */ +#define BCMPKT_TXPMD_AUX_SOBMH_SOP 116 +/*! Packet length. */ +#define BCMPKT_TXPMD_AUX_SOBMH_PKT_LENGTH 117 +/*! Copy to CPU. */ +#define BCMPKT_TXPMD_AUX_SOBMH_COPY_TO_CPU 118 +/*! Copy to debug. */ +#define BCMPKT_TXPMD_AUX_SOBMH_COPY_TO_DEBUG 119 +/*! CNG field. */ +#define BCMPKT_TXPMD_AUX_SOBMH_CNG 120 +/*! Queue number. */ +#define BCMPKT_TXPMD_AUX_SOBMH_COS 121 +/*! Indicates that PBI.UNICAST should be set to queue as unicast packet. */ +#define BCMPKT_TXPMD_AUX_SOBMH_UNICAST 122 +/*! Indicates that PBI.L2_BITMAP should be set (to queue as L2MC packet). */ +#define BCMPKT_TXPMD_AUX_SOBMH_SET_L2BM 123 +/*! RQE queue number. */ +#define BCMPKT_TXPMD_AUX_SOBMH_RQE_Q_NUM 124 +/*! Input priority. */ +#define BCMPKT_TXPMD_AUX_SOBMH_INPUT_PRI 125 +/*! Cell error indication. */ +#define BCMPKT_TXPMD_AUX_SOBMH_CELL_ERROR 126 +/*! Header type. */ +#define BCMPKT_TXPMD_AUX_SOBMH_HEADER_TYPE 127 +/*! Start of frame indicator. */ +#define BCMPKT_TXPMD_AUX_SOBMH_START 128 +/*! TXPMD FIELD ID NUMBER */ +#define BCMPKT_TXPMD_FID_COUNT 129 +/*! \} */ + +/*! TXPMD field name strings for debugging. */ +#define BCMPKT_TXPMD_FIELD_NAME_MAP_INIT \ + {"START", BCMPKT_TXPMD_START},\ + {"HEADER_TYPE", BCMPKT_TXPMD_HEADER_TYPE},\ + {"PKT_LENGTH", BCMPKT_TXPMD_PKT_LENGTH},\ + {"IPCF_PTR", BCMPKT_TXPMD_IPCF_PTR},\ + {"SOP", BCMPKT_TXPMD_SOP},\ + {"EOP", BCMPKT_TXPMD_EOP},\ + {"CELL_LENGTH", BCMPKT_TXPMD_CELL_LENGTH},\ + {"CELL_ERROR", BCMPKT_TXPMD_CELL_ERROR},\ + {"LOCAL_DEST_PORT", BCMPKT_TXPMD_LOCAL_DEST_PORT},\ + {"SRC_MODID", BCMPKT_TXPMD_SRC_MODID},\ + {"COS", BCMPKT_TXPMD_COS},\ + {"INPUT_PRI", BCMPKT_TXPMD_INPUT_PRI},\ + {"UNICAST", BCMPKT_TXPMD_UNICAST},\ + {"RQE_Q_NUM", BCMPKT_TXPMD_RQE_Q_NUM},\ + {"SET_L2BM", BCMPKT_TXPMD_SET_L2BM},\ + {"IEEE1588_ONE_STEP_ENABLE", BCMPKT_TXPMD_IEEE1588_ONE_STEP_ENABLE},\ + {"IEEE1588_REGEN_UDP_CHECKSUM", BCMPKT_TXPMD_IEEE1588_REGEN_UDP_CHECKSUM},\ + {"IEEE1588_INGRESS_TIMESTAMP_SIGN", BCMPKT_TXPMD_IEEE1588_INGRESS_TIMESTAMP_SIGN},\ + {"IEEE1588_TIMESTAMP_HDR_OFFSET", BCMPKT_TXPMD_IEEE1588_TIMESTAMP_HDR_OFFSET},\ + {"TX_TS", BCMPKT_TXPMD_TX_TS},\ + {"SPID_OVERRIDE", BCMPKT_TXPMD_SPID_OVERRIDE},\ + {"SPID", BCMPKT_TXPMD_SPID},\ + {"SPAP", BCMPKT_TXPMD_SPAP},\ + {"UNICAST_PKT", BCMPKT_TXPMD_UNICAST_PKT},\ + {"TS_ACTION_LSB", BCMPKT_TXPMD_TS_ACTION_LSB},\ + {"TS_ACTION_MSB", BCMPKT_TXPMD_TS_ACTION_MSB},\ + {"TS_TYPE", BCMPKT_TXPMD_TS_TYPE},\ + {"DST_SUBPORT_NUM", BCMPKT_TXPMD_DST_SUBPORT_NUM},\ + {"UDP_CHECKSUM_UPDATE_ENABLE", BCMPKT_TXPMD_UDP_CHECKSUM_UPDATE_ENABLE},\ + {"UDP_CHECKSUM_OFFSET", BCMPKT_TXPMD_UDP_CHECKSUM_OFFSET},\ + {"CNG", BCMPKT_TXPMD_CNG},\ + {"DESTINATION", BCMPKT_TXPMD_DESTINATION},\ + {"DESTINATION_TYPE", BCMPKT_TXPMD_DESTINATION_TYPE},\ + {"WRED_MARK_ELIGIBLE", BCMPKT_TXPMD_WRED_MARK_ELIGIBLE},\ + {"WRED_RESPONSE", BCMPKT_TXPMD_WRED_RESPONSE},\ + {"CPU_TX::MCAST_LB_INDEX", BCMPKT_TXPMD_CPU_TX_MCAST_LB_INDEX},\ + {"CPU_TX::ECMP_MEMBER_ID", BCMPKT_TXPMD_CPU_TX_ECMP_MEMBER_ID},\ + {"CPU_TX::DESTINATION", BCMPKT_TXPMD_CPU_TX_DESTINATION},\ + {"CPU_TX::DESTINATION_TYPE", BCMPKT_TXPMD_CPU_TX_DESTINATION_TYPE},\ + {"CPU_TX::DP", BCMPKT_TXPMD_CPU_TX_DP},\ + {"CPU_TX::INPUT_PRI", BCMPKT_TXPMD_CPU_TX_INPUT_PRI},\ + {"CPU_TX::INT_CN", BCMPKT_TXPMD_CPU_TX_INT_CN},\ + {"CPU_TX::INT_PRI", BCMPKT_TXPMD_CPU_TX_INT_PRI},\ + {"CPU_TX::MCAST_LB_INDEX_VLD", BCMPKT_TXPMD_CPU_TX_MCAST_LB_INDEX_VLD},\ + {"CPU_TX::PKT_PROFILE", BCMPKT_TXPMD_CPU_TX_PKT_PROFILE},\ + {"CPU_TX::QOS_FIELDS_VLD", BCMPKT_TXPMD_CPU_TX_QOS_FIELDS_VLD},\ + {"CPU_TX::ROUTED_PKT", BCMPKT_TXPMD_CPU_TX_ROUTED_PKT},\ + {"CPU_TX::UNICAST", BCMPKT_TXPMD_CPU_TX_UNICAST},\ + {"CPU_TX::SOP", BCMPKT_TXPMD_CPU_TX_SOP},\ + {"CPU_TX::VRF", BCMPKT_TXPMD_CPU_TX_VRF},\ + {"CPU_TX::VRF_VALID", BCMPKT_TXPMD_CPU_TX_VRF_VALID},\ + {"CPU_TX::WCMP_SEL", BCMPKT_TXPMD_CPU_TX_WCMP_SEL},\ + {"OAM_DOWNMEP_TX::CELL_ERROR", BCMPKT_TXPMD_OAM_DOWNMEP_TX_CELL_ERROR},\ + {"OAM_DOWNMEP_TX::CELL_LENGTH", BCMPKT_TXPMD_OAM_DOWNMEP_TX_CELL_LENGTH},\ + {"OAM_DOWNMEP_TX::COS", BCMPKT_TXPMD_OAM_DOWNMEP_TX_COS},\ + {"OAM_DOWNMEP_TX::DESTINATION", BCMPKT_TXPMD_OAM_DOWNMEP_TX_DESTINATION},\ + {"OAM_DOWNMEP_TX::DESTINATION_TYPE", BCMPKT_TXPMD_OAM_DOWNMEP_TX_DESTINATION_TYPE},\ + {"OAM_DOWNMEP_TX::EOP", BCMPKT_TXPMD_OAM_DOWNMEP_TX_EOP},\ + {"OAM_DOWNMEP_TX::INPUT_PRI", BCMPKT_TXPMD_OAM_DOWNMEP_TX_INPUT_PRI},\ + {"OAM_DOWNMEP_TX::LM_COUNTER_ACTION", BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION},\ + {"OAM_DOWNMEP_TX::LM_COUNTER_ID", BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ID},\ + {"OAM_DOWNMEP_TX::OAM_REPLACEMENT_OFFSET", BCMPKT_TXPMD_OAM_DOWNMEP_TX_OAM_REPLACEMENT_OFFSET},\ + {"OAM_DOWNMEP_TX::PKT_LENGTH", BCMPKT_TXPMD_OAM_DOWNMEP_TX_PKT_LENGTH},\ + {"OAM_DOWNMEP_TX::RQE_Q_NUM", BCMPKT_TXPMD_OAM_DOWNMEP_TX_RQE_Q_NUM},\ + {"OAM_DOWNMEP_TX::SOP", BCMPKT_TXPMD_OAM_DOWNMEP_TX_SOP},\ + {"OAM_DOWNMEP_TX::SPAP", BCMPKT_TXPMD_OAM_DOWNMEP_TX_SPAP},\ + {"OAM_DOWNMEP_TX::SPID", BCMPKT_TXPMD_OAM_DOWNMEP_TX_SPID},\ + {"OAM_DOWNMEP_TX::SPID_OVERRIDE", BCMPKT_TXPMD_OAM_DOWNMEP_TX_SPID_OVERRIDE},\ + {"OAM_DOWNMEP_TX::SRC_MODID", BCMPKT_TXPMD_OAM_DOWNMEP_TX_SRC_MODID},\ + {"OAM_DOWNMEP_TX::TIMESTAMP_ACTION", BCMPKT_TXPMD_OAM_DOWNMEP_TX_TIMESTAMP_ACTION},\ + {"OAM_DOWNMEP_TX::UNICAST", BCMPKT_TXPMD_OAM_DOWNMEP_TX_UNICAST},\ + {"COPY_TO_DEBUG", BCMPKT_TXPMD_COPY_TO_DEBUG},\ + {"COPY_TO_CPU", BCMPKT_TXPMD_COPY_TO_CPU},\ + {"WRED_RESPONSIVE", BCMPKT_TXPMD_WRED_RESPONSIVE},\ + {"CPU_TX::COOKIE", BCMPKT_TXPMD_CPU_TX_COOKIE},\ + {"CPU_TX::COOKIE_VALID", BCMPKT_TXPMD_CPU_TX_COOKIE_VALID},\ + {"COOKIE_7_0", BCMPKT_TXPMD_COOKIE_7_0},\ + {"COOKIE_8", BCMPKT_TXPMD_COOKIE_8},\ + {"AUX_SOBMH::UNICAST_PKT", BCMPKT_TXPMD_AUX_SOBMH_UNICAST_PKT},\ + {"AUX_SOBMH::TX_VPP_PORT", BCMPKT_TXPMD_AUX_SOBMH_TX_VPP_PORT},\ + {"AUX_SOBMH::TX_CHIP_PORT", BCMPKT_TXPMD_AUX_SOBMH_TX_CHIP_PORT},\ + {"AUX_SOBMH::RX_CHIP_PORT", BCMPKT_TXPMD_AUX_SOBMH_RX_CHIP_PORT},\ + {"CPU_TX::SVP", BCMPKT_TXPMD_CPU_TX_SVP},\ + {"SWITCH_COPY", BCMPKT_TXPMD_SWITCH_COPY},\ + {"SWITCH_COPY_TYPE", BCMPKT_TXPMD_SWITCH_COPY_TYPE},\ + {"SWITCH_COPY_DEST_PORT", BCMPKT_TXPMD_SWITCH_COPY_DEST_PORT},\ + {"SWITCH_COPY_COS", BCMPKT_TXPMD_SWITCH_COPY_COS},\ + {"CPU_TX::AR_GROUP", BCMPKT_TXPMD_CPU_TX_AR_GROUP},\ + {"CPU_TX::INCA_GROUP_ID", BCMPKT_TXPMD_CPU_TX_INCA_GROUP_ID},\ + {"CPU_TX::INCA_COLLECTIVE_ID", BCMPKT_TXPMD_CPU_TX_INCA_COLLECTIVE_ID},\ + {"CPU_TX::INCA_INTERNAL_QP_ID", BCMPKT_TXPMD_CPU_TX_INCA_INTERNAL_QP_ID},\ + {"CPU_TX::INCA_SRC_HOST_PROFILE", BCMPKT_TXPMD_CPU_TX_INCA_SRC_HOST_PROFILE},\ + {"CPU_TX::INCA_FLOW_TYPE", BCMPKT_TXPMD_CPU_TX_INCA_FLOW_TYPE},\ + {"CPU_TX::INCA_REDN_REQD", BCMPKT_TXPMD_CPU_TX_INCA_REDN_REQD},\ + {"CPU_TX::INCA_REPL_REQD", BCMPKT_TXPMD_CPU_TX_INCA_REPL_REQD},\ + {"CPU_TX::INCA_SECOND_PASS_DEST", BCMPKT_TXPMD_CPU_TX_INCA_SECOND_PASS_DEST},\ + {"CPU_TX::INCA_ICE_OPER_TYPE", BCMPKT_TXPMD_CPU_TX_INCA_ICE_OPER_TYPE},\ + {"CPU_TX::VLAN_PROFILE", BCMPKT_TXPMD_CPU_TX_VLAN_PROFILE},\ + {"CPU_TX::FWD_PROFILE", BCMPKT_TXPMD_CPU_TX_FWD_PROFILE},\ + {"CPU_TX::INCA_ICE_DATA_FORMAT", BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT},\ + {"CPU_TX::INCA_ICE_DATA_OFFSET", BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_OFFSET},\ + {"CPU_TX::CNG", BCMPKT_TXPMD_CPU_TX_CNG},\ + {"CPU_TX::PACKET_ENTROPY", BCMPKT_TXPMD_CPU_TX_PACKET_ENTROPY},\ + {"CPU_TX::SRC_PORT_NUM", BCMPKT_TXPMD_CPU_TX_SRC_PORT_NUM},\ + {"CPU_TX::PKT_CTRL_PROFILE", BCMPKT_TXPMD_CPU_TX_PKT_CTRL_PROFILE},\ + {"CPU_TX::COS", BCMPKT_TXPMD_CPU_TX_COS},\ + {"CPU_TX::INT_PRI_VALID", BCMPKT_TXPMD_CPU_TX_INT_PRI_VALID},\ + {"CPU_TX::CNG_VALID", BCMPKT_TXPMD_CPU_TX_CNG_VALID},\ + {"CPU_TX::INT_CN_VALID", BCMPKT_TXPMD_CPU_TX_INT_CN_VALID},\ + {"CPU_TX::INPUT_PRI_VALID", BCMPKT_TXPMD_CPU_TX_INPUT_PRI_VALID},\ + {"CPU_TX::COS_VALID", BCMPKT_TXPMD_CPU_TX_COS_VALID},\ + {"CPU_TX::CPU_TX_TYPE", BCMPKT_TXPMD_CPU_TX_CPU_TX_TYPE},\ + {"CPU_TX::DOP_TRIGGER", BCMPKT_TXPMD_CPU_TX_DOP_TRIGGER},\ + {"CPU_TX::VPP_TO_LPP_CLASS_ID", BCMPKT_TXPMD_CPU_TX_VPP_TO_LPP_CLASS_ID},\ + {"AUX_SOBMH::CELL_LENGTH", BCMPKT_TXPMD_AUX_SOBMH_CELL_LENGTH},\ + {"AUX_SOBMH::EOP", BCMPKT_TXPMD_AUX_SOBMH_EOP},\ + {"AUX_SOBMH::SOP", BCMPKT_TXPMD_AUX_SOBMH_SOP},\ + {"AUX_SOBMH::PKT_LENGTH", BCMPKT_TXPMD_AUX_SOBMH_PKT_LENGTH},\ + {"AUX_SOBMH::COPY_TO_CPU", BCMPKT_TXPMD_AUX_SOBMH_COPY_TO_CPU},\ + {"AUX_SOBMH::COPY_TO_DEBUG", BCMPKT_TXPMD_AUX_SOBMH_COPY_TO_DEBUG},\ + {"AUX_SOBMH::CNG", BCMPKT_TXPMD_AUX_SOBMH_CNG},\ + {"AUX_SOBMH::COS", BCMPKT_TXPMD_AUX_SOBMH_COS},\ + {"AUX_SOBMH::UNICAST", BCMPKT_TXPMD_AUX_SOBMH_UNICAST},\ + {"AUX_SOBMH::SET_L2BM", BCMPKT_TXPMD_AUX_SOBMH_SET_L2BM},\ + {"AUX_SOBMH::RQE_Q_NUM", BCMPKT_TXPMD_AUX_SOBMH_RQE_Q_NUM},\ + {"AUX_SOBMH::INPUT_PRI", BCMPKT_TXPMD_AUX_SOBMH_INPUT_PRI},\ + {"AUX_SOBMH::CELL_ERROR", BCMPKT_TXPMD_AUX_SOBMH_CELL_ERROR},\ + {"AUX_SOBMH::HEADER_TYPE", BCMPKT_TXPMD_AUX_SOBMH_HEADER_TYPE},\ + {"AUX_SOBMH::START", BCMPKT_TXPMD_AUX_SOBMH_START},\ + {"fid count", BCMPKT_TXPMD_FID_COUNT} + +/*! + * \name BCMPKT_TXPMD_START encodings. + * \anchor BCMPKT_TXPMD_START_XXX + */ +/*! \{ */ +/*! The header used internally only */ +#define BCMPKT_TXPMD_START_INTERNAL_HEADER 2 +/*! Frame type is Higig */ +#define BCMPKT_TXPMD_START_HIGIG 3 +/*! \} */ + +/*! BCMPKT_TXPMD_START encoding name strings for debugging. */ +#define BCMPKT_TXPMD_START_NAME_MAP_INIT \ + {"RESERVED_COUNTER", 0},\ + {"RESERVED_COUNTER", 1},\ + {"INTERNAL_HEADER", BCMPKT_TXPMD_START_INTERNAL_HEADER},\ + {"HIGIG", BCMPKT_TXPMD_START_HIGIG},\ + +/*! + * \name BCMPKT_TXPMD_HEADER_TYPE encodings. + * \anchor BCMPKT_TXPMD_HEADER_TYPE_XXX + */ +/*! \{ */ +/*! EP Copy to CPU format, SOBMH header in EP to Passthru NLF */ +#define BCMPKT_TXPMD_HEADER_T_TO_CPU 0 +/*! Packets from CPU with SOBMH header format to Passthru NLF */ +#define BCMPKT_TXPMD_HEADER_T_FROM_CPU 1 +/*! Header type CPU_TX in LPP pipeline */ +#define BCMPKT_TXPMD_HEADER_T_LPP_CPU_TX 1 +/*! Header type CPU_TX */ +#define BCMPKT_TXPMD_HEADER_T_CPU_TX 2 +/*! Header type TX_MD in LPP pipeline */ +#define BCMPKT_TXPMD_HEADER_T_LPP_TX_MD_HEADER 2 +/*! MAC in MAC packets to Passthru NLF */ +#define BCMPKT_TXPMD_HEADER_T_MIM 2 +/*! Packet with SOBMH header format */ +#define BCMPKT_TXPMD_HEADER_T_LPP_SOBMH 3 +/*! MPLS packets to Passthru NLF */ +#define BCMPKT_TXPMD_HEADER_T_MPLS_PMP 3 +/*! Trill Network Packets to Passthru NLF */ +#define BCMPKT_TXPMD_HEADER_T_TRILL_NW 4 +/*! Trill Access Layer Packets to Passthru NLF */ +#define BCMPKT_TXPMD_HEADER_T_TRILL_AC 5 +/*! WLAN Decap packets sent to WRX NLF */ +#define BCMPKT_TXPMD_HEADER_T_WLAN_DECAP 6 +/*! WLAN Encap packets sent to WTX NLF */ +#define BCMPKT_TXPMD_HEADER_T_WLAN_ENCAP 7 +/*! QCN Packets to Passthru NLF */ +#define BCMPKT_TXPMD_HEADER_T_QCN 8 +/*! DPI/Signature Matcher packets sent to SM NLF */ +#define BCMPKT_TXPMD_HEADER_T_SM_DPI 9 +/*! EP Redirection packets to Passthru NLF */ +#define BCMPKT_TXPMD_HEADER_T_EP_REDIR 10 +/*! Other generic passthrough to Passthru NLF */ +#define BCMPKT_TXPMD_HEADER_T_GENERIC 11 +/*! DOWN MEP Transmit OAM Packets from CPU or CCM from HW Engine or OLP */ +#define BCMPKT_TXPMD_HEADER_T_OAM_DOWNMEP_TX 12 +/*! UP MEP Transmit OAM Packets from CPU or CCM from HW Engine or OLP */ +#define BCMPKT_TXPMD_HEADER_T_OAM_UPMEP_TX 13 +/*! \} */ + +/*! BCMPKT_TXPMD_HEADER_TYPE encoding name strings for debugging. */ +#define BCMPKT_TXPMD_HEADER_TYPE_NAME_MAP_INIT \ + {"SOBMH_EP_COPY_TO_CPU", BCMPKT_TXPMD_HEADER_T_TO_CPU},\ + {"SOBMH_FROM_CPU", BCMPKT_TXPMD_HEADER_T_FROM_CPU},\ + {"LPP_CPU_TX", BCMPKT_TXPMD_HEADER_T_LPP_CPU_TX},\ + {"CPU_TX", BCMPKT_TXPMD_HEADER_T_CPU_TX},\ + {"LPP_TX_MD_HEADER", BCMPKT_TXPMD_HEADER_T_LPP_TX_MD_HEADER},\ + {"MIM", BCMPKT_TXPMD_HEADER_T_MIM},\ + {"LPP_SOBMH", BCMPKT_TXPMD_HEADER_T_LPP_SOBMH},\ + {"MPLS_PMP", BCMPKT_TXPMD_HEADER_T_MPLS_PMP},\ + {"TRILL_NW", BCMPKT_TXPMD_HEADER_T_TRILL_NW},\ + {"TRILL_AC", BCMPKT_TXPMD_HEADER_T_TRILL_AC},\ + {"WLAN_DECAP", BCMPKT_TXPMD_HEADER_T_WLAN_DECAP},\ + {"WLAN_ENCAP", BCMPKT_TXPMD_HEADER_T_WLAN_ENCAP},\ + {"QCN", BCMPKT_TXPMD_HEADER_T_QCN},\ + {"SM_DPI", BCMPKT_TXPMD_HEADER_T_SM_DPI},\ + {"EP_REDIR", BCMPKT_TXPMD_HEADER_T_EP_REDIR},\ + {"GENERIC", BCMPKT_TXPMD_HEADER_T_GENERIC},\ + {"OAM_DOWNMEP_TX", BCMPKT_TXPMD_HEADER_T_OAM_DOWNMEP_TX},\ + {"OAM_UPMEP_TX", BCMPKT_TXPMD_HEADER_T_OAM_UPMEP_TX},\ + +/*! + * \name BCMPKT_TXPMD_DESTINATION_TYPE encodings. + * \anchor BCMPKT_TXPMD_DESTINATION_TYPE_XXX + */ +/*! \{ */ +/*! Egress Port */ +#define BCMPKT_TXPMD_DESTINATION_T_EGRESS_PORT 0 +/*! Asserts bit selected by destination field in L2_PBM */ +#define BCMPKT_TXPMD_DESTINATION_T_L2_PBM 7 +/*! Destination is Invalid */ +#define BCMPKT_TXPMD_DESTINATION_T_INVALID 15 +/*! \} */ + +/*! BCMPKT_TXPMD_DESTINATION_TYPE encoding name strings for debugging. */ +#define BCMPKT_TXPMD_DESTINATION_TYPE_NAME_MAP_INIT \ + {"EGRESS_PORT", BCMPKT_TXPMD_DESTINATION_T_EGRESS_PORT},\ + {"RESERVED_COUNTER", 1},\ + {"RESERVED_COUNTER", 2},\ + {"RESERVED_COUNTER", 3},\ + {"RESERVED_COUNTER", 4},\ + {"RESERVED_COUNTER", 5},\ + {"RESERVED_COUNTER", 6},\ + {"L2_PBM", BCMPKT_TXPMD_DESTINATION_T_L2_PBM},\ + {"RESERVED_COUNTER", 8},\ + {"RESERVED_COUNTER", 9},\ + {"RESERVED_COUNTER", 10},\ + {"RESERVED_COUNTER", 11},\ + {"RESERVED_COUNTER", 12},\ + {"RESERVED_COUNTER", 13},\ + {"RESERVED_COUNTER", 14},\ + {"INVALID", BCMPKT_TXPMD_DESTINATION_T_INVALID},\ + +/*! + * \name BCMPKT_TXPMD_CPU_TX_DESTINATION_TYPE encodings. + * \anchor BCMPKT_TXPMD_CPU_TX_DESTINATION_TYPE_XXX + */ +/*! \{ */ +/*! Egress Port */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_EGRESS_PORT 0 +/*! Destination is Invalid */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_NULL 0 +/*! Egress Port */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_DEST_PORT 1 +/*! Next Hop Index */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_NHI 1 +/*! ECMP Group */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_ECMP 2 +/*! Trunk ID */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_TGID 2 +/*! ECMP member id */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_ECMP_MEMBER 3 +/*! Next Hop Index */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_NEXT_HOP 3 +/*! IP Multicast Group */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_IPMC 4 +/*! L2MC group */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_L2MC 5 +/*! Vlan Flooding */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_VLAN_FLOOD 6 +/*! Asserts bit selected by destination field in L2_PBM */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_L2_PBM 7 +/*! LAG ID */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_LAG_ID 8 +/*! Forward and derive destination normally */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_FORWARD 15 +/*! Destination is Invalid */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_T_INVALID 15 +/*! \} */ + +/*! BCMPKT_TXPMD_CPU_TX_DESTINATION_TYPE encoding name strings for debugging. */ +#define BCMPKT_TXPMD_CPU_TX_DESTINATION_TYPE_NAME_MAP_INIT \ + {"EGRESS_PORT", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_EGRESS_PORT},\ + {"NULL", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_NULL},\ + {"DEST_PORT", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_DEST_PORT},\ + {"NHI", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_NHI},\ + {"ECMP", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_ECMP},\ + {"TGID", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_TGID},\ + {"ECMP_MEMBER", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_ECMP_MEMBER},\ + {"NEXT_HOP", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_NEXT_HOP},\ + {"IPMC", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_IPMC},\ + {"L2MC", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_L2MC},\ + {"VLAN_FLOOD", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_VLAN_FLOOD},\ + {"L2_PBM", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_L2_PBM},\ + {"LAG_ID", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_LAG_ID},\ + {"RESERVED_COUNTER", 13},\ + {"RESERVED_COUNTER", 14},\ + {"FORWARD", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_FORWARD},\ + {"INVALID", BCMPKT_TXPMD_CPU_TX_DESTINATION_T_INVALID},\ + +/*! + * \name BCMPKT_TXPMD_CPU_TX_DP encodings. + * \anchor BCMPKT_TXPMD_CPU_TX_DP_XXX + */ +/*! \{ */ +/*! Green */ +#define BCMPKT_TXPMD_CPU_TX_DP_GREEN 0 +/*! Red */ +#define BCMPKT_TXPMD_CPU_TX_DP_RED 1 +/*! Yellow */ +#define BCMPKT_TXPMD_CPU_TX_DP_YELLOW 3 +/*! \} */ + +/*! BCMPKT_TXPMD_CPU_TX_DP encoding name strings for debugging. */ +#define BCMPKT_TXPMD_CPU_TX_DP_NAME_MAP_INIT \ + {"GREEN", BCMPKT_TXPMD_CPU_TX_DP_GREEN},\ + {"RED", BCMPKT_TXPMD_CPU_TX_DP_RED},\ + {"RESERVED_COUNTER", 2},\ + {"YELLOW", BCMPKT_TXPMD_CPU_TX_DP_YELLOW},\ + +/*! + * \name BCMPKT_TXPMD_OAM_DOWNMEP_TX_DESTINATION_TYPE encodings. + * \anchor BCMPKT_TXPMD_OAM_DOWNMEP_TX_DESTINATION_TYPE_XXX + */ +/*! \{ */ +/*! Egress Port */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_DESTINATION_T_EGRESS_PORT 0 +/*! \} */ + +/*! BCMPKT_TXPMD_OAM_DOWNMEP_TX_DESTINATION_TYPE encoding name strings for debugging. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_DESTINATION_TYPE_NAME_MAP_INIT \ + {"EGRESS_PORT", BCMPKT_TXPMD_OAM_DOWNMEP_TX_DESTINATION_T_EGRESS_PORT},\ + +/*! + * \name BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION encodings. + * \anchor BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION_XXX + */ +/*! \{ */ +/*! No operation. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION_NO_OP 0 +/*! Increment. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION_INCREMENT 1 +/*! Increment and sample. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION_INCREMENT_SAMPLE 2 +/*! Sample. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION_SAMPLE 3 +/*! \} */ + +/*! BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION encoding name strings for debugging. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION_NAME_MAP_INIT \ + {"NO_OP", BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION_NO_OP},\ + {"INCREMENT", BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION_INCREMENT},\ + {"INCREMENT_SAMPLE", BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION_INCREMENT_SAMPLE},\ + {"SAMPLE", BCMPKT_TXPMD_OAM_DOWNMEP_TX_LM_COUNTER_ACTION_SAMPLE},\ + +/*! + * \name BCMPKT_TXPMD_OAM_DOWNMEP_TX_TIMESTAMP_ACTION encodings. + * \anchor BCMPKT_TXPMD_OAM_DOWNMEP_TX_TIMESTAMP_ACTION_XXX + */ +/*! \{ */ +/*! No operation. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_TIMESTAMP_ACTION_NO_OP 0 +/*! Sample timestamp. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_TIMESTAMP_ACTION_SAMPLE 1 +/*! \} */ + +/*! BCMPKT_TXPMD_OAM_DOWNMEP_TX_TIMESTAMP_ACTION encoding name strings for debugging. */ +#define BCMPKT_TXPMD_OAM_DOWNMEP_TX_TIMESTAMP_ACTION_NAME_MAP_INIT \ + {"NO_OP", BCMPKT_TXPMD_OAM_DOWNMEP_TX_TIMESTAMP_ACTION_NO_OP},\ + {"SAMPLE", BCMPKT_TXPMD_OAM_DOWNMEP_TX_TIMESTAMP_ACTION_SAMPLE},\ + +/*! + * \name BCMPKT_TXPMD_CPU_TX_INCA_REDN_REQD encodings. + * \anchor BCMPKT_TXPMD_CPU_TX_INCA_REDN_REQD_XXX + */ +/*! \{ */ +/*! Reduction not required. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_REDN_REQD_BROADCAST 0 +/*! Reduction required. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_REDN_REQD_REDUCE 1 +/*! \} */ + +/*! BCMPKT_TXPMD_CPU_TX_INCA_REDN_REQD encoding name strings for debugging. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_REDN_REQD_NAME_MAP_INIT \ + {"BROADCAST", BCMPKT_TXPMD_CPU_TX_INCA_REDN_REQD_BROADCAST},\ + {"REDUCE", BCMPKT_TXPMD_CPU_TX_INCA_REDN_REQD_REDUCE},\ + +/*! + * \name BCMPKT_TXPMD_CPU_TX_INCA_REPL_REQD encodings. + * \anchor BCMPKT_TXPMD_CPU_TX_INCA_REPL_REQD_XXX + */ +/*! \{ */ +/*! Replication required. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_REPL_REQD_REDUCE 0 +/*! Replication not required. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_REPL_REQD_BROADCAST 1 +/*! \} */ + +/*! BCMPKT_TXPMD_CPU_TX_INCA_REPL_REQD encoding name strings for debugging. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_REPL_REQD_NAME_MAP_INIT \ + {"REDUCE", BCMPKT_TXPMD_CPU_TX_INCA_REPL_REQD_REDUCE},\ + {"BROADCAST", BCMPKT_TXPMD_CPU_TX_INCA_REPL_REQD_BROADCAST},\ + +/*! + * \name BCMPKT_TXPMD_CPU_TX_INCA_ICE_OPER_TYPE encodings. + * \anchor BCMPKT_TXPMD_CPU_TX_INCA_ICE_OPER_TYPE_XXX + */ +/*! \{ */ +/*! */ +#define BCMPKT_TXPMD_CPU_TX_INCA_ICE_OPER_T_SUM 0 +/*! */ +#define BCMPKT_TXPMD_CPU_TX_INCA_ICE_OPER_T_SUM_AND_SCALE 1 +/*! \} */ + +/*! BCMPKT_TXPMD_CPU_TX_INCA_ICE_OPER_TYPE encoding name strings for debugging. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_ICE_OPER_TYPE_NAME_MAP_INIT \ + {"SUM", BCMPKT_TXPMD_CPU_TX_INCA_ICE_OPER_T_SUM},\ + {"SUM_AND_SCALE", BCMPKT_TXPMD_CPU_TX_INCA_ICE_OPER_T_SUM_AND_SCALE},\ + +/*! + * \name BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT encodings. + * \anchor BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT_XXX + */ +/*! \{ */ +/*! */ +#define BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT_FP32 0 +/*! */ +#define BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT_FP16 1 +/*! */ +#define BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT_BF16 2 +/*! */ +#define BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT_INT32 3 +/*! */ +#define BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT_FP8 4 +/*! \} */ + +/*! BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT encoding name strings for debugging. */ +#define BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT_NAME_MAP_INIT \ + {"FP32", BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT_FP32},\ + {"FP16", BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT_FP16},\ + {"BF16", BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT_BF16},\ + {"INT32", BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT_INT32},\ + {"FP8", BCMPKT_TXPMD_CPU_TX_INCA_ICE_DATA_FORMAT_FP8},\ + +/*! + * \name BCMPKT_TXPMD_CPU_TX_CPU_TX_TYPE encodings. + * \anchor BCMPKT_TXPMD_CPU_TX_CPU_TX_TYPE_XXX + */ +/*! \{ */ +/*! Classic CPU TX (Masquerade, Dest-based). */ +#define BCMPKT_TXPMD_CPU_TX_CPU_TX_T_MASQUERADE 0 +/*! Sample timestamp. */ +#define BCMPKT_TXPMD_CPU_TX_CPU_TX_T_INCA 1 +/*! \} */ + +/*! BCMPKT_TXPMD_CPU_TX_CPU_TX_TYPE encoding name strings for debugging. */ +#define BCMPKT_TXPMD_CPU_TX_CPU_TX_TYPE_NAME_MAP_INIT \ + {"MASQUERADE", BCMPKT_TXPMD_CPU_TX_CPU_TX_T_MASQUERADE},\ + {"INCA", BCMPKT_TXPMD_CPU_TX_CPU_TX_T_INCA},\ + +/*! + * \name BCMPKT_TXPMD_AUX_SOBMH_HEADER_TYPE encodings. + * \anchor BCMPKT_TXPMD_AUX_SOBMH_HEADER_TYPE_XXX + */ +/*! \{ */ +/*! Reserved. */ +#define BCMPKT_TXPMD_AUX_SOBMH_HEADER_T_RESERVED 0 +/*! Packets from CPU with SOBMH header format to Passthru NLF */ +#define BCMPKT_TXPMD_AUX_SOBMH_HEADER_T_FROM_CPU 1 +/*! \} */ + +/*! BCMPKT_TXPMD_AUX_SOBMH_HEADER_TYPE encoding name strings for debugging. */ +#define BCMPKT_TXPMD_AUX_SOBMH_HEADER_TYPE_NAME_MAP_INIT \ + {"RESERVED", BCMPKT_TXPMD_AUX_SOBMH_HEADER_T_RESERVED},\ + {"SOBMH_FROM_CPU", BCMPKT_TXPMD_AUX_SOBMH_HEADER_T_FROM_CPU},\ + +/*! + * \name TX packet metadata internal usage field IDs. + * \anchor BCMPKT_TXPMD_I_XXX + */ +/*! \{ */ +/*! Invalid BCMPKT_TXPMD_I FID indicator */ +#define BCMPKT_TXPMD_I_FID_INVALID -1 +/*! TXPMD RX raw data size. */ +#define BCMPKT_TXPMD_I_SIZE 0 +/*! TXPMD_I FIELD ID NUMBER */ +#define BCMPKT_TXPMD_I_FID_COUNT 1 +/*! \} */ + +/*! TXPMD_I field name strings for debugging. */ +#define BCMPKT_TXPMD_I_FIELD_NAME_MAP_INIT \ + {"SIZE", BCMPKT_TXPMD_I_SIZE},\ + {"fid count", BCMPKT_TXPMD_I_FID_COUNT} + +#endif /*! BCMPKT_TXPMD_DEFS_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd_field.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd_field.h new file mode 100644 index 0000000..ccd1b7c --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd_field.h @@ -0,0 +1,72 @@ +/*! \file bcmpkt_txpmd_field.h + * + * TX Packet MetaData (TXPMD, called SOBMH in hardware) field api's. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_TXPMD_FIELD_H +#define BCMPKT_TXPMD_FIELD_H + +/*! + * \brief Get value from a TXPMD field. + * + * \param [in] dev_type Device type. + * \param [in] txpmd TXPMD handle. + * \param [in] fid TXPMD field ID, refer to \ref BCMPKT_TXPMD_XXX. + * \param [out] val Field value. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support the field. + */ +extern int +bcmpkt_txpmd_field_get(bcmdrd_dev_type_t dev_type, uint32_t *txpmd, + int fid, uint32_t *val); + +/*! + * \brief Set value into a TXPMD field. + * + * \param [in] dev_type Device type. + * \param [in,out] txpmd TXPMD handle. + * \param [in] fid TXPMD field ID, refer to \ref BCMPKT_TXPMD_XXX. + * \param [in] val Set value. + * + * \retval SHR_E_NONE success. + * \retval SHR_E_PARAM Check parameters failed. + * \retval SHR_E_UNAVAIL Not support the field. + */ +extern int +bcmpkt_txpmd_field_set(bcmdrd_dev_type_t dev_type, uint32_t *txpmd, + int fid, uint32_t val); + +#endif /* BCMPKT_TXPMD_FIELD_H */ + diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd_internal.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd_internal.h new file mode 100644 index 0000000..54f9080 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_txpmd_internal.h @@ -0,0 +1,79 @@ +/*! \file bcmpkt_txpmd_internal.h + * + * TX Packet MetaData (TXPMD, called SOBMH in hardware) access interface + * (Internal use only). + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_TXPMD_INTERNAL_H +#define BCMPKT_TXPMD_INTERNAL_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif +#include +#include + +/*! + * Array of TXPMD field getter functions for a particular device + * type. + */ +typedef struct bcmpkt_txpmd_fget_s { + bcmpkt_field_get_f fget[BCMPKT_TXPMD_FID_COUNT]; +} bcmpkt_txpmd_fget_t; + +/*! + * Array of TXPMD field setter functions for a particular device + * type. These functions are used for internally configuring packet + * filter. + */ +typedef struct bcmpkt_txpmd_fset_s { + bcmpkt_field_set_f fset[BCMPKT_TXPMD_FID_COUNT]; +} bcmpkt_txpmd_fset_t; + +/*! + * Array of TXPMD field address and length getter functions for a multiple + * words field of a particular device type. *addr is output address and return + * length. + */ +typedef struct bcmpkt_txpmd_figet_s { + bcmpkt_ifield_get_f fget[BCMPKT_TXPMD_I_FID_COUNT]; +} bcmpkt_txpmd_figet_t; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern void _bd##_txpmd_view_info_get(bcmpkt_pmd_view_info_t *info); +#define BCMDRD_DEVLIST_OVERRIDE +#include + +#endif /* BCMPKT_TXPMD_INTERNAL_H */ diff --git a/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_util.h b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_util.h new file mode 100644 index 0000000..6ffdc28 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/include/bcmpkt/bcmpkt_util.h @@ -0,0 +1,90 @@ +/*! \file bcmpkt_util.h + * + * BCMPKT utility functions. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef BCMPKT_UTIL_H +#define BCMPKT_UTIL_H + +#include +#include +#include + +/*! + * \brief Get device dispatch type based on device name. + * + * Device name is case-insensitive. + * + * \param [in] dev_name Device name, e.g. "bcm56000_a0". + * + * \return Device dispatch type or BCMDRD_DEV_T_NONE if not found. + */ +extern bcmdrd_dev_type_t +bcmpkt_util_dev_type_get(const char *dev_name); + +/*! + * \brief Get variant dispatch type based on device and variant names. + * + * Device and variant names are case-insensitive. + * + * \param [in] dev_name Device name, e.g. "bcm56000_a0". + * \param [in] var_name Variant name, e.g. "dna_6_5_30_1_1". + * + * \return Variant dispatch type or BCMLRD_VARIANT_T_NONE if not found. + */ +extern bcmlrd_variant_t +bcmpkt_util_variant_type_get(const char *dev_name, const char *var_name); + +/*! + * \brief Get device id based on device type. + * + * \param [in] dev_type Device type, e.g. "BCMDRD_DEV_T_BCM56000_A0". + * + * \return Device id or 0 if not found. + */ +extern uint32_t +bcmpkt_util_dev_id_get(const bcmdrd_dev_type_t dev_type); + +/*! + * \brief Initialize RCPU header based on device type. + * + * \param [in] dev_type Device type e.g. "BCMDRD_DEV_T_BCM56000_A0". + * \param [out] rhdr RCPU header handle. + * + * \return none. + */ +extern void +bcmpkt_util_rcpu_hdr_init(const bcmdrd_dev_type_t dev_type, + bcmpkt_rcpu_hdr_t *rhdr); + +#endif /* BCMPKT_UTIL_H */ diff --git a/src/bcm/common/pktio/bcmpkt/rxpmd/bcmpkt_rxpmd.c b/src/bcm/common/pktio/bcmpkt/rxpmd/bcmpkt_rxpmd.c new file mode 100644 index 0000000..b1653ac --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/rxpmd/bcmpkt_rxpmd.c @@ -0,0 +1,432 @@ +/*! \file bcmpkt_rxpmd.c + * + * RX Packet Meta Data (RXPMD, called EP_TO_CPU in hardware) access interfaces. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif +#include +#include + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern const bcmpkt_rxpmd_fget_t _bd##_rxpmd_fget; +#include + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + &_bd##_rxpmd_fget, +/*! This sequence should be same as bcmdrd_cm_dev_type_t */ +static const bcmpkt_rxpmd_fget_t *rxpmd_fget[] = { + NULL, +#include + NULL +}; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern const bcmpkt_rxpmd_fset_t _bd##_rxpmd_fset; +#include + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + &_bd##_rxpmd_fset, +/*! This sequence should be same as bcmdrd_cm_dev_type_t */ +static const bcmpkt_rxpmd_fset_t *rxpmd_fset[] = { + NULL, +#include + NULL +}; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern const bcmpkt_rxpmd_figet_t _bd##_rxpmd_figet; +#include + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + &_bd##_rxpmd_figet, +/*! This sequence should be same as bcmdrd_cm_dev_type_t */ +static const bcmpkt_rxpmd_figet_t *rxpmd_figet[] = { + NULL, +#include + NULL +}; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + &_bd##_rx_reason_decode, +/*! This sequence should be same as bcmdrd_cm_dev_type_t */ +static void (*reason_fdecode[])(const uint32_t*, bcmpkt_rx_reasons_t*) = { + NULL, +#include + NULL +}; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + &_bd##_rx_reason_encode, +static void (*reason_fencode[])(const bcmpkt_rx_reasons_t*, uint32_t*) = { + NULL, +#include + NULL +}; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + &_bd##_ep_rx_reason_decode, +/*! This sequence should be same as bcmdrd_cm_dev_type_t */ +static void (*ep_reason_fdecode[])(const uint32_t*, bcmpkt_rx_reasons_t*) = { + NULL, +#include + NULL +}; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + &_bd##_ep_rx_reason_encode, +static void (*ep_reason_fencode[])(const bcmpkt_rx_reasons_t*, uint32_t*) = { + NULL, +#include + NULL +}; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + &_bd##_rxpmd_view_info_get, +static void (*view_info_get[])(bcmpkt_pmd_view_info_t *) = { + NULL, +#include + NULL +}; + + +static const shr_enum_map_t field_names[] = +{ + BCMPKT_RXPMD_FIELD_NAME_MAP_INIT +}; + +static const shr_enum_map_t reason_names[] = +{ + BCMPKT_REASON_NAME_MAP_INIT +}; + +int +bcmpkt_rxpmd_len_get(bcmdrd_dev_type_t dev_type, uint32_t *len) +{ + + if (len == NULL) { + return SHR_E_PARAM; + } + + if (dev_type <= BCMDRD_DEV_T_NONE || + dev_type >= BCMDRD_DEV_T_COUNT) { + return SHR_E_PARAM; + } + + if (rxpmd_figet[dev_type] == NULL || + rxpmd_figet[dev_type]->fget[BCMPKT_RXPMD_I_SIZE] == NULL) { + return SHR_E_UNAVAIL; + } + + *len = rxpmd_figet[dev_type]->fget[BCMPKT_RXPMD_I_SIZE](NULL, NULL) * 4; + + return SHR_E_NONE; +} + +int +bcmpkt_rxpmd_field_get(bcmdrd_dev_type_t dev_type, uint32_t *rxpmd, + int fid, uint32_t *val) +{ + + if ((rxpmd == NULL) || (val == NULL)) { + return SHR_E_PARAM; + } + + if (dev_type <= BCMDRD_DEV_T_NONE || dev_type >= BCMDRD_DEV_T_COUNT) { + return SHR_E_PARAM; + } + + if (fid < 0 || fid >= BCMPKT_RXPMD_FID_COUNT) { + return SHR_E_PARAM; + } + + if (rxpmd_fget[dev_type] == NULL || + rxpmd_fget[dev_type]->fget[fid] == NULL) { + return SHR_E_UNAVAIL; + } + + *val = rxpmd_fget[dev_type]->fget[fid](rxpmd); + + return SHR_E_NONE; +} + +int +bcmpkt_rxpmd_field_set(bcmdrd_dev_type_t dev_type, uint32_t *rxpmd, + int fid, uint32_t val) +{ + + if (rxpmd == NULL) { + return SHR_E_PARAM; + } + + if (dev_type <= BCMDRD_DEV_T_NONE || dev_type >= BCMDRD_DEV_T_COUNT) { + return SHR_E_PARAM; + } + + if (fid < 0 || fid >= BCMPKT_RXPMD_FID_COUNT) { + return SHR_E_PARAM; + } + + if (rxpmd_fset[dev_type] == NULL || + rxpmd_fset[dev_type]->fset[fid] == NULL) { + return SHR_E_UNAVAIL; + } + + rxpmd_fset[dev_type]->fset[fid](rxpmd, val); + + return SHR_E_NONE; +} + +int +bcmpkt_rxpmd_mh_get(bcmdrd_dev_type_t dev_type, uint32_t *rxpmd, + uint32_t **hg_hdr) +{ + int len; + + if ((rxpmd == NULL) || (hg_hdr == NULL)) { + return SHR_E_PARAM; + } + + if (dev_type <= BCMDRD_DEV_T_NONE || dev_type >= BCMDRD_DEV_T_COUNT) { + return SHR_E_PARAM; + } + + if (rxpmd_figet[dev_type] == NULL || + rxpmd_figet[dev_type]->fget[BCMPKT_RXPMD_I_MODULE_HDR] == NULL) { + return SHR_E_UNAVAIL; + } + + len = rxpmd_figet[dev_type]->fget[BCMPKT_RXPMD_I_MODULE_HDR](rxpmd, hg_hdr); + if (len <= 0) { + return SHR_E_INTERNAL; + } + + return SHR_E_NONE; +} + +int +bcmpkt_rxpmd_flexdata_get(bcmdrd_dev_type_t dev_type, uint32_t *rxpmd, + uint32_t **flexdata, uint32_t *len) +{ + + if ((rxpmd == NULL) || (flexdata == NULL) || (len == NULL)) { + return SHR_E_PARAM; + } + + *len = 0; + if (dev_type <= BCMDRD_DEV_T_NONE || dev_type >= BCMDRD_DEV_T_COUNT) { + return SHR_E_PARAM; + } + + if (rxpmd_figet[dev_type] == NULL || + rxpmd_figet[dev_type]->fget[BCMPKT_RXPMD_I_FLEX_DATA] == NULL) { + return SHR_E_UNAVAIL; + } + + *len = rxpmd_figet[dev_type]->fget[BCMPKT_RXPMD_I_FLEX_DATA](rxpmd, flexdata); + if (*len == 0) { + return SHR_E_INTERNAL; + } + + return SHR_E_NONE; +} + +int +bcmpkt_rxpmd_reasons_get(bcmdrd_dev_type_t dev_type, uint32_t *rxpmd, + bcmpkt_rx_reasons_t *reasons) +{ + uint32_t *reason = NULL; + int len; + shr_error_t rv = SHR_E_NONE; + uint32_t reason_type = BCMPKT_RXPMD_REASON_T_FROM_IP; + + if ((rxpmd == NULL) || (reasons == NULL)) { + return SHR_E_PARAM; + } + + if (dev_type <= BCMDRD_DEV_T_NONE || dev_type >= BCMDRD_DEV_T_COUNT) { + return SHR_E_PARAM; + } + + if (rxpmd_figet[dev_type] == NULL || + rxpmd_figet[dev_type]->fget[BCMPKT_RXPMD_I_REASON] == NULL) { + return SHR_E_UNAVAIL; + } +#ifdef PKTIO_KIMPL + sal_memset(reasons, 0, sizeof(*reasons)); +#else + BCMPKT_RX_REASON_CLEAR_ALL(*reasons); +#endif + len = rxpmd_figet[dev_type]->fget[BCMPKT_RXPMD_I_REASON](rxpmd, &reason); + if (len <= 0) { + return SHR_E_INTERNAL; + } + + rv = bcmpkt_rxpmd_field_get(dev_type, rxpmd, BCMPKT_RXPMD_REASON_TYPE, + &reason_type); + if ((rv == SHR_E_NONE) && (reason_type == BCMPKT_RXPMD_REASON_T_FROM_EP)) { + ep_reason_fdecode[dev_type](reason, reasons); + } else { + reason_fdecode[dev_type](reason, reasons); + } + + return SHR_E_NONE; +} + +int +bcmpkt_rxpmd_reasons_set(bcmdrd_dev_type_t dev_type, + bcmpkt_rx_reasons_t *reasons, uint32_t *rxpmd) +{ + uint32_t *reason = NULL; + int len; + shr_error_t rv = SHR_E_NONE; + uint32_t reason_type = BCMPKT_RXPMD_REASON_T_FROM_IP; + + if ((rxpmd == NULL) || (reasons == NULL)) { + return SHR_E_PARAM; + } + + + if (dev_type <= BCMDRD_DEV_T_NONE || dev_type >= BCMDRD_DEV_T_COUNT) { + return SHR_E_PARAM; + } + + if (rxpmd_figet[dev_type] == NULL || + rxpmd_figet[dev_type]->fget[BCMPKT_RXPMD_I_REASON] == NULL) { + return SHR_E_UNAVAIL; + } + len = rxpmd_figet[dev_type]->fget[BCMPKT_RXPMD_I_REASON](rxpmd, &reason); + if (len <= 0) { + return SHR_E_UNAVAIL; + } + + sal_memset(reason, 0, len * 4); + rv = bcmpkt_rxpmd_field_get(dev_type, rxpmd, BCMPKT_RXPMD_REASON_TYPE, + (uint32_t *)&reason_type); + if ((rv == SHR_E_NONE) && (reason_type == BCMPKT_RXPMD_REASON_T_FROM_EP)) { + ep_reason_fencode[dev_type](reasons, reason); + } else { + reason_fencode[dev_type](reasons, reason); + } + return SHR_E_NONE; +} + +int +bcmpkt_rxpmd_field_name_get(int fid, char **name) +{ + if (name == NULL) { + return SHR_E_PARAM; + } + if (fid <= BCMPKT_RXPMD_FID_INVALID || + fid >= BCMPKT_RXPMD_FID_COUNT) { + return SHR_E_PARAM; + } + + *name = field_names[fid].name; + + return SHR_E_NONE; +} + +int +bcmpkt_rxpmd_field_id_get(char* name, int *fid) +{ + int i; + + if ((name == NULL) || (fid == NULL)) { + return SHR_E_PARAM; + } + + for (i = BCMPKT_RXPMD_FID_INVALID + 1; i < BCMPKT_RXPMD_FID_COUNT; i++) { + if (sal_strcasecmp(field_names[i].name, name) == 0) { + *fid = field_names[i].val; + return SHR_E_NONE; + } + } + + return SHR_E_NOT_FOUND; +} + +int +bcmpkt_rxpmd_fid_support_get(bcmdrd_dev_type_t dev_type, + bcmpkt_rxpmd_fid_support_t *support) +{ + int i; + bcmpkt_pmd_view_info_t view_info; + + if (dev_type <= BCMDRD_DEV_T_NONE || + dev_type >= BCMDRD_DEV_T_COUNT) { + return SHR_E_PARAM; + } + if (view_info_get[dev_type] == NULL) { + return SHR_E_INTERNAL; + } + if (support == NULL) { + return SHR_E_PARAM; + } + sal_memset(support, 0, sizeof(*support)); + + view_info_get[dev_type](&view_info); + if ((view_info.view_types == NULL) || (view_info.view_infos == NULL)) { + return SHR_E_UNAVAIL; + } + + for (i = BCMPKT_RXPMD_FID_INVALID + 1; i < BCMPKT_RXPMD_FID_COUNT; i++) { + if (view_info.view_infos[i] >= -1) { + SHR_BITSET(support->fbits, i); + } + } + + return SHR_E_NONE; +} + +int +bcmpkt_rx_reason_name_get(int reason, char **name) +{ + + if (name == NULL) { + return SHR_E_PARAM; + } + + if (reason <= BCMPKT_RX_REASON_NONE || + reason > BCMPKT_RX_REASON_COUNT) { + return SHR_E_PARAM; + } + + *name = reason_names[reason].name; + + return SHR_E_NONE; +} + diff --git a/src/bcm/common/pktio/bcmpkt/txpmd/bcmpkt_txpmd.c b/src/bcm/common/pktio/bcmpkt/txpmd/bcmpkt_txpmd.c new file mode 100644 index 0000000..fbe0073 --- /dev/null +++ b/src/bcm/common/pktio/bcmpkt/txpmd/bcmpkt_txpmd.c @@ -0,0 +1,273 @@ +/*! \file bcmpkt_txpmd.c + * + * TX Packet MetaData (TXPMD, called SOBMH in hardware) access interface. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif +#include +#include +#include + + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern const bcmpkt_txpmd_fget_t _bd##_txpmd_fget; +#include + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + &_bd##_txpmd_fget, +static const bcmpkt_txpmd_fget_t *txpmd_fget[] = { + NULL, +#include + NULL +}; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern const bcmpkt_txpmd_fset_t _bd##_txpmd_fset; +#include + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + &_bd##_txpmd_fset, +static const bcmpkt_txpmd_fset_t *txpmd_fset[] = { + NULL, +#include + NULL +}; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + extern const bcmpkt_txpmd_figet_t _bd##_txpmd_figet; +#include + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + &_bd##_txpmd_figet, +static const bcmpkt_txpmd_figet_t *txpmd_figet[] = { + NULL, +#include + NULL +}; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + &_bd##_txpmd_view_info_get, +static void (*view_info_get[])(bcmpkt_pmd_view_info_t *info) = { + NULL, +#include + NULL +}; + +static const shr_enum_map_t field_names[] = +{ + BCMPKT_TXPMD_FIELD_NAME_MAP_INIT +}; + +int +bcmpkt_txpmd_len_get(bcmdrd_dev_type_t dev_type, uint32_t *len) +{ + if (len == NULL) { + return SHR_E_PARAM; + } + + if (dev_type <= BCMDRD_DEV_T_NONE || + dev_type >= BCMDRD_DEV_T_COUNT) { + return SHR_E_PARAM; + } + + if (txpmd_figet[dev_type] == NULL || + txpmd_figet[dev_type]->fget[BCMPKT_TXPMD_I_SIZE] == NULL) { + return SHR_E_UNAVAIL; + } + + *len = txpmd_figet[dev_type]->fget[BCMPKT_TXPMD_I_SIZE](NULL, NULL) * 4; + + return SHR_E_NONE; +} + +int +bcmpkt_txpmd_field_get(bcmdrd_dev_type_t dev_type, uint32_t *txpmd, + int fid, uint32_t *val) +{ + + if ((txpmd == NULL) || (val == NULL)) { + return SHR_E_PARAM; + } + + if (dev_type <= BCMDRD_DEV_T_NONE || + dev_type >= BCMDRD_DEV_T_COUNT) { + return SHR_E_PARAM; + } + + if (fid < 0 || fid >= BCMPKT_TXPMD_FID_COUNT) { + return SHR_E_PARAM; + } + + if (txpmd_fget[dev_type] == NULL || + txpmd_fget[dev_type]->fget[fid] == NULL) { + return SHR_E_UNAVAIL; + } + + *val = txpmd_fget[dev_type]->fget[fid](txpmd); + + return SHR_E_NONE; +} + +int +bcmpkt_txpmd_field_set(bcmdrd_dev_type_t dev_type, uint32_t *txpmd, + int fid, uint32_t val) +{ + if (txpmd == NULL) { + return SHR_E_PARAM; + } + + if (dev_type <= BCMDRD_DEV_T_NONE || + dev_type >= BCMDRD_DEV_T_COUNT) { + return SHR_E_PARAM; + } + + if (fid < 0 || fid >= BCMPKT_TXPMD_FID_COUNT) { + return SHR_E_PARAM; + } + + if (txpmd_fset[dev_type] == NULL || + txpmd_fset[dev_type]->fset[fid] == NULL) { + return SHR_E_UNAVAIL; + } + + txpmd_fset[dev_type]->fset[fid](txpmd, val); + + return SHR_E_NONE; +} + +int +bcmpkt_txpmd_field_name_get(int fid, char **name) +{ + if (name == NULL) { + return SHR_E_PARAM; + } + + if (fid <= BCMPKT_TXPMD_FID_INVALID || + fid >= BCMPKT_TXPMD_FID_COUNT) { + return SHR_E_PARAM; + } + + *name = field_names[fid].name; + + return SHR_E_NONE; +} + +int +bcmpkt_txpmd_field_id_get(char* name, int *fid) +{ + int i; + + if ((name == NULL) || (fid == NULL)) { + return SHR_E_PARAM; + } + + for (i = BCMPKT_TXPMD_FID_INVALID + 1; i < BCMPKT_TXPMD_FID_COUNT; i++) { + if (sal_strcasecmp(field_names[i].name, name) == 0) { + *fid = field_names[i].val; + return SHR_E_NONE; + } + } + + return SHR_E_NOT_FOUND; +} + +int +bcmpkt_txpmd_fid_support_get(bcmdrd_dev_type_t dev_type, + bcmpkt_txpmd_fid_support_t *support) +{ + int i; + bcmpkt_pmd_view_info_t view_info; + + if (dev_type <= BCMDRD_DEV_T_NONE || + dev_type >= BCMDRD_DEV_T_COUNT) { + return SHR_E_PARAM; + } + if (view_info_get[dev_type] == NULL) { + return SHR_E_INTERNAL; + } + if (support == NULL) { + return SHR_E_PARAM; + } + sal_memset(support, 0, sizeof(*support)); + + view_info_get[dev_type](&view_info); + if ((view_info.view_types == NULL) || (view_info.view_infos == NULL)) { + return SHR_E_UNAVAIL; + } + + for (i = BCMPKT_TXPMD_FID_INVALID + 1; i < BCMPKT_TXPMD_FID_COUNT; i++) { + if (view_info.view_infos[i] >= -1) { + SHR_BITSET(support->fbits, i); + } + } + + return SHR_E_NONE; +} + +int +bcmpkt_txpmd_fid_view_get(bcmdrd_dev_type_t dev_type, + int fid, int *view) + +{ + bcmpkt_pmd_view_info_t view_info; + + if (dev_type <= BCMDRD_DEV_T_NONE || + dev_type >= BCMDRD_DEV_T_COUNT) { + return SHR_E_PARAM; + } + + if (view == NULL) { + return SHR_E_PARAM; + } + + if (fid <= BCMPKT_TXPMD_FID_INVALID || + fid >= BCMPKT_TXPMD_FID_COUNT) { + return SHR_E_PARAM; + } + + if (view_info_get[dev_type] == NULL) { + return SHR_E_INTERNAL; + } + + view_info_get[dev_type](&view_info); + if ((view_info.view_types == NULL) || (view_info.view_infos == NULL)) { + return SHR_E_UNAVAIL; + } + *view = view_info.view_infos[fid]; + + return SHR_E_NONE; +} diff --git a/src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pdma_attach.c b/src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pdma_attach.c new file mode 100644 index 0000000..3de09f9 --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pdma_attach.c @@ -0,0 +1,84 @@ +/*! \file bcm88690_a0_pdma_attach.c + * + * Initialize PDMA driver resources. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include + +#ifdef PKTIO_KIMPL +#include "ngknet_adapter.h" + +static pdma_rx_f ngkent_pkt_recv_func = NULL; + +static int +ngknet_dev_pkt_recv( + struct pdma_dev *dev, + int queue, + void *buf) +{ + int rv = 0; + rv = ngknet_adapter_frame_recv(dev, queue, buf); + if (rv < 0) { + return rv; + } + if (ngkent_pkt_recv_func) { + rv = ngkent_pkt_recv_func(dev, queue, buf); + } + return rv; +} +#endif /*PKTIO_KIMPL*/ + +int +bcm88690_a0_cnet_pdma_attach( + struct pdma_dev *dev) +{ + int rv; + rv = bcmcnet_cmicx_pdma_driver_attach(dev); + dev->flags |= PDMA_NO_FCS; +#ifdef PKTIO_KIMPL + if (ngkent_pkt_recv_func == NULL) { + ngkent_pkt_recv_func = dev->pkt_recv; + } + dev->pkt_recv = ngknet_dev_pkt_recv; +#endif /*PKTIO_KIMPL*/ + return rv; +} + +int +bcm88690_a0_cnet_pdma_detach( + struct pdma_dev *dev) +{ + return bcmcnet_cmicx_pdma_driver_detach(dev); +} diff --git a/src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pkt_rxpmd.c b/src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pkt_rxpmd.c new file mode 100644 index 0000000..cda9bbb --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pkt_rxpmd.c @@ -0,0 +1,439 @@ + /******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides RXPMD access functions for BCM88690_A0. + * + ******************************************************************************/ + +#include +#include +#include + +#define WORD_MASK(_bn) (((uint32_t)0x1<<(_bn))-1) +#define WORD_FIELD_GET(_d,_s,_l) (((_d) >> (_s)) & WORD_MASK(_l)) +#define WORD_FIELD_SET(_d,_s,_l,_v) (_d)=(((_d) & ~(WORD_MASK(_l) << (_s))) | (((_v) & WORD_MASK(_l)) << (_s))) +#define WORD_FIELD_MASK(_d,_s,_l) (_d)=((_d) | (WORD_MASK(_l) << (_s))) + +/******************************************************************************* + * SWFORMAT: RXPMD + * BLOCKS: + * SIZE: 1536 + ******************************************************************************/ +static void +bcmpkt_rxpmd_system_header_length_set( + uint32_t * data, + uint32_t val) +{ + data[0] = val; +} + +static uint32_t +bcmpkt_rxpmd_system_header_length_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[0]; + return val; +} + +static void +bcmpkt_rxpmd_rx_channel_set( + uint32_t * data, + uint32_t val) +{ + data[1] = val; +} + +static uint32_t +bcmpkt_rxpmd_rx_channel_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[1]; + return val; +} + +static void +bcmpkt_rxpmd_ftmh_tc_set( + uint32_t * data, + uint32_t val) +{ + data[2] = val; + return; +} + +static uint32_t +bcmpkt_rxpmd_ftmh_tc_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[2]; + return val; +} + +static void +bcmpkt_rxpmd_ftmh_src_sysport_set( + uint32_t * data, + uint32_t val) +{ + data[3] = val; + return; +} + +static uint32_t +bcmpkt_rxpmd_ftmh_src_sysport_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[3]; + return val; +} + +static void +bcmpkt_rxpmd_internal_trap_code_set( + uint32_t * data, + uint32_t val) +{ + data[4] = val; + return; +} + +static uint32_t +bcmpkt_rxpmd_internal_trap_code_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[4]; + return val; +} + +static void +bcmpkt_rxpmd_internal_trap_qualifier_set( + uint32_t * data, + uint32_t val) +{ + data[5] = val; + return; +} + +static uint32_t +bcmpkt_rxpmd_internal_trap_qualifier_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[5]; + return val; +} + +static uint32_t +bcmpkt_rxpmd_i_size_get( + uint32_t *data, + uint32_t **addr) +{ + return 16; +} + +/******************************************************************************* + * SWFORMAT: RX_REASON + * BLOCKS: + * SIZE: 42 + ******************************************************************************/ +void +bcm88690_a0_rx_reason_encode( + const bcmpkt_rx_reasons_t * reasons, + uint32_t * data) +{ +} + +void +bcm88690_a0_rx_reason_decode( + const uint32_t * data, + bcmpkt_rx_reasons_t * reasons) +{ +} + +void +bcm88690_a0_ep_rx_reason_encode( + const bcmpkt_rx_reasons_t * reasons, + uint32_t * data) +{ +} + +void +bcm88690_a0_ep_rx_reason_decode( + const uint32_t * data, + bcmpkt_rx_reasons_t * reasons) +{ +} + +const bcmpkt_rxpmd_fget_t bcm88690_a0_rxpmd_fget = { +{ + bcmpkt_rxpmd_system_header_length_get, + bcmpkt_rxpmd_rx_channel_get, + bcmpkt_rxpmd_ftmh_tc_get, + bcmpkt_rxpmd_ftmh_src_sysport_get, + bcmpkt_rxpmd_internal_trap_code_get, + bcmpkt_rxpmd_internal_trap_qualifier_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL +} +}; + +const bcmpkt_rxpmd_fset_t bcm88690_a0_rxpmd_fset = { +{ + bcmpkt_rxpmd_system_header_length_set, + bcmpkt_rxpmd_rx_channel_set, + bcmpkt_rxpmd_ftmh_tc_set, + bcmpkt_rxpmd_ftmh_src_sysport_set, + bcmpkt_rxpmd_internal_trap_code_set, + bcmpkt_rxpmd_internal_trap_qualifier_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL +} +}; + +const bcmpkt_rxpmd_figet_t bcm88690_a0_rxpmd_figet = { +{ + bcmpkt_rxpmd_i_size_get, + NULL, + NULL, + NULL +} +}; + +static shr_enum_map_t bcm88690_a0_rxpmd_view_types[] = { + {NULL, -1}, +}; + +/* -2: unsupported, -1: global, others: view's value */ +static int bcm88690_a0_rxpmd_view_infos[BCMPKT_RXPMD_FID_COUNT] = { + -1, -1, -1, -1, -1, -1, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2 +}; + +void +bcm88690_a0_rxpmd_view_info_get( + bcmpkt_pmd_view_info_t * info) +{ + info->view_infos = bcm88690_a0_rxpmd_view_infos; + info->view_types = bcm88690_a0_rxpmd_view_types; + info->view_type_get = NULL; +} diff --git a/src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pkt_rxpmd_dev_field.c b/src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pkt_rxpmd_dev_field.c new file mode 100644 index 0000000..5265fbb --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pkt_rxpmd_dev_field.c @@ -0,0 +1,42 @@ +/*! \file bcm88690_a0_pkt_rxpmd_dev_field.c + * + * This file provides RXPMD access functions for BCM88690_A0. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include + +const bcmpkt_rxpmd_func_t bcm88690_a0_rxpmd_func = { 0 }; + diff --git a/src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pkt_txpmd.c b/src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pkt_txpmd.c new file mode 100644 index 0000000..6f1abcd --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm88690_a0/bcm88690_a0_pkt_txpmd.c @@ -0,0 +1,405 @@ +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides TXPMD access functions for BCM88690_A0. + * + ******************************************************************************/ + +#include +#include + +#define MASK(_bn) (((uint32_t)0x1<<(_bn))-1) +#define WORD_FIELD_GET(_d,_s,_l) (((_d) >> (_s)) & MASK(_l)) +#define WORD_FIELD_SET(_d,_s,_l,_v) (_d)=(((_d) & ~(MASK(_l) << (_s))) | (((_v) & MASK(_l)) << (_s))) +#define WORD_FIELD_MASK(_d,_s,_l) (_d)=((_d) | (MASK(_l) << (_s))) +/******************************************************************************* + * SWFORMAT: TXPMD + * BLOCKS: + * SIZE: 128 + ******************************************************************************/ +static void +bcmpkt_txpmd_start_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[0], 30, 2, val); +} + +static uint32_t +bcmpkt_txpmd_start_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[0], 30, 2); + return val; +} + +static void +bcmpkt_txpmd_pkt_length_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[3], 10, 14, val); +} + +static uint32_t +bcmpkt_txpmd_pkt_length_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[3], 10, 14); + return val; +} + +static void +bcmpkt_txpmd_cpu_tx_src_port_num_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[4], 0, 18, val); +} + +static uint32_t +bcmpkt_txpmd_cpu_tx_src_port_num_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[4], 0, 18); + return val; +} + +static uint32_t +bcmpkt_txpmd_i_size_get( + uint32_t * data, + uint32_t ** addr) +{ + return 0; +} + +const bcmpkt_txpmd_fget_t bcm88690_a0_txpmd_fget = { + { + bcmpkt_txpmd_start_get, + NULL, + bcmpkt_txpmd_pkt_length_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + bcmpkt_txpmd_cpu_tx_src_port_num_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL} +}; + +const bcmpkt_txpmd_fset_t bcm88690_a0_txpmd_fset = { + { + bcmpkt_txpmd_start_set, + NULL, + bcmpkt_txpmd_pkt_length_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + bcmpkt_txpmd_cpu_tx_src_port_num_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL} +}; + +const bcmpkt_txpmd_figet_t bcm88690_a0_txpmd_figet = { + { + bcmpkt_txpmd_i_size_get} +}; + +static shr_enum_map_t bcm88690_a0_txpmd_view_types[] = { + {NULL, -1}, +}; + +/* -2: unsupported, -1: global, others: view's value */ +static int bcm88690_a0_txpmd_view_infos[BCMPKT_TXPMD_FID_COUNT] = { + -1, -2, -1, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -1, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, +}; + +void +bcm88690_a0_txpmd_view_info_get( + bcmpkt_pmd_view_info_t * info) +{ + info->view_infos = bcm88690_a0_txpmd_view_infos; + info->view_types = bcm88690_a0_txpmd_view_types; + info->view_type_get = NULL; +} diff --git a/src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pdma_attach.c b/src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pdma_attach.c new file mode 100644 index 0000000..1d12442 --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pdma_attach.c @@ -0,0 +1,84 @@ +/*! \file bcm88860_a0_pdma_attach.c + * + * Initialize PDMA driver resources. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include + +#ifdef PKTIO_KIMPL +#include "ngknet_adapter.h" + +static pdma_rx_f ngkent_pkt_recv_func = NULL; + +static int +ngknet_dev_pkt_recv( + struct pdma_dev *dev, + int queue, + void *buf) +{ + int rv = 0; + rv = ngknet_adapter_frame_recv(dev, queue, buf); + if (rv < 0) { + return rv; + } + if (ngkent_pkt_recv_func) { + rv = ngkent_pkt_recv_func(dev, queue, buf); + } + return rv; +} +#endif /*PKTIO_KIMPL*/ + +int +bcm88860_a0_cnet_pdma_attach( + struct pdma_dev *dev) +{ + int rv; + rv = bcmcnet_cmicr_pdma_driver_attach(dev); + dev->flags |= PDMA_NO_FCS; +#ifdef PKTIO_KIMPL + if (ngkent_pkt_recv_func == NULL) { + ngkent_pkt_recv_func = dev->pkt_recv; + } + dev->pkt_recv = ngknet_dev_pkt_recv; +#endif /*PKTIO_KIMPL*/ + return rv; +} + +int +bcm88860_a0_cnet_pdma_detach( + struct pdma_dev *dev) +{ + return bcmcnet_cmicr_pdma_driver_detach(dev); +} diff --git a/src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pkt_rxpmd.c b/src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pkt_rxpmd.c new file mode 100644 index 0000000..669a82a --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pkt_rxpmd.c @@ -0,0 +1,439 @@ + /******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides RXPMD access functions for BCM88860_A0. + * + ******************************************************************************/ + +#include +#include +#include + +#define WORD_MASK(_bn) (((uint32_t)0x1<<(_bn))-1) +#define WORD_FIELD_GET(_d,_s,_l) (((_d) >> (_s)) & WORD_MASK(_l)) +#define WORD_FIELD_SET(_d,_s,_l,_v) (_d)=(((_d) & ~(WORD_MASK(_l) << (_s))) | (((_v) & WORD_MASK(_l)) << (_s))) +#define WORD_FIELD_MASK(_d,_s,_l) (_d)=((_d) | (WORD_MASK(_l) << (_s))) + +/******************************************************************************* + * SWFORMAT: RXPMD + * BLOCKS: + * SIZE: 1536 + ******************************************************************************/ +static void +bcmpkt_rxpmd_system_header_length_set( + uint32_t * data, + uint32_t val) +{ + data[0] = val; +} + +static uint32_t +bcmpkt_rxpmd_system_header_length_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[0]; + return val; +} + +static void +bcmpkt_rxpmd_rx_channel_set( + uint32_t * data, + uint32_t val) +{ + data[1] = val; +} + +static uint32_t +bcmpkt_rxpmd_rx_channel_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[1]; + return val; +} + +static void +bcmpkt_rxpmd_ftmh_tc_set( + uint32_t * data, + uint32_t val) +{ + data[2] = val; + return; +} + +static uint32_t +bcmpkt_rxpmd_ftmh_tc_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[2]; + return val; +} + +static void +bcmpkt_rxpmd_ftmh_src_sysport_set( + uint32_t * data, + uint32_t val) +{ + data[3] = val; + return; +} + +static uint32_t +bcmpkt_rxpmd_ftmh_src_sysport_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[3]; + return val; +} + +static void +bcmpkt_rxpmd_internal_trap_code_set( + uint32_t * data, + uint32_t val) +{ + data[4] = val; + return; +} + +static uint32_t +bcmpkt_rxpmd_internal_trap_code_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[4]; + return val; +} + +static void +bcmpkt_rxpmd_internal_trap_qualifier_set( + uint32_t * data, + uint32_t val) +{ + data[5] = val; + return; +} + +static uint32_t +bcmpkt_rxpmd_internal_trap_qualifier_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[5]; + return val; +} + +static uint32_t +bcmpkt_rxpmd_i_size_get( + uint32_t *data, + uint32_t **addr) +{ + return 16; +} + +/******************************************************************************* + * SWFORMAT: RX_REASON + * BLOCKS: + * SIZE: 42 + ******************************************************************************/ +void +bcm88860_a0_rx_reason_encode( + const bcmpkt_rx_reasons_t * reasons, + uint32_t * data) +{ +} + +void +bcm88860_a0_rx_reason_decode( + const uint32_t * data, + bcmpkt_rx_reasons_t * reasons) +{ +} + +void +bcm88860_a0_ep_rx_reason_encode( + const bcmpkt_rx_reasons_t * reasons, + uint32_t * data) +{ +} + +void +bcm88860_a0_ep_rx_reason_decode( + const uint32_t * data, + bcmpkt_rx_reasons_t * reasons) +{ +} + +const bcmpkt_rxpmd_fget_t bcm88860_a0_rxpmd_fget = { +{ + bcmpkt_rxpmd_system_header_length_get, + bcmpkt_rxpmd_rx_channel_get, + bcmpkt_rxpmd_ftmh_tc_get, + bcmpkt_rxpmd_ftmh_src_sysport_get, + bcmpkt_rxpmd_internal_trap_code_get, + bcmpkt_rxpmd_internal_trap_qualifier_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL +} +}; + +const bcmpkt_rxpmd_fset_t bcm88860_a0_rxpmd_fset = { +{ + bcmpkt_rxpmd_system_header_length_set, + bcmpkt_rxpmd_rx_channel_set, + bcmpkt_rxpmd_ftmh_tc_set, + bcmpkt_rxpmd_ftmh_src_sysport_set, + bcmpkt_rxpmd_internal_trap_code_set, + bcmpkt_rxpmd_internal_trap_qualifier_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL +} +}; + +const bcmpkt_rxpmd_figet_t bcm88860_a0_rxpmd_figet = { +{ + bcmpkt_rxpmd_i_size_get, + NULL, + NULL, + NULL +} +}; + +static shr_enum_map_t bcm88860_a0_rxpmd_view_types[] = { + {NULL, -1}, +}; + +/* -2: unsupported, -1: global, others: view's value */ +static int bcm88860_a0_rxpmd_view_infos[BCMPKT_RXPMD_FID_COUNT] = { + -1, -1, -1, -1, -1, -1, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2 +}; + +void +bcm88860_a0_rxpmd_view_info_get( + bcmpkt_pmd_view_info_t * info) +{ + info->view_infos = bcm88860_a0_rxpmd_view_infos; + info->view_types = bcm88860_a0_rxpmd_view_types; + info->view_type_get = NULL; +} diff --git a/src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pkt_rxpmd_dev_field.c b/src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pkt_rxpmd_dev_field.c new file mode 100644 index 0000000..0902514 --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pkt_rxpmd_dev_field.c @@ -0,0 +1,41 @@ +/*! \file bcm88860_a0_pkt_rxpmd_dev_field.c + * + * This file provides RXPMD access functions for BCM56080_A0. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include + +const bcmpkt_rxpmd_func_t bcm88860_a0_rxpmd_func = { 0 }; diff --git a/src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pkt_txpmd.c b/src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pkt_txpmd.c new file mode 100644 index 0000000..5cbcffa --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm88860_a0/bcm88860_a0_pkt_txpmd.c @@ -0,0 +1,405 @@ +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides TXPMD access functions for BCM88860_A0. + * + ******************************************************************************/ + +#include +#include + +#define MASK(_bn) (((uint32_t)0x1<<(_bn))-1) +#define WORD_FIELD_GET(_d,_s,_l) (((_d) >> (_s)) & MASK(_l)) +#define WORD_FIELD_SET(_d,_s,_l,_v) (_d)=(((_d) & ~(MASK(_l) << (_s))) | (((_v) & MASK(_l)) << (_s))) +#define WORD_FIELD_MASK(_d,_s,_l) (_d)=((_d) | (MASK(_l) << (_s))) +/******************************************************************************* + * SWFORMAT: TXPMD + * BLOCKS: + * SIZE: 128 + ******************************************************************************/ +static void +bcmpkt_txpmd_start_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[0], 30, 2, val); +} + +static uint32_t +bcmpkt_txpmd_start_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[0], 30, 2); + return val; +} + +static void +bcmpkt_txpmd_pkt_length_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[3], 10, 14, val); +} + +static uint32_t +bcmpkt_txpmd_pkt_length_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[3], 10, 14); + return val; +} + +static void +bcmpkt_txpmd_cpu_tx_src_port_num_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[4], 0, 18, val); +} + +static uint32_t +bcmpkt_txpmd_cpu_tx_src_port_num_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[4], 0, 18); + return val; +} + +static uint32_t +bcmpkt_txpmd_i_size_get( + uint32_t * data, + uint32_t ** addr) +{ + return 0; +} + +const bcmpkt_txpmd_fget_t bcm88860_a0_txpmd_fget = { + { + bcmpkt_txpmd_start_get, + NULL, + bcmpkt_txpmd_pkt_length_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + bcmpkt_txpmd_cpu_tx_src_port_num_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL} +}; + +const bcmpkt_txpmd_fset_t bcm88860_a0_txpmd_fset = { + { + bcmpkt_txpmd_start_set, + NULL, + bcmpkt_txpmd_pkt_length_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + bcmpkt_txpmd_cpu_tx_src_port_num_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL} +}; + +const bcmpkt_txpmd_figet_t bcm88860_a0_txpmd_figet = { + { + bcmpkt_txpmd_i_size_get} +}; + +static shr_enum_map_t bcm88860_a0_txpmd_view_types[] = { + {NULL, -1}, +}; + +/* -2: unsupported, -1: global, others: view's value */ +static int bcm88860_a0_txpmd_view_infos[BCMPKT_TXPMD_FID_COUNT] = { + -1, -2, -1, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -1, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, +}; + +void +bcm88860_a0_txpmd_view_info_get( + bcmpkt_pmd_view_info_t * info) +{ + info->view_infos = bcm88860_a0_txpmd_view_infos; + info->view_types = bcm88860_a0_txpmd_view_types; + info->view_type_get = NULL; +} diff --git a/src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pdma_attach.c b/src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pdma_attach.c new file mode 100644 index 0000000..9e79c2c --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pdma_attach.c @@ -0,0 +1,84 @@ +/*! \file bcm88920_a0_pdma_attach.c + * + * Initialize PDMA driver resources. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include + +#ifdef PKTIO_KIMPL +#include "ngknet_adapter.h" + +static pdma_rx_f ngkent_pkt_recv_func = NULL; + +static int +ngknet_dev_pkt_recv( + struct pdma_dev *dev, + int queue, + void *buf) +{ + int rv = 0; + rv = ngknet_adapter_frame_recv(dev, queue, buf); + if (rv < 0) { + return rv; + } + if (ngkent_pkt_recv_func) { + rv = ngkent_pkt_recv_func(dev, queue, buf); + } + return rv; +} +#endif /*PKTIO_KIMPL*/ + +int +bcm88920_a0_cnet_pdma_attach( + struct pdma_dev *dev) +{ + int rv; + rv = bcmcnet_cmicr_pdma_driver_attach(dev); + dev->flags |= PDMA_NO_FCS; +#ifdef PKTIO_KIMPL + if (ngkent_pkt_recv_func == NULL) { + ngkent_pkt_recv_func = dev->pkt_recv; + } + dev->pkt_recv = ngknet_dev_pkt_recv; +#endif /*PKTIO_KIMPL*/ + return rv; +} + +int +bcm88920_a0_cnet_pdma_detach( + struct pdma_dev *dev) +{ + return bcmcnet_cmicr_pdma_driver_detach(dev); +} diff --git a/src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pkt_rxpmd.c b/src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pkt_rxpmd.c new file mode 100644 index 0000000..0427b0e --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pkt_rxpmd.c @@ -0,0 +1,367 @@ + /******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides RXPMD access functions for BCM88920_A0. + * + ******************************************************************************/ + +#include +#include +#include + +#define WORD_MASK(_bn) (((uint32_t)0x1<<(_bn))-1) +#define WORD_FIELD_GET(_d,_s,_l) (((_d) >> (_s)) & WORD_MASK(_l)) +#define WORD_FIELD_SET(_d,_s,_l,_v) (_d)=(((_d) & ~(WORD_MASK(_l) << (_s))) | (((_v) & WORD_MASK(_l)) << (_s))) +#define WORD_FIELD_MASK(_d,_s,_l) (_d)=((_d) | (WORD_MASK(_l) << (_s))) + +/******************************************************************************* + * SWFORMAT: RXPMD + * BLOCKS: + * SIZE: 1536 + ******************************************************************************/ +static void +bcmpkt_rxpmd_system_header_length_set( + uint32_t * data, + uint32_t val) +{ + data[0] = val; +} + +static uint32_t +bcmpkt_rxpmd_system_header_length_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[0]; + return val; +} + +static void +bcmpkt_rxpmd_rx_channel_set( + uint32_t * data, + uint32_t val) +{ + data[1] = val; +} + +static uint32_t +bcmpkt_rxpmd_rx_channel_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[1]; + return val; +} + +static uint32_t +bcmpkt_rxpmd_i_size_get( + uint32_t *data, + uint32_t **addr) +{ + return 16; +} + +/******************************************************************************* + * SWFORMAT: RX_REASON + * BLOCKS: + * SIZE: 42 + ******************************************************************************/ +void +bcm88920_a0_rx_reason_encode( + const bcmpkt_rx_reasons_t * reasons, + uint32_t * data) +{ +} + +void +bcm88920_a0_rx_reason_decode( + const uint32_t * data, + bcmpkt_rx_reasons_t * reasons) +{ +} + +void +bcm88920_a0_ep_rx_reason_encode( + const bcmpkt_rx_reasons_t * reasons, + uint32_t * data) +{ +} + +void +bcm88920_a0_ep_rx_reason_decode( + const uint32_t * data, + bcmpkt_rx_reasons_t * reasons) +{ +} + +const bcmpkt_rxpmd_fget_t bcm88920_a0_rxpmd_fget = { +{ + bcmpkt_rxpmd_system_header_length_get, + bcmpkt_rxpmd_rx_channel_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL +} +}; + +const bcmpkt_rxpmd_fset_t bcm88920_a0_rxpmd_fset = { +{ + bcmpkt_rxpmd_system_header_length_set, + bcmpkt_rxpmd_rx_channel_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL +} +}; + +const bcmpkt_rxpmd_figet_t bcm88920_a0_rxpmd_figet = { +{ + bcmpkt_rxpmd_i_size_get, + NULL, + NULL, + NULL +} +}; + +static shr_enum_map_t bcm88920_a0_rxpmd_view_types[] = { + {NULL, -1}, +}; + +/* -2: unsupported, -1: global, others: view's value */ +static int bcm88920_a0_rxpmd_view_infos[BCMPKT_RXPMD_FID_COUNT] = { + -1, -1, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2 +}; + +void +bcm88920_a0_rxpmd_view_info_get( + bcmpkt_pmd_view_info_t * info) +{ + info->view_infos = bcm88920_a0_rxpmd_view_infos; + info->view_types = bcm88920_a0_rxpmd_view_types; + info->view_type_get = NULL; +} diff --git a/src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pkt_rxpmd_dev_field.c b/src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pkt_rxpmd_dev_field.c new file mode 100644 index 0000000..17b9855 --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pkt_rxpmd_dev_field.c @@ -0,0 +1,41 @@ +/*! \file bcm88920_a0_pkt_rxpmd_dev_field.c + * + * This file provides RXPMD access functions for BCM88920_A0. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include + +const bcmpkt_rxpmd_func_t bcm88920_a0_rxpmd_func = { 0 }; diff --git a/src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pkt_txpmd.c b/src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pkt_txpmd.c new file mode 100644 index 0000000..ab19253 --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm88920_a0/bcm88920_a0_pkt_txpmd.c @@ -0,0 +1,405 @@ +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides TXPMD access functions for BCM88920_A0. + * + ******************************************************************************/ + +#include +#include + +#define MASK(_bn) (((uint32_t)0x1<<(_bn))-1) +#define WORD_FIELD_GET(_d,_s,_l) (((_d) >> (_s)) & MASK(_l)) +#define WORD_FIELD_SET(_d,_s,_l,_v) (_d)=(((_d) & ~(MASK(_l) << (_s))) | (((_v) & MASK(_l)) << (_s))) +#define WORD_FIELD_MASK(_d,_s,_l) (_d)=((_d) | (MASK(_l) << (_s))) +/******************************************************************************* + * SWFORMAT: TXPMD + * BLOCKS: + * SIZE: 128 + ******************************************************************************/ +static void +bcmpkt_txpmd_start_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[0], 30, 2, val); +} + +static uint32_t +bcmpkt_txpmd_start_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[0], 30, 2); + return val; +} + +static void +bcmpkt_txpmd_pkt_length_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[3], 10, 14, val); +} + +static uint32_t +bcmpkt_txpmd_pkt_length_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[3], 10, 14); + return val; +} + +static void +bcmpkt_txpmd_cpu_tx_src_port_num_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[4], 0, 18, val); +} + +static uint32_t +bcmpkt_txpmd_cpu_tx_src_port_num_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[4], 0, 18); + return val; +} + +static uint32_t +bcmpkt_txpmd_i_size_get( + uint32_t * data, + uint32_t ** addr) +{ + return 0; +} + +const bcmpkt_txpmd_fget_t bcm88920_a0_txpmd_fget = { + { + bcmpkt_txpmd_start_get, + NULL, + bcmpkt_txpmd_pkt_length_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + bcmpkt_txpmd_cpu_tx_src_port_num_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL} +}; + +const bcmpkt_txpmd_fset_t bcm88920_a0_txpmd_fset = { + { + bcmpkt_txpmd_start_set, + NULL, + bcmpkt_txpmd_pkt_length_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + bcmpkt_txpmd_cpu_tx_src_port_num_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL} +}; + +const bcmpkt_txpmd_figet_t bcm88920_a0_txpmd_figet = { + { + bcmpkt_txpmd_i_size_get} +}; + +static shr_enum_map_t bcm88920_a0_txpmd_view_types[] = { + {NULL, -1}, +}; + +/* -2: unsupported, -1: global, others: view's value */ +static int bcm88920_a0_txpmd_view_infos[BCMPKT_TXPMD_FID_COUNT] = { + -1, -2, -1, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -1, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, +}; + +void +bcm88920_a0_txpmd_view_info_get( + bcmpkt_pmd_view_info_t * info) +{ + info->view_infos = bcm88920_a0_txpmd_view_infos; + info->view_types = bcm88920_a0_txpmd_view_types; + info->view_type_get = NULL; +} diff --git a/src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pdma_attach.c b/src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pdma_attach.c new file mode 100644 index 0000000..2a39abb --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pdma_attach.c @@ -0,0 +1,83 @@ +/*! \file bcm99450_a0_pdma_attach.c + * + * Initialize PDMA driver resources. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include + +#ifdef PKTIO_KIMPL +#include "ngknet_adapter.h" + +static pdma_rx_f ngkent_pkt_recv_func = NULL; + +static int +ngknet_dev_pkt_recv( + struct pdma_dev *dev, + int queue, + void *buf) +{ + int rv = 0; + rv = ngknet_adapter_frame_recv(dev, queue, buf); + if (rv < 0) { + return rv; + } + if (ngkent_pkt_recv_func) { + rv = ngkent_pkt_recv_func(dev, queue, buf); + } + return rv; +} +#endif /*PKTIO_KIMPL*/ + +int +bcm99450_a0_cnet_pdma_attach( + struct pdma_dev *dev) +{ + int rv; + rv = bcmcnet_cmicr2_pdma_driver_attach(dev); +#ifdef PKTIO_KIMPL + if (ngkent_pkt_recv_func == NULL) { + ngkent_pkt_recv_func = dev->pkt_recv; + } + dev->pkt_recv = ngknet_dev_pkt_recv; +#endif /*PKTIO_KIMPL*/ + return rv; +} + +int +bcm99450_a0_cnet_pdma_detach( + struct pdma_dev *dev) +{ + return bcmcnet_cmicr2_pdma_driver_detach(dev); +} diff --git a/src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pkt_rxpmd.c b/src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pkt_rxpmd.c new file mode 100644 index 0000000..53bb21d --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pkt_rxpmd.c @@ -0,0 +1,439 @@ + /******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides RXPMD access functions for BCM99450_A0. + * + ******************************************************************************/ + +#include +#include +#include + +#define WORD_MASK(_bn) (((uint32_t)0x1<<(_bn))-1) +#define WORD_FIELD_GET(_d,_s,_l) (((_d) >> (_s)) & WORD_MASK(_l)) +#define WORD_FIELD_SET(_d,_s,_l,_v) (_d)=(((_d) & ~(WORD_MASK(_l) << (_s))) | (((_v) & WORD_MASK(_l)) << (_s))) +#define WORD_FIELD_MASK(_d,_s,_l) (_d)=((_d) | (WORD_MASK(_l) << (_s))) + +/******************************************************************************* + * SWFORMAT: RXPMD + * BLOCKS: + * SIZE: 1536 + ******************************************************************************/ +static void +bcmpkt_rxpmd_system_header_length_set( + uint32_t * data, + uint32_t val) +{ + data[0] = val; +} + +static uint32_t +bcmpkt_rxpmd_system_header_length_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[0]; + return val; +} + +static void +bcmpkt_rxpmd_rx_channel_set( + uint32_t * data, + uint32_t val) +{ + data[1] = val; +} + +static uint32_t +bcmpkt_rxpmd_rx_channel_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[1]; + return val; +} + +static void +bcmpkt_rxpmd_ftmh_tc_set( + uint32_t * data, + uint32_t val) +{ + data[2] = val; + return; +} + +static uint32_t +bcmpkt_rxpmd_ftmh_tc_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[2]; + return val; +} + +static void +bcmpkt_rxpmd_ftmh_src_sysport_set( + uint32_t * data, + uint32_t val) +{ + data[3] = val; + return; +} + +static uint32_t +bcmpkt_rxpmd_ftmh_src_sysport_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[3]; + return val; +} + +static void +bcmpkt_rxpmd_internal_trap_code_set( + uint32_t * data, + uint32_t val) +{ + data[4] = val; + return; +} + +static uint32_t +bcmpkt_rxpmd_internal_trap_code_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[4]; + return val; +} + +static void +bcmpkt_rxpmd_internal_trap_qualifier_set( + uint32_t * data, + uint32_t val) +{ + data[5] = val; + return; +} + +static uint32_t +bcmpkt_rxpmd_internal_trap_qualifier_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[5]; + return val; +} + +static uint32_t +bcmpkt_rxpmd_i_size_get( + uint32_t *data, + uint32_t **addr) +{ + return 16; +} + +/******************************************************************************* + * SWFORMAT: RX_REASON + * BLOCKS: + * SIZE: 42 + ******************************************************************************/ +void +bcm99450_a0_rx_reason_encode( + const bcmpkt_rx_reasons_t * reasons, + uint32_t * data) +{ +} + +void +bcm99450_a0_rx_reason_decode( + const uint32_t * data, + bcmpkt_rx_reasons_t * reasons) +{ +} + +void +bcm99450_a0_ep_rx_reason_encode( + const bcmpkt_rx_reasons_t * reasons, + uint32_t * data) +{ +} + +void +bcm99450_a0_ep_rx_reason_decode( + const uint32_t * data, + bcmpkt_rx_reasons_t * reasons) +{ +} + +const bcmpkt_rxpmd_fget_t bcm99450_a0_rxpmd_fget = { +{ + bcmpkt_rxpmd_system_header_length_get, + bcmpkt_rxpmd_rx_channel_get, + bcmpkt_rxpmd_ftmh_tc_get, + bcmpkt_rxpmd_ftmh_src_sysport_get, + bcmpkt_rxpmd_internal_trap_code_get, + bcmpkt_rxpmd_internal_trap_qualifier_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL +} +}; + +const bcmpkt_rxpmd_fset_t bcm99450_a0_rxpmd_fset = { +{ + bcmpkt_rxpmd_system_header_length_set, + bcmpkt_rxpmd_rx_channel_set, + bcmpkt_rxpmd_ftmh_tc_set, + bcmpkt_rxpmd_ftmh_src_sysport_set, + bcmpkt_rxpmd_internal_trap_code_set, + bcmpkt_rxpmd_internal_trap_qualifier_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL +} +}; + +const bcmpkt_rxpmd_figet_t bcm99450_a0_rxpmd_figet = { +{ + bcmpkt_rxpmd_i_size_get, + NULL, + NULL, + NULL +} +}; + +static shr_enum_map_t bcm99450_a0_rxpmd_view_types[] = { + {NULL, -1}, +}; + +/* -2: unsupported, -1: global, others: view's value */ +static int bcm99450_a0_rxpmd_view_infos[BCMPKT_RXPMD_FID_COUNT] = { + -1, -1, -1, -1, -1, -1, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2 +}; + +void +bcm99450_a0_rxpmd_view_info_get( + bcmpkt_pmd_view_info_t * info) +{ + info->view_infos = bcm99450_a0_rxpmd_view_infos; + info->view_types = bcm99450_a0_rxpmd_view_types; + info->view_type_get = NULL; +} diff --git a/src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pkt_rxpmd_dev_field.c b/src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pkt_rxpmd_dev_field.c new file mode 100644 index 0000000..d5acd0f --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pkt_rxpmd_dev_field.c @@ -0,0 +1,41 @@ +/*! \file bcm99450_a0_pkt_rxpmd_dev_field.c + * + * This file provides RXPMD access functions for BCM99450_A0. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include + +const bcmpkt_rxpmd_func_t bcm99450_a0_rxpmd_func = { 0 }; diff --git a/src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pkt_txpmd.c b/src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pkt_txpmd.c new file mode 100644 index 0000000..ea7556c --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm99450_a0/bcm99450_a0_pkt_txpmd.c @@ -0,0 +1,405 @@ +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides TXPMD access functions for BCM99450_A0. + * + ******************************************************************************/ + +#include +#include + +#define MASK(_bn) (((uint32_t)0x1<<(_bn))-1) +#define WORD_FIELD_GET(_d,_s,_l) (((_d) >> (_s)) & MASK(_l)) +#define WORD_FIELD_SET(_d,_s,_l,_v) (_d)=(((_d) & ~(MASK(_l) << (_s))) | (((_v) & MASK(_l)) << (_s))) +#define WORD_FIELD_MASK(_d,_s,_l) (_d)=((_d) | (MASK(_l) << (_s))) +/******************************************************************************* + * SWFORMAT: TXPMD + * BLOCKS: + * SIZE: 128 + ******************************************************************************/ +static void +bcmpkt_txpmd_start_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[0], 30, 2, val); +} + +static uint32_t +bcmpkt_txpmd_start_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[0], 30, 2); + return val; +} + +static void +bcmpkt_txpmd_pkt_length_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[3], 10, 14, val); +} + +static uint32_t +bcmpkt_txpmd_pkt_length_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[3], 10, 14); + return val; +} + +static void +bcmpkt_txpmd_cpu_tx_src_port_num_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[4], 0, 18, val); +} + +static uint32_t +bcmpkt_txpmd_cpu_tx_src_port_num_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[4], 0, 18); + return val; +} + +static uint32_t +bcmpkt_txpmd_i_size_get( + uint32_t * data, + uint32_t ** addr) +{ + return 0; +} + +const bcmpkt_txpmd_fget_t bcm99450_a0_txpmd_fget = { + { + bcmpkt_txpmd_start_get, + NULL, + bcmpkt_txpmd_pkt_length_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + bcmpkt_txpmd_cpu_tx_src_port_num_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL} +}; + +const bcmpkt_txpmd_fset_t bcm99450_a0_txpmd_fset = { + { + bcmpkt_txpmd_start_set, + NULL, + bcmpkt_txpmd_pkt_length_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + bcmpkt_txpmd_cpu_tx_src_port_num_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL} +}; + +const bcmpkt_txpmd_figet_t bcm99450_a0_txpmd_figet = { + { + bcmpkt_txpmd_i_size_get} +}; + +static shr_enum_map_t bcm99450_a0_txpmd_view_types[] = { + {NULL, -1}, +}; + +/* -2: unsupported, -1: global, others: view's value */ +static int bcm99450_a0_txpmd_view_infos[BCMPKT_TXPMD_FID_COUNT] = { + -1, -2, -1, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -1, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, +}; + +void +bcm99450_a0_txpmd_view_info_get( + bcmpkt_pmd_view_info_t * info) +{ + info->view_infos = bcm99450_a0_txpmd_view_infos; + info->view_types = bcm99450_a0_txpmd_view_types; + info->view_type_get = NULL; +} diff --git a/src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pdma_attach.c b/src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pdma_attach.c new file mode 100644 index 0000000..878c147 --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pdma_attach.c @@ -0,0 +1,83 @@ +/*! \file bcm99470_a0_pdma_attach.c + * + * Initialize PDMA driver resources. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include + +#ifdef PKTIO_KIMPL +#include "ngknet_adapter.h" + +static pdma_rx_f ngkent_pkt_recv_func = NULL; + +static int +ngknet_dev_pkt_recv( + struct pdma_dev *dev, + int queue, + void *buf) +{ + int rv = 0; + rv = ngknet_adapter_frame_recv(dev, queue, buf); + if (rv < 0) { + return rv; + } + if (ngkent_pkt_recv_func) { + rv = ngkent_pkt_recv_func(dev, queue, buf); + } + return rv; +} +#endif /*PKTIO_KIMPL*/ + +int +bcm99470_a0_cnet_pdma_attach( + struct pdma_dev *dev) +{ + int rv; + rv = bcmcnet_cmicr2_pdma_driver_attach(dev); +#ifdef PKTIO_KIMPL + if (ngkent_pkt_recv_func == NULL) { + ngkent_pkt_recv_func = dev->pkt_recv; + } + dev->pkt_recv = ngknet_dev_pkt_recv; +#endif /*PKTIO_KIMPL*/ + return rv; +} + +int +bcm99470_a0_cnet_pdma_detach( + struct pdma_dev *dev) +{ + return bcmcnet_cmicr2_pdma_driver_detach(dev); +} diff --git a/src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pkt_rxpmd.c b/src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pkt_rxpmd.c new file mode 100644 index 0000000..1c4f9c5 --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pkt_rxpmd.c @@ -0,0 +1,367 @@ + /******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides RXPMD access functions for BCM99470_A0. + * + ******************************************************************************/ + +#include +#include +#include + +#define WORD_MASK(_bn) (((uint32_t)0x1<<(_bn))-1) +#define WORD_FIELD_GET(_d,_s,_l) (((_d) >> (_s)) & WORD_MASK(_l)) +#define WORD_FIELD_SET(_d,_s,_l,_v) (_d)=(((_d) & ~(WORD_MASK(_l) << (_s))) | (((_v) & WORD_MASK(_l)) << (_s))) +#define WORD_FIELD_MASK(_d,_s,_l) (_d)=((_d) | (WORD_MASK(_l) << (_s))) + +/******************************************************************************* + * SWFORMAT: RXPMD + * BLOCKS: + * SIZE: 1536 + ******************************************************************************/ +static void +bcmpkt_rxpmd_system_header_length_set( + uint32_t * data, + uint32_t val) +{ + data[0] = val; +} + +static uint32_t +bcmpkt_rxpmd_system_header_length_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[0]; + return val; +} + +static void +bcmpkt_rxpmd_rx_channel_set( + uint32_t * data, + uint32_t val) +{ + data[1] = val; +} + +static uint32_t +bcmpkt_rxpmd_rx_channel_get( + uint32_t * data) +{ + uint32_t val = 0; + val = data[1]; + return val; +} + +static uint32_t +bcmpkt_rxpmd_i_size_get( + uint32_t *data, + uint32_t **addr) +{ + return 16; +} + +/******************************************************************************* + * SWFORMAT: RX_REASON + * BLOCKS: + * SIZE: 42 + ******************************************************************************/ +void +bcm99470_a0_rx_reason_encode( + const bcmpkt_rx_reasons_t * reasons, + uint32_t * data) +{ +} + +void +bcm99470_a0_rx_reason_decode( + const uint32_t * data, + bcmpkt_rx_reasons_t * reasons) +{ +} + +void +bcm99470_a0_ep_rx_reason_encode( + const bcmpkt_rx_reasons_t * reasons, + uint32_t * data) +{ +} + +void +bcm99470_a0_ep_rx_reason_decode( + const uint32_t * data, + bcmpkt_rx_reasons_t * reasons) +{ +} + +const bcmpkt_rxpmd_fget_t bcm99470_a0_rxpmd_fget = { +{ + bcmpkt_rxpmd_system_header_length_get, + bcmpkt_rxpmd_rx_channel_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL +} +}; + +const bcmpkt_rxpmd_fset_t bcm99470_a0_rxpmd_fset = { +{ + bcmpkt_rxpmd_system_header_length_set, + bcmpkt_rxpmd_rx_channel_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL +} +}; + +const bcmpkt_rxpmd_figet_t bcm99470_a0_rxpmd_figet = { +{ + bcmpkt_rxpmd_i_size_get, + NULL, + NULL, + NULL +} +}; + +static shr_enum_map_t bcm99470_a0_rxpmd_view_types[] = { + {NULL, -1}, +}; + +/* -2: unsupported, -1: global, others: view's value */ +static int bcm99470_a0_rxpmd_view_infos[BCMPKT_RXPMD_FID_COUNT] = { + -1, -1, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2 +}; + +void +bcm99470_a0_rxpmd_view_info_get( + bcmpkt_pmd_view_info_t * info) +{ + info->view_infos = bcm99470_a0_rxpmd_view_infos; + info->view_types = bcm99470_a0_rxpmd_view_types; + info->view_type_get = NULL; +} diff --git a/src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pkt_rxpmd_dev_field.c b/src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pkt_rxpmd_dev_field.c new file mode 100644 index 0000000..fd19892 --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pkt_rxpmd_dev_field.c @@ -0,0 +1,41 @@ +/*! \file bcm99470_a0_pkt_rxpmd_dev_field.c + * + * This file provides RXPMD access functions for BCM99470_A0. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include + +const bcmpkt_rxpmd_func_t bcm99470_a0_rxpmd_func = { 0 }; diff --git a/src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pkt_txpmd.c b/src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pkt_txpmd.c new file mode 100644 index 0000000..d8684ed --- /dev/null +++ b/src/bcm/common/pktio/chip/bcm99470_a0/bcm99470_a0_pkt_txpmd.c @@ -0,0 +1,405 @@ +/******************************************************************************* + * + * DO NOT EDIT THIS FILE! + * This file is auto-generated from the registers file. + * Edits to this file will be lost when it is regenerated. + * + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + * + * This file provides TXPMD access functions for BCM99470_A0. + * + ******************************************************************************/ + +#include +#include + +#define MASK(_bn) (((uint32_t)0x1<<(_bn))-1) +#define WORD_FIELD_GET(_d,_s,_l) (((_d) >> (_s)) & MASK(_l)) +#define WORD_FIELD_SET(_d,_s,_l,_v) (_d)=(((_d) & ~(MASK(_l) << (_s))) | (((_v) & MASK(_l)) << (_s))) +#define WORD_FIELD_MASK(_d,_s,_l) (_d)=((_d) | (MASK(_l) << (_s))) +/******************************************************************************* + * SWFORMAT: TXPMD + * BLOCKS: + * SIZE: 128 + ******************************************************************************/ +static void +bcmpkt_txpmd_start_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[0], 30, 2, val); +} + +static uint32_t +bcmpkt_txpmd_start_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[0], 30, 2); + return val; +} + +static void +bcmpkt_txpmd_pkt_length_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[3], 10, 14, val); +} + +static uint32_t +bcmpkt_txpmd_pkt_length_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[3], 10, 14); + return val; +} + +static void +bcmpkt_txpmd_cpu_tx_src_port_num_set( + uint32_t * data, + uint32_t val) +{ + WORD_FIELD_SET(data[4], 0, 18, val); +} + +static uint32_t +bcmpkt_txpmd_cpu_tx_src_port_num_get( + uint32_t * data) +{ + uint32_t val; + val = WORD_FIELD_GET(data[4], 0, 18); + return val; +} + +static uint32_t +bcmpkt_txpmd_i_size_get( + uint32_t * data, + uint32_t ** addr) +{ + return 0; +} + +const bcmpkt_txpmd_fget_t bcm99470_a0_txpmd_fget = { + { + bcmpkt_txpmd_start_get, + NULL, + bcmpkt_txpmd_pkt_length_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + bcmpkt_txpmd_cpu_tx_src_port_num_get, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL} +}; + +const bcmpkt_txpmd_fset_t bcm99470_a0_txpmd_fset = { + { + bcmpkt_txpmd_start_set, + NULL, + bcmpkt_txpmd_pkt_length_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + bcmpkt_txpmd_cpu_tx_src_port_num_set, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL} +}; + +const bcmpkt_txpmd_figet_t bcm99470_a0_txpmd_figet = { + { + bcmpkt_txpmd_i_size_get} +}; + +static shr_enum_map_t bcm99470_a0_txpmd_view_types[] = { + {NULL, -1}, +}; + +/* -2: unsupported, -1: global, others: view's value */ +static int bcm99470_a0_txpmd_view_infos[BCMPKT_TXPMD_FID_COUNT] = { + -1, -2, -1, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -1, -2, -2, -2, -2, -2, -2, -2, -2, + -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, + -2, +}; + +void +bcm99470_a0_txpmd_view_info_get( + bcmpkt_pmd_view_info_t * info) +{ + info->view_infos = bcm99470_a0_txpmd_view_infos; + info->view_types = bcm99470_a0_txpmd_view_types; + info->view_type_get = NULL; +} diff --git a/src/bcm/common/pktio/pktio_dep.h b/src/bcm/common/pktio/pktio_dep.h new file mode 100644 index 0000000..ac0e348 --- /dev/null +++ b/src/bcm/common/pktio/pktio_dep.h @@ -0,0 +1,401 @@ +/* + * + * PKTIO dependencies. + * + * Shim layer for resolving compatibilities between SDK6 and imported modules. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef _PKTIO_DEP_H_ +#define _PKTIO_DEP_H_ + +#ifdef PKTIO_KIMPL +#include +#include +#endif /* PKTIO_KIMPL */ +#ifndef PKTIO_KIMPL +#include +#include +#include +#include +#include +#include +#include +#endif /* PKTIO_KIMPL */ +#include +#include +#ifndef PKTIO_KIMPL +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +/* + * Basic types + */ +#ifdef LONGS_ARE_64BITS +typedef unsigned long int uint64_t; +#else +typedef long long unsigned int uint64_t; +#endif +typedef unsigned int uint32_t; +typedef unsigned short uint16_t; +typedef unsigned char uint8_t; +typedef enum { false = 0, true = 1 } bool; + +typedef unsigned int dma_addr_t; + +/* + * SAL + */ +#define SAL_SEM_FOREVER sal_sem_FOREVER +#define SAL_SEM_BINARY sal_sem_BINARY +#define SAL_SEM_COUNTING sal_sem_COUNTING +#define SAL_MUTEX_FOREVER sal_mutex_FOREVER +#define SAL_MUTEX_NOWAIT sal_mutex_NOWAIT + +#define PRId32 "d" +#define PRIx32 "x" +#define PRIu32 "u" +#ifdef LONGS_ARE_64BITS +#define PRIu64 "lu" +#else +#define PRIu64 "llu" +#endif + +#define SAL_CONFIG_MEMORY_BARRIER ; +#endif /* PKTIO_KIMPL */ + +/* + * SHR + */ +typedef _shr_error_t shr_error_t; +#define SHR_E_NONE _SHR_E_NONE +#define SHR_E_INTERNAL _SHR_E_INTERNAL +#define SHR_E_MEMORY _SHR_E_MEMORY +#define SHR_E_UNIT _SHR_E_UNIT +#define SHR_E_PARAM _SHR_E_PARAM +#define SHR_E_EMPTY _SHR_E_EMPTY +#define SHR_E_FULL _SHR_E_FULL +#define SHR_E_NOT_FOUND _SHR_E_NOT_FOUND +#define SHR_E_EXISTS _SHR_E_EXISTS +#define SHR_E_TIMEOUT _SHR_E_TIMEOUT +#define SHR_E_BUSY _SHR_E_BUSY +#define SHR_E_FAIL _SHR_E_FAIL +#define SHR_E_DISABLED _SHR_E_DISABLED +#define SHR_E_BADID _SHR_E_BADID +#define SHR_E_RESOURCE _SHR_E_RESOURCE +#define SHR_E_CONFIG _SHR_E_CONFIG +#define SHR_E_UNAVAIL _SHR_E_UNAVAIL +#define SHR_E_INIT _SHR_E_INIT +#define SHR_E_PORT _SHR_E_PORT +#define SHR_E_IO _SHR_E_IO +#define SHR_E_ACCESS _SHR_E_ACCESS +#define SHR_E_NO_HANDLER _SHR_E_NO_HANDLER +#define SHR_E_PARTIAL _SHR_E_PARTIAL + +/*! Ethernet MAC address length. */ +#define SHR_MAC_ADDR_LEN 6 +/*! Ethernet MAC address type. */ +typedef uint8_t shr_mac_t[SHR_MAC_ADDR_LEN]; + +#ifndef PKTIO_KIMPL + +#if defined(LE_HOST) +#ifndef shr_htonl +#define shr_htonl(_l) _shr_swap32(_l) +#endif +#ifndef shr_ntohl +#define shr_ntohl(_l) _shr_swap32(_l) +#endif +#else +#ifndef shr_htonl +#define shr_htonl(_l) (_l) +#endif +#ifndef shr_ntohl +#define shr_ntohl(_l) (_l) +#endif +#endif + +#ifdef SHR_BYTES2WORDS +#undef SHR_BYTES2WORDS +#endif +#define SHR_BYTES2WORDS BYTES2WORDS + +#ifdef LOG_ERROR_EX +#undef LOG_ERROR_EX +#endif +#define LOG_ERROR_EX(_log_module,_format_string, _p1,_p2,_p3,_p4) \ + if (bsl_fast_check(_log_module|BSL_ERROR)) \ + { \ + sal_printf("\r\n") ; \ + } \ + LOG_ERROR(_log_module, \ + (BSL_META_U(_func_unit,_format_string),_p1,_p2,_p3,_p4) ) + +#ifdef LOG_WARN_EX +#undef LOG_WARN_EX +#endif +#define LOG_WARN_EX(_log_module,_format_string, _p1,_p2,_p3,_p4) \ + if (bsl_fast_check(_log_module|BSL_WARN)) \ + { \ + sal_printf("\r\n") ; \ + } \ + LOG_WARN(_log_module, \ + (BSL_META_U(_func_unit,_format_string),_p1,_p2,_p3,_p4) ) + +#ifdef SHR_FUNC_INIT_VARS +#undef SHR_FUNC_INIT_VARS +#endif +#define SHR_FUNC_INIT_VARS(_unit) \ + int _func_unit = _unit ; \ + int _func_rv = _SHR_E_NONE ; \ + COMPILER_REFERENCE(_func_unit) + +#define SHR_FUNC_ENTER(_unit) SHR_FUNC_INIT_VARS(_unit) + +#undef SHR_FUNC_EXIT +#define SHR_FUNC_EXIT() return _func_rv + +#define SHR_RETURN_VAL_EXIT(_expr) \ + do { \ + _func_rv = _expr; \ + SHR_EXIT(); \ + } while (0) + +#ifdef SHR_IF_ERR_EXIT +#undef SHR_IF_ERR_EXIT +#endif +#define SHR_IF_ERR_EXIT(_expr) \ +do \ +{ \ + int _rv = _expr; \ + if (_rv < 0) \ + { \ + LOG_ERROR_EX(BSL_LOG_MODULE, \ + " Error '%d' indicated ; %s%s%s\r\n" , \ + _rv ,"","","") ; \ + _func_rv = _rv ; \ + SHR_EXIT() ; \ + } \ +} while (0) + +#ifdef SHR_IF_ERR_EXIT_EXCEPT_IF +#undef SHR_IF_ERR_EXIT_EXCEPT_IF +#endif +#define SHR_IF_ERR_EXIT_EXCEPT_IF(_expr, _rv_except) \ +{ \ + int _rv = _expr ; \ + if (SHR_FAILURE(_rv) && _rv != _rv_except) \ + { \ + LOG_ERROR_EX(BSL_LOG_MODULE, \ + " Error '%d' indicated ; %s%s%s\r\n" , \ + _rv ,"","","") ; \ + _func_rv = _rv ; \ + SHR_EXIT() ; \ + } \ +} + +#ifdef SHR_ERR_EXIT +#undef SHR_ERR_EXIT +#endif +#define SHR_ERR_EXIT(_rv) SHR_RETURN_VAL_EXIT(_rv) + +#ifdef SHR_EXIT +#undef SHR_EXIT +#endif +#define SHR_EXIT() goto exit + +#define SHR_IF_ERR_MSG_EXIT(_expr, _stuff) \ + do { \ + int _tmp_rv = _expr; \ + if (_tmp_rv < 0) { \ + LOG_ERROR(BSL_LOG_MODULE, _stuff); \ + _func_rv = _tmp_rv; \ + SHR_EXIT(); \ + } \ + } while(0) + +#define SHR_IF_ERR_VERBOSE_EXIT(_expr) \ + do { \ + int _tmp_rv = _expr; \ + if (_tmp_rv < 0) { \ + LOG_VERBOSE(BSL_LOG_MODULE, \ + (BSL_META_U(_func_unit, "%d\n"), \ + _tmp_rv)); \ + _func_rv = _tmp_rv; \ + SHR_EXIT(); \ + } \ + } while(0) + +#define SHR_IF_ERR_VERBOSE_MSG_EXIT(_expr, _stuff) \ + do { \ + int _tmp_rv = _expr; \ + if (_tmp_rv < 0) { \ + LOG_VERBOSE(BSL_LOG_MODULE, _stuff); \ + _func_rv = _tmp_rv; \ + SHR_EXIT(); \ + } \ + } while(0) + +#ifdef SHR_ERR_MSG_EXIT +#undef SHR_ERR_MSG_EXIT +#endif +#define SHR_ERR_MSG_EXIT SHR_IF_ERR_MSG_EXIT + +#define SHR_NULL_VERBOSE_CHECK(_ptr, _rv) \ + do { \ + if ((_ptr) == NULL) { \ + LOG_VERBOSE(BSL_LOG_MODULE, \ + (BSL_META_U(_func_unit, \ + "null\n"))); \ + _func_rv = _rv; \ + SHR_EXIT(); \ + } \ + } while (0) + +#undef SHR_NULL_CHECK +#define SHR_NULL_CHECK(_ptr, _rv) \ + do { \ + if ((_ptr) == NULL) { \ + LOG_ERROR(BSL_LOG_MODULE, \ + (BSL_META_U(_func_unit, \ + "null\n"))); \ + _func_rv = _rv; \ + SHR_EXIT(); \ + } \ + /* Coverity: the dead code is empty */ \ + /* coverity[dead_error_line:FALSE] */ \ + } while (0) + +#undef SHR_ALLOC +#define SHR_ALLOC(_ptr, _sz, _str) \ + do { \ + if ((_ptr) == NULL) { \ + (_ptr) = sal_alloc(_sz, _str); \ + } else { \ + LOG_ERROR(BSL_LOG_MODULE, \ + (BSL_META_U(_func_unit, \ + "not null (%s)\n"), \ + _str)); \ + SHR_EXIT(); \ + } \ + } while (0) + +#ifdef SHR_FREE +#undef SHR_FREE +#endif +#define SHR_FREE(_ptr) \ +{ \ + if ((_ptr) != NULL) \ + { \ + sal_free((void *)(_ptr)) ; \ + (_ptr) = NULL ; \ + } \ +} +#endif /* PKTIO_KIMPL */ + +#ifdef SHR_FAILURE +#undef SHR_FAILURE +#endif +#define SHR_FAILURE(_expr) ((_expr) < 0) + +#ifdef SHR_SUCCESS +#undef SHR_SUCCESS +#endif +#define SHR_SUCCESS(_expr) ((_expr) >= 0) + +#ifndef PKTIO_KIMPL +#ifdef SHR_FUNC_ERR +#undef SHR_FUNC_ERR +#endif +#define SHR_FUNC_ERR() SHR_FAILURE(_func_rv) + +#ifdef SHR_FUNC_VAL_IS +#undef SHR_FUNC_VAL_IS +#endif +#define SHR_FUNC_VAL_IS(_rv) (_func_rv == (_rv)) + +#ifdef SHR_IF_ERR_CONT +#undef SHR_IF_ERR_CONT +#endif +#define SHR_IF_ERR_CONT(_expr) \ +{ \ + int _rv = _expr; \ + if (SHR_FAILURE(_rv)) \ + { \ + LOG_WARN_EX(BSL_LOG_MODULE, \ + " Warning '%d' indicated ; %s%s%s\r\n" , \ + _rv ,"","","") ; \ + _func_rv = _rv ; \ + } \ +} +#endif /* PKTIO_KIMPL */ + +typedef struct shr_enum_map_s { + + /*! Enum name. */ + char *name; + + /*! Enum value. */ + int val; + +} shr_enum_map_t; + +#ifndef PKTIO_KIMPL +/* + * BSL + */ +#define LOG_CHECK_VERBOSE(ls_) LOG_CHECK(ls_|BSL_VERBOSE) + +#ifdef INVALIDr +#undef INVALIDr +#endif + +#ifdef INVALIDm +#undef INVALIDm +#endif + +#ifdef INVALIDf +#undef INVALIDf +#endif + +#define PKTIO_STR_LEN_MAX 128 +#endif /* PKTIO_KIMPL */ +#endif /* _PKTIO_DEP_H_ */ diff --git a/systems/bde/linux/include/linux-bde.h b/systems/bde/linux/include/linux-bde.h index d2257eb..d520d54 100644 --- a/systems/bde/linux/include/linux-bde.h +++ b/systems/bde/linux/include/linux-bde.h @@ -2,7 +2,7 @@ * * $Id: linux-bde.h,v 1.24 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. @@ -270,6 +270,7 @@ extern linux_bde_device_bitmap_t* lkbde_get_inst_devs(uint32 inst_id); extern int lkbde_irq_mask_set(int d, uint32 addr, uint32 mask, uint32 fmask); extern int lkbde_irq_mask_get(int d, uint32 *mask, uint32 *fmask); extern int lkbde_irq_status_get(int d, uint32_t addr, uint32 *status); +extern int lkbde_irq_clear_set(int d, uint32 addr); #ifdef BCM_SAND_SUPPORT extern int lkbde_cpu_write(int d, uint32 addr, uint32 *buf); @@ -298,6 +299,10 @@ extern void _update_apis_for_sram_dma(); #endif extern void lkbde_get_sram_dma_info(unsigned d, uint32 *sram_start, uint32 *sram_size); #endif /* INCLUDE_SRAM_DMA */ + +#ifdef INCLUDE_CPU_I2C +extern void lkbde_get_i2c_info(int d, uint32 *i2c_bus, uint32 *i2c_dev, uint32 *use_default); +#endif /* * This flag must be OR'ed onto the device number when calling * interrupt_connect/disconnect and irq_mask_set functions from diff --git a/systems/bde/linux/include/linux_dma.h b/systems/bde/linux/include/linux_dma.h index f408b62..70a7a5c 100644 --- a/systems/bde/linux/include/linux_dma.h +++ b/systems/bde/linux/include/linux_dma.h @@ -2,7 +2,7 @@ * * $Id: linux_dma.h,v 1.24 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/bde/linux/include/mpool.h b/systems/bde/linux/include/mpool.h index 1823bbd..fcf6c60 100644 --- a/systems/bde/linux/include/mpool.h +++ b/systems/bde/linux/include/mpool.h @@ -1,7 +1,7 @@ /* * $Id: mpool.h,v 1.2 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/bde/linux/kernel/Makefile b/systems/bde/linux/kernel/Makefile index 320f7bc..2b14881 100644 --- a/systems/bde/linux/kernel/Makefile +++ b/systems/bde/linux/kernel/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.18 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/bde/linux/kernel/linux-kernel-bde.c b/systems/bde/linux/kernel/linux-kernel-bde.c index 5a87699..e50b1ac 100644 --- a/systems/bde/linux/kernel/linux-kernel-bde.c +++ b/systems/bde/linux/kernel/linux-kernel-bde.c @@ -1,6 +1,6 @@ /* * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. @@ -204,6 +204,13 @@ MODULE_PARM_DESC(spifreq, #endif +#define I2C_NO_ID 0x7fffffff + +/* module param for adding dummy switch devices */ +static char *dummy_devices; +LKM_MOD_PARAM(dummy_devices, "s", charp, 0); +MODULE_PARM_DESC(dummy_devices, +"List of dummy switch devices to be added. Input format (devid=%x revid=%x type=%x unique_id=%x [i2c_bus=%x i2c_device=%x]"); /* Periodic timer to prevent stuck interrupt */ static int isrtickms = 1000; @@ -415,6 +422,10 @@ typedef struct bde_ctrl_s { uint32 dev_sram_dma_start; /* start address of device SRAM used for DMA */ uint32 dev_sram_dma_size; /* size in bytes of device SRAM used for DMA */ #endif /* INCLUDE_SRAM_DMA */ +#ifdef INCLUDE_CPU_I2C + uint32 i2c_bus; + uint32 i2c_dev; +#endif /* INCLUDE_CPU_I2C */ } bde_ctrl_t; static bde_ctrl_t _devices[LINUX_BDE_MAX_DEVICES]; @@ -433,6 +444,7 @@ static int _ether_ndevices = 0; static int _cpu_ndevices = 0; #define VALID_DEVICE(_n) ((_n >= 0) && (_n < _ndevices)) +#define REMOVED_DEVICE(_n) (_devices[_n].dev_state == BDE_DEV_STATE_REMOVED) #if defined(IPROC_CMICD) && defined(CONFIG_OF) #define ICFG_CHIP_ID_REG 0x10236000 @@ -1280,20 +1292,6 @@ static const struct pci_device_id _id_table[] = { { BROADCOM_VENDOR_ID, BCM56801_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, { BROADCOM_VENDOR_ID, BCM56802_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, { BROADCOM_VENDOR_ID, BCM56803_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56630_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56634_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56636_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56638_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56639_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56538_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56520_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56521_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56522_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56524_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56526_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56534_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56331_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, - { BROADCOM_VENDOR_ID, BCM56333_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, { BROADCOM_VENDOR_ID, BCM56534_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, { BROADCOM_VENDOR_ID, BCM56334_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, { BROADCOM_VENDOR_ID, BCM56320_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, @@ -1806,6 +1804,19 @@ static const struct pci_device_id _id_table[] = { { BROADCOM_VENDOR_ID, Q4D_DEVICE_ID + 9, PCI_ANY_ID, PCI_ANY_ID }, #endif +#ifdef BCM_Q4DL_SUPPORT + { BROADCOM_VENDOR_ID, Q4DL_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, + { BROADCOM_VENDOR_ID, Q4DL_DEVICE_ID + 1, PCI_ANY_ID, PCI_ANY_ID }, + { BROADCOM_VENDOR_ID, Q4DL_DEVICE_ID + 2, PCI_ANY_ID, PCI_ANY_ID }, + { BROADCOM_VENDOR_ID, Q4DL_DEVICE_ID + 3, PCI_ANY_ID, PCI_ANY_ID }, + { BROADCOM_VENDOR_ID, Q4DL_DEVICE_ID + 4, PCI_ANY_ID, PCI_ANY_ID }, + { BROADCOM_VENDOR_ID, Q4DL_DEVICE_ID + 5, PCI_ANY_ID, PCI_ANY_ID }, + { BROADCOM_VENDOR_ID, Q4DL_DEVICE_ID + 6, PCI_ANY_ID, PCI_ANY_ID }, + { BROADCOM_VENDOR_ID, Q4DL_DEVICE_ID + 7, PCI_ANY_ID, PCI_ANY_ID }, + { BROADCOM_VENDOR_ID, Q4DL_DEVICE_ID + 8, PCI_ANY_ID, PCI_ANY_ID }, + { BROADCOM_VENDOR_ID, Q4DL_DEVICE_ID + 9, PCI_ANY_ID, PCI_ANY_ID }, +#endif + #ifdef BCM_J4L_SUPPORT { BROADCOM_VENDOR_ID, J4L_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, @@ -1821,6 +1832,8 @@ static const struct pci_device_id _id_table[] = { #endif + + #endif #endif /* BCM_DNX_SUPPORT */ #ifdef BCM_DFE_SUPPORT @@ -2693,6 +2706,10 @@ _pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) ctrl->dev_type |= BDE_SWITCH_DEV_TYPE; ctrl->domain_no = pci_domain_nr(dev->bus); ctrl->bus_no = dev->bus->number; +#ifdef INCLUDE_CPU_I2C + ctrl->i2c_bus = I2C_NO_ID; + ctrl->i2c_dev = I2C_NO_ID; +#endif ctrl->dev_state = BDE_DEV_STATE_NORMAL; add_dev = 1; } @@ -3118,6 +3135,17 @@ _pci_remove(struct pci_dev* dev) /* Unused device */ return; } + +#ifdef CONFIG_PCI_MSI + /* Stop the ISR tick timer BEFORE setting dev_state + * This prevents the timer from firing after memory is unmapped */ + if (ctrl->intr_pending && ctrl->use_msi >= PCI_USE_INT_MSI + && ctrl->timer_active) { + ctrl->timer_active = 0; + del_timer_sync(&ctrl->isr_tick); + } +#endif + ctrl->dev_state = BDE_DEV_STATE_REMOVED; if (debug >= 1) { gprintk("PCI device %04x:%04x is removed. \n", @@ -3141,11 +3169,6 @@ _pci_remove(struct pci_dev* dev) } } #ifdef CONFIG_PCI_MSI - if (ctrl->intr_pending && ctrl->use_msi >= PCI_USE_INT_MSI && ctrl->timer_active) { - ctrl->timer_active = 0; - del_timer_sync(&ctrl->isr_tick); - } - _msi_disconnect(ctrl); #endif @@ -3157,9 +3180,11 @@ _pci_remove(struct pci_dev* dev) if (ctrl->bde_dev.base_address1) { iounmap((void *)ctrl->bde_dev.base_address1); + ctrl->bde_dev.base_address1 = 0; } if (ctrl->bde_dev.base_address) { iounmap((void *)ctrl->bde_dev.base_address); + ctrl->bde_dev.base_address = 0; } } @@ -3316,7 +3341,89 @@ probe_plx_local_bus(void) #endif /* BCM_PLX9656_LOCAL_BUS */ +/* + * Add a dummy (non-real) switch device used for testing the BDE. + * Returns zero on success. + */ +static int +add_dummy_switch_device(uint16 device_id, uint8 revision_id, uint32 dev_type, uint32 unique_id, uint32 i2c_bus, uint32 i2c_device) +{ + bde_ctrl_t *ctrl = _devices + _ndevices; +#ifdef INCLUDE_SRAM_DMA + uint32 icfg_rts_straps_addr = 0, iproc_version = 0; +#endif + + if (_ndevices >= LINUX_BDE_MAX_DEVICES) return -1; + + ctrl->dev_type = dev_type; + ctrl->pci_device = NULL; /* No PCI bus */ + ctrl->bde_dev.base_address = 0; + ctrl->iowin[0].addr = 0; + ctrl->iowin[0].size = 0; + ctrl->bde_dev.device = device_id; + ctrl->bde_dev.rev = revision_id; + ctrl->bde_dev.dev_unique_id = unique_id; +#ifdef INCLUDE_CPU_I2C + ctrl->i2c_bus = i2c_bus; + ctrl->i2c_dev = i2c_device; +#endif + +#ifdef INCLUDE_SRAM_DMA + /* Check if the device should use SRAM for DMA, if so configure the SRAM to be used */ + if (use_sram_for_dma) { + switch (device_id & DNXC_DEVID_FAMILY_MASK) { + case RAMON2_DEVICE_ID: /* Mark the device as user type if SRAM mode RM2/3 */ + case RAMON3_DEVICE_ID: + case JERICHO3_DEVICE_ID: + case J3AI_DEVICE_ID: + case Q3D_DEVICE_ID: +#ifdef BCM_Q3A_SUPPORT + case Q3A_DEVICE_ID: + case Q3U_DEVICE_ID: +#endif + iproc_version = 20; + break; + + case JERICHO4_DEVICE_ID: + case Q4_DEVICE_ID: + case Q4D_DEVICE_ID: + case J4L_DEVICE_ID: + iproc_version = 21; + break; + default: + gprintk("Error: device 0x%x does not support SRAMDMA access\n", device_id); + } + + if (iproc_version == 20) { + icfg_rts_straps_addr = 0x2920034; + } else if (iproc_version >= 21) { + icfg_rts_straps_addr = 0x2920030; + } + + if (icfg_rts_straps_addr) { + if ((shbde_iproc_pci_read(&ctrl->shbde, (void *)ctrl->bde_dev.base_address1, icfg_rts_straps_addr) & 2) != 0) { + ctrl->dev_sram_dma_start = 0x38100000; + ctrl->dev_sram_dma_size = 0x400000; /* 4MB */ + } else { /* Use free M0SSQ SRAM */ + ctrl->dev_sram_dma_start = 0x2070000; + ctrl->dev_sram_dma_size = 0x10000; /* 64KB */ + } + + ctrl->dev_type |= BDE_USER_DEV_TYPE; /* Mark as user defined access for BDE handling access to BARs */ + if (debug >= 4) { + gprintk("PCI device 0x%x using SRAM DMA at 0x%x size 0x%x dev_type=0x%x dev=%u\n", device_id, + ctrl->dev_sram_dma_start, ctrl->dev_sram_dma_size, ctrl->dev_type, (unsigned)(ctrl - _devices)); + } + } else { + ctrl->dev_sram_dma_start = ctrl->dev_sram_dma_size = 0; + } + } +#endif /* INCLUDE_SRAM_DMA */ + + _bde_add_device(); + return 0; +} @@ -3453,6 +3560,36 @@ _init(void) } + /* If argument was provided, add dummy devices according to it */ + if (dummy_devices) { + char *token; + unsigned int devid = 0, revid = 0, devtype = 0, unique_id = 0; + unsigned int i2c_bus = I2C_NO_ID, i2c_device = I2C_NO_ID; + + gprintk("dummy device to add: %s\n", dummy_devices); + token = strtok(dummy_devices, ";"); + while (token) { + _parse_eb_args(token, "devid=%x,revid=%x,type=%x,unique_id=%x,i2c_bus=%x,i2c_device=%x", + &devid, &revid, &devtype, &unique_id, &i2c_bus, &i2c_device); + if (!devid || !devtype || !unique_id) { + gprintk("Invalid dummy_devices format or zero values: devid=0x%x revid=0x%x type=0x%x unique_id=0x%x [i2c_bus=0x%x i2c_device=0x%x]\n", + devid, revid, devtype, unique_id, i2c_bus, i2c_device); + break; + } + + /* Add dummy devices based on kernel module argument */ + if (add_dummy_switch_device(devid, revid, devtype, unique_id, i2c_bus, i2c_device)) { + gprintk("failed adding dummy device: devid=0x%x revid=0x%x type=0x%x unique_id=0x%x [i2c_bus=0x%x i2c_device=0x%x]\n", + devid, revid, devtype, unique_id, i2c_bus, i2c_device); + } else if (debug >= 1) { + gprintk("added dummy device: devid=0x%x revid=0x%x type=0x%x unique_id=0x%x [i2c_bus=0x%x i2c_device=0x%x]\n", + devid, revid, devtype, unique_id, i2c_bus, i2c_device); + } + + token = strtok(NULL, ";"); + } + } + for (i = 0; i < LINUX_BDE_MAX_DEVICES; ++i) { _devices[i].inst_id = BDE_DEV_INST_ID_INVALID; _devices[i].timer_active = 0; @@ -3611,6 +3748,24 @@ _pprint(struct seq_file *m) pprintf(m, "EB Bus Device 0x%x:0x%x\n", ctrl->bde_dev.device, ctrl->bde_dev.rev); + } else if (ctrl->dev_type & (BDE_USER_DEV_TYPE | BDE_I2C_DEV_TYPE)) { + pprintf(m, "Dummy Device using I2C 0x%x:0x%x\n", + ctrl->bde_dev.device, + ctrl->bde_dev.rev); +#ifdef INCLUDE_CPU_I2C + pprintf(m, "\t\ti2c_bus=0x%x i2c_dev=0x%x\n", + ctrl->i2c_bus, + ctrl->i2c_dev); +#endif +#ifdef INCLUDE_SRAM_DMA + pprintf(m, "\t\tdev_sram_dma_start=0x%x dev_sram_dma_size=0x%x\n", + ctrl->dev_sram_dma_start, + ctrl->dev_sram_dma_size); +#endif + } else if (ctrl->dev_type & BDE_USER_DEV_TYPE) { + pprintf(m, "User defined Device 0x%x:0x%x\n", + ctrl->bde_dev.device, + ctrl->bde_dev.rev); } if (debug >= 1) { pprintf(m, "\t\timask:imask2:fmask 0x%x:0x%x:0x%x unique_id=0x%x inst_id ", @@ -3778,12 +3933,21 @@ _pci_conf_read(int d, uint32 addr) return 0xFFFFFFFF; } + if (REMOVED_DEVICE(d)) { + gprintk("_pci_conf_read: Device was removed %d\n", d); + return 0xFFFFFFFF; + } + if (!(_devices[d].dev_type & BDE_PCI_DEV_TYPE)) { gprintk("_pci_conf_read: Not PCI device %d, type %x\n", d, _devices[d].dev_type); return 0xFFFFFFFF; } + if (_devices[d].pci_device == NULL) { + return 0xFFFFFFFF; + } + pci_read_config_dword(_devices[d].pci_device, addr, &rc); return rc; #endif /* BCM_ICS */ @@ -3800,12 +3964,21 @@ _pci_conf_write(int d, uint32 addr, uint32 data) return -1; } + if (REMOVED_DEVICE(d)) { + gprintk("_pci_conf_write: Device was removed %d\n", d); + return -1; + } + if (!(_devices[d].dev_type & BDE_PCI_DEV_TYPE)) { gprintk("_pci_conf_write: Not PCI device %d, type %x\n", d, _devices[d].dev_type); return -1; } + if (_devices[d].pci_device == NULL) { + return -1; + } + pci_write_config_dword(_devices[d].pci_device, addr, data); return 0; #endif /* BCM_ICS */ @@ -3846,7 +4019,7 @@ _read(int d, uint32_t addr) volatile uint16 msb, lsb; uint32 sl_addr, data; - if (!VALID_DEVICE(d)) { + if (!VALID_DEVICE(d) || REMOVED_DEVICE(d)) { return -1; } @@ -3882,7 +4055,7 @@ _write(int d, uint32_t addr, uint32_t data) unsigned long flags; uint32 sl_addr; - if (!VALID_DEVICE(d)) { + if (!VALID_DEVICE(d) || REMOVED_DEVICE(d)) { return -1; } @@ -3922,7 +4095,7 @@ static uint64 _read64(int d, uint32_t addr) { uint64_t data; - if (!VALID_DEVICE(d)) { + if (!VALID_DEVICE(d) || REMOVED_DEVICE(d)) { data = (uint64_t)-1; return *(uint64 *)&data; } @@ -3942,7 +4115,8 @@ _read64(int d, uint32_t addr) static void _write64(int d, uint32_t addr, uint64 data) { - if (!VALID_DEVICE(d) || !(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { + if (!VALID_DEVICE(d) || !(BDE_DEV_MEM_MAPPED(_devices[d].dev_type)) + || REMOVED_DEVICE(d)) { return; } @@ -4399,7 +4573,7 @@ _iproc_ihost_write(int d, uint32_t addr, uint32_t data) static uint32_t _iproc_read(int d, uint32_t addr) { - if (!VALID_DEVICE(d)) { + if (!VALID_DEVICE(d) || REMOVED_DEVICE(d)) { return -1; } @@ -4422,7 +4596,7 @@ _iproc_read(int d, uint32_t addr) static int _iproc_write(int d, uint32_t addr, uint32_t data) { - if (!VALID_DEVICE(d)) { + if (!VALID_DEVICE(d) || REMOVED_DEVICE(d)) { return -1; } @@ -4534,12 +4708,16 @@ lkbde_cpu_pci_register(int d) bde_ctrl_t* ctrl; uint16 cmd = 0; - if (!VALID_DEVICE(d)) { + if (!VALID_DEVICE(d) || REMOVED_DEVICE(d)) { return -1; } ctrl = &_devices[d]; + if (ctrl->pci_device == NULL) { + return -1; + } + /* enable device */ if (pci_enable_device(ctrl->pci_device)) { gprintk("Cannot enable pci device : vendor_id = %x, device_id = %x\n", @@ -4677,6 +4855,9 @@ lkbde_cpu_pci_register(int d) #ifdef BCM_Q4D_SUPPORT case Q4D_DEVICE_ID: #endif +#ifdef BCM_Q4DL_SUPPORT + case Q4DL_DEVICE_ID: +#endif #ifdef BCM_J4L_SUPPORT case J4L_DEVICE_ID: #endif @@ -4734,7 +4915,7 @@ lkbde_mem_write(int d, uint32 addr, uint32 *buf) bde_ctrl_t* ctrl; void *full_addr; - if (!VALID_DEVICE(d)) return -1; + if (!VALID_DEVICE(d) || REMOVED_DEVICE(d)) return -1; ctrl = &_devices[d]; full_addr = (void *)ctrl->bde_dev.base_address + addr; @@ -4749,7 +4930,7 @@ lkbde_mem_read(int d, uint32 addr, uint32 *buf) bde_ctrl_t* ctrl; void *full_addr; - if (!VALID_DEVICE(d)) return -1; + if (!VALID_DEVICE(d) || REMOVED_DEVICE(d)) return -1; ctrl = &_devices[d]; full_addr = (void *)ctrl->bde_dev.base_address + addr; @@ -4964,13 +5145,16 @@ lkbde_get_dev_resource(int d, int rsrc, uint32_t *phys_lo, void * lkbde_get_dma_dev(int d) { - if (!VALID_DEVICE(d)) { + if (!VALID_DEVICE(d) || REMOVED_DEVICE(d)) { return NULL; } #ifdef LINUX_BDE_DMA_DEVICE_SUPPORT return (void *)_devices[d].dma_dev; #else + if (_devices[d].pci_device == NULL) { + return NULL; + } return (void *)_devices[d].pci_device; #endif } @@ -4978,7 +5162,11 @@ lkbde_get_dma_dev(int d) void * lkbde_get_hw_dev(int d) { - if (!VALID_DEVICE(d)) { + if (!VALID_DEVICE(d) || REMOVED_DEVICE(d)) { + return NULL; + } + + if (_devices[d].pci_device == NULL) { return NULL; } @@ -5120,6 +5308,36 @@ lkbde_irq_mask_set(int d, uint32_t addr, uint32_t mask, uint32_t fmask) return 0; } +int +lkbde_irq_clear_set(int d, uint32_t addr) +{ + bde_ctrl_t *ctrl; + int iproc_reg; + unsigned long flags; + + iproc_reg = d & LKBDE_IPROC_REG; + d &= ~(LKBDE_ISR2_DEV | LKBDE_IPROC_REG); + + if (!VALID_DEVICE(d)) { + return -1; + } + + ctrl = _devices + d; + + /* Lock is required to synchronize access from user space */ + spin_lock_irqsave(&ctrl->lock, flags); + + if (iproc_reg) { + _iproc_write(d, addr, ~(ctrl->imask | ctrl->imask2)); + } else { + _write(d, addr, ~(ctrl->imask | ctrl->imask2)); + } + + spin_unlock_irqrestore(&ctrl->lock, flags); + + return 0; +} + /* * When a secondary interrupt handler is installed, this function * is used to avoid activating the user mode interrupt handler @@ -5328,6 +5546,25 @@ lkbde_get_sram_dma_info(unsigned d, uint32 *sram_start, uint32 *sram_size) } #endif /* INCLUDE_SRAM_DMA */ +#ifdef INCLUDE_CPU_I2C +/* Return the i2c bus and i2c device if they were specified in the kernel arguments */ +void +lkbde_get_i2c_info(int d, uint32 *i2c_bus, uint32 *i2c_dev, uint32 *use_default) +{ + + if (d < _ndevices && _devices[d].i2c_bus != I2C_NO_ID && _devices[d].i2c_dev != I2C_NO_ID) { /* This is an I2C info was specified */ + *i2c_bus = _devices[d].i2c_bus; + *i2c_dev = _devices[d].i2c_dev; + *use_default = 0; + } else { + *use_default = 1; + } +} + +LKM_EXPORT_SYM(lkbde_get_i2c_info); + +#endif /* INCLUDE_CPU_I2C */ + /* * Export functions */ @@ -5341,6 +5578,7 @@ LKM_EXPORT_SYM(lkbde_get_dma_dev); LKM_EXPORT_SYM(lkbde_irq_mask_set); LKM_EXPORT_SYM(lkbde_irq_mask_get); LKM_EXPORT_SYM(lkbde_irq_status_get); +LKM_EXPORT_SYM(lkbde_irq_clear_set); LKM_EXPORT_SYM(lkbde_get_dev_phys_hi); LKM_EXPORT_SYM(lkbde_dev_state_set); LKM_EXPORT_SYM(lkbde_dev_state_get); diff --git a/systems/bde/linux/kernel/linux_dma.c b/systems/bde/linux/kernel/linux_dma.c index c52e090..c49d2d8 100644 --- a/systems/bde/linux/kernel/linux_dma.c +++ b/systems/bde/linux/kernel/linux_dma.c @@ -1,7 +1,7 @@ /* * $Id: linux_dma.c,v 1.414 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. @@ -92,10 +92,19 @@ #define ALLOC_TYPE_API 1 /* use one allocation */ #define ALLOC_TYPE_HIMEM 2 /* use high memory */ +/* MAX_ORDER changed meaning in 6.4 and was removed in 6.8 */ +#ifndef MAX_PAGE_ORDER +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,4,0)) +#define MAX_PAGE_ORDER MAX_ORDER +#else +#define MAX_PAGE_ORDER (MAX_ORDER - 1) +#endif +#endif + #if _SIMPLE_MEMORY_ALLOCATION_ #include #ifndef CONFIG_CMA -#define DMA_MAX_ALLOC_SIZE (1 << (MAX_PAGE_ORDER - 1 + PAGE_SHIFT)) /* Maximum size the kernel can allocate in one allocation */ +#define DMA_MAX_ALLOC_SIZE (1 << (MAX_PAGE_ORDER + PAGE_SHIFT)) /* Maximum size the kernel can allocate in one allocation */ #endif /* !CONFIG_CMA */ #endif /* _SIMPLE_MEMORY_ALLOCATION_ */ @@ -140,7 +149,7 @@ #endif #ifndef KMALLOC_MAX_SIZE -#define KMALLOC_MAX_SIZE (1UL << (MAX_PAGE_ORDER - 1 + PAGE_SHIFT)) +#define KMALLOC_MAX_SIZE (1UL << (MAX_PAGE_ORDER + PAGE_SHIFT)) #endif /* Compatibility */ diff --git a/systems/bde/linux/kernel/linux_shbde.c b/systems/bde/linux/kernel/linux_shbde.c index 64fcd38..8211136 100644 --- a/systems/bde/linux/kernel/linux_shbde.c +++ b/systems/bde/linux/kernel/linux_shbde.c @@ -1,7 +1,7 @@ /* * $Id: $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/bde/linux/kernel/linux_shbde.h b/systems/bde/linux/kernel/linux_shbde.h index 1b9cb4e..ba0587e 100644 --- a/systems/bde/linux/kernel/linux_shbde.h +++ b/systems/bde/linux/kernel/linux_shbde.h @@ -1,7 +1,7 @@ /* * $Id: $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/bde/linux/shared/mpool.c b/systems/bde/linux/shared/mpool.c index 4363b2e..235d114 100644 --- a/systems/bde/linux/shared/mpool.c +++ b/systems/bde/linux/shared/mpool.c @@ -1,7 +1,7 @@ /* * $Id: mpool.c,v 1.18 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/bde/linux/user/kernel/Makefile b/systems/bde/linux/user/kernel/Makefile index def9206..a3c187c 100644 --- a/systems/bde/linux/user/kernel/Makefile +++ b/systems/bde/linux/user/kernel/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.13 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/bde/linux/user/kernel/linux-user-bde.c b/systems/bde/linux/user/kernel/linux-user-bde.c index 54af651..144d326 100644 --- a/systems/bde/linux/user/kernel/linux-user-bde.c +++ b/systems/bde/linux/user/kernel/linux-user-bde.c @@ -1,6 +1,6 @@ /* * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. @@ -519,9 +519,17 @@ _cmicx_interrupt_prepare(bde_ctrl_t *ctrl) int d, ind, ret = 0; uint32 stat, iena, mask, fmask; uint32 intrs = 0; + uint32 dev_state = BDE_DEV_STATE_NORMAL; d = (((uint8 *)ctrl - (uint8 *)_devices) / sizeof (bde_ctrl_t)); + (void)lkbde_dev_state_get(d, &dev_state); + if (dev_state == BDE_DEV_STATE_REMOVED) { + /* Return directly if PCIe device was removed */ + return -1; + } + + #ifdef BDE_EDK_SUPPORT /* Check for interrupts meant for EDK and return without wasting time */ if (ctrl->edk_irq_enabled) { @@ -629,11 +637,18 @@ _cmicx_interrupt_pending(void *data) int d, ind; uint32 stat, iena; bde_ctrl_t *ctrl = (bde_ctrl_t *)data; + uint32 dev_state = BDE_DEV_STATE_NORMAL; if (ctrl->dev_type & BDE_PCI_DEV_TYPE) { d = (((uint8 *)ctrl - (uint8 *)_devices) / sizeof (bde_ctrl_t)); + (void)lkbde_dev_state_get(d, &dev_state); + if (dev_state == BDE_DEV_STATE_REMOVED) { + /* Not handling interrupts if PCIe device was removed */ + return 0; + } + for (ind = 0; ind < ctrl->intr_regs.intc_intr_nof_regs; ind++) { IPROC_READ(d, ctrl->intr_regs.intc_intr_status_base + 4 * ind, stat); IPROC_READ(d, ctrl->intr_regs.intc_intr_enable_base + 4 * ind, iena); @@ -1411,10 +1426,13 @@ _devices_init(int d) #ifdef BCM_Q4D_SUPPORT case Q4D_DEVICE_ID: #endif +#ifdef BCM_Q4DL_SUPPORT + case Q4DL_DEVICE_ID: +#endif #ifdef BCM_J4L_SUPPORT case J4L_DEVICE_ID: #endif -#endif +#endif /* BCM_DNX3_SUPPORT */ #ifdef BCM_DNXF3_SUPPORT case RAMON2_DEVICE_ID: case RAMON3_DEVICE_ID: @@ -2205,6 +2223,13 @@ _ioctl(unsigned int cmd, unsigned long arg) else if (_devices[io.dev].isr == _cmicx_gen2_interrupt) { io.rc = lkbde_irq_mask_set(io.dev | LKBDE_IPROC_REG, io.d0, io.d1, 0); + /* Set clear_enable based on irq mask */ + if (io.rc == LUBDE_SUCCESS) + { + bde_ctrl_t *ctrl; + ctrl = &_devices[io.dev]; + io.rc = lkbde_irq_clear_set(io.dev | LKBDE_IPROC_REG, ctrl->intr_regs.intc_intr_clear_enable_base + (io.d0 - ctrl->intr_regs.intc_intr_set_enable_base)); + } } #endif else { @@ -2333,6 +2358,18 @@ _ioctl(unsigned int cmd, unsigned long arg) user_bde->write64(io.dev, io.d0, val); } break; + case LUBDE_GET_I2C_INFO: + if (!VALID_DEVICE(io.dev)) { + return -EINVAL; + } +#ifdef INCLUDE_CPU_I2C + lkbde_get_i2c_info(io.dev, &io.dx.dw[0], &io.dx.dw[1], &io.dx.dw[2]); + break; +#else + gprintk("Error: The build does not support the LUBDE_GET_I2C_INFO ioctl (%08x)\n", cmd); + io.rc = LUBDE_FAIL; + break; +#endif default: gprintk("Error: Invalid ioctl (%08x)\n", cmd); diff --git a/systems/bde/linux/user/kernel/linux-user-bde.h b/systems/bde/linux/user/kernel/linux-user-bde.h index 7d1a047..67275df 100644 --- a/systems/bde/linux/user/kernel/linux-user-bde.h +++ b/systems/bde/linux/user/kernel/linux-user-bde.h @@ -1,7 +1,7 @@ /* * $Id: linux-user-bde.h,v 1.23 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. @@ -106,6 +106,7 @@ typedef struct { #define LUBDE_BAR2_WRITE32 _IO(LUBDE_MAGIC, 40) #define LUBDE_BAR2_READ64 _IO(LUBDE_MAGIC, 41) #define LUBDE_BAR2_WRITE64 _IO(LUBDE_MAGIC, 42) +#define LUBDE_GET_I2C_INFO _IO(LUBDE_MAGIC, 43) #define LUBDE_SEM_OP_CREATE 1 diff --git a/systems/bde/shared/include/shbde.h b/systems/bde/shared/include/shbde.h index 8d40891..4f2950d 100644 --- a/systems/bde/shared/include/shbde.h +++ b/systems/bde/shared/include/shbde.h @@ -1,7 +1,7 @@ /* * $Id: $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/bde/shared/include/shbde_iproc.h b/systems/bde/shared/include/shbde_iproc.h index 6fff1e2..dedc3bf 100644 --- a/systems/bde/shared/include/shbde_iproc.h +++ b/systems/bde/shared/include/shbde_iproc.h @@ -1,7 +1,7 @@ /* * $Id: $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/bde/shared/include/shbde_mdio.h b/systems/bde/shared/include/shbde_mdio.h index 992753f..7d70ba1 100644 --- a/systems/bde/shared/include/shbde_mdio.h +++ b/systems/bde/shared/include/shbde_mdio.h @@ -1,7 +1,7 @@ /* * $Id: $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/bde/shared/include/shbde_pci.h b/systems/bde/shared/include/shbde_pci.h index adf4b48..2ec93e2 100644 --- a/systems/bde/shared/include/shbde_pci.h +++ b/systems/bde/shared/include/shbde_pci.h @@ -1,7 +1,7 @@ /* * $Id: $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/bde/shared/shbde_iproc.c b/systems/bde/shared/shbde_iproc.c index bf5afab..61464f6 100644 --- a/systems/bde/shared/shbde_iproc.c +++ b/systems/bde/shared/shbde_iproc.c @@ -1,7 +1,7 @@ /* * $Id: $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/bde/shared/shbde_mdio.c b/systems/bde/shared/shbde_mdio.c index d8139da..a840cad 100644 --- a/systems/bde/shared/shbde_mdio.c +++ b/systems/bde/shared/shbde_mdio.c @@ -1,7 +1,7 @@ /* * $Id: $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/bde/shared/shbde_pci.c b/systems/bde/shared/shbde_pci.c index 7c68c6b..2689d08 100644 --- a/systems/bde/shared/shbde_pci.c +++ b/systems/bde/shared/shbde_pci.c @@ -1,7 +1,7 @@ /* * $Id: $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/Makefile b/systems/linux/kernel/modules/Makefile index 99afe69..32ac49b 100644 --- a/systems/linux/kernel/modules/Makefile +++ b/systems/linux/kernel/modules/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.10 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/bcm-genl/Makefile b/systems/linux/kernel/modules/bcm-genl/Makefile index ae99cde..76efd38 100644 --- a/systems/linux/kernel/modules/bcm-genl/Makefile +++ b/systems/linux/kernel/modules/bcm-genl/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.3 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/bcm-genl/bcm-genl-dev.c b/systems/linux/kernel/modules/bcm-genl/bcm-genl-dev.c index d492308..d861b67 100644 --- a/systems/linux/kernel/modules/bcm-genl/bcm-genl-dev.c +++ b/systems/linux/kernel/modules/bcm-genl/bcm-genl-dev.c @@ -1,6 +1,6 @@ /* * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/bcm-genl/bcm-genl-dev.h b/systems/linux/kernel/modules/bcm-genl/bcm-genl-dev.h index 5f656a3..eff32c1 100644 --- a/systems/linux/kernel/modules/bcm-genl/bcm-genl-dev.h +++ b/systems/linux/kernel/modules/bcm-genl/bcm-genl-dev.h @@ -1,6 +1,6 @@ /* * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/bcm-genl/bcm-genl-netif.c b/systems/linux/kernel/modules/bcm-genl/bcm-genl-netif.c index 2fb9e86..9ea442c 100644 --- a/systems/linux/kernel/modules/bcm-genl/bcm-genl-netif.c +++ b/systems/linux/kernel/modules/bcm-genl/bcm-genl-netif.c @@ -1,6 +1,6 @@ /* * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/bcm-genl/bcm-genl-netif.h b/systems/linux/kernel/modules/bcm-genl/bcm-genl-netif.h index 84b93d9..b40bc34 100644 --- a/systems/linux/kernel/modules/bcm-genl/bcm-genl-netif.h +++ b/systems/linux/kernel/modules/bcm-genl/bcm-genl-netif.h @@ -1,6 +1,6 @@ /* * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/bcm-genl/bcm-genl-packet.c b/systems/linux/kernel/modules/bcm-genl/bcm-genl-packet.c index 6cbd594..2c3992f 100644 --- a/systems/linux/kernel/modules/bcm-genl/bcm-genl-packet.c +++ b/systems/linux/kernel/modules/bcm-genl/bcm-genl-packet.c @@ -1,6 +1,6 @@ /* * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/bcm-genl/bcm-genl-packet.h b/systems/linux/kernel/modules/bcm-genl/bcm-genl-packet.h index d4298e2..ea9a8a6 100644 --- a/systems/linux/kernel/modules/bcm-genl/bcm-genl-packet.h +++ b/systems/linux/kernel/modules/bcm-genl/bcm-genl-packet.h @@ -1,6 +1,6 @@ /* * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/bcm-genl/bcm-genl-psample.c b/systems/linux/kernel/modules/bcm-genl/bcm-genl-psample.c index c34d0b3..98deddc 100644 --- a/systems/linux/kernel/modules/bcm-genl/bcm-genl-psample.c +++ b/systems/linux/kernel/modules/bcm-genl/bcm-genl-psample.c @@ -1,6 +1,6 @@ /* * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. @@ -803,7 +803,7 @@ static ssize_t psample_proc_debug_write(struct file *file, const char *buf, size_t count, loff_t *loff) { - char debug_str[40]; + char debug_str[40] = {0}; char *ptr; if (count >= sizeof(debug_str)) { diff --git a/systems/linux/kernel/modules/bcm-genl/bcm-genl-psample.h b/systems/linux/kernel/modules/bcm-genl/bcm-genl-psample.h index b2b3943..092e666 100644 --- a/systems/linux/kernel/modules/bcm-genl/bcm-genl-psample.h +++ b/systems/linux/kernel/modules/bcm-genl/bcm-genl-psample.h @@ -1,6 +1,6 @@ /* * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/bcm-genl/bcm-genl.c b/systems/linux/kernel/modules/bcm-genl/bcm-genl.c index ec8db14..883137d 100644 --- a/systems/linux/kernel/modules/bcm-genl/bcm-genl.c +++ b/systems/linux/kernel/modules/bcm-genl/bcm-genl.c @@ -1,6 +1,6 @@ /* * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/bcm-knet/Makefile b/systems/linux/kernel/modules/bcm-knet/Makefile index 20bbb1b..1d97012 100644 --- a/systems/linux/kernel/modules/bcm-knet/Makefile +++ b/systems/linux/kernel/modules/bcm-knet/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.3 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. @@ -76,7 +76,7 @@ $(KMODULE): $(SRCS_COMPOSING) cp ./*.c $(BLDDIR)/ cp ../shared/*.c $(BLDDIR)/ cat ${KBUILD_EXTRA_SYMBOLS} > $(BLDDIR)/Module.symvers - MOD_OBJS=$(OBJECTS_COMPOSING) MOD_NAME=$(THIS_MOD_NAME) KBUILD_EXTRA_SYMBOLS="${KBUILD_EXTRA_SYMBOLS}" $(MAKE) -C $(BLDDIR) $(THIS_MOD_NAME).ko LOC_BLDDIR=$(BLDDIR) LOC_SRCDIR=$(PWD) + MOD_OBJS=$(OBJECTS_COMPOSING) MOD_NAME=$(THIS_MOD_NAME) $(MAKE) -C $(BLDDIR) $(THIS_MOD_NAME).ko LOC_BLDDIR=$(BLDDIR) LOC_SRCDIR=$(PWD) # } else # { diff --git a/systems/linux/kernel/modules/bcm-knet/bcm-knet.c b/systems/linux/kernel/modules/bcm-knet/bcm-knet.c index 50d3b25..21fcdb1 100644 --- a/systems/linux/kernel/modules/bcm-knet/bcm-knet.c +++ b/systems/linux/kernel/modules/bcm-knet/bcm-knet.c @@ -1,5 +1,6 @@ /* - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. @@ -186,7 +187,8 @@ MODULE_PARM_DESC(mirror_local, /* * Force to add one layer of VLAN tag to untagged packets on Dune devices */ -#if defined(SAI_FIXUP) && defined(BCM_DNX_SUPPORT) /* SONIC-16195 CS9129167 - Change the default to NOT add tag */ +#if defined(SAI_FIXUP) && defined(BCM_DNX_SUPPORT) +/* SONIC-16195 CS9129167 - Change the default to NOT add tag */ static int force_tagged = 0; #else static int force_tagged = 1; @@ -1317,8 +1319,9 @@ bkn_sleep(int clicks) * PAXB_0_INTC_SET_INTR_ENABLE_REG5r sets interrupt enable bit for interrupts 191 down to 160 * Packet DMA interrupt enable bit is [168 : 199], here bit [168 : 183] is considered because it is assumed that only cmc0 */ -#define PAXB_0_INTC_SET_INTR_ENABLE_REG5r 0x0292D114 -#define PAXB_0_INTC_INTR_RAW_STATUS_REG5r 0x0292D18C +#define PAXB_0_INTC_SET_INTR_ENABLE_REG5r 0x0292D114 +#define PAXB_0_INTC_CLEAR_INTR_ENABLE_REG5r 0x0292D13C +#define PAXB_0_INTC_INTR_RAW_STATUS_REG5r 0x0292D18C /* CMICR interrupts reserved for kernel handler */ @@ -2205,7 +2208,8 @@ xgsr_irq_fmask_get(bkn_switch_info_t *sinfo, uint32_t *fmask) static inline void xgsr_irq_mask_set(bkn_switch_info_t *sinfo, uint32_t mask) { - uint32_t irq_mask_reg = PAXB_0_INTC_SET_INTR_ENABLE_REG5r; + uint32_t irq_mask_set_reg = PAXB_0_INTC_SET_INTR_ENABLE_REG5r; + uint32_t irq_mask_clear_set_reg = PAXB_0_INTC_CLEAR_INTR_ENABLE_REG5r; uint32_t fmask = CMICR_TXRX_IRQ_MASK; if ((sinfo->base_id & 0x8000) == 0x8000) { @@ -2226,7 +2230,8 @@ xgsr_irq_mask_set(bkn_switch_info_t *sinfo, uint32_t mask) } lkbde_irq_mask_set(sinfo->dev_no | LKBDE_ISR2_DEV | LKBDE_IPROC_REG, - irq_mask_reg, mask, fmask); + irq_mask_set_reg, mask, fmask); + lkbde_irq_clear_set(sinfo->dev_no | LKBDE_ISR2_DEV | LKBDE_IPROC_REG, irq_mask_clear_set_reg); } static inline void diff --git a/systems/linux/kernel/modules/bcm-ngknet/Kbuild b/systems/linux/kernel/modules/bcm-ngknet/Kbuild new file mode 100644 index 0000000..e643620 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/Kbuild @@ -0,0 +1,67 @@ +# -*- Kbuild -*- +# +# Linux KNET module. +# +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. +# +# Permission is granted to use, copy, modify and/or distribute this +# software under either one of the licenses below. +# +# License Option 1: GPL +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License, version 2, as +# published by the Free Software Foundation (the "GPL"). +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License version 2 (GPLv2) for more details. +# +# You should have received a copy of the GNU General Public License +# version 2 (GPLv2) along with this source code. +# +# +# License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license +# +# This software is governed by the Broadcom Open Network Switch APIs license: +# https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ +# +# +# + +obj-m := linux-ngknet.o + +#Predefine the variable, it may become empty with recursive calls +ifndef SDKBUILD +SDKBUILD :=build +endif +ifneq ($(SDK_OUTDIR),) +INCLUDES := -I$(SDK_OUTDIR)/$(SDKBUILD)/bcm-ngknet/generated/include \ + -I$(SDK_OUTDIR)/$(SDKBUILD)/bcm-ngknet/generated +endif +ccflags-y := $(KNET_CPPFLAGS) $(LKM_CFLAGS) $(LKM_CPPFLAGS) \ + -I$(SDK)/include/ \ + -I$(SDK)/src/bcm/common/pktio/bcmdrd/include \ + -I$(SDK)/systems/bde/linux/include \ + -I$(SDK)/systems/linux/kernel/modules/bcm-ngknet/include \ + $(INCLUDES) + +linux-ngknet-y := $(CHIP_OBJS) \ + bcmcnet_cmicx_pdma_hw.o \ + bcmcnet_cmicx_pdma_rxtx.o \ + bcmcnet_cmicr_pdma_hw.o \ + bcmcnet_cmicr_pdma_rxtx.o \ + bcmcnet_cmicr2_pdma_rxtx.o \ + bcmcnet_core.o \ + bcmcnet_dev.o \ + bcmcnet_rxtx.o \ + ngknet_buff.o \ + ngknet_callback.o \ + ngknet_extra.o \ + ngknet_linux.o \ + ngknet_main.o \ + ngknet_procfs.o \ + ngknet_ptp.o \ + ngknet_adapter.o \ + ngknet_parser.o diff --git a/systems/linux/kernel/modules/bcm-ngknet/Makefile b/systems/linux/kernel/modules/bcm-ngknet/Makefile new file mode 100644 index 0000000..04e4d3d --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/Makefile @@ -0,0 +1,184 @@ +# +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. +# +# Permission is granted to use, copy, modify and/or distribute this +# software under either one of the licenses below. +# +# License Option 1: GPL +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License, version 2, as +# published by the Free Software Foundation (the "GPL"). +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License version 2 (GPLv2) for more details. +# +# You should have received a copy of the GNU General Public License +# version 2 (GPLv2) along with this source code. +# +# +# License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license +# +# This software is governed by the Broadcom Open Network Switch APIs license: +# https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ +# +# +# +# Linux KNET module. +# + +LOCALDIR = systems/linux/kernel/modules/bcm-ngknet +PKTIO_IMPL = 1 +include ${SDK}/make/Make.config + +PKTIODIR = $(SDK)/src/bcm/common/pktio +CNETDIR = $(PKTIODIR)/bcmcnet +KNETDIR = $(SDK)/systems/linux/kernel/modules/bcm-ngknet +GENDIR = $(KNETDIR)/generated +SRCIDIR = $(CNETDIR)/include/bcmcnet +ifneq ($(SDK_OUTDIR),) +GENDIR = $(SDK_OUTDIR)/$(SDKBUILD)/bcm-ngknet/generated +endif +DSTIDIR = $(GENDIR)/include/bcmcnet + +# Change comma-separated list to space-separated list +comma = , +empty = +space = $(empty) $(empty) +spc_sep = $(subst $(comma),$(space),$1) + +# Convert chip name to uppercase +chip_uc = $(subst a,A,$(subst b,B,$(subst c,C,$(subst m,M,$1)))) + +# Convert chip name to lowercase +chip_lc = $(subst A,a,$(subst B,b,$(subst C,c,$(subst M,m,$1)))) + +# +# If SDK_CHIPS is defined, then exclude any chip directory which is +# not part of this list. +# +KNET_CHIPS := $(subst $(PKTIODIR)/chip/,,$(wildcard $(PKTIODIR)/chip/bcm*)) +ifdef SDK_CHIPS +# Create space-separated lowercase version of chip list +SDK_CHIPS_SPC := $(call spc_sep,$(SDK_CHIPS)) +SDK_CHIPS_LC := $(call chip_lc,$(SDK_CHIPS_SPC)) +# Configure build flags according to chip list +KNET_CHIPS := $(filter $(SDK_CHIPS_LC),$(KNET_CHIPS)) +KNET_CPPFLAGS := CHIP_DEFAULT=0 $(addsuffix =1,$(call chip_uc,$(KNET_CHIPS))) +KNET_CPPFLAGS := $(addprefix -DBCMDRD_CONFIG_INCLUDE_,$(KNET_CPPFLAGS)) +export KNET_CPPFLAGS +endif +# +# Redefine KAPI interface API name to avoid symbol conflict. +# +KAPI_FUNCS = ngbde_kapi_dma_dev_get \ + ngbde_kapi_dma_bus_to_virt \ + ngbde_kapi_dma_virt_to_bus \ + ngbde_kapi_pio_write32 \ + ngbde_kapi_pio_read32 \ + ngbde_kapi_pio_membase \ + ngbde_kapi_iio_write32 \ + ngbde_kapi_iio_read32 \ + ngbde_kapi_intr_connect \ + ngbde_kapi_intr_disconnect \ + ngbde_kapi_intr_mask_write \ + ngbde_kapi_knet_connect \ + ngbde_kapi_knet_disconnect \ + ngknet_dev_init_cb_register \ + ngknet_dev_init_cb_unregister \ + ngknet_rx_cb_register \ + ngknet_rx_cb_unregister \ + ngknet_tx_cb_register \ + ngknet_tx_cb_unregister \ + ngknet_netif_create_cb_register \ + ngknet_netif_create_cb_unregister \ + ngknet_netif_destroy_cb_register \ + ngknet_netif_destroy_cb_unregister \ + ngknet_filter_cb_register \ + ngknet_filter_cb_register_by_name \ + ngknet_filter_cb_unregister \ + ngknet_ptp_rx_config_set_cb_register \ + ngknet_ptp_rx_config_set_cb_unregister \ + ngknet_ptp_tx_config_set_cb_register \ + ngknet_ptp_tx_config_set_cb_unregister \ + ngknet_ptp_rx_hwts_get_cb_register \ + ngknet_ptp_rx_hwts_get_cb_unregister \ + ngknet_ptp_tx_hwts_get_cb_register \ + ngknet_ptp_tx_hwts_get_cb_unregister \ + ngknet_ptp_tx_meta_set_cb_register \ + ngknet_ptp_tx_meta_set_cb_unregister \ + ngknet_ptp_phc_index_get_cb_register \ + ngknet_ptp_phc_index_get_cb_unregister \ + ngknet_ptp_dev_ctrl_cb_register \ + ngknet_ptp_dev_ctrl_cb_unregister \ + ngknet_ptp_rx_pre_process_cb_register \ + ngknet_ptp_rx_pre_process_cb_unregister + +KAPI_FUNCS_PREFIX = pktio +CFGFLAGS += $(foreach f,${KAPI_FUNCS},-D$f=${KAPI_FUNCS_PREFIX}_$f) + +LKM_CFLAGS := $(CFGFLAGS) $(LKM_BUILD_INFO) -DPKTIO_KIMPL=1 +LKM_CPPFLAGS := $(CFGFLAGS) $(LKM_BUILD_INFO) -DPKTIO_KIMPL=1 +export LKM_CFLAGS +export LKM_CPPFLAGS + +.PHONY: mklinks rmlinks + +knet: mklinks + $(Q)echo Building kernel module $(BLDDIR) + $(MAKE) -C $(GENDIR) all + +# +# Suppress symlink error messages. +# +# Note that we do not use "ln -f" as this may cause failures if +# multiple builds are done in parallel on the same source tree. +# +R = 2>/dev/null + +mklinks: + mkdir -p $(DSTIDIR) + -ln -s $(PKTIODIR)/pktio_dep.h $(GENDIR)/pktio_dep.h $(R) + -ln -s $(KNETDIR)/ngknet_dep.h $(DSTIDIR)/bcmcnet_dep.h $(R) + -ln -s $(KNETDIR)/ngknet_buff.h $(DSTIDIR)/bcmcnet_buff.h $(R) + -ln -s $(SRCIDIR)/bcmcnet_types.h $(DSTIDIR) $(R) + -ln -s $(SRCIDIR)/bcmcnet_internal.h $(DSTIDIR) $(R) + -ln -s $(SRCIDIR)/bcmcnet_core.h $(DSTIDIR) $(R) + -ln -s $(SRCIDIR)/bcmcnet_dev.h $(DSTIDIR) $(R) + -ln -s $(SRCIDIR)/bcmcnet_rxtx.h $(DSTIDIR) $(R) + -ln -s $(SRCIDIR)/bcmcnet_cmicx.h $(DSTIDIR) $(R) + -ln -s $(SRCIDIR)/bcmcnet_cmicr_acc.h $(DSTIDIR) $(R) + -ln -s $(SRCIDIR)/bcmcnet_cmicr.h $(DSTIDIR) $(R) + -ln -s $(SRCIDIR)/bcmcnet_cmicr2.h $(DSTIDIR) $(R) + -ln -s $(PKTIODIR)/chip/*/*attach.c $(GENDIR) $(R) + -ln -s $(CNETDIR)/hmi/cmicx/*.c $(GENDIR) $(R) + -ln -s $(CNETDIR)/hmi/cmicr/*.c $(GENDIR) $(R) + -ln -s $(CNETDIR)/main/bcmcnet_core.c $(GENDIR) $(R) + -ln -s $(CNETDIR)/main/bcmcnet_dev.c $(GENDIR) $(R) + -ln -s $(CNETDIR)/main/bcmcnet_rxtx.c $(GENDIR) $(R) + -ln -s $(KNETDIR)/*.[ch] $(GENDIR) $(R) + -ln -s $(KNETDIR)/ngknet_adapter.c $(GENDIR) $(R) + -ln -s $(KNETDIR)/Makefile $(GENDIR) $(R) + -ln -s $(KNETDIR)/Kbuild $(GENDIR) $(R) + +rmlinks: + -rm -rf $(GENDIR) + +CHIP_SRCS := $(addsuffix _pdma_attach.c,$(KNET_CHIPS)) +CHIP_OBJS ?= $(patsubst %.c, %.o, $(CHIP_SRCS)) +export CHIP_OBJS + +include Kbuild + +ifeq ($(KERNELRELEASE),) + +MOD_NAME = linux-ngknet + +include $(SDK)/make/Make.lkm +endif + +.PHONY: distclean + +distclean:: rmlinks diff --git a/systems/linux/kernel/modules/bcm-ngknet/include/lkm/lkm.h b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/lkm.h new file mode 100644 index 0000000..95c1cf1 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/lkm.h @@ -0,0 +1,214 @@ +/*! \file lkm.h + * + * Linux compatibility macros. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef LKM_H +#define LKM_H + +#include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) +#error Kernel too old +#endif +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) +#include +#endif +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_DEVFS_FS +#include +#endif + +/* Compatibility Macros */ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,5,0) +#define PROC_OWNER(_m) +#else +#define PROC_OWNER(_m) .owner = _m, +#define proc_ops file_operations +#define proc_open open +#define proc_read read +#define proc_write write +#define proc_lseek llseek +#define proc_release release +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) +#define PROC_CREATE(_entry, _name, _acc, _path, _fops) \ + do { \ + _entry = proc_create(_name, _acc, _path, _fops); \ + } while (0) + +#define PROC_CREATE_DATA(_entry, _name, _acc, _path, _fops, _data) \ + do { \ + _entry = proc_create_data(_name, _acc, _path, _fops, _data); \ + } while (0) + +#define PROC_PDE_DATA(_node) PDE_DATA(_node) +#else +#define PROC_CREATE(_entry, _name, _acc, _path, _fops) \ + do { \ + _entry = create_proc_entry(_name, _acc, _path); \ + if (_entry) { \ + _entry->proc_fops = _fops; \ + } \ + } while (0) + +#define PROC_CREATE_DATA(_entry, _name, _acc, _path, _fops, _data) \ + do { \ + _entry = create_proc_entry(_name, _acc, _path); \ + if (_entry) { \ + _entry->proc_fops = _fops; \ + _entry->data=_data; \ + } \ + } while (0) + +#define PROC_PDE_DATA(_node) PROC_I(_node)->pde->data +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0) +#define timer_arg(var, context, timer_fieldname) \ + (typeof(var))(context) +#define timer_context_t unsigned long +#else +#define timer_context_t struct timer_list * +#define timer_arg(var, context, timer_fieldname) \ + from_timer(var, context, timer_fieldname) +#endif + +#ifndef setup_timer +#define setup_timer(timer, fn, data) \ + timer_setup(timer, fn, 0) +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) +static inline void page_ref_inc(struct page *page) +{ + atomic_inc(&page->_count); +} + +static inline void page_ref_dec(struct page *page) +{ + atomic_dec(&page->_count); +} +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0) +#define DMA_FORCE_CONTIGUOUS NULL +#else +#define DMA_FORCE_CONTIGUOUS DMA_ATTR_FORCE_CONTIGUOUS +#endif + +#ifndef PCI_IRQ_MSI +/* Emulate new IRQ API if not available */ +#define PCI_IRQ_LEGACY (1 << 0) +#define PCI_IRQ_MSI (1 << 1) +#define PCI_IRQ_MSIX (1 << 2) +static inline int +pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags) +{ + /* We do not attempt to support MSI-X via old API */ + if (flags & PCI_IRQ_MSI) { + if (pci_enable_msi(dev) == 0) { + return 1; + } + } + if (flags & PCI_IRQ_LEGACY) { + return 1; + } + return 0; +} +static inline void +pci_free_irq_vectors(struct pci_dev *dev) +{ + pci_disable_msi(dev); +} +static inline int +pci_irq_vector(struct pci_dev *dev, unsigned int nr) +{ + return dev->irq; +} +#endif + +/* Renamed in 6.8 */ +#ifndef PCI_IRQ_INTX +#define PCI_IRQ_INTX PCI_IRQ_LEGACY +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,19,0) +#define strscpy strlcpy +#endif + +#ifndef MAX_PAGE_ORDER +#define MAX_PAGE_ORDER MAX_ORDER +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(6,11,0) +#define kernel_ethtool_ts_info ethtool_ts_info +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(6,11,0) +#define PLATFORM_DRIVER_REMOVE_RETURN_TYPE int +#define PLATFORM_DRIVER_REMOVE_RETURN_VALUE(_v) return (_v) +#endif + +#ifndef PLATFORM_DRIVER_REMOVE_RETURN_TYPE +#define PLATFORM_DRIVER_REMOVE_RETURN_TYPE void +#endif + +#ifndef PLATFORM_DRIVER_REMOVE_RETURN_VALUE +#define PLATFORM_DRIVER_REMOVE_RETURN_VALUE(_v) +#endif + +#endif /* LKM_H */ diff --git a/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngbde_ioctl.h b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngbde_ioctl.h new file mode 100644 index 0000000..9f17261 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngbde_ioctl.h @@ -0,0 +1,448 @@ +/*! \file ngbde_ioctl.h + * + * NGBDE device I/O control definitions. + * + * This file is intended for use in both kernel mode and user mode. + * + * IMPORTANT! + * All shared structures must be properly 64-bit aligned. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGBDE_IOCTL_H +#define NGBDE_IOCTL_H + +#include +#include + +/*! Must be updated if backward compatibility is broken. */ +#define NGBDE_IOC_VERSION 2 + +/*! LUBDE IOCTL command magic. */ +#define NGBDE_IOC_MAGIC 'L' + +/*! + * \name IOCTL commands for the NGBDE kernel module. + * \anchor NGBDE_IOC_xxx + * + * Note that we use __u64 for the IOCTL parameter size because + * sizeof(void *) is different between 32-bit and 64-bit code, and we + * need a 32-bit user mode application to generate the same IOCTL + * command codes as a 64-bit kernel when using the _IOW macro. + */ + +/*! \{ */ + +/*! Get kernel module information. */ +#define NGBDE_IOC_MOD_INFO _IOW(NGBDE_IOC_MAGIC, 0, __u64) + +/*! Get information about registered devices. */ +#define NGBDE_IOC_PROBE_INFO _IOW(NGBDE_IOC_MAGIC, 1, __u64) + +/*! Get detailed switch device information. */ +#define NGBDE_IOC_DEV_INFO _IOW(NGBDE_IOC_MAGIC, 2, __u64) + +/*! Get a physical memory address associated with a switch device. */ +#define NGBDE_IOC_PHYS_ADDR _IOW(NGBDE_IOC_MAGIC, 3, __u64) + +/*! Interrupt control command (see \ref NGBDE_ICTL_xxx). */ +#define NGBDE_IOC_INTR_CTRL _IOW(NGBDE_IOC_MAGIC, 4, __u64) + +/*! Add interrupt status/mask register for kernel to control. */ +#define NGBDE_IOC_IRQ_REG_ADD _IOW(NGBDE_IOC_MAGIC, 5, __u64) + +/*! Write to a shared interrupt mask register. */ +#define NGBDE_IOC_IRQ_MASK_WR _IOW(NGBDE_IOC_MAGIC, 6, __u64) + +/*! Map device registers in kernel space. */ +#define NGBDE_IOC_PIO_WIN_MAP _IOW(NGBDE_IOC_MAGIC, 7, __u64) + +/*! Map interrupt controller registers in kernel space. */ +#define NGBDE_IOC_IIO_WIN_MAP _IOW(NGBDE_IOC_MAGIC, 8, __u64) + +/*! Map PCI bridge registers in kernel space. */ +#define NGBDE_IOC_PAXB_WIN_MAP _IOW(NGBDE_IOC_MAGIC, 9, __u64) + +/*! Add interrupt ACK register for kernel to control. */ +#define NGBDE_IOC_IACK_REG_ADD _IOW(NGBDE_IOC_MAGIC, 10, __u64) + +/*! Initialize kernel interrupt driver. */ +#define NGBDE_IOC_IRQ_INIT _IOW(NGBDE_IOC_MAGIC, 11, __u64) + +/*! \} */ + +/*! IOCTL command return code for success. */ +#define NGBDE_IOC_SUCCESS 0 + +/*! IOCTL command return code for failure. */ +#define NGBDE_IOC_FAIL ((__u32)-1) + +/*! + * \name Compatibility features. + * + * This allows user mode applications to work with both current and + * older kernel modules. + * + * \anchor NGBDE_COMPAT_xxx + */ + +/*! \{ */ + +/*! Support for IRQ_INIT IOCTL command. */ +#define NGBDE_COMPAT_IRQ_INIT (1 << 0) + +/*! \} */ + +/*! Kernel module information. */ +struct ngbde_ioc_mod_info_s { + + /*! IOCTL version used by kernel module. */ + __u16 version; + + /*! Compatibility options (\ref NGBDE_COMPAT_xxx). */ + __u16 compat; +}; + +/*! Probing results. */ +struct ngbde_ioc_probe_info_s { + + /*! Number of switch devices. */ + __u16 num_swdev; +}; + +/*! + * \name Bus types. + * \anchor NGBDE_DEV_BT_xxx + */ + +/*! \{ */ + +/*! PCI bus. */ +#define NGBDE_DEV_BT_PCI 0 + +/*! ARM AXI bus. */ +#define NGBDE_DEV_BT_AXI 1 + +/*! \} */ + +/*! Device information. */ +struct ngbde_ioc_dev_info_s { + + /*! Device type (currently unused). */ + __u8 device_type; + + /*! Bus type (\ref NGBDE_DEV_BT_xxx). */ + __u8 bus_type; + + /*! Device flags (currently unused). */ + __u16 flags; + + /*! Vendor ID (typically the PCI vendor ID). */ + __u16 vendor_id; + + /*! Device ID (typically the PCI vendor ID). */ + __u16 device_id; + + /*! Device revision (typically the PCI device revision). */ + __u16 revision; + + /*! Device model (device-identification beyond PCI generic ID). */ + __u16 model; +}; + +/*! + * \name I/O resource types. + * \anchor NGBDE_IO_RSRC_xxx + */ + +/*! \{ */ + +/*! Memory-mapped I/O. */ +#define NGBDE_IO_RSRC_DEV_IO 0 + +/*! DMA memory pool. */ +#define NGBDE_IO_RSRC_DMA_MEM 1 + +/*! DMA memory pool as mapped by IOMMU. */ +#define NGBDE_IO_RSRC_DMA_BUS 2 + +/*! \} */ + +/*! + * \brief Resource ID (IOCTL input). + * + * This structure is used to query a physical address resource in the + * kernel module. The caller must provide a resource type (device I/O, + * DMA memory, etc.) and a resource instance number (e.g. a PCI BAR + * address will have multiple instances). + * + * Also see \ref ngbde_ioc_phys_addr_s. + */ +struct ngbde_ioc_rsrc_id_s { + + /*! Resource type (\ref NGBDE_IO_RSRC_xxx). */ + __u32 type; + + /*! Resource instance number. */ + __u32 inst; +}; + +/*! + * \brief Physical device address. + * + * This structure is returned in response to the \ref + * NGBDE_IOC_PHYS_ADDR command. The caller must identify the requested + * physical address using the \ref ngbde_ioc_rsrc_id_s structure. + */ +struct ngbde_ioc_phys_addr_s { + + /*! Physical address. */ + __u64 addr; + + /*! Resource size (in bytes). */ + __u32 size; +}; + +/*! + * Initialize kernel interrupt driver. + * + * The user mode driver will provide the number of desired interrupt + * lines, and the kernel mode driver will respond with the actual + * number of interrupt lines available (which may be a smaller + * number). + */ +struct ngbde_ioc_irq_init_s { + + /*! Maximum number of interrupt lines per device. */ + __u32 irq_max; +}; + +/*! + * \name Interrupt control commands. + * \anchor NGBDE_ICTL_xxx + */ + +/*! \{ */ + +/*! Connect interrupt handler. */ +#define NGBDE_ICTL_INTR_CONN 0 + +/*! Disconnect interrupt handler. */ +#define NGBDE_ICTL_INTR_DISC 1 + +/*! Wait for interrupt. */ +#define NGBDE_ICTL_INTR_WAIT 2 + +/*! Force waiting interrupt thread to return. */ +#define NGBDE_ICTL_INTR_STOP 3 + +/*! Clear list of interrupt status/mask registers. */ +#define NGBDE_ICTL_REGS_CLR 4 + +/*! \} */ + +/*! Interrupt control operation. */ +struct ngbde_ioc_intr_ctrl_s { + + /*! Interrupt instance for this device. */ + __u32 irq_num; + + /*! Interrupt control command (see \ref NGBDE_ICTL_xxx). */ + __u32 cmd; +}; + +/*! + * \name Interrupt register access flags. + * \anchor NGBDE_IRQ_REG_F_xxx + */ + +/*! \{ */ + +/*! IRQ register is of type "write 1 to clear". */ +#define NGBDE_IRQ_REG_F_W1TC (1 << 0) + +/*! IRQ status register is a bitwise AND of mask and raw status. */ +#define NGBDE_IRQ_REG_F_MASKED (1 << 1) + +/*! + * Indicates that the interrupts in the kmask field should be handled + * by the kernel (typically the KNET kernel network driver). The + * remaining interrupts in the interrupt register (if any) will be + * handled by the user mode interrupt driver, except if \ref + * NGBDE_IRQ_REG_F_UMASK is set, in which case the remaining + * interrupts in the kmask will be ignored. + */ +#define NGBDE_IRQ_REG_F_KMASK (1 << 2) + +/*! + * Indicates that the interrupts in the umask field should be handled + * by the user mode interrupt handler. + */ +#define NGBDE_IRQ_REG_F_UMASK (1 << 3) + +/*! \} */ + +/*! Add interrupt register information. */ +struct ngbde_ioc_irq_reg_add_s { + + /*! Interrupt line associated with these registers. */ + __u32 irq_num; + + /*! Interrupt status register address offset. */ + __u32 status_reg; + + /*! Interrupt mask register address offset. */ + __u32 mask_reg; + + /*! + * Indicates which kernel mode interrupts in the interrupt + * registers that are associated with this interrupt line (\c + * irq_num). Note that the \ref NGBDE_IRQ_REG_F_xxx flags may + * affect how this value is interpreted. + */ + __u32 kmask; + + /*! Flags for special handling (\ref NGBDE_IRQ_REG_F_xxx). */ + __u32 flags; + + /*! + * Indicates which user mode interrupts in the interrupt registers + * that are associated with this interrupt line (\c irq_num). Note + * that the \ref NGBDE_IRQ_REG_F_xxx flags may affect how this + * value is interpreted. + */ + __u32 umask; +}; + +/*! + * \name Interrupt ACK register access flags. + * \anchor NGBDE_IACK_REG_F_xxx + */ + +/*! \{ */ + +/*! ACK registers resides in PCI bridge I/O window. */ +#define NGBDE_IACK_REG_F_PAXB (1 << 0) + +/*! \} */ + +/*! Add interrupt ACK register information. */ +struct ngbde_ioc_iack_reg_add_s { + + /*! Interrupt instance for this device. */ + __u32 irq_num; + + /*! Interrupt ACK register address offset. */ + __u32 ack_reg; + + /*! Interrupt ACK register value to write. */ + __u32 ack_val; + + /*! Interrupt ACK register access flags (\ref NGBDE_IACK_REG_F_xxx). */ + __u32 flags; +}; + +/*! Memory-mapped I/O window */ +struct ngbde_ioc_pio_win_s { + + /*! Physical address */ + __u64 addr; + + /*! Resource size */ + __u32 size; +}; + +/*! Interrupt mask register write */ +struct ngbde_ioc_irq_mask_wr_s { + + /*! Interrupt instance for this device. */ + __u32 irq_num; + + /*! Register offset. */ + __u32 offs; + + /*! Value to write. */ + __u32 val; +}; + +/*! IOCTL operation data. */ +union ngbde_ioc_op_s { + + /*! Get kernel module information. */ + struct ngbde_ioc_mod_info_s mod_info; + + /*! Get information about registered devices. */ + struct ngbde_ioc_probe_info_s probe_info; + + /*! Get detailed switch device information. */ + struct ngbde_ioc_dev_info_s dev_info; + + /*! Resource ID (input). */ + struct ngbde_ioc_rsrc_id_s rsrc_id; + + /*! Get a physical memory address associated with a switch device. */ + struct ngbde_ioc_phys_addr_s phys_addr; + + /*! Get information about interrupt capabilities. */ + struct ngbde_ioc_irq_init_s irq_init; + + /*! Interrupt control command. */ + struct ngbde_ioc_intr_ctrl_s intr_ctrl; + + /*! Add interrupt status/mask register for kernel to control. */ + struct ngbde_ioc_irq_reg_add_s irq_reg_add; + + /*! Add interrupt ACK register for kernel to control. */ + struct ngbde_ioc_iack_reg_add_s iack_reg_add; + + /*! Write to a shared interrupt mask register. */ + struct ngbde_ioc_irq_mask_wr_s irq_mask_wr; + + /*! Map device registers in kernel space. */ + struct ngbde_ioc_pio_win_s pio_win; +}; + +/*! IOCTL command message. */ +typedef struct ngbde_ioc_cmd_s { + + /*! Device handle. */ + __u32 devid; + + /*! Return code (0 means success). */ + __u32 rc; + + /*! IOCTL operation. */ + union ngbde_ioc_op_s op; + +} ngbde_ioc_cmd_t; + +#endif /* NGBDE_IOCTL_H */ diff --git a/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngbde_kapi.h b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngbde_kapi.h new file mode 100644 index 0000000..ee94f1e --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngbde_kapi.h @@ -0,0 +1,326 @@ +/*! \file ngbde_kapi.h + * + * NGBDE kernel API. + * + * This file is intended for use by other kernel modules relying on the BDE. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGBDE_KAPI_H +#define NGBDE_KAPI_H + +#include + +/*! Maximum number of switch devices supported. */ +#ifndef NGBDE_NUM_SWDEV_MAX +#define NGBDE_NUM_SWDEV_MAX 16 +#endif + +/*! Device has been removed. */ +#define NGBDE_EVENT_DEV_REMOVE 1 + +/*! + * \brief KNET handler. + * + * The KNET handler with the Linux kernel. + * + * \param [in] kdev Switch device number. + * \param [in] event PCI event, see NGBDE_EVENT_xxx for event definitions. + * \param [in] data KNET handler context. + * + */ +typedef int (*knet_func_f)(int kdev, int event, void *data); + +/*! + * \brief Get Linux PCI device handle for a switch device. + * + * \param [in] kdev Device number. + * + * \return Linux PCI device handle or NULL if unavailable. + */ +extern struct pci_dev * +ngbde_kapi_pci_dev_get(int kdev); + +/*! + * \brief Get Linux kernel device handle for a switch device. + * + * \param [in] kdev Device number. + * + * \return Linux kernel device handle or NULL if unavailable. + */ +extern struct device * +ngbde_kapi_dma_dev_get(int kdev); + +/*! + * \brief Convert DMA bus address to virtual address. + * + * This API will convert a physical DMA bus address to a kernel + * virtual address for a memory location that belongs to one of the + * DMA memory pools allocated by the BDE module. + * + * \param [in] kdev Device number. + * \param [in] baddr Physical DMA bus address for this device. + * + * \return Virtual kernel address or NULL on error. + */ +extern void * +ngbde_kapi_dma_bus_to_virt(int kdev, dma_addr_t baddr); + +/*! + * \brief Convert virtual address to DMA bus address. + * + * This API will convert a kernel virtual address to a physical DMA + * bus address for a memory location that belongs to one of the DMA + * memory pools allocated by the BDE module. + * + * \param [in] kdev Device number. + * \param [in] vaddr Virtual kernel address. + * + * \return Physical DMA bus address for this device or 0 on error. + */ +extern dma_addr_t +ngbde_kapi_dma_virt_to_bus(int kdev, void *vaddr); + +/*! + * \brief Allocate physically continguous memory. + * + * This function can be used to allocate a large physically contiguous + * block of memory suitable for DMA operations. + * + * Use the kernel API dma_map_single to map the memory to a physical + * device. A suitable DMA device for this operation can be obtained + * via \ref ngbde_kapi_dma_dev_get. + * + * Memory should be freed via \ref ngbde_kapi_dma_free. + * + * \param [in] size Number of bytes to allocate. + * + * \return Pointer to allocated memory or NULL on error. + */ +extern void * +ngbde_kapi_dma_alloc(size_t size); + +/*! + * \brief Free physically continguous memory. + * + * Free memory previously allocated via \ref ngbde_kapi_dma_alloc. + * + * If the memory has been used for DMA operation, then it must first + * be unmapped via the kernel API dma_unmap_single. + * + * \param [in] ptr Pointer to memory to be freed. + * + * \retval 0 No errors. + * \retval -1 Invalid memory pointer. + */ +extern int +ngbde_kapi_dma_free(void *ptr); + +/*! + * \brief Write a memory-mapped register in kernel driver. + * + * \param [in] kdev Device number. + * \param [in] offs Register address offset. + * \param [in] val Value to write to register. + * + * \return Nothing. + */ +extern void +ngbde_kapi_pio_write32(int kdev, uint32_t offs, uint32_t val); + +/*! + * \brief Read a memory-mapped register in kernel driver. + * + * \param [in] kdev Device number. + * \param [in] offs Register address offset. + * + * \return Value read from register. + */ +extern uint32_t +ngbde_kapi_pio_read32(int kdev, uint32_t offs); + +/*! + * \brief Get base address of memory-mapped I/O memory. + * + * The logical base address returned can be used with ioread32, etc. + * + * \param [in] kdev Device number. + * + * \return Logical base address or NULL if unavailable. + */ +extern void * +ngbde_kapi_pio_membase(int kdev); + +/*! + * \brief Write a memory-mapped interrupt controller register. + * + * \param [in] kdev Device number. + * \param [in] offs Register address offset. + * \param [in] val Value to write to register. + * + * \return Nothing. + */ +extern void +ngbde_kapi_iio_write32(int kdev, uint32_t offs, uint32_t val); + +/*! + * \brief Read a memory-mapped interrupt controller register. + * + * \param [in] kdev Device number. + * \param [in] offs Register address offset. + * + * \return Value read from register. + */ +extern uint32_t +ngbde_kapi_iio_read32(int kdev, uint32_t offs); + +/*! + * \brief Get base address of memory-mapped interrupt controller memory. + * + * The logical base address returned can be used with ioread32, etc. + * + * \param [in] kdev Device number. + * + * \return Logical base address or NULL if unavailable. + */ +extern void * +ngbde_kapi_iio_membase(int kdev); + +/*! + * \brief Write a memory-mapped PCI bridge register. + * + * \param [in] kdev Device number. + * \param [in] offs Register address offset. + * \param [in] val Value to write to register. + * + * \return Nothing. + */ +extern void +ngbde_kapi_paxb_write32(int kdev, uint32_t offs, uint32_t val); + +/*! + * \brief Read a memory-mapped PCI bridge register. + * + * \param [in] kdev Device number. + * \param [in] offs Register address offset. + * + * \return Value read from register. + */ +extern uint32_t +ngbde_kapi_paxb_read32(int kdev, uint32_t offs); + +/*! + * \brief Get base address of memory-mapped PCI bridge memory. + * + * The logical base address returned can be used with ioread32, etc. + * + * \param [in] kdev Device number. + * + * \return Logical base address or NULL if unavailable. + */ +extern void * +ngbde_kapi_paxb_membase(int kdev); + +/*! + * \brief Install kernel mode interrupt handler. + * + * \param [in] kdev Device number. + * \param [in] irq_num Interrupt number (MSI vector). + * \param [in] isr_func Interrupt handler function. + * \param [in] isr_data Interrupt handler context. + * + * \retval 0 No errors + */ +extern int +ngbde_kapi_intr_connect(int kdev, unsigned int irq_num, + int (*isr_func)(void *), void *isr_data); + +/*! + * \brief Uninstall kernel mode interrupt handler. + * + * \param [in] kdev Device number. + * \param [in] irq_num Interrupt number (MSI vector). + * + * \retval 0 No errors + */ +extern int +ngbde_kapi_intr_disconnect(int kdev, unsigned int irq_num); + +/*! + * \brief Write shared interrupt mask register. + * + * This function is used by an interrupt handler when a shared + * interrupt mask register needs to be updated. + * + * Note that the mask register to access is referenced by the + * corrsponding status register. This is because the mask register may + * be different depending on the host CPU interface being used + * (e.g. PCI vs. AXI). On the other hand, the status register is the + * same irrespective of the host CPU interface. + * + * \param [in] kdev Device number. + * \param [in] irq_num Interrupt number (MSI vector). + * \param [in] status_reg Corresponding interrupt status register offset. + * \param [in] mask_val New value to write to mask register. + * + * \retval 0 No errors + * \retval -1 Something went wrong. + */ +extern int +ngbde_kapi_intr_mask_write(int kdev, unsigned int irq_num, + uint32_t status_reg, uint32_t mask_val); + +/*! + * \brief Install KNET callback handler. + * + * Register a callback function to handle BDE events on KNET. + * + * \param [in] kdev Device number. + * \param [in] knet_func KNET callback function. + * \param [in] knet_data Context of KNET callback function. + * + * \retval 0 No errors + */ +extern int +ngbde_kapi_knet_connect(int kdev, knet_func_f knet_func, void *knet_data); + +/*! + * \brief Uninstall KNET callback handler. + * + * \param [in] kdev Device number. + * + * \retval 0 No errors + */ +extern int +ngbde_kapi_knet_disconnect(int kdev); + +#endif /* NGBDE_KAPI_H */ diff --git a/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngedk_ioctl.h b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngedk_ioctl.h new file mode 100644 index 0000000..c9fe523 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngedk_ioctl.h @@ -0,0 +1,214 @@ +/*! \file ngedk_ioctl.h + * + * NGEDK device I/O control definitions. + * + * This file is intended for use in both kernel mode and user mode. + * + * IMPORTANT! + * All shared structures must be properly 64-bit aligned. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGEDK_IOCTL_H +#define NGEDK_IOCTL_H + +#include +#include + +/*! Module information */ +#define NGEDK_MODULE_NAME "linux_ngedk" +#define NGEDK_MODULE_MAJOR 62 + +/*! Must be updated if backward compatibility is broken. */ +#define NGEDK_IOC_VERSION 1 + +/*! LUEDK IOCTL command magic. */ +#define NGEDK_IOC_MAGIC 'L' + +/*! Maximum number of mHosts supported per switch device. */ +#ifndef MCS_NUM_UC +#define MCS_NUM_UC 6 +#endif + +/*! + * \name IOCTL commands for the NGEDK kernel module. + * \anchor NGEDK_IOC_xxx + * + * Note that we use __u64 for the IOCTL parameter size because + * sizeof(void *) is different between 32-bit and 64-bit code, and we + * need a 32-bit user mode application to generate the same IOCTL + * command codes as a 64-bit kernel when using the _IOW macro. + */ + +/*! \{ */ + +/*! Get kernel module information. */ +#define NGEDK_IOC_MOD_INFO _IOW(NGEDK_IOC_MAGIC, 0, __u64) + +/*! Attach EDK instance. */ +#define NGEDK_IOC_ATTACH_INST _IOW(NGEDK_IOC_MAGIC, 1, __u64) + +/*! Get EDK DMA memory information. */ +#define NGEDK_IOC_GET_DMA_INFO _IOW(NGEDK_IOC_MAGIC, 2, __u64) + +/*! Enable EDK interrupts in this unit. */ +#define NGEDK_IOC_INTR_ENABLE _IOW(NGEDK_IOC_MAGIC, 3, __u64) + +/*! Disable EDK interrupts in this unit. */ +#define NGEDK_IOC_INTR_DISABLE _IOW(NGEDK_IOC_MAGIC, 4, __u64) + +/*! Set Interrupt registers and mask values used by the EDK. */ +#define NGEDK_IOC_INTR_SET _IOW(NGEDK_IOC_MAGIC, 5, __u64) + +/*! Wait for an EDK interrupt. */ +#define NGEDK_IOC_INTR_WAIT _IOW(NGEDK_IOC_MAGIC, 6, __u64) + +/*! Handle EDK software interrupt. */ +#define NGEDK_IOC_SW_INTR _IOW(NGEDK_IOC_MAGIC, 7, __u64) + +/*! Handle EDK timer interrupt. */ +#define NGEDK_IOC_TIMER_INTR _IOW(NGEDK_IOC_MAGIC, 8, __u64) + +/*! \} */ + +/*! IOCTL command return code for success. */ +#define NGEDK_IOC_SUCCESS 0 + +/*! IOCTL command return code for failure. */ +#define NGEDK_IOC_FAIL ((__u32)-1) + +/*! + * \name EDK IOC flags. + * \anchor NGEDK_IOC_F_xxx + */ + +/*! \{ */ + +/*! Interrupt enable/disable registers are "write 1 to clear". */ +#define NGEDK_IOC_F_W1TC (1 << 0) + +/*! \} */ + +/*! Kernel module information. */ +struct ngedk_ioc_mod_info_s { + + /*! IOCTL version used by kernel module. */ + __u16 version; +}; + +/*! Attach EDK Instance */ +struct ngedk_ioc_attach_inst_s { + + /*! HostRAM size for this instance. */ + __u32 size_mb; +}; + +/*! Get EDK DMA information */ +struct ngedk_ioc_dma_info_s { + + /*! Virtual address */ + __u64 vaddr; + + /*! Physical address */ + __u64 paddr; + + /*! Bus address as maped by IOMMU */ + __u64 baddr; + + /*! DMA pool size */ + __u32 size; +}; + +/* Set details of interrupts handled by EDK */ +struct ngedk_ioc_intr_s { + + /*! Active cores */ + __u32 active_bmp; + + /*! Timer interrupts status offset */ + __u32 timer_intrc_stat_reg; + + /*! Timer interrupts disable offset */ + __u32 timer_intrc_disable_reg; + + /*! Timer interrupts mask */ + __u32 timer_intrc_mask_val; + + /*! Bitmap of cores that triggered SW interrupt. */ + __u32 sw_intr_cores; + + /*! EDK ioctl flags (\ref NGEDK_IOC_F_xxx). */ + __u32 flags; +}; + +/*! IOCTL operation data. */ +struct ngedk_ioc_sw_intr_s { + + /*! mHost core number corresponding to this SW interrupt */ + __u32 uc; + +}; + +/*! IOCTL operation data. */ +union ngedk_ioc_op_s { + + /*! Get kernel module information. */ + struct ngedk_ioc_mod_info_s mod_info; + + /*! Attach EDK Instance */ + struct ngedk_ioc_attach_inst_s attach_inst; + + /*! EDK DMA information */ + struct ngedk_ioc_dma_info_s dma_info; + + /*! EDK Interrupt setting */ + struct ngedk_ioc_intr_s edk_intr; + + /*! EDK software interrupt */ + struct ngedk_ioc_sw_intr_s sw_intr; +}; + +/*! IOCTL command message. */ +typedef struct ngedk_ioc_cmd_s { + + /*! Device handle. */ + __u32 devid; + + /*! Return code (0 means success). */ + __u32 rc; + + /*! IOCTL operation. */ + union ngedk_ioc_op_s op; + +} ngedk_ioc_cmd_t; + +#endif /* NGEDK_IOCTL_H */ diff --git a/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngedk_kapi.h b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngedk_kapi.h new file mode 100644 index 0000000..8dc60a5 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngedk_kapi.h @@ -0,0 +1,52 @@ +/*! \file ngedk_kapi.h + * + * NGEDK kernel API. + * + * This file is intended for use by other kernel modules relying on the NGEDK. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGEDK_KAPI_H +#define NGEDK_KAPI_H + +/*! + * \brief Converts physical address to virtual address. + * + * \param [in] paddr physical address. + * + * \retval void * Corresponding virtual address. + */ +extern void * +ngedk_dmamem_map_p2v(dma_addr_t paddr); + +#endif /* NGEDK_KAPI_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_dev.h b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_dev.h new file mode 100644 index 0000000..d58999b --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_dev.h @@ -0,0 +1,480 @@ +/*! \file ngknet_dev.h + * + * NGKNET device definitions. + * + * This file is intended for use in both kernel mode and user mode. + * + * IMPORTANT! + * All shared structures must be properly 64-bit aligned. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_DEV_H +#define NGKNET_DEV_H + +#include + +/*! Maximum number of devices supported */ +#ifdef NGBDE_NUM_SWDEV_MAX +#define NUM_PDMA_DEV_MAX NGBDE_NUM_SWDEV_MAX +#else +#define NUM_PDMA_DEV_MAX 16 +#endif + +/*! Device name length */ +#define NGKNET_DEV_NAME_MAX 16 + +/*! Maximum number of virtual network devices */ +#ifndef NGKNET_NETIF_MAX +#define NUM_VDEV_MAX 128 +#else +#define NUM_VDEV_MAX NGKNET_NETIF_MAX +#endif + +/*! Maximum number of filters */ +#ifndef NGKNET_FILTER_MAX +#define NUM_FILTER_MAX 128 +#else +#define NUM_FILTER_MAX NGKNET_FILTER_MAX +#endif + +/*! + * \brief System network interface + * + * Network interface types: + * + * NGKNET_NETIF_T_VLAN + * Transmits to this interface will go to ingress PIPE of switch + * CPU port using specified VLAN ID. Packet will be switched. + * + * NGKNET_NETIF_T_PORT + * Transmits to this interface will go to unmodified to specified + * physical switch port. All switching logic is bypassed. Meta data + * should be provided when this interface is created. + * + * NGKNET_NETIF_T_META + * Transmits to this interface will be done using raw meta data + * as DMA descriptors. + * + * Network interface flags: + * + * NGKNET_NETIF_F_RCPU_ENCAP + * Use RCPU encapsulation for packets that enter and exit this + * interface. + * + * NGKNET_NETIF_F_ADD_TAG + * Add VLAN tag to packets sent directly to physical port. + * + * NGKNET_NETIF_F_BIND_CHAN + * Bind this interface to a Rx channel. + */ +/*! Max network interface name length */ +#define NGKNET_NETIF_NAME_MAX 16 +/*! Max network interface meta bytes */ +#if defined(BCM_DNX_SUPPORT) || defined(BCM_DNXF_SUPPORT) +#define NGKNET_NETIF_META_MAX 64 +#else +#define NGKNET_NETIF_META_MAX 32 +#endif + +/*! Max netif user data in bytes */ +#define NGKNET_NETIF_USER_DATA 64 + +/*! Send packets to switch */ +#define NGKNET_NETIF_T_VLAN 0 +/*! Send packets to port */ +#define NGKNET_NETIF_T_PORT 1 +/*! Send packets with matadata attached */ +#define NGKNET_NETIF_T_META 2 + +/*! Send packets with RCPU encapsulation */ +#define NGKNET_NETIF_F_RCPU_ENCAP (1U << 0) +/*! Send packets with vlan tag */ +#define NGKNET_NETIF_F_ADD_TAG (1U << 1) +/*! Bind network interface to Rx channel */ +#define NGKNET_NETIF_F_BIND_CHAN (1U << 2) +/*! Create network interface with specified ID */ +#define NGKNET_NETIF_F_WITH_ID (1U << 3) +/*! Replace network interface with ID. */ +#define NGKNET_NETIF_F_REPLACE (1U << 4) +/*! Use shared net device on composite devices. */ +#define NGKNET_NETIF_F_USE_SHARED_NDEV (1U << 10) + +/*! + * \brief Network interface description. + */ +typedef struct ngknet_netif_s { + /*! This network interface ID */ + uint16_t id; + + /*! Next network interface ID */ + uint16_t next; + + /*! Network interface type */ + uint16_t type; + + /*! Network interface flags */ + uint16_t flags; + + /*! Network interface VLAN ID */ + uint16_t vlan; + + /*! Network interface MAC address */ + uint8_t macaddr[6]; + + /*! Network interface MTU */ + uint32_t mtu; + + /*! Network interface bound to channel */ + uint32_t chan; + + /*! Network interface port */ + uint32_t port; + + /*! Network interface name */ + char name[NGKNET_NETIF_NAME_MAX]; + + /*! Metadata offset from Ethernet header */ + uint16_t meta_off; + + /*! Metadata length */ + uint16_t meta_len; + + /*! Metadata used to send packets to physical port */ + uint8_t meta_data[NGKNET_NETIF_META_MAX]; + + /*! User data gotten back through callbacks */ + uint8_t user_data[NGKNET_NETIF_USER_DATA]; +} ngknet_netif_t; + +/*! + * \brief Packet filters + * + * Filters work like software TCAMs where a mask is applied to the + * source data, and the result is then compared to the filter data. + * + * Filters are checked in priority order with the lowest priority + * values being checked first (i.e. 0 is the highest priority). + * + * Filter types: + * + * NGKNET_FILTER_T_RX_PKT + * Filter data and mask are applied to the Rx DMA control block + * as well as to the Rx packet contents. + * + * Destination types: + * + * NGKNET_FILTER_DEST_T_NULL + * Packet is dropped. + * + * NGKNET_FILTER_DEST_T_NETIF + * Packet is sent to network interface with ID . + * + * NGKNET_FILTER_DEST_T_VNET + * Packet is sent to VNET in user space. + * + * NGKNET_FILTER_DEST_T_CB + * Packet is sent to kernel filter call-back function for further filtering. + * + * Filter flags: + * + * NGKNET_FILTER_F_ANY_DATA + * When this flags is set the filter will match any packet on + * the associated unit. + * + * NGKNET_FILTER_F_STRIP_TAG + * Strip VLAN tag before packet is sent to destination. + */ +/*! Roundup to word */ +#define NGKNET_BYTES2WORDS(bytes) ((bytes + 3) / 4) + +/*! Max filter description length */ +#define NGKNET_FILTER_DESC_MAX 32 +/*! Max filter bytes size */ +#define NGKNET_FILTER_BYTES_MAX 256 +/*! Max filter words size */ +#define NGKNET_FILTER_WORDS_MAX NGKNET_BYTES2WORDS(NGKNET_FILTER_BYTES_MAX) +/*! Max filter user data in bytes */ +#define NGKNET_FILTER_USER_DATA 64 + +/*! Filter to Rx */ +#define NGKNET_FILTER_T_RX_PKT 1 + +/*! Drop packet */ +#define NGKNET_FILTER_DEST_T_NULL 0 +/*! Send packet to netif */ +#define NGKNET_FILTER_DEST_T_NETIF 1 +/*! Send packet to VNET */ +#define NGKNET_FILTER_DEST_T_VNET 2 +/*! Send packet to kernel filter call-back function */ +#define NGKNET_FILTER_DEST_T_CB 3 + +/*! Match any data */ +#define NGKNET_FILTER_F_ANY_DATA (1U << 0) +/*! Strip vlan tag */ +#define NGKNET_FILTER_F_STRIP_TAG (1U << 1) +/*! Match Rx channel */ +#define NGKNET_FILTER_F_MATCH_CHAN (1U << 2) +/*! Filter created with raw metadata */ +#define NGKNET_FILTER_F_RAW_PMD (1U << 15) + +/*! + * \brief Filter description. + */ +typedef struct ngknet_filter_s { + /*! This filter ID */ + uint16_t id; + + /*! Next filter ID */ + uint16_t next; + + /*! Filter type. Refer to \ref NGKNET_FILTER_T_XXX. */ + uint16_t type; + + /*! Filter flags. Refer to \ref NGKNET_FILTER_F_XXX. */ + uint16_t flags; + + /*! Filter priority */ + uint32_t priority; + + /*! Filter belong to */ + uint32_t chan; + + /*! Filter description */ + char desc[NGKNET_FILTER_DESC_MAX]; + + /*! Destination type. Refer to \ref NGKNET_FILTER_DEST_T_XXX. */ + uint16_t dest_type; + + /*! Destination network interface ID */ + uint16_t dest_id; + + /*! Destination network interface protocol type */ + uint16_t dest_proto; + + /*! Mirror type */ + uint16_t mirror_type; + + /*! Mirror network interface ID */ + uint16_t mirror_id; + + /*! Mirror network interface protocol type */ + uint16_t mirror_proto; + + /*! Out band data offset */ + uint16_t oob_data_offset; + + /*! Out band data size */ + uint16_t oob_data_size; + + /*! Packet data offset */ + uint16_t pkt_data_offset; + + /*! Packet data size */ + uint16_t pkt_data_size; + + /*! Filtering data */ + union { + uint8_t b[NGKNET_FILTER_BYTES_MAX]; + uint32_t w[NGKNET_FILTER_WORDS_MAX]; + } data; + + /*! Filtering mask */ + union { + uint8_t b[NGKNET_FILTER_BYTES_MAX]; + uint32_t w[NGKNET_FILTER_WORDS_MAX]; + } mask; + + /*! User data gotten back through callbacks */ + uint8_t user_data[NGKNET_FILTER_USER_DATA]; +} ngknet_filter_t; + +/*! + * \brief Device information. + */ +typedef struct ngknet_dev_info_s { + /*! Device number (from BDE) */ + int dev_no; + + /*! Device ID */ + uint32_t dev_id; + + /*! Device type string */ + char type_str[NGKNET_DEV_NAME_MAX]; + + /*! Device variant string */ + char var_str[NGKNET_DEV_NAME_MAX]; + + /*! Virtual network devices, pointer to ngknet_dev.vdev[] */ + struct net_device **vdev; +} ngknet_dev_info_t; + +/*! + * \brief Device configuration structure. + */ +typedef struct ngknet_dev_cfg_s { + /*! Device name */ + char name[NGKNET_DEV_NAME_MAX]; + + /*! Device type string */ + char type_str[NGKNET_DEV_NAME_MAX]; + + /*! Device variant string */ + char var_str[NGKNET_DEV_NAME_MAX]; + + /*! Device ID */ + uint32_t dev_id; + + /*! Device mode */ + int mode; + + /*! Number of groups */ + uint32_t nb_grp; + + /*! Bitmap of groups */ + uint32_t bm_grp; + + /*! Rx packet header size */ + uint32_t rx_ph_size; + + /*! Tx packet header size */ + uint32_t tx_ph_size; + + /*! Base network interface */ + ngknet_netif_t base_netif; + + /*! Configuration flags */ + uint32_t flags; + /*! Rx polling for single queue */ +#define NGKNET_RX_POLL_SQ (1 << 0) +} ngknet_dev_cfg_t; + +/*! + * \brief Channel configure structure. + */ +typedef struct ngknet_chan_cfg_s { + /*! Channel number */ + int chan; + + /*! Number of descriptors */ + uint32_t nb_desc; + + /*! Rx buffer size */ + uint32_t rx_buf_size; + + /*! Channel control */ + uint32_t chan_ctrl; + /*! Packet_byte_swap */ +#define NGKNET_PKT_BYTE_SWAP (1 << 0) + /*! Non packet_byte_swap */ +#define NGKNET_OTH_BYTE_SWAP (1 << 1) + /*! Header_byte_swap */ +#define NGKNET_HDR_BYTE_SWAP (1 << 2) + + /*! Rx or Tx */ + int dir; + /*! Rx channel */ +#define NGKNET_RX_CHAN 0 + /*! Tx channel */ +#define NGKNET_TX_CHAN 1 + + /*! Pipe specified for Rx/Tx */ + int pipe; +} ngknet_chan_cfg_t; + +/*! + * \brief RCPU header structure. + */ +struct ngknet_rcpu_hdr { + /*! Destination MAC address */ + uint8_t dst_mac[6]; + + /*! Source MAC address */ + uint8_t src_mac[6]; + + /*! VLAN TPID */ + uint16_t vlan_tpid; + + /*! VLAN TCI */ + uint16_t vlan_tci; + + /*! Ethernet type */ + uint16_t eth_type; + + /*! Packet signature */ + uint16_t pkt_sig; + + /*! Operation code */ + uint8_t op_code; + + /*! Flags */ + uint8_t flags; + + /*! Transaction number */ + uint16_t trans_id; + + /*! Packet data length */ + uint16_t data_len; + + /*! Header profile */ + uint16_t hdr_prof; + + /*! packet meta data length */ + uint8_t meta_len; + + /*! Transmission queue number */ + uint8_t queue_id; + + /*! Reserved must be 0 */ + uint16_t rsvd; +}; + +/*! RCPU Rx operation */ +#define RCPU_OPCODE_RX 0x10 +/*! RCPU Tx operation */ +#define RCPU_OPCODE_TX 0x20 + +/*! RCPU purge flag */ +#define RCPU_FLAG_PURGE (1 << 0) +/*! RCPU pause flag */ +#define RCPU_FLAG_PAUSE (1 << 1) +/*! RCPU modhdr flag */ +#define RCPU_FLAG_MODHDR (1 << 2) +/*! RCPU bind queue flag */ +#define RCPU_FLAG_BIND_QUE (1 << 3) +/*! RCPU no pad flag */ +#define RCPU_FLAG_NO_PAD (1 << 4) +/*! RCPU data RAW mode */ +#define RCPU_FLAG_DATA_RAW (1 << 5) + +#endif /* NGKNET_DEV_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_ioctl.h b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_ioctl.h new file mode 100644 index 0000000..5818081 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_ioctl.h @@ -0,0 +1,126 @@ +/*! \file ngknet_ioctl.h + * + * NGKNET I/O control definitions. + * + * This file is intended for use in both kernel mode and user mode. + * + * IMPORTANT! + * All shared structures must be properly 64-bit aligned. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_IOCTL_H +#define NGKNET_IOCTL_H + +/*! Module information */ +#define NGKNET_MODULE_NAME "linux-ngknet" +#define NGKNET_MODULE_MAJOR 123 + +/*! Must be updated if backward compatibility is broken */ +#define NGKNET_IOC_VERSION 3 + +/*! Max number of input arguments */ +#define NGKNET_IOC_IARG_MAX 2 + +#define NGKNET_IOC_MAGIC 'K' + +#define NGKNET_VERSION_GET _IOR(NGKNET_IOC_MAGIC, 0xa0, unsigned int) +#define NGKNET_RX_RATE_LIMIT _IOWR(NGKNET_IOC_MAGIC, 0xa1, unsigned int) +#define NGKNET_DEV_INIT _IOWR(NGKNET_IOC_MAGIC, 0xb0, unsigned int) +#define NGKNET_DEV_DEINIT _IOWR(NGKNET_IOC_MAGIC, 0xb1, unsigned int) +#define NGKNET_DEV_SUSPEND _IOWR(NGKNET_IOC_MAGIC, 0xb2, unsigned int) +#define NGKNET_DEV_RESUME _IOWR(NGKNET_IOC_MAGIC, 0xb3, unsigned int) +#define NGKNET_DEV_VNET_WAIT _IOWR(NGKNET_IOC_MAGIC, 0xb4, unsigned int) +#define NGKNET_DEV_HNET_WAKE _IOWR(NGKNET_IOC_MAGIC, 0xb5, unsigned int) +#define NGKNET_DEV_VNET_DOCK _IOWR(NGKNET_IOC_MAGIC, 0xb6, unsigned int) +#define NGKNET_DEV_VNET_UNDOCK _IOWR(NGKNET_IOC_MAGIC, 0xb7, unsigned int) +#define NGKNET_QUEUE_CONFIG _IOWR(NGKNET_IOC_MAGIC, 0xc0, unsigned int) +#define NGKNET_QUEUE_QUERY _IOR(NGKNET_IOC_MAGIC, 0xc1, unsigned int) +#define NGKNET_RCPU_CONFIG _IOWR(NGKNET_IOC_MAGIC, 0xc2, unsigned int) +#define NGKNET_RCPU_GET _IOR(NGKNET_IOC_MAGIC, 0xc3, unsigned int) +#define NGKNET_NETIF_CREATE _IOWR(NGKNET_IOC_MAGIC, 0xd0, unsigned int) +#define NGKNET_NETIF_DESTROY _IOWR(NGKNET_IOC_MAGIC, 0xd1, unsigned int) +#define NGKNET_NETIF_GET _IOR(NGKNET_IOC_MAGIC, 0xd2, unsigned int) +#define NGKNET_NETIF_NEXT _IOR(NGKNET_IOC_MAGIC, 0xd3, unsigned int) +#define NGKNET_NETIF_LINK_SET _IOW(NGKNET_IOC_MAGIC, 0xd4, unsigned int) +#define NGKNET_FILT_CREATE _IOWR(NGKNET_IOC_MAGIC, 0xe0, unsigned int) +#define NGKNET_FILT_DESTROY _IOWR(NGKNET_IOC_MAGIC, 0xe1, unsigned int) +#define NGKNET_FILT_GET _IOR(NGKNET_IOC_MAGIC, 0xe2, unsigned int) +#define NGKNET_FILT_NEXT _IOR(NGKNET_IOC_MAGIC, 0xe3, unsigned int) +#define NGKNET_INFO_GET _IOR(NGKNET_IOC_MAGIC, 0xf0, unsigned int) +#define NGKNET_STATS_GET _IOR(NGKNET_IOC_MAGIC, 0xf1, unsigned int) +#define NGKNET_STATS_RESET _IOWR(NGKNET_IOC_MAGIC, 0xf2, unsigned int) +#define NGKNET_PTP_DEV_CTRL _IOWR(NGKNET_IOC_MAGIC, 0x90, unsigned int) +#define NGKNET_MESSAGE _IOWR(NGKNET_IOC_MAGIC, 0x80, unsigned int) + +/*! Kernel module information. */ +struct ngknet_ioc_mod_info { + /*! IOCTL version used by kernel module */ + uint32_t version; +}; + +/*! Data transmission */ +struct ngknet_ioc_data_xmit { + /*! Data buffer address */ + uint64_t buf; + + /*! Data buffer length */ + uint32_t len; +}; + +/*! IOCTL operations */ +union ngknet_ioc_op { + /*! Get module info */ + struct ngknet_ioc_mod_info info; + /*! Transmit data */ + struct ngknet_ioc_data_xmit data; +}; + +/*! + * \brief NGKNET IOCTL command message. + */ +struct ngknet_ioctl { + /*! Device number */ + uint32_t unit; + + /*! Return code (0 means success) */ + uint32_t rc; + + /*! Input arguments */ + int iarg[NGKNET_IOC_IARG_MAX]; + + /*! IOCTL operation */ + union ngknet_ioc_op op; +}; + +#endif /* NGKNET_IOCTL_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_kapi.h b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_kapi.h new file mode 100644 index 0000000..89126d3 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_kapi.h @@ -0,0 +1,436 @@ +/*! \file ngknet_kapi.h + * + * NGKNET kernel API. + * + * This file is intended for use by other kernel modules relying on the KNET. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_KAPI_H +#define NGKNET_KAPI_H + +#include +#include + +/*! + * \brief NGKNET callback description. + */ +struct ngknet_callback_desc { + /* Device information */ + ngknet_dev_info_t *dinfo; + + /*! Network interface */ + ngknet_netif_t *netif; + + /*! Matched filter */ + ngknet_filter_t *filt; + + /*! Packet meta data */ + uint8_t *pmd; + + /*! Packet meta data length */ + int pmd_len; + + /*! Packet data length */ + int pkt_len; + + /*! Network device */ + struct net_device *net_dev; +}; + +/*! SKB callback data */ +#define NGKNET_SKB_CB(_skb) ((struct ngknet_callback_desc *)_skb->cb) + +/*! + * PHC specific private data + */ +struct ngknet_ptp_data { + /*! Physical port */ + int phy_port; + + /*! HW timestamp Tx type */ + int hwts_tx_type; +}; + +/*! TX/RX callback init */ +typedef void +(*ngknet_dev_init_cb_f)(ngknet_dev_info_t *dinfo); + +/*! Handle Rx packet */ +typedef struct sk_buff * +(*ngknet_rx_cb_f)(struct sk_buff *skb); + +/*! Handle Tx packet */ +typedef struct sk_buff * +(*ngknet_tx_cb_f)(struct sk_buff *skb); + +/*! Handle Netif callback */ +typedef int +(*ngknet_netif_cb_f)(ngknet_dev_info_t *dinfo, ngknet_netif_t *netif); + +/*! Handle Filter callback */ +typedef struct sk_buff * +(*ngknet_filter_cb_f)(struct sk_buff *skb, ngknet_filter_t **filt); + +/*! PTP Rx/Tx config set */ +typedef int +(*ngknet_ptp_config_set_cb_f)(ngknet_dev_info_t *dinfo, ngknet_netif_t *netif, int *value); + +/*! PTP Rx/Tx HW timestamp get */ +typedef int +(*ngknet_ptp_hwts_get_cb_f)(struct sk_buff *skb, uint64_t *ts); + +/*! PTP Tx meta set */ +typedef int +(*ngknet_ptp_meta_set_cb_f)(struct sk_buff *skb); + +/*! PTP PHC index get */ +typedef int +(*ngknet_ptp_phc_index_get_cb_f)(ngknet_dev_info_t *dinfo, ngknet_netif_t *netif, int *index); + +/*! PTP device control */ +typedef int +(*ngknet_ptp_dev_ctrl_cb_f)(ngknet_dev_info_t *dinfo, int cmd, char *data, int len); + +/*! PTP RX Preprocessing */ +typedef int +(*ngknet_ptp_rx_pre_process_cb_f)(struct sk_buff *skb, uint32_t *cust_hdr_len); + +/*! + * \brief Register TX/RX callback device initialization callback function. + * + * The device initialization callback allows an external module to + * perform device-specific initialization in preparation for Tx and Rx + * packet processing. + * + * \param [in] dev_init_cb TX/RX callback device initialization callback + * function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_dev_init_cb_register(ngknet_dev_init_cb_f dev_init_cb); + +/*! + * \brief Unegister TX/RX callback device initialization callback function. + * + * The device initialization callback allows an external module to + * perform device-specific initialization in preparation for Tx and Rx + * packet processing. + * + * \param [in] dev_init_cb TX/RX callback device initialization callback + * function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_dev_init_cb_unregister(ngknet_dev_init_cb_f dev_init_cb); + +/*! + * \brief Register Rx callback. + * + * \param [in] rx_cb Rx callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_rx_cb_register(ngknet_rx_cb_f rx_cb); + +/*! + * \brief Unregister Rx callback. + * + * \param [in] rx_cb Rx callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_rx_cb_unregister(ngknet_rx_cb_f rx_cb); + +/*! + * \brief Register Tx callback. + * + * \param [in] tx_cb Tx callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_tx_cb_register(ngknet_tx_cb_f tx_cb); + +/*! + * \brief Unregister Tx callback. + * + * \param [in] tx_cb Tx callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_tx_cb_unregister(ngknet_tx_cb_f tx_cb); + +/*! + * \brief Register callback for network interface creation. + * + * Register a function to be called whenever a virtual network interface + * is created in the KNET kernel module. + * + * \param [in] netif_cb Callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_netif_create_cb_register(ngknet_netif_cb_f netif_cb); + +/*! + * \brief Unregister callback for network interface creation. + * + * \param [in] netif_cb Callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_netif_create_cb_unregister(ngknet_netif_cb_f netif_cb); + +/*! + * \brief Register callback for network interface destruction. + * + * Register a function to be called whenever a virtual network interface + * is destroyed in the KNET kernel module. + * + * \param [in] netif_cb Callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_netif_destroy_cb_register(ngknet_netif_cb_f netif_cb); + +/*! + * \brief Unregister callback for network interface destruction. + * + * \param [in] netif_cb Callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_netif_destroy_cb_unregister(ngknet_netif_cb_f netif_cb); + +/*! + * \brief Register filter callback. + * + * \param [in] filter_cb Filter callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_filter_cb_register(ngknet_filter_cb_f filter_cb); + +/*! + * \brief Register filter callback by name. + * + * \param [in] filter_cb Filter callback function. + * \param [in] desc Filter description. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_filter_cb_register_by_name(ngknet_filter_cb_f filter_cb, const char *desc); + +/*! + * \brief Unregister filter callback. + * + * \param [in] filter_cb Filter callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_filter_cb_unregister(ngknet_filter_cb_f filter_cb); + +/*! + * \brief Register PTP Rx config set callback. + * + * \param [in] ptp_rx_config_set_cb Rx config set callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_rx_config_set_cb_register(ngknet_ptp_config_set_cb_f ptp_rx_config_set_cb); + +/*! + * \brief Unregister PTP Rx config set callback. + * + * \param [in] ptp_rx_config_set_cb Rx config set callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_rx_config_set_cb_unregister(ngknet_ptp_config_set_cb_f ptp_rx_config_set_cb); + +/*! + * \brief Register PTP Tx config set callback. + * + * \param [in] ptp_tx_config_set_cb Tx config set callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_tx_config_set_cb_register(ngknet_ptp_config_set_cb_f ptp_tx_config_set_cb); + +/*! + * \brief Unregister PTP Tx config set callback. + * + * \param [in] ptp_tx_config_set_cb Tx config set callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_tx_config_set_cb_unregister(ngknet_ptp_config_set_cb_f ptp_tx_config_set_cb); + +/*! + * \brief Register PTP Rx HW timestamp get callback. + * + * \param [in] ptp_rx_hwts_get_cb Rx HW timestamp get callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_rx_hwts_get_cb_register(ngknet_ptp_hwts_get_cb_f ptp_rx_hwts_get_cb); + +/*! + * \brief Unregister PTP Rx HW timestamp get callback. + * + * \param [in] ptp_rx_hwts_get_cb Rx HW timestamp get callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_rx_hwts_get_cb_unregister(ngknet_ptp_hwts_get_cb_f ptp_rx_hwts_get_cb); + +/*! + * \brief Register PTP Tx HW timestamp get callback. + * + * \param [in] ptp_tx_hwts_get_cb Tx HW timestamp get callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_tx_hwts_get_cb_register(ngknet_ptp_hwts_get_cb_f ptp_tx_hwts_get_cb); + +/*! + * \brief Unregister PTP Tx HW timestamp get callback. + * + * \param [in] ptp_tx_hwts_get_cb Tx HW timestamp get callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_tx_hwts_get_cb_unregister(ngknet_ptp_hwts_get_cb_f ptp_tx_hwts_get_cb); + +/*! + * \brief Register PTP Tx meta set callback. + * + * \param [in] ptp_tx_meta_set_cb Tx meta set callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_tx_meta_set_cb_register(ngknet_ptp_meta_set_cb_f ptp_tx_meta_set_cb); + +/*! + * \brief Unregister PTP Tx meta set callback. + * + * \param [in] ptp_tx_meta_set_cb Tx meta set callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_tx_meta_set_cb_unregister(ngknet_ptp_meta_set_cb_f ptp_tx_meta_set_cb); + +/*! + * \brief Register PTP PHC index get callback. + * + * \param [in] ptp_phc_index_get_cb PHC index get callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_phc_index_get_cb_register(ngknet_ptp_phc_index_get_cb_f ptp_phc_index_get_cb); + +/*! + * \brief Unregister PTP PHC index get callback. + * + * \param [in] ptp_phc_index_get_cb PHC index get callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_phc_index_get_cb_unregister(ngknet_ptp_phc_index_get_cb_f ptp_phc_index_get_cb); + +/*! + * \brief Register PTP device control callback. + * + * \param [in] ptp_dev_ctrl_cb Device control callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_dev_ctrl_cb_register(ngknet_ptp_dev_ctrl_cb_f ptp_dev_ctrl_cb); + +/*! + * \brief Unregister PTP device control callback. + * + * \param [in] ptp_dev_ctrl_cb Device control callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_dev_ctrl_cb_unregister(ngknet_ptp_dev_ctrl_cb_f ptp_dev_ctrl_cb); + +/*! + * \brief Register PTP RX pre processing callback. + * + * \param [in] ptp_rx_pre_process_cb RX pre processing callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_rx_pre_process_cb_register(ngknet_ptp_rx_pre_process_cb_f ptp_rx_pre_process_cb); + +/*! + * \brief Unregister PTP RX pre processing callback. + * + * \param [in] ptp_rx_pre_process_cb RX pre processing callback function. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_rx_pre_process_cb_unregister(ngknet_ptp_rx_pre_process_cb_f ptp_rx_pre_process_cb); + +#endif /* NGKNET_KAPI_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_msg.h b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_msg.h new file mode 100644 index 0000000..720ab4a --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngknet_msg.h @@ -0,0 +1,83 @@ +/*! \file ngknet_msg.h + * + * NGKNET messages. + * + * This file is intended for use by other kernel modules relying on the KNET. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_MSG_H +#define NGKNET_MSG_H + +#include + +#define NGKNET_MSG_CMD_RX_START_INFO (1) +#define NGKNET_MSG_CMD_DBG_LVL_INFO (2) +#define NGKNET_MSG_CMD_SCRATCH_INFO (3) +#define NGKNET_MSG_CMD_SCRATCH_INFO_FETCH (4) + +#define NGKNET_SCRATCH_DATA_WORDS 4 +#define NGKNET_SCRATCH_DATA_BYTES 16 +#define NGKNET_OAMP_PORT_MAX 8 + +typedef struct ngknet_msg_rx_start_info_s { + uint32_t flags; +#define NGKNET_F_RX_START_INFO_DELIVERED (0x1 << 0) +#define NGKNET_F_RX_PKT_UNPARSED (0x1 << 1) +#define NGKNET_F_RX_PKT_AI_FORMAT (0x1 << 2) + uint32_t enet_channels; + uint32_t system_headers_mode; + uint8_t ftmh_lb_key_size; + uint8_t ftmh_stacking_ext_size; + uint8_t udh_enabled; + uint8_t pph_base_size; + uint8_t pph_lif_ext_size[8]; + uint8_t udh_length_type[4]; + uint16_t oamp_system_port_0; + uint16_t oamp_system_port_1; + uint16_t up_mep_ingress_cpu_trap_id1; + uint16_t up_mep_ingress_cpu_trap_id2; + uint32_t oamp_port_number; + uint32_t oamp_ports[NGKNET_OAMP_PORT_MAX]; + uint8_t spa_mode; +} ngknet_msg_rx_start_info_t; + +typedef struct ngknet_msg_scratch_data_s { + int filter_id; + int spa_unit; + uint32_t match_flags; + uint32_t data[NGKNET_SCRATCH_DATA_WORDS]; + uint32_t mask[NGKNET_SCRATCH_DATA_WORDS]; +} ngknet_msg_scratch_data_t; + +#endif /* NGKNET_MSG_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngptpclock_ioctl.h b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngptpclock_ioctl.h new file mode 100644 index 0000000..e6d0b8e --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/include/lkm/ngptpclock_ioctl.h @@ -0,0 +1,56 @@ +/*! \file ngptpclock_ioctl.h + * + * NGPTPCLOCK I/O control definitions. + * + * This file is intended for use in both kernel mode and user mode. + * + * IMPORTANT! + * All shared structures must be properly 64-bit aligned. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGPTPCLOCK_IOCTL_H +#define NGPTPCLOCK_IOCTL_H + +/* Module Information */ +#define NGPTPCLOCK_MODULE_NAME "linux_ngptpclock" + +/*! + * \brief PTP hardware clock driver commands + */ +/*! Initialize PTP hardware clock driver module */ +#define NGPTPCLOCK_HW_INIT 0 +/*! Clean up PTP hardware clock driver module */ +#define NGPTPCLOCK_HW_CLEANUP 1 + +#endif /* NGPTPCLOCK_IOCTL_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_adapter.c b/systems/linux/kernel/modules/bcm-ngknet/ngknet_adapter.c new file mode 100644 index 0000000..010745c --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_adapter.c @@ -0,0 +1,1096 @@ +/*! \file ngknet_adapter.c + * + * Adapter routines for Linux kernel APIs abstraction. + * + * RX: From CNET ... + * ngknet_dev_pkt_recv() : See bcmxxx_xx_pdma_attach.c : *pdev->pkt_recv()* + * | + * |-> ngknet_adapter_frame_recv() + * | | + * | \-> ngknet_rx_parser() : Parser packet and fill the scratch data. + * | | + * | \-> skb_put(scratch_data) : 16 Bytes + * | + * \-> ngknet_frame_recv() + * | + * |-> ngknet_rx_pkt_filter() + * | | + * | |-> ngknet_filter_match() : if true + * | | | + * | | |-> ngknet_adapter_filter_scratch_data_match() : (DNX devices only) + * | | | + * | | \-> Compare the OOB and scratch data. + * | | + * | |-> ngknet_filter_callback() + * | | + * | \-> ngknet_filter_process() + * | | + * | \-> _adapter_pkt_recv() : *priv->pkt_recv()* + * | | + * | |-> skb_trim(scratch_data) : 16 Bytes + * | | + * | \-> ngknet_pkt_recv() + * | | + * | \-> ngknet_netif_recv() + * | | + * | |-> ngknet_rx_frame_process() + * | | | + * | | |-> Add RCPU encapsulation or strip matadata if needed. + * | | | + * | | \-> rx_cb() + * | | + * | \-> netif_receive_skb() : to netif. + * | + * \-> ngknet_pkt_stats() + * + * TX: To CNET ... + * ngknet_start_xmit() : from netif. + * | + * |-> ngknet_pkt_stats() + * | + * |-> ngknet_tx_frame_process() + * | | + * | |-> Strip RCPU encapsulation, setup CNET packet buffer, add vlan tag. + * | | + * | \-> tx_cb() + * | + * |-> ngknet_tx_queue_schedule() + * | + * |-> skb_tx_timestamp() + * | + * \-> ngknet_adapter_frame_xmit() : *pdev->pkt_xmit()* + * | + * \-> pdev->pkt_xmit() + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include + +#include + +#include "ngknet_adapter.h" +#include "ngknet_parser.h" + +extern struct ngknet_dev ngknet_devices[]; + +static ibde_t *kernel_bde = NULL; +static int debug = 0; + +static struct adapter_dev adapter_devices[NUM_PDMA_DEV_MAX] = {0}; + +#define ADAPTER_RX_START_INFO(_adev) ((_adev)->rsi) +#define ADAPTER_RX_START_INFO_IS_DELIVERED(_adev) (ADAPTER_RX_START_INFO(_adev).flags & NGKNET_RX_START_INFO_DELIVERED) + +/* CMICR interrupts reserved for kernel handler */ +#define CMICR_TXRX_IRQ_MASK 0xffff00 +/* CMICx interrupts reserved for kernel handler */ +#define CMICX_TXRX_IRQ_MASK 0xffffffff + +/* + * PAXB_0_INTC_SET_INTR_ENABLE_REG5r sets interrupt enable bit for interrupts 191 down to 160 + * Packet DMA interrupt enable bit is [168 : 199], here bit [168 : 183] is considered because it is assumed that only cmc0 + * PAXB_0_INTC_INTR_ENABLE_STATUS_REG5 is used to check the intr enabled status. + * PAXB_0_INTC_CLEAR_INTR_ENABLE_REG5 is used to disable the intrs. + */ +#define PAXB_0_INTC_SET_INTR_ENABLE_REG5r 0x0292D114 + +#define CMICX_IRQ_ENABr 0x18013100 + +/* + * Get a 16-bit value from packet offset + * _data Pointer to packet + * _offset Offset + */ +#define PKT_U16_GET(_data, _offset) \ + (uint16_t)(_data[_offset] << 8 | _data[_offset + 1]) + +static void +_adapter_pkt_recv(struct net_device *ndev, struct sk_buff *skb); + +static int +_adapter_info_show( + struct seq_file *m, + void *v) +{ + struct ngknet_dev *dev; + struct adapter_dev *adev; + int di, ai = 0, gi, qi, chan_id, i, j; + int queue, dir; + int hw_grp, hw_que; + char *cmic_type_str[] = ADAPTER_CMIC_TYPE_STR; + + for (di = 0; di < NUM_PDMA_DEV_MAX; di++) { + struct pdma_dev *pdev = NULL; + struct pdma_hw *phw = NULL; + struct net_device *ndev = NULL; + struct ngknet_private *priv = NULL; + + adev = &adapter_devices[di]; + + if (!(adev->flags & ADAPTER_ACTIVE)) { + continue; + } + ai++; + pdev = adev->pdma_dev; + phw = adev->pdma_hw; + dev = adev->dev; + + seq_printf(m, "kdev: %d\n", di); + seq_printf(m, "------------ dev -------------\n"); + seq_printf(m, "device_is_sand(%d): %s\n", di, device_is_sand(di) ? "Yes" : "No"); + seq_printf(m, "------- dev->dev_info --------\n"); + seq_printf(m, "dev_no: %d\n", dev->dev_info.dev_no); + seq_printf(m, "dev_id: 0x%x\n", dev->dev_info.dev_id); + seq_printf(m, "type_str: %s\n", dev->dev_info.type_str); + seq_printf(m, "var_str: %s\n", dev->dev_info.var_str); + seq_printf(m, "------- dev->rcpu_ctrl -------\n"); + seq_printf(m, "dst_mac: "); + for (i = 0; i < 6; i++) { + seq_printf(m, "%02x%s", dev->rcpu_ctrl.dst_mac[i], i == (6-1) ? "\n":":"); + } + seq_printf(m, "src_mac: "); + for (i = 0; i < 6; i++) { + seq_printf(m, "%02x%s", dev->rcpu_ctrl.src_mac[i], i == (6-1) ? "\n":":"); + } + seq_printf(m, "vlan_tpid: 0x%04x (0x%04x)\n", dev->rcpu_ctrl.vlan_tpid, htons(dev->rcpu_ctrl.vlan_tpid)); + seq_printf(m, "vlan_tci: 0x%04x (0x%04x)\n", dev->rcpu_ctrl.vlan_tci, htons(dev->rcpu_ctrl.vlan_tci)); + seq_printf(m, "eth_type: 0x%04x (0x%04x)\n", dev->rcpu_ctrl.eth_type, htons(dev->rcpu_ctrl.eth_type)); + seq_printf(m, "pkt_sig: 0x%04x (0x%04x)\n", dev->rcpu_ctrl.pkt_sig, htons(dev->rcpu_ctrl.pkt_sig)); + seq_printf(m, "trans_id: 0x%04x (0x%04x)\n", dev->rcpu_ctrl.trans_id, htons(dev->rcpu_ctrl.trans_id)); + seq_printf(m, "------- dev->net_dev ----------\n"); + ndev = dev->net_dev; + if (ndev) { + priv = netdev_priv(ndev); + seq_printf(m, "net_dev:\n"); + seq_printf(m, " priv:\n"); + seq_printf(m, " netif.id: %d\n", priv->netif.id); + seq_printf(m, " netif.flags: 0x%x%s\n", priv->netif.flags, priv->netif.flags & NGKNET_NETIF_F_USE_SHARED_NDEV ? "(shared)":""); + seq_printf(m, " pkt_recv: %s\n", priv->pkt_recv == _adapter_pkt_recv ? "_adapter_pkt_recv": priv->pkt_recv ? "ngknet_pkt_recv":""); + seq_printf(m, " users: %d\n", priv->users); + seq_printf(m, " ref_count: %d\n", priv->ref_count); + } + seq_printf(m, "------- dev->bdev[?] ---------\n"); + for (chan_id = 0; chan_id < NUM_Q_MAX; chan_id++) { + ndev = dev->bdev[chan_id]; + if (ndev) { + priv = netdev_priv(ndev); + seq_printf(m, "chan_id: %d\n", chan_id); + seq_printf(m, " priv:\n"); + seq_printf(m, " netif.id: %d\n", priv->netif.id); + seq_printf(m, " netif.flags: 0x%x%s\n", priv->netif.flags, priv->netif.flags & NGKNET_NETIF_F_USE_SHARED_NDEV ? "(shared)":""); + seq_printf(m, " bkn_dev: %s\n", priv->bkn_dev == dev ? "Master":"Slave"); + seq_printf(m, " pkt_recv: %s\n", priv->pkt_recv == _adapter_pkt_recv ? "_adapter_pkt_recv": priv->pkt_recv ? "ngknet_pkt_recv":""); + seq_printf(m, " users: %d\n", priv->users); + seq_printf(m, " ref_count: %d\n", priv->ref_count); + } + } + seq_printf(m, "------- dev->vdev[?] ---------\n"); + seq_printf(m, "num: %ld\n", (long)dev->vdev[0]); + for (i = 1; i < NUM_VDEV_MAX + 1; i++) { + ndev = dev->vdev[i]; + if (ndev) { + priv = netdev_priv(ndev); + seq_printf(m, "netif_id: %d\n", i); + seq_printf(m, " priv:\n"); + seq_printf(m, " netif.id: %d\n", priv->netif.id); + seq_printf(m, " netif.flags: 0x%x%s\n", priv->netif.flags, priv->netif.flags & NGKNET_NETIF_F_USE_SHARED_NDEV ? "(shared)":""); + seq_printf(m, " bkn_dev: %s\n", priv->bkn_dev == dev ? "Master":"Slave"); + seq_printf(m, " pkt_recv: %s\n", priv->pkt_recv == _adapter_pkt_recv ? "_adapter_pkt_recv": priv->pkt_recv ? "ngknet_pkt_recv":""); + seq_printf(m, " users: %d\n", priv->users); + seq_printf(m, " ref_count: %d\n", priv->ref_count); + } + } + seq_printf(m, "------------ adev ------------\n"); + seq_printf(m, "debug: 0x%x\n", debug); + seq_printf(m, "base_addr: %p\n", ngbde_kapi_pio_membase(di)); + seq_printf(m, "cmic_type: %s\n", cmic_type_str[adev->cmic_type]); + seq_printf(m, "nof_chans: %d\n", adev->nof_chans); + seq_printf(m, "irq_mask: 0x%x\n", adev->irq_mask); + seq_printf(m, "irq_mask_reg: 0x%x\n", adev->irq_mask_reg); + seq_printf(m, "irq_fmask: 0x%x\n", adev->irq_fmask); + seq_printf(m, "irq_status_reg: 0x%x\n", adev->irq_status_reg); + seq_printf(m, "irq_mask_cnt: %d\n", adev->irq_mask_cnt); + seq_printf(m, "irq_num: %d\n", adev->irq_num); + seq_printf(m, "isr_connected: %d\n", adev->isr_connected); + seq_printf(m, "isr_received: %d\n", adev->isr_received); + seq_printf(m, "isr_handled: %d\n", adev->isr_handled); +#if ADAPTER_DMA_ADDR_DEBUG + seq_printf(m, "p2l_cnt: %d\n", adev->p2l_cnt); + seq_printf(m, "p2l_baddr: 0x%llx (dma_addr_t %lu)\n", adev->p2l_baddr, sizeof(dma_addr_t)); + seq_printf(m, "p2l_paddr: 0x%lx (sal_paddr_t %lu)\n", adev->p2l_paddr, sizeof(sal_paddr_t)); + seq_printf(m, "p2l_vaddr: %p (void * %lu)\n", adev->p2l_vaddr, sizeof(void *)); + seq_printf(m, "l2p_cnt: %d\n", adev->l2p_cnt); + seq_printf(m, "l2p_vaddr: %p (void * %lu)\n", adev->l2p_vaddr, sizeof(void *)); + seq_printf(m, "l2p_paddr: 0x%lx (sal_paddr_t %lu)\n", adev->l2p_paddr, sizeof(sal_paddr_t)); + seq_printf(m, "l2p_baddr: 0x%llx (dma_addr_t %lu)\n", adev->l2p_baddr, sizeof(dma_addr_t)); +#endif /* ADAPTER_DMA_ADDR_DEBUG */ + seq_printf(m, "iio_base: 0x%x\n", adev->iio_base); + seq_printf(m, "iio_recorder_cnt: %d\n", adev->iio_recorder_cnt); + for (i = 0; i < ADAPTER_IIO_RECORDER_SIZE; i++) { + if (adev->iio_recorder[i].op) { + char *op = adev->iio_recorder[i].op == ADAPTER_IIO_OP_WRITE ? "write" : + adev->iio_recorder[i].op == ADAPTER_IIO_OP_READ ? "read" : "none"; + bool curr = ((adev->iio_recorder_cnt - 1) % ADAPTER_IIO_RECORDER_SIZE) == i; + seq_printf(m, "iio_recorder[%2d]: %s: [0x%x] = 0x%08x %s\n", + i, op, adev->iio_recorder[i].offs, adev->iio_recorder[i].val, curr ? "<--" : ""); + } + } + seq_printf(m, "imask_recorder_cnt: %d\n", adev->imask_recorder_cnt); + for (i = 0; i < ADAPTER_IMASK_RECORDER_SIZE; i++) { + if (adev->imask_recorder[i].mask_val) { + bool curr = ((adev->imask_recorder_cnt - 1) % ADAPTER_IMASK_RECORDER_SIZE) == i; + seq_printf(m, "imask_recorder[%2d]: [%d] = 0x%08x %s\n", + i, adev->imask_recorder[i].inum, adev->imask_recorder[i].mask_val, curr ? "<--" : ""); + } + } + seq_printf(m, "def_netif: %d\n", adev->def_netif); + seq_printf(m, "pkt_recv: %s\n", adev->pkt_recv == _adapter_pkt_recv ? "_adapter_pkt_recv" : adev->pkt_recv ? "ngknet_pkt_recv":""); + seq_printf(m, "------------ rsi -------------\n"); + seq_printf(m, "flags: 0x%x\n", ADAPTER_RX_START_INFO(adev).flags); + seq_printf(m, "enet_channels: 0x%x\n", ADAPTER_RX_START_INFO(adev).enet_channels); + seq_printf(m, "system_headers_mode: 0x%x\n", ADAPTER_RX_START_INFO(adev).system_headers_mode); + seq_printf(m, "ftmh_lb_key_size: %d\n", ADAPTER_RX_START_INFO(adev).ftmh_lb_key_size); + seq_printf(m, "ftmh_stacking_ext_size: %d\n", ADAPTER_RX_START_INFO(adev).ftmh_stacking_ext_size); + seq_printf(m, "pph_base_size: %d\n", ADAPTER_RX_START_INFO(adev).pph_base_size); + for (i = 0; i < 8; i++) { + seq_printf(m, "pph_lif_ext_size[%d]: %d\n",i, ADAPTER_RX_START_INFO(adev).pph_lif_ext_size[i]); + } + seq_printf(m, "udh_enabled: %d\n", ADAPTER_RX_START_INFO(adev).udh_enabled); + for (i = 0; i < 4; i++) { + seq_printf(m, "udh_length_type[%d]: %d\n",i, ADAPTER_RX_START_INFO(adev).udh_length_type[i]); + } + seq_printf(m, "oamp_system_port_0: %d\n", ADAPTER_RX_START_INFO(adev).oamp_system_port_0); + seq_printf(m, "oamp_system_port_1: %d\n", ADAPTER_RX_START_INFO(adev).oamp_system_port_1); + seq_printf(m, "up_mep_ingress_cpu_trap_id1: %d\n", ADAPTER_RX_START_INFO(adev).up_mep_ingress_cpu_trap_id1); + seq_printf(m, "up_mep_ingress_cpu_trap_id2: %d\n", ADAPTER_RX_START_INFO(adev).up_mep_ingress_cpu_trap_id2); + seq_printf(m, "oamp_port_number: %d {", ADAPTER_RX_START_INFO(adev).oamp_port_number); + for (i = 0; i < NGKNET_OAMP_PORT_MAX; i++) { + seq_printf(m, "%d%s", ADAPTER_RX_START_INFO(adev).oamp_ports[i], i == (NGKNET_OAMP_PORT_MAX-1) ? "}\n":","); + } + seq_printf(m, "spa_mode: %d\n", ADAPTER_RX_START_INFO(adev).spa_mode); + seq_printf(m, "------- filter scratch -------\n"); + for (i = 1; i < NUM_FILTER_MAX; i++) { + if (adev->scratch[i].filter_id == i) { + seq_printf(m, "filter_id: %d\n", adev->scratch[i].filter_id); + seq_printf(m, " spa_unit: %d\n", adev->scratch[i].spa_unit); + seq_printf(m, " mflags: 0x%x\n", adev->scratch[i].match_flags); + seq_printf(m, " data: "); + for (j = 0; j < NGKNET_SCRATCH_DATA_WORDS; j++) { + seq_printf(m, "%08x%s", adev->scratch[i].data[j], j == (NGKNET_SCRATCH_DATA_WORDS-1) ? "\n":" "); + } + seq_printf(m, " mask: "); + for (j = 0; j < NGKNET_SCRATCH_DATA_WORDS; j++) { + seq_printf(m, "%08x%s", adev->scratch[i].mask[j], j == (NGKNET_SCRATCH_DATA_WORDS-1) ? "\n":" "); + } + } + } + seq_printf(m, "------------ pdev ------------\n"); + seq_printf(m, "dev_id: 0x%x\n", pdev->dev_id); + seq_printf(m, "dev_type: %d\n", pdev->dev_type); + seq_printf(m, "flags: 0x%x\n", pdev->flags); + seq_printf(m, "mode: %d\n", pdev->mode); + seq_printf(m, "ops: %s\n", pdev->ops ? "Attached" : "Not Attach"); + seq_printf(m, "num_groups: %d\n", pdev->num_groups); + seq_printf(m, "grp_queues: %d\n", pdev->grp_queues); + seq_printf(m, "rx_ph_size: %d\n", pdev->rx_ph_size); + seq_printf(m, "tx_ph_size: %d\n", pdev->tx_ph_size); + seq_printf(m, "ctrl.bm_grp: 0x%x\n", pdev->ctrl.bm_grp); + seq_printf(m, "ctrl.nb_grp: %d\n", pdev->ctrl.nb_grp); + seq_printf(m, "ctrl.bm_txq: 0x%x\n", pdev->ctrl.bm_txq); + seq_printf(m, "ctrl.nb_txq: %d\n", pdev->ctrl.nb_txq); + seq_printf(m, "ctrl.bm_rxq: 0x%x\n", pdev->ctrl.bm_rxq); + seq_printf(m, "ctrl.nb_rxq: %d\n", pdev->ctrl.nb_rxq); + + for (gi = 0; gi < pdev->num_groups; gi++) { + seq_printf(m, " gi %d: %s\n", gi, pdev->ctrl.grp[gi].attached ? "Attached" : ""); + seq_printf(m, " irq_mask: 0x%x\n", pdev->ctrl.grp[gi].irq_mask); + seq_printf(m, " bm_rxq: 0x%x\n", pdev->ctrl.grp[gi].bm_rxq); + for (qi = 0; qi < pdev->grp_queues; qi++) { + if (1 << qi & pdev->ctrl.grp[gi].bm_rxq) { + struct pdma_rx_queue *rxq = NULL; + struct intr_handle *ih = NULL; + pdev->ops->dev_pq_to_lq(pdev, qi + gi * pdev->grp_queues, &queue, &dir); + seq_printf(m, " qi %d:\n", qi); + seq_printf(m, " queue: %d\n", queue); + seq_printf(m, " dir: %d\n", dir); + rxq = (struct pdma_rx_queue *)pdev->ctrl.rx_queue[queue]; + hw_grp = rxq->chan_id / adev->nof_chans; + hw_que = rxq->chan_id % adev->nof_chans; + seq_printf(m, " chan_id: %d\n", rxq->chan_id); + seq_printf(m, " hw_grp: %d\n", hw_grp); + seq_printf(m, " hw_que: %d\n", hw_que); + seq_printf(m, " irq_mask: 0x%x\n", phw->dev->ctrl.grp[hw_grp].irq_mask); + ih = &pdev->ctrl.grp[gi].intr_hdl[qi]; + seq_printf(m, " intr_hdl: group %d chan %d queue %d dir %d budget %d inum %d\n", + ih->group, ih->chan, ih->queue, ih->dir, ih->budget, ih->inum); + seq_printf(m, " intr_flags 0x%x extra_poll %s\n", + ih->intr_flags, ih->extra_poll ? "T":"F"); + } + } + seq_printf(m, " bm_txq: 0x%x\n", pdev->ctrl.grp[gi].bm_txq); + for (qi = 0; qi < pdev->grp_queues; qi++) { + if (1 << qi & pdev->ctrl.grp[gi].bm_txq) { + struct pdma_tx_queue *txq = NULL; + struct intr_handle *ih = NULL; + pdev->ops->dev_pq_to_lq(pdev, qi + gi * pdev->grp_queues, &queue, &dir); + seq_printf(m, " qi %d:\n", qi); + seq_printf(m, " queue: %d\n", queue); + seq_printf(m, " dir: %d\n", dir); + txq = (struct pdma_tx_queue *)pdev->ctrl.tx_queue[queue]; + hw_grp = txq->chan_id / adev->nof_chans; + hw_que = txq->chan_id % adev->nof_chans; + seq_printf(m, " chan_id: %d\n", txq->chan_id); + seq_printf(m, " hw_grp: %d\n", hw_grp); + seq_printf(m, " hw_que: %d\n", hw_que); + seq_printf(m, " irq_mask: 0x%x\n", phw->dev->ctrl.grp[hw_grp].irq_mask); + ih = &pdev->ctrl.grp[gi].intr_hdl[qi]; + seq_printf(m, " intr_hdl: group %d chan %d queue %d dir %d budget %d inum %d\n", + ih->group, ih->chan, ih->queue, ih->dir, ih->budget, ih->inum); + seq_printf(m, " intr_flags 0x%x extra_poll %s\n", + ih->intr_flags, ih->extra_poll ? "T":"F"); + } + } + } + seq_printf(m, "------------ phw -------------\n"); + seq_printf(m, "dev->mode: %d\n", phw->dev->mode); + } + if (!ai) { + seq_printf(m, "%s\n", "No active device"); + } else { + seq_printf(m, "------------------------\n"); + seq_printf(m, "Total %d devices\n", ai); + } + return 0; +} + +static int +_adapter_info_open( + struct inode *inode, + struct file *file) +{ + return single_open(file, _adapter_info_show, NULL); +} + +static int +_adapter_info_release( + struct inode *inode, + struct file *file) +{ + return single_release(inode, file); +} + +struct proc_ops ngknet_adapter_info_fops = { + PROC_OWNER(THIS_MODULE) + .proc_open = _adapter_info_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = _adapter_info_release, +}; + +/*! + * Dump packet content for debug + */ +static void +_adapter_pkt_dump( + uint8_t *data, + int len) +{ + char str[128]; + int i; + + len = len > 256 ? 256 : len; + + for (i = 0; i < len; i++) { + if ((i & 0x1f) == 0) { + sprintf(str, "%04x: ", i); + } + sprintf(&str[strlen(str)], "%02x", data[i]); + if ((i & 0x1f) == 0x1f) { + sprintf(&str[strlen(str)], "\n"); + printk(str); + continue; + } + if ((i & 0x3) == 0x3) { + sprintf(&str[strlen(str)], " "); + } + } + if ((i & 0x1f) != 0) { + sprintf(&str[strlen(str)], "\n"); + printk(str); + } + printk("\n"); +} + +static inline void +_adapter_pkt_rx_mark_skb_vlan_tagged( + struct sk_buff *skb, + uint16_t tpid, + uint16_t tci, + int rcpu_encap) +{ + if (rcpu_encap) { + kal_vlan_hwaccel_put_tag(skb, ETH_P_8021Q, tci); + } else { + if (tpid == ETH_P_8021AD) { + kal_vlan_hwaccel_put_tag(skb, ETH_P_8021AD, tci); + } else { + kal_vlan_hwaccel_put_tag(skb, ETH_P_8021Q, tci); + } + } +} + +static void +_adapter_pkt_recv(struct net_device *ndev, struct sk_buff *skb) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + int kdev = dev->dev_info.dev_no; + struct adapter_dev *adev = &adapter_devices[kdev]; + ngknet_netif_t *netif = &priv->netif; + struct pkt_buf *pkb = (struct pkt_buf *)skb->data; + struct pkt_hdr *pkh = &pkb->pkh; + int pkt_len = PKT_HDR_SIZE + pkh->meta_len + pkh->data_len; + /* + * By default, NGKNET does not support marking the vlan tag + */ + /* + uint8_t *pkt = &skb->data[PKT_HDR_SIZE + pkh->meta_len]; + */ + + DBG_VERB(("_adapter_pkt_recv: skb->len = %d, pkt_len = %d\n", skb->len, pkt_len)); + /* Indicate the packet is parsed by adapter_rx_parser(). */ + if ((skb->len - pkt_len) == NGKNET_SCRATCH_DATA_BYTES) { + /* Remove the scratch data which was put to the end of packet */ + skb_trim(skb, pkt_len); + /* To API rx netif, the meta_len should be zero. */ + if (netif->id == adev->def_netif) { + pkh->data_len += pkh->meta_len; + pkh->meta_len = 0; + } + } + if ((debug & DBG_LVL_PKT)) { + _adapter_pkt_dump(skb->data, skb->len); + } + /* + * Mark packet as VLAN-tagged, otherwise newer + * kernels will strip the tag. + */ + /* + if (!(pkb->pkh.attrs & PDMA_RX_STRIP_TAG)) { + uint16_t vlan_proto = PKT_U16_GET(pkt, 12); + uint16_t tci = PKT_U16_GET(pkt, 14); + int renc = (netif->flags & NGKNET_NETIF_F_RCPU_ENCAP) ? 1 : 0; + DBG_VERB(("_adapter_pkt_recv: vlan_proto = 0x%04x, tci = %d, renc = %s\n", vlan_proto, tci, renc ? "true":"false")); + + _adapter_pkt_rx_mark_skb_vlan_tagged(skb, vlan_proto, tci, renc); + } + */ + /* See: ngknet_pkt_recv() */ + if (adev->pkt_recv) { + adev->pkt_recv(ndev, skb); + } + DBG_VERB(("\n--> Sent to netif(%d)...\n", netif->id)); + return; +} + +static int +_adapter_dev_netif_cb( + ngknet_dev_info_t *dinfo, + ngknet_netif_t *netif) +{ + struct adapter_dev *adev = NULL; + struct net_device *ndev = NULL; + struct ngknet_private *priv = NULL; + struct ngknet_dev *dev = NULL; + int kdev; + + if (!dinfo || !netif) { + return -1; + } + kdev = dinfo->dev_no; + adev = &adapter_devices[kdev]; + DBG_VERB(("_adapter_dev_netif_cb: Kdev%d, Id=%d.\n", kdev, netif->id)); + if (ADAPTER_IS_ACTIVED(adev)) { + dev = adev->dev; + ndev = dev->vdev[netif->id]; + priv = netdev_priv(ndev); + priv->pkt_recv = _adapter_pkt_recv; + DBG_VERB(("_adapter_dev_netif_cb: Pass.\n")); + return 0; + } + return -1; +} + +static void +_adapter_dev_isr( + void *isr_data) +{ + if (isr_data) + { + struct adapter_dev *adev = (struct adapter_dev *)isr_data; + if (ADAPTER_IS_ACTIVED(adev)) { + if (adev->isr_func) { + int rv; + rv = adev->isr_func(adev->isr_data); + adev->isr_received++; + if (rv == IRQ_HANDLED) { + adev->isr_handled++; + } + } + } + } +} + +static int +_adapter_dev_intr_connect( + int kdev, + uint32_t irq_num, + isr_func_f isr_func, + void *isr_data) +{ + struct adapter_dev *adev = &adapter_devices[kdev]; + if (ADAPTER_IS_ACTIVED(adev)) { + adev->irq_num = irq_num; + adev->isr_func = isr_func; + adev->isr_data = isr_data; + /* Register interrupt handler */ + kernel_bde->interrupt_connect(kdev | LKBDE_ISR2_DEV, _adapter_dev_isr, adev); + adev->isr_connected++; + return 0; + } + return -1; +} + +static int +_adapter_dev_intr_disconnect( + int kdev, + unsigned int irq_num) +{ + struct adapter_dev *adev = &adapter_devices[kdev]; + if (ADAPTER_IS_ACTIVED(adev)) { + kernel_bde->interrupt_disconnect(kdev | LKBDE_ISR2_DEV); + adev->isr_connected--; + adev->irq_num = 0; + adev->isr_func = NULL; + adev->isr_data = NULL; + return 0; + } + return -1; +} + + +static int +_adapter_dev_init( + int kdev) +{ + struct ngknet_dev *dev = &ngknet_devices[kdev]; + struct pdma_dev *pdev = &dev->pdma_dev; + struct net_device *ndev = dev->net_dev; + struct ngknet_private *priv = netdev_priv(ndev); + if (pdev->attached) { + struct dev_ctrl *ctrl = &pdev->ctrl; + struct pdma_hw *hw = (struct pdma_hw *)ctrl->hw; + struct adapter_dev *adev = &adapter_devices[kdev]; + sal_memset(adev, 0, sizeof(*adev)); + adev->pdma_dev = pdev; + adev->pdma_hw = hw; + adev->dev = dev; + if (strcmp(hw->info.name, CMICR_DEV_NAME) == 0) { + adev->cmic_type = ADAPTER_CMIC_T_CMICR; + adev->nof_chans = 16; /* CMICR_PDMA_CMC_CHAN */ + adev->irq_fmask = CMICR_TXRX_IRQ_MASK; + adev->irq_mask_reg = PAXB_0_INTC_SET_INTR_ENABLE_REG5r; + adev->iio_base = adev->irq_mask_reg & ~0xfff; + } else if (strcmp(hw->info.name, CMICX_DEV_NAME) == 0) { + adev->cmic_type = ADAPTER_CMIC_T_CMICX; + adev->nof_chans = 8; /* CMICX_PDMA_CMC_CHAN */ + adev->irq_fmask = CMICX_TXRX_IRQ_MASK; + adev->irq_mask_reg = CMICX_IRQ_ENABr; + adev->iio_base = adev->irq_mask_reg & ~0xfff; + } else if (strcmp(hw->info.name, CMICD_DEV_NAME) == 0) { + adev->cmic_type = ADAPTER_CMIC_T_CMICD; + return -1; + } else { + return -1; + } + adev->def_netif = 1; + if (adev->pkt_recv == NULL) { + adev->pkt_recv = priv->pkt_recv; + } + adev->flags |= ADAPTER_ACTIVE; + + /* Re-attach the hooks */ + do { + int i; + for (i = 1; i < NUM_VDEV_MAX + 1; i++) { + ndev = dev->vdev[i]; + if (ndev) { + priv = netdev_priv(ndev); + if (priv->pkt_recv && priv->pkt_recv != _adapter_pkt_recv) { + priv->pkt_recv = _adapter_pkt_recv; + } + } + } + if (pdev->pkt_xmit) { + adev->pkt_xmit = pdev->pkt_xmit; + pdev->pkt_xmit = ngknet_adapter_frame_xmit; + } + } while(0); + return 0; + } + return -1; +} + +static int +_adapter_dev_cleanup( + int kdev) +{ + struct adapter_dev *adev = &adapter_devices[kdev]; + if (ADAPTER_IS_ACTIVED(adev)) { + sal_memset(adev, 0, sizeof(*adev)); + return 0; + } + return -1; +} + +static int +_adapter_init(void) +{ + /* Connect to the kernel bde */ + if ((linux_bde_create(NULL, &kernel_bde) < 0) || kernel_bde == NULL) { + return -1; + } + /* + * Register a callback function to override priv->pkt_recv(), + * while create a new netif. + */ + ngknet_netif_create_cb_register(_adapter_dev_netif_cb); + return 0; +} + +int +ngknet_adapter_frame_recv( + struct pdma_dev *pdev, + int queue, + void *buf) +{ + struct ngknet_dev *dev = (struct ngknet_dev *)pdev->priv; + struct sk_buff *skb = (struct sk_buff *)buf; + struct pkt_buf *pkb = (struct pkt_buf *)skb->data; + struct pkt_hdr *pkh = &pkb->pkh; + int kdev = dev->dev_info.dev_no; + struct adapter_dev *adev = &adapter_devices[kdev]; + int rv = -1, chan_id; + DBG_VERB(("\n<-- Injected from CNET...\n")); + DBG_VERB(("Adapter Rx packet (%d bytes) from kdev %d queue %d.\n", skb->len, kdev, queue)); + if ((debug & DBG_LVL_PKT)) { + _adapter_pkt_dump(skb->data, skb->len); + } + if (ADAPTER_IS_ACTIVED(adev)) { + rv = bcmcnet_pdma_dev_queue_to_chan(&dev->pdma_dev, pkh->queue_id, + PDMA_Q_RX, &chan_id); + if (SHR_FAILURE(rv)) { + return rv; + } + if (!(adev->rsi.enet_channels & (0x1 << chan_id))) { + if (!(adev->rsi.flags & NGKNET_F_RX_PKT_UNPARSED)) { + /* parse the system header. */ + rv = ngknet_rx_parser(adev, skb); + if (SHR_FAILURE(rv)) { + return rv; + } + } + } + } + + DBG_VERB(("Adapter Rx packet got (%d bytes).\n", skb->len)); + if ((debug & DBG_LVL_PKT)) { + _adapter_pkt_dump(skb->data, PKT_HDR_SIZE); + _adapter_pkt_dump(skb->data + PKT_HDR_SIZE, pkh->meta_len); + _adapter_pkt_dump(skb->data + PKT_HDR_SIZE + pkh->meta_len, pkh->data_len); + _adapter_pkt_dump(skb->data + PKT_HDR_SIZE + pkh->meta_len + pkh->data_len, skb->len - PKT_HDR_SIZE - pkh->meta_len - pkh->data_len); + } + return rv; +} + +int +ngknet_adapter_frame_xmit( + struct pdma_dev *pdev, + int queue, + void *buf) +{ + struct ngknet_dev *dev = (struct ngknet_dev *)pdev->priv; + struct sk_buff *skb = (struct sk_buff *)buf; + struct pkt_buf *pkb = (struct pkt_buf *)skb->data; + struct pkt_hdr *pkh = &pkb->pkh; + int kdev = dev->dev_info.dev_no; + struct adapter_dev *adev = &adapter_devices[kdev]; + int rv = 0; + DBG_VERB(("\n--> Send to CNET...\n")); + DBG_VERB(("Adapter Tx packet (%d bytes) to kdev %d queue %d.\n", skb->len, kdev, queue)); + if ((debug & DBG_LVL_PKT)) { + _adapter_pkt_dump(skb->data, PKT_HDR_SIZE); + _adapter_pkt_dump(skb->data + PKT_HDR_SIZE, pkh->meta_len); + _adapter_pkt_dump(skb->data + PKT_HDR_SIZE + pkh->meta_len, pkh->data_len); + } + if (adev->pkt_xmit) { + rv = adev->pkt_xmit(pdev, queue, buf); + } + return rv; +} + +bool +ngknet_adapter_filter_scratch_data_match( + int kdev, + int chan_id, + struct sk_buff *skb, + ngknet_filter_t *filt) +{ + struct adapter_dev * adev = &adapter_devices[kdev]; + if (ADAPTER_IS_ACTIVED(adev)) { + /* + * return true to skip the scratch data match. + */ + if (filt->id != adev->scratch[filt->id].filter_id) { + return true; + } + return ngknet_rx_parser_scratch_data_match(adev, skb, filt); + } + return false; +} + +int +ngknet_adapter_msg( + struct ngknet_dev *dev, + int kdev, + int cmd, + int target, + char *data, + int len) +{ + struct adapter_dev *adev = &adapter_devices[kdev]; + unsigned long flags; + if (ADAPTER_IS_ACTIVED(adev)) { + switch(cmd) { + case NGKNET_MSG_CMD_RX_START_INFO: + if (len != sizeof(adev->rsi)) { + printk("Invalid len (%d, expect %lu)\n", len, sizeof(adev->rsi)); + return -1; + } + spin_lock_irqsave(&dev->lock, flags); + sal_memcpy(&adev->rsi, data, len); + adev->rsi.flags |= NGKNET_F_RX_START_INFO_DELIVERED; + spin_unlock_irqrestore(&dev->lock, flags); + break; + case NGKNET_MSG_CMD_DBG_LVL_INFO: + if (len != sizeof(debug)) { + printk("Invalid len (%d, expect %lu)\n", len, sizeof(debug)); + return -1; + } + debug = *(int *)data; + ngknet_rx_parser_debug_set(debug); + break; + case NGKNET_MSG_CMD_SCRATCH_INFO: + if (target < 0 || target >= NUM_FILTER_MAX) { + printk("Invalid target (%d)\n", target); + return -1; + } + if (len != sizeof(ngknet_msg_scratch_data_t)) { + printk("Invalid len (%d, expect %lu)\n", len, sizeof(adev->scratch[target])); + return -1; + } + sal_memcpy(&adev->scratch[target], data, len); + break; + case NGKNET_MSG_CMD_SCRATCH_INFO_FETCH: + if (target < 0 || target >= NUM_FILTER_MAX) { + printk("Invalid target (%d)\n", target); + return -1; + } + if (len != sizeof(ngknet_msg_scratch_data_t)) { + printk("Invalid len (%d, expect %lu)\n", len, sizeof(adev->scratch[target])); + return -1; + } + sal_memcpy(data, &adev->scratch[target], len); + break; + default: + break; + } + + return 0; + } + printk("Adapter kdev(%d) is not active for now.\n", kdev); + return -1; +} + +int +ngknet_adapter_device_is_sand( + int kdev) +{ + struct adapter_dev *adev = &adapter_devices[kdev]; + if (ADAPTER_IS_ACTIVED(adev)) { + struct ngknet_dev *dev = adev->dev; + uint32 dev_family = dev->dev_info.dev_id & 0xf000; + + /** + * 0xb000 : 56xxx (XGS) + * 0xf000 : 78xxx (XGS) + * 0x8000 : 88xxx (DNX) + * 0x9000 : 99xxx (DNX) + */ + if (dev_family == 0x8000 || dev_family == 0x9000) { + return 1; + } + } + return 0; +} + +struct device * +ngbde_kapi_dma_dev_get( + int kdev) +{ + void *sd = NULL; +#ifdef LINUX_BDE_DMA_DEVICE_SUPPORT + sd = lkbde_get_dma_dev(kdev); +#endif + if (!sd) { + return NULL; + } + return (struct device *)sd; +} + +void * +ngbde_kapi_dma_bus_to_virt( + int kdev, + dma_addr_t baddr) +{ +#if ADAPTER_DMA_ADDR_DEBUG + struct adapter_dev *adev = &adapter_devices[kdev]; +#endif /* ADAPTER_DMA_ADDR_DEBUG */ + sal_paddr_t paddr; + void *vaddr = NULL; + if (kernel_bde == NULL) { + return NULL; + } + paddr = (sal_paddr_t)baddr; + vaddr = kernel_bde->p2l(kdev, paddr); +#if ADAPTER_DMA_ADDR_DEBUG + if (ADAPTER_IS_ACTIVED(adev)) { + adev->p2l_baddr = baddr; + adev->p2l_paddr = paddr; + adev->p2l_vaddr = vaddr; + adev->p2l_cnt++; + } +#endif /* ADAPTER_DMA_ADDR_DEBUG */ + return vaddr; +} + +dma_addr_t +ngbde_kapi_dma_virt_to_bus( + int kdev, + void *vaddr) +{ +#if ADAPTER_DMA_ADDR_DEBUG + struct adapter_dev *adev = &adapter_devices[kdev]; +#endif /* ADAPTER_DMA_ADDR_DEBUG */ + dma_addr_t baddr; + sal_paddr_t paddr; + if (kernel_bde == NULL) { + return (dma_addr_t)NULL; + } + paddr = kernel_bde->l2p(kdev, vaddr); + baddr = (dma_addr_t)paddr; +#if ADAPTER_DMA_ADDR_DEBUG + if (ADAPTER_IS_ACTIVED(adev)) { + adev->l2p_baddr = baddr; + adev->l2p_paddr = paddr; + adev->l2p_vaddr = vaddr; + adev->l2p_cnt++; + } +#endif /* ADAPTER_DMA_ADDR_DEBUG */ + return baddr; +} + +void +ngbde_kapi_pio_write32( + int kdev, + uint32_t offs, + uint32_t val) +{ + if (kernel_bde == NULL) { + return; + } + kernel_bde->write(kdev, offs, val); + return; +} + +uint32_t +ngbde_kapi_pio_read32( + int kdev, + uint32_t offs) +{ + if (kernel_bde == NULL) { + return (uint32_t)-1; + } + return kernel_bde->read(kdev, offs); +} + +void * +ngbde_kapi_pio_membase( + int kdev) +{ + if (kernel_bde == NULL) { + if (_adapter_init() < 0) { + return NULL; + } + } + return lkbde_get_dev_virt(kdev); +} + +void +ngbde_kapi_iio_write32( + int kdev, + uint32_t offs, + uint32_t val) +{ + uint32_t iio_base = 0; + struct adapter_dev *adev = &adapter_devices[kdev]; + if (kernel_bde == NULL) { + return; + } + if (ADAPTER_IS_ACTIVED(adev)) { + adev->iio_recorder[adev->iio_recorder_cnt % ADAPTER_IIO_RECORDER_SIZE].op = ADAPTER_IIO_OP_WRITE; + adev->iio_recorder[adev->iio_recorder_cnt % ADAPTER_IIO_RECORDER_SIZE].offs = offs; + adev->iio_recorder[adev->iio_recorder_cnt % ADAPTER_IIO_RECORDER_SIZE].val = val; + adev->iio_recorder_cnt++; + iio_base = adev->iio_base; + /** + * See description of lkbde_irq_mask_set() function. + * for synchronizing hardware access to the IRQ mask register. + */ + lkbde_irq_mask_set(kdev | LKBDE_ISR2_DEV | LKBDE_IPROC_REG, + iio_base + offs, val, adev->irq_fmask); + return; + } + kernel_bde->iproc_write(kdev, iio_base + offs, val); + return; +} + +uint32_t +ngbde_kapi_iio_read32( + int kdev, + uint32_t offs) +{ + uint32_t iio_base = 0; + uint32_t val; + struct adapter_dev *adev = &adapter_devices[kdev]; + if (kernel_bde == NULL) { + return (uint32_t)-1; + } + if (ADAPTER_IS_ACTIVED(adev)) { + iio_base = adev->iio_base; + } + val = kernel_bde->iproc_read(kdev, iio_base + offs); + if (ADAPTER_IS_ACTIVED(adev)) { + adev->iio_recorder[adev->iio_recorder_cnt % ADAPTER_IIO_RECORDER_SIZE].op = ADAPTER_IIO_OP_READ; + adev->iio_recorder[adev->iio_recorder_cnt % ADAPTER_IIO_RECORDER_SIZE].offs = offs; + adev->iio_recorder[adev->iio_recorder_cnt % ADAPTER_IIO_RECORDER_SIZE].val = val; + adev->iio_recorder_cnt++; + } + return val; +} + +int +ngbde_kapi_intr_connect( + int kdev, + unsigned int irq_num, + int (*isr_func)(void *), + void *isr_data) +{ + if (kernel_bde == NULL) { + return -1; + } + if (_adapter_dev_init(kdev) < 0) { + return -1; + } + _adapter_dev_intr_connect(kdev, irq_num, isr_func, isr_data); + return 0; +} + +int +ngbde_kapi_intr_disconnect( + int kdev, + unsigned int irq_num) +{ + if (kernel_bde == NULL) { + return -1; + } + _adapter_dev_intr_disconnect(kdev, irq_num); + _adapter_dev_cleanup(kdev); + return 0; +} + +int +ngbde_kapi_intr_mask_write( + int kdev, + unsigned int irq_num, + uint32_t status_reg, + uint32_t mask_val) +{ + struct adapter_dev *adev = &adapter_devices[kdev]; + if (ADAPTER_IS_ACTIVED(adev)) { + adev->irq_mask = mask_val; + adev->irq_status_reg = status_reg; + adev->irq_mask_cnt++; + adev->imask_recorder[adev->imask_recorder_cnt % ADAPTER_IMASK_RECORDER_SIZE].inum = irq_num; + adev->imask_recorder[adev->imask_recorder_cnt % ADAPTER_IMASK_RECORDER_SIZE].mask_val = mask_val; + adev->imask_recorder_cnt++; + return lkbde_irq_mask_set(kdev | LKBDE_ISR2_DEV | LKBDE_IPROC_REG, + adev->irq_mask_reg, adev->irq_mask, adev->irq_fmask); + } + return -1; +} + +int +ngbde_kapi_knet_connect( + int kdev, + knet_func_f knet_func, + void *knet_data) +{ + return 0; +} + +int +ngbde_kapi_knet_disconnect( + int kdev) +{ + return 0; +} diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_adapter.h b/systems/linux/kernel/modules/bcm-ngknet/ngknet_adapter.h new file mode 100644 index 0000000..e6b319c --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_adapter.h @@ -0,0 +1,305 @@ +/*! \file ngknet_adapter.h + * + * Definitions and APIs declaration for Adapter. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_ADAPTER_H +#define NGKNET_ADAPTER_H + +#include + +#include +#include + +#include +#include +#include + +#include "ngknet_main.h" + +typedef int (*isr_func_f)(void *); +typedef enum adapter_dev_cmic_type_e { + ADAPTER_CMIC_T_NONE, + ADAPTER_CMIC_T_CMICD, + ADAPTER_CMIC_T_CMICX, + ADAPTER_CMIC_T_CMICR, + ADAPTER_CMIC_T_COUNT +} adapter_dev_cmic_type_t; + +#define ADAPTER_CMIC_TYPE_STR { \ + "none", \ + "cmicd", \ + "cmicx", \ + "cmicr", \ +} + +/* + * TO debug address mapping. + */ +#ifndef ADAPTER_DMA_ADDR_DEBUG +#define ADAPTER_DMA_ADDR_DEBUG 0 +#endif + +#define ADAPTER_IIO_OP_READ 1 +#define ADAPTER_IIO_OP_WRITE 2 + +#define ADAPTER_IIO_RECORDER_SIZE (20) +#define ADAPTER_IMASK_RECORDER_SIZE (20) + + +struct adapter_iio_recorder { + uint32_t op; + uint32_t offs; + uint32_t val; +}; + +struct adapter_imask_recorder { + int inum; + uint32_t mask_val; +}; + +/*! + * Adapter description + */ +struct adapter_dev { + /*! Flags */ + int flags; + /*! Adapter is active */ +#define ADAPTER_ACTIVE (1 << 0) + + /*! PDMA device */ + struct pdma_dev *pdma_dev; + + /*! PDMA hardware */ + struct pdma_hw *pdma_hw; + + /*! PDMA adapter Tx interface */ + pdma_tx_f pkt_xmit; + + /*! NGKNET devices */ + struct ngknet_dev *dev; + + /*! CMIC type, See adapter_dev_cmic_type_t */ + adapter_dev_cmic_type_t cmic_type; + + /*! Number of channels */ + uint32_t nof_chans; + + /*! Interrupt mask */ + uint32_t irq_mask; + + /*! Interrupt mask register */ + uint32_t irq_mask_reg; + + /*! Interrupt filter mask */ + uint32_t irq_fmask; + + /*! Interrupt status register */ + uint32_t irq_status_reg; + + /*! Interrupt mask counter */ + uint32_t irq_mask_cnt; + + /*! Interrupt counter */ + uint32_t irq_num; + + /*! Interrupt SubRoutine counter */ + uint32_t isr_connected; + + /*! Interrupt SubRoutine */ + isr_func_f isr_func; + + /*! Interrupt SubRoutine data */ + void * isr_data; + + /*! Interrupt SubRoutine counter */ + uint32_t isr_received; + + /*! Interrupt handled counter */ + uint32_t isr_handled; +#if ADAPTER_DMA_ADDR_DEBUG + /*! p2l counter */ + uint32_t p2l_cnt; + + /*! last bus address */ + dma_addr_t p2l_baddr; + + /*! last phy address */ + sal_paddr_t p2l_paddr; + + /*! last virt address */ + void * p2l_vaddr; + + /*! l2p counter */ + uint32_t l2p_cnt; + + /*! last bus address */ + dma_addr_t l2p_baddr; + + /*! last phy address */ + sal_paddr_t l2p_paddr; + + /*! last virt address */ + void * l2p_vaddr; +#endif /* ADAPTER_DMA_ADDR_DEBUG */ + /*! iio_base */ + uint32_t iio_base; + + /*! iio_recorder */ + struct adapter_iio_recorder iio_recorder[ADAPTER_IIO_RECORDER_SIZE]; + + /*! iio_recorder counter */ + int iio_recorder_cnt; + + /*! imask_recorder */ + struct adapter_imask_recorder imask_recorder[ADAPTER_IMASK_RECORDER_SIZE]; + + /*! imask_recorder counter */ + int imask_recorder_cnt; + + /* Default netif for API tx/rx */ + int def_netif; + + /*! Record the packet receiver that ngknet_private struct used. */ + ngknet_pkt_recv_f pkt_recv; + + /*! Rx start info */ + ngknet_msg_rx_start_info_t rsi; + + /*! Rx scratch data for each filter */ + ngknet_msg_scratch_data_t scratch[NUM_FILTER_MAX]; + +}; + +#define ADAPTER_IS_ACTIVED(_adev) ((_adev)->flags & ADAPTER_ACTIVE) + +#define ADAPTER_IS_CMICR(_adev) ((_adev)->cmic_type == ADAPTER_CMIC_T_CMICR) +#define ADAPTER_IS_CMICX(_adev) ((_adev)->cmic_type == ADAPTER_CMIC_T_CMICX) +#define ADAPTER_IS_AI(_adev) ((_adev)->rsi.flags & NGKNET_F_RX_PKT_AI_FORMAT) + +#define device_is_sand(_kdev) (ngknet_adapter_device_is_sand(_kdev)) + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(6,5,0) +#define netdev_get_by_name(net, dev, tracker, gfp) \ + dev_get_by_name(net, dev) +#endif /* KERNEL_VERSION(6,5,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(6,0,0) +#define netdev_put(dev, tracker) \ + dev_put(dev) +#endif /* KERNEL_VERSION(6,0,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) +#define dev_net_set(dev, net) +#endif + + +extern struct proc_ops ngknet_adapter_info_fops; + +/*! + * \brief Adapter frame receiver. + * + * \param [in] dev Pkt dma device. + * \param [in] queue Rx logical queue. + * \param [in] buf SKB Data buffer. + * + * \retval SHR_E_NONE No errors. + */ +extern int ngknet_adapter_frame_recv( + struct pdma_dev *pdev, + int queue, + void *buf); + +/*! + * \brief Adapter frame transmitter. + * + * \param [in] dev Pkt dma device. + * \param [in] queue Rx logical queue. + * \param [in] buf SKB Data buffer. + * + * \retval SHR_E_NONE No errors. + */ +extern int ngknet_adapter_frame_xmit( + struct pdma_dev *pdev, + int queue, + void *buf); + +/*! + * \brief match the scratch data. + * + * \param [in] kdev Kernel device number. + * \param [in] chan_id Dma channel id. + * \param [in] skb SKB Data buffer. + * \param [in] filt Packet filter. + * + * \retval SHR_E_NONE No errors. + */ +extern bool ngknet_adapter_filter_scratch_data_match( + int kdev, + int chan_id, + struct sk_buff *skb, + ngknet_filter_t *filt); + +/*! + * \brief Adapter messages. + * + * \param [in] dev NGKNET device structure point. + * \param [in] kdev NGKNET device unit number. + * \param [in] cmd Command. + * \param [in] target Target. + * \param [in] data Data buffer. + * \param [in] len Data length. + * + * \retval SHR_E_NONE No errors. + */ +extern int ngknet_adapter_msg( + struct ngknet_dev *dev, + int kdev, + int cmd, + int target, + char *data, + int len); + +/*! + * \brief device is sand/DNX. + * + * \param [in] kdev NGKNET device number. + * + * \retval 0-NOT, 1-YES. + */ +extern int ngknet_adapter_device_is_sand( + int kdev); + +#endif /* NGKNET_ADAPTER_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_buff.c b/systems/linux/kernel/modules/bcm-ngknet/ngknet_buff.c new file mode 100644 index 0000000..b342709 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_buff.c @@ -0,0 +1,364 @@ +/*! \file ngknet_buff.c + * + * Utility routines for NGKNET packet buffer management in Linux kernel mode. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include "ngknet_main.h" +#include "ngknet_buff.h" + +/*! + * Allocate coherent memory + */ +static void * +ngknet_ring_buf_alloc(struct pdma_dev *dev, uint32_t size, dma_addr_t *dma) +{ + struct ngknet_dev *kdev = (struct ngknet_dev *)dev->priv; + + return dma_alloc_coherent(kdev->dev, size, dma, GFP_KERNEL); +} + +/*! + * Free coherent memory + */ +static void +ngknet_ring_buf_free(struct pdma_dev *dev, uint32_t size, void *addr, dma_addr_t dma) +{ + struct ngknet_dev *kdev = (struct ngknet_dev *)dev->priv; + + dma_free_coherent(kdev->dev, size, addr, dma); +} + +/*! + * Allocate Rx buffer + */ +static int +ngknet_rx_buf_alloc(struct pdma_dev *dev, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf) +{ + struct ngknet_dev *kdev = (struct ngknet_dev *)dev->priv; + dma_addr_t dma; + struct page *page; + struct sk_buff *skb; + + if (rxq->buf_mode == PDMA_BUF_MODE_PAGE) { + page = kal_dev_alloc_pages(rxq->page_order); + if (unlikely(!page)) { + return SHR_E_MEMORY; + } + dma = kal_dma_map_page_attrs(kdev->dev, page, 0, PAGE_SIZE * (1 << rxq->page_order), DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING); + if (unlikely(dma_mapping_error(kdev->dev, dma))) { + __free_pages(page, rxq->page_order); + return SHR_E_MEMORY; + } + pbuf->dma = dma; + pbuf->page = page; + pbuf->page_offset = 0; + } else { + skb = netdev_alloc_skb(kdev->net_dev, PDMA_RXB_RESV + pbuf->adj + rxq->buf_size); + if (unlikely(!skb)) { + return SHR_E_MEMORY; + } + skb_reserve(skb, PDMA_RXB_ALIGN - (((unsigned long)skb->data) & (PDMA_RXB_ALIGN - 1))); + pbuf->skb = skb; + pbuf->pkb = (struct pkt_buf *)skb->data; + dma = dma_map_single(kdev->dev, &pbuf->pkb->data + pbuf->adj, rxq->buf_size, DMA_FROM_DEVICE); + if (unlikely(dma_mapping_error(kdev->dev, dma))) { + dev_kfree_skb_any(skb); + return SHR_E_MEMORY; + } + pbuf->dma = dma; + } + + return SHR_E_NONE; +} + +/*! + * Get Rx buffer DMA address + */ +static void +ngknet_rx_buf_dma(struct pdma_dev *dev, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf, dma_addr_t *addr) +{ + if (rxq->buf_mode == PDMA_BUF_MODE_PAGE) { + *addr = pbuf->dma + pbuf->page_offset + PDMA_RXB_RESV + pbuf->adj; + } else { + *addr = pbuf->dma; + } +} + +/*! + * Check Rx buffer + */ +static bool +ngknet_rx_buf_avail(struct pdma_dev *dev, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf) +{ + if (rxq->buf_mode == PDMA_BUF_MODE_PAGE) { + pbuf->skb = NULL; + } + + return (pbuf->dma != 0); +} + +/*! + * Get Rx buffer + */ +static struct pkt_hdr * +ngknet_rx_buf_get(struct pdma_dev *dev, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf, int len) +{ + struct ngknet_dev *kdev = (struct ngknet_dev *)dev->priv; + struct sk_buff *skb; + uint32_t pages_size; + + if (rxq->buf_mode == PDMA_BUF_MODE_PAGE) { + if (pbuf->skb) { + return &pbuf->pkb->pkh; + } + skb = kal_build_skb(page_address(pbuf->page) + pbuf->page_offset, + PDMA_RXB_SIZE(rxq->buf_size + pbuf->adj)); + if (unlikely(!skb)) { + return NULL; + } + skb_reserve(skb, PDMA_RXB_ALIGN); + pages_size = PAGE_SIZE * (1 << rxq->page_order); + dma_sync_single_range_for_cpu(kdev->dev, pbuf->dma, pbuf->page_offset, + pages_size >> 1, DMA_FROM_DEVICE); + pbuf->skb = skb; + pbuf->pkb = (struct pkt_buf *)skb->data; + + /* Try to reuse this page */ + if (unlikely(page_count(pbuf->page) != 1) || + kal_page_is_pfmemalloc(pbuf->page) || + page_to_nid(pbuf->page) != numa_mem_id()) { + kal_dma_unmap_page_attrs(kdev->dev, pbuf->dma, pages_size, DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING); + pbuf->dma = 0; + } else { + pbuf->page_offset ^= pages_size >> 1; + page_ref_inc(pbuf->page); + dma_sync_single_range_for_device(kdev->dev, pbuf->dma, pbuf->page_offset, + pages_size >> 1, DMA_FROM_DEVICE); + } + } else { + if (!pbuf->dma) { + return &pbuf->pkb->pkh; + } + skb = pbuf->skb; + dma_unmap_single(kdev->dev, pbuf->dma, rxq->buf_size, DMA_FROM_DEVICE); + pbuf->dma = 0; + } + + skb_put(skb, PKT_HDR_SIZE + pbuf->adj + len); + + return &pbuf->pkb->pkh; +} + +/*! + * Put Rx buffer + */ +static int +ngknet_rx_buf_put(struct pdma_dev *dev, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf, int len) +{ + struct ngknet_dev *kdev = (struct ngknet_dev *)dev->priv; + dma_addr_t dma; + struct sk_buff *skb; + + if (rxq->buf_mode == PDMA_BUF_MODE_PAGE) { + dev_kfree_skb_any(pbuf->skb); + } else { + skb = pbuf->skb; + if (pbuf->pkb != (struct pkt_buf *)skb->data) { + dev_kfree_skb_any(skb); + pbuf->dma = 0; + return SHR_E_NONE; + } + dma = dma_map_single(kdev->dev, &pbuf->pkb->data + pbuf->adj, + rxq->buf_size, DMA_FROM_DEVICE); + if (unlikely(dma_mapping_error(kdev->dev, dma))) { + dev_kfree_skb_any(skb); + pbuf->dma = 0; + return SHR_E_MEMORY; + } + pbuf->dma = dma; + skb_trim(skb, 0); + } + + return SHR_E_NONE; +} + +/*! + * Free Rx buffer + */ +static void +ngknet_rx_buf_free(struct pdma_dev *dev, struct pdma_rx_queue *rxq, + struct pdma_rx_buf *pbuf) +{ + struct ngknet_dev *kdev = (struct ngknet_dev *)dev->priv; + uint32_t pages_size; + + if (rxq->buf_mode == PDMA_BUF_MODE_PAGE) { + if (!pbuf->page) { + return; + } + pages_size = PAGE_SIZE * (1 << rxq->page_order); + kal_dma_unmap_page_attrs(kdev->dev, pbuf->dma, pages_size, DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING); + __free_pages(pbuf->page, rxq->page_order); + } else { + if (!pbuf->skb) { + return; + } + dma_unmap_single(kdev->dev, pbuf->dma, rxq->buf_size, DMA_FROM_DEVICE); + dev_kfree_skb_any(pbuf->skb); + } + + pbuf->dma = 0; + pbuf->page = NULL; + pbuf->page_offset = 0; + pbuf->skb = NULL; + pbuf->pkb = NULL; + pbuf->adj = 0; +} + +/*! + * Get Rx buffer mode + */ +static enum buf_mode +ngknet_rx_buf_mode(struct pdma_dev *dev, struct pdma_rx_queue *rxq) +{ + uint32_t len, order; + + if (ngknet_page_buffer_mode_get() == 0) { + return PDMA_BUF_MODE_SKB; + } + + len = dev->rx_ph_size ? rxq->buf_size : rxq->buf_size + PDMA_RXB_META; + for (order = 0; order < 32; order++) { + if (PDMA_RXB_SIZE(len) * 2 <= PAGE_SIZE * (1 << order)) { + rxq->page_order = order; + break; + } + } + + return PDMA_BUF_MODE_PAGE; +} + +/*! + * Get Tx buffer + */ +static struct pkt_hdr * +ngknet_tx_buf_get(struct pdma_dev *dev, struct pdma_tx_queue *txq, + struct pdma_tx_buf *pbuf, void *buf) +{ + struct ngknet_dev *kdev = (struct ngknet_dev *)dev->priv; + struct sk_buff *skb = (struct sk_buff *)buf; + struct pkt_buf *pkb = (struct pkt_buf *)skb->data; + dma_addr_t dma; + + pbuf->len = pkb->pkh.data_len + (pbuf->adj ? pkb->pkh.meta_len : 0); + dma = dma_map_single(kdev->dev, &pkb->data + (pbuf->adj ? 0 : pkb->pkh.meta_len), + pbuf->len, DMA_TO_DEVICE); + if (unlikely(dma_mapping_error(kdev->dev, dma))) { + dev_kfree_skb_any(skb); + return NULL; + } + pbuf->dma = dma; + pbuf->skb = skb; + pbuf->pkb = pkb; + + return &pkb->pkh; +} + +/*! + * Get Tx buffer DMA address + */ +static void +ngknet_tx_buf_dma(struct pdma_dev *dev, struct pdma_tx_queue *txq, + struct pdma_tx_buf *pbuf, dma_addr_t *addr) +{ + *addr = pbuf->dma; +} + +/*! + * Free Tx buffer + */ +static void +ngknet_tx_buf_free(struct pdma_dev *dev, struct pdma_tx_queue *txq, + struct pdma_tx_buf *pbuf) +{ + struct ngknet_dev *kdev = (struct ngknet_dev *)dev->priv; + + if (!pbuf->skb) { + return; + } + + dma_unmap_single(kdev->dev, pbuf->dma, pbuf->len, DMA_TO_DEVICE); + dev_kfree_skb_any(pbuf->skb); + + pbuf->dma = 0; + pbuf->len = 0; + pbuf->skb = NULL; + pbuf->pkb = NULL; + pbuf->adj = 0; +} + +static const struct pdma_buf_mngr buf_mngr = { + .ring_buf_alloc = ngknet_ring_buf_alloc, + .ring_buf_free = ngknet_ring_buf_free, + .rx_buf_alloc = ngknet_rx_buf_alloc, + .rx_buf_dma = ngknet_rx_buf_dma, + .rx_buf_avail = ngknet_rx_buf_avail, + .rx_buf_get = ngknet_rx_buf_get, + .rx_buf_put = ngknet_rx_buf_put, + .rx_buf_free = ngknet_rx_buf_free, + .rx_buf_mode = ngknet_rx_buf_mode, + .tx_buf_get = ngknet_tx_buf_get, + .tx_buf_dma = ngknet_tx_buf_dma, + .tx_buf_free = ngknet_tx_buf_free, +}; + +/*! + * Open a device + */ +void +bcmcnet_buf_mngr_init(struct pdma_dev *dev) +{ + dev->ctrl.buf_mngr = (struct pdma_buf_mngr *)&buf_mngr; +} + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_buff.h b/systems/linux/kernel/modules/bcm-ngknet/ngknet_buff.h new file mode 100644 index 0000000..ea65e2c --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_buff.h @@ -0,0 +1,94 @@ +/*! \file ngknet_buff.h + * + * Generic data structure definitions for NGKNET packet buffer management. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_BUFF_H +#define NGKNET_BUFF_H + +/*! Rx buffer align size */ +#define PDMA_RXB_ALIGN 32 +/*! Rx buffer reserved size */ +#define PDMA_RXB_RESV (PDMA_RXB_ALIGN + PKT_HDR_SIZE) +/*! Rx SKB reserved size */ +#define PDMA_SKB_RESV (PDMA_RXB_RESV + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) +/*! Rx buffer size */ +#define PDMA_RXB_SIZE(len) (SKB_DATA_ALIGN(len) + PDMA_SKB_RESV) +/*! Rx reserved meta size */ +#define PDMA_RXB_META 64 + +/*! + * \brief Rx buffer. + */ +struct pdma_rx_buf { + /*! DMA address */ + dma_addr_t dma; + + /*! Buffer page */ + struct page *page; + + /*! Buffer page offset */ + unsigned int page_offset; + + /*! Rx SKB */ + struct sk_buff *skb; + + /*! Packet buffer point */ + struct pkt_buf *pkb; + + /*! Packet buffer adjustment */ + uint32_t adj; +}; + +/*! + * \brief Tx buffer. + */ +struct pdma_tx_buf { + /*! DMA address */ + dma_addr_t dma; + + /*! Tx buffer length */ + uint32_t len; + + /*! Tx SKB */ + struct sk_buff *skb; + + /*! Packet buffer point */ + struct pkt_buf *pkb; + + /*! Packet buffer adjustment */ + uint32_t adj; +}; + +#endif /* NGKNET_BUFF_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_callback.c b/systems/linux/kernel/modules/bcm-ngknet/ngknet_callback.c new file mode 100644 index 0000000..ac67cd2 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_callback.c @@ -0,0 +1,626 @@ +/*! \file ngknet_callback.c + * + * Utility routines for NGKNET callbacks. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include "ngknet_main.h" +#include "ngknet_callback.h" +#include "ngknet_extra.h" + +static struct ngknet_callback_ctrl callback_ctrl; + +void +ngknet_callback_init(struct ngknet_dev *devs) +{ + INIT_LIST_HEAD(&callback_ctrl.dev_init_cb_list); + INIT_LIST_HEAD(&callback_ctrl.netif_create_cb_list); + INIT_LIST_HEAD(&callback_ctrl.netif_destroy_cb_list); + INIT_LIST_HEAD(&callback_ctrl.filter_cb_list); + callback_ctrl.devs = devs; +} + +void +ngknet_callback_cleanup(void) +{ + dev_cb_t *dev_cb; + netif_cb_t *netif_cb; + filter_cb_t *filter_cb; + + while (!list_empty(&callback_ctrl.dev_init_cb_list)) { + dev_cb = list_entry(callback_ctrl.dev_init_cb_list.next, + dev_cb_t, list); + list_del(&dev_cb->list); + kfree(dev_cb); + } + while (!list_empty(&callback_ctrl.netif_create_cb_list)) { + netif_cb = list_entry(callback_ctrl.netif_create_cb_list.next, + netif_cb_t, list); + list_del(&netif_cb->list); + kfree(netif_cb); + } + while (!list_empty(&callback_ctrl.netif_destroy_cb_list)) { + netif_cb = list_entry(callback_ctrl.netif_destroy_cb_list.next, + netif_cb_t, list); + list_del(&netif_cb->list); + kfree(netif_cb); + } + while (!list_empty(&callback_ctrl.filter_cb_list)) { + filter_cb = list_entry(callback_ctrl.filter_cb_list.next, + filter_cb_t, list); + list_del(&filter_cb->list); + kfree(filter_cb); + } +} + +int +ngknet_callback_control_get(struct ngknet_callback_ctrl **cbc) +{ + *cbc = &callback_ctrl; + + return 0; +} + +/*! + * Call-back interfaces for other Linux kernel drivers. + */ + +int +ngknet_dev_init_cb_register(ngknet_dev_init_cb_f dev_init_cb) +{ + struct list_head *list; + dev_cb_t *dev_cb; + + if (dev_init_cb == NULL) { + return -1; + } + + list_for_each(list, &callback_ctrl.dev_init_cb_list) { + dev_cb = list_entry(list, dev_cb_t, list); + if (dev_cb->cb == dev_init_cb) { + return -1; + } + } + + dev_cb = kmalloc(sizeof(*dev_cb), GFP_KERNEL); + if (dev_cb == NULL) { + return -1; + } + dev_cb->cb = dev_init_cb; + list_add_tail(&dev_cb->list, &callback_ctrl.dev_init_cb_list); + + return 0; +} + +int +ngknet_dev_init_cb_unregister(ngknet_dev_init_cb_f dev_init_cb) +{ + struct list_head *list, *list_next; + dev_cb_t *dev_cb; + + if (dev_init_cb == NULL) { + return -1; + } + + list_for_each_safe(list, list_next, &callback_ctrl.dev_init_cb_list) { + dev_cb = list_entry(list, dev_cb_t, list); + if (dev_cb->cb == dev_init_cb) { + list_del(list); + kfree(dev_cb); + return 0; + } + } + + return -1; +} + +int +ngknet_rx_cb_register(ngknet_rx_cb_f rx_cb) +{ + if (callback_ctrl.rx_cb != NULL) { + return -1; + } + callback_ctrl.rx_cb = rx_cb; + + return 0; +} + +int +ngknet_rx_cb_unregister(ngknet_rx_cb_f rx_cb) +{ + if (rx_cb == NULL || callback_ctrl.rx_cb != rx_cb) { + return -1; + } + callback_ctrl.rx_cb = NULL; + + return 0; +} + +int +ngknet_tx_cb_register(ngknet_tx_cb_f tx_cb) +{ + if (callback_ctrl.tx_cb != NULL) { + return -1; + } + callback_ctrl.tx_cb = tx_cb; + + return 0; +} + +int +ngknet_tx_cb_unregister(ngknet_tx_cb_f tx_cb) +{ + if (tx_cb == NULL || callback_ctrl.tx_cb != tx_cb) { + return -1; + } + callback_ctrl.tx_cb = NULL; + + return 0; +} + +int +ngknet_netif_create_cb_register(ngknet_netif_cb_f netif_cb) +{ + struct list_head *list; + netif_cb_t *netif_create_cb; + + if (netif_cb == NULL) { + return -1; + } + list_for_each(list, &callback_ctrl.netif_create_cb_list) { + netif_create_cb = list_entry(list, netif_cb_t, list); + if (netif_create_cb->cb == netif_cb) { + return -1; + } + } + netif_create_cb = kmalloc(sizeof(*netif_create_cb), GFP_KERNEL); + if (netif_create_cb == NULL) { + return -1; + } + netif_create_cb->cb = netif_cb; + list_add_tail(&netif_create_cb->list, &callback_ctrl.netif_create_cb_list); + + return 0; +} + +int +ngknet_netif_create_cb_unregister(ngknet_netif_cb_f netif_cb) +{ + struct list_head *list, *list_next; + netif_cb_t *netif_create_cb; + int found = 0; + + if (netif_cb == NULL) { + return -1; + } + list_for_each_safe(list, list_next, &callback_ctrl.netif_create_cb_list) { + netif_create_cb = list_entry(list, netif_cb_t, list); + if (netif_create_cb->cb == netif_cb) { + found = 1; + list_del(list); + break; + } + } + if (!found) { + return -1; + } + kfree(netif_create_cb); + + return 0; +} + +int +ngknet_netif_destroy_cb_register(ngknet_netif_cb_f netif_cb) +{ + struct list_head *list; + netif_cb_t *netif_destroy_cb; + + if (netif_cb == NULL) { + return -1; + } + list_for_each(list, &callback_ctrl.netif_destroy_cb_list) { + netif_destroy_cb = list_entry(list, netif_cb_t, list); + if (netif_destroy_cb->cb == netif_cb) { + return -1; + } + } + netif_destroy_cb = kmalloc(sizeof(*netif_destroy_cb), GFP_KERNEL); + if (netif_destroy_cb == NULL) { + return -1; + } + netif_destroy_cb->cb = netif_cb; + list_add_tail(&netif_destroy_cb->list, &callback_ctrl.netif_destroy_cb_list); + + return 0; +} + +int +ngknet_netif_destroy_cb_unregister(ngknet_netif_cb_f netif_cb) +{ + struct list_head *list, *list_next; + netif_cb_t *netif_destroy_cb; + int found = 0; + + if (netif_cb == NULL) { + return -1; + } + list_for_each_safe(list, list_next, &callback_ctrl.netif_destroy_cb_list) { + netif_destroy_cb = list_entry(list, netif_cb_t, list); + if (netif_destroy_cb->cb == netif_cb) { + found = 1; + list_del(list); + break; + } + } + if (!found) { + return -1; + } + kfree(netif_destroy_cb); + + return 0; +} + +int +ngknet_filter_cb_register(ngknet_filter_cb_f filter_cb) +{ + if (callback_ctrl.filter_cb != NULL) { + return -1; + } + callback_ctrl.filter_cb = filter_cb; + + return 0; +} + +int +ngknet_filter_cb_register_by_name(ngknet_filter_cb_f filter_cb, const char *desc) +{ + struct ngknet_dev *dev; + struct list_head *list; + struct filt_ctrl *fc = NULL; + filter_cb_t *fcb; + unsigned long flags; + int idx; + + if (filter_cb == NULL || desc == NULL) { + return -1; + } + if (desc[0] == '\0' || strlen(desc) >= NGKNET_FILTER_DESC_MAX) { + return -1; + } + + list_for_each(list, &callback_ctrl.filter_cb_list) { + fcb = list_entry(list, filter_cb_t, list); + if (strcmp(fcb->desc, desc) == 0) { + return -1; + } + } + fcb = kmalloc(sizeof(*fcb), GFP_KERNEL); + if (fcb == NULL) { + return -1; + } + fcb->cb = filter_cb; + strscpy(fcb->desc, desc, sizeof(fcb->desc)); + list_add_tail(&fcb->list, &callback_ctrl.filter_cb_list); + + /* Check if any existing filter matches the registered name */ + for (idx = 0; idx < NUM_PDMA_DEV_MAX; idx++) { + dev = &callback_ctrl.devs[idx]; + if (!(dev->flags & NGKNET_DEV_ACTIVE) || + list_empty(&dev->filt_list)) { + continue; + } + spin_lock_irqsave(&dev->lock, flags); + list_for_each(list, &dev->filt_list) { + fc = (struct filt_ctrl *)list; + if (fc && + fc->filt.dest_type == NGKNET_FILTER_DEST_T_CB && + fc->filt.desc[0] != '\0') { + if (strcmp(fc->filt.desc, desc) == 0) { + fc->filter_cb = filter_cb; + } + } + } + spin_unlock_irqrestore(&dev->lock, flags); + } + return 0; +} + +int +ngknet_filter_cb_unregister(ngknet_filter_cb_f filter_cb) +{ + struct ngknet_dev *dev; + struct list_head *list, *list2; + struct filt_ctrl *fc = NULL; + filter_cb_t *fcb; + unsigned long flags; + int found = 0, idx; + + if (filter_cb == NULL) { + return -1; + } + + /* Check if the any existing filter-specific callback matches */ + + /* Remove from list */ + list_for_each_safe(list, list2, &callback_ctrl.filter_cb_list) { + fcb = list_entry(list, filter_cb_t, list); + if (fcb->cb == filter_cb) { + found = 1; + list_del(&fcb->list); + kfree(fcb); + break; + } + } + /* Check if the callback is set to filters */ + if (found) { + for (idx = 0; idx < NUM_PDMA_DEV_MAX; idx++) { + dev = &callback_ctrl.devs[idx]; + if (!(dev->flags & NGKNET_DEV_ACTIVE) || + list_empty(&dev->filt_list)) { + continue; + } + spin_lock_irqsave(&dev->lock, flags); + list_for_each(list, &dev->filt_list) { + fc = (struct filt_ctrl *)list; + if (fc && + fc->filt.dest_type == NGKNET_FILTER_DEST_T_CB && + fc->filter_cb == filter_cb) { + fc->filter_cb = NULL; + } + } + spin_unlock_irqrestore(&dev->lock, flags); + } + } + + if (!found && filter_cb != callback_ctrl.filter_cb) { + return -1; + } + if (!found || filter_cb == callback_ctrl.filter_cb) { + callback_ctrl.filter_cb = NULL; + } + return 0; +} + +int +ngknet_ptp_rx_config_set_cb_register(ngknet_ptp_config_set_cb_f ptp_rx_config_set_cb) +{ + if (callback_ctrl.ptp_rx_config_set_cb != NULL) { + return -1; + } + callback_ctrl.ptp_rx_config_set_cb = ptp_rx_config_set_cb; + + return 0; +} + +int +ngknet_ptp_rx_config_set_cb_unregister(ngknet_ptp_config_set_cb_f ptp_rx_config_set_cb) +{ + if (ptp_rx_config_set_cb == NULL || + callback_ctrl.ptp_rx_config_set_cb != ptp_rx_config_set_cb) { + return -1; + } + callback_ctrl.ptp_rx_config_set_cb = NULL; + + return 0; +} + +int +ngknet_ptp_tx_config_set_cb_register(ngknet_ptp_config_set_cb_f ptp_tx_config_set_cb) +{ + if (callback_ctrl.ptp_tx_config_set_cb != NULL) { + return -1; + } + callback_ctrl.ptp_tx_config_set_cb = ptp_tx_config_set_cb; + + return 0; +} + +int +ngknet_ptp_tx_config_set_cb_unregister(ngknet_ptp_config_set_cb_f ptp_tx_config_set_cb) +{ + if (ptp_tx_config_set_cb == NULL || + callback_ctrl.ptp_tx_config_set_cb != ptp_tx_config_set_cb) { + return -1; + } + callback_ctrl.ptp_tx_config_set_cb = NULL; + + return 0; +} + +int +ngknet_ptp_rx_hwts_get_cb_register(ngknet_ptp_hwts_get_cb_f ptp_rx_hwts_get_cb) +{ + if (callback_ctrl.ptp_rx_hwts_get_cb != NULL) { + return -1; + } + callback_ctrl.ptp_rx_hwts_get_cb = ptp_rx_hwts_get_cb; + + return 0; +} + +int +ngknet_ptp_rx_hwts_get_cb_unregister(ngknet_ptp_hwts_get_cb_f ptp_rx_hwts_get_cb) +{ + if (ptp_rx_hwts_get_cb == NULL || + callback_ctrl.ptp_rx_hwts_get_cb != ptp_rx_hwts_get_cb) { + return -1; + } + callback_ctrl.ptp_rx_hwts_get_cb = NULL; + + return 0; +} + +int +ngknet_ptp_tx_hwts_get_cb_register(ngknet_ptp_hwts_get_cb_f ptp_tx_hwts_get_cb) +{ + if (callback_ctrl.ptp_tx_hwts_get_cb != NULL) { + return -1; + } + callback_ctrl.ptp_tx_hwts_get_cb = ptp_tx_hwts_get_cb; + + return 0; +} + +int +ngknet_ptp_tx_hwts_get_cb_unregister(ngknet_ptp_hwts_get_cb_f ptp_tx_hwts_get_cb) +{ + if (ptp_tx_hwts_get_cb == NULL || + callback_ctrl.ptp_tx_hwts_get_cb != ptp_tx_hwts_get_cb) { + return -1; + } + callback_ctrl.ptp_tx_hwts_get_cb = NULL; + + return 0; +} + +int +ngknet_ptp_tx_meta_set_cb_register(ngknet_ptp_meta_set_cb_f ptp_tx_meta_set_cb) +{ + if (callback_ctrl.ptp_tx_meta_set_cb != NULL) { + return -1; + } + callback_ctrl.ptp_tx_meta_set_cb = ptp_tx_meta_set_cb; + + return 0; +} + +int +ngknet_ptp_tx_meta_set_cb_unregister(ngknet_ptp_meta_set_cb_f ptp_tx_meta_set_cb) +{ + if (ptp_tx_meta_set_cb == NULL || + callback_ctrl.ptp_tx_meta_set_cb != ptp_tx_meta_set_cb) { + return -1; + } + callback_ctrl.ptp_tx_meta_set_cb = NULL; + + return 0; +} + +int +ngknet_ptp_phc_index_get_cb_register(ngknet_ptp_phc_index_get_cb_f ptp_phc_index_get_cb) +{ + if (callback_ctrl.ptp_phc_index_get_cb != NULL) { + return -1; + } + callback_ctrl.ptp_phc_index_get_cb = ptp_phc_index_get_cb; + + return 0; +} + +int +ngknet_ptp_phc_index_get_cb_unregister(ngknet_ptp_phc_index_get_cb_f ptp_phc_index_get_cb) +{ + if (ptp_phc_index_get_cb == NULL || + callback_ctrl.ptp_phc_index_get_cb != ptp_phc_index_get_cb) { + return -1; + } + callback_ctrl.ptp_phc_index_get_cb = NULL; + + return 0; +} + +int +ngknet_ptp_dev_ctrl_cb_register(ngknet_ptp_dev_ctrl_cb_f ptp_dev_ctrl_cb) +{ + if (callback_ctrl.ptp_dev_ctrl_cb != NULL) { + return -1; + } + callback_ctrl.ptp_dev_ctrl_cb = ptp_dev_ctrl_cb; + + return 0; +} + +int +ngknet_ptp_dev_ctrl_cb_unregister(ngknet_ptp_dev_ctrl_cb_f ptp_dev_ctrl_cb) +{ + if (ptp_dev_ctrl_cb == NULL || + callback_ctrl.ptp_dev_ctrl_cb != ptp_dev_ctrl_cb) { + return -1; + } + callback_ctrl.ptp_dev_ctrl_cb = NULL; + + return 0; +} + +int +ngknet_ptp_rx_pre_process_cb_register(ngknet_ptp_rx_pre_process_cb_f ptp_rx_pre_process_cb) +{ + if (callback_ctrl.ptp_rx_pre_process_cb != NULL) { + return -1; + } + callback_ctrl.ptp_rx_pre_process_cb = ptp_rx_pre_process_cb; + + return 0; +} + +int +ngknet_ptp_rx_pre_process_cb_unregister(ngknet_ptp_rx_pre_process_cb_f ptp_rx_pre_process_cb) +{ + if (ptp_rx_pre_process_cb == NULL || + callback_ctrl.ptp_rx_pre_process_cb != ptp_rx_pre_process_cb) { + return -1; + } + callback_ctrl.ptp_rx_pre_process_cb = NULL; + + return 0; +} + +EXPORT_SYMBOL(ngknet_dev_init_cb_register); +EXPORT_SYMBOL(ngknet_dev_init_cb_unregister); +EXPORT_SYMBOL(ngknet_rx_cb_register); +EXPORT_SYMBOL(ngknet_rx_cb_unregister); +EXPORT_SYMBOL(ngknet_tx_cb_register); +EXPORT_SYMBOL(ngknet_tx_cb_unregister); +EXPORT_SYMBOL(ngknet_netif_create_cb_register); +EXPORT_SYMBOL(ngknet_netif_create_cb_unregister); +EXPORT_SYMBOL(ngknet_netif_destroy_cb_register); +EXPORT_SYMBOL(ngknet_netif_destroy_cb_unregister); +EXPORT_SYMBOL(ngknet_filter_cb_register); +EXPORT_SYMBOL(ngknet_filter_cb_register_by_name); +EXPORT_SYMBOL(ngknet_filter_cb_unregister); +EXPORT_SYMBOL(ngknet_ptp_rx_config_set_cb_register); +EXPORT_SYMBOL(ngknet_ptp_rx_config_set_cb_unregister); +EXPORT_SYMBOL(ngknet_ptp_tx_config_set_cb_register); +EXPORT_SYMBOL(ngknet_ptp_tx_config_set_cb_unregister); +EXPORT_SYMBOL(ngknet_ptp_rx_hwts_get_cb_register); +EXPORT_SYMBOL(ngknet_ptp_rx_hwts_get_cb_unregister); +EXPORT_SYMBOL(ngknet_ptp_tx_hwts_get_cb_register); +EXPORT_SYMBOL(ngknet_ptp_tx_hwts_get_cb_unregister); +EXPORT_SYMBOL(ngknet_ptp_tx_meta_set_cb_register); +EXPORT_SYMBOL(ngknet_ptp_tx_meta_set_cb_unregister); +EXPORT_SYMBOL(ngknet_ptp_phc_index_get_cb_register); +EXPORT_SYMBOL(ngknet_ptp_phc_index_get_cb_unregister); +EXPORT_SYMBOL(ngknet_ptp_dev_ctrl_cb_register); +EXPORT_SYMBOL(ngknet_ptp_dev_ctrl_cb_unregister); +EXPORT_SYMBOL(ngknet_ptp_rx_pre_process_cb_register); +EXPORT_SYMBOL(ngknet_ptp_rx_pre_process_cb_unregister); + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_callback.h b/systems/linux/kernel/modules/bcm-ngknet/ngknet_callback.h new file mode 100644 index 0000000..0c07748 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_callback.h @@ -0,0 +1,145 @@ +/*! \file ngknet_callback.h + * + * Data structure definitions for NGKNET callbacks. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_CALLBACK_H +#define NGKNET_CALLBACK_H + +#include + +typedef struct dev_cb_s { + /*! List head */ + struct list_head list; + + /*! Device callback */ + ngknet_dev_init_cb_f cb; +} dev_cb_t; + +typedef struct netif_cb_s { + /*! List head */ + struct list_head list; + + /*! Handle Netif creation or destruction */ + ngknet_netif_cb_f cb; +} netif_cb_t; + +typedef struct filter_cb_s { + /*! List head */ + struct list_head list; + + char desc[NGKNET_FILTER_DESC_MAX]; + + /*! Handle Filter callback */ + ngknet_filter_cb_f cb; +} filter_cb_t; + +/*! + * \brief NGKNET callback control. + */ +struct ngknet_callback_ctrl { + /*! Device initialization callback list */ + struct list_head dev_init_cb_list; + + /*! Handle Rx packet */ + ngknet_rx_cb_f rx_cb; + + /*! Handle Tx packet */ + ngknet_tx_cb_f tx_cb; + + /*! Netif creation list */ + struct list_head netif_create_cb_list; + + /*! Netif destruction list */ + struct list_head netif_destroy_cb_list; + + /*! Filter callback list */ + struct list_head filter_cb_list; + + /*! Handle filter callback */ + ngknet_filter_cb_f filter_cb; + + /*! PTP Rx config set */ + ngknet_ptp_config_set_cb_f ptp_rx_config_set_cb; + + /*! PTP Tx config set */ + ngknet_ptp_config_set_cb_f ptp_tx_config_set_cb; + + /*! PTP Rx HW timestamp get */ + ngknet_ptp_hwts_get_cb_f ptp_rx_hwts_get_cb; + + /*! PTP Tx HW timestamp get */ + ngknet_ptp_hwts_get_cb_f ptp_tx_hwts_get_cb; + + /*! PTP Tx meta set */ + ngknet_ptp_meta_set_cb_f ptp_tx_meta_set_cb; + + /*! PTP PHC index get */ + ngknet_ptp_phc_index_get_cb_f ptp_phc_index_get_cb; + + /*! PTP device control */ + ngknet_ptp_dev_ctrl_cb_f ptp_dev_ctrl_cb; + + /*! PTP Rx pre processing */ + ngknet_ptp_rx_pre_process_cb_f ptp_rx_pre_process_cb; + + /*! Devices */ + struct ngknet_dev *devs; +}; + +/*! + * \brief Initialize callback control. + * + * \param [in] devs Devices array. + */ +extern void +ngknet_callback_init(struct ngknet_dev *devs); + +/*! + * \brief Cleanup callback control. + * + */ +extern void +ngknet_callback_cleanup(void); + +/*! + * \brief Get callback control. + * + * \param [in] cbc Pointer to callback control. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_callback_control_get(struct ngknet_callback_ctrl **cbc); + +#endif /* NGKNET_CALLBACK_H */ diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_dep.h b/systems/linux/kernel/modules/bcm-ngknet/ngknet_dep.h new file mode 100644 index 0000000..3d4ea7d --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_dep.h @@ -0,0 +1,72 @@ +/*! \file ngknet_dep.h + * + * Macro definitions for NGKNET dependence. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_DEP_H +#define NGKNET_DEP_H + +#ifdef PKTIO_IMPL +#include +#else +#include +#endif +#include + +/*! Memorry barrier */ +#define MEMORY_BARRIER smp_mb() + +/*! CNET log macros */ +#define CNET_INFO(unit, fmt, args...) printk(KERN_INFO fmt, ##args) +#define CNET_ERROR(unit, fmt, args...) printk(KERN_ERR fmt, ##args) + +struct pdma_dev; + +/*! Externs for the required functions. */ +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ +extern int _bd##_cnet_pdma_attach(struct pdma_dev *dev); \ +extern int _bd##_cnet_pdma_detach(struct pdma_dev *dev); +#include + +/*! Create enumeration values from list of supported devices. */ +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + NGKNET_DEV_T_##_bd, +/*! Enumeration for all base device types. */ +typedef enum { + NGKNET_DEV_T_NONE = 0, +#include + NGKNET_DEV_T_COUNT +} ngknet_dev_type_t; + +#endif /* NGKNET_DEP_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_extra.c b/systems/linux/kernel/modules/bcm-ngknet/ngknet_extra.c new file mode 100644 index 0000000..4e7d555 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_extra.c @@ -0,0 +1,732 @@ +/*! \file ngknet_extra.c + * + * Utility routines for NGKNET enhancement. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "ngknet_main.h" +#include "ngknet_extra.h" +#include "ngknet_callback.h" +#include "ngknet_ptp.h" +#include "ngknet_adapter.h" + +/*! Defalut Rx tick for Rx rate limit control. */ +#define NGKNET_EXTRA_RATE_LIMIT_DEFAULT_RX_TICK 10 + +/*! + * SKB replicate mode when multiple filter hits, default to use skb_copy to be + * safe. + */ +#ifndef KNET_USE_SKB_CLONE +#define KNET_USE_SKB_CLONE 0 +#endif +#if KNET_USE_SKB_CLONE +#define skb_replicate(_skb, _gfp) skb_clone(_skb, _gfp) +#else +#define skb_replicate(_skb, _gfp) skb_copy(_skb, _gfp) +#endif + +static struct ngknet_rl_ctrl rl_ctrl; + +/*! + * The destination type NGKNET_FILTER_DEST_T_CB allows the user to + * perform advanced filtering and packet processing via a + * user-supplied filter callback function. + * + * The filter callback function is implemented in a separate Linux + * kernel module which is loaded on top of the KNET module, and the + * following APIs can be used to register the callback function with + * the KNET driver: + * + * ngknet_filter_cb_register + * (legacy API - only one callback possible per device) + * + * ngknet_filter_cb_register_by_name + * (supports multiple named callbacks per device) + * + * ngknet_filter_cb_unregister + * (unregisters a callback function) + * + * Notes: + * + * 1) The callbacks are done from interrupt context, so the user + * should defer any advanced processing to a work queue. + * + * 2) The named callbacks take priority over unnamed (legacy) + * callbacks if the filter priorities are the same. + * + * 3) Packet filters are processed in order of priority, and further + * processing is stopped once a matching filter is encountered. If + * additional filters have the same priority as the first matching + * filter, then all these filters will be processed as well, + * i.e. if such a filter matches, the associated filter action will + * be executed. + * + * 4) The sk_buff (skb) and ngknet_filter_t (filt) returned by the + * callback function (filter_cb) determine the next steps of the + * KNET driver: + * + * A) If skb == NULL, the callback has taken ownership of the + * packet and the callback function must ensure that the skb is + * freed. The filt parameter is ignored by the KNET driver. + * + * B) If skb != NULL, the packet will be redirected according to + * the destination returned by the callback function (filt). If + * filt is NULL or the destination is invalid, the packet is + * dropped and skb will be freed. + * + * 5) When multiple filters are matched, the KNET driver will ensure + * that each filter gets its own copy of the packet (skb), + * i.e. from the filters' perspective, no special processing is + * required. + */ +static inline int +ngknet_filter_callback(struct ngknet_dev *dev, struct filt_ctrl *fc, + struct sk_buff **skb, ngknet_filter_t **filt) +{ + struct ngknet_callback_desc *cbd = NGKNET_SKB_CB((*skb)); + struct pkt_hdr *pkh = (struct pkt_hdr *)(*skb)->data; + ngknet_filter_cb_f filter_cb; + + filter_cb = fc->filter_cb ? fc->filter_cb : dev->cbc->filter_cb; + if (!filter_cb) { + return SHR_E_UNAVAIL; + } + + cbd->dinfo = &dev->dev_info; + cbd->pmd = (*skb)->data + PKT_HDR_SIZE; + cbd->pmd_len = pkh->meta_len; + cbd->pkt_len = pkh->data_len; + cbd->filt = *filt; + *skb = filter_cb(*skb, filt); + return SHR_E_NONE; +} + +static inline bool +ngknet_filter_match(struct ngknet_dev *dev, int chan_id, + struct sk_buff *skb, ngknet_filter_t *filt) +{ + struct pkt_buf *pkb; + ngknet_filter_t scratch; + uint8_t *oob; + int idx, wsize; + + if (!dev || !skb || !filt) { + return false; + } + if (filt->flags & NGKNET_FILTER_F_ANY_DATA) { + return true; + } + if (filt->flags & NGKNET_FILTER_F_MATCH_CHAN && filt->chan != chan_id) { + return false; + } + + pkb = (struct pkt_buf *)skb->data; + do { + struct pkt_hdr *pkh = &pkb->pkh; + int pkt_len = PKT_HDR_SIZE + pkh->meta_len + pkh->data_len; + /* + * Try to match the scratch data if have. + */ + if ((skb->len - pkt_len) == NGKNET_SCRATCH_DATA_BYTES) { + if (!ngknet_adapter_filter_scratch_data_match(dev->dev_info.dev_no, chan_id, skb, filt)) { + return false; + } + } + } while (0); + + oob = &pkb->data; + + memcpy(&scratch.data.b[0], + &oob[filt->oob_data_offset], filt->oob_data_size); + memcpy(&scratch.data.b[filt->oob_data_size], + &pkb->data + pkb->pkh.meta_len + filt->pkt_data_offset, + filt->pkt_data_size); + wsize = NGKNET_BYTES2WORDS(filt->oob_data_size + filt->pkt_data_size); + for (idx = 0; idx < wsize; idx++) { + scratch.data.w[idx] &= filt->mask.w[idx]; + if (scratch.data.w[idx] != filt->data.w[idx]) { + break; + } + } + if (idx == wsize) { + return true; + } + return false; +} + +static inline int +ngknet_filter_process(struct ngknet_dev *dev, + struct sk_buff *skb, ngknet_filter_t *filt) +{ + struct ngknet_private *priv = NULL; + struct pkt_buf *pkb; + struct sk_buff *mirror_skb = NULL; + struct net_device *dest_ndev = NULL, *mirror_ndev = NULL; + unsigned long flags; + uint8_t *data = NULL; + uint16_t tpid; + int eth_offset = 0, cust_hdr_len = 0; + + if (!dev) { + return SHR_E_INTERNAL; + } + if (!skb) { + /* SKB was consumed by callback */ + return SHR_E_NONE; + } + if (!filt) { + return SHR_E_NO_HANDLER; + } + + spin_lock_irqsave(&dev->lock, flags); + + pkb = (struct pkt_buf *)skb->data; + switch (filt->dest_type) { + case NGKNET_FILTER_DEST_T_NETIF: + if (filt->dest_id == 0) { + dest_ndev = dev->net_dev; + } else { + dest_ndev = dev->vdev[filt->dest_id]; + } + if (dest_ndev) { + skb->dev = dest_ndev; + if (filt->dest_proto) { + pkb->pkh.attrs |= PDMA_RX_SET_PROTO; + skb->protocol = filt->dest_proto; + } + priv = netdev_priv(dest_ndev); + priv->users++; + } + break; + case NGKNET_FILTER_DEST_T_VNET: + pkb->pkh.attrs |= PDMA_RX_TO_VNET; + break; + case NGKNET_FILTER_DEST_T_NULL: + default: + break; + } + + spin_unlock_irqrestore(&dev->lock, flags); + + if (!dest_ndev) { + return SHR_E_NO_HANDLER; + } + + /* PTP Rx Pre processing */ + if (priv->hwts_rx_filter) { + ngknet_ptp_rx_pre_process(dest_ndev, skb, &cust_hdr_len); + } + + if (filt->flags & NGKNET_FILTER_F_STRIP_TAG) { + pkb->pkh.attrs |= PDMA_RX_STRIP_TAG; + eth_offset = PKT_HDR_SIZE + pkb->pkh.meta_len + cust_hdr_len; + data = skb->data + eth_offset; + tpid = data[12] << 8 | data[13]; + if (tpid == ETH_P_8021Q || tpid == ETH_P_8021AD) { + pkb->pkh.data_len -= VLAN_HLEN; + memmove(skb->data + VLAN_HLEN, skb->data, eth_offset + 2 * ETH_ALEN); + skb_pull(skb, VLAN_HLEN); + } + } + + if (dev->cbc->rx_cb) { + NGKNET_SKB_CB(skb)->filt = filt; + } + + if (filt->mirror_type == NGKNET_FILTER_DEST_T_NETIF) { + spin_lock_irqsave(&dev->lock, flags); + if (filt->mirror_id == 0) { + mirror_ndev = dev->net_dev; + } else { + mirror_ndev = dev->vdev[filt->mirror_id]; + } + if (mirror_ndev) { + mirror_skb = pskb_copy(skb, GFP_ATOMIC); + if (mirror_skb) { + mirror_skb->dev = mirror_ndev; + if (filt->mirror_proto) { + pkb->pkh.attrs |= PDMA_RX_SET_PROTO; + mirror_skb->protocol = filt->mirror_proto; + } + priv = netdev_priv(mirror_ndev); + priv->users++; + + if (dev->cbc->rx_cb) { + NGKNET_SKB_CB(mirror_skb)->filt = filt; + } + } + } + spin_unlock_irqrestore(&dev->lock, flags); + } + + /* Receive packet */ + priv->pkt_recv(dest_ndev, skb); + + /* Receive mirrored packet */ + if (mirror_ndev && mirror_skb) { + priv->pkt_recv(mirror_ndev, mirror_skb); + } + + return SHR_E_NONE; +} + +int +ngknet_filter_create(struct ngknet_dev *dev, ngknet_filter_t *filter) +{ + struct filt_ctrl *fc = NULL; + struct list_head *list = NULL; + ngknet_filter_t *filt = NULL; + filter_cb_t *filter_cb; + unsigned long flags; + int num, id, done = 0; + + switch (filter->type) { + case NGKNET_FILTER_T_RX_PKT: + break; + default: + return SHR_E_UNAVAIL; + } + + switch (filter->dest_type) { + case NGKNET_FILTER_DEST_T_NULL: + case NGKNET_FILTER_DEST_T_NETIF: + case NGKNET_FILTER_DEST_T_VNET: + case NGKNET_FILTER_DEST_T_CB: + break; + default: + return SHR_E_UNAVAIL; + } + + fc = kzalloc(sizeof(*fc), GFP_KERNEL); + if (!fc) { + return SHR_E_MEMORY; + } + + spin_lock_irqsave(&dev->lock, flags); + + num = (long)dev->fc[0]; + for (id = 1; id < num + 1; id++) { + if (!dev->fc[id]) { + break; + } + } + if (id > NUM_FILTER_MAX) { + spin_unlock_irqrestore(&dev->lock, flags); + kfree(fc); + return SHR_E_RESOURCE; + } + + dev->fc[id] = fc; + num += id == (num + 1) ? 1 : 0; + dev->fc[0] = (void *)(long)num; + + memcpy(&fc->filt, filter, sizeof(fc->filt)); + fc->filt.id = id; + + /* Check for filter-specific callback */ + if (filter->dest_type == NGKNET_FILTER_DEST_T_CB && + filter->desc[0] != '\0') { + list_for_each(list, &dev->cbc->filter_cb_list) { + filter_cb = list_entry(list, filter_cb_t, list); + if (strncmp(filter->desc, filter_cb->desc, + strlen(filter_cb->desc)) == 0) { + fc->filter_cb = filter_cb->cb; + break; + } + } + } + + list_for_each(list, &dev->filt_list) { + filt = &((struct filt_ctrl *)list)->filt; + if (filt->flags & NGKNET_FILTER_F_MATCH_CHAN) { + if (!(fc->filt.flags & NGKNET_FILTER_F_MATCH_CHAN) || + fc->filt.chan > filt->chan) { + continue; + } + if (fc->filt.chan < filt->chan || + fc->filt.priority < filt->priority) { + list_add_tail(&fc->list, list); + done = 1; + break; + } + } else { + if (fc->filt.flags & NGKNET_FILTER_F_MATCH_CHAN || + fc->filt.priority < filt->priority) { + list_add_tail(&fc->list, list); + done = 1; + break; + } + } + } + if (!done) { + list_add_tail(&fc->list, &dev->filt_list); + } + + filter->id = fc->filt.id; + + spin_unlock_irqrestore(&dev->lock, flags); + + return SHR_E_NONE; +} + +int +ngknet_filter_destroy(struct ngknet_dev *dev, int id) +{ + struct filt_ctrl *fc = NULL; + unsigned long flags; + int num; + + if (id <= 0 || id > NUM_FILTER_MAX) { + return SHR_E_PARAM; + } + + spin_lock_irqsave(&dev->lock, flags); + + fc = (struct filt_ctrl *)dev->fc[id]; + if (!fc) { + spin_unlock_irqrestore(&dev->lock, flags); + return SHR_E_NOT_FOUND; + } + + list_del(&fc->list); + kfree(fc); + + dev->fc[id] = NULL; + num = (long)dev->fc[0]; + while (num-- == id--) { + if (dev->fc[id]) { + dev->fc[0] = (void *)(long)num; + break; + } + } + + spin_unlock_irqrestore(&dev->lock, flags); + + return SHR_E_NONE; +} + +int +ngknet_filter_destroy_all(struct ngknet_dev *dev) +{ + int id; + int rv; + + for (id = 1; id <= NUM_FILTER_MAX; id++) { + rv = ngknet_filter_destroy(dev, id); + if (SHR_FAILURE(rv)) { + return rv; + } + } + + return SHR_E_NONE; +} + +int +ngknet_filter_get(struct ngknet_dev *dev, int id, ngknet_filter_t *filter) +{ + struct filt_ctrl *fc = NULL; + unsigned long flags; + int num; + + if (id <= 0 || id > NUM_FILTER_MAX) { + return SHR_E_PARAM; + } + + spin_lock_irqsave(&dev->lock, flags); + + fc = (struct filt_ctrl *)dev->fc[id]; + if (!fc) { + spin_unlock_irqrestore(&dev->lock, flags); + return SHR_E_NOT_FOUND; + } + + memcpy(filter, &fc->filt, sizeof(*filter)); + + num = (long)dev->fc[0]; + for (id++; id < num + 1; id++) { + if (dev->fc[id]) { + break; + } + } + filter->next = id == (num + 1) ? 0 : id; + + spin_unlock_irqrestore(&dev->lock, flags); + + return SHR_E_NONE; +} + +int +ngknet_filter_get_next(struct ngknet_dev *dev, ngknet_filter_t *filter) +{ + int id; + int rv; + + if (!filter->next) { + for (id = 1; id <= NUM_FILTER_MAX; id++) { + rv = ngknet_filter_get(dev, id, filter); + if (SHR_SUCCESS(rv)) { + return rv; + } + } + if (id > NUM_FILTER_MAX) { + return SHR_E_NOT_FOUND; + } + } + + return ngknet_filter_get(dev, filter->next, filter); +} + +int +ngknet_rx_pkt_filter(struct ngknet_dev *dev, struct sk_buff *skb) +{ + struct sk_buff *fskb = NULL; + struct net_device *dest_ndev = NULL; + struct ngknet_private *priv = NULL; + struct filt_ctrl *fc = NULL; + struct list_head *list = NULL, *next_list = NULL; + ngknet_filter_t *filt = NULL, *next_filt = NULL; + struct pkt_buf *pkb = (struct pkt_buf *)skb->data; + unsigned long flags; + int rv, chan_id; + uint32_t next_filter_match = 0, same_pri_idx; + + rv = bcmcnet_pdma_dev_queue_to_chan(&dev->pdma_dev, pkb->pkh.queue_id, + PDMA_Q_RX, &chan_id); + if (SHR_FAILURE(rv)) { + return rv; + } + + spin_lock_irqsave(&dev->lock, flags); + + dest_ndev = dev->bdev[chan_id]; + if (dest_ndev) { + skb->dev = dest_ndev; + priv = netdev_priv(dest_ndev); + priv->users++; + spin_unlock_irqrestore(&dev->lock, flags); + priv->pkt_recv(dest_ndev, skb); + return SHR_E_NONE; + } + + if (list_empty(&dev->filt_list)) { + spin_unlock_irqrestore(&dev->lock, flags); + return SHR_E_NO_HANDLER; + } + + rv = SHR_E_NO_HANDLER; + list_for_each(list, &dev->filt_list) { + fc = (struct filt_ctrl *)list; + filt = &fc->filt; + if (next_filter_match || ngknet_filter_match(dev, chan_id, skb, filt)) { + if (next_filter_match && --next_filter_match > 0) { + /* Same priority, but not matching */ + continue; + } + fc->hits++; + fskb = skb; + next_list = list->next; + same_pri_idx = 0; + /* Look for matching filters with same priority */ + while (next_list != &dev->filt_list) { + next_filt = &((struct filt_ctrl *)next_list)->filt; + if (next_filt->priority != filt->priority) { + break; + } + same_pri_idx++; + if (ngknet_filter_match(dev, chan_id, skb, next_filt)) { + /* Found another matching filter with same priority */ + fskb = skb_replicate(skb, GFP_ATOMIC); + next_filter_match = same_pri_idx; + break; + } + next_list = next_list->next; + } + + spin_unlock_irqrestore(&dev->lock, flags); + + if (filt->dest_type == NGKNET_FILTER_DEST_T_CB) { + (void)ngknet_filter_callback(dev, fc, &fskb, &filt); + } + + rv = ngknet_filter_process(dev, fskb, filt); + if (SHR_FAILURE(rv) && fskb != skb) { + dev_kfree_skb_any(fskb); + } + + spin_lock_irqsave(&dev->lock, flags); + + if (!next_filter_match) { + break; + } + } + } + + spin_unlock_irqrestore(&dev->lock, flags); + + return rv; +} + +static void +ngknet_rl_process(timer_context_t data) +{ + struct ngknet_rl_ctrl *rc = timer_arg(rc, data, timer); + struct ngknet_dev *dev; + unsigned long flags; + int idx; + + spin_lock_irqsave(&rc->lock, flags); + rc->rx_pkts = 0; + for (idx = 0; idx < NUM_PDMA_DEV_MAX; idx++) { + dev = &rc->devs[idx]; + if (rc->dev_active[idx] && rc->dev_paused[idx]) { + bcmcnet_pdma_dev_rx_resume(&dev->pdma_dev); + rl_ctrl.dev_paused[dev->dev_info.dev_no] = 0; + } + } + spin_unlock_irqrestore(&rc->lock, flags); + + rc->timer.expires = jiffies + HZ / rc->rx_ticks; + add_timer(&rc->timer); +} + +void +ngknet_rx_rate_limit_init(struct ngknet_dev *devs) +{ + sal_memset(&rl_ctrl, 0, sizeof(rl_ctrl)); + rl_ctrl.rx_ticks = NGKNET_EXTRA_RATE_LIMIT_DEFAULT_RX_TICK; + setup_timer(&rl_ctrl.timer, ngknet_rl_process, (timer_context_t)&rl_ctrl); + spin_lock_init(&rl_ctrl.lock); + rl_ctrl.devs = devs; +} + +void +ngknet_rx_rate_limit_cleanup(void) +{ + del_timer_sync(&rl_ctrl.timer); +} + +int +ngknet_rx_rate_limit_started(void) +{ + return rl_ctrl.started; +} + +void +ngknet_rx_rate_limit_start(struct ngknet_dev *dev) +{ + unsigned long flags; + + spin_lock_irqsave(&rl_ctrl.lock, flags); + rl_ctrl.dev_active[dev->dev_info.dev_no] = 1; + spin_unlock_irqrestore(&rl_ctrl.lock, flags); + + if (!rl_ctrl.started) { + rl_ctrl.started = 1; + rl_ctrl.timer.expires = jiffies + HZ / rl_ctrl.rx_ticks; + add_timer(&rl_ctrl.timer); + } +} + +void +ngknet_rx_rate_limit_stop(struct ngknet_dev *dev) +{ + unsigned long flags; + + spin_lock_irqsave(&rl_ctrl.lock, flags); + rl_ctrl.dev_active[dev->dev_info.dev_no] = 0; + spin_unlock_irqrestore(&rl_ctrl.lock, flags); +} + +void +ngknet_rx_rate_limit(struct ngknet_dev *dev, int limit) +{ + unsigned long flags; + + /* To support lower rate, we should use smaller tick (larger interval). */ + if (limit < 1000) { + rl_ctrl.rx_ticks = (limit + 99) / 100; + } else { + rl_ctrl.rx_ticks = NGKNET_EXTRA_RATE_LIMIT_DEFAULT_RX_TICK; + } + + spin_lock_irqsave(&rl_ctrl.lock, flags); + if ((++rl_ctrl.rx_pkts + rl_ctrl.rx_overruns > limit / rl_ctrl.rx_ticks) && + !rl_ctrl.dev_paused[dev->dev_info.dev_no] && + rl_ctrl.dev_active[dev->dev_info.dev_no]) { + rl_ctrl.dev_paused[dev->dev_info.dev_no] = 1; + rl_ctrl.rx_overruns = 0; + bcmcnet_pdma_dev_rx_suspend(&dev->pdma_dev); + } + if (rl_ctrl.dev_paused[dev->dev_info.dev_no]) { + rl_ctrl.rx_overruns++; + } + spin_unlock_irqrestore(&rl_ctrl.lock, flags); +} + +void +ngknet_tx_queue_schedule(struct ngknet_dev *dev, struct sk_buff *skb, int *queue) +{ + struct pkt_buf *pkb = (struct pkt_buf *)skb->data; + + if (pkb->pkh.attrs & PDMA_TX_BIND_QUE) { + *queue = pkb->pkh.queue_id; + } +} + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_extra.h b/systems/linux/kernel/modules/bcm-ngknet/ngknet_extra.h new file mode 100644 index 0000000..862213b --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_extra.h @@ -0,0 +1,233 @@ +/*! \file ngknet_extra.h + * + * Generic data structure definitions for NGKNET enhancement. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_EXTRA_H +#define NGKNET_EXTRA_H + +#include + +/*! + * \brief Filter control. + */ +struct filt_ctrl { + /*! List head */ + struct list_head list; + + /*! Device number */ + int dev_no; + + /*! Number of hits */ + uint64_t hits; + + /*! Filter description */ + ngknet_filter_t filt; + + /*! Filter callback */ + ngknet_filter_cb_f filter_cb; +}; + +/*! + * \brief Create filter. + * + * \param [in] dev Device structure point. + * \param [in] filter Filter structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +ngknet_filter_create(struct ngknet_dev *dev, ngknet_filter_t *filter); + +/*! + * \brief Destroy filter. + * + * \param [in] dev Device structure point. + * \param [in] id Filter ID. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +ngknet_filter_destroy(struct ngknet_dev *dev, int id); + +/*! + * \brief Destroy all the filters. + * + * \param [in] dev Device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +ngknet_filter_destroy_all(struct ngknet_dev *dev); + +/*! + * \brief Get filter. + * + * \param [in] dev Device structure point. + * \param [in] id Filter ID. + * \param [out] filter Filter structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +ngknet_filter_get(struct ngknet_dev *dev, int id, ngknet_filter_t *filter); + +/*! + * \brief Get the next filter. + * + * \param [in] dev Device structure point. + * \param [out] filter Filter structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +ngknet_filter_get_next(struct ngknet_dev *dev, ngknet_filter_t *filter); + +/*! + * \brief Filter packet. + * + * \param [in] dev Device structure point. + * \param [in] skb Rx packet SKB. + * + * \retval Matched network interface. + * \retval NULL No matched network interface. + */ +extern int +ngknet_rx_pkt_filter(struct ngknet_dev *dev, struct sk_buff *skb); + +/*! + * \brief Rx rate limit control. + * + * This contains all the control information for Rx rate limit such as + * the number of Rx packets, status related to Rx rate limit, etc. + * + * The rate limit is kernel-oriented, i.e. all the Rx packets from any + * device/channel will be accounted for. Once the received packets reach + * the limit value in an 1-Sec interval, the driver API XXXX_rx_suspend() + * will be called to suspend Rx. The 1-Sec basis timer will call the driver + * API XXXX_rx_resume() to resume Rx and reset rate-related status/counters + * at the begin of the next 1-Sec interval. + * + * The NGKNET module parameter 'rx_rate_limit' is used to decide the maximum + * Rx rate. Disable Rx rate limit if set 0. It can be set when inserting + * NGKNET module or modified using its SYSFS attributions. + */ +struct ngknet_rl_ctrl { + /*! Rx packets */ + int rx_pkts; + + /*! Rx overruns */ + int rx_overruns; + + /*! Rx ticks */ + int rx_ticks; + + /*! Active devices under rate control */ + int dev_active[NUM_PDMA_DEV_MAX]; + + /*! Paused devices due to no Rx credit */ + int dev_paused[NUM_PDMA_DEV_MAX]; + + /*! Rate limit timer */ + struct timer_list timer; + + /*! Rate limit lock */ + spinlock_t lock; + + /*! Devices */ + struct ngknet_dev *devs; + + /*! Rate limit status indicator */ + int started; +}; + +/*! + * \brief Initialize Rx rate limit. + * + * \param [in] devs Devices array. + */ +extern void +ngknet_rx_rate_limit_init(struct ngknet_dev *devs); + +/*! + * \brief Cleanup Rx rate limit. + */ +extern void +ngknet_rx_rate_limit_cleanup(void); + +/*! + * \brief Get Rx rate limit state. + */ +extern int +ngknet_rx_rate_limit_started(void); + +/*! + * \brief Start Rx rate limit. + * + * \param [in] dev Device structure point. + */ +extern void +ngknet_rx_rate_limit_start(struct ngknet_dev *dev); + +/*! + * \brief Stop Rx rate limit. + * + * \param [in] dev Device structure point. + */ +extern void +ngknet_rx_rate_limit_stop(struct ngknet_dev *dev); + +/*! + * \brief Limit Rx rate. + * + * \param [in] dev Device structure point. + */ +extern void +ngknet_rx_rate_limit(struct ngknet_dev *dev, int limit); + +/*! + * \brief Schedule Tx queue. + * + * \param [in] dev Device structure point. + * \param [in] queue Tx queue number. + */ +extern void +ngknet_tx_queue_schedule(struct ngknet_dev *dev, struct sk_buff *skb, int *queue); + +#endif /* NGKNET_EXTRA_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_linux.c b/systems/linux/kernel/modules/bcm-ngknet/ngknet_linux.c new file mode 100644 index 0000000..68ab649 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_linux.c @@ -0,0 +1,182 @@ +/*! \file ngknet_linux.c + * + * Utility routines for Linux kernel APIs abstraction. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ngknet_linux.h" + +/*! + * Time + */ + +unsigned long +sal_time_usecs(void) +{ + return (unsigned long)kal_time_usecs(); +} + +void +sal_usleep(unsigned long usec) +{ + unsigned long then, now, hz; + + hz = usec * HZ / 1000000; + if (hz) { + schedule_timeout(hz); + } + usec = usec * HZ % 1000000 / HZ; + if (usec) { + then = sal_time_usecs(); + do { + schedule(); + now = sal_time_usecs(); + } while (now > then && (now - then) < usec); + } +} + +/*! + * Synchronization + */ + +typedef struct { + struct semaphore sem; + char *desc; + int binary; +} sem_ctrl_t; + +sal_sem_t +sal_sem_create(char *desc, int binary, int count) +{ + sem_ctrl_t *sc = kmalloc(sizeof(*sc), GFP_KERNEL); + + if (sc != NULL) { + sema_init(&sc->sem, count); + sc->desc = desc; + sc->binary = binary; + } + + return (sal_sem_t)sc; +} + +void +sal_sem_destroy(sal_sem_t sem) +{ + sem_ctrl_t *sc = (sem_ctrl_t *)sem; + + kfree(sc); +} + +int +sal_sem_take(sal_sem_t sem, int usec) +{ + sem_ctrl_t *sc = (sem_ctrl_t *)sem; + int rv; + + if (usec == SAL_SEM_FOREVER) { + do { + rv = down_interruptible(&sc->sem); + } while (rv == -EINTR); + return rv ? -1 : 0; + } + + return -1; +} + +int +sal_sem_give(sal_sem_t sem) +{ + sem_ctrl_t *sc = (sem_ctrl_t *)sem; + + up(&sc->sem); + + return 0; +} + +typedef struct spinlock_ctrl_s { + spinlock_t spinlock; + unsigned long flags; + char *desc; +} *spinlock_ctrl_t; + +sal_spinlock_t +sal_spinlock_create(char *desc) +{ + spinlock_ctrl_t sl = kmalloc(sizeof(*sl), GFP_KERNEL); + + if (sl != NULL) { + spin_lock_init(&sl->spinlock); + sl->flags = 0; + sl->desc = desc; + } + + return (sal_spinlock_t)sl; +} + +void +sal_spinlock_destroy(sal_spinlock_t lock) +{ + spinlock_ctrl_t sl = (spinlock_ctrl_t)lock; + + kfree(sl); +} + +int +sal_spinlock_lock(sal_spinlock_t lock) +{ + spinlock_ctrl_t sl = (spinlock_ctrl_t)lock; + + spin_lock_irqsave(&sl->spinlock, sl->flags); + + return 0; +} + +int +sal_spinlock_unlock(sal_spinlock_t lock) +{ + spinlock_ctrl_t sl = (spinlock_ctrl_t)lock; + + spin_unlock_irqrestore(&sl->spinlock, sl->flags); + + return 0; +} + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_linux.h b/systems/linux/kernel/modules/bcm-ngknet/ngknet_linux.h new file mode 100644 index 0000000..1057552 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_linux.h @@ -0,0 +1,326 @@ +/*! \file ngknet_linux.h + * + * Data structure and macro definitions for Linux kernel APIs abstraction. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_LINUX_H +#define NGKNET_LINUX_H + +#include +#include +#include +#include + +/*! + * Kernel abstraction + */ + +#define MODULE_PARAM(n, t, p) module_param(n, t, p) + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,19,0)) +#define kal_netif_napi_add(_dev, _napi, _poll, _weight) \ + netif_napi_add(_dev, _napi, _poll, _weight) +#else +#define kal_netif_napi_add(_dev, _napi, _poll, _weight) \ + netif_napi_add_weight(_dev, _napi, _poll, _weight) +#endif + +/* + * The eth_hw_addr_set was added in Linux 5.15, but later backported + * to various longterm releases, so we need a more advanced check with + * the option to override the default. + */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)) +#define KERNEL_HAS_ETH_HW_ADDR_SET 1 +#endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,11,0) && \ + LINUX_VERSION_CODE >= KERNEL_VERSION(5,10,188)) +#define KERNEL_HAS_ETH_HW_ADDR_SET 1 +#endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,5,0) && \ + LINUX_VERSION_CODE >= KERNEL_VERSION(5,4,251)) +#define KERNEL_HAS_ETH_HW_ADDR_SET 1 +#endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,20,0) && \ + LINUX_VERSION_CODE >= KERNEL_VERSION(4,19,291)) +#define KERNEL_HAS_ETH_HW_ADDR_SET 1 +#endif +#ifndef KERNEL_HAS_ETH_HW_ADDR_SET +#define KERNEL_HAS_ETH_HW_ADDR_SET 0 +#endif + +#if (KERNEL_HAS_ETH_HW_ADDR_SET == 0) +static inline void +eth_hw_addr_set(struct net_device *dev, const u8 *addr) +{ + memcpy(dev->dev_addr, addr, ETH_ALEN); +} +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)) +#define NGKNET_ETHTOOL_LINK_SETTINGS 1 +#else +#define NGKNET_ETHTOOL_LINK_SETTINGS 0 +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) +#define kal_vlan_hwaccel_put_tag(skb, proto, tci) \ + __vlan_hwaccel_put_tag(skb, tci) +#define NETIF_F_HW_VLAN_CTAG_RX NETIF_F_HW_VLAN_RX +#define NETIF_F_HW_VLAN_CTAG_TX NETIF_F_HW_VLAN_TX +#else +#define kal_vlan_hwaccel_put_tag(skb, proto, tci) \ + __vlan_hwaccel_put_tag(skb, htons(proto), tci) +#endif /* KERNEL_VERSION(3,10,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,19,0) +static inline struct page * +kal_dev_alloc_pages(unsigned int order) +{ + return alloc_pages(GFP_ATOMIC | __GFP_ZERO | __GFP_COLD | + __GFP_COMP | __GFP_MEMALLOC, order); +} +#else +static inline struct page * +kal_dev_alloc_pages(unsigned int order) +{ + return dev_alloc_pages(order); +} +#endif /* KERNEL_VERSION(3,19,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) +static inline struct sk_buff * +kal_build_skb(void *data, unsigned int frag_size) +{ + return NULL; +} +#else +static inline struct sk_buff * +kal_build_skb(void *data, unsigned int frag_size) +{ + return build_skb(data, frag_size); +} +#endif /* KERNEL_VERSION(3,5,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0) +static inline bool +kal_page_is_pfmemalloc(struct page *page) +{ + return false; +} +#else +static inline bool +kal_page_is_pfmemalloc(struct page *page) +{ + return page_is_pfmemalloc(page); +} +#endif /* KERNEL_VERSION(4,2,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) +static inline void +kal_netif_trans_update(struct net_device *dev) +{ + dev->trans_start = jiffies; +} +#else +static inline void +kal_netif_trans_update(struct net_device *dev) +{ + netif_trans_update(dev); +} +#endif /* KERNEL_VERSION(4,7,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,10,0) +static inline dma_addr_t +kal_dma_map_page_attrs(struct device *dev, struct page *page, + size_t offset, size_t size, enum dma_data_direction dir, + unsigned long attrs) +{ + return dma_map_page(dev, page, offset, size, dir); +} +static inline void +kal_dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, + size_t size, enum dma_data_direction dir, + unsigned long attrs) +{ + dma_unmap_page(dev, addr, size, dir); +} +#else +static inline dma_addr_t +kal_dma_map_page_attrs(struct device *dev, struct page *page, + size_t offset, size_t size, enum dma_data_direction dir, + unsigned long attrs) +{ + return dma_map_page_attrs(dev, page, offset, size, dir, attrs); +} +static inline void +kal_dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, + size_t size, enum dma_data_direction dir, + unsigned long attrs) +{ + dma_unmap_page_attrs(dev, addr, size, dir, attrs); +} +#endif /* KERNEL_VERSION(4,10,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,17,0) +static inline s64 +kal_time_usecs(void) +{ + struct timeval tv; + do_gettimeofday(&tv); + return tv.tv_sec * 1000000 + tv.tv_usec; +} +#else +static inline s64 +kal_time_usecs(void) +{ + struct timespec64 ts; + ktime_get_real_ts64(&ts); + return ts.tv_sec * 1000000 + ts.tv_nsec / 1000; +} +#endif /* KERNEL_VERSION(3,17,0) */ + +static inline unsigned long +kal_copy_from_user(void *to, const void __user *from, + unsigned int dl, unsigned int sl) +{ + unsigned int len = dl; + + if (unlikely(len != sl)) { + printk(KERN_WARNING "Unmatched linux_ngknet.ko, please use the latest.\n"); + len = min(dl, sl); + } + + return copy_from_user(to, from, len); +} + +static inline unsigned long +kal_copy_to_user(void __user *to, const void *from, + unsigned int dl, unsigned int sl) +{ + unsigned int len = dl; + + if (unlikely(len != sl)) { + printk(KERN_WARNING "Unmatched linux_ngknet.ko, please use the latest.\n"); + len = min(dl, sl); + } + + return copy_to_user(to, from, len); +} + +/*! + * System abstraction + */ + +static inline void * +sal_alloc(unsigned int sz, char *s) +{ + return kmalloc(sz, GFP_KERNEL); +} + +static inline void +sal_free(void *addr) +{ + kfree(addr); +} + +static inline void * +sal_memset(void *dest, int c, size_t cnt) +{ + return memset(dest, c, cnt); +} + +static inline void * +sal_memcpy(void *dest, const void *src, size_t cnt) +{ + return memcpy(dest, src, cnt); +} + +static inline char * +sal_strncpy(char *dest, const char *src, size_t cnt) +{ + return strncpy(dest, src, cnt); +} + +/*! + * Time + */ + +extern unsigned long +sal_time_usecs(void); + +extern void +sal_usleep(unsigned long usec); + +/*! + * Synchronization + */ + +typedef struct sal_sem_s { + char semaphore_opaque_type; +} *sal_sem_t; + +typedef struct sal_spinlock_s { + char spinlock_opaque_type; +} *sal_spinlock_t; + +#define SAL_SEM_FOREVER -1 +#define SAL_SEM_BINARY 1 +#define SAL_SEM_COUNTING 0 + +extern sal_sem_t +sal_sem_create(char *desc, int binary, int count); + +extern void +sal_sem_destroy(sal_sem_t sem); + +extern int +sal_sem_take(sal_sem_t sem, int usec); + +extern int +sal_sem_give(sal_sem_t sem); + +extern sal_spinlock_t +sal_spinlock_create(char *desc); + +extern void +sal_spinlock_destroy(sal_spinlock_t lock); + +extern int +sal_spinlock_lock(sal_spinlock_t lock); + +extern int +sal_spinlock_unlock(sal_spinlock_t lock); + +#endif /* NGKNET_LINUX_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_main.c b/systems/linux/kernel/modules/bcm-ngknet/ngknet_main.c new file mode 100644 index 0000000..2f65429 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_main.c @@ -0,0 +1,3457 @@ +/*! \file ngknet_main.c + * + * NGKNET module entry. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +/* + * This module implements a Linux network driver for Broadcom + * XGS switch devices. The driver simultaneously serves a + * number of virtual Linux network devices. + * + * Packets received from the switch device are sent to a virtual + * Linux network device based on a set of packet filters. + * + * Packets from the virtual Linux network devices are multiplexed + * with fifo mode if only one Tx queue enabled. + * + * A command-based IOCTL interface is used for managing the devices, + * packet filters and virtual Linux network interfaces. + * + * A virtual network interface can be configured to work in RCPU + * mode, which means that packets from the switch device will + * be encapsulated with a RCPU header and a block of meta data + * that basically contains the core DCB information. Likewise, + * packets received from the Linux network stack are assumed to + * be RCPU encapsulated when going out on an interface in RCPU + * mode. If a virtual network interface does not work in RCPU + * mode and transmits to this interface will unmodified go to + * specified physical switch port, DCB information should be + * provided when the interface is created. + * + * The module implements basic Rx DMA rate control. The rate is + * specified in packets per second, and different Rx DMA channels + * can be configured to use different maximum packet rates. + * The packet rate can be configure as a module parameter, and + * it can also be changed dynamically through the proc file + * system (syntax is described in function header comment). + * + * For a list of supported module parameters, please see below. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include "ngknet_main.h" +#include "ngknet_extra.h" +#include "ngknet_procfs.h" +#include "ngknet_callback.h" +#include "ngknet_ptp.h" +#include "ngknet_adapter.h" + +/*! \cond */ +MODULE_AUTHOR("Broadcom Corporation"); +MODULE_DESCRIPTION("Network Device Driver Module"); +MODULE_LICENSE("GPL"); +/*! \endcond */ + +/*! \cond */ +static int debug = 0; +MODULE_PARAM(debug, int, 0); +MODULE_PARM_DESC(debug, +"Debug level (default 0)"); +/*! \endcond */ + +/*! \cond */ +static char *base_dev_name = "bcm"; +MODULE_PARAM(base_dev_name, charp, 0); +MODULE_PARM_DESC(base_dev_name, +"Base device name (default bcm0, bcm1, etc.)"); +/*! \endcond */ + +/*! \cond */ +static char *mac_addr = NULL; +MODULE_PARAM(mac_addr, charp, 0); +MODULE_PARM_DESC(mac_addr, +"Ethernet MAC address (default 02:10:18:xx:xx:xx)"); +/*! \endcond */ + +/*! \cond */ +static int default_mtu = 1500; +MODULE_PARAM(default_mtu, int, 0); +MODULE_PARM_DESC(default_mtu, +"MTU size for KNET network interfaces (default 1500)"); +/*! \endcond */ + +/*! \cond */ +static int rx_buffer_size = RX_BUF_SIZE_DFLT; +MODULE_PARAM(rx_buffer_size, int, 0); +MODULE_PARM_DESC(rx_buffer_size, +"RX packet buffer size in bytes (default 9216)"); +/*! \endcond */ + +/*! \cond */ +static int rx_rate_limit = -1; +MODULE_PARAM(rx_rate_limit, int, 0); +MODULE_PARM_DESC(rx_rate_limit, +"Rx rate limit in packets per second (default -1 for no limit)"); +/*! \endcond */ + +/*! \cond */ +static int tx_polling = 0; +MODULE_PARAM(tx_polling, int, 0); +MODULE_PARM_DESC(tx_polling, +"Enable Tx poll mode (default 0 for interrupt mode)"); +/*! \endcond */ + +/*! \cond */ +static int rx_batching = 0; +MODULE_PARAM(rx_batching, int, 0); +MODULE_PARM_DESC(rx_batching, +"Enable Rx batch fill mode (default 0 for single fill mode)"); +/*! \endcond */ + +/*! \cond */ +static int page_buffer_mode = 0; +MODULE_PARAM(page_buffer_mode, int, 0); +MODULE_PARM_DESC(page_buffer_mode, +"Enable SKB page buffer mode (default 0 for legacy SKB mode)"); +/*! \endcond */ + +typedef int (*drv_ops_attach)(struct pdma_dev *dev); + +struct bcmcnet_drv_ops { + const char *drv_desc; + drv_ops_attach drv_attach; + drv_ops_attach drv_detach; +}; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + static struct bcmcnet_drv_ops _bd##_cnet_drv_ops = { \ + #_bd, \ + _bd##_cnet_pdma_attach, \ + _bd##_cnet_pdma_detach, \ + }; +#include + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + &_bd##_cnet_drv_ops, +static struct bcmcnet_drv_ops *drv_ops[] = { + NULL, +#include + NULL +}; +static int drv_num = sizeof(drv_ops) / sizeof(drv_ops[0]); + +struct ngknet_dev ngknet_devices[NUM_PDMA_DEV_MAX]; + +/* Default random MAC address has Broadcom OUI with local admin bit set */ +static uint8_t ngknet_dev_mac[6] = {0x02, 0x10, 0x18, 0x00, 0x00, 0x00}; + +/* Interrupt handles */ +struct ngknet_intr_handle { + struct napi_struct napi; + struct intr_handle *hdl; + int napi_resched; + int napi_pending; +}; + +static struct ngknet_intr_handle priv_hdl[NUM_PDMA_DEV_MAX][NUM_Q_MAX]; + +/*! + * Dump packet content for debug + */ +static void +ngknet_pkt_dump(uint8_t *data, int len) +{ + char str[128]; + int i; + + len = len > 256 ? 256 : len; + + for (i = 0; i < len; i++) { + if ((i & 0x1f) == 0) { + sprintf(str, "%04x: ", i); + } + sprintf(&str[strlen(str)], "%02x", data[i]); + if ((i & 0x1f) == 0x1f) { + sprintf(&str[strlen(str)], "\n"); + printk(str); + continue; + } + if ((i & 0x3) == 0x3) { + sprintf(&str[strlen(str)], " "); + } + } + if ((i & 0x1f) != 0) { + sprintf(&str[strlen(str)], "\n"); + printk(str); + } + printk("\n"); +} + +/*! + * Rx packets rate test for debug + */ +static void +ngknet_pkt_stats(struct pdma_dev *pdev, int dir) +{ + s64 ts0[2], ts1[2]; + static uint32_t pkts[2] = {0}, prts[2] = {0}; + static uint64_t intrs = 0; + uint32_t iv_time; + uint32_t pps; + uint32_t boudary; + + if (rx_rate_limit == -1 || rx_rate_limit >= 100000) { + /* Dump every 100K packets */ + boudary = 100000; + } else if (rx_rate_limit >= 10000) { + /* Dump every 10K packets */ + boudary = 10000; + } else { + /* Dump every 1K packets */ + boudary = 1000; + } + + if (pkts[dir] == 0) { + ts0[dir] = kal_time_usecs(); + intrs = pdev->stats.intrs; + } + if (++pkts[dir] >= boudary) { + ts1[dir] = kal_time_usecs(); + iv_time = ts1[dir] - ts0[dir]; + pps = boudary * 1000 / (iv_time / 1000); + prts[dir]++; + /* pdev->stats.intrs is reset and re-count from 0. */ + if (intrs > pdev->stats.intrs) { + intrs = 0; + } + if (pps <= boudary || prts[dir] * boudary >= pps) { + printk(KERN_CRIT "%s - limit: %d pps, %dK pkts time: %d usec, " + "rate: %d pps, intrs: %llu\n", + dir == PDMA_Q_RX ? "Rx" : "Tx", + dir == PDMA_Q_RX ? rx_rate_limit : -1, (boudary / 1000), + iv_time, pps, pdev->stats.intrs - intrs); + prts[dir] = 0; + } + pkts[dir] = 0; + } +} + +/*! + * Read 32-bit register callback + */ +static int +ngknet_dev_read32(struct pdma_dev *dev, uint32_t addr, uint32_t *data) +{ + *data = ngbde_kapi_pio_read32(dev->unit, addr); + + return 0; +} + +/*! + * Write 32-bit register callback + */ +static int +ngknet_dev_write32(struct pdma_dev *dev, uint32_t addr, uint32_t data) +{ + ngbde_kapi_pio_write32(dev->unit, addr, data); + + return 0; +} + +/*! + * Set Rx HW timestamping. + */ +static int +ngknet_ptp_rx_hwts_set(struct net_device *ndev, struct sk_buff *skb) +{ + struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); + uint64_t ts = 0; + int rv; + + rv = ngknet_ptp_rx_hwts_get(ndev, skb, &ts); + if (SHR_FAILURE(rv) || !ts) { + return SHR_E_FAIL; + } + + memset(shhwtstamps, 0, sizeof(*shhwtstamps)); + shhwtstamps->hwtstamp = ns_to_ktime(ts); + + return SHR_E_NONE; +} + +/*! + * \brief Process Rx packet. + * + * Add RCPU encapsulation or strip matadata if needed + * + * \param [in] ndev Network device structure point. + * \param [in] oskb Rx packet SKB. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +ngknet_rx_frame_process(struct net_device *ndev, struct sk_buff **oskb) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + struct pdma_dev *pdev = &dev->pdma_dev; + struct sk_buff *skb = *oskb; + struct ngknet_rcpu_hdr *rch = (struct ngknet_rcpu_hdr *)skb->data; + struct pkt_hdr *pkh = (struct pkt_hdr *)skb->data; + uint8_t meta_len = pkh->meta_len; + uint8_t fcs_len = pdev->flags & PDMA_NO_FCS ? 0 : ETH_FCS_LEN; + + /* Remove FCS from packet length */ + skb_trim(skb, skb->len - fcs_len); + pkh->data_len -= fcs_len; + + if (priv->netif.flags & NGKNET_NETIF_F_RCPU_ENCAP) { + /* Set up RCPU header */ + memcpy(skb->data, skb->data + PKT_HDR_SIZE + meta_len, 2 * ETH_ALEN); + if (*(uint32_t *)&dev->rcpu_ctrl.dst_mac[0] != 0 || + *(uint16_t *)&dev->rcpu_ctrl.dst_mac[4] != 0) { + memcpy(rch->dst_mac, dev->rcpu_ctrl.dst_mac, ETH_ALEN); + } + if (*(uint32_t *)&dev->rcpu_ctrl.src_mac[0] != 0 || + *(uint16_t *)&dev->rcpu_ctrl.src_mac[4] != 0) { + memcpy(rch->src_mac, dev->rcpu_ctrl.src_mac, ETH_ALEN); + } + rch->vlan_tpid = htons(dev->rcpu_ctrl.vlan_tpid); + rch->vlan_tci = htons(dev->rcpu_ctrl.vlan_tci); + rch->eth_type = htons(dev->rcpu_ctrl.eth_type); + rch->pkt_sig = htons(dev->rcpu_ctrl.pkt_sig); + rch->op_code = RCPU_OPCODE_RX; + rch->flags = RCPU_FLAG_MODHDR; + rch->trans_id = htons(dev->rcpu_ctrl.trans_id); + rch->data_len = htons(pkh->data_len); + } else { + /* Remove packet header and meta data */ + skb_pull(skb, PKT_HDR_SIZE + meta_len); + } + + /* Do Rx timestamping */ + if (priv->hwts_rx_filter) { + ngknet_ptp_rx_hwts_set(ndev, skb); + } + + /* Optional callback handle */ + if (dev->cbc->rx_cb) { + struct ngknet_callback_desc *cbd = NGKNET_SKB_CB(skb); + cbd->dinfo = &dev->dev_info; + cbd->netif = &priv->netif; + cbd->net_dev = priv->net_dev; + + if (priv->netif.flags & NGKNET_NETIF_F_RCPU_ENCAP) { + cbd->pmd = skb->data + PKT_HDR_SIZE; + cbd->pkt_len = ntohs(rch->data_len); + } else { + cbd->pmd = skb->data - meta_len; + cbd->pkt_len = pkh->data_len; + } + cbd->pmd_len = meta_len; + skb = dev->cbc->rx_cb(skb); + if (!skb) { + *oskb = NULL; + return SHR_E_UNAVAIL; + } + if (priv->netif.flags & NGKNET_NETIF_F_RCPU_ENCAP) { + rch = (struct ngknet_rcpu_hdr *)skb->data; + rch->data_len = htons(skb->len - PKT_HDR_SIZE - meta_len); + } + } + + /* Update SKB pointer */ + *oskb = skb; + + return SHR_E_NONE; +} + +/*! + * Get network interface status. + */ +static bool +ngknet_netif_ok(struct net_device *ndev) +{ + return (netif_carrier_ok(ndev) && netif_running(ndev)); +} + +/*! + * \brief Network interface Rx function. + * + * After processing the packet, send it up to network stack. + * + * \param [in] ndev Network device structure point. + * \param [in] skb Rx packet SKB. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +ngknet_netif_recv(struct net_device *ndev, struct sk_buff *skb) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + struct pkt_hdr *pkh = (struct pkt_hdr *)skb->data; + uint16_t proto; + int rv; + + /* Handle one incoming packet */ + rv = ngknet_rx_frame_process(ndev, &skb); + if (!skb) { + return SHR_E_NONE; + } + if (SHR_FAILURE(rv)) { + return rv; + } + + DBG_VERB(("Rx packet sent up to ndev%d (%d bytes).\n", + priv->netif.id, skb->len)); + if (debug & DBG_LVL_PDMP) { + ngknet_pkt_dump(skb->data, skb->len); + } + + if (ndev->features & NETIF_F_RXCSUM) { + if ((pkh->attrs & (PDMA_RX_TU_CSUM | PDMA_RX_IP_CSUM)) == + (PDMA_RX_TU_CSUM | PDMA_RX_IP_CSUM)) { + skb->ip_summed = CHECKSUM_UNNECESSARY; + } else { + skb_checksum_none_assert(skb); + } + } + + proto = eth_type_trans(skb, ndev); + if (priv->netif.flags & NGKNET_NETIF_F_RCPU_ENCAP) { + skb->protocol = htons(dev->rcpu_ctrl.eth_type); + } else if (!(pkh->attrs & PDMA_RX_SET_PROTO) || !skb->protocol) { + skb->protocol = proto; + } + + skb_record_rx_queue(skb, pkh->queue_id); + + /* Update accounting */ + priv->stats.rx_packets++; + priv->stats.rx_bytes += skb->len; + + netif_receive_skb(skb); + + /* Rate limit */ + if (rx_rate_limit >= 0) { + if (!ngknet_rx_rate_limit_started()) { + ngknet_rx_rate_limit_start(dev); + } + ngknet_rx_rate_limit(dev, rx_rate_limit); + } + + return SHR_E_NONE; +} + +/*! + * \brief Packet Rx callback. + * + * Take over the control of SKB and send packet to network interface. + * + * \param [in] ndev Network device structure point. + * \param [in] skb Rx packet SKB. + */ +static void +ngknet_pkt_recv(struct net_device *ndev, struct sk_buff *skb) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + unsigned long flags; + + /* Send the packet to network interface */ + if (ngknet_netif_ok(ndev)) { + if (SHR_FAILURE(ngknet_netif_recv(ndev, skb))) { + dev_kfree_skb_any(skb); + if (!netif_queue_stopped(ndev)) { + priv->stats.rx_dropped++; + } + } + } else { + dev_kfree_skb_any(skb); + } + + spin_lock_irqsave(&dev->lock, flags); + priv->users--; + if (!priv->users && priv->wait) { + wake_up(&dev->wq); + } + spin_unlock_irqrestore(&dev->lock, flags); +} + +/*! + * \brief Driver Rx callback. + * + * After processing the packet, send it up to network stack. + * + * \param [in] pdev Packet DMA device structure point. + * \param [in] buf Raw Rx buffer. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +ngknet_frame_recv(struct pdma_dev *pdev, int queue, void *buf) +{ + struct ngknet_dev *dev = (struct ngknet_dev *)pdev->priv; + struct sk_buff *skb = (struct sk_buff *)buf; + int rv; + + DBG_VERB(("Rx packet (%d bytes).\n", skb->len)); + if (debug & DBG_LVL_PDMP) { + ngknet_pkt_dump(skb->data, skb->len); + } + + DBG_NDEV(("Valid virtual network devices: %ld.\n", (long)dev->vdev[0])); + + /* Go through the filters and process it. */ + rv = ngknet_rx_pkt_filter(dev, skb); + if (SHR_FAILURE(rv)) { + return rv; + } + + /* Measure speed */ + if (debug & DBG_LVL_RATE) { + ngknet_pkt_stats(pdev, PDMA_Q_RX); + } + + return rv; +} + +/*! + * Set Tx HW timestamping. + */ +static int +ngknet_ptp_tx_hwts_set(struct net_device *ndev, struct sk_buff *skb) +{ + struct skb_shared_hwtstamps shhwtstamps; + uint64_t ts = 0; + int rv; + + rv = ngknet_ptp_tx_hwts_get(ndev, skb, &ts); + if (SHR_FAILURE(rv) || !ts) { + return SHR_E_FAIL; + } + + memset(&shhwtstamps, 0, sizeof(shhwtstamps)); + shhwtstamps.hwtstamp = ns_to_ktime(ts); + skb_tstamp_tx(skb, &shhwtstamps); + + return SHR_E_NONE; +} + +/*! + * PTP Tx worker. + */ +static void +ngknet_ptp_tx_work(struct work_struct *work) +{ + struct ngknet_dev *dev = container_of(work, struct ngknet_dev, ptp_tx_work); + struct sk_buff *skb; + int rv; + + while (skb_queue_len(&dev->ptp_tx_queue)) { + skb = skb_dequeue(&dev->ptp_tx_queue); + rv = ngknet_ptp_tx_hwts_set(dev->net_dev, skb); + if (SHR_FAILURE(rv)) { + printk("Timestamp value has not been set for current skb.\n"); + } + dev_kfree_skb_any(skb); + } +} + +/*! + * Config Tx metadata for HW timestamping. + */ +static int +ngknet_ptp_tx_config(struct net_device *ndev, struct sk_buff *skb) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + uint64_t *tx_ts = (uint64_t *)skb->cb; + int rv; + + if (priv->netif.type == NGKNET_NETIF_T_PORT || + priv->netif.type == NGKNET_NETIF_T_META) { + rv = ngknet_ptp_tx_meta_set(ndev, skb); + if (SHR_FAILURE(rv)) { + return rv; + } + } else if (priv->hwts_tx_type != HWTSTAMP_TX_ONESTEP_SYNC) { + return SHR_E_UNAVAIL; + } + + /* For 1step meta_set will populate the TX timestamp for + * the required PTP packets (i.e. DELAY_REQ), only in such + * case we should schedule ptp_tx_work for the TX timestamp + * to be sent back on the socket. + */ + if (priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC && + *tx_ts == 0) { + return SHR_E_NONE; + } + + skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; + + if (priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC) { + skb_queue_tail(&dev->ptp_tx_queue, skb_get(skb)); + schedule_work(&dev->ptp_tx_work); + } + + return SHR_E_NONE; +} + +/*! + * \brief Process Tx packet. + * + * Strip RCPU encapsulation, setup CNET packet buffer, add vlan tag + * or pad the packet. + * + * \param [in] ndev Network device structure point. + * \param [in] oskb Tx packet SKB. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +ngknet_tx_frame_process(struct net_device *ndev, struct sk_buff **oskb) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + struct pdma_dev *pdev = &dev->pdma_dev; + struct sk_buff *skb = *oskb; + struct ngknet_rcpu_hdr *rch = (struct ngknet_rcpu_hdr *)skb->data; + struct pkt_hdr *pkh = (struct pkt_hdr *)skb->data; + struct sk_buff *nskb = NULL; + char *data = NULL; + uint32_t copy_len, meta_len, data_len, pkt_len, tag_len, pad_len; + uint16_t fcs_len = pdev->flags & PDMA_NO_FCS ? 0 : ETH_FCS_LEN; + uint16_t tpid; + + /* Set up packet header */ + if (priv->netif.flags & NGKNET_NETIF_F_RCPU_ENCAP) { + /* RCPU encapsulation packet */ + data_len = pkh->attrs & PDMA_TX_HDR_COOKED ? + pkh->data_len - fcs_len : ntohs(rch->data_len); + pkt_len = PKT_HDR_SIZE + rch->meta_len + data_len; + if (skb->len != pkt_len || skb->len < (PKT_HDR_SIZE + ETH_HLEN)) { + DBG_WARN(("Tx drop: Invalid packet length\n")); + return SHR_E_PARAM; + } + if (dev->rcpu_ctrl.pkt_sig && dev->rcpu_ctrl.pkt_sig != ntohs(rch->pkt_sig)) { + DBG_WARN(("Tx drop: Invalid packet signature\n")); + return SHR_E_PARAM; + } + if (pkh->attrs & PDMA_TX_HDR_COOKED) { + /* Resumed packet */ + return SHR_E_NONE; + } + pkh->data_len = data_len + fcs_len; + pkh->meta_len = rch->meta_len; + pkh->attrs = 0; + if (rch->flags & RCPU_FLAG_MODHDR) { + pkh->attrs |= PDMA_TX_HIGIG_PKT; + } + if (rch->flags & RCPU_FLAG_PAUSE) { + pkh->attrs |= PDMA_TX_PAUSE_PKT; + } + if (rch->flags & RCPU_FLAG_PURGE) { + pkh->attrs |= PDMA_TX_PURGE_PKT; + } + if (rch->flags & RCPU_FLAG_BIND_QUE) { + pkh->attrs |= PDMA_TX_BIND_QUE; + } + if (rch->flags & RCPU_FLAG_NO_PAD) { + pkh->attrs |= PDMA_TX_NO_PAD; + } + if (rch->flags & RCPU_FLAG_DATA_RAW) { + pkh->attrs |= PDMA_TX_DATA_RAW; + } + } else { + /* Non-RCPU encapsulation packet */ + data_len = pkh->data_len - fcs_len; + pkt_len = PKT_HDR_SIZE + pkh->meta_len + data_len; + if (skb->len == pkt_len && pkh->attrs & PDMA_TX_HDR_COOKED && + pkh->pkt_sig == dev->rcpu_ctrl.pkt_sig) { + /* Resumed packet */ + return SHR_E_NONE; + } + meta_len = 0; + if (priv->netif.type == NGKNET_NETIF_T_PORT || + priv->netif.type == NGKNET_NETIF_T_META) { + meta_len = priv->netif.meta_len; + if (!meta_len) { + printk("Tx abort: no metadata\n"); + return SHR_E_UNAVAIL; + } + } + if (skb_header_cloned(skb) || + skb_headroom(skb) < (PKT_HDR_SIZE + meta_len + VLAN_HLEN) || + skb_tailroom(skb) < fcs_len) { + nskb = skb_copy_expand(skb, PKT_HDR_SIZE + meta_len + VLAN_HLEN, + fcs_len, GFP_ATOMIC); + if (!nskb) { + return SHR_E_MEMORY; + } + skb_shinfo(nskb)->tx_flags = skb_shinfo(skb)->tx_flags; + nskb->sk = skb->sk; + skb = nskb; + } + skb_push(skb, PKT_HDR_SIZE + meta_len); + memset(skb->data, 0, PKT_HDR_SIZE + meta_len); + pkh = (struct pkt_hdr *)skb->data; + pkh->data_len = skb->len - PKT_HDR_SIZE - meta_len + fcs_len; + pkh->meta_len = meta_len; + pkh->attrs = 0; + if (priv->netif.type == NGKNET_NETIF_T_PORT || + priv->netif.type == NGKNET_NETIF_T_META) { + /* Send to physical port using netif metadata */ + if (priv->netif.meta_off) { + memmove(skb->data + PKT_HDR_SIZE, + skb->data + PKT_HDR_SIZE + meta_len, + priv->netif.meta_off); + } + memcpy(skb->data + PKT_HDR_SIZE + priv->netif.meta_off, + priv->netif.meta_data, priv->netif.meta_len); + pkh->attrs |= PDMA_TX_HIGIG_PKT; + } + pkh->pkt_sig = dev->rcpu_ctrl.pkt_sig; + } + + /* Packet header done here */ + pkh->attrs |= PDMA_TX_HDR_COOKED; + + data = skb->data + PKT_HDR_SIZE + pkh->meta_len; + tpid = data[12] << 8 | data[13]; + tag_len = (tpid == ETH_P_8021Q || tpid == ETH_P_8021AD) ? VLAN_HLEN : 0; + + /* Need to add VLAN tag if packet is untagged */ + if (tag_len == 0 && (priv->netif.vlan & 0xfff) != 0 && + (!(pkh->attrs & PDMA_TX_HIGIG_PKT) || + priv->netif.flags & NGKNET_NETIF_F_ADD_TAG) && !(pkh->attrs & PDMA_TX_DATA_RAW)) { + copy_len = PKT_HDR_SIZE + pkh->meta_len + 2 * ETH_ALEN; + if (skb_header_cloned(skb) || skb_headroom(skb) < VLAN_HLEN) { + nskb = skb_copy_expand(skb, VLAN_HLEN, 0, GFP_ATOMIC); + if (!nskb) { + return SHR_E_MEMORY; + } + skb_shinfo(nskb)->tx_flags = skb_shinfo(skb)->tx_flags; + nskb->sk = skb->sk; + skb = nskb; + } + skb_push(skb, VLAN_HLEN); + memmove(skb->data, skb->data + VLAN_HLEN, copy_len); + pkh = (struct pkt_hdr *)skb->data; + data = skb->data + PKT_HDR_SIZE + pkh->meta_len; + data[12] = 0x81; + data[13] = 0x00; + data[14] = priv->netif.vlan >> 8 & 0xf; + data[15] = priv->netif.vlan & 0xff; + pkh->data_len += VLAN_HLEN; + tag_len = VLAN_HLEN; + } + + /* Optional callback handle */ + if (dev->cbc->tx_cb) { + struct ngknet_callback_desc *cbd = NGKNET_SKB_CB(skb); + cbd->dinfo = &dev->dev_info; + cbd->netif = &priv->netif; + cbd->pmd = skb->data + PKT_HDR_SIZE; + cbd->pmd_len = pkh->meta_len; + cbd->pkt_len = skb->len - PKT_HDR_SIZE - pkh->meta_len; + skb = dev->cbc->tx_cb(skb); + if (!skb) { + if (!nskb) { + *oskb = NULL; + } + return SHR_E_UNAVAIL; + } + pkh = (struct pkt_hdr *)skb->data; + pkh->data_len = skb->len - PKT_HDR_SIZE - pkh->meta_len + fcs_len; + } + + /* Pad packet if needed */ + pad_len = ETH_ZLEN + tag_len + fcs_len; + if (pkh->data_len < pad_len && !(pkh->attrs & PDMA_TX_NO_PAD)) { + pkh->data_len = pad_len; + if (skb_padto(skb, + PKT_HDR_SIZE + pkh->meta_len + pkh->data_len - fcs_len)) { + if (!nskb) { + *oskb = NULL; + } + return SHR_E_MEMORY; + } + } + + /* Update SKB pointer */ + *oskb = skb; + + return SHR_E_NONE; +} + +/*! + * Network device detach callback + */ +static void +ngknet_ndev_detach(struct pdma_dev *pdev) +{ + struct ngknet_dev *dev = (struct ngknet_dev *)pdev->priv; + int vdi; + + netif_tx_lock(dev->net_dev); + netif_device_detach(dev->net_dev); + netif_tx_unlock(dev->net_dev); + + for (vdi = 1; vdi <= NUM_VDEV_MAX; vdi++) { + if (!dev->vdev[vdi]) { + continue; + } + netif_tx_lock(dev->vdev[vdi]); + netif_device_detach(dev->vdev[vdi]); + netif_tx_unlock(dev->vdev[vdi]); + } +} + +/*! + * Network device attach callback + */ +static void +ngknet_ndev_attach(struct pdma_dev *pdev) +{ + struct ngknet_dev *dev = (struct ngknet_dev *)pdev->priv; + int vdi; + + netif_tx_lock(dev->net_dev); + netif_device_attach(dev->net_dev); + netif_tx_unlock(dev->net_dev); + + for (vdi = 1; vdi <= NUM_VDEV_MAX; vdi++) { + if (!dev->vdev[vdi]) { + continue; + } + netif_tx_lock(dev->vdev[vdi]); + netif_device_attach(dev->vdev[vdi]); + netif_tx_unlock(dev->vdev[vdi]); + } +} + +/*! + * Suspend Tx queue callback + */ +static void +ngknet_tx_suspend(struct pdma_dev *pdev, int queue) +{ + struct ngknet_dev *dev = (struct ngknet_dev *)pdev->priv; + unsigned long flags; + int vdi; + + netif_stop_subqueue(dev->net_dev, queue); + + spin_lock_irqsave(&dev->lock, flags); + for (vdi = 1; vdi <= NUM_VDEV_MAX; vdi++) { + if (!dev->vdev[vdi]) { + continue; + } + netif_stop_subqueue(dev->vdev[vdi], queue); + } + spin_unlock_irqrestore(&dev->lock, flags); +} + +/*! + * Resume Tx queue callback + */ +static void +ngknet_tx_resume(struct pdma_dev *pdev, int queue) +{ + struct ngknet_dev *dev = (struct ngknet_dev *)pdev->priv; + unsigned long flags; + int vdi; + + if (__netif_subqueue_stopped(dev->net_dev, queue)) { + netif_wake_subqueue(dev->net_dev, queue); + } + + spin_lock_irqsave(&dev->lock, flags); + for (vdi = 1; vdi <= NUM_VDEV_MAX; vdi++) { + if (!dev->vdev[vdi]) { + continue; + } + if (__netif_subqueue_stopped(dev->vdev[vdi], queue)) { + netif_wake_subqueue(dev->vdev[vdi], queue); + } + } + spin_unlock_irqrestore(&dev->lock, flags); + + if (pdev->mode == DEV_MODE_HNET) { + atomic_set(&dev->hnet_active, 1); + wake_up_interruptible(&dev->hnet_wq); + } +} + +/*! + * Enable interrupt callback + */ +static void +ngknet_intr_enable(struct pdma_dev *pdev, int cmc, int chan, + uint32_t reg, uint32_t val) +{ + if (val) { + ngbde_kapi_iio_write32(pdev->unit, reg, val); + } else { + ngbde_kapi_intr_mask_write(pdev->unit, 0, reg, pdev->ctrl.grp[cmc].irq_mask); + } +} + +/*! + * Disable interrupt callback + */ +static void +ngknet_intr_disable(struct pdma_dev *pdev, int cmc, int chan, + uint32_t reg, uint32_t val) +{ + if (val) { + ngbde_kapi_iio_write32(pdev->unit, reg, val); + } else { + ngbde_kapi_intr_mask_write(pdev->unit, 0, reg, pdev->ctrl.grp[cmc].irq_mask); + } +} + +/*! + * NAPI polling function + */ +static int +ngknet_poll(struct napi_struct *napi, int budget) +{ + struct ngknet_intr_handle *kih = (struct ngknet_intr_handle *)napi; + struct intr_handle *hdl = kih->hdl; + struct pdma_dev *pdev = (struct pdma_dev *)hdl->dev; + struct ngknet_dev *dev = (struct ngknet_dev *)pdev->priv; + unsigned long flags; + int work_done; + + DBG_NAPI(("Scheduled NAPI on queue %d.\n", hdl->queue)); + + kih->napi_pending = 0; + + if (pdev->flags & PDMA_GROUP_INTR) { + work_done = bcmcnet_group_poll(pdev, hdl->group, budget); + } else { + if (!kih->napi_resched) { + bcmcnet_queue_intr_ack(pdev, hdl); + } + work_done = bcmcnet_queue_poll(pdev, hdl, budget); + } + + if (work_done < budget) { + kih->napi_resched = 0; + napi_complete(napi); + if (kih->napi_pending && napi_schedule_prep(napi)) { + kih->napi_resched = 1; + __napi_schedule(napi); + return work_done; + } + spin_lock_irqsave(&dev->lock, flags); + if (pdev->flags & PDMA_GROUP_INTR) { + bcmcnet_group_intr_enable(pdev, hdl->group); + } else { + bcmcnet_queue_intr_enable(pdev, hdl); + } + spin_unlock_irqrestore(&dev->lock, flags); + } + + return work_done; +} + +/*! + * NGKNET ISR + */ +static int +ngknet_isr(void *isr_data) +{ + struct ngknet_dev *dev = isr_data; + struct pdma_dev *pdev = &dev->pdma_dev; + struct intr_handle *hdl = NULL; + struct napi_struct *napi = NULL; + unsigned long bm_queue; + unsigned long flags; + int gi, qi; + int iv = 0; + + for (gi = 0; gi < pdev->num_groups; gi++) { + if (!pdev->ctrl.grp[gi].attached) { + continue; + } + bm_queue = pdev->ctrl.grp[gi].bm_rxq | pdev->ctrl.grp[gi].bm_txq; + for (qi = 0; qi < pdev->grp_queues; qi++) { + if (!(pdev->flags & PDMA_GROUP_INTR) && !(1 << qi & bm_queue)) { + continue; + } + hdl = &pdev->ctrl.grp[gi].intr_hdl[qi]; + if (pdev->flags & PDMA_GROUP_INTR) { + if (!bcmcnet_group_intr_check(pdev, gi)) { + break; + } + } else { + if (!bcmcnet_queue_intr_check(pdev, hdl)) { + continue; + } + } + spin_lock_irqsave(&dev->lock, flags); + if (pdev->flags & PDMA_GROUP_INTR) { + bcmcnet_group_intr_disable(pdev, gi); + } else { + bcmcnet_queue_intr_disable(pdev, hdl); + } + spin_unlock_irqrestore(&dev->lock, flags); + napi = (struct napi_struct *)hdl->priv; + if (likely(napi_schedule_prep(napi))) { + __napi_schedule(napi); + } + iv++; + if (pdev->flags & PDMA_GROUP_INTR) { + break; + } + } + } + + if (iv) { + DBG_IRQ(("Got interrupt on device %d.\n", dev->dev_info.dev_no)); + pdev->stats.intrs++; + return IRQ_HANDLED; + } else { + return IRQ_NONE; + } +} + +/*! + * Hypervisor network work handler + */ +static void +ngknet_dev_hnet_work(struct pdma_dev *pdev) +{ + struct intr_handle *hdl = NULL; + struct napi_struct *napi = NULL; + struct ngknet_intr_handle *kih = NULL; + unsigned long bm_queue; + int gi, qi; + + for (gi = 0; gi < pdev->num_groups; gi++) { + if (!pdev->ctrl.grp[gi].attached) { + continue; + } + bm_queue = pdev->ctrl.grp[gi].bm_rxq | pdev->ctrl.grp[gi].bm_txq; + for (qi = 0; qi < pdev->grp_queues; qi++) { + if (!(pdev->flags & PDMA_GROUP_INTR) && !(1 << qi & bm_queue)) { + continue; + } + hdl = &pdev->ctrl.grp[gi].intr_hdl[qi]; + napi = (struct napi_struct *)hdl->priv; + kih = (struct ngknet_intr_handle *)napi; + kih->napi_pending = 1; + if (napi_schedule_prep(napi)) { + kih->napi_resched = 1; + local_bh_disable(); + __napi_schedule(napi); + local_bh_enable(); + } + if (pdev->flags & PDMA_GROUP_INTR) { + break; + } + } + } +} + +/*! + * Hypervisor network wait handler + */ +static int +ngknet_dev_hnet_wait(struct pdma_dev *pdev) +{ + struct ngknet_dev *dev = (struct ngknet_dev *)pdev->priv; + uint32_t bmp; + int budget, qi; + + while (!kthread_should_stop()) { + wait_event_interruptible(dev->hnet_wq, + atomic_read(&dev->hnet_active) != 0); + if (!(dev->flags & NGKNET_DEV_ACTIVE)) { + schedule_timeout(HZ); + continue; + } + atomic_set(&dev->hnet_active, 0); + + schedule_work(&dev->hnet_work); + + do { + bmp = 0x0; + for (qi = 0; qi < pdev->ctrl.nb_txq; qi++) { + bmp |= 1 << qi; + budget = pdev->ctrl.budget; + while (budget--) { + if (SHR_FAILURE(pdev->pkt_xmit(pdev, qi, 0))) { + bmp &= ~(1 << qi); + break; + } + } + } + } while (bmp); + } + + return 0; +} + +/*! + * Hypervisor network wake handler + */ +static int +ngknet_dev_vnet_wake(struct pdma_dev *pdev) +{ + struct ngknet_dev *dev = (struct ngknet_dev *)pdev->priv; + + if (atomic_read(&dev->vnet_active) != 1) { + atomic_set(&dev->vnet_active, 1); + wake_up_interruptible(&dev->vnet_wq); + } + + return SHR_E_NONE; +} + +/*! + * Hypervisor network process + */ +static int +ngknet_dev_hnet_process(void *data) +{ + return ngknet_dev_hnet_wait((struct pdma_dev *)data); +} + +/*! + * Hypervisor network schedule + */ +static void +ngknet_dev_hnet_schedule(struct work_struct *work) +{ + struct ngknet_dev *dev = container_of(work, struct ngknet_dev, hnet_work); + + ngknet_dev_hnet_work(&dev->pdma_dev); +} + +/*! + * Convert physical address to virtual address + */ +static void * +ngknet_sys_p2v(struct pdma_dev *pdev, uint64_t paddr) +{ + return ngbde_kapi_dma_bus_to_virt(pdev->unit, (dma_addr_t)paddr); +} + +/*! + * Convert virtual address to physical address + */ +static uint64_t +ngknet_sys_v2p(struct pdma_dev *pdev, void *vaddr) +{ + return (uint64_t)ngbde_kapi_dma_virt_to_bus(pdev->unit, vaddr); +} + +/*! + * Open network device + */ +static int +ngknet_enet_open(struct net_device *ndev) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + struct pdma_dev *pdev = &dev->pdma_dev; + struct napi_struct *napi = NULL; + unsigned long bm_queue; + int gi, qi; + int rv; + + if (!pdev->ctrl.bm_rxq || !pdev->ctrl.bm_txq) { + printk("Not config Rx or Tx queue yet!\n"); + return -EPERM; + } + + if (priv->netif.id <= 0) { + /* Register interrupt handler */ + ngbde_kapi_intr_connect(dev->dev_info.dev_no, 0, ngknet_isr, dev); + + /* Start PDMA device */ + rv = bcmcnet_pdma_dev_start(pdev); + if (SHR_FAILURE(rv)) { + ngbde_kapi_intr_disconnect(dev->dev_info.dev_no, 0); + return -EPERM; + } + + /* Start rate limit */ + if (rx_rate_limit >= 0) { + ngknet_rx_rate_limit_start(dev); + } + + /* Notify the stack of the actual queue counts. */ + rv = netif_set_real_num_rx_queues(dev->net_dev, pdev->ctrl.nb_rxq); + if (rv < 0) { + ngbde_kapi_intr_disconnect(dev->dev_info.dev_no, 0); + return rv; + } + rv = netif_set_real_num_tx_queues(dev->net_dev, pdev->ctrl.nb_txq); + if (rv < 0) { + ngbde_kapi_intr_disconnect(dev->dev_info.dev_no, 0); + return rv; + } + + for (gi = 0; gi < pdev->num_groups; gi++) { + if (!pdev->ctrl.grp[gi].attached) { + continue; + } + bm_queue = pdev->ctrl.grp[gi].bm_rxq | pdev->ctrl.grp[gi].bm_txq; + for (qi = 0; qi < pdev->grp_queues; qi++) { + napi = (struct napi_struct *)pdev->ctrl.grp[gi].intr_hdl[qi].priv; + if (pdev->flags & PDMA_GROUP_INTR) { + napi_enable(napi); + break; + } + if (1 << qi & bm_queue) { + napi_enable(napi); + } + } + } + } else { + /* Notify the stack of the actual queue counts. */ + rv = netif_set_real_num_rx_queues(ndev, pdev->ctrl.nb_rxq); + if (rv < 0) { + return rv; + } + rv = netif_set_real_num_tx_queues(ndev, pdev->ctrl.nb_txq); + if (rv < 0) { + return rv; + } + } + + /* Prevent tx timeout */ + kal_netif_trans_update(ndev); + + netif_tx_wake_all_queues(ndev); + + return 0; +} + +/*! + * Stop network device + */ +static int +ngknet_enet_stop(struct net_device *ndev) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + struct pdma_dev *pdev = &dev->pdma_dev; + struct napi_struct *napi = NULL; + unsigned long bm_queue; + int gi, qi; + + netif_tx_stop_all_queues(ndev); + + if (priv->netif.id <= 0) { + /* Stop rate limit */ + if (rx_rate_limit >= 0) { + ngknet_rx_rate_limit_stop(dev); + } + + for (gi = 0; gi < pdev->num_groups; gi++) { + if (!pdev->ctrl.grp[gi].attached) { + continue; + } + bm_queue = pdev->ctrl.grp[gi].bm_rxq | pdev->ctrl.grp[gi].bm_txq; + for (qi = 0; qi < pdev->grp_queues; qi++) { + napi = (struct napi_struct *)pdev->ctrl.grp[gi].intr_hdl[qi].priv; + if (pdev->flags & PDMA_GROUP_INTR) { + napi_disable(napi); + break; + } + if (1 << qi & bm_queue) { + napi_disable(napi); + } + } + } + + /* Stop PDMA device */ + bcmcnet_pdma_dev_stop(pdev); + + /* Unregister interrupt handler */ + ngbde_kapi_intr_disconnect(dev->dev_info.dev_no, 0); + } + + return 0; +} + +/*! + * Start transmission + */ +static int +ngknet_start_xmit(struct sk_buff *skb, struct net_device *ndev) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + struct pdma_dev *pdev = &dev->pdma_dev; + struct sk_buff *bskb = skb; + uint32_t len = skb->len; + int queue; + int rv; + + DBG_VERB(("Tx packet from ndev%d (%d bytes).\n", priv->netif.id, skb->len)); + if (debug & DBG_LVL_PDMP) { + ngknet_pkt_dump(skb->data, skb->len); + } + + /* Do not transmit on base device */ + if (priv->netif.id <= 0) { + priv->stats.tx_dropped++; + dev_kfree_skb_any(skb); + return NETDEV_TX_OK; + } + + /* Measure speed */ + if (debug & DBG_LVL_RATE) { + ngknet_pkt_stats(pdev, PDMA_Q_TX); + } + + queue = skb->queue_mapping; + + /* Handle one outgoing packet */ + rv = ngknet_tx_frame_process(ndev, &skb); + if (SHR_FAILURE(rv)) { + priv->stats.tx_dropped++; + if (skb) { + dev_kfree_skb_any(skb); + } + return NETDEV_TX_OK; + } + + /* Schedule Tx queue */ + ngknet_tx_queue_schedule(dev, skb, &queue); + skb->queue_mapping = queue; + + DBG_VERB(("Tx packet (%d bytes).\n", skb->len)); + if (debug & DBG_LVL_PDMP) { + ngknet_pkt_dump(skb->data, skb->len); + } + + /* Do Tx timestamping */ + if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { + ngknet_ptp_tx_config(ndev, skb); + } + + skb_tx_timestamp(skb); + + rv = pdev->pkt_xmit(pdev, queue, skb); + + if (rv == SHR_E_BUSY) { + DBG_WARN(("Tx suspend: DMA device is busy and temporarily " + "unavailable.\n")); + priv->stats.tx_fifo_errors++; + if (skb != bskb) { + dev_kfree_skb_any(skb); + } + return NETDEV_TX_BUSY; + } else if (rv != SHR_E_NONE) { + DBG_WARN(("Tx drop: DMA device not ready or not supported.\n")); + priv->stats.tx_dropped++; + if (skb != bskb) { + dev_kfree_skb_any(skb); + } + dev_kfree_skb_any(bskb); + return NETDEV_TX_OK; + } else { + if (skb != bskb) { + dev_kfree_skb_any(bskb); + } + } + + /* Update accounting */ + priv->stats.tx_packets++; + priv->stats.tx_bytes += len; + + return NETDEV_TX_OK; +} + +/*! + * Get network device stats + */ +static struct net_device_stats * +ngknet_get_stats(struct net_device *ndev) +{ + struct ngknet_private *priv = netdev_priv(ndev); + + return &priv->stats; +} + +/*! + * Set network device MC list + */ +static void +ngknet_set_multicast_list(struct net_device *ndev) +{ + return; +} + +/*! + * Set network device MAC address + */ +static int +ngknet_set_mac_address(struct net_device *ndev, void *addr) +{ + if (!is_valid_ether_addr(((struct sockaddr *)addr)->sa_data)) { + return -EINVAL; + } + + netdev_info(ndev, "Setting new MAC address\n"); + eth_hw_addr_set(ndev, ((struct sockaddr *)addr)->sa_data); + + return 0; +} + +/*! + * Change network device MTU + */ +static int +ngknet_change_mtu(struct net_device *ndev, int new_mtu) +{ + int frame_size = new_mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN; + + if (frame_size < (ETH_ZLEN + ETH_FCS_LEN) || frame_size > rx_buffer_size) { + return -EINVAL; + } + + netdev_info(ndev, "Changing MTU from %d to %d\n", ndev->mtu, new_mtu); + ndev->mtu = new_mtu; + + return 0; +} + +/*! + * Do I/O control + */ +static int +ngknet_do_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct hwtstamp_config config; + int rv; + + if (cmd == SIOCSHWTSTAMP) { + if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) { + return -EFAULT; + } + + if (priv->netif.type != NGKNET_NETIF_T_PORT && + priv->netif.type != NGKNET_NETIF_T_META) { + return -ENOSYS; + } + + switch (config.tx_type) { + case HWTSTAMP_TX_OFF: + priv->hwts_tx_type = HWTSTAMP_TX_OFF; + rv = ngknet_ptp_tx_config_set(ndev, priv->hwts_tx_type); + if (SHR_FAILURE(rv)) { + return -ENOSYS; + } + break; + case HWTSTAMP_TX_ON: + priv->hwts_tx_type = HWTSTAMP_TX_ON; + rv = ngknet_ptp_tx_config_set(ndev, priv->hwts_tx_type); + if (SHR_FAILURE(rv)) { + return -ENOSYS; + } + break; + case HWTSTAMP_TX_ONESTEP_SYNC: + priv->hwts_tx_type = HWTSTAMP_TX_ONESTEP_SYNC; + rv = ngknet_ptp_tx_config_set(ndev, priv->hwts_tx_type); + if (SHR_FAILURE(rv)) { + return -ENOSYS; + } + break; + default: + return -ERANGE; + } + + switch (config.rx_filter) { + case HWTSTAMP_FILTER_NONE: + rv = ngknet_ptp_rx_config_set(ndev, &config.rx_filter); + if (SHR_FAILURE(rv)) { + return -ENOSYS; + } + priv->hwts_rx_filter = HWTSTAMP_FILTER_NONE; + break; + default: + rv = ngknet_ptp_rx_config_set(ndev, &config.rx_filter); + if (SHR_FAILURE(rv)) { + return -ENOSYS; + } + priv->hwts_rx_filter = config.rx_filter; + break; + } + + return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; + } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) + if (cmd == SIOCGHWTSTAMP) { + config.flags = 0; + config.tx_type = priv->hwts_tx_type; + config.rx_filter = priv->hwts_rx_filter; + + return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; + } +#endif + + return -EINVAL; +} + +#ifdef CONFIG_NET_POLL_CONTROLLER +/*! + * Poll network device + */ +static void +ngknet_poll_controller(struct net_device *ndev) +{ + struct ngknet_private *priv = netdev_priv(ndev); + + disable_irq(ndev->irq); + ngknet_isr(priv->bkn_dev); + enable_irq(ndev->irq); +} +#endif + +static const struct net_device_ops ngknet_netdev_ops = { + .ndo_open = ngknet_enet_open, + .ndo_stop = ngknet_enet_stop, + .ndo_start_xmit = ngknet_start_xmit, + .ndo_get_stats = ngknet_get_stats, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_rx_mode = ngknet_set_multicast_list, + .ndo_set_mac_address = ngknet_set_mac_address, + .ndo_change_mtu = ngknet_change_mtu, + .ndo_set_features = NULL, + .ndo_do_ioctl = ngknet_do_ioctl, + .ndo_tx_timeout = NULL, +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = ngknet_poll_controller, +#endif +}; + +static void +ngknet_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *drvinfo) +{ + strscpy(drvinfo->driver, "linux_ngknet", sizeof(drvinfo->driver)); + snprintf(drvinfo->version, sizeof(drvinfo->version), "%d", NGKNET_IOC_VERSION); + strscpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); + strscpy(drvinfo->bus_info, "N/A", sizeof(drvinfo->bus_info)); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)) +static int +ngknet_get_ts_info(struct net_device *ndev, struct kernel_ethtool_ts_info *info) +{ + int rv; + + info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | + SOF_TIMESTAMPING_TX_SOFTWARE | + SOF_TIMESTAMPING_RX_HARDWARE | + SOF_TIMESTAMPING_RX_SOFTWARE | + SOF_TIMESTAMPING_SOFTWARE | + SOF_TIMESTAMPING_RAW_HARDWARE; + info->tx_types = + (1 << HWTSTAMP_TX_OFF) | + (1 << HWTSTAMP_TX_ON) | + (1 << HWTSTAMP_TX_ONESTEP_SYNC); + info->rx_filters = + (1 << HWTSTAMP_FILTER_NONE) | + (1 << HWTSTAMP_FILTER_ALL); + rv = ngknet_ptp_phc_index_get(ndev, &info->phc_index); + if (SHR_FAILURE(rv)) { + info->phc_index = -1; + } + + return 0; +} +#endif + +#if NGKNET_ETHTOOL_LINK_SETTINGS +static int +ngknet_get_link_ksettings(struct net_device *ndev, + struct ethtool_link_ksettings *cmd) +{ + struct ngknet_private *priv = netdev_priv(ndev); + + cmd->base.speed = priv->link_settings.speed; + cmd->base.duplex = priv->link_settings.duplex; + + return 0; +} + +static int +ngknet_set_link_ksettings(struct net_device *ndev, + const struct ethtool_link_ksettings *cmd) +{ + struct ngknet_private *priv = netdev_priv(ndev); + + priv->link_settings.speed = cmd->base.speed; + priv->link_settings.duplex = cmd->base.speed ? DUPLEX_FULL : 0; + + return 0; +} +#endif + +static const struct ethtool_ops ngknet_ethtool_ops = { + .get_drvinfo = ngknet_get_drvinfo, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)) + .get_ts_info = ngknet_get_ts_info, +#endif +#if NGKNET_ETHTOOL_LINK_SETTINGS + .get_link_ksettings = ngknet_get_link_ksettings, + .set_link_ksettings = ngknet_set_link_ksettings, +#endif +}; + +/*! + * \brief Initialize network device. + * + * \param [in] name Network device name. + * \param [in] mac Network device MAC address. + * \param [out] nd New registered network device. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +ngknet_ndev_init(ngknet_netif_t *netif, struct net_device **nd) +{ + struct net_device *ndev = NULL; + uint8_t *ma; + int rv; + + if (!netif) { + DBG_WARN(("Network interface is NULL.\n")); + return SHR_E_PARAM; + } + if (!nd) { + DBG_WARN(("Network device is NULL.\n")); + return SHR_E_PARAM; + } + + ndev = alloc_etherdev_mq(sizeof(struct ngknet_private), NUM_Q_MAX); + if (!ndev) { + DBG_WARN(("Error allocating network device.\n")); + return SHR_E_MEMORY; + } + if (!ndev->dev_addr) { + DBG_WARN(("ndev->dev_addr is NULL\n")); + free_netdev(ndev); + return SHR_E_INTERNAL; + } + + /* Device information -- not available right now */ + ndev->irq = 0; + ndev->base_addr = 0; + + /* Fill in the dev structure */ + ndev->watchdog_timeo = 5 * HZ; + + /* Default MTU should not exceed MTU of switch front-panel ports */ + ndev->mtu = netif->mtu; + if (!ndev->mtu) { + ndev->mtu = default_mtu ? default_mtu : rx_buffer_size; + } + + /* MTU range: 32 - 9198 */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0)) + ndev->min_mtu = PKT_HDR_SIZE; /* Min 50-byte length of packet with RCPU-encap */ + ndev->max_mtu = rx_buffer_size - (ETH_HLEN + ETH_FCS_LEN); +#endif + + ndev->netdev_ops = &ngknet_netdev_ops; + ndev->ethtool_ops = &ngknet_ethtool_ops; + + /* Network device name */ + if (netif->name[0] != '\0') { + strncpy(ndev->name, netif->name, IFNAMSIZ - 1); + } + + /* Set the device MAC address */ + ma = netif->macaddr; + if ((ma[0] | ma[1] | ma[2] | ma[3] | ma[4] | ma[5]) == 0) { + ngknet_dev_mac[5]++; + if (ngknet_dev_mac[5] == 0) { + ngknet_dev_mac[4]++; + } + ma = ngknet_dev_mac; + } + eth_hw_addr_set(ndev, ma); + + /* Initialize the device features */ + ndev->hw_features = NETIF_F_RXCSUM | + NETIF_F_HW_VLAN_CTAG_RX | + NETIF_F_HW_VLAN_CTAG_TX; + ndev->features = NETIF_F_RXCSUM | + NETIF_F_HIGHDMA | + NETIF_F_HW_VLAN_CTAG_RX; + + /* Register the kernel network device */ + rv = register_netdev(ndev); + if (rv < 0) { + DBG_WARN(("Error registering network device %s.\n", ndev->name)); + free_netdev(ndev); + return SHR_E_FAIL; + } + + *nd = ndev; + + /*DBG_VERB(("Created network device %s.\n", ndev->name));*/ + + return SHR_E_NONE; +} + +static int +ngknet_dev_remove(int dn); + +static int +ngknet_bde_event_handler(int kdev, int event, void *data) +{ + DBG_VERB(("%s: callback from BDE with kdev(%d) event(%d).\n", + __FUNCTION__, kdev, event)); + + if (event == NGBDE_EVENT_DEV_REMOVE) { + ngknet_dev_remove(kdev); + } + + return SHR_E_NONE; +} + +/*! + * \brief Initialize Packet DMA device. + * + * \param [in] dev NGKNET device structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +ngknet_pdev_init(struct ngknet_dev *dev) +{ + struct pdma_dev *pdev = &dev->pdma_dev; + int rv; + + /* Initialize PDMA control structure */ + pdev->unit = dev->dev_info.dev_no; + pdev->priv = dev; + pdev->ctrl.dev = pdev; + pdev->ctrl.hw_addr = dev->base_addr; + pdev->ctrl.rx_buf_size = rx_buffer_size; + + /* Hook callbacks */ + pdev->dev_read32 = ngknet_dev_read32; + pdev->dev_write32 = ngknet_dev_write32; + pdev->pkt_recv = ngknet_frame_recv; + pdev->ndev_detach = ngknet_ndev_detach; + pdev->ndev_attach = ngknet_ndev_attach; + pdev->tx_suspend = ngknet_tx_suspend; + pdev->tx_resume = ngknet_tx_resume; + pdev->intr_unmask = ngknet_intr_enable; + pdev->intr_mask = ngknet_intr_disable; + pdev->xnet_wait = ngknet_dev_hnet_wait; + pdev->xnet_wake = ngknet_dev_vnet_wake; + pdev->sys_p2v = ngknet_sys_p2v; + pdev->sys_v2p = ngknet_sys_v2p; + + if (tx_polling) { + pdev->flags |= PDMA_TX_POLLING; + } + if (rx_batching || pdev->mode == DEV_MODE_HNET) { + pdev->flags |= PDMA_RX_BATCHING; + } + + /* Attach PDMA driver */ + rv = drv_ops[pdev->dev_type]->drv_attach(pdev); + if (SHR_FAILURE(rv)) { + DBG_WARN(("Attach DMA driver failed.\n")); + return rv; + } + + /* Initialize PDMA device */ + rv = bcmcnet_pdma_dev_init(pdev); + if (SHR_FAILURE(rv)) { + DBG_WARN(("Init DMA device.failed.\n")); + return rv; + } + + DBG_VERB(("Attached DMA device %s.\n", pdev->name)); + + return SHR_E_NONE; +} + +/*! + * \brief Get device information from BDE. + * + * \param [in] dn Device number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +ngknet_dev_info_get(int dn) +{ + struct ngknet_dev *dev = &ngknet_devices[dn]; + + dev->base_addr = ngbde_kapi_pio_membase(dn); + dev->dev = ngbde_kapi_dma_dev_get(dn); + + if (!dev->base_addr || !dev->dev) { + return SHR_E_ACCESS; + } + + dev->dev_info.dev_no = dn; + strscpy(dev->dev_info.type_str, drv_ops[dev->pdma_dev.dev_type]->drv_desc, + sizeof(dev->dev_info.type_str)); + dev->dev_info.vdev = dev->vdev; + return SHR_E_NONE; +} + +/*! + * \brief Probe device. + * + * Get the information from BDE, initialize Packet DMA device, + * initialize base network device and allocate other resources. + * + * \param [in] dn Device number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +ngknet_dev_probe(int dn, ngknet_netif_t *netif) +{ + struct ngknet_dev *dev = &ngknet_devices[dn]; + struct pdma_dev *pdev = &dev->pdma_dev; + struct net_device *ndev = NULL; + struct ngknet_private *priv = NULL; + struct intr_handle *hdl = NULL; + struct cpumask mask; + int gi, qi; + int rv; + + DBG_VERB(("%s: dev %d\n",__FUNCTION__, dn)); + + /* Get device information */ + rv = ngknet_dev_info_get(dn); + if (SHR_FAILURE(rv)) { + return rv; + } + + /* Initialize PDMA device */ + rv = ngknet_pdev_init(dev); + if (SHR_FAILURE(rv)) { + return rv; + } + + /* Get base network device name */ + if (netif->name[0] == '\0') { + /* Reserve 6 vacancies for base&vitual device number, i.e. nameAB_XYZ */ + if (strlen(base_dev_name) < IFNAMSIZ - 6) { + snprintf(netif->name, IFNAMSIZ, "%s%d", base_dev_name, dn); + } else { + DBG_WARN(("Too long network device name: %s.\n", base_dev_name)); + return SHR_E_PARAM; + } + } + + if (netif->chan >= NUM_Q_MAX) { + DBG_WARN(("Exceed max number of queues : %d.\n", netif->chan)); + return SHR_E_PARAM; + } + + rv = ngknet_ndev_init(netif, &ndev); + if (SHR_FAILURE(rv)) { + bcmcnet_pdma_dev_cleanup(pdev); + return rv; + } + dev->net_dev = ndev; + + /* Initialize private information for base network device */ + priv = netdev_priv(ndev); + priv->net_dev = ndev; + priv->bkn_dev = dev; + priv->pkt_recv = ngknet_pkt_recv; + priv->ref_count = 1; + + netif->id = 0; + memcpy(netif->macaddr, ndev->dev_addr, ETH_ALEN); + netif->mtu = ndev->mtu; + memcpy(netif->name, ndev->name, sizeof(netif->name) - 1); + memcpy(&priv->netif, netif, sizeof(priv->netif)); + + if (priv->netif.flags & NGKNET_NETIF_F_BIND_CHAN) { + dev->bdev[priv->netif.chan] = ndev; + } + + /* Register for napi */ + for (gi = 0; gi < pdev->num_groups; gi++) { + if (!pdev->ctrl.grp[gi].attached) { + continue; + } + for (qi = 0; qi < pdev->grp_queues; qi++) { + hdl = &pdev->ctrl.grp[gi].intr_hdl[qi]; + priv_hdl[hdl->unit][hdl->chan].hdl = hdl; + hdl->priv = &priv_hdl[hdl->unit][hdl->chan]; + kal_netif_napi_add(ndev, (struct napi_struct *)hdl->priv, + ngknet_poll, pdev->ctrl.budget); + if (pdev->flags & PDMA_GROUP_INTR) { + break; + } + } + } + + /* Get callback control */ + ngknet_callback_control_get(&dev->cbc); + + INIT_LIST_HEAD(&dev->filt_list); + spin_lock_init(&dev->lock); + init_waitqueue_head(&dev->wq); + if (pdev->mode == DEV_MODE_HNET) { + init_waitqueue_head(&dev->vnet_wq); + atomic_set(&dev->vnet_active, 0); + init_waitqueue_head(&dev->hnet_wq); + atomic_set(&dev->hnet_active, 0); + dev->hnet_task = kthread_run(ngknet_dev_hnet_process, pdev, pdev->name); + if (IS_ERR(dev->hnet_task)) { + dev->hnet_task = NULL; + return SHR_E_INTERNAL; + } + cpumask_clear(&mask); + cpumask_set_cpu(num_online_cpus() / 2, &mask); + set_cpus_allowed_ptr(dev->hnet_task, &mask); + INIT_WORK(&dev->hnet_work, ngknet_dev_hnet_schedule); + } + + skb_queue_head_init(&dev->ptp_tx_queue); + INIT_WORK(&dev->ptp_tx_work, ngknet_ptp_tx_work); + + dev->link_wq = create_workqueue("ngknet"); + if (!dev->link_wq) { + return SHR_E_INTERNAL; + } + + dev->flags |= NGKNET_DEV_ACTIVE; + + DBG_NDEV(("Broadcom NGKNET Attached\n")); + DBG_NDEV(("MAC: %pM\n", ndev->dev_addr)); + DBG_NDEV(("Running with NAPI enabled\n")); + + /* Register handler for BDE events. */ + ngbde_kapi_knet_connect(dn, ngknet_bde_event_handler, dev); + + return SHR_E_NONE; +} + +/*! + * \brief Remove device. + * + * Suspend device firstly, destroy all virtual network devices + * and filters, clean up Packet DMA device. + * + * \param [in] dn Device number. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +ngknet_dev_remove(int dn) +{ + struct ngknet_dev *dev = &ngknet_devices[dn]; + struct pdma_dev *pdev = &dev->pdma_dev; + struct net_device *ndev = NULL; + struct ngknet_private *priv = NULL; + struct intr_handle *hdl = NULL; + int di, gi, qi; + int rv; + + if (!(dev->flags & NGKNET_DEV_ACTIVE)) { + ngbde_kapi_knet_disconnect(dn); + return SHR_E_NONE; + } + + DBG_VERB(("%s: dev %d\n",__FUNCTION__, dn)); + + dev->flags &= ~NGKNET_DEV_ACTIVE; + + if (dev->link_wq) { + flush_workqueue(dev->link_wq); + destroy_workqueue(dev->link_wq); + } + + skb_queue_purge(&dev->ptp_tx_queue); + + if (pdev->mode == DEV_MODE_HNET && dev->hnet_task) { + atomic_set(&dev->hnet_active, 1); + wake_up_interruptible(&dev->hnet_wq); + kthread_stop(dev->hnet_task); + dev->hnet_task = NULL; + } + + /* Destroy all the filters */ + ngknet_filter_destroy_all(dev); + + /* Destroy all the virtual devices */ + for (di = 1; di <= NUM_VDEV_MAX; di++) { + ndev = dev->vdev[di]; + if (ndev) { + priv = netdev_priv(ndev); + if (--priv->ref_count > 0) { + netdev_put(ndev, NULL); + } else { + unregister_netdev(ndev); + free_netdev(ndev); + } + dev->vdev[di] = NULL; + } + } + dev->vdev[0] = NULL; + + DBG_VERB(("Removing base network device %s.\n", dev->net_dev->name)); + + /* Destroy the base network device */ + ndev = dev->net_dev; + unregister_netdev(ndev); + free_netdev(ndev); + + for (qi = 0; qi < NUM_Q_MAX; qi++) { + dev->bdev[qi] = NULL; + } + + for (gi = 0; gi < pdev->num_groups; gi++) { + if (!pdev->ctrl.grp[gi].attached) { + continue; + } + for (qi = 0; qi < pdev->grp_queues; qi++) { + hdl = &pdev->ctrl.grp[gi].intr_hdl[qi]; + netif_napi_del((struct napi_struct *)hdl->priv); + priv_hdl[hdl->unit][hdl->chan].hdl = NULL; + if (pdev->flags & PDMA_GROUP_INTR) { + break; + } + } + } + + /* Clean up PDMA device */ + bcmcnet_pdma_dev_cleanup(pdev); + + /* Detach PDMA driver */ + rv = drv_ops[pdev->dev_type]->drv_detach(pdev); + if (SHR_FAILURE(rv)) { + DBG_WARN(("Detach DMA driver failed.\n")); + } + ngbde_kapi_knet_disconnect(dn); + + return rv; +} + +static void +ngknet_netif_link_process(struct work_struct *work) +{ + struct ngknet_private *priv = container_of(work, struct ngknet_private, + link_work); + struct net_device *ndev = priv->net_dev; + + if (netif_carrier_ok(ndev)) { + netif_carrier_off(ndev); + netif_tx_stop_all_queues(ndev); + } else { + netif_carrier_on(ndev); + netif_tx_wake_all_queues(ndev); + } +} + +/*! + * Network interface functions + */ + +int +ngknet_netif_create(struct ngknet_dev *dev, ngknet_netif_t *netif) +{ + struct net_device *ndev = NULL; + struct ngknet_private *priv = NULL; + unsigned long flags; + uint16_t id, num; + int rv; + struct list_head *list; + netif_cb_t *netif_create_cb; + + switch (netif->type) { + case NGKNET_NETIF_T_VLAN: + case NGKNET_NETIF_T_PORT: + case NGKNET_NETIF_T_META: + break; + default: + return SHR_E_UNAVAIL; + } + + /* Get vitual network device name */ + if (netif->name[0] == '\0') { + /* Reserve 6 vacancies for base&vitual device number, i.e. nameAB_XYZ */ + if (strlen(base_dev_name) < IFNAMSIZ - 6) { + snprintf(netif->name, IFNAMSIZ, "%s%d%s", + base_dev_name, dev->dev_info.dev_no, "_"); + strncat(netif->name, "%d", 3); + } else { + DBG_WARN(("Too long network device name: %s.\n", base_dev_name)); + return SHR_E_PARAM; + } + } + + if (netif->chan >= NUM_Q_MAX) { + DBG_WARN(("Exceed max number of queues : %d.\n", netif->chan)); + return SHR_E_PARAM; + } + + rv = ngknet_ndev_init(netif, &ndev); + if (SHR_FAILURE(rv)) { + return rv; + } + + spin_lock_irqsave(&dev->lock, flags); + + num = (long)dev->vdev[0]; + id = netif->id; + if (netif->flags & NGKNET_NETIF_F_WITH_ID) { + if (id == 0 || id > NUM_VDEV_MAX) { + rv = SHR_E_PARAM; + } else { + /* ID assignment is specifed by user. */ + if (dev->vdev[id]) { + DBG_WARN(("ID %d is already in use\n", id)); + rv = SHR_E_BUSY; + } + } + } else { + /* Automatic ID assignment. */ + for (id = 1; id < num + 1; id++) { + if (!dev->vdev[id]) { + break; + } + } + if (id > NUM_VDEV_MAX) { + rv = SHR_E_RESOURCE; + } + } + if (SHR_FAILURE(rv)) { + spin_unlock_irqrestore(&dev->lock, flags); + unregister_netdev(ndev); + free_netdev(ndev); + return rv; + } + + dev->vdev[id] = ndev; + if (id > num) { + num = id; + } + dev->vdev[0] = (struct net_device *)(long)num; + + spin_unlock_irqrestore(&dev->lock, flags); + + priv = netdev_priv(ndev); + priv->net_dev = ndev; + priv->bkn_dev = dev; + priv->pkt_recv = ngknet_pkt_recv; + priv->ref_count = 1; + + netif->id = id; + memcpy(netif->macaddr, ndev->dev_addr, ETH_ALEN); + netif->mtu = ndev->mtu; + memcpy(netif->name, ndev->name, sizeof(netif->name) - 1); + memcpy(&priv->netif, netif, sizeof(priv->netif)); + + if (priv->netif.flags & NGKNET_NETIF_F_BIND_CHAN) { + dev->bdev[priv->netif.chan] = ndev; + } + + /* Optional netif create callback handle */ + list_for_each(list, &dev->cbc->netif_create_cb_list) { + netif_create_cb = list_entry(list, netif_cb_t, list); + if (netif_create_cb->cb(&dev->dev_info, &priv->netif)) { + DBG_WARN(("Network interface callback (create) failed for '%s'\n", + ndev->name)); + } + } + + INIT_WORK(&priv->link_work, ngknet_netif_link_process); + + DBG_VERB(("Created virtual network device %s (%d).\n", + ndev->name, priv->netif.id)); + + return SHR_E_NONE; +} + +int +ngknet_netif_destroy(struct ngknet_dev *dev, int id) +{ + struct net_device *ndev = NULL; + struct ngknet_private *priv = NULL; + unsigned long flags; + int num; + struct list_head *list; + netif_cb_t *netif_destroy_cb; + DECLARE_WAITQUEUE(wait, current); + + if (id <= 0 || id > NUM_VDEV_MAX) { + return SHR_E_PARAM; + } + + spin_lock_irqsave(&dev->lock, flags); + + ndev = dev->vdev[id]; + if (!ndev) { + spin_unlock_irqrestore(&dev->lock, flags); + return SHR_E_NOT_FOUND; + } + priv = netdev_priv(ndev); + + add_wait_queue(&dev->wq, &wait); + + while (priv->users) { + priv->wait = 1; + set_current_state(TASK_INTERRUPTIBLE); + spin_unlock_irqrestore(&dev->lock, flags); + schedule(); + spin_lock_irqsave(&dev->lock, flags); + priv->wait = 0; + set_current_state(TASK_RUNNING); + } + + if (priv->netif.flags & NGKNET_NETIF_F_BIND_CHAN) { + dev->bdev[priv->netif.chan] = NULL; + } + + dev->vdev[id] = NULL; + num = (long)dev->vdev[0]; + while (num-- == id--) { + if (dev->vdev[id]) { + dev->vdev[0] = (struct net_device *)(long)num; + break; + } + } + + priv->ref_count--; + + spin_unlock_irqrestore(&dev->lock, flags); + + remove_wait_queue(&dev->wq, &wait); + + /* Optional netif destroy callback handle */ + list_for_each(list, &dev->cbc->netif_destroy_cb_list) { + netif_destroy_cb = list_entry(list, netif_cb_t, list); + if (netif_destroy_cb->cb(&dev->dev_info, &priv->netif)) { + DBG_WARN(("Network interface callback (destroy) failed for '%s'\n", + ndev->name)); + } + } + + DBG_VERB(("Removing virtual network device %s (%d).\n", + ndev->name, priv->netif.id)); + + unregister_netdev(ndev); + free_netdev(ndev); + + return SHR_E_NONE; +} + +int +ngknet_netif_get(struct ngknet_dev *dev, int id, ngknet_netif_t *netif) +{ + struct net_device *ndev = NULL; + struct ngknet_private *priv = NULL; + unsigned long flags; + int num; + + if (id < 0 || id > NUM_VDEV_MAX) { + return SHR_E_PARAM; + } + + spin_lock_irqsave(&dev->lock, flags); + + ndev = id == 0 ? dev->net_dev : dev->vdev[id]; + if (!ndev) { + spin_unlock_irqrestore(&dev->lock, flags); + return SHR_E_NOT_FOUND; + } + + priv = netdev_priv(ndev); + memcpy(netif, &priv->netif, sizeof(*netif)); + + num = (long)dev->vdev[0]; + for (id++; id < num + 1; id++) { + if (dev->vdev[id]) { + break; + } + } + netif->next = id == (num + 1) ? 0 : id; + + spin_unlock_irqrestore(&dev->lock, flags); + + DBG_VERB(("Got virtual network device %s (%d).\n", + ndev->name, priv->netif.id)); + + return SHR_E_NONE; +} + +int +ngknet_netif_get_next(struct ngknet_dev *dev, ngknet_netif_t *netif) +{ + return ngknet_netif_get(dev, netif->next, netif); +} + +/*! + * \brief Lookup network device by netif name. + * + * \param [in] name Network device name. + * \param [in] mac Network device MAC address. + * \param [out] nd New registered network device. + * + */ +static void +ngknet_sand_ndev_lookup( + ngknet_netif_t *netif, + struct net_device **nd) +{ + struct net_device *ndev = NULL; + uint8_t *ma; + + if (!nd) { + DBG_WARN(("Network device is NULL.\n")); + return; + } + if (!netif) { + *nd = NULL; + DBG_WARN(("Network interface is NULL.\n")); + return; + } + + /* get Ethernet device */ + ndev = netdev_get_by_name(current->nsproxy->net_ns, netif->name, NULL, GFP_ATOMIC); + if (ndev == NULL) { + *nd = NULL; + DBG_WARN(("Error to get Ethernet device by name (%s).\n", netif->name)); + return; + } + + /* Compare the device MAC address */ + ma = netif->macaddr; + if (ndev->dev_addr[0] != ma[0] || ndev->dev_addr[1] != ma[1] || + ndev->dev_addr[2] != ma[2] || ndev->dev_addr[3] != ma[3] || + ndev->dev_addr[4] != ma[4] || ndev->dev_addr[5] != ma[5]) { + *nd = NULL; + DBG_WARN(("The Mac address doesn't match the Ethernet device that found by name.\n")); + netdev_put(ndev, NULL); + return; + } + + *nd = ndev; + return; +} + +/*! + * \brief Initialize network device. + * + * \param [in] name Network device name. + * \param [in] mac Network device MAC address. + * \param [out] nd New registered network device. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +static int +ngknet_sand_ndev_init(ngknet_netif_t *netif, struct net_device **nd) +{ + struct net_device *ndev = NULL; + uint8_t *ma; + int rv; + + if (!netif) { + DBG_WARN(("Network interface is NULL.\n")); + return SHR_E_PARAM; + } + if (!nd) { + DBG_WARN(("Network device is NULL.\n")); + return SHR_E_PARAM; + } + + ndev = alloc_etherdev_mq(sizeof(struct ngknet_private), NUM_Q_MAX); + if (!ndev) { + DBG_WARN(("Error allocating network device.\n")); + return SHR_E_MEMORY; + } + if (!ndev->dev_addr) { + DBG_WARN(("ndev->dev_addr is NULL\n")); + free_netdev(ndev); + return SHR_E_INTERNAL; + } + + /* Device information -- not available right now */ + ndev->irq = 0; + ndev->base_addr = 0; + + /* Fill in the dev structure */ + ndev->watchdog_timeo = 5 * HZ; + + /* Default MTU should not exceed MTU of switch front-panel ports */ + ndev->mtu = netif->mtu; + if (!ndev->mtu) { + ndev->mtu = default_mtu ? default_mtu : rx_buffer_size; + } + + /* MTU range: 32 - 9198 */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0)) + ndev->min_mtu = PKT_HDR_SIZE; /* Min 50-byte length of packet with RCPU-encap */ + ndev->max_mtu = rx_buffer_size - (ETH_HLEN + ETH_FCS_LEN); +#endif + + ndev->netdev_ops = &ngknet_netdev_ops; + ndev->ethtool_ops = &ngknet_ethtool_ops; + + /* Network device name */ + if (netif->name[0] != '\0') { + strncpy(ndev->name, netif->name, IFNAMSIZ - 1); + } + + /* Set the device MAC address */ + ma = netif->macaddr; + if ((ma[0] | ma[1] | ma[2] | ma[3] | ma[4] | ma[5]) == 0) { + ngknet_dev_mac[5]++; + if (ngknet_dev_mac[5] == 0) { + ngknet_dev_mac[4]++; + } + ma = ngknet_dev_mac; + } + eth_hw_addr_set(ndev, ma); + + /* Initialize the device features */ + ndev->hw_features = NETIF_F_RXCSUM | + NETIF_F_HW_VLAN_CTAG_RX | + NETIF_F_HW_VLAN_CTAG_TX; + ndev->features = NETIF_F_RXCSUM | + NETIF_F_HIGHDMA | + NETIF_F_HW_VLAN_CTAG_RX; + + dev_net_set(ndev, current->nsproxy->net_ns); + + /* Register the kernel network device */ + rv = register_netdev(ndev); + if (rv < 0) { + DBG_WARN(("Error registering network device %s.\n", ndev->name)); + free_netdev(ndev); + return SHR_E_FAIL; + } + + *nd = ndev; + + /*DBG_VERB(("Created network device %s.\n", ndev->name));*/ + + return SHR_E_NONE; +} + +static int +ngknet_sand_netif_create(struct ngknet_dev *dev, ngknet_netif_t *netif) +{ + struct net_device *ndev = NULL; + struct ngknet_private *priv = NULL; + unsigned long flags; + uint16_t id, num; + int rv; + struct list_head *list; + netif_cb_t *netif_create_cb; + + switch (netif->type) { + case NGKNET_NETIF_T_VLAN: + case NGKNET_NETIF_T_PORT: + case NGKNET_NETIF_T_META: + break; + default: + return SHR_E_UNAVAIL; + } + + /* Get vitual network device name */ + if (netif->name[0] == '\0') { + /* Reserve 6 vacancies for base&vitual device number, i.e. nameAB_XYZ */ + if (strlen(base_dev_name) < IFNAMSIZ - 6) { + snprintf(netif->name, IFNAMSIZ, "%s%d%s", + base_dev_name, dev->dev_info.dev_no, "_"); + strncat(netif->name, "%d", 3); + } else { + DBG_WARN(("Too long network device name: %s.\n", base_dev_name)); + return SHR_E_PARAM; + } + } + + if (netif->chan >= NUM_Q_MAX) { + DBG_WARN(("Exceed max number of queues : %d.\n", netif->chan)); + return SHR_E_PARAM; + } + + ngknet_sand_ndev_lookup(netif, &ndev); + if (ndev == NULL) { + if (netif->flags & NGKNET_NETIF_F_REPLACE) { + return SHR_E_NOT_FOUND; + } + rv = ngknet_sand_ndev_init(netif, &ndev); + if (SHR_FAILURE(rv)) { + return rv; + } + priv = netdev_priv(ndev); + priv->net_dev = ndev; + priv->bkn_dev = dev; + priv->pkt_recv = ngknet_pkt_recv; + priv->ref_count = 1; + } else { + if (netif->flags & NGKNET_NETIF_F_REPLACE) { + /** + * netdev_get_by_name() increases the device reference count, + * netdev_put() is called to avoid a reference leak. + */ + netdev_put(ndev, NULL); + + priv = netdev_priv(ndev); + if (netif->flags & NGKNET_NETIF_F_WITH_ID) { + if (netif->id != priv->netif.id) { + DBG_WARN(("ID %d is already in use\n", id)); + return SHR_E_PARAM; + } + } else { + return SHR_E_PARAM; + } + } else { + if ((netif->flags & NGKNET_NETIF_F_USE_SHARED_NDEV) == 0) { + netdev_put(ndev, NULL); + return SHR_E_FAIL; + } + priv = netdev_priv(ndev); + priv->netif.flags |= NGKNET_NETIF_F_USE_SHARED_NDEV; + priv->ref_count++; + } + } + + spin_lock_irqsave(&dev->lock, flags); + + num = (long)dev->vdev[0]; + id = netif->id; + if (netif->flags & NGKNET_NETIF_F_WITH_ID) { + if (id == 0 || id > NUM_VDEV_MAX) { + rv = SHR_E_PARAM; + } else { + /* ID assignment is specifed by user. */ + if (netif->flags & NGKNET_NETIF_F_REPLACE) { + if (!dev->vdev[id]) { + DBG_WARN(("ID %d is not in use. Replace operation failed.\n", id)); + rv = SHR_E_BADID; + } + } else { + if (dev->vdev[id]) { + DBG_WARN(("ID %d is already in use\n", id)); + rv = SHR_E_BUSY; + } + } + } + } else { + /* Automatic ID assignment. */ + for (id = 1; id < num + 1; id++) { + if (!dev->vdev[id]) { + break; + } + } + if (id > NUM_VDEV_MAX) { + rv = SHR_E_RESOURCE; + } + } + + if (netif->flags & NGKNET_NETIF_F_REPLACE) { + int qi; + if (SHR_FAILURE(rv)) { + spin_unlock_irqrestore(&dev->lock, flags); + return rv; + } + for (qi = 0; qi < NUM_Q_MAX; qi++) { + if (dev->bdev[qi] == ndev) { + dev->bdev[qi] = NULL; + } + } + if ((netif->flags & NGKNET_NETIF_F_USE_SHARED_NDEV) == 0) { + /* + * If core_group changed, we should update the dev&netif here. + */ + if (priv->bkn_dev != dev) { + priv->bkn_dev = dev; + } + netif->mtu = ndev->mtu; + memcpy(&priv->netif, netif, sizeof(priv->netif)); + } else { + priv->netif.flags |= NGKNET_NETIF_F_USE_SHARED_NDEV; + } + if (priv->netif.flags & NGKNET_NETIF_F_BIND_CHAN) { + dev->bdev[priv->netif.chan] = ndev; + } + spin_unlock_irqrestore(&dev->lock, flags); + + /* Optional netif create callback handle */ + list_for_each(list, &dev->cbc->netif_create_cb_list) { + netif_create_cb = list_entry(list, netif_cb_t, list); + if (netif_create_cb->cb(&dev->dev_info, &priv->netif)) { + DBG_WARN(("Network interface callback (replace) failed for '%s'\n", + ndev->name)); + } + } + DBG_VERB(("Replace virtual network device %s (%d).\n", + ndev->name, priv->netif.id)); + /* Replace return here. */ + return SHR_E_NONE; + } + + if (SHR_FAILURE(rv)) { + spin_unlock_irqrestore(&dev->lock, flags); + priv->ref_count--; + if (priv->ref_count <= 0) { + unregister_netdev(ndev); + free_netdev(ndev); + } else { + netdev_put(ndev, NULL); + } + return rv; + } + + dev->vdev[id] = ndev; + if (id > num) { + num = id; + } + dev->vdev[0] = (struct net_device *)(long)num; + + spin_unlock_irqrestore(&dev->lock, flags); + + if (priv->ref_count == 1) { + netif->id = id; + memcpy(netif->macaddr, ndev->dev_addr, ETH_ALEN); + netif->mtu = ndev->mtu; + memcpy(netif->name, ndev->name, sizeof(netif->name) - 1); + memcpy(&priv->netif, netif, sizeof(priv->netif)); + } else { + netif->id = id; + DBG_NDEV(("Use Shared Netif ID %d\n", id)); + } + + if (priv->netif.flags & NGKNET_NETIF_F_BIND_CHAN) { + dev->bdev[priv->netif.chan] = ndev; + } + + /* Optional netif create callback handle */ + list_for_each(list, &dev->cbc->netif_create_cb_list) { + netif_create_cb = list_entry(list, netif_cb_t, list); + if (netif_create_cb->cb(&dev->dev_info, &priv->netif)) { + DBG_WARN(("Network interface callback (create) failed for '%s'\n", + ndev->name)); + } + } + + INIT_WORK(&priv->link_work, ngknet_netif_link_process); + + DBG_VERB(("Created virtual network device %s (%d).\n", + ndev->name, priv->netif.id)); + + return SHR_E_NONE; +} + +static int +ngknet_sand_netif_destroy(struct ngknet_dev *dev, int id) +{ + struct net_device *ndev = NULL; + struct ngknet_private *priv = NULL; + unsigned long flags; + int num; + struct list_head *list; + netif_cb_t *netif_destroy_cb; + DECLARE_WAITQUEUE(wait, current); + + if (id <= 0 || id > NUM_VDEV_MAX) { + return SHR_E_PARAM; + } + + spin_lock_irqsave(&dev->lock, flags); + + ndev = dev->vdev[id]; + if (!ndev) { + spin_unlock_irqrestore(&dev->lock, flags); + return SHR_E_NOT_FOUND; + } + priv = netdev_priv(ndev); + + add_wait_queue(&dev->wq, &wait); + + while (priv->users) { + priv->wait = 1; + set_current_state(TASK_INTERRUPTIBLE); + spin_unlock_irqrestore(&dev->lock, flags); + schedule(); + spin_lock_irqsave(&dev->lock, flags); + priv->wait = 0; + set_current_state(TASK_RUNNING); + } + + if (priv->netif.flags & NGKNET_NETIF_F_BIND_CHAN) { + dev->bdev[priv->netif.chan] = NULL; + } + + dev->vdev[id] = NULL; + num = (long)dev->vdev[0]; + while (num-- == id--) { + if (dev->vdev[id]) { + dev->vdev[0] = (struct net_device *)(long)num; + break; + } + } + + priv->ref_count--; + + spin_unlock_irqrestore(&dev->lock, flags); + + remove_wait_queue(&dev->wq, &wait); + + /* Optional netif destroy callback handle */ + list_for_each(list, &dev->cbc->netif_destroy_cb_list) { + netif_destroy_cb = list_entry(list, netif_cb_t, list); + if (netif_destroy_cb->cb(&dev->dev_info, &priv->netif)) { + DBG_WARN(("Network interface callback (destroy) failed for '%s'\n", + ndev->name)); + } + } + + if (priv->ref_count <= 0) { + DBG_VERB(("Removing virtual network device %s (%d).\n", + ndev->name, priv->netif.id)); + + unregister_netdev(ndev); + free_netdev(ndev); + } else { + netdev_put(ndev, NULL); + } + return SHR_E_NONE; +} + +/*! + * System control interfaces + */ + +int +ngknet_debug_level_get(void) +{ + return debug; +} + +void +ngknet_debug_level_set(int debug_level) +{ + debug = debug_level; +} + +int +ngknet_rx_rate_limit_get(void) +{ + return rx_rate_limit; +} + +void +ngknet_rx_rate_limit_set(int rate_limit) +{ + rx_rate_limit = rate_limit; +} + +int +ngknet_page_buffer_mode_get(void) +{ + return page_buffer_mode; +} + +/*! + * Generic module functions + */ + +static int +ngknet_open(struct inode *inode, struct file *filp) +{ + return 0; +} + +static int +ngknet_release(struct inode *inode, struct file *filp) +{ + return 0; +} + +static long +ngknet_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + struct ngknet_ioctl ioc; + struct ngknet_dev *dev = NULL; + struct net_device *ndev = NULL; + struct ngknet_private *priv = NULL; + struct pdma_dev *pdev = NULL; + union { + ngknet_dev_cfg_t dev_cfg; + ngknet_chan_cfg_t chan_cfg; + ngknet_netif_t netif; + ngknet_filter_t filter; + } iod; + ngknet_dev_cfg_t *dev_cfg = &iod.dev_cfg; + ngknet_chan_cfg_t *chan_cfg = &iod.chan_cfg; + ngknet_netif_t *netif = &iod.netif; + ngknet_filter_t *filter = &iod.filter; + struct list_head *list = NULL; + dev_cb_t *dev_cb = NULL; + char *data = NULL; + int dt, gi, qi; + + if (_IOC_TYPE(cmd) != NGKNET_IOC_MAGIC) { + DBG_WARN(("Unsupported command (cmd=%d)\n", cmd)); + return -EINVAL; + } + + if (copy_from_user(&ioc, (void *)arg, sizeof(ioc))) { + return -EFAULT; + } + + ioc.rc = SHR_E_NONE; + + if (ioc.unit >= NUM_PDMA_DEV_MAX) { + ioc.rc = SHR_E_PARAM; + if (copy_to_user((void *)arg, &ioc, sizeof(ioc))) { + return -EFAULT; + } + return 0; + } + + dev = &ngknet_devices[ioc.unit]; + pdev = &dev->pdma_dev; + + if (cmd != NGKNET_VERSION_GET && + cmd != NGKNET_RX_RATE_LIMIT && + cmd != NGKNET_DEV_INIT && + !(dev->flags & NGKNET_DEV_ACTIVE)) { + ioc.rc = SHR_E_UNAVAIL; + if (copy_to_user((void *)arg, &ioc, sizeof(ioc))) { + return -EFAULT; + } + return 0; + } + + memset(&iod, 0, sizeof(iod)); + + switch (cmd) { + case NGKNET_VERSION_GET: + DBG_CMD(("NGKNET_VERSION_GET\n")); + ioc.op.info.version = NGKNET_IOC_VERSION; + break; + case NGKNET_RX_RATE_LIMIT: + DBG_CMD(("NGKNET_RX_RATE_LIMIT\n")); + if (ioc.iarg[0]) { + ngknet_rx_rate_limit_set(ioc.iarg[1]); + } else { + ioc.iarg[1] = ngknet_rx_rate_limit_get(); + } + break; + case NGKNET_DEV_INIT: + DBG_CMD(("NGKNET_DEV_INIT\n")); + if (dev->flags & NGKNET_DEV_ACTIVE) { + DBG_CMD(("NGKNET_DEV_INIT, retrieve device configurations.\n")); + strscpy(dev_cfg->name, pdev->name, sizeof(dev_cfg->name)); + dev_cfg->dev_id = pdev->dev_id; + dev_cfg->nb_grp = pdev->ctrl.nb_grp; + dev_cfg->bm_grp = pdev->ctrl.bm_grp; + ioc.rc = ngknet_netif_get(dev, 0, &dev_cfg->base_netif); + if (SHR_FAILURE((int)ioc.rc)) { + break; + } + if (kal_copy_to_user((void *)(unsigned long)ioc.op.data.buf, dev_cfg, + ioc.op.data.len, sizeof(*dev_cfg))) { + return -EFAULT; + } + break; + } + if (kal_copy_from_user(dev_cfg, (void *)(unsigned long)ioc.op.data.buf, + sizeof(*dev_cfg), ioc.op.data.len)) { + return -EFAULT; + } + if (!dev_cfg->name[0] || !dev_cfg->bm_grp || + dev_cfg->bm_grp >= (1 << NUM_GRP_MAX)) { + DBG_WARN(("Invalid parameter: name=%s, bm_grp=0x%x\n", + dev_cfg->name, dev_cfg->bm_grp)); + ioc.rc = SHR_E_PARAM; + break; + } + memset(pdev, 0, sizeof(*pdev)); + strscpy(pdev->name, dev_cfg->name, sizeof(pdev->name)); + pdev->dev_id = dev_cfg->dev_id; + for (dt = 0; dt < drv_num; dt++) { + if (!drv_ops[dt]) { + continue; + } + if (!strcasecmp(dev_cfg->type_str, drv_ops[dt]->drv_desc)) { + pdev->dev_type = dt; + strscpy(dev->dev_info.var_str, dev_cfg->var_str, + sizeof(dev->dev_info.var_str)); + break; + } + } + if (pdev->dev_type <= NGKNET_DEV_T_NONE || + pdev->dev_type >= NGKNET_DEV_T_COUNT) { + ioc.rc = SHR_E_PARAM; + break; + } + dev->dev_info.dev_id = pdev->dev_id; + pdev->ctrl.bm_grp = dev_cfg->bm_grp; + for (gi = 0; gi < NUM_GRP_MAX; gi++) { + if (1 << gi & dev_cfg->bm_grp) { + pdev->ctrl.nb_grp++; + pdev->ctrl.grp[gi].attached = true; + pdev->num_groups = gi + 1; + } + } + pdev->rx_ph_size = dev_cfg->rx_ph_size; + pdev->tx_ph_size = dev_cfg->tx_ph_size; + pdev->flags |= PDMA_GROUP_INTR; + if (dev_cfg->flags & NGKNET_RX_POLL_SQ) { + pdev->flags &= ~PDMA_GROUP_INTR; + } + pdev->mode = dev_cfg->mode; + if (pdev->mode != DEV_MODE_KNET && pdev->mode != DEV_MODE_HNET) { + pdev->mode = DEV_MODE_KNET; + } + ioc.rc = ngknet_dev_probe(ioc.unit, &dev_cfg->base_netif); + if (SHR_FAILURE((int)ioc.rc)) { + break; + } + list_for_each(list, &dev->cbc->dev_init_cb_list) { + dev_cb = list_entry(list, dev_cb_t, list); + dev_cb->cb(&dev->dev_info); + } + if (kal_copy_to_user((void *)(unsigned long)ioc.op.data.buf, dev_cfg, + ioc.op.data.len, sizeof(*dev_cfg))) { + return -EFAULT; + } + break; + case NGKNET_DEV_DEINIT: + DBG_CMD(("NGKNET_DEV_DEINIT\n")); + if (dev->flags & NGKNET_DEV_ACTIVE) { + ioc.rc = ngknet_dev_remove(ioc.unit); + } + break; + case NGKNET_QUEUE_CONFIG: + DBG_CMD(("NGKNET_QUEUE_CONFIG\n")); + if (kal_copy_from_user(chan_cfg, (void *)(unsigned long)ioc.op.data.buf, + sizeof(*chan_cfg), ioc.op.data.len)) { + return -EFAULT; + } + gi = chan_cfg->chan / pdev->grp_queues; + if (!(1 << gi & pdev->ctrl.bm_grp)) { + DBG_WARN(("Invalid parameter: chan=%d (bm_grp=0x%x)\n", + chan_cfg->chan, pdev->ctrl.bm_grp)); + ioc.rc = SHR_E_PARAM; + break; + } + if (chan_cfg->dir == PDMA_Q_RX) { + if (1 << chan_cfg->chan & pdev->ctrl.bm_txq) { + pdev->ctrl.bm_txq &= ~(1 << chan_cfg->chan); + pdev->ctrl.nb_txq--; + } + if (!(1 << chan_cfg->chan & pdev->ctrl.bm_rxq)) { + pdev->ctrl.bm_rxq |= 1 << chan_cfg->chan; + pdev->ctrl.nb_rxq++; + } + } else { + if (1 << chan_cfg->chan & pdev->ctrl.bm_rxq) { + pdev->ctrl.bm_rxq &= ~(1 << chan_cfg->chan); + pdev->ctrl.nb_rxq--; + } + if (!(1 << chan_cfg->chan & pdev->ctrl.bm_txq)) { + pdev->ctrl.bm_txq |= 1 << chan_cfg->chan; + pdev->ctrl.nb_txq++; + } + } + qi = chan_cfg->chan % pdev->grp_queues; + pdev->ctrl.grp[gi].nb_desc[qi] = chan_cfg->nb_desc; + pdev->ctrl.grp[gi].rx_size[qi] = chan_cfg->rx_buf_size; + pdev->ctrl.grp[gi].que_ctrl[qi] &= ~(PDMA_PKT_BYTE_SWAP | + PDMA_OTH_BYTE_SWAP | + PDMA_HDR_BYTE_SWAP); + if (chan_cfg->chan_ctrl & NGKNET_PKT_BYTE_SWAP) { + pdev->ctrl.grp[gi].que_ctrl[qi] |= PDMA_PKT_BYTE_SWAP; + } + if (chan_cfg->chan_ctrl & NGKNET_OTH_BYTE_SWAP) { + pdev->ctrl.grp[gi].que_ctrl[qi] |= PDMA_OTH_BYTE_SWAP; + } + if (chan_cfg->chan_ctrl & NGKNET_HDR_BYTE_SWAP) { + pdev->ctrl.grp[gi].que_ctrl[qi] |= PDMA_HDR_BYTE_SWAP; + } + pdev->ctrl.grp[gi].pipe[qi] = chan_cfg->pipe; + break; + case NGKNET_QUEUE_QUERY: + DBG_CMD(("NGKNET_QUEUE_QUERY\n")); + if (kal_copy_from_user(chan_cfg, (void *)(unsigned long)ioc.op.data.buf, + sizeof(*chan_cfg), ioc.op.data.len)) { + return -EFAULT; + } + if (1 << chan_cfg->chan & pdev->ctrl.bm_rxq) { + chan_cfg->dir = PDMA_Q_RX; + } else if (1 << chan_cfg->chan & pdev->ctrl.bm_txq) { + chan_cfg->dir = PDMA_Q_TX; + } else { + ioc.rc = SHR_E_UNAVAIL; + break; + } + gi = chan_cfg->chan / pdev->grp_queues; + qi = chan_cfg->chan % pdev->grp_queues; + chan_cfg->nb_desc = pdev->ctrl.grp[gi].nb_desc[qi]; + chan_cfg->chan_ctrl = pdev->ctrl.grp[gi].que_ctrl[qi]; + if (chan_cfg->dir == PDMA_Q_RX) { + chan_cfg->rx_buf_size = pdev->ctrl.grp[gi].rx_size[qi]; + } else { + chan_cfg->rx_buf_size = 0; + } + chan_cfg->pipe = pdev->ctrl.grp[gi].pipe[qi]; + if (kal_copy_to_user((void *)(unsigned long)ioc.op.data.buf, chan_cfg, + ioc.op.data.len, sizeof(*chan_cfg))) { + return -EFAULT; + } + break; + case NGKNET_DEV_SUSPEND: + DBG_CMD(("NGKNET_DEV_SUSPEND\n")); + if (rx_rate_limit >= 0) { + ngknet_rx_rate_limit_stop(dev); + } + if (ioc.iarg[0]) { + /* Graceful suspend */ + ioc.rc = bcmcnet_pdma_dev_suspend(pdev); + } else { + pdev->flags |= PDMA_ABORT; + ioc.rc = bcmcnet_pdma_dev_suspend(pdev); + } + break; + case NGKNET_DEV_RESUME: + DBG_CMD(("NGKNET_DEV_RESUME\n")); + ioc.rc = bcmcnet_pdma_dev_resume(pdev); + if (rx_rate_limit >= 0) { + ngknet_rx_rate_limit_start(dev); + } + break; + case NGKNET_DEV_VNET_WAIT: + DBG_CMD(("NGKNET_DEV_VNET_WAIT\n")); + if (pdev->mode != DEV_MODE_HNET) { + ioc.rc = SHR_E_UNAVAIL; + break; + } + wait_event_interruptible(dev->vnet_wq, + atomic_read(&dev->vnet_active) != 0); + atomic_set(&dev->vnet_active, 0); + break; + case NGKNET_DEV_HNET_WAKE: + DBG_CMD(("NGKNET_DEV_HNET_WAKE\n")); + if (pdev->mode != DEV_MODE_HNET) { + ioc.rc = SHR_E_UNAVAIL; + break; + } + if (atomic_read(&dev->hnet_active) != 1) { + atomic_set(&dev->hnet_active, 1); + wake_up_interruptible(&dev->hnet_wq); + } + break; + case NGKNET_DEV_VNET_DOCK: + DBG_CMD(("NGKNET_DEV_VNET_DOCK\n")); + if (pdev->mode != DEV_MODE_HNET) { + ioc.rc = SHR_E_UNAVAIL; + break; + } + if (kal_copy_from_user(&pdev->ctrl.vsync, (void *)(unsigned long)ioc.op.data.buf, + sizeof(pdev->ctrl.vsync), ioc.op.data.len)) { + return -EFAULT; + } + ioc.rc = bcmcnet_pdma_dev_dock(pdev); + break; + case NGKNET_DEV_VNET_UNDOCK: + DBG_CMD(("NGKNET_DEV_VNET_UNDOCK\n")); + if (pdev->mode != DEV_MODE_HNET) { + ioc.rc = SHR_E_UNAVAIL; + break; + } + ngknet_dev_vnet_wake(pdev); + ioc.rc = bcmcnet_pdma_dev_undock(pdev); + break; + case NGKNET_RCPU_CONFIG: + DBG_CMD(("NGKNET_RCPU_CONFIG\n")); + if (kal_copy_from_user(&dev->rcpu_ctrl, (void *)(unsigned long)ioc.op.data.buf, + sizeof(dev->rcpu_ctrl), ioc.op.data.len)) { + return -EFAULT; + } + break; + case NGKNET_RCPU_GET: + DBG_CMD(("NGKNET_RCPU_GET\n")); + if (kal_copy_to_user((void *)(unsigned long)ioc.op.data.buf, &dev->rcpu_ctrl, + ioc.op.data.len, sizeof(dev->rcpu_ctrl))) { + return -EFAULT; + } + break; + case NGKNET_INFO_GET: + DBG_CMD(("NGKNET_INFO_GET\n")); + bcmcnet_pdma_dev_info_get(pdev); + if (kal_copy_to_user((void *)(unsigned long)ioc.op.data.buf, &pdev->info, + ioc.op.data.len, sizeof(pdev->info))) { + return -EFAULT; + } + break; + case NGKNET_STATS_GET: + DBG_CMD(("NGKNET_STATS_GET\n")); + bcmcnet_pdma_dev_stats_get(pdev); + if (kal_copy_to_user((void *)(unsigned long)ioc.op.data.buf, &pdev->stats, + ioc.op.data.len, sizeof(pdev->stats))) { + return -EFAULT; + } + break; + case NGKNET_STATS_RESET: + DBG_CMD(("NGKNET_STATS_RESET\n")); + bcmcnet_pdma_dev_stats_reset(pdev); + break; + case NGKNET_NETIF_CREATE: + DBG_CMD(("NGKNET_NETIF_CREATE\n")); + if (kal_copy_from_user(netif, (void *)(unsigned long)ioc.op.data.buf, + sizeof(*netif), ioc.op.data.len)) { + return -EFAULT; + } + if (device_is_sand(ioc.unit)) { + ioc.rc = ngknet_sand_netif_create(dev, netif); + } else { + ioc.rc = ngknet_netif_create(dev, netif); + } + if (SHR_FAILURE((int)ioc.rc)) { + break; + } + if (kal_copy_to_user((void *)(unsigned long)ioc.op.data.buf, netif, + ioc.op.data.len, sizeof(*netif))) { + return -EFAULT; + } + break; + case NGKNET_NETIF_DESTROY: + DBG_CMD(("NGKNET_NETIF_DESTROY\n")); + if (device_is_sand(ioc.unit)) { + ioc.rc = ngknet_sand_netif_destroy(dev, ioc.iarg[0]); + } else { + ioc.rc = ngknet_netif_destroy(dev, ioc.iarg[0]); + } + break; + case NGKNET_NETIF_GET: + DBG_CMD(("NGKNET_NETIF_GET\n")); + ioc.rc = ngknet_netif_get(dev, ioc.iarg[0], netif); + if (SHR_FAILURE((int)ioc.rc)) { + break; + } + if (kal_copy_to_user((void *)(unsigned long)ioc.op.data.buf, netif, + ioc.op.data.len, sizeof(*netif))) { + return -EFAULT; + } + break; + case NGKNET_NETIF_NEXT: + DBG_CMD(("NGKNET_NETIF_NEXT\n")); + if (kal_copy_from_user(netif, (void *)(unsigned long)ioc.op.data.buf, + sizeof(*netif), ioc.op.data.len)) { + return -EFAULT; + } + ioc.rc = ngknet_netif_get_next(dev, netif); + if (SHR_FAILURE((int)ioc.rc)) { + break; + } + if (kal_copy_to_user((void *)(unsigned long)ioc.op.data.buf, netif, + ioc.op.data.len, sizeof(*netif))) { + return -EFAULT; + } + break; + case NGKNET_NETIF_LINK_SET: + DBG_CMD(("NGKNET_NETIF_LINK_SET\n")); + ioc.rc = ngknet_netif_get(dev, ioc.iarg[0], netif); + if (SHR_FAILURE((int)ioc.rc)) { + break; + } + ndev = dev->vdev[netif->id]; + priv = netdev_priv(ndev); + if (ioc.iarg[1]) { + if (!netif_carrier_ok(ndev)) { + queue_work(dev->link_wq, &priv->link_work); + flush_work(&priv->link_work); + DBG_LINK(("%s: link up\n", netif->name)); + } + } else { + if (netif_carrier_ok(ndev)) { + queue_work(dev->link_wq, &priv->link_work); + flush_work(&priv->link_work); + DBG_LINK(("%s: link down\n", netif->name)); + } + } + break; + case NGKNET_FILT_CREATE: + DBG_CMD(("NGKNET_FILT_CREATE\n")); + if (kal_copy_from_user(filter, (void *)(unsigned long)ioc.op.data.buf, + sizeof(*filter), ioc.op.data.len)) { + return -EFAULT; + } + ioc.rc = ngknet_filter_create(dev, filter); + if (SHR_FAILURE((int)ioc.rc)) { + break; + } + if (kal_copy_to_user((void *)(unsigned long)ioc.op.data.buf, filter, + ioc.op.data.len, sizeof(*filter))) { + return -EFAULT; + } + break; + case NGKNET_FILT_DESTROY: + DBG_CMD(("NGKNET_FILT_DESTROY\n")); + ioc.rc = ngknet_filter_destroy(dev, ioc.iarg[0]); + break; + case NGKNET_FILT_GET: + DBG_CMD(("NGKNET_FILT_GET\n")); + ioc.rc = ngknet_filter_get(dev, ioc.iarg[0], filter); + if (SHR_FAILURE((int)ioc.rc)) { + break; + } + if (kal_copy_to_user((void *)(unsigned long)ioc.op.data.buf, filter, + ioc.op.data.len, sizeof(*filter))) { + return -EFAULT; + } + break; + case NGKNET_FILT_NEXT: + DBG_CMD(("NGKNET_FILT_NEXT\n")); + if (kal_copy_from_user(filter, (void *)(unsigned long)ioc.op.data.buf, + sizeof(*filter), ioc.op.data.len)) { + return -EFAULT; + } + ioc.rc = ngknet_filter_get_next(dev, filter); + if (SHR_FAILURE((int)ioc.rc)) { + break; + } + if (kal_copy_to_user((void *)(unsigned long)ioc.op.data.buf, filter, + ioc.op.data.len, sizeof(*filter))) { + return -EFAULT; + } + break; + case NGKNET_PTP_DEV_CTRL: + DBG_CMD(("NGKNET_PTP_DEV_CTRL\n")); + if (ioc.op.data.len) { + data = kmalloc(ioc.op.data.len, GFP_ATOMIC); + if (data == NULL) { + printk("Fatal error: no memory for PTP device ioctl\n"); + return -EFAULT; + } + if (copy_from_user(data, (void *)(unsigned long)ioc.op.data.buf, + ioc.op.data.len)) { + kfree(data); + return -EFAULT; + } + } + ioc.rc = ngknet_ptp_dev_ctrl(dev, ioc.iarg[0], data, ioc.op.data.len); + if (SHR_FAILURE((int)ioc.rc)) { + if (data) { + kfree(data); + } + break; + } + if (ioc.op.data.len) { + if (copy_to_user((void *)(unsigned long)ioc.op.data.buf, data, + ioc.op.data.len)) { + kfree(data); + return -EFAULT; + } + kfree(data); + } + break; + case NGKNET_MESSAGE: + DBG_CMD(("NGKNET_MESSAGE\n")); + if (ioc.op.data.len) { + data = kmalloc(ioc.op.data.len, GFP_ATOMIC); + if (data == NULL) { + printk("Fatal error: no memory for message.\n"); + return -EFAULT; + } + if (copy_from_user(data, (void *)(unsigned long)ioc.op.data.buf, + ioc.op.data.len)) { + kfree(data); + return -EFAULT; + } + } + ioc.rc = ngknet_adapter_msg(dev, ioc.unit, ioc.iarg[0], ioc.iarg[1], data, ioc.op.data.len); + if (SHR_FAILURE((int)ioc.rc)) { + if (data) { + kfree(data); + } + break; + } + if (ioc.op.data.len) { + if (copy_to_user((void *)(unsigned long)ioc.op.data.buf, data, + ioc.op.data.len)) { + kfree(data); + return -EFAULT; + } + kfree(data); + } + break; + default: + ioc.rc = SHR_E_UNAVAIL; + printk("Invalid IOCTL"); + break; + } + + if (copy_to_user((void *)arg, &ioc, sizeof(ioc))) { + return -EFAULT; + } + + return 0; +} + +static int +ngknet_mmap(struct file *filp, struct vm_area_struct *vma) +{ + return 0; +} + +static struct file_operations ngknet_fops = { + .open = ngknet_open, + .release = ngknet_release, + .unlocked_ioctl = ngknet_ioctl, + .compat_ioctl = ngknet_ioctl, + .mmap = ngknet_mmap, +}; + +static int __init +ngknet_init_module(void) +{ + int idx; + int rv; + + rv = register_chrdev(NGKNET_MODULE_MAJOR, NGKNET_MODULE_NAME, &ngknet_fops); + if (rv < 0) { + printk(KERN_WARNING "%s: can't get major %d\n", + NGKNET_MODULE_NAME, NGKNET_MODULE_MAJOR); + return rv; + } + + /* Randomize lower 3 bytes of the MAC address (TESTING ONLY) */ + get_random_bytes(&ngknet_dev_mac[3], 3); + + /* Check for user-supplied MAC address (recommended) */ + if (mac_addr != NULL && strlen(mac_addr) == 17) { + for (idx = 0; idx < 6; idx++) { + ngknet_dev_mac[idx] = simple_strtoul(&mac_addr[idx * 3], NULL, 16); + } + /* Do not allow multicast address */ + ngknet_dev_mac[0] &= ~0x01; + } + + /* Initialize procfs */ + ngknet_procfs_init(); + + /* Initialize Rx rate limit */ + ngknet_rx_rate_limit_init(ngknet_devices); + + /* Initialize Callback control */ + ngknet_callback_init(ngknet_devices); + + return 0; +} + +static void __exit +ngknet_exit_module(void) +{ + int idx; + + /* Cleanup Callback control */ + ngknet_callback_cleanup(); + + /* Cleanup Rx rate limit */ + ngknet_rx_rate_limit_cleanup(); + + /* Cleanup procfs */ + ngknet_procfs_cleanup(); + + /* Remove all the devices */ + for (idx = 0; idx < NUM_PDMA_DEV_MAX; idx++) { + ngknet_dev_remove(idx); + } + + unregister_chrdev(NGKNET_MODULE_MAJOR, NGKNET_MODULE_NAME); +} + +module_init(ngknet_init_module); +module_exit(ngknet_exit_module); + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_main.h b/systems/linux/kernel/modules/bcm-ngknet/ngknet_main.h new file mode 100644 index 0000000..fbeaadd --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_main.h @@ -0,0 +1,289 @@ +/*! \file ngknet_main.h + * + * Data structure and macro definitions for NGKNET kernel module. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_MAIN_H +#define NGKNET_MAIN_H + +#include +#include +#include +#include +#include + +/*! + * Debug levels + */ +#define DBG_LVL_VERB 0x0001 +#define DBG_LVL_PKT 0x0002 +#define DBG_LVL_CMD 0x0004 +#define DBG_LVL_IRQ 0x0008 +#define DBG_LVL_NAPI 0x0010 +#define DBG_LVL_NDEV 0x0020 +#define DBG_LVL_FILT 0x0040 +#define DBG_LVL_RCPU 0x0080 +#define DBG_LVL_WARN 0x0100 +#define DBG_LVL_PDMP 0x0200 +#define DBG_LVL_RATE 0x0400 +#define DBG_LVL_LINK 0x0800 + +#define DBG_VERB(_s) do { if (debug & DBG_LVL_VERB) printk _s; } while (0) +#define DBG_PKT(_s) do { if (debug & DBG_LVL_PKT) printk _s; } while (0) +#define DBG_CMD(_s) do { if (debug & DBG_LVL_CMD) printk _s; } while (0) +#define DBG_IRQ(_s) do { if (debug & DBG_LVL_IRQ) printk _s; } while (0) +#define DBG_NAPI(_s) do { if (debug & DBG_LVL_NAPI) printk _s; } while (0) +#define DBG_NDEV(_s) do { if (debug & DBG_LVL_NDEV) printk _s; } while (0) +#define DBG_FILT(_s) do { if (debug & DBG_LVL_FILT) printk _s; } while (0) +#define DBG_RCPU(_s) do { if (debug & DBG_LVL_RCPU) printk _s; } while (0) +#define DBG_WARN(_s) do { if (debug & DBG_LVL_WARN) printk _s; } while (0) +#define DBG_PDMP(_s) do { if (debug & DBG_LVL_PDMP) printk _s; } while (0) +#define DBG_RATE(_s) do { if (debug & DBG_LVL_RATE) printk _s; } while (0) +#define DBG_LINK(_s) do { if (debug & DBG_LVL_LINK) printk _s; } while (0) + +/* Take over the control of SKB and send packet to network interface. */ +typedef void (*ngknet_pkt_recv_f)(struct net_device *ndev, struct sk_buff *skb); + +/*! + * Device description + */ +struct ngknet_dev { + /* Device information */ + ngknet_dev_info_t dev_info; + + /*! Base address for PCI register access */ + volatile void *base_addr; + + /*! Required for DMA memory control */ + struct device *dev; + + /*! Required for PCI memory control */ + struct pci_dev *pci_dev; + + /*! Base network device */ + struct net_device *net_dev; + + /*! PDMA device */ + struct pdma_dev pdma_dev; + + /*! Virtual network devices, 0 is used for max ID number. */ + struct net_device *vdev[NUM_VDEV_MAX + 1]; + + /*! Virtual network devices bound to queue */ + struct net_device *bdev[NUM_Q_MAX]; + + /*! Filter list */ + struct list_head filt_list; + + /*! Filter control, 0 is reserved */ + void *fc[NUM_FILTER_MAX + 1]; + + /*! Callback control */ + struct ngknet_callback_ctrl *cbc; + + /*! RCPU control */ + struct ngknet_rcpu_hdr rcpu_ctrl; + + /*! NGKNET lock */ + spinlock_t lock; + + /*! NGKNET wait queue */ + wait_queue_head_t wq; + + /*! VNET wait queue */ + wait_queue_head_t vnet_wq; + + /*! VNET is active */ + atomic_t vnet_active; + + /*! HNET wait queue */ + wait_queue_head_t hnet_wq; + + /*! HNET is active */ + atomic_t hnet_active; + + /*! HNET deamon */ + struct task_struct *hnet_task; + + /*! HNET work */ + struct work_struct hnet_work; + + /*! PTP Tx queue */ + struct sk_buff_head ptp_tx_queue; + + /*! PTP Tx work */ + struct work_struct ptp_tx_work; + + /*! NGKNET work queue for link process */ + struct workqueue_struct *link_wq; + + /*! Flags */ + int flags; + /*! NGKNET device is active */ +#define NGKNET_DEV_ACTIVE (1 << 0) +}; + +/*! + * Network interface specific private data + */ +struct ngknet_private { + /*! Network device */ + struct net_device *net_dev; + + /*! Network stats */ + struct net_device_stats stats; + + /*! NGKNET device */ + struct ngknet_dev *bkn_dev; + + /*! Network interface */ + ngknet_netif_t netif; + + /*! Packet receive callback */ + ngknet_pkt_recv_f pkt_recv; + + /*! Link work */ + struct work_struct link_work; + + /*! Users of this network interface */ + int users; + + /*! Wait for this network interface free */ + int wait; + + /*! HW timestamp Rx filter */ + int hwts_rx_filter; + + /*! HW timestamp Tx type */ + int hwts_tx_type; + +#if NGKNET_ETHTOOL_LINK_SETTINGS + /* Link settings */ + struct ethtool_link_settings link_settings; +#endif + + /*! reference count for shared net device. */ + int ref_count; +}; + +/*! + * \brief Create network interface. + * + * \param [in] dev NGKNET device structure point. + * \param [in] netif Network interface structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +ngknet_netif_create(struct ngknet_dev *dev, ngknet_netif_t *netif); + +/*! + * \brief Destroy network interface. + * + * \param [in] dev NGKNET device structure point. + * \param [in] id Network interface ID. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +ngknet_netif_destroy(struct ngknet_dev *dev, int id); + +/*! + * \brief Get network interface. + * + * \param [in] dev NGKNET device structure point. + * \param [in] id Network interface ID. + * \param [out] netif Network interface structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +ngknet_netif_get(struct ngknet_dev *dev, int id, ngknet_netif_t *netif); + +/*! + * \brief Get the next network interface. + * + * \param [in] dev NGKNET device structure point. + * \param [out] netif Network interface structure point. + * + * \retval SHR_E_NONE No errors. + * \retval SHR_E_XXXX Operation failed. + */ +extern int +ngknet_netif_get_next(struct ngknet_dev *dev, ngknet_netif_t *netif); + +/*! + * \brief Get debug level. + * + * \retval Current debug level. + */ +extern int +ngknet_debug_level_get(void); + +/*! + * \brief Set debug level. + * + * \param [in] debug_level Debug level to be set. + */ +extern void +ngknet_debug_level_set(int debug_level); + +/*! + * \brief Get Rx rate limit. + * + * \retval Current Rx rate limit. + */ +extern int +ngknet_rx_rate_limit_get(void); + +/*! + * \brief Set Rx rate limit. + * + * \param [in] rate_limit Rx rate limit to be set. + */ +extern void +ngknet_rx_rate_limit_set(int rate_limit); + +/*! + * \brief Get page buffer mode. + * + * \retval Current page buffer mode. + */ +extern int +ngknet_page_buffer_mode_get(void); + +#endif /* NGKNET_MAIN_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_parser.c b/systems/linux/kernel/modules/bcm-ngknet/ngknet_parser.c new file mode 100644 index 0000000..b479fdd --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_parser.c @@ -0,0 +1,1231 @@ +/*! \file ngknet_parser.c + * + * Parser routines for Knet RX. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include "ngknet_parser.h" +#include "ngknet_buff.h" + +static int debug = 0; + +/* DCB words */ +#define BKN_DNX_DCB_WORDS 4 +/* 0x1 - Jericho 2 mode */ +#define BKN_DNX_JR2_MODE 1 +/* PTCH_2 */ +#define BKN_DNX_PTCH_2_SIZE 2 +/* ITMH */ +#define BKN_DNX_ITMH_SIZE 5 +/* Modlue Header */ +#define BKN_DNX_MODULE_HEADER_SIZE 16 +/* FTMH */ +#define BKN_DNX_FTMH_TC_MSB 14 +#define BKN_DNX_FTMH_TC_NOF_BITS 3 +#define BKN_DNX_FTMH_SRC_SYS_PORT_AGGREGATE_MSB 17 +#define BKN_DNX_FTMH_SRC_SYS_PORT_AGGREGATE_NOF_BITS 16 +#define BKN_DNX_FTMH_PP_DSP_MSB 33 +#define BKN_DNX_FTMH_PP_DSP_NOF_BITS 8 +#define BKN_DNX_FTMH_ACTION_TYPE_MSB 43 +#define BKN_DNX_FTMH_ACTION_TYPE_NOF_BITS 2 +#define BKN_DNX_FTMH_PPH_TYPE_IS_TSH_EN_MSB 73 +#define BKN_DNX_FTMH_PPH_TYPE_IS_TSH_EN_NOF_BITS 1 +#define BKN_DNX_FTMH_PPH_TYPE_IS_PPH_EN_MSB 74 +#define BKN_DNX_FTMH_PPH_TYPE_IS_PPH_EN_NOF_BITS 1 +#define BKN_DNX_FTMH_TM_DST_EXT_PRESENT_MSB 75 +#define BKN_DNX_FTMH_TM_DST_EXT_PRESENT_NOF_BITS 1 +#define BKN_DNX_FTMH_APP_SPECIFIC_EXT_SIZE_MSB 76 +#define BKN_DNX_FTMH_APP_SPECIFIC_EXT_SIZE_NOF_BITS 1 +#define BKN_DNX_FTMH_FLOW_ID_EXT_SIZE_MSB 77 +#define BKN_DNX_FTMH_FLOW_ID_EXT_SIZE_NOF_BITS 1 +#define BKN_DNX_FTMH_BIER_BFR_EXT_SIZE_MSB 78 +#define BKN_DNX_FTMH_BIER_BFR_EXT_SIZE_NOF_BITS 1 +/* Fix Length for FTMH and Extension headers */ +#define BKN_DNX_FTMH_BASE_SIZE 10 +#define BKN_DNX_FTMH_BIER_BFR_EXT_SIZE 2 +#define BKN_DNX_FTMH_TM_DST_EXT_SIZE 3 +#define BKN_DNX_FTMH_FLOW_ID_EXT_SIZE 3 +#define BKN_DNX_FTMH_APP_SPECIFIC_EXT_SIZE 6 +#define BKN_DNX_SYSPORTS_PER_DEVICE_MASK 0x3FF +/*ASE*/ +#define BKN_DNX_FTMH_ASE_OAM_SUB_TYPE_MSB 0 +#define BKN_DNX_FTMH_ASE_OAM_SUB_TYPE_NOF_BITS 4 +#define BKN_DNX_FTMH_ASE_OAM_SUB_TYPE_DM_1588 2 +#define BKN_DNX_FTMH_ASE_OAM_SUB_TYPE_DM_NTP 3 +#define BKN_DNX_FTMH_ASE_TYPE_MSB 47 +#define BKN_DNX_FTMH_ASE_TYPE_NOF_BITS 1 +#define BKN_DNX_FTMH_ASE_TYPE_OAM 0 +/* TSH */ +#define BKN_DNX_TSH_SIZE 4 +/* PPH */ +#define BKN_DNX_INTERNAL_BASE_TYPE_9 9 +#define BKN_DNX_INTERNAL_BASE_TYPE_10 10 +#define BKN_DNX_INTERNAL_BASE_TYPE_12 12 +#define BKN_DNX_INTERNAL_9_FORWARD_DOMAIN_MSB 5 +#define BKN_DNX_INTERNAL_9_FORWARD_DOMAIN_NOF_BITS 16 +#define BKN_DNX_INTERNAL_9_LEARN_EXT_PRESENT_MSB 53 +#define BKN_DNX_INTERNAL_9_LEARN_EXT_PRESENT_NOF_BITS 1 +#define BKN_DNX_INTERNAL_9_FHEI_SIZE_MSB 54 +#define BKN_DNX_INTERNAL_9_FHEI_SIZE_NOF_BITS 2 +#define BKN_DNX_INTERNAL_9_LIF_EXT_TYPE_MSB 56 +#define BKN_DNX_INTERNAL_9_LIF_EXT_TYPE_NOF_BITS 3 +#define BKN_DNX_INTERNAL_10_FORWARD_DOMAIN_MSB 9 +#define BKN_DNX_INTERNAL_10_FORWARD_DOMAIN_NOF_BITS 16 +#define BKN_DNX_INTERNAL_10_LEARN_EXT_PRESENT_MSB 61 +#define BKN_DNX_INTERNAL_10_LEARN_EXT_PRESENT_NOF_BITS 1 +#define BKN_DNX_INTERNAL_10_FHEI_SIZE_MSB 62 +#define BKN_DNX_INTERNAL_10_FHEI_SIZE_NOF_BITS 2 +#define BKN_DNX_INTERNAL_10_LIF_EXT_TYPE_MSB 64 +#define BKN_DNX_INTERNAL_10_LIF_EXT_TYPE_NOF_BITS 3 +#define BKN_DNX_INTERNAL_12_FORWARD_DOMAIN_MSB 21 +#define BKN_DNX_INTERNAL_12_FORWARD_DOMAIN_NOF_BITS 18 +#define BKN_DNX_INTERNAL_12_LEARN_EXT_PRESENT_MSB 77 +#define BKN_DNX_INTERNAL_12_LEARN_EXT_PRESENT_NOF_BITS 1 +#define BKN_DNX_INTERNAL_12_FHEI_SIZE_MSB 78 +#define BKN_DNX_INTERNAL_12_FHEI_SIZE_NOF_BITS 2 +#define BKN_DNX_INTERNAL_12_LIF_EXT_TYPE_MSB 80 +#define BKN_DNX_INTERNAL_12_LIF_EXT_TYPE_NOF_BITS 3 +#define BKN_DNX_INTERNAL_12_PARSING_START_OFFSET_MSB 83 +#define BKN_DNX_INTERNAL_12_PARSING_START_OFFSET_NOF_BITS 7 +/* PPH.FHEI_TYPE */ +#define BKN_DNX_INTERNAL_FHEI_TYPE_SZ0 1 +#define BKN_DNX_INTERNAL_FHEI_TYPE_SZ1 2 +#define BKN_DNX_INTERNAL_FHEI_TYPE_SZ2 3 +/* FHEI */ +#define BKN_DNX_INTERNAL_FHEI_SZ0_SIZE 3 +#define BKN_DNX_INTERNAL_FHEI_SZ1_SIZE 5 +#define BKN_DNX_INTERNAL_FHEI_SZ2_SIZE 8 +#define BKN_DNX_INTERNAL_FHEI_TRAP_5B_QUALIFIER_MSB 0 +#define BKN_DNX_INTERNAL_FHEI_TRAP_5B_QUALIFIER_NOF_BITS 27 +#define BKN_DNX_INTERNAL_FHEI_TRAP_5B_CODE_MSB 27 +#define BKN_DNX_INTERNAL_FHEI_TRAP_5B_CODE_NOF_BITS 9 +#define BKN_DNX_INTERNAL_FHEI_TRAP_5B_TYPE_MSB 36 +#define BKN_DNX_INTERNAL_FHEI_TRAP_5B_TYPE_NOF_BITS 4 +/* PPH Extension */ +#define BKN_DNX_INTERNAL_LEARN_EXT_SIZE 19 +/* UDH */ +#define BKN_DNX_UDH_DATA_TYPE_0_MSB 0 +#define BKN_DNX_UDH_DATA_TYPE_0_NOF_BITS 2 +#define BKN_DNX_UDH_DATA_TYPE_1_MSB 2 +#define BKN_DNX_UDH_DATA_TYPE_1_NOF_BITS 2 +#define BKN_DNX_UDH_DATA_TYPE_2_MSB 4 +#define BKN_DNX_UDH_DATA_TYPE_2_NOF_BITS 2 +#define BKN_DNX_UDH_DATA_TYPE_3_MSB 6 +#define BKN_DNX_UDH_DATA_TYPE_3_NOF_BITS 2 +#define BKN_DNX_UDH_BASE_SIZE 1 +/* TOD SECOND header */ +#define BKN_DNX_TOD_SECOND_SIZE 4 +/* OIBIH */ +#define BKN_DNX_OIBIH_SIZE 14 +#define BKN_DNX_OIBIH_OAM_PDU_OFFSET_MSB 104 +#define BKN_DNX_OIBIH_OAM_PDU_OFFSET_NOF_BITS 8 + + +/* PPH fwd_domain type. */ +#define BKN_DNX_PPH_FWD_DOMAIN_TYPE_VSI 0 +#define BKN_DNX_PPH_FWD_DOMAIN_TYPE_VRF 3 + +#define BKN_DNX_PPH_FWD_DOMAIN_TYPE_GET(_fwd_domain) (((_fwd_domain) >> 16) & 0x3) +#define BKN_DNX_PPH_FWD_DOMAIN_ID_GET(_fwd_domain) ((_fwd_domain) & 0xffff) +#define BKN_DNX_PPH_FWD_DOMAIN_IS_VSI(_fwd_domain) (BKN_DNX_PPH_FWD_DOMAIN_TYPE_GET(_fwd_domain) == BKN_DNX_PPH_FWD_DOMAIN_TYPE_VSI) +#define BKN_DNX_PPH_FWD_DOMAIN_IS_VRF(_fwd_domain) (BKN_DNX_PPH_FWD_DOMAIN_TYPE_GET(_fwd_domain) == BKN_DNX_PPH_FWD_DOMAIN_TYPE_VRF) + +#define BKN_DNX_INGRESS_TRAP_ID_TRAP_OAM_LEVEL (162) +#define BKN_DNX_INGRESS_TRAP_ID_TRAP_OAM_PASSIVE (172) + +#define BKN_DNX_SPA_MODE_16_BITS (0) +#define BKN_DNX_SPA_MODE_17_BITS (1) +#define BKN_DNX_SPA_MODE_18_BITS (2) + +/* ftmh action type. */ +typedef enum bkn_dpp_ftmh_action_type_e { + BKN_DPP_FTMH_ACTION_TYPE_FORWARD = 0, /* TM action is forward */ + BKN_DPP_FTMH_ACTION_TYPE_SNOOP = 1, /* TM action is snoop */ + BKN_DPP_FTMH_ACTION_TYPE_INBOUND_MIRROR = 2, /* TM action is inbound mirror. */ + BKN_DPP_FTMH_ACTION_TYPE_OUTBOUND_MIRROR = 3 /* TM action is outbound mirror. */ +}bkn_dpp_ftmh_action_type_t; + +/* ftmh dest extension. */ +typedef struct bkn_dpp_ftmh_dest_extension_s { + uint8_t valid; /* Set if the extension is present */ + uint32_t dst_sys_port; /* Destination System Port */ +} bkn_dpp_ftmh_dest_extension_t; + +/* dnx packet */ +typedef struct bkn_dune_system_header_info_s { + uint32_t system_header_size; + struct { + uint32_t tc; /* traffic class */ + uint32_t action_type; /* Indicates if the copy is one of the Forward Snoop or Mirror packet copies */ + uint32_t source_sys_port_aggregate; /* Source System port*/ + } ftmh; + struct { + uint32_t parsing_start_offset; + uint32_t forward_domain; + uint32_t trap_qualifier; + uint32_t trap_id; + } internal; + /** Flags for RX header parser */ + /** Indicates whether 1st system header is following */ +#define BKN_RX_HEADER_F_HAS_ONE_SYSTEM_HEADER (0x1 << 0) + /** Indicates whether 2nd system header is following */ +#define BKN_RX_HEADER_F_HAS_TWO_SYSTEM_HEADER (0x1 << 1) + /** Indicates whether TSH is following */ +#define BKN_RX_HEADER_F_HAS_TSH (0x1 << 2) + /** Indicates whether OTSH is following */ +#define BKN_RX_HEADER_F_HAS_OTSH (0x1 << 3) + /** Indicates whether internal header is following */ +#define BKN_RX_HEADER_F_HAS_INTERNAL_HEADER (0x1 << 4) + /** Indicates whether TOD second header is following */ +#define BKN_RX_HEADER_F_HAS_OAM_DM_TOD_SECOND (0x1 << 5) + uint32_t flags; +} bkn_dune_system_header_info_t; + +#define BKN_DNX_BIT(x) (1<<(x)) +#define BKN_DNX_RBIT(x) (~(1<<(x))) +#ifdef __LITTLE_ENDIAN +#define BKN_DNX_BYTE_SWAP(x) (x) +#else +#define BKN_DNX_BYTE_SWAP(x) ((((x) << 24)) | (((x) & 0xff00) << 8) | (((x) & 0xff0000) >> 8) | (((x) >> 24))) +#endif + +static void +bkn_bitstream_set_field(uint32_t *input_buffer, uint32_t start_bit, uint32_t nof_bits, uint32_t field) +{ + uint32_t place; + uint32_t field_bit_i; + uint32_t bit_indicator; + + if( nof_bits > 32) + { + return; + } + + for( place=start_bit, field_bit_i = 0; field_bit_i< nof_bits; ++place, ++field_bit_i) + { + bit_indicator = field & BKN_DNX_BIT(nof_bits-field_bit_i-1); + if(bit_indicator) + { + input_buffer[place>>5] |= (0x80000000 >> (place & 0x0000001F)); + } + else + { + input_buffer[place>>5] &= ~(0x80000000 >> (place & 0x0000001F)); + } + } + return; +} + +static void +bkn_bitstream_get_field(uint8_t *input_buffer, uint32_t start_bit, uint32_t nof_bits, uint32_t *output_value) +{ + uint32_t idx; + uint32_t buf_sizes=0; + uint32_t tmp_output_value[2]={0}; + uint32_t first_byte_ndx; + uint32_t last_byte_ndx; + uint32_t place; + uint32_t field_bit_i; + uint8_t *tmp_output_value_u8_ptr = (uint8_t*)&tmp_output_value; + uint32_t bit_indicator; + + if (nof_bits > 32) + { + return; + } + + first_byte_ndx = start_bit / 8; + last_byte_ndx = ((start_bit + nof_bits - 1) / 8); + *output_value=0; + + /* get 32 bit value, MSB */ + for (idx = first_byte_ndx; idx <= last_byte_ndx; ++idx) + { + tmp_output_value_u8_ptr[last_byte_ndx - idx] = input_buffer[idx]; + buf_sizes += 8; + } + tmp_output_value[0] = BKN_DNX_BYTE_SWAP(tmp_output_value[0]); + if (last_byte_ndx > 4) + { + tmp_output_value[1] = BKN_DNX_BYTE_SWAP(tmp_output_value[1]); + } + + place = buf_sizes - (start_bit % 8 + nof_bits); + for (field_bit_i = 0; field_bit_i< nof_bits; ++place, ++field_bit_i) + { + uint32_t result; + result = tmp_output_value[place>>5] & BKN_DNX_BIT(place & 0x0000001F); + if (result) + { + bit_indicator = 1; + } else { + bit_indicator = 0; + } + *output_value |= bit_indicator << field_bit_i; + } + return; +} + +static int +bkn_dnx_packet_parse_ftmh( + struct adapter_dev *adev, + uint8_t *buf, + uint32_t buf_len, + bkn_dune_system_header_info_t *packet_info) +{ + uint32_t fld_val; + uint32_t pkt_offset = packet_info->system_header_size; + uint8_t tm_dst_ext_present = 0; + uint8_t app_specific_ext_size = 0; + uint8_t flow_id_ext_size = 0; + uint8_t bier_bfr_ext_size = 0; + + if ((adev == NULL) || (buf == NULL) || (packet_info == NULL)) { + return -1; + } + + /* FTMH: Traffic-Class */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_TC_MSB, + BKN_DNX_FTMH_TC_NOF_BITS, + &fld_val); + packet_info->ftmh.tc = fld_val; + /* FTMH: Source-System-Port-Aggregate */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_SRC_SYS_PORT_AGGREGATE_MSB, + BKN_DNX_FTMH_SRC_SYS_PORT_AGGREGATE_NOF_BITS, + &fld_val); + packet_info->ftmh.source_sys_port_aggregate = fld_val; + /* FTMH: Action-Type */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_ACTION_TYPE_MSB, + BKN_DNX_FTMH_ACTION_TYPE_NOF_BITS, + &fld_val); + packet_info->ftmh.action_type = fld_val; + /* FTMH: PPH-Type TSH */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_PPH_TYPE_IS_TSH_EN_MSB, + BKN_DNX_FTMH_PPH_TYPE_IS_TSH_EN_NOF_BITS, + &fld_val); + packet_info->flags |= fld_val ? BKN_RX_HEADER_F_HAS_TSH : 0; + /* FTMH: PPH-Type PPH base */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_PPH_TYPE_IS_PPH_EN_MSB, + BKN_DNX_FTMH_PPH_TYPE_IS_PPH_EN_NOF_BITS, + &fld_val); + packet_info->flags |= fld_val ? BKN_RX_HEADER_F_HAS_INTERNAL_HEADER : 0; + /* FTMH: TM-Destination-Extension-Present */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_TM_DST_EXT_PRESENT_MSB, + BKN_DNX_FTMH_TM_DST_EXT_PRESENT_NOF_BITS, + &fld_val); + tm_dst_ext_present = fld_val; + /* FTMH: Application-Specific-Extension-Size */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_APP_SPECIFIC_EXT_SIZE_MSB, + BKN_DNX_FTMH_APP_SPECIFIC_EXT_SIZE_NOF_BITS, + &fld_val); + app_specific_ext_size = fld_val; + /* FTMH: Flow-ID-Extension-Size */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_FLOW_ID_EXT_SIZE_MSB, + BKN_DNX_FTMH_FLOW_ID_EXT_SIZE_NOF_BITS, + &fld_val); + flow_id_ext_size = fld_val; + /* FTMH: BIER-BFR-Extension-Size */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_BIER_BFR_EXT_SIZE_MSB, + BKN_DNX_FTMH_BIER_BFR_EXT_SIZE_NOF_BITS, + &fld_val); + bier_bfr_ext_size = fld_val; + + pkt_offset += BKN_DNX_FTMH_BASE_SIZE; + + DBG_VERB(("FTMH(10-%u): traffic-class %u source-system-port 0x%x action_type %u\n", + pkt_offset, packet_info->ftmh.tc, packet_info->ftmh.source_sys_port_aggregate, + packet_info->ftmh.action_type)); + + /* FTMH LB-Key Extension */ + if (adev->rsi.ftmh_lb_key_size > 0) + { + pkt_offset += adev->rsi.ftmh_lb_key_size; + DBG_VERB(("FTMH LB-Key Extension(%u-%u) is present\n", adev->rsi.ftmh_lb_key_size, pkt_offset)); + } + /* FTMH Stacking Extension */ + if (adev->rsi.ftmh_stacking_ext_size > 0) + { + pkt_offset += adev->rsi.ftmh_stacking_ext_size; + DBG_VERB(("FTMH Stacking Extension(%u-%u) is present\n", adev->rsi.ftmh_stacking_ext_size, pkt_offset)); + } + if (adev->rsi.spa_mode == BKN_DNX_SPA_MODE_16_BITS) + { + /* FTMH BIER BFR Extension */ + if (bier_bfr_ext_size > 0) + { + pkt_offset += BKN_DNX_FTMH_BIER_BFR_EXT_SIZE; + DBG_VERB(("FTMH BIER BFR Extension(2-%u) is present\n", pkt_offset)); + } + } + if (adev->rsi.spa_mode == BKN_DNX_SPA_MODE_16_BITS) + { + /* FTMH TM Destination Extension */ + if (tm_dst_ext_present > 0) + { + pkt_offset += BKN_DNX_FTMH_TM_DST_EXT_SIZE; + DBG_VERB(("FTMH TM Destination Extension(3-%u) is present\n", pkt_offset)); + } + } + if (adev->rsi.spa_mode == BKN_DNX_SPA_MODE_18_BITS) + { + packet_info->ftmh.source_sys_port_aggregate |= (tm_dst_ext_present ? 1:0) << 16; + packet_info->ftmh.source_sys_port_aggregate |= (bier_bfr_ext_size ? 1:0) << 17; + DBG_VERB(("FTMH(10): source-system-port(18b) 0x%x\n", packet_info->ftmh.source_sys_port_aggregate)); + } + /* FTMH Application Specific Extension */ + if (app_specific_ext_size > 0) + { + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_ASE_TYPE_MSB, + BKN_DNX_FTMH_ASE_TYPE_NOF_BITS, + &fld_val); + if (fld_val == BKN_DNX_FTMH_ASE_TYPE_OAM) { + /* ASE: OAM_SUB_TYPE */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_ASE_OAM_SUB_TYPE_MSB, + BKN_DNX_FTMH_ASE_OAM_SUB_TYPE_NOF_BITS, + &fld_val); + if ((fld_val == BKN_DNX_FTMH_ASE_OAM_SUB_TYPE_DM_1588) || + (fld_val == BKN_DNX_FTMH_ASE_OAM_SUB_TYPE_DM_NTP)) { + packet_info->flags |= BKN_RX_HEADER_F_HAS_OAM_DM_TOD_SECOND; + } + } + pkt_offset += BKN_DNX_FTMH_APP_SPECIFIC_EXT_SIZE; + DBG_VERB(("FTMH Application Specific Extension(6-%u) is present\n", pkt_offset)); + } + /* FTMH Flow-ID Extension */ + if (flow_id_ext_size > 0) + { + pkt_offset += BKN_DNX_FTMH_FLOW_ID_EXT_SIZE; + DBG_VERB(("FTMH Flow-ID Extension(3-%u) is present\n", pkt_offset)); + } + DBG_VERB(("FTMH flags = 0x%08x\n", packet_info->flags)); + + packet_info->system_header_size = pkt_offset; + + return 0; +} + + +static int +bkn_dnx_packet_parse_internal( + struct adapter_dev *adev, + uint8_t *buf, + uint32_t buf_len, + bkn_dune_system_header_info_t *packet_info, + uint8_t is_oamp_punted, + uint8_t *is_trapped) +{ + uint32_t fld_val; + uint32_t pkt_offset = packet_info->system_header_size; + uint8_t learn_ext_present; + uint8_t fhei_size; + uint8_t lif_ext_type; + uint8_t udh_en = adev->rsi.udh_enabled; + + if ((adev == NULL) || (buf == NULL) || (packet_info == NULL)) { + return -1; + } + + /* Internal: Forward-Domain */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_INTERNAL_12_FORWARD_DOMAIN_MSB, + BKN_DNX_INTERNAL_12_FORWARD_DOMAIN_NOF_BITS, + &fld_val); + packet_info->internal.forward_domain = fld_val; + /* Internal: Learn-Extension-Present */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_INTERNAL_12_LEARN_EXT_PRESENT_MSB, + BKN_DNX_INTERNAL_12_LEARN_EXT_PRESENT_NOF_BITS, + &fld_val); + learn_ext_present = fld_val; + /* Internal: FHEI-Size */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_INTERNAL_12_FHEI_SIZE_MSB, + BKN_DNX_INTERNAL_12_FHEI_SIZE_NOF_BITS, + &fld_val); + fhei_size = fld_val; + /* Internal: LIF-Extension-Type */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_INTERNAL_12_LIF_EXT_TYPE_MSB, + BKN_DNX_INTERNAL_12_LIF_EXT_TYPE_NOF_BITS, + &fld_val); + lif_ext_type = fld_val; + + /* Internal: Parsing-Start-Offset */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_INTERNAL_12_PARSING_START_OFFSET_MSB, + BKN_DNX_INTERNAL_12_PARSING_START_OFFSET_NOF_BITS, + &fld_val); + packet_info->internal.parsing_start_offset = fld_val; + + pkt_offset += BKN_DNX_INTERNAL_BASE_TYPE_12; + DBG_VERB(("Internal(12-%u): FWD_DOMAIN 0x%x(%d,%d), LEARN_EXT %d, FHEI_SIZE %d, LIF_EXT %d \n", + pkt_offset, packet_info->internal.forward_domain, + BKN_DNX_PPH_FWD_DOMAIN_TYPE_GET(packet_info->internal.forward_domain), + BKN_DNX_PPH_FWD_DOMAIN_ID_GET(packet_info->internal.forward_domain), + learn_ext_present, fhei_size, lif_ext_type)); + + if (fhei_size) + { + switch (fhei_size) + { + case BKN_DNX_INTERNAL_FHEI_TYPE_SZ0: + pkt_offset += BKN_DNX_INTERNAL_FHEI_SZ0_SIZE; + DBG_VERB(("FHEI(3-%u) is present\n", pkt_offset)); + break; + case BKN_DNX_INTERNAL_FHEI_TYPE_SZ1: + /* FHEI: Type */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_INTERNAL_FHEI_TRAP_5B_TYPE_MSB, + BKN_DNX_INTERNAL_FHEI_TRAP_5B_TYPE_NOF_BITS, + &fld_val); + /* FHEI-Size == 5B, FHEI-Type == Trap/Sniff */ + if (fld_val == 0x5) + { + /* Action_Type: 0-Forward, 1-Snoop, 2-Mirror, 3-StatisticalSampling */ + if (!packet_info->ftmh.action_type) { + *is_trapped = TRUE; + } + /* FHEI: Qualifier */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_INTERNAL_FHEI_TRAP_5B_QUALIFIER_MSB, + BKN_DNX_INTERNAL_FHEI_TRAP_5B_QUALIFIER_NOF_BITS, + &fld_val); + packet_info->internal.trap_qualifier = fld_val; + /* FHEI: Code */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_INTERNAL_FHEI_TRAP_5B_CODE_MSB, + BKN_DNX_INTERNAL_FHEI_TRAP_5B_CODE_NOF_BITS, + &fld_val); + packet_info->internal.trap_id= fld_val; + } + pkt_offset += BKN_DNX_INTERNAL_FHEI_SZ1_SIZE; + DBG_VERB(("FHEI(5-%u): code 0x%x qualifier 0x%x\n", pkt_offset, packet_info->internal.trap_id, packet_info->internal.trap_qualifier)); + break; + case BKN_DNX_INTERNAL_FHEI_TYPE_SZ2: + pkt_offset += BKN_DNX_INTERNAL_FHEI_SZ2_SIZE; + DBG_VERB(("FHEI(8-%u) is present\n", pkt_offset)); + break; + } + } + + /* PPH LIF Extension */ + if (lif_ext_type) + { + pkt_offset += adev->rsi.pph_lif_ext_size[lif_ext_type]; + DBG_VERB(("PPH LIF Extension(%d-%u) is present\n", adev->rsi.pph_lif_ext_size[lif_ext_type], pkt_offset)); + } + + /* PPH Learn Extension */ + if (learn_ext_present) + { + pkt_offset += BKN_DNX_INTERNAL_LEARN_EXT_SIZE; + DBG_VERB(("PPH Learn Extension(19-%u) is present\n", pkt_offset)); + } + + /** Skip UDH If packet is punted to CPU by OAMP */ + if (is_oamp_punted) { + udh_en = FALSE; + } + + /* OAM DMM/DMR TOD second header: PPH+TOD+UDH */ + if (packet_info->flags & BKN_RX_HEADER_F_HAS_ONE_SYSTEM_HEADER) { + if (packet_info->flags & BKN_RX_HEADER_F_HAS_OAM_DM_TOD_SECOND) { + pkt_offset += BKN_DNX_TOD_SECOND_SIZE; + if (packet_info->internal.parsing_start_offset >= BKN_DNX_TOD_SECOND_SIZE) { + packet_info->internal.parsing_start_offset -= BKN_DNX_TOD_SECOND_SIZE; + } + DBG_VERB(("TOD second Header(4-%u) is present\n", pkt_offset)); + } + } + + /* UDH Header */ + if (udh_en) + { + uint8_t data_type_0; + uint8_t data_type_1; + uint8_t data_type_2; + uint8_t data_type_3; + + if (ADAPTER_IS_CMICR(adev)) + { + /* UDH: UDH-Data-Type[3] */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_UDH_DATA_TYPE_0_MSB, + BKN_DNX_UDH_DATA_TYPE_0_NOF_BITS, + &fld_val); + data_type_3 = fld_val; + /* UDH: UDH-Data-Type[2] */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_UDH_DATA_TYPE_1_MSB, + BKN_DNX_UDH_DATA_TYPE_1_NOF_BITS, + &fld_val); + data_type_2 = fld_val; + /* UDH: UDH-Data-Type[1] */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_UDH_DATA_TYPE_2_MSB, + BKN_DNX_UDH_DATA_TYPE_2_NOF_BITS, + &fld_val); + data_type_1 = fld_val; + /* UDH: UDH-Data-Type[0] */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_UDH_DATA_TYPE_3_MSB, + BKN_DNX_UDH_DATA_TYPE_3_NOF_BITS, + &fld_val); + data_type_0 = fld_val; + pkt_offset += BKN_DNX_UDH_BASE_SIZE; + + if (data_type_0) + { + pkt_offset += adev->rsi.udh_length_type[0]; + } + if (data_type_1) + { + pkt_offset += adev->rsi.udh_length_type[1]; + } + if (data_type_2) + { + pkt_offset += adev->rsi.udh_length_type[2]; + } + if (data_type_3) + { + pkt_offset += adev->rsi.udh_length_type[3]; + } + } + else + { + /* UDH: UDH-Data-Type[0] */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_UDH_DATA_TYPE_0_MSB, + BKN_DNX_UDH_DATA_TYPE_0_NOF_BITS, + &fld_val); + data_type_0 = fld_val; + /* UDH: UDH-Data-Type[1] */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_UDH_DATA_TYPE_1_MSB, + BKN_DNX_UDH_DATA_TYPE_1_NOF_BITS, + &fld_val); + data_type_1 = fld_val; + /* UDH: UDH-Data-Type[2] */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_UDH_DATA_TYPE_2_MSB, + BKN_DNX_UDH_DATA_TYPE_2_NOF_BITS, + &fld_val); + data_type_2 = fld_val; + /* UDH: UDH-Data-Type[3] */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_UDH_DATA_TYPE_3_MSB, + BKN_DNX_UDH_DATA_TYPE_3_NOF_BITS, + &fld_val); + data_type_3 = fld_val; + pkt_offset += BKN_DNX_UDH_BASE_SIZE; + + pkt_offset += adev->rsi.udh_length_type[data_type_0]; + pkt_offset += adev->rsi.udh_length_type[data_type_1]; + pkt_offset += adev->rsi.udh_length_type[data_type_2]; + pkt_offset += adev->rsi.udh_length_type[data_type_3]; + } + DBG_VERB(("UDH base(1-%u) is present\n", pkt_offset)); + } + + packet_info->system_header_size = pkt_offset; + + return 0; +} + +static int +bkn_dnx_packet_parse_header( + struct adapter_dev *adev, + uint8_t *buff, + uint32_t buff_len, + bkn_dune_system_header_info_t *packet_info) +{ + uint8_t is_oamp_punted = FALSE; + uint8_t is_trapped = FALSE; + uint8_t idx = 0; + uint8_t is_2_system_header_from_trap = FALSE; + uint32_t cpu_trap_qualifier; + + if ((adev == NULL) || (buff == NULL) || (packet_info == NULL)) { + return -1; + } + + packet_info->flags = BKN_RX_HEADER_F_HAS_ONE_SYSTEM_HEADER; + /* FTMH */ + bkn_dnx_packet_parse_ftmh(adev, buff, buff_len, packet_info); + + /* Time-Stamp */ + if (packet_info->flags & BKN_RX_HEADER_F_HAS_TSH) + { + packet_info->system_header_size += BKN_DNX_TSH_SIZE; + DBG_VERB(("Time-Stamp Header(4-%u) is present\n", packet_info->system_header_size)); + } + + /* Check if packet was punted to CPU by OAMP */ + for (idx = 0; idx < adev->rsi.oamp_port_number; idx++) + { + if (packet_info->ftmh.source_sys_port_aggregate == adev->rsi.oamp_ports[idx]) + { + is_oamp_punted = TRUE; + break; + } + } + + /* Internal */ + if (packet_info->flags & BKN_RX_HEADER_F_HAS_INTERNAL_HEADER) + { + bkn_dnx_packet_parse_internal(adev, buff, buff_len, packet_info, is_oamp_punted, &is_trapped); + } + + cpu_trap_qualifier = packet_info->internal.trap_qualifier & 0xffff; + + if (is_trapped && cpu_trap_qualifier == 0) + { + /* + * For egress trap such as oam up mep destination 1, oam level error + * and down mep passive, the trapped packet might have 2 sets of system header + */ + switch (packet_info->internal.trap_id) + { + case BKN_DNX_INGRESS_TRAP_ID_TRAP_OAM_LEVEL: + case BKN_DNX_INGRESS_TRAP_ID_TRAP_OAM_PASSIVE: + is_2_system_header_from_trap = TRUE; + break; + default: + /** Get ingress cpu trap id of oam up mep destination 1. */ + if (adev->rsi.up_mep_ingress_cpu_trap_id1 == packet_info->internal.trap_id) + { + is_2_system_header_from_trap = TRUE; + break; + } + if (adev->rsi.system_headers_mode == BKN_DNX_JR2_MODE) + { + /** Get ingress cpu trap id of oam up mep destination 2. */ + if (adev->rsi.up_mep_ingress_cpu_trap_id2 == packet_info->internal.trap_id) + { + is_2_system_header_from_trap = TRUE; + break; + } + } + } + } + + if ((is_oamp_punted && is_trapped) || is_2_system_header_from_trap) + { + uint32_t oibih_oam_pdu_offset = 0; + is_trapped = FALSE; + + packet_info->flags = BKN_RX_HEADER_F_HAS_TWO_SYSTEM_HEADER; + if (ADAPTER_IS_CMICR(adev)) + { + if (is_oamp_punted) + { + /* OIBIH: OAM_PDU_Offset */ + bkn_bitstream_get_field( + &buff[packet_info->system_header_size], + BKN_DNX_OIBIH_OAM_PDU_OFFSET_MSB, + BKN_DNX_OIBIH_OAM_PDU_OFFSET_NOF_BITS, + &oibih_oam_pdu_offset); + packet_info->system_header_size += BKN_DNX_OIBIH_SIZE; + DBG_VERB(("OIBIH Header(14-%u) is present\n", packet_info->system_header_size)); + } + } + /* FTMH */ + bkn_dnx_packet_parse_ftmh(adev, buff, buff_len, packet_info); + /* Time-Stamp */ + if (packet_info->flags & BKN_RX_HEADER_F_HAS_TSH) + { + packet_info->system_header_size += BKN_DNX_TSH_SIZE; + DBG_VERB(("Time-Stamp Header(4-%u) is present\n", packet_info->system_header_size)); + } + /* Internal */ + if (packet_info->flags & BKN_RX_HEADER_F_HAS_INTERNAL_HEADER) + { + bkn_dnx_packet_parse_internal(adev, buff, buff_len, packet_info, FALSE, &is_trapped); + } + if (oibih_oam_pdu_offset) + { + /* + * parsing_start_offset indicates the bytes before OAM PDU including PTCH, etc. For example, it's the length of PTCH + ETH1 + * oibih_oam_pdu_offset indicates the bytes from the end of system headers to OAM PDU. For example, it's the length of ETH1 + */ + if (packet_info->internal.parsing_start_offset > oibih_oam_pdu_offset) + { + packet_info->system_header_size += (packet_info->internal.parsing_start_offset - oibih_oam_pdu_offset); + DBG_VERB(("Offset after system headers %u\n", (packet_info->internal.parsing_start_offset - oibih_oam_pdu_offset))); + } + } + } + else + { + /* + * J2,J3 devices does not have PTCH header. NO need to calculate parsing_start_offset. + * The future devices will have PTCH header. Should consider how to calculate the Eth + * header position. + */ + if (packet_info->internal.parsing_start_offset && ADAPTER_IS_CMICR(adev)) + { + packet_info->system_header_size += packet_info->internal.parsing_start_offset; + DBG_VERB(("Offset after system headers %u\n", packet_info->internal.parsing_start_offset)); + } + } + + DBG_VERB(("Total length of headers is %u (0x%x)\n", packet_info->system_header_size, packet_info->system_header_size)); + + return 0; +} + +static int +bkn_dnx_packet_parse_ai_ftmh( + struct adapter_dev *adev, + uint8_t *buf, + uint32_t buf_len, + bkn_dune_system_header_info_t *packet_info) +{ + uint32_t fld_val; + uint32_t pkt_offset = packet_info->system_header_size; + uint8_t app_specific_ext_size = 0; + + if ((adev == NULL) || (buf == NULL) || (packet_info == NULL)) { + return -1; + } + + /* FTMH: Traffic-Class */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_TC_MSB, + BKN_DNX_FTMH_TC_NOF_BITS, + &fld_val); + packet_info->ftmh.tc = fld_val; + /* FTMH: Source-System-Port-Aggregate */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_SRC_SYS_PORT_AGGREGATE_MSB, + BKN_DNX_FTMH_SRC_SYS_PORT_AGGREGATE_NOF_BITS, + &fld_val); + packet_info->ftmh.source_sys_port_aggregate = fld_val; + /* FTMH: Action-Type */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_ACTION_TYPE_MSB, + BKN_DNX_FTMH_ACTION_TYPE_NOF_BITS, + &fld_val); + packet_info->ftmh.action_type = fld_val; + /* FTMH: PPH-Type TSH */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_PPH_TYPE_IS_TSH_EN_MSB, + BKN_DNX_FTMH_PPH_TYPE_IS_TSH_EN_NOF_BITS, + &fld_val); + packet_info->flags |= fld_val ? BKN_RX_HEADER_F_HAS_TSH : 0; + /* FTMH: PPH-Type PPH base */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_PPH_TYPE_IS_PPH_EN_MSB, + BKN_DNX_FTMH_PPH_TYPE_IS_PPH_EN_NOF_BITS, + &fld_val); + packet_info->flags |= fld_val ? BKN_RX_HEADER_F_HAS_INTERNAL_HEADER : 0; + /* FTMH: Application-Specific-Extension-Size */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_FTMH_APP_SPECIFIC_EXT_SIZE_MSB, + BKN_DNX_FTMH_APP_SPECIFIC_EXT_SIZE_NOF_BITS, + &fld_val); + app_specific_ext_size = fld_val; + + pkt_offset += BKN_DNX_FTMH_BASE_SIZE; + + DBG_VERB(("FTMH(10-%u): traffic-class %u source-system-port 0x%x action_type %u\n", + pkt_offset, packet_info->ftmh.tc, packet_info->ftmh.source_sys_port_aggregate, + packet_info->ftmh.action_type)); + + /* FTMH LB-Key Extension */ + if (adev->rsi.ftmh_lb_key_size > 0) + { + pkt_offset += adev->rsi.ftmh_lb_key_size; + DBG_VERB(("FTMH LB-Key Extension(%u-%u) is present\n", adev->rsi.ftmh_lb_key_size, pkt_offset)); + } + /* FTMH Application Specific Extension */ + if (app_specific_ext_size > 0) + { + pkt_offset += BKN_DNX_FTMH_APP_SPECIFIC_EXT_SIZE; + DBG_VERB(("FTMH Application Specific Extension(6-%u) is present\n", pkt_offset)); + } + + DBG_VERB(("FTMH flags = 0x%08x\n", packet_info->flags)); + + packet_info->system_header_size = pkt_offset; + + return 0; +} + + +static int +bkn_dnx_packet_parse_ai_internal( + struct adapter_dev *adev, + uint8_t *buf, + uint32_t buf_len, + bkn_dune_system_header_info_t *packet_info, + uint8_t is_oamp_punted, + uint8_t *is_trapped) +{ + uint32_t fld_val; + uint32_t pkt_offset = packet_info->system_header_size; + uint8_t fhei_size; + uint8_t udh_en = adev->rsi.udh_enabled; + + if ((adev == NULL) || (buf == NULL) || (packet_info == NULL)) { + return -1; + } + /* Internal: FHEI-Size */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_INTERNAL_12_FHEI_SIZE_MSB, + BKN_DNX_INTERNAL_12_FHEI_SIZE_NOF_BITS, + &fld_val); + fhei_size = fld_val; + + /* Internal: PPH base */ + pkt_offset += BKN_DNX_INTERNAL_BASE_TYPE_12; + DBG_VERB(("Internal(12-%u): FHEI_SIZE %d \n", pkt_offset, fhei_size)); + + if (fhei_size) + { + switch (fhei_size) + { + case BKN_DNX_INTERNAL_FHEI_TYPE_SZ0: + pkt_offset += BKN_DNX_INTERNAL_FHEI_SZ0_SIZE; + DBG_VERB(("FHEI(3-%u) is present\n", pkt_offset)); + break; + case BKN_DNX_INTERNAL_FHEI_TYPE_SZ1: + /* FHEI: Type */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_INTERNAL_FHEI_TRAP_5B_TYPE_MSB, + BKN_DNX_INTERNAL_FHEI_TRAP_5B_TYPE_NOF_BITS, + &fld_val); + /* FHEI-Size == 5B, FHEI-Type == Trap/Sniff */ + if (fld_val == 0x5) + { + /* Action_Type: 0-Forward, 1-Snoop, 2-Mirror, 3-StatisticalSampling */ + if (!packet_info->ftmh.action_type) { + *is_trapped = TRUE; + } + /* FHEI: Qualifier */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_INTERNAL_FHEI_TRAP_5B_QUALIFIER_MSB, + BKN_DNX_INTERNAL_FHEI_TRAP_5B_QUALIFIER_NOF_BITS, + &fld_val); + packet_info->internal.trap_qualifier = fld_val; + /* FHEI: Code */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_INTERNAL_FHEI_TRAP_5B_CODE_MSB, + BKN_DNX_INTERNAL_FHEI_TRAP_5B_CODE_NOF_BITS, + &fld_val); + packet_info->internal.trap_id= fld_val; + } + pkt_offset += BKN_DNX_INTERNAL_FHEI_SZ1_SIZE; + DBG_VERB(("FHEI(5-%u): code 0x%x qualifier 0x%x\n", pkt_offset, packet_info->internal.trap_id, packet_info->internal.trap_qualifier)); + break; + case BKN_DNX_INTERNAL_FHEI_TYPE_SZ2: + pkt_offset += BKN_DNX_INTERNAL_FHEI_SZ2_SIZE; + DBG_VERB(("FHEI(8-%u) is present\n", pkt_offset)); + break; + } + } + + /* UDH Header */ + if (udh_en) + { + uint8_t data_type_0; + uint8_t data_type_1; + uint8_t data_type_2; + uint8_t data_type_3; + + if (ADAPTER_IS_CMICR(adev)) + { + /* UDH: UDH-Data-Type[3] */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_UDH_DATA_TYPE_0_MSB, + BKN_DNX_UDH_DATA_TYPE_0_NOF_BITS, + &fld_val); + data_type_3 = fld_val; + /* UDH: UDH-Data-Type[2] */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_UDH_DATA_TYPE_1_MSB, + BKN_DNX_UDH_DATA_TYPE_1_NOF_BITS, + &fld_val); + data_type_2 = fld_val; + /* UDH: UDH-Data-Type[1] */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_UDH_DATA_TYPE_2_MSB, + BKN_DNX_UDH_DATA_TYPE_2_NOF_BITS, + &fld_val); + data_type_1 = fld_val; + /* UDH: UDH-Data-Type[0] */ + bkn_bitstream_get_field( + &buf[pkt_offset], + BKN_DNX_UDH_DATA_TYPE_3_MSB, + BKN_DNX_UDH_DATA_TYPE_3_NOF_BITS, + &fld_val); + data_type_0 = fld_val; + pkt_offset += BKN_DNX_UDH_BASE_SIZE; + + if (data_type_0) + { + pkt_offset += adev->rsi.udh_length_type[0]; + } + if (data_type_1) + { + pkt_offset += adev->rsi.udh_length_type[1]; + } + if (data_type_2) + { + pkt_offset += adev->rsi.udh_length_type[2]; + } + if (data_type_3) + { + pkt_offset += adev->rsi.udh_length_type[3]; + } + } + DBG_VERB(("UDH base(1-%u) is present\n", pkt_offset)); + } + + packet_info->system_header_size = pkt_offset; + + return 0; +} + +static int +bkn_dnx_packet_parse_ai_header( + struct adapter_dev *adev, + uint8_t *buff, + uint32_t buff_len, + bkn_dune_system_header_info_t *packet_info) +{ + uint8_t is_oamp_punted = FALSE; + uint8_t is_trapped = FALSE; + + if ((adev == NULL) || (buff == NULL) || (packet_info == NULL)) { + return -1; + } + + packet_info->flags = BKN_RX_HEADER_F_HAS_ONE_SYSTEM_HEADER; + /* FTMH */ + bkn_dnx_packet_parse_ai_ftmh(adev, buff, buff_len, packet_info); + + /* Time-Stamp */ + if (packet_info->flags & BKN_RX_HEADER_F_HAS_TSH) + { + packet_info->system_header_size += BKN_DNX_TSH_SIZE; + DBG_VERB(("Time-Stamp Header(4-%u) is present\n", packet_info->system_header_size)); + } + + /* Internal */ + if (packet_info->flags & BKN_RX_HEADER_F_HAS_INTERNAL_HEADER) + { + bkn_dnx_packet_parse_ai_internal(adev, buff, buff_len, packet_info, is_oamp_punted, &is_trapped); + } + + DBG_VERB(("Total length of headers is %u (0x%x)\n", packet_info->system_header_size, packet_info->system_header_size)); + + return 0; +} + +static void +bkn_dnx_scratch_data_generate( + struct adapter_dev *adev, + struct sk_buff *skb, + bkn_dune_system_header_info_t *packet_info, + int queue_id, + uint32_t *sand_scratch_data) +{ + struct pdma_dev *pdev = adev->pdma_dev; + struct dev_ctrl *ctrl = &pdev->ctrl; + struct queue_group *grp = NULL; + struct pdma_rx_queue *rxq = NULL; + uint32_t *ring = NULL, *dcb = NULL; + struct pdma_rx_buf *pbuf = NULL; + int gi, qi; + bkn_bitstream_set_field(sand_scratch_data, 0, 16, + packet_info->internal.trap_id); + bkn_bitstream_set_field(sand_scratch_data, 16, 16, + packet_info->internal.trap_qualifier); + bkn_bitstream_set_field(sand_scratch_data, 32, 18, + packet_info->ftmh.source_sys_port_aggregate); + bkn_bitstream_set_field(sand_scratch_data, 64, 2, + packet_info->ftmh.action_type); + bkn_bitstream_set_field(sand_scratch_data, 66, 18, + packet_info->internal.forward_domain); + + for (gi = 0; gi < pdev->num_groups; gi++) { + grp = &ctrl->grp[gi]; + if (!grp->attached) { + continue; + } + for (qi = 0; qi < pdev->grp_queues; qi++) { + if (1 << qi & grp->bm_rxq) { + rxq = grp->rx_queue[qi]; + if (queue_id == rxq->queue_id) { + break; + } + } + } + if (qi == pdev->grp_queues) { + continue; + } + ring = rxq->ring; + pbuf = &rxq->pbuf[rxq->curr]; + if (pbuf->skb == skb) { + dcb = &ring[rxq->curr * BKN_DNX_DCB_WORDS]; + break; + } + } + if (dcb) { + DBG_VERB(("DCB(gi %d, qi %d, curr %d): {%08x,%08x,%08x,%08x}\n", gi, qi, rxq->curr, dcb[0],dcb[1],dcb[2],dcb[3])); + sand_scratch_data[BKN_DNX_DCB_WORDS - 1] = dcb[BKN_DNX_DCB_WORDS - 1]; + } +} + +static int +ngknet_packet_header_parse( + struct adapter_dev *adev, + struct sk_buff *skb) +{ + bkn_dune_system_header_info_t packet_info = {0}; + struct pkt_buf *pkb = (struct pkt_buf *)skb->data; + struct pkt_hdr *pkh = &pkb->pkh; + uint32_t sand_scratch_data[NGKNET_SCRATCH_DATA_WORDS] = {0}; + void *ssdp = NULL; + + /* Jericho 2 mode */ + if (ADAPTER_IS_AI(adev)) { + bkn_dnx_packet_parse_ai_header(adev, &pkb->data, pkh->meta_len + pkh->data_len, &packet_info); + } else { + bkn_dnx_packet_parse_header(adev, &pkb->data, pkh->meta_len + pkh->data_len, &packet_info); + } + pkh->meta_len += packet_info.system_header_size; + pkh->data_len -= packet_info.system_header_size; + bkn_dnx_scratch_data_generate(adev, skb, &packet_info, pkh->queue_id, sand_scratch_data); + ssdp = skb_put(skb, sizeof(sand_scratch_data)); + memcpy(ssdp, sand_scratch_data, sizeof(sand_scratch_data)); + + return 0; +} + +int +ngknet_rx_parser_debug_set( + int debug_lvl) +{ + debug = debug_lvl; + return 0; +} + +int +ngknet_rx_parser( + struct adapter_dev *adev, + struct sk_buff *skb) +{ + return ngknet_packet_header_parse(adev, skb); +} + +bool +ngknet_rx_parser_scratch_data_match( + struct adapter_dev *adev, + struct sk_buff *skb, + ngknet_filter_t *filt) +{ + ngknet_msg_scratch_data_t *scratch; + uint32_t *scratch_data = NULL; + uint32_t sdata; + int idx; + + scratch = &adev->scratch[filt->id]; + scratch_data = (uint32_t *)&skb->data[skb->len - NGKNET_SCRATCH_DATA_BYTES]; + DBG_VERB(("Filter: %d\n", scratch->filter_id)); + for (idx = 0; idx < NGKNET_SCRATCH_DATA_WORDS; idx++) { + DBG_VERB(("OOB[%d]: 0x%08x [0x%08x]\n", idx, scratch->data[idx], scratch->mask[idx])); + } + DBG_VERB(("Meta Data [+ Selected Raw packet data]\n")); + for (idx = 0; idx < NGKNET_SCRATCH_DATA_WORDS; idx++) { + DBG_VERB(("Scratch[%d]: 0x%08x\n", idx, scratch_data[idx])); + } + for (idx = 0; idx < NGKNET_SCRATCH_DATA_WORDS; idx++) { + sdata = scratch_data[idx] & scratch->mask[idx]; + if (sdata != scratch->data[idx]) { + return false; + } + } + return true; +} diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_parser.h b/systems/linux/kernel/modules/bcm-ngknet/ngknet_parser.h new file mode 100644 index 0000000..8cd08ed --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_parser.h @@ -0,0 +1,53 @@ +/*! \file ngknet_parser.h + * + * Definitions and APIs declaration for KNET parser. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_PARSER_H +#define NGKNET_PARSER_H + +#include "ngknet_adapter.h" + +extern int ngknet_rx_parser_debug_set( + int debug_lvl); + +extern int ngknet_rx_parser( + struct adapter_dev *adev, + struct sk_buff *skb); + +extern bool ngknet_rx_parser_scratch_data_match( + struct adapter_dev *adev, + struct sk_buff *skb, + ngknet_filter_t *filt); +#endif /* NGKNET_PARSER_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_procfs.c b/systems/linux/kernel/modules/bcm-ngknet/ngknet_procfs.c new file mode 100644 index 0000000..48f0148 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_procfs.c @@ -0,0 +1,687 @@ +/*! \file ngknet_procfs.c + * + * + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#include "ngknet_main.h" +#include "ngknet_extra.h" +#include "ngknet_procfs.h" +#include "ngknet_adapter.h" + +extern struct ngknet_dev ngknet_devices[]; + +static struct proc_dir_entry *proc_root = NULL; + +static void +proc_data_show(struct seq_file *m, const unsigned char *buf, size_t len) +{ + uint32_t i; + + if (!buf || !len) { + seq_printf(m, "\n"); + return; + } + + for (i = 0; i < len; i++) { + seq_printf(m, "%02x ", buf[i]); + if ((i + 1) % 32 == 0 || (i + 1) == len) { + seq_printf(m, "\n"); + if ((i + 1) < len) { + seq_printf(m, " "); + } + } + } +} + +static int +proc_debug_level_show(struct seq_file *m, void *v) +{ + seq_printf(m, "Debug level: 0x%x\n", ngknet_debug_level_get()); + + return 0; +} + +static int +proc_debug_level_open(struct inode *inode, struct file *file) +{ + return single_open(file, proc_debug_level_show, NULL); +} + +static ssize_t +proc_debug_level_write(struct file *file, const char *buf, + size_t count, loff_t *loff) +{ + char level_str[11] = {0}; + int debug_level; + + if (copy_from_user(level_str, buf, sizeof(level_str) - 1)) { + return -EFAULT; + } + debug_level = simple_strtol(level_str, NULL, 16); + + ngknet_debug_level_set(debug_level); + printk("Debug level set to: 0x%x\n", debug_level); + + return count; +} + +static int +proc_debug_level_release(struct inode *inode, struct file *file) +{ + return single_release(inode, file); +} + +static struct proc_ops proc_debug_level_fops = { + PROC_OWNER(THIS_MODULE) + .proc_open = proc_debug_level_open, + .proc_read = seq_read, + .proc_write = proc_debug_level_write, + .proc_lseek = seq_lseek, + .proc_release = proc_debug_level_release, +}; + +static int +proc_device_info_show(struct seq_file *m, void *v) +{ + struct ngknet_dev *dev; + struct bcmcnet_dev_info *info; + int di, qi, ai = 0; + int rv; + + for (di = 0; di < NUM_PDMA_DEV_MAX; di++) { + dev = &ngknet_devices[di]; + if (!(dev->flags & NGKNET_DEV_ACTIVE)) { + continue; + } + ai++; + + rv = bcmcnet_pdma_dev_info_get(&dev->pdma_dev); + if (SHR_FAILURE(rv)) { + printk("ngknet: get device%d info failed\n", di); + break; + } + + info = &dev->pdma_dev.info; + seq_printf(m, "dev_no: %d\n", di); + seq_printf(m, "dev_name: %s\n", info->dev_name); + seq_printf(m, "dev_id: 0x%x\n", info->dev_id); + seq_printf(m, "dev_type: %d\n", info->dev_type); + seq_printf(m, "max_groups: %d\n", info->max_groups); + seq_printf(m, "max_queues: %d\n", info->max_queues); + seq_printf(m, "bm_groups: 0x%x\n", info->bm_groups); + seq_printf(m, "bm_rx_queues: 0x%x\n", info->bm_rx_queues); + seq_printf(m, "bm_tx_queues: 0x%x\n", info->bm_tx_queues); + seq_printf(m, "nb_groups: %d\n", info->nb_groups); + seq_printf(m, "nb_rx_queues: %d\n", info->nb_rx_queues); + seq_printf(m, "nb_tx_queues: %d\n", info->nb_tx_queues); + seq_printf(m, "rx_desc_size: %d\n", info->rx_desc_size); + seq_printf(m, "tx_desc_size: %d\n", info->tx_desc_size); + seq_printf(m, "rx_ph_size: %d\n", info->rx_ph_size); + seq_printf(m, "tx_ph_size: %d\n", info->tx_ph_size); + for (qi = 0; qi < info->nb_rx_queues; qi++) { + seq_printf(m, "rx_buf_sz[%d]: %d\n", qi, info->rx_buf_size[qi]); + } + for (qi = 0; qi < info->nb_rx_queues; qi++) { + seq_printf(m, "nb_rx_desc[%d]: %d\n", qi, info->nb_rx_desc[qi]); + } + for (qi = 0; qi < info->nb_rx_queues; qi++) { + seq_printf(m, "rxq_state[%d]: 0x%x\n", qi, info->rxq_state[qi]); + } + for (qi = 0; qi < info->nb_tx_queues; qi++) { + seq_printf(m, "nb_tx_desc[%d]: %d\n", qi, info->nb_tx_desc[qi]); + } + for (qi = 0; qi < info->nb_tx_queues; qi++) { + seq_printf(m, "txq_state[%d]: 0x%x\n", qi, info->txq_state[qi]); + } + } + + if (!ai) { + seq_printf(m, "%s\n", "No active device"); + } else { + seq_printf(m, "------------------------\n"); + seq_printf(m, "Total %d devices\n", ai); + } + + return 0; +} + +static int +proc_device_info_open(struct inode *inode, struct file *file) +{ + return single_open(file, proc_device_info_show, NULL); +} + +static int +proc_device_info_release(struct inode *inode, struct file *file) +{ + return single_release(inode, file); +} + +static struct proc_ops proc_device_info_fops = { + PROC_OWNER(THIS_MODULE) + .proc_open = proc_device_info_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = proc_device_info_release, +}; + +static int +proc_filter_info_show(struct seq_file *m, void *v) +{ + struct ngknet_dev *dev; + ngknet_filter_t filt = {0}; + int di, dn = 0, fn = 0; + int rv; + + for (di = 0; di < NUM_PDMA_DEV_MAX; di++) { + dev = &ngknet_devices[di]; + if (!(dev->flags & NGKNET_DEV_ACTIVE)) { + continue; + } + dn++; + + do { + rv = ngknet_filter_get_next(dev, &filt); + if (SHR_FAILURE(rv)) { + printk("ngknet: get device%d filter failed\n", di); + break; + } + fn++; + + seq_printf(m, "\n"); + seq_printf(m, "dev_no: %d\n", di); + seq_printf(m, "id: %d\n", filt.id); + seq_printf(m, "next: %d\n", filt.next); + seq_printf(m, "type: %d\n", filt.type); + seq_printf(m, "flags: 0x%x\n", filt.flags); + seq_printf(m, "prio: %d\n", filt.priority); + seq_printf(m, "chan: %d\n", filt.chan); + seq_printf(m, "desc: %s\n", filt.desc); + seq_printf(m, "dest_type: %d\n", filt.dest_type); + seq_printf(m, "dest_id: %d\n", filt.dest_id); + seq_printf(m, "dest_proto: 0x%x\n", filt.dest_proto); + seq_printf(m, "mirror_type: %d\n", filt.mirror_type); + seq_printf(m, "mirror_id: %d\n", filt.mirror_id); + seq_printf(m, "mirror_proto: 0x%x\n", filt.mirror_proto); + seq_printf(m, "oob_offset: %d\n", filt.oob_data_offset); + seq_printf(m, "oob_size: %d\n", filt.oob_data_size); + seq_printf(m, "pkt_offset: %d\n", filt.pkt_data_offset); + seq_printf(m, "pkt_size: %d\n", filt.pkt_data_size); + seq_printf(m, "filt_data: "); + proc_data_show(m, filt.data.b, filt.oob_data_size + filt.pkt_data_size); + seq_printf(m, "filt_mask: "); + proc_data_show(m, filt.mask.b, filt.oob_data_size + filt.pkt_data_size); + seq_printf(m, "user_data: "); + proc_data_show(m, filt.user_data, NGKNET_FILTER_USER_DATA); + seq_printf(m, "hits: %llu\n", ((struct filt_ctrl *)dev->fc[filt.id])->hits); + } while (filt.next); + } + + if (!dn) { + seq_printf(m, "%s\n", "No active device"); + } else { + seq_printf(m, "--------------------------------\n"); + seq_printf(m, "Total %d devices, %d filters\n", dn, fn); + } + + return 0; +} + +static int +proc_filter_info_open(struct inode *inode, struct file *file) +{ + return single_open(file, proc_filter_info_show, NULL); +} + +static int +proc_filter_info_release(struct inode *inode, struct file *file) +{ + return single_release(inode, file); +} + +static struct proc_ops proc_filter_info_fops = { + PROC_OWNER(THIS_MODULE) + .proc_open = proc_filter_info_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = proc_filter_info_release, +}; + +static int +proc_netif_info_show(struct seq_file *m, void *v) +{ + struct ngknet_dev *dev; + struct net_device *ndev; + struct ngknet_private *priv; + ngknet_netif_t netif = {0}; + int di, ma, dn = 0, nn = 0; + int rv; + + for (di = 0; di < NUM_PDMA_DEV_MAX; di++) { + dev = &ngknet_devices[di]; + if (!(dev->flags & NGKNET_DEV_ACTIVE)) { + continue; + } + dn++; + + do { + rv = ngknet_netif_get_next(dev, &netif); + if (SHR_FAILURE(rv)) { + printk("ngknet: get device%d netif failed\n", di); + break; + } + nn++; + ndev = netif.id == 0 ? dev->net_dev : dev->vdev[netif.id]; + priv = netdev_priv(ndev); + + seq_printf(m, "\n"); + seq_printf(m, "dev_no: %d\n", di); + seq_printf(m, "id: %d\n", netif.id); + seq_printf(m, "next: %d\n", netif.next); + seq_printf(m, "type: %d\n", netif.type); + seq_printf(m, "flags: 0x%x\n", netif.flags); + seq_printf(m, "vlan: %d\n", netif.vlan); + seq_printf(m, "port: %d\n", netif.port); + seq_printf(m, "mac: "); + for (ma = 0; ma < 6; ma++) { + if (ma == 5) { + seq_printf(m, "%02x\n", netif.macaddr[ma]); + } else { + seq_printf(m, "%02x:", netif.macaddr[ma]); + } + } + seq_printf(m, "mtu: %d\n", netif.mtu); + seq_printf(m, "chan: %d\n", netif.chan); + seq_printf(m, "name: %s\n", netif.name); + seq_printf(m, "meta_off: %d\n", netif.meta_off); + seq_printf(m, "meta_len: %d\n", netif.meta_len); + seq_printf(m, "meta_data: "); + proc_data_show(m, netif.meta_data, netif.meta_len); + seq_printf(m, "user_data: "); + proc_data_show(m, netif.user_data, NGKNET_NETIF_USER_DATA); + seq_printf(m, "rx_packets: %lu\n", priv->stats.rx_packets); + seq_printf(m, "rx_bytes: %lu\n", priv->stats.rx_bytes); + seq_printf(m, "rx_dropped: %lu\n", priv->stats.rx_dropped); + seq_printf(m, "rx_errors: %lu\n", priv->stats.rx_errors); + seq_printf(m, "tx_packets: %lu\n", priv->stats.tx_packets); + seq_printf(m, "tx_bytes: %lu\n", priv->stats.tx_bytes); + seq_printf(m, "tx_dropped: %lu\n", priv->stats.tx_dropped); + seq_printf(m, "tx_errors: %lu\n", priv->stats.tx_errors); + } while (netif.next); + } + + if (!dn) { + seq_printf(m, "%s\n", "No active device"); + } else { + seq_printf(m, "--------------------------------\n"); + seq_printf(m, "Total %d devices, %d netifs\n", dn, nn); + } + + return 0; +} + +static int +proc_netif_info_open(struct inode *inode, struct file *file) +{ + return single_open(file, proc_netif_info_show, NULL); +} + +static int +proc_netif_info_release(struct inode *inode, struct file *file) +{ + return single_release(inode, file); +} + +static struct proc_ops proc_netif_info_fops = { + PROC_OWNER(THIS_MODULE) + .proc_open = proc_netif_info_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = proc_netif_info_release, +}; + +static int +proc_pkt_stats_show(struct seq_file *m, void *v) +{ + struct ngknet_dev *dev; + struct bcmcnet_dev_stats *stats; + int di, qi, ai = 0; + int rv; + + for (di = 0; di < NUM_PDMA_DEV_MAX; di++) { + dev = &ngknet_devices[di]; + if (!(dev->flags & NGKNET_DEV_ACTIVE)) { + continue; + } + ai++; + + rv = bcmcnet_pdma_dev_stats_get(&dev->pdma_dev); + if (SHR_FAILURE(rv)) { + printk("ngknet: get device%d stats failed\n", di); + break; + } + + stats = &dev->pdma_dev.stats; + seq_printf(m, "rx_packets: %llu\n", (unsigned long long)stats->rx_packets); + seq_printf(m, "rx_bytes: %llu\n", (unsigned long long)stats->rx_bytes); + for (qi = 0; qi < dev->pdma_dev.ctrl.nb_rxq; qi++) { + seq_printf(m, "rx_packets[%d]: %llu\n", qi, (unsigned long long)stats->rxq_packets[qi]); + seq_printf(m, "rx_bytes[%d]: %llu\n", qi, (unsigned long long)stats->rxq_bytes[qi]); + } + seq_printf(m, "rx_dropped: %llu\n", (unsigned long long)stats->rx_dropped); + seq_printf(m, "rx_errors: %llu\n", (unsigned long long)stats->rx_errors); + seq_printf(m, "rx_head_errors: %llu\n", (unsigned long long)stats->rx_head_errors); + seq_printf(m, "rx_data_errors: %llu\n", (unsigned long long)stats->rx_data_errors); + seq_printf(m, "rx_cell_errors: %llu\n", (unsigned long long)stats->rx_cell_errors); + seq_printf(m, "rx_nomems: %llu\n", (unsigned long long)stats->rx_nomems); + seq_printf(m, "tx_packets: %llu\n", (unsigned long long)stats->tx_packets); + seq_printf(m, "tx_bytes: %llu\n", (unsigned long long)stats->tx_bytes); + for (qi = 0; qi < dev->pdma_dev.ctrl.nb_txq; qi++) { + seq_printf(m, "tx_packets[%d]: %llu\n", qi, (unsigned long long)stats->txq_packets[qi]); + seq_printf(m, "tx_bytes[%d]: %llu\n", qi, (unsigned long long)stats->txq_bytes[qi]); + } + seq_printf(m, "tx_dropped: %llu\n", (unsigned long long)stats->tx_dropped); + seq_printf(m, "tx_errors: %llu\n", (unsigned long long)stats->tx_errors); + seq_printf(m, "tx_xoffs: %llu\n", (unsigned long long)stats->tx_xoffs); + seq_printf(m, "interrupts: %llu\n", (unsigned long long)stats->intrs); + } + + if (!ai) { + seq_printf(m, "%s\n", "No active device"); + } else { + seq_printf(m, "------------------------\n"); + seq_printf(m, "Total %d devices\n", ai); + } + + return 0; +} + +static int +proc_pkt_stats_open(struct inode *inode, struct file *file) +{ + return single_open(file, proc_pkt_stats_show, NULL); +} + +static int +proc_pkt_stats_release(struct inode *inode, struct file *file) +{ + return single_release(inode, file); +} + +static struct proc_ops proc_pkt_stats_fops = { + PROC_OWNER(THIS_MODULE) + .proc_open = proc_pkt_stats_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = proc_pkt_stats_release, +}; + +static int +proc_rate_limit_show(struct seq_file *m, void *v) +{ + seq_printf(m, "Rx rate limit: %d pps\n", ngknet_rx_rate_limit_get()); + + return 0; +} + +static int +proc_rate_limit_open(struct inode *inode, struct file *file) +{ + return single_open(file, proc_rate_limit_show, NULL); +} + +static ssize_t +proc_rate_limit_write(struct file *file, const char *buf, + size_t count, loff_t *loff) +{ + char limit_str[9] = {0}; + int rate_limit; + + if (copy_from_user(limit_str, buf, sizeof(limit_str) - 1)) { + return -EFAULT; + } + rate_limit = simple_strtol(limit_str, NULL, 10); + + ngknet_rx_rate_limit_set(rate_limit); + printk("Rx rate limit set to: %d pps\n", rate_limit); + + return count; +} + +static int +proc_rate_limit_release(struct inode *inode, struct file *file) +{ + return single_release(inode, file); +} + +static struct proc_ops proc_rate_limit_fops = { + PROC_OWNER(THIS_MODULE) + .proc_open = proc_rate_limit_open, + .proc_read = seq_read, + .proc_write = proc_rate_limit_write, + .proc_lseek = seq_lseek, + .proc_release = proc_rate_limit_release, +}; + +static int +proc_reg_status_show(struct seq_file *m, void *v) +{ + struct ngknet_dev *dev; + int di, qi, ai = 0; + + for (di = 0; di < NUM_PDMA_DEV_MAX; di++) { + dev = &ngknet_devices[di]; + if (!(dev->flags & NGKNET_DEV_ACTIVE)) { + continue; + } + ai++; + for (qi = 0; qi < dev->pdma_dev.ctrl.nb_rxq; qi++) { + bcmcnet_pdma_rx_queue_reg_dump(&dev->pdma_dev, qi); + } + for (qi = 0; qi < dev->pdma_dev.ctrl.nb_txq; qi++) { + bcmcnet_pdma_tx_queue_reg_dump(&dev->pdma_dev, qi); + } + } + + if (!ai) { + seq_printf(m, "%s\n", "No active device"); + } else { + seq_printf(m, "------------------------\n"); + seq_printf(m, "Total %d devices\n", ai); + } + + return 0; +} + +static int +proc_reg_status_open(struct inode *inode, struct file *file) +{ + return single_open(file, proc_reg_status_show, NULL); +} + +static int +proc_reg_status_release(struct inode *inode, struct file *file) +{ + return single_release(inode, file); +} + +static struct proc_ops proc_reg_status_fops = { + PROC_OWNER(THIS_MODULE) + .proc_open = proc_reg_status_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = proc_reg_status_release, +}; + +static int +proc_ring_status_show(struct seq_file *m, void *v) +{ + struct ngknet_dev *dev; + int di, qi, ai = 0; + + for (di = 0; di < NUM_PDMA_DEV_MAX; di++) { + dev = &ngknet_devices[di]; + if (!(dev->flags & NGKNET_DEV_ACTIVE)) { + continue; + } + ai++; + seq_printf(m, "%s-%d, ", "Unit", di); + for (qi = 0; qi < dev->pdma_dev.ctrl.nb_rxq; qi++) { + bcmcnet_pdma_rx_ring_dump(&dev->pdma_dev, qi); + } + seq_printf(m, "%s%d, ", "Rx queues: ", qi); + for (qi = 0; qi < dev->pdma_dev.ctrl.nb_txq; qi++) { + bcmcnet_pdma_tx_ring_dump(&dev->pdma_dev, qi); + } + seq_printf(m, "%s%d. ", "Tx queues: ", qi); + seq_printf(m, "\n"); + } + + if (!ai) { + seq_printf(m, "%s\n", "No active device"); + } else { + seq_printf(m, "------------------------\n"); + seq_printf(m, "Total %d devices\n", ai); + } + + return 0; +} + +static int +proc_ring_status_open(struct inode *inode, struct file *file) +{ + return single_open(file, proc_ring_status_show, NULL); +} + +static int +proc_ring_status_release(struct inode *inode, struct file *file) +{ + return single_release(inode, file); +} + +static struct proc_ops proc_ring_status_fops = { + PROC_OWNER(THIS_MODULE) + .proc_open = proc_ring_status_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = proc_ring_status_release, +}; + +int +ngknet_procfs_init(void) +{ + struct proc_dir_entry *entry = NULL; + + proc_root = proc_mkdir(NGKNET_MODULE_NAME, NULL); + if (proc_root == NULL) { + printk(KERN_ERR "ngknet: proc_mkdir failed\n"); + return -1; + } + + PROC_CREATE(entry, "debug_level", 0666, proc_root, &proc_debug_level_fops); + if (entry == NULL) { + printk(KERN_ERR "ngknet: proc_create failed\n"); + return -1; + } + + PROC_CREATE(entry, "device_info", 0444, proc_root, &proc_device_info_fops); + if (entry == NULL) { + printk(KERN_ERR "ngknet: proc_create failed\n"); + return -1; + } + + PROC_CREATE(entry, "filter_info", 0444, proc_root, &proc_filter_info_fops); + if (entry == NULL) { + printk(KERN_ERR "ngknet: proc_create failed\n"); + return -1; + } + + PROC_CREATE(entry, "netif_info", 0444, proc_root, &proc_netif_info_fops); + if (entry == NULL) { + printk(KERN_ERR "ngknet: proc_create failed\n"); + return -1; + } + + PROC_CREATE(entry, "pkt_stats", 0444, proc_root, &proc_pkt_stats_fops); + if (entry == NULL) { + printk(KERN_ERR "ngknet: proc_create failed\n"); + return -1; + } + + PROC_CREATE(entry, "rate_limit", 0666, proc_root, &proc_rate_limit_fops); + if (entry == NULL) { + printk(KERN_ERR "ngknet: proc_create failed\n"); + return -1; + } + + PROC_CREATE(entry, "reg_status", 0444, proc_root, &proc_reg_status_fops); + if (entry == NULL) { + printk(KERN_ERR "ngknet: proc_create failed\n"); + return -1; + } + + PROC_CREATE(entry, "ring_status", 0444, proc_root, &proc_ring_status_fops); + if (entry == NULL) { + printk(KERN_ERR "ngknet: proc_create failed\n"); + return -1; + } + + PROC_CREATE(entry, "adapter_info", 0444, proc_root, &ngknet_adapter_info_fops); + if (entry == NULL) { + printk(KERN_ERR "ngknet: proc_create failed\n"); + return -1; + } + + return 0; +} + +int +ngknet_procfs_cleanup(void) +{ + remove_proc_entry("debug_level", proc_root); + remove_proc_entry("device_info", proc_root); + remove_proc_entry("filter_info", proc_root); + remove_proc_entry("netif_info", proc_root); + remove_proc_entry("pkt_stats", proc_root); + remove_proc_entry("rate_limit", proc_root); + remove_proc_entry("reg_status", proc_root); + remove_proc_entry("ring_status", proc_root); + remove_proc_entry("adapter_info", proc_root); + + remove_proc_entry(NGKNET_MODULE_NAME, NULL); + + return 0; +} + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_procfs.h b/systems/linux/kernel/modules/bcm-ngknet/ngknet_procfs.h new file mode 100644 index 0000000..f1beebb --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_procfs.h @@ -0,0 +1,60 @@ +/*! \file ngknet_procfs.h + * + * Procfs-related definitions and APIs for NGKNET module. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_PROCFS_H +#define NGKNET_PROCFS_H + +/*! + * \brief Initialize procfs for KNET driver. + * + * Create procfs read/write interfaces. + * + * \return 0 if no errors, otherwise -1. + */ +extern int +ngknet_procfs_init(void); + +/*! + * \brief Clean up procfs for KNET driver. + * + * Clean up resources allocated by \ref ngknet_procfs_init. + * + * \return 0 if no errors, otherwise -1. + */ +extern int +ngknet_procfs_cleanup(void); + +#endif /* NGKNET_PROCFS_H */ + diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_ptp.c b/systems/linux/kernel/modules/bcm-ngknet/ngknet_ptp.c new file mode 100644 index 0000000..8ec9288 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_ptp.c @@ -0,0 +1,226 @@ +/*! \file ngknet_ptp.c + * + * Utility routines for PTP. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include "ngknet_callback.h" +#include "ngknet_ptp.h" + +int +ngknet_ptp_rx_config_set(struct net_device *ndev, int *filter) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + + if (!dev->cbc->ptp_rx_config_set_cb) { + return SHR_E_UNAVAIL; + } + + /* + * The expected Rx filter value is passed to the callback. The callback + * should pass back the actual filter value by the paramter . + * The callback can use netif->user_data to get other private parameters + * like phys_port which should be introduced when the netif is created. + */ + return dev->cbc->ptp_rx_config_set_cb(&dev->dev_info, &priv->netif, filter); +} + +int +ngknet_ptp_tx_config_set(struct net_device *ndev, int type) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + + if (!dev->cbc->ptp_tx_config_set_cb) { + return SHR_E_UNAVAIL; + } + + /* + * The Tx type value is passed to the callback by the parameter . + * The callback should do the configuration according to the type. + * The callback can use netif->user_data to get other private parameters + * like phys_port which should be introduced when the netif is created. + */ + return dev->cbc->ptp_tx_config_set_cb(&dev->dev_info, &priv->netif, &type); +} + +int +ngknet_ptp_rx_hwts_get(struct net_device *ndev, struct sk_buff *skb, uint64_t *ts) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + struct ngknet_callback_desc *cbd = NGKNET_SKB_CB(skb); + struct pkt_hdr *pkh = (struct pkt_hdr *)skb->data; + + if (!dev->cbc->ptp_rx_hwts_get_cb) { + return SHR_E_UNAVAIL; + } + + cbd->dinfo = &dev->dev_info; + cbd->netif = &priv->netif; + cbd->pmd = skb->data + PKT_HDR_SIZE; + cbd->pmd_len = pkh->meta_len; + cbd->pkt_len = pkh->data_len; + + /* + * The callback should get timestamp value for a Rx packet and return + * by the parameter . + * Some parameters have been consolidated to SKB as above. They can be + * achieved by NGKNET_SKB_CB(skb). Specially more private paramters are + * in NGKNET_SKB_CB(skb)->dinfo or NGKNET_SKB_CB(skb)->netif->user_data + * such as dev_type, phys_port and so on. + */ + return dev->cbc->ptp_rx_hwts_get_cb(skb, ts); +} + +int +ngknet_ptp_tx_hwts_get(struct net_device *ndev, struct sk_buff *skb, uint64_t *ts) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + + if (!dev->cbc->ptp_tx_hwts_get_cb) { + return SHR_E_UNAVAIL; + } + + /* + * The callback should get timestamp value for a Tx packet and return + * by the parameter . + * For HWTSTAMP_TX_ONESTEP_SYNC type, the time value can be achieved and + * returned immediately. Otherwise, for HWTSTAMP_TX_ON type, the callback + * should wait till the time value can be available, i.e. the packet has + * been tranmitted out from port. + * Some parameters have been consolidated to SKB as above. They can be + * achieved by NGKNET_SKB_CB(skb). Specially more private paramters are + * in NGKNET_SKB_CB(skb)->dinfo or NGKNET_SKB_CB(skb)->netif->user_data + * such as dev_type, phys_port and so on. + */ + return dev->cbc->ptp_tx_hwts_get_cb(skb, ts); +} + +int +ngknet_ptp_tx_meta_set(struct net_device *ndev, struct sk_buff *skb) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + struct ngknet_callback_desc *cbd = NGKNET_SKB_CB(skb); + struct pkt_hdr *pkh = (struct pkt_hdr *)skb->data; + struct ngknet_ptp_data *pd = (struct ngknet_ptp_data *)priv->netif.user_data; + + if (!dev->cbc->ptp_tx_meta_set_cb) { + return SHR_E_UNAVAIL; + } + + /* First 4bytes of user_data already has phy_port */ + pd->hwts_tx_type = priv->hwts_tx_type; + cbd->dinfo = &dev->dev_info; + cbd->netif = &priv->netif; + cbd->pmd = skb->data + PKT_HDR_SIZE; + cbd->pmd_len = pkh->meta_len; + cbd->pkt_len = pkh->data_len; + + /* + * The callback should configure the metadata pmd> + * for HW timestamping according to the corresponding switch device. + * Some parameters have been consolidated to SKB as above. They can be + * achieved by NGKNET_SKB_CB(skb). Specially more private paramters are + * in NGKNET_SKB_CB(skb)->dinfo or NGKNET_SKB_CB(skb)->netif->user_data + * such as dev_type, phys_port and so on. + */ + return dev->cbc->ptp_tx_meta_set_cb(skb); +} + +int +ngknet_ptp_phc_index_get(struct net_device *ndev, int *index) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + + if (!dev->cbc->ptp_phc_index_get_cb) { + return SHR_E_UNAVAIL; + } + + /* + * The callback should return the HPC index by the parameter . + * netif->user_data can be used to get other private parameters such as + * phys_port which should be introduced when the netif is created. + */ + return dev->cbc->ptp_phc_index_get_cb(&dev->dev_info, &priv->netif, index); +} + +int +ngknet_ptp_dev_ctrl(struct ngknet_dev *dev, int cmd, char *data, int len) +{ + if (!dev->cbc->ptp_dev_ctrl_cb) { + return SHR_E_UNAVAIL; + } + + /* + * The callback is IOCTL dispatcher for PTP kernel driver/module. + * The parameter is the command defined by the user. The parameter + * and are used for interactions between the user application + * and the driver for PTP device start/stop, enable/disable, set/get, and + * so on. + */ + return dev->cbc->ptp_dev_ctrl_cb(&dev->dev_info, cmd, data, len); +} + +extern int +ngknet_ptp_rx_pre_process(struct net_device *ndev, struct sk_buff *skb, + uint32_t *cust_hdr_len) +{ + struct ngknet_private *priv = netdev_priv(ndev); + struct ngknet_dev *dev = priv->bkn_dev; + struct ngknet_callback_desc *cbd = NGKNET_SKB_CB(skb); + struct pkt_hdr *pkh = (struct pkt_hdr *)skb->data; + + if (!dev->cbc->ptp_rx_pre_process_cb) { + return SHR_E_UNAVAIL; + } + + cbd->dinfo = &dev->dev_info; + cbd->netif = &priv->netif; + cbd->pmd = skb->data + PKT_HDR_SIZE; + cbd->pmd_len = pkh->meta_len; + cbd->pkt_len = pkh->data_len; + + /* + * The callback should get custom header length return by the parameter + * . + * Some parameters have been consolidated to SKB as above. They can be + * achieved by NGKNET_SKB_CB(skb). Specially more private paramters are + * in NGKNET_SKB_CB(skb)->dinfo or NGKNET_SKB_CB(skb)->netif->user_data + * such as dev_type, phys_port and so on. + */ + return dev->cbc->ptp_rx_pre_process_cb(skb, cust_hdr_len); +} diff --git a/systems/linux/kernel/modules/bcm-ngknet/ngknet_ptp.h b/systems/linux/kernel/modules/bcm-ngknet/ngknet_ptp.h new file mode 100644 index 0000000..a7a8e47 --- /dev/null +++ b/systems/linux/kernel/modules/bcm-ngknet/ngknet_ptp.h @@ -0,0 +1,140 @@ +/*! \file ngknet_ptp.h + * + * Definitions and APIs declaration for PTP. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#ifndef NGKNET_PTP_H +#define NGKNET_PTP_H + +#include +#include "ngknet_main.h" + +/*! + * \brief PTP Rx config set. + * + * \param [in] ndev Network device structure point. + * \param [in] filter Rx filter. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_rx_config_set(struct net_device *ndev, int *filter); + +/*! + * \brief PTP Tx config set. + * + * \param [in] ndev Network device structure point. + * \param [in] type Tx type. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_tx_config_set(struct net_device *ndev, int type); + +/*! + * \brief PTP Rx HW timestamping get. + * + * \param [in] ndev Network device structure point. + * \param [in] skb Rx packet SKB. + * \param [out] ts Timestamp value. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_rx_hwts_get(struct net_device *ndev, struct sk_buff *skb, uint64_t *ts); + +/*! + * \brief PTP Tx HW timestamping get. + * + * \param [in] ndev Network device structure point. + * \param [in] skb Tx packet SKB. + * \param [out] ts Timestamp value. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_tx_hwts_get(struct net_device *ndev, struct sk_buff *skb, uint64_t *ts); + +/*! + * \brief PTP Tx meta set. + * + * \param [in] ndev Network device structure point. + * \param [in] skb Tx packet SKB. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_tx_meta_set(struct net_device *ndev, struct sk_buff *skb); + +/*! + * \brief PTP PHC index get. + * + * \param [in] ndev Network device structure point. + * \param [out] index PHC index. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_phc_index_get(struct net_device *ndev, int *index); + +/*! + * \brief PTP device control. + * + * \param [in] dev NGKNET device structure point. + * \param [in] cmd Command. + * \param [in] data Data buffer. + * \param [in] len Data length. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_dev_ctrl(struct ngknet_dev *dev, int cmd, char *data, int len); + +/*! + * \brief PTP Rx pre-process to get custom header length. + * + * If the RX PTP packet is timestamped by the HW and requires + * timestamp processing then, this function can be used + * to get the custom/system header length encapsulated by the FW. + * + * \param [in] dev NGKNET device structure point. + * \param [in] skb Rx packet SKB. + * \param [out] Custom header length. + * + * \retval SHR_E_NONE No errors. + */ +extern int +ngknet_ptp_rx_pre_process(struct net_device *ndev, struct sk_buff *skb, uint32_t *cust_hdr_len); + +#endif /* NGKNET_PTP_H */ + diff --git a/systems/linux/kernel/modules/bcm-ptp-clock/bcm-ptp-clock.c b/systems/linux/kernel/modules/bcm-ptp-clock/bcm-ptp-clock.c index c174846..81eb76e 100644 --- a/systems/linux/kernel/modules/bcm-ptp-clock/bcm-ptp-clock.c +++ b/systems/linux/kernel/modules/bcm-ptp-clock/bcm-ptp-clock.c @@ -519,6 +519,7 @@ typedef struct bksync_bs_info_s { u32 bc; u32 hb; bksync_time_spec_t offset; + u32 protocol; } bksync_bs_info_t; typedef struct bksync_gpio_info_s { @@ -2521,7 +2522,8 @@ bksync_dnx_ase1588_tsh_hdr_update(bksync_dev_t *dev_info, struct sk_buff *skb, i ptp_hdr_offset -= BKSYNC_DNXJR2_MODULE_HEADER_LEN; } else { - ptp_hdr_offset -= (BKSYNC_DNXJR2_MODULE_HEADER_LEN + BKSYNC_DNX_PTCH_2_SIZE + BKSYNC_DNXJR2_ITMH_HEADER_LEN); + ptp_hdr_offset -= (BKSYNC_DNXJR2_MODULE_HEADER_LEN + BKSYNC_DNX_PTCH_2_SIZE + BKSYNC_DNXJR2_ITMH_HEADER_LEN + + BKSYNC_DNXJR2_FTMH_APP_SPECIFIC_EXT_LEN + BKSYNC_DNXJR2_TSH_HDR_SIZE); } /* Inserting TSH and ASE before PPH and UDH - shifted PPH and UDH by 13 bytes in skb->data */ @@ -3076,6 +3078,7 @@ static int bksync_broadsync_cmd(bksync_dev_t *dev_info, int bs_id) subcmd = (bs_id == 0) ? BKSYNC_BROADSYNC_BS0_CONFIG : BKSYNC_BROADSYNC_BS1_CONFIG; subcmd_data = ((dev_info->bksync_bs_info[bs_id]).enable & 0x1); + subcmd_data |= (((dev_info->bksync_bs_info[bs_id]).protocol & 0x1) << 1); subcmd_data |= (((dev_info->bksync_bs_info[bs_id]).mode & 0x1) << 8); subcmd_data |= ((dev_info->bksync_bs_info[bs_id]).hb << 16); subcmd_data |= (((u64)(dev_info->bksync_bs_info[bs_id]).bc) << 32); @@ -3439,7 +3442,7 @@ static ssize_t bksync_proc_txts_write(struct file *file, const char *buf, size_t count, loff_t *loff) { - char debug_str[40]; + char debug_str[40] = {0}; char *ptr; int port; int dev_no; @@ -3494,7 +3497,7 @@ static ssize_t bksync_proc_debug_write(struct file *file, const char *buf, size_t count, loff_t *loff) { - char debug_str[40]; + char debug_str[40] = {0}; char *ptr; if (copy_from_user(debug_str, buf, count)) { @@ -3672,6 +3675,7 @@ static ssize_t bs_attr_store(struct kobject *kobj, int dev_no = -1; bksync_dev_t *dev_info = NULL; bksync_time_spec_t offset = {0}; + int protocol = 0; if (ATTRCMP(bs0)) { bs_id = 0; @@ -3691,13 +3695,14 @@ static ssize_t bs_attr_store(struct kobject *kobj, dev_info = &ptp_priv->dev_info[dev_no]; - ret = sscanf(buf, "enable:%d mode:%d bc:%u hb:%u sign:%d offset:%llu.%u", &enable, &mode, &bc, &hb, &offset.sign, &offset.sec, &offset.nsec); - DBG_VERB(("rd:%d bs0: enable:%d mode:%d bc:%d hb:%d sign:%d offset:%llu.%u\n", rd_iter++, enable, mode, bc, hb, offset.sign, offset.sec, offset.nsec)); + ret = sscanf(buf, "enable:%d mode:%d bc:%u hb:%u sign:%d offset:%llu.%u protocol:%d", &enable, &mode, &bc, &hb, &offset.sign, &offset.sec, &offset.nsec, &protocol); + DBG_VERB(("rd:%d bs0: enable:%d mode:%d bc:%d hb:%d sign:%d offset:%llu.%u protocol:%d\n", rd_iter++, enable, mode, bc, hb, offset.sign, offset.sec, offset.nsec, protocol)); dev_info->bksync_bs_info[bs_id].enable = enable; dev_info->bksync_bs_info[bs_id].mode = mode; dev_info->bksync_bs_info[bs_id].bc = bc; dev_info->bksync_bs_info[bs_id].hb = hb; + dev_info->bksync_bs_info[bs_id].protocol = protocol; (void)bksync_broadsync_cmd(dev_info, bs_id); @@ -3741,7 +3746,7 @@ static ssize_t bs_attr_show(struct kobject *kobj, variance = (status >> 32); status = (status & 0xFFFFFFFF); - bytes = sprintf(buf, "enable:%d mode:%d bc:%u hb:%u sign:%d offset:%llu.%u status:%u(%u)\n", + bytes = sprintf(buf, "enable:%d mode:%d bc:%u hb:%u sign:%d offset:%llu.%u protocol:%d status:%u(%u)\n", dev_info->bksync_bs_info[bs_id].enable, dev_info->bksync_bs_info[bs_id].mode, dev_info->bksync_bs_info[bs_id].bc, @@ -3749,9 +3754,10 @@ static ssize_t bs_attr_show(struct kobject *kobj, dev_info->bksync_bs_info[bs_id].offset.sign, dev_info->bksync_bs_info[bs_id].offset.sec, dev_info->bksync_bs_info[bs_id].offset.nsec, + dev_info->bksync_bs_info[bs_id].protocol, (u32)status, variance); - DBG_VERB(("wr:%d bs1: enable:%d mode:%d bc:%u hb:%u sign:%d offset:%llu.%u status:%u(%u)\n", + DBG_VERB(("wr:%d bs1: enable:%d mode:%d bc:%u hb:%u sign:%d offset:%llu.%u protocol:%d status:%u(%u)\n", wr_iter++, dev_info->bksync_bs_info[bs_id].enable, dev_info->bksync_bs_info[bs_id].mode, @@ -3760,6 +3766,7 @@ static ssize_t bs_attr_show(struct kobject *kobj, dev_info->bksync_bs_info[bs_id].offset.sign, dev_info->bksync_bs_info[bs_id].offset.sec, dev_info->bksync_bs_info[bs_id].offset.nsec, + dev_info->bksync_bs_info[bs_id].protocol, (u32)status, variance)); @@ -4614,6 +4621,7 @@ bksync_ioctl_cmd_handler(kcom_msg_clock_cmd_t *kmsg, int len, int dcb_type, int dev_info->bksync_bs_info[bs_id].mode = kmsg->clock_info.data[1]; dev_info->bksync_bs_info[bs_id].bc = kmsg->clock_info.data[2]; dev_info->bksync_bs_info[bs_id].hb = kmsg->clock_info.data[3]; + dev_info->bksync_bs_info[bs_id].protocol = kmsg->clock_info.data[4]; (void)bksync_broadsync_cmd(dev_info, bs_id); break; diff --git a/systems/linux/kernel/modules/genl-packet/Makefile b/systems/linux/kernel/modules/genl-packet/Makefile index 188a85c..4be6d8c 100644 --- a/systems/linux/kernel/modules/genl-packet/Makefile +++ b/systems/linux/kernel/modules/genl-packet/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.3 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/include/bcm-knet.h b/systems/linux/kernel/modules/include/bcm-knet.h index 99cf8c5..17538d2 100644 --- a/systems/linux/kernel/modules/include/bcm-knet.h +++ b/systems/linux/kernel/modules/include/bcm-knet.h @@ -1,7 +1,7 @@ /* * $Id: bcm-knet.h,v 1.4 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/include/gmodule.h b/systems/linux/kernel/modules/include/gmodule.h index 1c1c7a6..8921b46 100644 --- a/systems/linux/kernel/modules/include/gmodule.h +++ b/systems/linux/kernel/modules/include/gmodule.h @@ -1,7 +1,7 @@ /* * $Id: gmodule.h,v 1.9 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/include/lkm.h b/systems/linux/kernel/modules/include/lkm.h index fa53465..17c191c 100644 --- a/systems/linux/kernel/modules/include/lkm.h +++ b/systems/linux/kernel/modules/include/lkm.h @@ -1,7 +1,7 @@ /* * $Id: lkm.h,v 1.22 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/knet-cb/Makefile b/systems/linux/kernel/modules/knet-cb/Makefile index 78d0bcb..5048330 100644 --- a/systems/linux/kernel/modules/knet-cb/Makefile +++ b/systems/linux/kernel/modules/knet-cb/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.3 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/knet-cb/knet-cb.c b/systems/linux/kernel/modules/knet-cb/knet-cb.c index eeba6d7..55fdca6 100644 --- a/systems/linux/kernel/modules/knet-cb/knet-cb.c +++ b/systems/linux/kernel/modules/knet-cb/knet-cb.c @@ -1,5 +1,6 @@ /* - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/ngknetcb/Kbuild b/systems/linux/kernel/modules/ngknetcb/Kbuild new file mode 100644 index 0000000..6fecb69 --- /dev/null +++ b/systems/linux/kernel/modules/ngknetcb/Kbuild @@ -0,0 +1,53 @@ +# -*- Kbuild -*- +# +# Linux KNET Callback module. +# +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. +# +# Permission is granted to use, copy, modify and/or distribute this +# software under either one of the licenses below. +# +# License Option 1: GPL +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License, version 2, as +# published by the Free Software Foundation (the "GPL"). +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License version 2 (GPLv2) for more details. +# +# You should have received a copy of the GNU General Public License +# version 2 (GPLv2) along with this source code. +# +# +# License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license +# +# This software is governed by the Broadcom Open Network Switch APIs license: +# https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ +# +# +# + +obj-m := linux-ngknetcb.o + +#Predefine the variable, it may become empty with recursive calls +ifndef SDKBUILD +SDKBUILD := build +endif +ifneq ($(SDK_OUTDIR),) +INCLUDES := -I$(SDK_OUTDIR)/$(SDKBUILD)/ngknetcb/generated +endif +ccflags-y := $(SDK_PMD_KFLAGS) $(LKM_CFLAGS) $(LKM_CPPFLAGS) \ + -I$(SDK)/include/ \ + -I$(SDK)/src/bcm/common/pktio/bcmdrd/include \ + -I$(SDK)/src/bcm/common/pktio/bcmltd/include \ + -I$(SDK)/src/bcm/common/pktio/bcmlrd/include \ + -I$(SDK)/src/bcm/common/pktio/bcmpkt/include \ + -I$(SDK)/systems/bde/linux/include \ + -I$(SDK)/systems/linux/kernel/modules/bcm-ngknet/include \ + $(INCLUDES) + +linux-ngknetcb-y := $(SDK_PMD_KOBJS) \ + ngknetcb_main.o diff --git a/systems/linux/kernel/modules/ngknetcb/Makefile b/systems/linux/kernel/modules/ngknetcb/Makefile new file mode 100644 index 0000000..3eb9953 --- /dev/null +++ b/systems/linux/kernel/modules/ngknetcb/Makefile @@ -0,0 +1,121 @@ +# +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. +# +# Permission is granted to use, copy, modify and/or distribute this +# software under either one of the licenses below. +# +# License Option 1: GPL +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License, version 2, as +# published by the Free Software Foundation (the "GPL"). +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License version 2 (GPLv2) for more details. +# +# You should have received a copy of the GNU General Public License +# version 2 (GPLv2) along with this source code. +# +# +# License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license +# +# This software is governed by the Broadcom Open Network Switch APIs license: +# https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ +# +# +# +# Linux NGKNET Callback module. +# + +LOCALDIR = systems/linux/kernel/modules/ngknetcb +PKTIO_IMPL = 1 +include ${SDK}/make/Make.config + +# Include PMD library by default +ifneq (0,$(KPMD)) + +# Kernel module source directory +KMODDIR = $(CURDIR) + +# Avoid creating links in original kernel module source directory +GENDIR = $(KMODDIR)/generated + +ifneq ($(SDK_OUTDIR),) +GENDIR = $(SDK_OUTDIR)/$(SDKBUILD)/ngknetcb/generated +endif + +knetcb: kpmd + $(MAKE) -C $(GENDIR) all + +# +# Redefine KAPI interface API name to avoid symbol conflict. +# +KAPI_FUNCS = ngknet_dev_init_cb_register \ + ngknet_dev_init_cb_unregister \ + ngknet_rx_cb_register \ + ngknet_rx_cb_unregister \ + ngknet_tx_cb_register \ + ngknet_tx_cb_unregister \ + ngknet_netif_create_cb_register \ + ngknet_netif_create_cb_unregister \ + ngknet_netif_destroy_cb_register \ + ngknet_netif_destroy_cb_unregister \ + ngknet_filter_cb_register \ + ngknet_filter_cb_register_by_name \ + ngknet_filter_cb_unregister \ + bcmpkt_rxpmd_field_list_dump \ + bcmpkt_rxpmd_dump \ + bcmpkt_rxpmd_len_get \ + bcmpkt_rxpmd_field_get \ + bcmpkt_rxpmd_field_set \ + bcmpkt_rxpmd_mh_get \ + bcmpkt_rxpmd_flexdata_get \ + bcmpkt_rxpmd_reasons_get \ + bcmpkt_rxpmd_reasons_set \ + bcmpkt_rxpmd_field_name_get \ + bcmpkt_rxpmd_field_id_get \ + bcmpkt_rxpmd_fid_support_get \ + bcmpkt_txpmd_field_list_dump \ + bcmpkt_txpmd_dump \ + bcmpkt_txpmd_dnx_field_list_dump \ + bcmpkt_txpmd_dnx_dump \ + bcmpkt_txpmd_len_get \ + bcmpkt_txpmd_field_get \ + bcmpkt_txpmd_field_set \ + bcmpkt_txpmd_field_name_get \ + bcmpkt_txpmd_field_id_get \ + bcmpkt_txpmd_fid_support_get \ + bcmpkt_txpmd_fid_view_get + + +KAPI_FUNCS_PREFIX = pktio +CFGFLAGS += $(foreach f,${KAPI_FUNCS},-D$f=${KAPI_FUNCS_PREFIX}_$f) + +LKM_CFLAGS := $(CFGFLAGS) $(LKM_BUILD_INFO) -DPKTIO_KIMPL=1 -Dsal_memset=memset -Dsal_strcasecmp=strcasecmp +LKM_CPPFLAGS := $(CFGFLAGS) $(LKM_BUILD_INFO) -DPKTIO_KIMPL=1 -Dsal_memset=memset -Dsal_strcasecmp=strcasecmp +export LKM_CFLAGS +export LKM_CPPFLAGS + +# SDK make helper for stand-alone PMD kernel module +include $(SDK)/make/Make.kpmd + +distclean:: + rm -rf $(GENDIR) + +endif # KPMD + +include Kbuild + +ifeq ($(KERNELRELEASE),) + +MOD_NAME = linux-ngknetcb + +include $(SDK)/make/Make.lkm + +endif + +.PHONY: distclean + +distclean:: diff --git a/systems/linux/kernel/modules/ngknetcb/ngknetcb_main.c b/systems/linux/kernel/modules/ngknetcb/ngknetcb_main.c new file mode 100644 index 0000000..113937e --- /dev/null +++ b/systems/linux/kernel/modules/ngknetcb/ngknetcb_main.c @@ -0,0 +1,672 @@ +/*! \file ngknetcb_main.c + * + * NGKNET Callback module entry. + * + */ +/* + * + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. + * + * Permission is granted to use, copy, modify and/or distribute this + * software under either one of the licenses below. + * + * License Option 1: GPL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + * + * + * License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license + * + * This software is governed by the Broadcom Open Network Switch APIs license: + * https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ + * + * + */ + +#include +#include +#ifdef KPMD +#include +#include +#include +#include +#include +#include +#include +#endif /* KPMD */ + +/*! \cond */ +MODULE_AUTHOR("Broadcom Corporation"); +MODULE_DESCRIPTION("NGKNET Callback Module"); +MODULE_LICENSE("GPL"); +/*! \endcond */ + +/*! Module information */ +#define NGKNETCB_MODULE_NAME "linux_ngknetcb" + +#ifndef KPMD +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + BCMDRD_DEV_T_##_bd, +/*! Enumeration for all base device types. */ +typedef enum { + BCMDRD_DEV_T_NONE = 0, +/*! \cond */ +#include +/*! \endcond */ + BCMDRD_DEV_T_COUNT +} bcmdrd_dev_type_t; + +/*! Create enumeration values from list of supported variants. */ +#define BCMLRD_VARIANT_ENTRY(_bd,_bu,_va,_ve,_vu,_vv,_vo,_vd,_r0,_r1)\ + BCMLRD_VARIANT_T_##_bd##_##_ve, + +/*! Enumeration for all device variants. */ +typedef enum bcmlrd_variant_e { + BCMLRD_VARIANT_T_NONE = 0, +/*! \cond */ +#include +/*! \endcond */ + BCMLRD_VARIANT_T_COUNT +} bcmlrd_variant_t; +#endif /* !KPMD */ + +typedef struct ngknetcb_dev_s { + bool initialized; + bcmdrd_dev_type_t dev_type; + bcmlrd_variant_t var_type; +} ngknetcb_dev_t; + +typedef struct ngknetcb_pmd_unit_s { + bool added; /* User cares about this pmd info */ + bool valid; /* Unit is initialized and added */ +} ngknetcb_pmd_unit_t; + +static ngknetcb_dev_t cb_dev[NUM_PDMA_DEV_MAX]; +static ngknetcb_pmd_unit_t pmd_units[NUM_PDMA_DEV_MAX]; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + {#_bd, BCMDRD_DEV_T_##_bd}, +static const struct { + char *name; + bcmdrd_dev_type_t dev; +} device_types[] = { + {"device_none", BCMDRD_DEV_T_NONE}, +#include + {"device_count", BCMDRD_DEV_T_COUNT} +}; + +#define BCMDRD_DEVLIST_ENTRY(_nm,_vn,_dv,_rv,_md,_pi,_bd,_bc,_fn,_cn,_pf,_pd,_r0,_r1) \ + {BCMDRD_DEV_T_##_bd, _dv}, +static const struct { + bcmdrd_dev_type_t dev_type; + uint32 dev_id; +} device_ids[] = { + {BCMDRD_DEV_T_NONE, 0}, +#include + {BCMDRD_DEV_T_COUNT, 0} +}; + +#define BCMLRD_VARIANT_ENTRY(_bd,_bu,_va,_ve,_vu,_vv,_vo,_vd,_r0,_r1)\ + {#_bd, #_ve, BCMLRD_VARIANT_T_##_bd##_##_ve}, +static const struct { + char *dev_name; + char *var_name; + bcmlrd_variant_t var; +} variant_types[] = { + {"device_none", "variant_none", BCMLRD_VARIANT_T_NONE}, +#include + {"device_count", "variant_count", BCMLRD_VARIANT_T_COUNT} +}; + +#ifdef KPMD + +/* BEGIN EXAMPLE PMD CODE */ + +struct name_value_pair_s { + char *name; + int value; +}; + +static struct name_value_pair_s rxpmd_info[] = { + BCMPKT_RXPMD_FIELD_NAME_MAP_INIT +}; + +static struct name_value_pair_s dnx_rxpmd_info[] = { + BCMPKT_RXPMD_DNX_FIELD_NAME_MAP_INIT +}; + +static int +device_type_is_sand(bcmdrd_dev_type_t dev_type) +{ + uint32 dev_family; + if (dev_type <= BCMDRD_DEV_T_NONE || + dev_type >= BCMDRD_DEV_T_COUNT) { + return 0; + } + dev_family = device_ids[dev_type].dev_id & 0xf000; + /** + * 0xb000 : 56xxx (XGS) + * 0xf000 : 78xxx (XGS) + * 0x8000 : 88xxx (DNX) + * 0x9000 : 99xxx (DNX) + */ + if (dev_family == 0x8000 || dev_family == 0x9000) { + return 1; + } + return 0; +} + +static void +print_supported_rxpmd_fields(bcmdrd_dev_type_t dev_type) +{ + int field_id; + bcmpkt_rxpmd_fid_support_t support; + + printk("\nRX Metadata types for this device\n"); + bcmpkt_rxpmd_fid_support_get(dev_type, &support); + BCMPKT_RXPMD_FID_SUPPORT_ITER(support, field_id) { + if (device_type_is_sand(dev_type)) { + printk("Field: %2d [%s]\n", field_id, dnx_rxpmd_info[field_id].name); + } else { + printk("Field: %2d [%s]\n", field_id, rxpmd_info[field_id].name); + } + } +} + +static void +print_all_rxpmd_fields(bcmdrd_dev_type_t dev_type, const uint8_t *rxpmd) +{ + int field_id; + bcmpkt_rxpmd_fid_support_t support; + uint32_t val; + + printk("\nRX Metadata for this packet\n"); + bcmpkt_rxpmd_fid_support_get(dev_type, &support); + + BCMPKT_RXPMD_FID_SUPPORT_ITER(support, field_id) { + int rv = bcmpkt_rxpmd_field_get(dev_type, (uint32_t *) rxpmd, field_id, + &val); + if (rv == 0) { + if (device_type_is_sand(dev_type)) { + printk(" %-26s = %4d [%X]\n", dnx_rxpmd_info[field_id].name, val, + val); + } else { + printk(" %-26s = %4d [%X]\n", rxpmd_info[field_id].name, val, + val); + } + } + } +} + +static void +print_packet_tag_type(bcmdrd_dev_type_t dev_type, const uint8_t *rxpmd) +{ + bcmpkt_rxpmd_fid_support_t support; + uint32_t val; + const char *tag_type[4] = { + "Untagged", + "Inner Tagged", + "Outer Tagged", + "Double Tagged" + }; + + if (device_type_is_sand(dev_type)) { + printk("\nRX Ingress Tag Type: not support on DNX family!\n"); + return; + } + + bcmpkt_rxpmd_fid_support_get(dev_type, &support); + + if (BCMPKT_RXPMD_FID_SUPPORT_GET(support, BCMPKT_RXPMD_ING_TAG_TYPE)) { + int rv = + bcmpkt_rxpmd_field_get(dev_type, (uint32_t *) rxpmd, + BCMPKT_RXPMD_ING_TAG_TYPE, &val); + if (rv == 0) { + printk("\nRX Ingress Tag Type: %s\n", tag_type[val]); + } + } +} + +static void +print_all_supported(bcmdrd_dev_type_t dev_type) +{ + print_supported_rxpmd_fields(dev_type); +} + +/* END EXAMPLE PMD CODE */ +#endif /* KPMD */ + +/*! + * \brief Device Initialization Callback. + * + * The device initialization callback allows an external module to + * perform device-specific initialization in preparation for Tx and Rx + * packet processing. + * + * \param [in] dinfo Device information. + * + */ +static void +init_cb(ngknet_dev_info_t *dinfo) +{ + int unit; + bcmdrd_dev_type_t dt; + bcmlrd_variant_t var; + + unit = dinfo->dev_no; + + if ((unsigned int)unit >= NUM_PDMA_DEV_MAX) { + return; + } + + for (dt = 0; dt < BCMDRD_DEV_T_COUNT; dt++) { + if (!strcasecmp(dinfo->type_str, device_types[dt].name)) { + cb_dev[unit].dev_type = dt; + break; + } + } + + for (var = 0; var < BCMLRD_VARIANT_T_COUNT; var++) { + if ((!strcasecmp(dinfo->type_str, variant_types[var].dev_name)) && + (!strcasecmp(dinfo->var_str, variant_types[var].var_name))) { + cb_dev[unit].var_type = var; + break; + } + } + + printk("%s; unit: %d; dev %s; dev_id: 0x%x variant: %s\n", + __func__, dinfo->dev_no, dinfo->type_str, dinfo->dev_id, dinfo->var_str); + printk(" dev_type: %d\n", cb_dev[unit].dev_type); + printk(" variant: %d\n", cb_dev[unit].var_type); + + cb_dev[unit].initialized = true; + if (pmd_units[unit].added == true) { + pmd_units[unit].valid = true; + printk("%s; setting valid for unit: %d\n", __func__, unit); + } +#ifdef KPMD + print_all_supported(dt); +#else + printk("%s: Not compiled with KPMD\n", __func__); +#endif /* KPMD */ +} + +/* Print 16 hex bytes per line to console */ +static void +print_buffer(const uint8_t *pmd, const int len) +{ + const char *const to_hex = "0123456789ABCDEF"; + int i; + char buffer[64]; + char *buffer_ptr; + int addr = 0; + + buffer_ptr = buffer; + for (i = 0; i < len; i++) { + *buffer_ptr++ = ' '; + if ((i % 16) == 8) { + *buffer_ptr++ = ' '; + } + *buffer_ptr++ = to_hex[(pmd[i] >> 4) & 0xF]; + *buffer_ptr++ = to_hex[pmd[i] & 0xF]; + if (((i % 16) == 15) || (i == len - 1)) { + *buffer_ptr = '\0'; + buffer_ptr = buffer; + printk("%04X %s\n", addr, buffer); + addr = i + 1; + } + } +} + +static void +print_mac(const uint8_t *pkt) +{ + printk("DMAC=%02X:%02X:%02X:%02X:%02X:%02X\n", + pkt[0], pkt[1], pkt[2], pkt[3], pkt[4], pkt[5]); +} + +/*! + * \brief Rx Callback. + * + * The Rx call-back allows an external module to modify packet contents + * before it is handed off to the Linux network stack. + * + * \param [in] skb NGKNET callback description. + * + */ +static struct sk_buff * +test_rx_cb(struct sk_buff *skb) +{ + struct ngknet_callback_desc *cbd = NGKNET_SKB_CB(skb); + int unit = cbd->dinfo->dev_no; + + if (cb_dev[unit].initialized) { + printk("********************************\n"); + printk("%s; device %d: %s; variant: %s\n", __func__, cbd->dinfo->dev_no, + cbd->dinfo->type_str, + variant_types[cb_dev[unit].var_type].var_name); + printk(" dev_type: %d\n", cb_dev[unit].dev_type); + printk(" variant: %d\n", cb_dev[unit].var_type); + + if (cbd->pmd_len != 0) { + printk(" Rx PMD: %d bytes\n", cbd->pmd_len); + print_buffer(cbd->pmd, cbd->pmd_len); +#ifdef KPMD + print_all_rxpmd_fields(cb_dev[unit].dev_type, cbd->pmd); + print_packet_tag_type(cb_dev[unit].dev_type, cbd->pmd); +#endif /* KPMD */ + printk(" Rx Packet: %d bytes\n", cbd->pkt_len); + print_buffer(cbd->pmd + cbd->pmd_len, cbd->pkt_len); + +#ifdef KPMD + /* + * Use the valid flag to control pmd parsing code. + * This is set specifying the units module parameter + */ + if (pmd_units[unit].valid) { + int rv = 0; + uint32_t val; + uint32_t rxpmd_flex[32]; + uint32_t flexdata_len_words; + uint32_t flexdata_len_bytes; + uint32_t *flexdata_addr; + + rv = bcmpkt_rxpmd_field_get(cb_dev[unit].dev_type, + (uint32_t *) cbd->pmd, 1, &val); + if (rv == 0) { + printk("%s; bcmpkt_rxpmd_field_get val: %d\n", __func__, + val); + } else { + printk("%s; bcmpkt_rxpmd_field_get FAILED, rv = %d\n", + __func__, rv); + } + + /* Check whether device supports flex metadata. */ + rv = + bcmpkt_rxpmd_flexdata_get(cb_dev[unit].dev_type, rxpmd_flex, + &flexdata_addr, + &flexdata_len_words); + if (rv == 0) { + flexdata_len_bytes = flexdata_len_words * 4; + printk("%s; flexdata_len_bytes = %d\n", + __func__, flexdata_len_bytes); + } else { + printk("%s; bcmpkt_rxpmd_flexdata_get failed, rv = %d\n", + __func__, rv); + } + } +#endif /* KPMD */ + } + printk("%s; netif user data: 0x%08x\n", __func__, + *(uint32_t *) cbd->netif->user_data); + if (cbd->filt) { + printk("%s; filter user data: 0x%08x\n", __func__, + *(uint32_t *) cbd->filt->user_data); + } + } + + return skb; +} + +/*! + * \brief Tx Callback. + * + * The Tx call-back allows an external module to modify packet contents + * before it is injected into the switch. + * + * \param [in] skb NGKNET callback description. + * + */ +static struct sk_buff * +test_tx_cb(struct sk_buff *skb) +{ + struct ngknet_callback_desc *cbd = NGKNET_SKB_CB(skb); + int unit = cbd->dinfo->dev_no; + + if (cb_dev[unit].initialized) { + printk("********************************\n"); + printk("%s; dev %d: %s; variant: %s\n", __func__, cbd->dinfo->dev_no, + cbd->dinfo->type_str, variant_types[cb_dev[unit].var_type].var_name); + printk(" dev_type: %d\n", cb_dev[unit].dev_type); + printk(" variant: %d\n", cb_dev[unit].var_type); + + if (cbd->pmd_len != 0) { +#ifdef KPMD + int rv = 0; + uint32_t val; + rv = bcmpkt_txpmd_field_get(cb_dev[unit].dev_type, + (uint32_t *) cbd->pmd, 1, &val); + if (rv == 0) { + printk("%s; bcmpkt_txpmd_field_get val: %d\n", __func__, val); + } else { + printk("%s; bcmpkt_txpmd_field_get failed, rv = %d\n", __func__, rv); + } +#endif /* KPMD */ + printk(" Tx PMD: %d bytes\n", cbd->pmd_len); + print_buffer(cbd->pmd, cbd->pmd_len); + printk(" Tx Packet: %d bytes\n", cbd->pkt_len); + print_buffer(cbd->pmd + cbd->pmd_len, cbd->pkt_len); + } + } + + return skb; +} + +static struct sk_buff * +test_filter_cb(struct sk_buff *skb, ngknet_filter_t **filt) +{ + struct ngknet_callback_desc *cbd = NGKNET_SKB_CB(skb); + + printk("********************************\n"); + printk("%s; dev %d: %s\n", __func__, + cbd->dinfo->dev_no, cbd->dinfo->type_str); + + printk(" cbd->pmd_len: %d; cbd->pkt_len: %d;\n", cbd->pmd_len, cbd->pkt_len); + if (cbd->pmd_len != 0) { + print_buffer(cbd->pmd, cbd->pmd_len); + print_mac(cbd->pmd + cbd->pmd_len); + } + if (cbd->filt) { + printk("%s; filter user data: 0x%08x;\n", __func__, + *(uint32_t *)cbd->filt->user_data); + } + if (filt) { + *filt = NULL; + } + return skb; +} + +static struct sk_buff * +test_a_filter_cb(struct sk_buff *skb, ngknet_filter_t **filt) +{ + struct ngknet_callback_desc *cbd = NGKNET_SKB_CB(skb); + printk("%s; dev %d: %s\n", __func__, + cbd->dinfo->dev_no, cbd->dinfo->type_str); + + printk(" cbd->pmd_len: %d; cbd->pkt_len: %d;\n", cbd->pmd_len, cbd->pkt_len); + if (cbd->pmd_len != 0) { + print_buffer(cbd->pmd, cbd->pmd_len); + print_mac(cbd->pmd + cbd->pmd_len); + } + if (cbd->filt) { + printk("%s; filter user data: 0x%08x\n", __func__, + *(uint32_t *)cbd->filt->user_data); + } + if (filt) { + *filt = NULL; + } + return skb; +} + +static struct sk_buff * +test_b_filter_cb(struct sk_buff *skb, ngknet_filter_t **filt) +{ + struct ngknet_callback_desc *cbd = NGKNET_SKB_CB(skb); + + printk("%s; dev %d: %s\n", __func__, + cbd->dinfo->dev_no, cbd->dinfo->type_str); + + printk(" cbd->pmd_len: %d; cbd->pkt_len: %d;\n", cbd->pmd_len, cbd->pkt_len); + if (cbd->pmd_len != 0) { + print_buffer(cbd->pmd, cbd->pmd_len); + print_mac(cbd->pmd + cbd->pmd_len); + } + if (cbd->filt) { + printk("%s; filter user data: 0x%08x;\n", __func__, + *(uint32_t *)cbd->filt->user_data); + } + if (filt) { + *filt = NULL; + } + return skb; +} + +static char *units = NULL; +module_param(units, charp, 0660); + +/* + * Parse the units module parameter and update the pmd_units table + * units='0,1,2' + * units=0 + */ +static void +pmd_parse_init(void) +{ + char *p, *s = NULL; + int pmd_unit; + + if (units != NULL) { + printk("%s; unit param: %s\n", __func__, units); + } else { + printk("%s; unit param not provided\n", __func__); + return; + } + /* Parse the unit value */ + if (strchr(units, ',') != NULL) { + s = units; + p = strchr(s, ','); + while (p) { + *p = '\0'; + pmd_unit = simple_strtol(s, &s, 10); + printk("%s; parameter parsed for unit: %d\n", __func__, pmd_unit); + if ((pmd_unit >= 0) && (pmd_unit < NUM_PDMA_DEV_MAX)) { + pmd_units[pmd_unit].added = true; + printk("%s; setting pmd_units added to true for unit: %d\n", + __func__, pmd_unit); + } + s = &p[1]; + p = strchr(s, ','); + } + pmd_unit = simple_strtol(s, &s, 10); + printk("%s; parameter parsed for unit: %d\n", __func__, pmd_unit); + if ((pmd_unit >= 0) && (pmd_unit < NUM_PDMA_DEV_MAX)) { + pmd_units[pmd_unit].added = true; + printk("%s; setting pmd_units added to true for unit: %d\n", + __func__, pmd_unit); + } + } else { + pmd_unit = simple_strtol(units, &units, 10); + if ((pmd_unit >= 0) && (pmd_unit < NUM_PDMA_DEV_MAX)) { + pmd_units[pmd_unit].added = true; + printk("%s; setting pmd_units added to true for unit: %d\n", + __func__, pmd_unit); + } + } +} + +static int +test_a_netif_create_cb(ngknet_dev_info_t *dinfo, ngknet_netif_t *netif) +{ + int retv = 0; + + printk("%s; device %d: %s\n", __func__, dinfo->dev_no, dinfo->type_str); + + return retv; +} + +static int +test_b_netif_create_cb(ngknet_dev_info_t *dinfo, ngknet_netif_t *netif) +{ + int retv = 0; + + printk("%s; device %d: %s\n", __func__, dinfo->dev_no, dinfo->type_str); + + return retv; +} + + +static int +test_a_netif_destroy_cb(ngknet_dev_info_t *dinfo, ngknet_netif_t *netif) +{ + int retv = 0; + + printk("%s; device %d: %s\n", __func__, + dinfo->dev_no, dinfo->type_str); + + return retv; +} + +static int +test_b_netif_destroy_cb(ngknet_dev_info_t *dinfo, ngknet_netif_t *netif) +{ + int retv = 0; + + printk("%s; device %d: %s\n", __func__, + dinfo->dev_no, dinfo->type_str); + + return retv; +} + +static int __init +ngknetcb_init_module(void) +{ + memset(pmd_units, 0, sizeof(ngknetcb_pmd_unit_t)*NUM_PDMA_DEV_MAX); + pmd_parse_init(); + + printk("%s: Initialize and register callbacks\n", __func__); + ngknet_rx_cb_register(test_rx_cb); + ngknet_tx_cb_register(test_tx_cb); + ngknet_filter_cb_register(test_filter_cb); + ngknet_filter_cb_register_by_name(test_a_filter_cb, "test_a_filter_cb"); + ngknet_filter_cb_register_by_name(test_b_filter_cb, "test_b_filter_cb"); + ngknet_dev_init_cb_register(init_cb); + + /* register callbacks of netif create/destroy */ + ngknet_netif_create_cb_register(test_a_netif_create_cb); + ngknet_netif_create_cb_register(test_b_netif_create_cb); + ngknet_netif_destroy_cb_register(test_a_netif_destroy_cb); + ngknet_netif_destroy_cb_register(test_b_netif_destroy_cb); + + return 0; +} + +static void __exit +ngknetcb_exit_module(void) +{ + printk("%s: Unregister callbacks\n", __func__); + ngknet_rx_cb_unregister(test_rx_cb); + ngknet_tx_cb_unregister(test_tx_cb); + ngknet_filter_cb_unregister(test_a_filter_cb); + ngknet_filter_cb_unregister(test_b_filter_cb); + ngknet_filter_cb_unregister(test_filter_cb); + ngknet_dev_init_cb_unregister(init_cb); + + /* unregister callbacks of netif create/destroy */ + ngknet_netif_create_cb_unregister(test_a_netif_create_cb); + ngknet_netif_create_cb_unregister(test_b_netif_create_cb); + ngknet_netif_destroy_cb_unregister(test_a_netif_destroy_cb); + ngknet_netif_destroy_cb_unregister(test_b_netif_destroy_cb); +} + +module_init(ngknetcb_init_module); +module_exit(ngknetcb_exit_module); diff --git a/systems/linux/kernel/modules/shared/Makefile b/systems/linux/kernel/modules/shared/Makefile index d87d0f6..6598bd5 100644 --- a/systems/linux/kernel/modules/shared/Makefile +++ b/systems/linux/kernel/modules/shared/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.2 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/linux/kernel/modules/shared/gmodule.c b/systems/linux/kernel/modules/shared/gmodule.c index 225caf7..08b9ea6 100644 --- a/systems/linux/kernel/modules/shared/gmodule.c +++ b/systems/linux/kernel/modules/shared/gmodule.c @@ -1,7 +1,7 @@ /* * $Id: gmodule.c,v 1.20 Broadcom SDK $ * - * $Copyright: 2017-2025 Broadcom Inc. All rights reserved. + * $Copyright: 2017-2026 Broadcom Inc. All rights reserved. * * Permission is granted to use, copy, modify and/or distribute this * software under either one of the licenses below. diff --git a/systems/linux/user/common/Makefile b/systems/linux/user/common/Makefile index dbca66a..feb2390 100644 --- a/systems/linux/user/common/Makefile +++ b/systems/linux/user/common/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.4 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. @@ -70,6 +70,7 @@ KERN_BLDROOT=${SDK}/${SDKBUILD}/${BLDCONFIG}/$(kernel-override)$(bldroot_suffix) else ifdef SDK_OUTDIR KERN_BLDROOT=${SDK_OUTDIR}/${SDKBUILD}/$(kernel-override)$(bldroot_suffix) +OUTPUT_DIR=${SDK_OUTDIR}/${SDKBUILD} else KERN_BLDROOT=${SDK}/${SDKBUILD}/$(kernel-override)$(bldroot_suffix) endif @@ -93,6 +94,16 @@ ifeq ($(DEST_DIR),) DEST_DIR=${BLDDIR} endif +# Support quiet make +ifneq (,$(findstring s,$(MAKEFLAGS))) +export quiet = quiet_ +export KBUILD_VERBOSE = 1 +endif + +ifndef KDIR +export KDIR=$(KERNDIR) +endif + KERNEL_BDE_LOCAL := linux-kernel-bde.$(KOBJ) KERNEL_BDE := $(DEST_DIR)/$(KERNEL_BDE_LOCAL) @@ -116,6 +127,12 @@ BCM_GENL := $(DEST_DIR)/$(BCM_GENL_LOCAL) BCM_KNET_LOCAL := linux-bcm-knet.$(KOBJ) BCM_KNET := $(DEST_DIR)/$(BCM_KNET_LOCAL) +BCM_NGKNET_LOCAL := linux-ngknet.$(KOBJ) +BCM_NGKNET := $(DEST_DIR)/$(BCM_NGKNET_LOCAL) + +NGKNETCB_LOCAL := linux-ngknetcb.$(KOBJ) +NGKNETCB := $(DEST_DIR)/$(NGKNETCB_LOCAL) + ifeq (,$(findstring DELIVER,$(MAKECMDGOALS))) .DEFAULT_GOAL := all all_targets := kernel_modules $(KERNEL_BDE) $(USER_BDE) @@ -133,6 +150,13 @@ ifndef BUILD_KNET BUILD_KNET = 1 endif +ifndef BUILD_NGKNET +BUILD_NGKNET = 1 +endif + +#Skip building NGKNET_CB +BUILD_NGKNET_CB = 0 + ifeq ($(BUILD_KNET),1) # Kernel network support all_targets += $(BCM_KNET) @@ -179,6 +203,42 @@ ADD_TO_CFLAGS += -I$(SDK)/systems/linux/kernel/modules/include COND_KNET_LIBS = libuser.$(libext) endif +ifeq (1,$(BUILD_NGKNET)) +# Kernel network support +all_targets += $(BCM_NGKNET) +knet_subdirs += bcm-ngknet + +ifeq ($(NO_LOCAL_TARGETS),) +LOCAL_TARGETS +=$(patsubst %,../$(platform)/%,$(BCM_NGKNET_LOCAL)) +all_targets +=$(LOCAL_TARGETS) +endif + +ifeq (1,$(BUILD_NGKNET_CB)) +all_targets += $(NGKNETCB) +knet_subdirs += ngknetcb + +ifeq ($(NO_LOCAL_TARGETS),) +LOCAL_TARGETS +=$(patsubst %,../$(platform)/%,$(NGKNETCB_LOCAL)) +all_targets +=$(LOCAL_TARGETS) +endif + +ifdef KPMD +KPMD_OPT := KPMD=1 +endif +endif +endif + +ifeq (1,$(BUILD_NGKNET)) +NGKNET_BDE_BLDDIR = $(KERN_BLDROOT)/systems/bde/linux/kernel/kernel_module +NGKNET_LKM_BLDROOT = $(KERN_BLDROOT)/systems/linux/kernel/modules/bcm-ngknet +NGKNET_BLDDIR = $(NGKNET_LKM_BLDROOT) +endif # BUILD_NGKNET + +ifeq (1,$(BUILD_NGKNET_CB)) +NGKNETCB_LKM_BLDROOT = $(KERN_BLDROOT)/systems/linux/kernel/modules/ngknetcb +NGKNETCB_BLDDIR = $(NGKNETCB_LKM_BLDROOT) +endif # BUILD_NGKNET_CB + all: $(BLDDIR)/.tree $(all_targets) ifeq ($(NO_LOCAL_TARGETS),) @@ -224,6 +284,18 @@ endif OPT_CFLAGS="$(ADD_TO_KCFLAGS)" override-target=linux-$(platform) endif endif +ifeq ($(BUILD_NGKNET),1) + $(MAKE) -C $(SDK)/systems/linux/kernel/modules/bcm-ngknet $(OPT_KERNEL_TOOLCHAIN) quiet=$(quiet) LKM_BLDDIR=$(NGKNET_BLDDIR) KBUILD_VERBOSE=$(KBUILD_VERBOSE) \ + KBUILD_EXTRA_SYMBOLS=$(NGKNET_BDE_BLDDIR)/Module.symvers kernel_version=$(kernel_version) OPT_CFLAGS="$(ADD_TO_KCFLAGS)" \ + override-target=linux-$(platform) + (cd $(KERN_BLDROOT); ln -s -f $(NGKNET_BLDDIR)/*.ko ./) +ifneq (,$(filter ngknetcb,$(knet_subdirs))) + $(MAKE) -C $(SDK)/systems/linux/kernel/modules/ngknetcb $(OPT_KERNEL_TOOLCHAIN) $(KPMD_OPT) quiet=$(quiet) LKM_BLDDIR=$(NGKNETCB_BLDDIR) KBUILD_VERBOSE=$(KBUILD_VERBOSE) \ + KBUILD_EXTRA_SYMBOLS=$(NGKNET_BLDDIR)/Module.symvers kernel_version=$(kernel_version) OPT_CFLAGS="$(ADD_TO_KCFLAGS)" \ + override-target=linux-$(platform) + (cd $(KERN_BLDROOT); ln -s -f $(NGKNETCB_BLDDIR)/*.ko ./) +endif +endif $(KERNEL_BDE): $(KERN_BLDROOT)/$(KERNEL_BDE_LOCAL) mkdir -p $(@D) @@ -238,6 +310,12 @@ $(BCM_KNET): $(KERN_BLDROOT)/$(BCM_KNET_LOCAL) $(KNET_CB): $(KERN_BLDROOT)/$(KNET_CB_LOCAL) $(OBJCOPY) --strip-debug $< $@ +$(BCM_NGKNET): $(KERN_BLDROOT)/$(BCM_NGKNET_LOCAL) + $(OBJCOPY) --strip-debug $< $@ + +$(NGKNETCB): $(KERN_BLDROOT)/$(NGKNETCB_LOCAL) + $(OBJCOPY) --strip-debug $< $@ + $(GENL_PACKET): $(KERN_BLDROOT)/$(GENL_PACKET_LOCAL) $(OBJCOPY) --strip-debug $< $@ @@ -259,10 +337,18 @@ clean:: override-target=linux-$(platform) $@ $(RM) $(KERNEL_BDE) $(USER_BDE) $(RM) $(BCM_KNET) $(KNET_CB) $(GENL_PACKET) $(BCM_GENL) +ifdef BUILD_NGKNET + $(RM) $(BCM_NGKNET) +endif +ifdef BUILD_NGKNET_CB + $(RM) $(NGKNETCB) +endif $(RM) $(KERN_BLDROOT)/$(KERNEL_BDE_LOCAL) $(RM) $(KERN_BLDROOT)/$(USER_BDE_LOCAL) $(RM) $(KERN_BLDROOT)/$(BCM_KNET_LOCAL) $(RM) $(KERN_BLDROOT)/$(KNET_CB_LOCAL) + $(RM) $(KERN_BLDROOT)/$(BCM_NGKNET_LOCAL) + $(RM) $(KERN_BLDROOT)/$(NGKNETCB_LOCAL) $(RM) $(KERN_BLDROOT)/$(GENL_PACKET_LOCAL) $(RM) $(KERN_BLDROOT)/$(BCM_GENL_LOCAL) $(RM) $(LOCAL_TARGETS) diff --git a/systems/linux/user/gts/Makefile b/systems/linux/user/gts/Makefile index 4697764..246e374 100644 --- a/systems/linux/user/gts/Makefile +++ b/systems/linux/user/gts/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 0.1 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/linux/user/iproc-3_14/Makefile b/systems/linux/user/iproc-3_14/Makefile index 846dd74..1d016d8 100644 --- a/systems/linux/user/iproc-3_14/Makefile +++ b/systems/linux/user/iproc-3_14/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.7 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/linux/user/iproc-4_4/Makefile b/systems/linux/user/iproc-4_4/Makefile index eff1890..dc0caac 100644 --- a/systems/linux/user/iproc-4_4/Makefile +++ b/systems/linux/user/iproc-4_4/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.7 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/linux/user/iproc/Makefile b/systems/linux/user/iproc/Makefile index 2b0c889..569e2c8 100644 --- a/systems/linux/user/iproc/Makefile +++ b/systems/linux/user/iproc/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.7 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. @@ -54,7 +54,7 @@ endif export SDK -override kernel_version=6_6 +override kernel_version=6_12 platform=iproc IPROC_BUILD=1 diff --git a/systems/linux/user/iproc_64/Makefile b/systems/linux/user/iproc_64/Makefile index 93c56df..52fdb68 100644 --- a/systems/linux/user/iproc_64/Makefile +++ b/systems/linux/user/iproc_64/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.7 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. @@ -54,7 +54,7 @@ endif export SDK -override kernel_version=6_6 +override kernel_version=6_12 platform=iproc_64 IPROC_BUILD=1 diff --git a/systems/linux/user/slk/Makefile b/systems/linux/user/slk/Makefile index 0c052f3..397116f 100644 --- a/systems/linux/user/slk/Makefile +++ b/systems/linux/user/slk/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 0.1 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/linux/user/x86-5_10/Makefile b/systems/linux/user/x86-5_10/Makefile index bdf30d5..5f4f35b 100644 --- a/systems/linux/user/x86-5_10/Makefile +++ b/systems/linux/user/x86-5_10/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 0.1 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/linux/user/x86-64-fc28/Makefile b/systems/linux/user/x86-64-fc28/Makefile index 663755f..e461d77 100644 --- a/systems/linux/user/x86-64-fc28/Makefile +++ b/systems/linux/user/x86-64-fc28/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 0.1 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/linux/user/x86-6_10/Makefile b/systems/linux/user/x86-6_10/Makefile new file mode 100644 index 0000000..68f4411 --- /dev/null +++ b/systems/linux/user/x86-6_10/Makefile @@ -0,0 +1,82 @@ +# -*- Makefile -*- +# $Id: Makefile,v 0.1 Broadcom SDK $ +# +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. +# +# Permission is granted to use, copy, modify and/or distribute this +# software under either one of the licenses below. +# +# License Option 1: GPL +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License, version 2, as +# published by the Free Software Foundation (the "GPL"). +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License version 2 (GPLv2) for more details. +# +# You should have received a copy of the GNU General Public License +# version 2 (GPLv2) along with this source code. +# +# +# License Option 2: Broadcom Open Network Switch APIs (OpenNSA) license +# +# This software is governed by the Broadcom Open Network Switch APIs license: +# https://www.broadcom.com/products/ethernet-connectivity/software/opennsa $ +# +# + +# +# This make job requires the following environment variables to be set: +# +# SDK - path to StrataXGS SDK root directory +# +# Optionally the following environment variables can be set to +# override the default build server configuration: +# +# TOOLS_DIR - path to build tools (if not in PATH already) +# CROSS_COMPILE - cross compile tools prefix +# LINUX_INCLUDE - path to Linux kernel include directory +# + +# SHARED_LIBRARY_SUPPORT will enable the shared library creation - update the BINUTILSVER version. +ifneq ($(filter $(SHARED_LIBRARY_SUPPORT) $(COMPILE_OPENNSA_SUPPORT),1),) +# Newer GNU BINUTILS are neeed in order to avoid a known internal bug +# in GCC that results in a linker error when creating a .so library +export BINUTILSVER = 2.27 +endif + +SDK :=$(shell if [ -n "$$SDK" ] ; then\ + echo $$SDK;\ + else\ + cd $(dir $(lastword $(MAKEFILE_LIST))); while /usr/bin/test ! -e RELEASE ; do \ + dir=`cd ../;pwd`; \ + if [ "$$dir" = "/" ] ; then \ + echo Cannot find SDK in $(lastword $(MAKEFILE_LIST)) 1>&2; \ + exit 1; \ + fi ; \ + cd $$dir; \ + done ; \ + pwd; \ + fi) + +ifeq ($(SDK),) +$(error Please run this in a tree) +endif + +export SDK + +override kernel_version=6_10 +platform=x86-6_10 + +export LINKER_RELAX = 1 + +# SHARED_LIBRARY_SUPPORT will enable the shared library creation - add a PIC to the compilation flags. +ifneq ($(filter $(SHARED_LIBRARY_SUPPORT) $(COMPILE_OPENNSA_SUPPORT),1),) +ADD_TO_CFLAGS = -frecord-gcc-switches -DSAL_THREAD_STACK_MIN=8388608 +export ADD_TO_CFLAGS +endif + +include ${SDK}/make/Make.linux diff --git a/systems/linux/user/x86-smp_generic_64-2_6/Makefile b/systems/linux/user/x86-smp_generic_64-2_6/Makefile index 0e831a6..fba3fbe 100644 --- a/systems/linux/user/x86-smp_generic_64-2_6/Makefile +++ b/systems/linux/user/x86-smp_generic_64-2_6/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 1.2 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/systems/linux/user/xlr/Makefile b/systems/linux/user/xlr/Makefile index 7fa9ad2..3e3b7a4 100644 --- a/systems/linux/user/xlr/Makefile +++ b/systems/linux/user/xlr/Makefile @@ -1,7 +1,7 @@ # -*- Makefile -*- # $Id: Makefile,v 0.1 Broadcom SDK $ # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. diff --git a/tools/mktool.pl b/tools/mktool.pl index 0589a48..7c01d7b 100644 --- a/tools/mktool.pl +++ b/tools/mktool.pl @@ -4,7 +4,7 @@ # $Id: mktool.pl,v 1.5 Broadcom SDK $ # # -# $Copyright: 2017-2025 Broadcom Inc. All rights reserved. +# $Copyright: 2017-2026 Broadcom Inc. All rights reserved. # # Permission is granted to use, copy, modify and/or distribute this # software under either one of the licenses below. From 41b73f328a95b37217c2a351efff3830a58bea86 Mon Sep 17 00:00:00 2001 From: Vijay Anand R Date: Thu, 4 Jun 2026 19:04:03 +0000 Subject: [PATCH 2/4] make clean --- systems/linux/kernel/modules/bcm-ngknet/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/systems/linux/kernel/modules/bcm-ngknet/Makefile b/systems/linux/kernel/modules/bcm-ngknet/Makefile index 04e4d3d..9ed48a0 100644 --- a/systems/linux/kernel/modules/bcm-ngknet/Makefile +++ b/systems/linux/kernel/modules/bcm-ngknet/Makefile @@ -177,6 +177,9 @@ ifeq ($(KERNELRELEASE),) MOD_NAME = linux-ngknet include $(SDK)/make/Make.lkm + +# Make.depend is before clean:: so that Make.depend's clean:: runs first. +include ${SDK}/make/Make.depend endif .PHONY: distclean From b40b6d9f7c323b22e2574acd388757fac5a5db6b Mon Sep 17 00:00:00 2001 From: Vijay Anand R Date: Thu, 4 Jun 2026 19:15:19 +0000 Subject: [PATCH 3/4] fix parameter --- systems/linux/kernel/modules/knet-cb/knet-cb.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/systems/linux/kernel/modules/knet-cb/knet-cb.c b/systems/linux/kernel/modules/knet-cb/knet-cb.c index 55fdca6..73ef66a 100644 --- a/systems/linux/kernel/modules/knet-cb/knet-cb.c +++ b/systems/linux/kernel/modules/knet-cb/knet-cb.c @@ -387,23 +387,23 @@ knet_filter_cb(uint8_t * pkt, int size, int dev_no, void *meta, } static int -/*knet_netif_create_cb(int unit, kcom_netif_t *netif, struct net_device *dev)*/ -knet_netif_create_cb(struct net_device *dev, int unit, kcom_netif_t *netif) +/*knet_netif_create_cb(int unit, kcom_netif_t *netif, uint16 spa, struct net_device *dev)*/ +knet_netif_create_cb(struct net_device *dev, int unit, kcom_netif_t *netif, uint16 spa) { int retv = 0; #ifdef PSAMPLE_SUPPORT - retv = psample_netif_create_cb(unit, netif, dev); + retv = psample_netif_create_cb(unit, netif, spa, dev); #endif return retv; } static int -/*knet_netif_destroy_cb(int unit, kcom_netif_t *netif, struct net_device *dev)*/ -knet_netif_destroy_cb(struct net_device *dev, int unit, kcom_netif_t *netif) +/*knet_netif_destroy_cb(int unit, kcom_netif_t *netif, uint16 spa, struct net_device *dev)*/ +knet_netif_destroy_cb(struct net_device *dev, int unit, kcom_netif_t *netif, uint16 spa) { int retv = 0; #ifdef PSAMPLE_SUPPORT - retv = psample_netif_destroy_cb(unit, netif, dev); + retv = psample_netif_destroy_cb(unit, netif, spa, dev); #endif return retv; } From 1c0cf068014d26177872c47eed6526863ef04240 Mon Sep 17 00:00:00 2001 From: Vijay Anand R Date: Fri, 5 Jun 2026 01:19:06 +0000 Subject: [PATCH 4/4] fix headers --- systems/linux/kernel/modules/bcm-ngknet/Kbuild | 3 +++ 1 file changed, 3 insertions(+) diff --git a/systems/linux/kernel/modules/bcm-ngknet/Kbuild b/systems/linux/kernel/modules/bcm-ngknet/Kbuild index e643620..a2b8224 100644 --- a/systems/linux/kernel/modules/bcm-ngknet/Kbuild +++ b/systems/linux/kernel/modules/bcm-ngknet/Kbuild @@ -39,6 +39,9 @@ endif ifneq ($(SDK_OUTDIR),) INCLUDES := -I$(SDK_OUTDIR)/$(SDKBUILD)/bcm-ngknet/generated/include \ -I$(SDK_OUTDIR)/$(SDKBUILD)/bcm-ngknet/generated +else +INCLUDES := -I$(SDK)/systems/linux/kernel/modules/bcm-ngknet/generated/include \ + -I$(SDK)/systems/linux/kernel/modules/bcm-ngknet/generated endif ccflags-y := $(KNET_CPPFLAGS) $(LKM_CFLAGS) $(LKM_CPPFLAGS) \ -I$(SDK)/include/ \