Findings related to ptx ld modifiers.

[Repeater9]

Description:
When disassembling the CUDA binary with both nvdisasm and cuobjdump, I noticed that load instructions inside branch targets are completely omitted by the NVCC compiler—except those marked with the .volatile modifier. As a result, any timing measured against these loads does not reflect true L1-cache access latency.

I change the function uncached_access_timing_device to store temp to gloabl memory at the end, and I get consistent latency across different load modifiers.

Thank you for your impressive work on gpu Rowhammer attack! It helps me a lot.

[ShaopengLin]

Thanks for reporting this. I am a little busy recently but I promis I will look into it soon!