Add support for interrupts

[shalan]

Add support for receiving interrupts from peripherals. This way, the DMAC can transfer data from FIFO enabled peripherals every time the fifo is full w/o the need for interrupting the CPU. We are going to refer to the FIFO data as a frame.

[shalan]

1. Add a new port PIRQ[3:0]
2. Add a register that specifies the number of frames to be transferred before issuing a CPU interrupt.
3. Add a frame counter; the done signal will be used to decrement this counter. The CPU interrupt is generated on done & (frame_counter == 0).
4. The trigger field bits specify the PIRQ source. If zero, it is SW trigger.

[shalan]

Implemented in 5b4ab25