A detailed description of the overall Analyzer and Inspector concept can be found under Analyzer and Inspector Description. It includes also a list of existing checks.
There are several different possibilites to configure the bahavior of the ErrorAnalyzer. The corresponding description can be found under Configuration File Description.
The logging message generated by the ErrorAnalyzer follow a common structure and format. The corresponding description can be found under Logging Description.
The YAML database, including the information about ErrorAnalyzer, every analyzer used in the run, as well as failure reports and possible fixes, follows a common structure and format. The corresponding description can be found under Database Description.
ErrorAnalyzer generates a big number of different messages. A list of all existing messages can be found under Message Description.
The overall file structure of all ErrorAnalyzer data can be found under the File Structure Description.
There are several examples available to demonstrate the functionality of the ErrorAnalyzer. All examples are placed under the examples directory.
For running the examples a Makefile is available for each example. All examples can be run either with Verilator, Cadence Xcelium or Icarus Verilog.
The directory structure of the examples looks as follows:
<example>
- rtl … containing the RTL design
- testbench … containing the testbench / verification environment
- sim.verilator … simulation directory for Verilator including a make file (`Makefile`) for starting the simulation
- sim.xcelium … simulation directory for Cadence Xcelium including a make file (`Makefile`) for starting the simulation
- sim.icarus … simulation directory for Icarus Verilog including a make file (`Makefile`) for starting the simulation
- sim.cocotb … simulation directory for Icarus Verilog Python verification including a make file (`Makefile`) for starting the simulation
For running examples, first clone the GIT repository to your local machine. Make sure that all required software described above is installed. Change to the simulation directory.
cd example/<example>/sim.verilator
cd ea/example/<example>/sim.xcelium
cd ea/example/<example>/sim.icarus
cd ea/example/<example>/sim.cocotb
Start the simulation
call `make` for running the example
This will compile and run the simulation. Running the simulation using the simple make command runs the simulation without any error. Therefore, ErrorAnalyzer can't provide any error pattern proposal. To show the ErrorAnalyzer features some errors must be present. Errors are enabled by running the make command with different macro definitions. The required macro definitions are example dependent and can be obtained by calling make help . This allows the ErrorAnalyer to provide error pattern suggestions.
Beside the console output ErrorAnalyzer generates the following files.
eaLogFile.log: ErrorAnalyzer log file including reporting of each AnalyzereaAnalyzerSummary.csv: ErrorAnalyzer comma separated file including reporting of fixable fails with error patternseaInspectorWaves.fst: ErrorAnalyzer traces giving details regarding the result of each Analyzer and Inspector in GTKWave FST formateaInspectorWaves.vcd: ErrorAnalyzer traces giving details regarding the result of each Analyzer and Inspector in vcd format
Within each of the examples different errors can be inserted. The errors can selectively enabled via defines. The simulations are started via make command. All available options can be shown via make help.
Not all examples run with all simulators and verification environments (eg cocotb versus plain testbench). An overview of the available examples and the supported simulators can be found under ErrorAnalyzer example matrix. As there are different integration methods for ErrorAnalyzer, a few different approaches can be made. The Verilog Procedural Interface allows user to call ErrorAnalyzer functionality from interactive mode. API functions are enlisted here.
The example meas consists of an RTL design called meas_top. It contains an SPI master with two channels for reading in ADC data, an average for each channel and a second SPI master for transferring the averaged data to a DAC. The ADC and the DAC are modeled within the verification environment as VIPs.
The block diagram of the example design can be found under meas_top_tb.
The table below contains all triggerable errors, which allow modification of the verification environment, together with short description.
| Simulation fail triggers | Error description |
|---|---|
| EA_ERROR_BITSHIFT | Bit shift error |
| EA_ERROR_TIMESHIFT | Time shift error |
| EA_ERROR_SAT | Saturation error |
| EA_ERROR_STUCK | Stuck at error |
The following four commands modify the design and the verification environment to trigger simulation fails.
make EA_ERROR_BITSHIFT='en'
make EA_ERROR_TIMESHIFT='en'
make EA_ERROR_SAT='en'
make EA_ERROR_STUCK='en'
The example shiftreg consists of an RTL design called ste_shift_reg. It contains simple shift register with synchronous clear and a parallel load.
The table below contains all triggerable errors, which allow modification of the verification environment, together with short description.
| Simulation fail triggers | Error description |
|---|---|
| EA_ERROR_BITSHIFT | Bit shift error |
| EA_ERROR_BITSINVERSED | Inversed bits error |
| EA_ERROR_BITSREVERSED | Reversed bits error |
| EA_ERROR_BYTESSWAPPED | Swapped bytes error |
| EA_ERROR_CONST | Constant value error |
The following five commands modify the design and the verification environment to trigger simulation fails.
make EA_ERROR_BITSHIFT='en'
make EA_ERROR_BITSINVERSED='en'
make EA_ERROR_BITSREVERSED='en'
make EA_ERROR_BYTESSWAPPED='en'
make EA_ERROR_CONST='en'
The example division consists of an RTL design called div_int. It divides an integer by another integer and results in a quotient and remainder.
The table below contains all triggerable errors, which allow modification of the verification environment, together with short description.
| Simulation fail triggers | Error description |
|---|---|
| EA_ERROR_DBZ | Division by 0 error |
| EA_ERROR_SHIFT | Bit shift error |
The following two commands modify the design and the verification environment to trigger simulation fails.
make EA_ERROR_DBZ='en'
make EA_ERROR_SHIFT='en'
The example logging shows how to use the various logging functions through the API.