multicycle-risc-v-cpu/makefile at main · secureshellprotocol/multicycle-risc-v-cpu · GitHub

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VCS=#VCS	This can be adapted to `iverilog`
VCSARGS=+incdir+../src +incdir+../tb
DC=#DC Compiler
DCARGS=-topographic
BUILDDIR=build
SYNDIR=syn

.PHONY: simtrigger
simtrigger: sim

sim:
	mkdir -p $(BUILDDIR)

tb_ff_reset: simtrigger
	cd $(BUILDDIR)/ &&\
		$(VCS) $(VCSARGS) ../tb/ff/tb_ff_reset.v &&\
		./simv

tb_ff_reset_enable: simtrigger
	cd $(BUILDDIR)/ &&\
		$(VCS) $(VCSARGS) ../tb/ff/tb_ff_reset_enable.v &&\
		./simv

tb_adder: simtrigger
	cd $(BUILDDIR)/ &&\
		$(VCS) $(VCSARGS) ../tb/tb_adder.v &&\
		./simv

tb_alu: simtrigger
	cd $(BUILDDIR)/ &&\
		$(VCS) $(VCSARGS) ../tb/tb_alu.v &&\
		./simv

tb_top: simtrigger
	cd $(BUILDDIR)/ &&\
		$(VCS) $(VCSARGS) ../tb/tb_top.v &&\
		./simv

synthesis: simtrigger tb_top
	cd $(SYNDIR) &&\
		echo -e 'source ./synthesis.tcl' | $(DC) $(DCARGS)

clean:
	rm -r \
		$(BUILDDIR) sxcmd.log* \
		$(SYNDIR)/*.log $(SYNDIR)/design_lib \
		$(SYNDIR)/reports $(SYNDIR)/results $(SYNDIR)/alib-52 \
		*.log cds.lib .cadence