Merge branch 'main' of https://github.com/rustbox/esp32c3-vgaterm into refactor/nom-it-up

Author: sethp

Cargo.lock

@@ -28,6 +28,7 @@ path  = "src/bin/keypad.rs"
 
 [profile.release]
 opt-level = 2
+lto       = true
 
 [profile.dev]
 debug     = true # Symbols are nice and they don't increase the size on Flash
@@ -40,13 +41,13 @@ critical-section = "1.1.1"
 embedded-graphics = "0.7.1"
 embedded-hal = "0.2"
 esp-alloc = { version = "0.2.0", features = ["oom-handler"] }
-esp-backtrace = { version = "0.6.0", features = [
+esp-backtrace = { version = "0.7.0", features = [
   "esp32c3",
   "panic-handler",
   "exception-handler",
   "print-jtag-serial",
 ] }
-esp-println = { version = "0.4.0", default-features = false, features = [
+esp-println = { version = "0.5.0", default-features = false, features = [
   "esp32c3",
   "jtag_serial",
 ] }
@@ -63,8 +64,11 @@ unroll = "0.1.5"
 
 [dev-dependencies]
 
+[features]
+default  = ["perf_log"]
+perf_log = []
 
 [patch.crates-io]
 # TODO: automate these updates
-esp32c3-hal    = { git = "https://github.com/rustbox/esp-hal", rev = "72aefcc" }
-esp-hal-common = { git = "https://github.com/rustbox/esp-hal", rev = "72aefcc" }
+esp32c3-hal    = { git = "https://github.com/rustbox/esp-hal", rev = "f49dc55" }
+esp-hal-common = { git = "https://github.com/rustbox/esp-hal", rev = "f49dc55" }

Cargo.toml

@@ -13,7 +13,7 @@ This is targeted at the RISC-V architecture esp32-c3 processor from espressif. T
 
 `rustup target add riscv32imc-unknown-none-elf`
 
-3. Using Cargo, install the `espflash` tool which can upload and flash the code across a serial 
+3. Using Cargo, install the `espflash` tool which can upload and flash the code across a serial
 port (through usb) to the esp32 chip:
 
 `cargo install espflash`

README.md

@@ -61,14 +61,18 @@ extern "C" fn stop() -> ! {
 #[entry]
 fn main() -> ! {
     let peripherals = Peripherals::take();
-    let system = peripherals.SYSTEM.split();
+    let mut system = peripherals.SYSTEM.split();
     let clocks = ClockControl::configure(system.clock_control, CpuClock::Clock160MHz).freeze();
 
     // Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
     // the RTC WDT, and the TIMG WDTs.
     let mut rtc = Rtc::new(peripherals.RTC_CNTL);
 
-    let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
+    let timer_group1 = TimerGroup::new(
+        peripherals.TIMG1,
+        &clocks,
+        &mut system.peripheral_clock_control,
+    );
     let mut wdt1 = timer_group1.wdt;
 
     rtc.swd.disable();
@@ -79,8 +83,13 @@ fn main() -> ! {
 
     init_heap();
 
-    vgaterm::configure_timer0(peripherals.TIMG0, &clocks);
-    let mut _rx = vgaterm::uart::configure0(peripherals.UART0);
+    vgaterm::configure_timer0(
+        peripherals.TIMG0,
+        &clocks,
+        &mut system.peripheral_clock_control,
+    );
+    let mut _rx =
+        vgaterm::uart::configure0(peripherals.UART0, &mut system.peripheral_clock_control);
     vgaterm::uart::interrupt_enable0(vgaterm::interrupt::Priority::Priority5);
 
     unsafe {