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Tracking Issue for AVX10 target features #138843
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A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)A-target-featureArea: Enabling/disabling target features like AVX, Neon, etc.Area: Enabling/disabling target features like AVX, Neon, etc.C-tracking-issueCategory: An issue tracking the progress of sth. like the implementation of an RFCCategory: An issue tracking the progress of sth. like the implementation of an RFCO-x86_32Target: x86 processors, 32 bit (like i686-*) (also known as IA-32, i386, i586, i686)Target: x86 processors, 32 bit (like i686-*) (also known as IA-32, i386, i586, i686)O-x86_64Target: x86-64 processors (like x86_64-*) (also known as amd64 and x64)Target: x86-64 processors (like x86_64-*) (also known as amd64 and x64)T-libs-apiRelevant to the library API team, which will review and decide on the PR/issue.Relevant to the library API team, which will review and decide on the PR/issue.
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A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)A-target-featureArea: Enabling/disabling target features like AVX, Neon, etc.Area: Enabling/disabling target features like AVX, Neon, etc.C-tracking-issueCategory: An issue tracking the progress of sth. like the implementation of an RFCCategory: An issue tracking the progress of sth. like the implementation of an RFCO-x86_32Target: x86 processors, 32 bit (like i686-*) (also known as IA-32, i386, i586, i686)Target: x86 processors, 32 bit (like i686-*) (also known as IA-32, i386, i586, i686)O-x86_64Target: x86-64 processors (like x86_64-*) (also known as amd64 and x64)Target: x86-64 processors (like x86_64-*) (also known as amd64 and x64)T-libs-apiRelevant to the library API team, which will review and decide on the PR/issue.Relevant to the library API team, which will review and decide on the PR/issue.
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Feature gate:
#![feature(avx10_target_feature)]This is a tracking issue for Intel
AVX10target features. The official reference to AVX10.1 can be found in chapter 16, Volume 1 of Intel Software Developer's Manual.AVX10 is a "converged vector ISA", which attempts to simplify the mess that AVX512 was (21 ISAs). AVX10.1 is just a cleanup ISA, which implies the following AVX512 ISAs.
avx512bf16avx512bitalgavx512bwavx512cdavx512dqavx512favx512fp16avx512ifmaavx512vbmiavx512vbmi2avx512vlavx512vnniavx512vpopcntdqNotably, the ISAs listed below, even though part of AVX512, will not be part of AVX10.1
avx512er,avx512pf- Deprecated ISAs, were only available in the KNL and KNM series, neither Rust/LLVM nor GCC supports them anymoreavx5124fmaps,avx5124vnniw- Deprecated ISAs, were only available in the KNM series, neither Rust/LLVM nor GCC supports themavx512vp2intersect- Only Intel CPU to support it was TigerLake, recently AMD has added support in Zen5vaes,vpclmulqdq,gfni- Intel probably wants to keep these separate from other SIMD intrinsicsAVX10.2 introduces a lot of new instructions (these have not yet been added to SDM, the latest reference is this)
This tracking issue is meant to be incremental, i.e. new target features will be added as Intel publishes new versions of AVX10, and old versions will be stabilized.
Public API
The following target features and their associated intrinsics in
stdarchavx10.1avx10.2Implementation History:
Unresolved Questions
Related: #111137, #44839
@rustbot label O-x86-32 O-x86_64 A-target-feature A-SIMD