librustc_back: enable fpxx on 32-bit hardfloat mips targets

See this page for details about FPXX:
https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking

Using FPXX is the most compatible floating point mode available and
allows the generated code to work in both FR0 and FR1 modes of the
processor. Using MSA (MIPS SIMD) requires FR1, so to use any MSA code we
need a compatible floating point mode.

This commit also sets nooddspreg (disabling the use of odd numbered
single precision float registers) as recommended when enabling FPXX.

Author: jcowgill

src/librustc_back/target/mips_unknown_linux_gnu.rs

@@ -25,7 +25,7 @@ pub fn target() -> TargetResult {
         linker_flavor: LinkerFlavor::Gcc,
         options: TargetOptions {
             cpu: "mips32r2".to_string(),
-            features: "+mips32r2".to_string(),
+            features: "+mips32r2,+fpxx,+nooddspreg".to_string(),
             max_atomic_width: Some(32),
 
             // see #36994

src/librustc_back/target/mipsel_unknown_linux_gnu.rs

@@ -26,7 +26,7 @@ pub fn target() -> TargetResult {
 
         options: TargetOptions {
             cpu: "mips32r2".to_string(),
-            features: "+mips32r2".to_string(),
+            features: "+mips32r2,+fpxx,+nooddspreg".to_string(),
             max_atomic_width: Some(32),
 
             // see #36994