Require infallible chipselect pins

Author: GrantM11235

embedded-hal-bus/src/spi/critical_section.rs

@@ -1,10 +1,10 @@
 use core::cell::RefCell;
+use core::convert::Infallible;
 use critical_section::Mutex;
 use embedded_hal::delay::DelayNs;
 use embedded_hal::digital::OutputPin;
 use embedded_hal::spi::{ErrorType, Operation, SpiBus, SpiDevice};
 
-use super::DeviceError;
 use crate::spi::shared::transaction;
 
 /// `critical-section`-based shared bus [`SpiDevice`] implementation.
@@ -61,15 +61,15 @@ impl<'a, BUS, CS> CriticalSectionDevice<'a, BUS, CS, super::NoDelay> {
 impl<'a, BUS, CS, D> ErrorType for CriticalSectionDevice<'a, BUS, CS, D>
 where
     BUS: ErrorType,
-    CS: OutputPin,
+    CS: OutputPin<Error = Infallible>,
 {
-    type Error = DeviceError<BUS::Error, CS::Error>;
+    type Error = BUS::Error;
 }
 
 impl<'a, Word: Copy + 'static, BUS, CS, D> SpiDevice<Word> for CriticalSectionDevice<'a, BUS, CS, D>
 where
     BUS: SpiBus<Word>,
-    CS: OutputPin,
+    CS: OutputPin<Error = Infallible>,
     D: DelayNs,
 {
     #[inline]

embedded-hal-bus/src/spi/exclusive.rs

@@ -1,5 +1,7 @@
 //! SPI bus sharing mechanisms.
 
+use core::convert::Infallible;
+
 use embedded_hal::delay::DelayNs;
 use embedded_hal::digital::OutputPin;
 use embedded_hal::spi::{ErrorType, Operation, SpiBus, SpiDevice};
@@ -10,7 +12,6 @@ use embedded_hal_async::{
 };
 
 use super::shared::transaction;
-use super::DeviceError;
 
 /// [`SpiDevice`] implementation with exclusive access to the bus (not shared).
 ///
@@ -72,15 +73,15 @@ impl<BUS, CS> ExclusiveDevice<BUS, CS, super::NoDelay> {
 impl<BUS, CS, D> ErrorType for ExclusiveDevice<BUS, CS, D>
 where
     BUS: ErrorType,
-    CS: OutputPin,
+    CS: OutputPin<Error = Infallible>,
 {
-    type Error = DeviceError<BUS::Error, CS::Error>;
+    type Error = BUS::Error;
 }
 
 impl<Word: Copy + 'static, BUS, CS, D> SpiDevice<Word> for ExclusiveDevice<BUS, CS, D>
 where
     BUS: SpiBus<Word>,
-    CS: OutputPin,
+    CS: OutputPin<Error = Infallible>,
     D: DelayNs,
 {
     #[inline]
@@ -94,15 +95,17 @@ where
 impl<Word: Copy + 'static, BUS, CS, D> AsyncSpiDevice<Word> for ExclusiveDevice<BUS, CS, D>
 where
     BUS: AsyncSpiBus<Word>,
-    CS: OutputPin,
+    CS: OutputPin<Error = Infallible>,
     D: AsyncDelayNs,
 {
     #[inline]
     async fn transaction(
         &mut self,
         operations: &mut [Operation<'_, Word>],
     ) -> Result<(), Self::Error> {
-        self.cs.set_low().map_err(DeviceError::Cs)?;
+        use crate::spi::shared::into_ok;
+
+        into_ok(self.cs.set_low());
 
         let op_res = 'ops: {
             for op in operations {
@@ -128,12 +131,8 @@ where
 
         // On failure, it's important to still flush and deassert CS.
         let flush_res = self.bus.flush().await;
-        let cs_res = self.cs.set_high();
-
-        op_res.map_err(DeviceError::Spi)?;
-        flush_res.map_err(DeviceError::Spi)?;
-        cs_res.map_err(DeviceError::Cs)?;
+        into_ok(self.cs.set_high());
 
-        Ok(())
+        op_res.and(flush_res)
     }
 }

embedded-hal-bus/src/spi/mod.rs

@@ -1,7 +1,6 @@
 //! `SpiDevice` implementations.
 
 use core::fmt::Debug;
-use embedded_hal::spi::{Error, ErrorKind};
 
 mod exclusive;
 pub use exclusive::*;
@@ -19,30 +18,6 @@ pub use self::critical_section::*;
 #[cfg(feature = "defmt-03")]
 use crate::defmt;
 
-/// Error type for [`ExclusiveDevice`] operations.
-#[derive(Copy, Clone, Eq, PartialEq, Debug)]
-#[cfg_attr(feature = "defmt-03", derive(defmt::Format))]
-pub enum DeviceError<BUS, CS> {
-    /// An inner SPI bus operation failed.
-    Spi(BUS),
-    /// Asserting or deasserting CS failed.
-    Cs(CS),
-}
-
-impl<BUS, CS> Error for DeviceError<BUS, CS>
-where
-    BUS: Error + Debug,
-    CS: Debug,
-{
-    #[inline]
-    fn kind(&self) -> ErrorKind {
-        match self {
-            Self::Spi(e) => e.kind(),
-            Self::Cs(_) => ErrorKind::ChipSelectFault,
-        }
-    }
-}
-
 /// Dummy [`DelayNs`](embedded_hal::delay::DelayNs) implementation that panics on use.
 #[derive(Copy, Clone, Eq, PartialEq, Debug)]
 #[cfg_attr(feature = "defmt-03", derive(defmt::Format))]

embedded-hal-bus/src/spi/mutex.rs

@@ -1,9 +1,10 @@
+use core::convert::Infallible;
+
 use embedded_hal::delay::DelayNs;
 use embedded_hal::digital::OutputPin;
 use embedded_hal::spi::{ErrorType, Operation, SpiBus, SpiDevice};
 use std::sync::Mutex;
 
-use super::DeviceError;
 use crate::spi::shared::transaction;
 
 /// `std` `Mutex`-based shared bus [`SpiDevice`] implementation.
@@ -59,15 +60,15 @@ impl<'a, BUS, CS> MutexDevice<'a, BUS, CS, super::NoDelay> {
 impl<'a, BUS, CS, D> ErrorType for MutexDevice<'a, BUS, CS, D>
 where
     BUS: ErrorType,
-    CS: OutputPin,
+    CS: OutputPin<Error = Infallible>,
 {
-    type Error = DeviceError<BUS::Error, CS::Error>;
+    type Error = BUS::Error;
 }
 
 impl<'a, Word: Copy + 'static, BUS, CS, D> SpiDevice<Word> for MutexDevice<'a, BUS, CS, D>
 where
     BUS: SpiBus<Word>,
-    CS: OutputPin,
+    CS: OutputPin<Error = Infallible>,
     D: DelayNs,
 {
     #[inline]

embedded-hal-bus/src/spi/refcell.rs

@@ -1,9 +1,9 @@
 use core::cell::RefCell;
+use core::convert::Infallible;
 use embedded_hal::delay::DelayNs;
 use embedded_hal::digital::OutputPin;
 use embedded_hal::spi::{ErrorType, Operation, SpiBus, SpiDevice};
 
-use super::DeviceError;
 use crate::spi::shared::transaction;
 
 /// `RefCell`-based shared bus [`SpiDevice`] implementation.
@@ -58,15 +58,15 @@ impl<'a, BUS, CS> RefCellDevice<'a, BUS, CS, super::NoDelay> {
 impl<'a, BUS, CS, D> ErrorType for RefCellDevice<'a, BUS, CS, D>
 where
     BUS: ErrorType,
-    CS: OutputPin,
+    CS: OutputPin<Error = Infallible>,
 {
-    type Error = DeviceError<BUS::Error, CS::Error>;
+    type Error = BUS::Error;
 }
 
 impl<'a, Word: Copy + 'static, BUS, CS, D> SpiDevice<Word> for RefCellDevice<'a, BUS, CS, D>
 where
     BUS: SpiBus<Word>,
-    CS: OutputPin,
+    CS: OutputPin<Error = Infallible>,
     D: DelayNs,
 {
     #[inline]

embedded-hal-bus/src/spi/shared.rs

@@ -1,24 +1,24 @@
+use core::convert::Infallible;
+
 use embedded_hal::delay::DelayNs;
 use embedded_hal::digital::OutputPin;
 use embedded_hal::spi::{ErrorType, Operation, SpiBus};
 
-use crate::spi::DeviceError;
-
 /// Common implementation to perform a transaction against the device.
 #[inline]
 pub fn transaction<Word, BUS, CS, D>(
     operations: &mut [Operation<Word>],
     bus: &mut BUS,
     delay: &mut D,
     cs: &mut CS,
-) -> Result<(), DeviceError<BUS::Error, CS::Error>>
+) -> Result<(), BUS::Error>
 where
     BUS: SpiBus<Word> + ErrorType,
-    CS: OutputPin,
+    CS: OutputPin<Error = Infallible>,
     D: DelayNs,
     Word: Copy,
 {
-    cs.set_low().map_err(DeviceError::Cs)?;
+    into_ok(cs.set_low());
 
     let op_res = operations.iter_mut().try_for_each(|op| match op {
         Operation::Read(buf) => bus.read(buf),
@@ -34,11 +34,15 @@ where
 
     // On failure, it's important to still flush and deassert CS.
     let flush_res = bus.flush();
-    let cs_res = cs.set_high();
+    into_ok(cs.set_high());
 
-    op_res.map_err(DeviceError::Spi)?;
-    flush_res.map_err(DeviceError::Spi)?;
-    cs_res.map_err(DeviceError::Cs)?;
+    op_res.and(flush_res)
+}
 
-    Ok(())
+/// see https://github.com/rust-lang/rust/issues/61695
+pub(crate) fn into_ok<T>(res: Result<T, Infallible>) -> T {
+    match res {
+        Ok(t) => t,
+        Err(infallible) => match infallible {},
+    }
 }