From 9c4987c5770f27d0c964d6f8ec44d4d45f561cfe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=87a=C4=9Fatay=20Yi=C4=9Fit=20=C5=9Eahin?= Date: Fri, 3 Jul 2026 18:46:14 +0200 Subject: [PATCH] Add missing TGran4 value An additional value is defined in the Arm A-profile Architecture Registers documentation (https://developer.arm.com/documentation/ddi0601/2026-06/AArch64-Registers/ID-AA64MMFR0-EL1--AArch64-Memory-Model-Feature-Register-0#fieldset_0-31_28). --- packages/aarch64-cpu/src/registers/id_aa64mmfr0_el1.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/packages/aarch64-cpu/src/registers/id_aa64mmfr0_el1.rs b/packages/aarch64-cpu/src/registers/id_aa64mmfr0_el1.rs index 1d48a98..1e13ccb 100644 --- a/packages/aarch64-cpu/src/registers/id_aa64mmfr0_el1.rs +++ b/packages/aarch64-cpu/src/registers/id_aa64mmfr0_el1.rs @@ -17,11 +17,13 @@ register_bitfields! {u64, /// Support for 4KiB memory translation granule size. Defined values are: /// /// 0000 4KiB granule supported. + /// 0001 4KiB granule supports 52-bit input addresses and can describe 52-bit output addresses. (Applies when FEAT_LPA2 is implemented) /// 1111 4KiB granule not supported. /// /// All other values are reserved. TGran4 OFFSET(28) NUMBITS(4) [ Supported = 0b0000, + SupportedWith52BitAddresses = 0b0001, NotSupported = 0b1111 ],