Commit d263897
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Arm backend: Fix two control flow bugs (#16274)
Arm backend: Regularize submodules before processing them.
Add a function _regularize_submodule that contains special
handling needed for submodules. This mainly solves two problems:
- Buffers in submodules are (currently) handled differently depending
on whether they are from tracing or added in passes. The old solution
tried avoiding having to add a new meta field, but was brittle.
The new solution simply marks all all placeholders before passes.
- The pass pipeline assumes the dim_order of inputs and outputs to match
the actual dim_order (tosa_dim_order). We need to ensure this.
------------------------
Arm backend: Fix while quantization
The output of the while loop body can either re-enter
the body, or exit the while loop. Therefore, A and B
in the diagrambelow need to share the same quantization parameters.
A -> while ( RESCALE -> ... -> RESCALE -> ) -> B
Earlier tests happened to get equal qparams on the
input and output, but this is not the general case.
Signed-off-by: Erik Lundell <erik.lundell@arm.com>1 parent 84b4a33 commit d263897
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lines changed- backends/arm
- quantizer
- test/ops
- tosa
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