Guidance Request: Setting up and Running a RISC-V Multicore Ara SoC #430
Description
I am currently studying the Ara vector co-processor and working to reproduce the multi-core experiments described in your paper, “Exploring Single- and Multi-Core Vector Processing with an Efficient RVV 1.0 Compliant Open-Source Processor”. In particular, the "Multicore Analysis" section benchmarks several configurations, such as an 8-core CVA6 system where each core is connected to a 2-lane Ara co-processor.
So far, I have successfully familiarized myself with the single-core ara_soc setup and understand how Ara connects to one CVA6 instance. However, being new to multicore, I am struggling to extend this to a Multicore Ara SoC. I could not find documentation or clear examples in the repository that explain how to scale up the design.
My Goal
To create, simulate, and run benchmarks on a multicore Ara SoC, similar to the configurations tested in the paper. I would also like to learn more about multicore SoC design and execution models in general. Also, suggest some starter resources on multicore RISC-V SoCs and Ara-like designs.
What I Need Guidance On
- Hardware Configuration
- What is the intended way to instantiate multiple ara_system clusters to form a multicore SoC?
- Which SystemVerilog files and parameters should be modified? Currently, hardware/src/ara_soc.sv looks like a single-core design, and it’s not clear how to extend it for multiple CVA6+Ara pairs.
- Recommended Learning Resources
- Since I’m just beginning to explore multicore SoC design, any pointers to introductory resources, example projects, or documentation would be hugely helpful.
- Are there other open-source multicore RISC-V SoC architectures that you’d recommend I look into to get a better feel of real-world multicore designs?
As a first step, I’d like to begin with a dual-core configuration to observe the practical speed-up. Would someone be able to provide a clear, step-by-step checklist (which files/parameters to edit, exact build/simulation commands, and how to collect timing/performance results)?
Thank you for your time and for maintaining this open-source project!
If anyone can help me, I will be very grateful!