Check whether we can access vs1 and vs2 in VMADC/VMSBC

[Zissi-Lei]

In ara_dispatcher, when it decodes a VMADC/VMSBC instruction, you check accessibilities of vs1 and vs2 using
unique case (ara_req_d.emul)
LMUL_2:
if ((insn.varith_type.rs2 & 5'b00001) == (insn.varith_type.rd & 5'b00001))
illegal_insn = 1'b1;
LMUL_4:
if ((insn.varith_type.rs2 & 5'b00011) == (insn.varith_type.rd & 5'b00011))
illegal_insn = 1'b1;
LMUL_8:
if ((insn.varith_type.rs2 & 5'b00111) == (insn.varith_type.rd & 5'b00111))
illegal_insn = 1'b1;
default: if (insn.varith_type.rs2 == insn.varith_type.rd) illegal_insn = 1'b1;
endcase
I don't understand what you want to do here. Actually in LMUL_2, when rd=v6 and vs2=v2 will cause a illegal instruction according to these code. But this is legal in rvv. Can you explain it detailly? Thanks for your time!

[mp-17]

Solving various bugs here: #353. Namely, this bug is fixed with this commit.