ManyRVData/Bender.yml at main · pulp-platform/ManyRVData · GitHub

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# Copyright 2025 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51

package:
  name: cachepool

dependencies:
  axi:                 { git: "https://github.com/pulp-platform/axi.git",                version: =0.39.1-beta         }
  axi_riscv_atomics:   { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",  version: 0.7.0                }
  common_cells:        { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.28.0               }
  FPnew:               { git: "https://github.com/pulp-platform/cvfpu.git",              rev:     pulp-v0.1.3          }
  idma:                { git: "https://github.com/pulp-platform/iDMA.git",               version: 0.4.2                }
  register_interface:  { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8                }
  riscv-dbg:           { git: "https://github.com/pulp-platform/riscv-dbg.git",          version: 0.7.0                }
  tech_cells_generic:  { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11               }
  Insitu-Cache:        { git: "https://github.com/pulp-platform/Insitu-Cache.git",       rev:     zexin/cachepool_dev  }
  spatz:               { git: "https://github.com/pulp-platform/spatz.git",              rev:     cachepool-32b        }
  dram_rtl_sim:        { git: "https://github.com/pulp-platform/dram_rtl_sim.git",       rev:     cachepool            }

workspace:
  checkout_dir: "./hardware/deps"

export_include_dirs:

sources:
  # Level 0
  - hardware/src/reqrsp_xbar.sv
  - hardware/src/tcdm_cache_interco.sv
  - hardware/src/tcdm_id_remapper.sv
  - hardware/src/spatz_cache_amo.sv
  # Memory-mapped register
  - hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv
  - hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv
  - hardware/cachepool_peripheral/cachepool_peripheral.sv
  # Bootrom
  - hardware/bootrom/bootrom.sv
  # Barrier
  - hardware/src/cachepool_tile_barrier.sv
  - hardware/src/cachepool_cluster_barrier.sv
  # Level 1
  - hardware/src/cachepool_pkg.sv
  - hardware/src/cachepool_cc.sv
  # Level 2
  - hardware/src/cachepool_tile.sv
  # Level 3
  - hardware/src/cachepool_group.sv

  - hardware/src/cachepool_cluster.sv
  # Level 4
  - hardware/tb/cachepool_cluster_wrapper.sv
  # testbench
  - target: cachepool_test
    files:
    - hardware/tb/axi_uart.sv
    - hardware/tb/tb_cachepool.sv