sim-safe.c

/* sim-safe.c - sample functional simulator implementation */

/* SimpleScalar(TM) Tool Suite
 * Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
 * All Rights Reserved. 
 * 
 * THIS IS A LEGAL DOCUMENT, BY USING SIMPLESCALAR,
 * YOU ARE AGREEING TO THESE TERMS AND CONDITIONS.
 * 
 * No portion of this work may be used by any commercial entity, or for any
 * commercial purpose, without the prior, written permission of SimpleScalar,
 * LLC (info@simplescalar.com). Nonprofit and noncommercial use is permitted
 * as described below.
 * 
 * 1. SimpleScalar is provided AS IS, with no warranty of any kind, express
 * or implied. The user of the program accepts full responsibility for the
 * application of the program and the use of any results.
 * 
 * 2. Nonprofit and noncommercial use is encouraged. SimpleScalar may be
 * downloaded, compiled, executed, copied, and modified solely for nonprofit,
 * educational, noncommercial research, and noncommercial scholarship
 * purposes provided that this notice in its entirety accompanies all copies.
 * Copies of the modified software can be delivered to persons who use it
 * solely for nonprofit, educational, noncommercial research, and
 * noncommercial scholarship purposes provided that this notice in its
 * entirety accompanies all copies.
 * 
 * 3. ALL COMMERCIAL USE, AND ALL USE BY FOR PROFIT ENTITIES, IS EXPRESSLY
 * PROHIBITED WITHOUT A LICENSE FROM SIMPLESCALAR, LLC (info@simplescalar.com).
 * 
 * 4. No nonprofit user may place any restrictions on the use of this software,
 * including as modified by the user, by any other authorized user.
 * 
 * 5. Noncommercial and nonprofit users may distribute copies of SimpleScalar
 * in compiled or executable form as set forth in Section 2, provided that
 * either: (A) it is accompanied by the corresponding machine-readable source
 * code, or (B) it is accompanied by a written offer, with no time limit, to
 * give anyone a machine-readable copy of the corresponding source code in
 * return for reimbursement of the cost of distribution. This written offer
 * must permit verbatim duplication by anyone, or (C) it is distributed by
 * someone who received only the executable form, and is accompanied by a
 * copy of the written offer of source code.
 * 
 * 6. SimpleScalar was developed by Todd M. Austin, Ph.D. The tool suite is
 * currently maintained by SimpleScalar LLC (info@simplescalar.com). US Mail:
 * 2395 Timbercrest Court, Ann Arbor, MI 48105.
 * 
 * Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
 */


#include <stdio.h>
#include <stdlib.h>
#include <math.h>

#include "host.h"
#include "misc.h"
#include "machine.h"
#include "regs.h"
#include "memory.h"
#include "loader.h"
#include "syscall.h"
#include "sdb.h"
#include "options.h"
#include "stats.h"
#include "sim.h"

/*
 * This file implements a functional simulator.  This functional simulator is
 * the simplest, most user-friendly simulator in the simplescalar tool set.
 * Unlike sim-fast, this functional simulator checks for all instruction
 * errors, and the implementation is crafted for clarity rather than speed.
 */

/* simulated registers */
static struct regs_t regs;

/* simulated memory - not static because machine.c needs access */
struct mem_t *mem = NULL;

/* debug trace flag for detailed output */
int debug_trace = FALSE;  /* Disable excessive debug output */

/* comprehensive memory and register debugging */
int debug_mem_regs = FALSE;  /* Disable detailed debugging for production */

/* temporary: trace specific instructions near crash */
static int trace_near_crash = FALSE;

/* Debug counter for diagnosing loops */
static unsigned long long trap_redirect_count = 0;

/* Instruction execution counter */
static unsigned long long insn_exec_count = 0;

/* trap redirect state for handling traps in functional simulator */
int trap_redirect_pending = FALSE;
md_addr_t trap_redirect_PC = 0;

/* Signal trap redirect function (called from trap handlers) */
void
md_signal_trap_redirect(md_addr_t redirect_pc)
{
    extern struct regs_t regs;
    if (debug_mem_regs) {
        fprintf(stderr, "\n>>> SIGNAL_REDIRECT: PC=0x%08x CWP=%d WIM=0x%02x <<<\n", 
                (unsigned)redirect_pc, regs.regs_R.CWP, regs.regs_C.WIM);
        fprintf(stderr, "    Setting trap_redirect_pending=TRUE, redirect_PC=0x%08x\n",
                (unsigned)redirect_pc);
    }
    trap_redirect_pending = TRUE;
    trap_redirect_PC = redirect_pc;
}

/* ASI cache diagnostic stubs - sim-safe does not simulate caches */
word_t asi_0x02_load(md_addr_t addr) { return 0; }
void asi_0x02_store(md_addr_t addr, word_t data) { }
word_t asi_icache_tag_read(md_addr_t addr) { return 0; }
void asi_icache_tag_write(md_addr_t addr, word_t data) { }
word_t asi_icache_data_read(md_addr_t addr) { return 0; }
void asi_icache_data_write(md_addr_t addr, word_t data) { }
word_t asi_dcache_tag_read(md_addr_t addr) { return 0; }
void asi_dcache_tag_write(md_addr_t addr, word_t data) { }
word_t asi_dcache_data_read(md_addr_t addr) { return 0; }
void asi_dcache_data_write(md_addr_t addr, word_t data) { }

/* track number of refs */
static counter_t sim_num_refs = 0;

/* maximum number of inst's to execute */
static unsigned int max_insts;

/* benchmark seed and count for SPEC benchmarks */
static int bench_seed = 0;
static int bench_count = 0;
static char *bench_file = NULL;


/* register simulator-specific options */
void
sim_reg_options(struct opt_odb_t *odb)
{
  opt_reg_header(odb, 
"sim-safe: This simulator implements a functional simulator.  This\n"
"functional simulator is the simplest, most user-friendly simulator in the\n"
"simplescalar tool set.  Unlike sim-fast, this functional simulator checks\n"
"for all instruction errors, and the implementation is crafted for clarity\n"
"rather than speed.\n"
		 );

  /* instruction limit */
  opt_reg_uint(odb, "-max:inst", "maximum number of inst's to execute",
	       &max_insts, /* default */0,
	       /* print */TRUE, /* format */NULL);

  /* benchmark arguments */
  opt_reg_int(odb, "-bench:seed", "benchmark seed value for SPEC benchmarks",
	      &bench_seed, /* default */0,
	      /* print */TRUE, /* format */NULL);

  opt_reg_int(odb, "-bench:count", "benchmark count value for SPEC benchmarks",
	      &bench_count, /* default */0,
	      /* print */TRUE, /* format */NULL);

  opt_reg_string(odb, "-bench:file", "benchmark input file path for SPEC benchmarks",
		 &bench_file, /* default */NULL,
		 /* print */TRUE, /* format */NULL);

}

/* check simulator-specific option values */
void
sim_check_options(struct opt_odb_t *odb, int argc, char **argv)
{
  /* nada */
}

/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
  stat_reg_counter(sdb, "sim_num_insn",
		   "total number of instructions executed",
		   &sim_num_insn, sim_num_insn, NULL);
  stat_reg_counter(sdb, "sim_num_refs",
		   "total number of loads and stores executed",
		   &sim_num_refs, 0, NULL);
  stat_reg_int(sdb, "sim_elapsed_time",
	       "total simulation time in seconds",
	       &sim_elapsed_time, 0, NULL);
  stat_reg_formula(sdb, "sim_inst_rate",
		   "simulation speed (in insts/sec)",
		   "sim_num_insn / sim_elapsed_time", NULL);
  ld_reg_stats(sdb);
  mem_reg_stats(mem, sdb);
}

/* initialize the simulator */
void
sim_init(void)
{
  sim_num_refs = 0;

  /* allocate and initialize register file */
  regs_init(&regs);

  /* allocate and initialize memory space */
  mem = mem_create("mem");
  mem_init(mem);
}

/* load program into simulated state */
void
sim_load_prog(char *fname,		/* program to load */
	      int argc, char **argv,	/* program arguments */
	      char **envp)		/* program environment */
{
  char **new_argv = NULL;
  int new_argc = argc;
  
  /* If bench_seed or bench_count are set, add them to argv */
  if (bench_seed != 0 || bench_count != 0)
    {
      /* Allocate new argv array with space for 2 extra arguments */
      new_argv = (char **)calloc(argc + 3, sizeof(char *));
      if (!new_argv)
        fatal("out of memory allocating new argv");
      
      /* Copy original argv[0] (program name) */
      new_argv[0] = argv[0];
      new_argc = 1;
      
      /* Add bench_seed if non-zero */
      if (bench_seed != 0)
        {
          new_argv[new_argc] = (char *)malloc(32);
          sprintf(new_argv[new_argc], "%d", bench_seed);
          new_argc++;
        }
      
      /* Add bench_count if non-zero */
      if (bench_count != 0)
        {
          new_argv[new_argc] = (char *)malloc(32);
          sprintf(new_argv[new_argc], "%d", bench_count);
          new_argc++;
        }
      
      /* Copy remaining original arguments */
      for (int i = 1; i < argc; i++)
        {
          new_argv[new_argc] = argv[i];
          new_argc++;
        }
      
      new_argv[new_argc] = NULL;
      
      /* Use new argv */
      argv = new_argv;
      argc = new_argc;
    }
  
  /* load program text and data, set up environment, memory, and regs */
  ld_load_prog(fname, argc, argv, envp, &regs, mem, TRUE);
  
  /* Initialize WIM register for window overflow/underflow detection */
  md_init_wim(&regs);
  
  /* Note: Don't write bench_file here - program initialization will overwrite it.
   * It will be written after some instructions have executed, in the main loop. */
  
  /* Free allocated memory if we created new_argv */
  if (new_argv)
    {
      for (int i = 1; i < argc; i++)
        {
          if (i <= (bench_seed != 0 ? 1 : 0) + (bench_count != 0 ? 1 : 0))
            free(new_argv[i]);
        }
      free(new_argv);
    }

  /* initialize the SDB (SPARC Debugger) */
  sdb_init(md_reg_obj, sdb_mem_obj, sdb_mstate_obj);
}

/* print simulator-specific configuration information */
void
sim_aux_config(FILE *stream)		/* output stream */
{
  /* nothing currently */
}

/* dump simulator-specific auxiliary simulator statistics */
void
sim_aux_stats(FILE *stream)		/* output stream */
{
  /* nada */
}

/* un-initialize simulator-specific state */
void
sim_uninit(void)
{
  /* nada */
}


/*
 * configure the execution engine
 */

/*
 * precise architected register accessors
 */

/* next program counter */
/* SPARC has delay slots: the instruction after a branch executes (unless annulled) */
#define SET_NPC(EXPR)		do { \
  delay_slot_target = (EXPR); \
  delay_slot_active = TRUE; \
  delay_slot_annul = FALSE; \
} while (0)

/* SET_NPC with annul support - if annul=TRUE, delay slot is skipped */
#define SET_NPC_ANNUL(EXPR, ANNUL)	do { \
  delay_slot_target = (EXPR); \
  delay_slot_active = TRUE; \
  delay_slot_annul = (ANNUL); \
} while (0)

/* current program counter */
#define CPC			(regs.regs_PC)

/* general purpose registers */
#define GPR(N)			(regs.regs_R[N])
#define SET_GPR(N,EXPR)		(regs.regs_R[N] = (EXPR))

#if defined(TARGET_PISA)

/* floating point registers, L->word, F->single-prec, D->double-prec */
#define FPR_L(N)		(regs.regs_F.l[(N)])
#define SET_FPR_L(N,EXPR)	(regs.regs_F.l[(N)] = (EXPR))
#define FPR_F(N)		(regs.regs_F.f[(N)])
#define SET_FPR_F(N,EXPR)	(regs.regs_F.f[(N)] = (EXPR))
#define FPR_D(N)		(regs.regs_F.d[(N) >> 1])
#define SET_FPR_D(N,EXPR)	(regs.regs_F.d[(N) >> 1] = (EXPR))

/* miscellaneous register accessors */
#define SET_HI(EXPR)		(regs.regs_C.hi = (EXPR))
#define HI			(regs.regs_C.hi)
#define SET_LO(EXPR)		(regs.regs_C.lo = (EXPR))
#define LO			(regs.regs_C.lo)
#define FCC			(regs.regs_C.fcc)
#define SET_FCC(EXPR)		(regs.regs_C.fcc = (EXPR))

#elif defined(TARGET_ALPHA)

/* floating point registers, L->word, F->single-prec, D->double-prec */
#define FPR_Q(N)		(regs.regs_F.q[N])
#define SET_FPR_Q(N,EXPR)	(regs.regs_F.q[N] = (EXPR))
#define FPR(N)			(regs.regs_F.d[(N)])
#define SET_FPR(N,EXPR)		(regs.regs_F.d[(N)] = (EXPR))

/* miscellaneous register accessors */
#define FPCR			(regs.regs_C.fpcr)
#define SET_FPCR(EXPR)		(regs.regs_C.fpcr = (EXPR))
#define UNIQ			(regs.regs_C.uniq)
#define SET_UNIQ(EXPR)		(regs.regs_C.uniq = (EXPR))
#elif defined(TARGET_SPARC)
/* general register dependence decoders */
#define DGPR(N)         (N) 
#define DFPR(N)         ((N)+32)

#undef GPR
#define GPR(N)                  md_get_gpr(&regs, (N))
#undef SET_GPR
#define SET_GPR(N,EXPR)         md_set_gpr(&regs, (N), (EXPR))

/* Local PC access macros required by instruction implementations */
/* SPARC has delay slots: the instruction after a branch executes (unless annulled) */
#define SET_NPC(EXPR)		do { \
  delay_slot_target = (EXPR); \
  delay_slot_active = TRUE; \
  delay_slot_annul = FALSE; \
} while (0)

/* SET_NPC with annul support - if annul=TRUE, delay slot is skipped */
#define SET_NPC_ANNUL(EXPR, ANNUL)	do { \
  delay_slot_target = (EXPR); \
  delay_slot_active = TRUE; \
  delay_slot_annul = (ANNUL); \
} while (0)

/* current program counter */
#define CPC			(regs.regs_PC)

/* floating point register accessors */
/* N is 0-31. F uses 32-bit sfloat_t array. */
#define FPR_F(N)  regs.regs_F.f[(N)]
#define SET_FPR_F(N,EXPR) (regs.regs_F.f[(N)] = (EXPR))

/* N is 0, 2, 4... D uses 64-bit dfloat_t array, indexed by N/2 
 * Cross-endian: swap words so f[N]=MSW, f[N+1]=LSW matches SPARC semantics */
#define FPR_D(N)  MD_SWAPD_WORDS(regs.regs_F.d[(N) >> 1])
#define SET_FPR_D(N,EXPR) (regs.regs_F.d[(N) >> 1] = MD_SWAPD_WORDS(EXPR))

/* N is 0, 4, 8... Q uses 128-bit (quad) floating point, indexed by N/4 */
#define FPR_Q(N)  regs.regs_F.q[(N) >> 2]
#define SET_FPR_Q(N,EXPR) (regs.regs_F.q[(N) >> 2] = (EXPR))

/* miscellaneous register dependence decoders */
#define DPSR            (0+32+32) [cite: 3]
#define DY              (1+32+32)
#define DTBR            (2+32+32)
#define DFSR            (3+32+32) /* (matches sparc.h) */

/* FP Status Register (%fsr) is regs_C.fsr (assumed index 3) */
#define FSR		regs.regs_C.fsr
#define SET_FSR(EXPR)		(regs.regs_C.fsr = (EXPR))
/* === END OF ADDED MACROS === */

#else
#error No ISA target defined...
#endif

/* precise architected memory state accessor macros */
#define READ_BYTE(SRC, FAULT)						\
  ((FAULT) = md_fault_none, addr = (SRC), MEM_READ_BYTE(mem, addr))
#define READ_HALF(SRC, FAULT)						\
  ((FAULT) = md_fault_none, addr = (SRC), MEM_READ_HALF(mem, addr))
#define READ_WORD(SRC, FAULT)						\
  ((FAULT) = md_fault_none, addr = (SRC), MEM_READ_WORD(mem, addr))
#ifdef HOST_HAS_QWORD
#define READ_QWORD(SRC, FAULT)						\
  ((FAULT) = md_fault_none, addr = (SRC), MEM_READ_QWORD(mem, addr))
#endif /* HOST_HAS_QWORD */

#define WRITE_BYTE(SRC, DST, FAULT)					\
  ((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_BYTE(mem, addr, (SRC)))
#define WRITE_HALF(SRC, DST, FAULT)					\
  ((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_HALF(mem, addr, (SRC)))
#define WRITE_WORD(SRC, DST, FAULT)					\
  ((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_WORD(mem, addr, (SRC)))
#ifdef HOST_HAS_QWORD
#define WRITE_QWORD(SRC, DST, FAULT)					\
  ((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_QWORD(mem, addr, (SRC)))
#endif /* HOST_HAS_QWORD */

/* system call handler macro */
#define SYSCALL(INST)	sys_syscall(&regs, mem_access, mem, INST, TRUE)

/* SPARC Delay Slot Support */
static int delay_slot_active = FALSE;      /* TRUE if we just executed a control transfer */
static md_addr_t delay_slot_target = 0;    /* Target PC to jump to after delay slot */
static int delay_slot_annul = FALSE;       /* TRUE if delay slot should be annulled (skipped) */

/* start simulation, program loaded, processor precise state initialized */
void
sim_main(void)
{
  md_inst_t inst;
  register md_addr_t addr;
  enum md_opcode op;
  register int is_write;
  enum md_fault_type fault;

  fprintf(stderr, "sim: ** starting functional simulation **\n");
  
  /* Debug: Check initial argc/argv setup */
  word_t argc = md_get_gpr(&regs, 8);  /* %o0 */
  md_addr_t argv_ptr = md_get_gpr(&regs, 9);  /* %o1 */
  fprintf(stderr, "DEBUG sim_main: argc=%u, argv_ptr=0x%llx\n", 
          argc, (unsigned long long)argv_ptr);
  
  /* Read argv[0] and argv[1] pointers */
  if (argc >= 1) {
    md_addr_t arg0_ptr;
    mem_access(mem, Read, argv_ptr, &arg0_ptr, sizeof(md_addr_t));
    fprintf(stderr, "DEBUG sim_main: argv[0] pointer = 0x%llx\n", 
            (unsigned long long)arg0_ptr);
    
    if (argc >= 2) {
      md_addr_t arg1_ptr;
      mem_access(mem, Read, argv_ptr + sizeof(md_addr_t), &arg1_ptr, sizeof(md_addr_t));
      fprintf(stderr, "DEBUG sim_main: argv[1] pointer = 0x%llx\n", 
              (unsigned long long)arg1_ptr);
      
      /* Try to read the actual argv[1] string */
      char arg1_str[256];
      int i;
      for (i = 0; i < 255; i++) {
        byte_t ch;
        mem_access(mem, Read, arg1_ptr + i, &ch, 1);
        arg1_str[i] = ch;
        if (ch == 0) break;
      }
      arg1_str[255] = 0;
      fprintf(stderr, "DEBUG sim_main: argv[1] string = '%s'\n", arg1_str);
    }
  }
  fflush(stderr);

  /* set up initial default next PC */
  regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);

  /* check for SDB (SPARC Debugger) entry condition */
  if (sdb_check_break(regs.regs_PC, /* !access */0, /* addr */0, 0, 0))
    sdb_main(regs.regs_PC - sizeof(md_inst_t),
	       regs.regs_PC, sim_num_insn, &regs, mem);

  /* Write benchmark file after BSS initialization (after ~1000 instructions) */
  static int bench_file_written = 0;
  
  while (TRUE)
    {
      /* maintain $r0 semantics */
      regs.regs_R.phys_gpr[MD_REG_ZERO] = 0;
#ifdef TARGET_ALPHA
      regs.regs_F.d[MD_REG_ZERO] = 0.0;
#endif /* TARGET_ALPHA */

      /* get the next instruction to execute */
      MD_FETCH_INST(inst, mem, regs.regs_PC);

      /* Trace near crash point - __stdio_fwrite is at 0x189f0, crash at 0x189f4 */
      if (trace_near_crash && regs.regs_PC >= 0x110c4 && regs.regs_PC <= 0x189f8) {
        /* Trace the call path to __stdio_fwrite */
        if (regs.regs_PC == 0x110c4 || regs.regs_PC == 0x110dc || 
            regs.regs_PC == 0x110e4 || regs.regs_PC == 0x110e8 ||
            regs.regs_PC == 0x189f0 || regs.regs_PC == 0x189f4) {
          fprintf(stderr, "TRACE@0x%05x: CWP=%d o0=%08x o1=%08x o2=%08x i0=%08x i1=%08x i2=%08x\n",
                  (unsigned)regs.regs_PC, regs.regs_R.CWP,
                  (unsigned)GPR(8), (unsigned)GPR(9), (unsigned)GPR(10),
                  (unsigned)GPR(24), (unsigned)GPR(25), (unsigned)GPR(26));
          fflush(stderr);
        }
      }

      /* keep an instruction count */
      sim_num_insn++;
      
      /* Write bench_file after initial BSS clearing but before main() */
      if (!bench_file_written && bench_file != NULL && sim_num_insn == 1000) {
        md_addr_t bench_file_addr = 0x501b8;
        fprintf(stderr, "\nWriting bench:file '%s' to 0x%llx at instruction %lld\n",
                bench_file, (unsigned long long)bench_file_addr, (long long)sim_num_insn);
        
        size_t file_len = strlen(bench_file);
        for (size_t i = 0; i <= file_len; i++) {
          byte_t ch = (i < file_len) ? bench_file[i] : 0;
          mem_access(mem, Write, bench_file_addr + i, &ch, sizeof(byte_t));
        }
        fprintf(stderr, "Wrote %zu bytes\n\n", file_len + 1);
        fflush(stderr);
        bench_file_written = 1;
      }

      /* set default reference address and access mode */
      addr = 0; is_write = FALSE;

      /* set default fault - none */
      fault = md_fault_none;

      /* decode the instruction */
      MD_SET_OPCODE(op, inst);

      insn_exec_count++;
      
      /* Debug: trace every 10000th instruction with full register context */
      if (debug_mem_regs && (insn_exec_count % 10000 == 0)) {
        fprintf(stderr, "\n=== INSN %llu at PC=0x%08x NPC=0x%08x ===\n",
                insn_exec_count, (unsigned)regs.regs_PC, (unsigned)regs.regs_NPC);
        fprintf(stderr, "  CWP=%d WIM=0x%02x PSR=0x%08x\n",
                regs.regs_R.CWP, regs.regs_C.WIM, regs.regs_C.PSR);
        fprintf(stderr, "  %%o0-%%o3: 0x%08x 0x%08x 0x%08x 0x%08x\n",
                (unsigned)GPR(8), (unsigned)GPR(9), (unsigned)GPR(10), (unsigned)GPR(11));
        fprintf(stderr, "  %%o6(sp): 0x%08x %%o7(ret): 0x%08x\n",
                (unsigned)GPR(14), (unsigned)GPR(15));
        fprintf(stderr, "  %%i0-%%i3: 0x%08x 0x%08x 0x%08x 0x%08x\n",
                (unsigned)GPR(24), (unsigned)GPR(25), (unsigned)GPR(26), (unsigned)GPR(27));
        fprintf(stderr, "  %%i6(fp): 0x%08x %%i7(ret): 0x%08x\n",
                (unsigned)GPR(30), (unsigned)GPR(31));
      }
      
      /* Debug: trace every 10000th instruction with full context */
      if (debug_mem_regs && (insn_exec_count % 10000 == 0)) {
        fprintf(stderr, "\n=== INSN %llu at PC=0x%08x NPC=0x%08x ===",
                insn_exec_count, (unsigned)regs.regs_PC, (unsigned)regs.regs_NPC);
        fprintf(stderr, "\n  CWP=%d WIM=0x%02x PSR=0x%08x\n",
                regs.regs_R.CWP, regs.regs_C.WIM, regs.regs_C.PSR);
        fprintf(stderr, "  %%o0-%%o3: 0x%08x 0x%08x 0x%08x 0x%08x\n",
                (unsigned)GPR(8), (unsigned)GPR(9), (unsigned)GPR(10), (unsigned)GPR(11));
        fprintf(stderr, "  %%o6(sp): 0x%08x %%o7(ret): 0x%08x\n",
                (unsigned)GPR(14), (unsigned)GPR(15));
        fprintf(stderr, "  %%i0-%%i3: 0x%08x 0x%08x 0x%08x 0x%08x\n",
                (unsigned)GPR(24), (unsigned)GPR(25), (unsigned)GPR(26), (unsigned)GPR(27));
        fprintf(stderr, "  %%i6(fp): 0x%08x %%i7(ret): 0x%08x\n",
                (unsigned)GPR(30), (unsigned)GPR(31));
      }

      /* execute the instruction */
      switch (op)
	{
#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3)		\
	case OP:							\
          SYMCAT(OP,_IMPL);						\
          break;
#define DEFLINK(OP,MSK,NAME,MASK,SHIFT)					\
        case OP:							\
          panic("attempted to execute a linking opcode");
#define CONNECT(OP)
#define DECLARE_FAULT(FAULT)						\
	  { fault = (FAULT); break; }
#include "machine.def"
	default:
	  panic("attempted to execute a bogus opcode");
      }
      /* Debug output removed */
      if (fault != md_fault_none) {
        fprintf(stderr, "FAULT DEBUG: PC=0x%08x fault=%d\n", (unsigned)regs.regs_PC, fault);
        fprintf(stderr, "  %%i0-%%i7: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
                (unsigned)GPR(24), (unsigned)GPR(25), (unsigned)GPR(26), (unsigned)GPR(27),
                (unsigned)GPR(28), (unsigned)GPR(29), (unsigned)GPR(30), (unsigned)GPR(31));
        fprintf(stderr, "  %%o0-%%o7: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
                (unsigned)GPR(8), (unsigned)GPR(9), (unsigned)GPR(10), (unsigned)GPR(11),
                (unsigned)GPR(12), (unsigned)GPR(13), (unsigned)GPR(14), (unsigned)GPR(15));
        /* Dump stdout FILE structure at 0x40070 */
        fprintf(stderr, "  FILE* at 0x40020: ");
        for (int dbg_i = 0; dbg_i < 8; dbg_i++) {
            fprintf(stderr, "%08x ", MEM_READ_WORD(mem, 0x40020 + dbg_i*4));
        }
        fprintf(stderr, "\n  FILE struct at 0x40070: ");
        for (int dbg_i = 0; dbg_i < 8; dbg_i++) {
            fprintf(stderr, "%08x ", MEM_READ_WORD(mem, 0x40070 + dbg_i*4));
        }
        fprintf(stderr, "\n");
	fatal("fault (%d) detected @ 0x%08p", fault, regs.regs_PC);
      }

      if (verbose)
	{
	  myfprintf(stderr, "%10n [xor: 0x%08x] @ 0x%08p: ",
		    sim_num_insn, md_xor_regs(&regs), regs.regs_PC);
	  md_print_insn(inst, regs.regs_PC, stderr);
	  if (MD_OP_FLAGS(op) & F_MEM)
	    myfprintf(stderr, "  mem: 0x%08p", addr);
	  fprintf(stderr, "\n");
	  /* fflush(stderr); */
	}

      if (MD_OP_FLAGS(op) & F_MEM)
	{
	  sim_num_refs++;
      if (MD_OP_FLAGS(op) & F_STORE)
	    is_write = TRUE;
	}

      /* check for SDB (SPARC Debugger) entry condition */
      if (sdb_check_break(regs.regs_NPC,
			    is_write ? ACCESS_WRITE : ACCESS_READ,
			    addr, sim_num_insn, sim_num_insn))
	sdb_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, &regs, mem);

      /* Check for trap redirect (window overflow/underflow) */
      if (debug_mem_regs && (sim_num_insn % 5000 == 0)) {
        fprintf(stderr, "CHECK[%llu]: pending=%d PC=0x%08x CWP=%d WIM=0x%02x\n",
                sim_num_insn, trap_redirect_pending, (unsigned)regs.regs_PC,
                regs.regs_R.CWP, regs.regs_C.WIM);
      }
      
      if (trap_redirect_pending) {
        if (debug_mem_regs) {
          fprintf(stderr, "\n*** TRAP REDIRECT #%llu: PC=0x%08x->0x%08x CWP=%d WIM=0x%02x ***\n",
                  trap_redirect_count + 1, (unsigned)regs.regs_PC, 
                  (unsigned)trap_redirect_PC, regs.regs_R.CWP, regs.regs_C.WIM);
        }
        /* Re-execute the instruction that triggered overflow/underflow */
        regs.regs_PC = trap_redirect_PC;
        regs.regs_NPC = trap_redirect_PC + sizeof(md_inst_t);
        trap_redirect_pending = FALSE;
        trap_redirect_PC = 0;
        trap_redirect_count++;
        if (trap_redirect_count % 100 == 0) {
          fprintf(stderr, "DEBUG: Trap redirect count: %llu at PC=0x%x\n", 
                  trap_redirect_count, (unsigned)regs.regs_PC);
        }
        /* Don't update sim_num_insn - this is a re-execution */
        continue;  /* Skip rest of loop, go back to fetch */
      }

      /* Debug: Periodic progress report */
      if (debug_mem_regs && (sim_num_insn % 50000 == 0)) {
        fprintf(stderr, "\n### PROGRESS: %llu instructions, PC=0x%08x, trap_redirects=%llu ###\n",
                sim_num_insn, (unsigned)regs.regs_PC, trap_redirect_count);
      }

      /* SPARC Delay Slot Handling - check BEFORE updating PC */
      
      /* Determine next NPC based on delay slot state */
      if (delay_slot_active == 2) {
        /* We just executed the delay slot - jump to the saved target */
        regs.regs_NPC = delay_slot_target;
        delay_slot_active = FALSE;
        delay_slot_target = 0;
        delay_slot_annul = FALSE;
      } else if (delay_slot_active == TRUE) {
        /* We just executed a control transfer */
        if (delay_slot_annul) {
          /* Delay slot is annulled - skip it and jump directly to target */
          regs.regs_NPC = delay_slot_target;
          delay_slot_active = FALSE;
          delay_slot_target = 0;
          delay_slot_annul = FALSE;
        } else {
          /* Normal delay slot - execute it next, then jump */
          regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);  /* Delay slot is sequential after current PC */
          delay_slot_active = 2;  /* Mark that delay slot will execute next */
        }
      } else {
        /* Normal sequential execution */
        regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
      }
      
      /* Now update PC to NPC */
      regs.regs_PC = regs.regs_NPC;

      /* finish early? */
      if (max_insts && sim_num_insn >= max_insts)
	return;
    }
}