reset.c

/*
 * reset.c - CPU Reset Implementation for UT699/LEON3FT SPARC V8 Processor
 * 
 * Implements CPU reset, register initialization, and system state reset.
 */

#include <stdio.h>
#include <string.h>
#include "sim.h"
#include "regs.h"
#include "memory.h"
#include "machine.h"
#include "reset.h"
#include "interrupt.h"

/*
 * Perform a CPU reset of the specified type
 * This initializes all registers and system state to reset values
 */
void
cpu_reset(reset_type_t reset_type, struct regs_t *regs, struct mem_t *mem)
{
    int i;
    
    fprintf(stderr, "CPU: Performing reset (type=%d)\n", reset_type);
    
    /* Clear all integer registers */
    for (i = 0; i < PHYS_GPR_FILE_SIZE; i++) {
        regs->regs_R.phys_gpr[i] = 0;
    }
    
    /* Clear all floating point registers */
    for (i = 0; i < MD_NUM_FREGS; i++) {
        regs->regs_F.f[i] = 0.0;
    }
    
    /* Initialize control registers */
    regs->regs_C.Y = 0;              /* Y register - multiply/divide */
    regs->regs_C.PSR = PSR_S_MASK;   /* PSR: Supervisor mode, traps disabled */
    regs->regs_C.WIM = 1;            /* WIM: Only window 0 valid initially */
    regs->regs_C.TBR = 0;            /* TBR: Trap Base Register */
    regs->regs_C.fsr = 0;            /* FSR: Floating-point Status Register */
    
    /* Set initial PSR state: S=1 (supervisor), ET=0 (traps disabled), PIL=15 (all masked) */
    regs->regs_C.PSR |= PSR_PIL_MASK;     /* PIL = 15 (all interrupts masked) */
    regs->regs_C.PSR &= ~PSR_ET_MASK;     /* ET = 0 (traps disabled) */
    regs->regs_C.PSR |= PSR_S_MASK;       /* S = 1 (supervisor mode) */
    
    /* Set CWP (Current Window Pointer) to 0 */
    regs->regs_C.PSR = (regs->regs_C.PSR & ~PSR_CWP_MASK) | 0;
    regs->regs_R.CWP = 0;
    
    /* Initialize PC and NPC to reset vector */
    regs->regs_PC = RESET_VECTOR;
    regs->regs_NPC = RESET_VECTOR + sizeof(md_inst_t);
    
    /* Stack pointer is register %o6 (reg 14 in current window)
     * We'll use md_set_gpr once initialized via machine.h functions */
    
    /* Note: Interrupt controller is managed separately in the simulator */
    /* It should be reset using interrupt_init(&int_ctrl) from the caller */
    
    if (debug_trace) {
        fprintf(stderr, "CPU: Reset complete\n");
        fprintf(stderr, "  PC=0x%08x, NPC=0x%08x\n", 
                (unsigned)regs->regs_PC, (unsigned)regs->regs_NPC);
        fprintf(stderr, "  PSR=0x%08x (S=%d, ET=%d, PIL=%d, CWP=%d)\n",
                (unsigned)regs->regs_C.PSR,
                (regs->regs_C.PSR >> PSR_S_BIT) & 1,
                (regs->regs_C.PSR >> PSR_ET_BIT) & 1,
                (regs->regs_C.PSR >> PSR_PIL_SHIFT) & 0xF,
                (regs->regs_C.PSR) & PSR_CWP_MASK);
        fprintf(stderr, "  WIM=0x%08x, TBR=0x%08x\n",
                (unsigned)regs->regs_C.WIM, (unsigned)regs->regs_C.TBR);
    }
}

/*
 * Initialize CPU for execution with entry point
 * This is called after program loading
 */
void
cpu_initialize(struct regs_t *regs, md_addr_t entry_point)
{
    fprintf(stderr, "CPU: Initializing for execution at 0x%x\n", (unsigned)entry_point);
    
    /* Set PC to entry point */
    regs->regs_PC = entry_point;
    regs->regs_NPC = entry_point + sizeof(md_inst_t);
    
    /* Enable traps (set ET bit in PSR) */
    regs->regs_C.PSR |= PSR_ET_MASK;
    
    /* Set PIL to 0 (all interrupts enabled) */
    regs->regs_C.PSR &= ~PSR_PIL_MASK;
    
    if (debug_trace) {
        fprintf(stderr, "CPU: Initialization complete, PSR=0x%08x\n",
                (unsigned)regs->regs_C.PSR);
    }
}