peripherals.h

/* peripherals.h - LEON3/UT699 Memory-Mapped I/O Peripheral Definitions */

/*
 * SPARC V8 UT699/LEON3FT Simulator - Peripheral Emulation
 * 
 * This file defines the memory-mapped I/O (MMIO) regions and register
 * addresses for UT699/LEON3 peripherals. The address map follows the
 * GRLIB IP Core conventions used in LEON3FT processors.
 * 
 * Memory Map Overview:
 *   0x00000000 - 0x7FFFFFFF: RAM/ROM (program memory)
 *   0x80000000 - 0x8FFFFFFF: APB Peripherals
 *   0x90000000 - 0x9FFFFFFF: AHB Peripherals (optional)
 */

#ifndef PERIPHERALS_H
#define PERIPHERALS_H

#include "host.h"
#include "machine.h"

/*===========================================================================
 * MMIO Address Regions
 *===========================================================================*/

/* APB Bus Base Address */
#define APB_BASE            0x80000000
#define APB_SIZE            0x10000000  /* 256 MB */

/* Check if address is in MMIO region */
#define IS_MMIO_ADDR(addr)  ((addr) >= APB_BASE)

/*===========================================================================
 * Interrupt Controller (IRQ) - Based on GRLIB IRQMP
 * Base Address: 0x80000200
 *===========================================================================*/

#define IRQ_BASE            0x80000200

/* Interrupt Controller Registers */
#define IRQ_LEVEL           (IRQ_BASE + 0x00)   /* Interrupt Level Register */
#define IRQ_PENDING         (IRQ_BASE + 0x04)   /* Interrupt Pending Register */
#define IRQ_FORCE           (IRQ_BASE + 0x08)   /* Interrupt Force Register */
#define IRQ_CLEAR           (IRQ_BASE + 0x0C)   /* Interrupt Clear Register */
#define IRQ_STATUS          (IRQ_BASE + 0x10)   /* Multiprocessor Status */
#define IRQ_BROADCAST       (IRQ_BASE + 0x14)   /* Broadcast Register */
#define IRQ_MASK            (IRQ_BASE + 0x40)   /* Processor 0 IRQ Mask */
#define IRQ_MASK_FORCE      (IRQ_BASE + 0x44)   /* Processor 0 Force Register */
#define IRQ_EXT_ACK         (IRQ_BASE + 0x48)   /* Extended Interrupt Ack */

/* Interrupt Levels */
#define IRQ_LEVEL_TIMER1    8   /* General Purpose Timer 1 */
#define IRQ_LEVEL_TIMER2    9   /* General Purpose Timer 2 */
#define IRQ_LEVEL_UART1     3   /* UART 1 */
#define IRQ_LEVEL_UART2     4   /* UART 2 */
#define IRQ_LEVEL_GPIO      5   /* GPIO */
#define IRQ_LEVEL_SPACEWIRE 10  /* SpaceWire */
#define IRQ_LEVEL_NMI       15  /* Non-Maskable Interrupt */

/*===========================================================================
 * General Purpose Timer Unit (GPTIMER) - Based on GRLIB GPTIMER
 * Base Address: 0x80000300
 *===========================================================================*/

#define TIMER_BASE          0x80000300

/* Timer Unit Configuration */
#define TIMER_SCALER_CNT    (TIMER_BASE + 0x00)   /* Scaler Counter Value */
#define TIMER_SCALER_RLD    (TIMER_BASE + 0x04)   /* Scaler Reload Value */
#define TIMER_CONFIG        (TIMER_BASE + 0x08)   /* Configuration Register */

/* Timer 1 Registers (offset 0x10) */
#define TIMER1_COUNTER      (TIMER_BASE + 0x10)   /* Counter Value */
#define TIMER1_RELOAD       (TIMER_BASE + 0x14)   /* Reload Value */
#define TIMER1_CONTROL      (TIMER_BASE + 0x18)   /* Control Register */
#define TIMER1_LATCH        (TIMER_BASE + 0x1C)   /* Latch Register */

/* Timer 2 Registers (offset 0x20) */
#define TIMER2_COUNTER      (TIMER_BASE + 0x20)   /* Counter Value */
#define TIMER2_RELOAD       (TIMER_BASE + 0x24)   /* Reload Value */
#define TIMER2_CONTROL      (TIMER_BASE + 0x28)   /* Control Register */
#define TIMER2_LATCH        (TIMER_BASE + 0x2C)   /* Latch Register */

/* Timer Control Register Bits */
#define TIMER_CTRL_EN       (1 << 0)  /* Enable */
#define TIMER_CTRL_RS       (1 << 1)  /* Restart on underflow */
#define TIMER_CTRL_LD       (1 << 2)  /* Load counter from reload */
#define TIMER_CTRL_IE       (1 << 3)  /* Interrupt enable */
#define TIMER_CTRL_IP       (1 << 4)  /* Interrupt pending */
#define TIMER_CTRL_CH       (1 << 5)  /* Chain mode */
#define TIMER_CTRL_DH       (1 << 6)  /* Debug halt */

/* Timer Configuration Register Bits */
#define TIMER_CFG_NTIMERS_MASK  0x7     /* Number of timers (bits 2:0) */
#define TIMER_CFG_IRQ_MASK      0xF8    /* IRQ number (bits 7:3) */
#define TIMER_CFG_SI            (1 << 8)  /* Separate interrupts */
#define TIMER_CFG_DF            (1 << 9)  /* Disable freeze */
#define TIMER_CFG_EL            (1 << 10) /* Enable latching */

/*===========================================================================
 * UART (APB UART) - Based on GRLIB APBUART
 * UART 1 Base: 0x80000100
 * UART 2 Base: 0x80000200 (alternate: 0x80100100)
 *===========================================================================*/

#define UART1_BASE          0x80000100
#define UART2_BASE          0x80100100

/* UART Register Offsets */
#define UART_DATA_OFF       0x00    /* Data Register */
#define UART_STATUS_OFF     0x04    /* Status Register */
#define UART_CONTROL_OFF    0x08    /* Control Register */
#define UART_SCALER_OFF     0x0C    /* Scaler/Baud Rate Register */
#define UART_FIFO_DBG_OFF   0x10    /* FIFO Debug Register */

/* UART Absolute Addresses */
#define UART1_DATA          (UART1_BASE + UART_DATA_OFF)
#define UART1_STATUS        (UART1_BASE + UART_STATUS_OFF)
#define UART1_CONTROL       (UART1_BASE + UART_CONTROL_OFF)
#define UART1_SCALER        (UART1_BASE + UART_SCALER_OFF)

#define UART2_DATA          (UART2_BASE + UART_DATA_OFF)
#define UART2_STATUS        (UART2_BASE + UART_STATUS_OFF)
#define UART2_CONTROL       (UART2_BASE + UART_CONTROL_OFF)
#define UART2_SCALER        (UART2_BASE + UART_SCALER_OFF)

/* UART Status Register Bits */
#define UART_STAT_DR        (1 << 0)  /* Data Ready */
#define UART_STAT_TS        (1 << 1)  /* Transmitter Shift Empty */
#define UART_STAT_TE        (1 << 2)  /* Transmitter FIFO Empty */
#define UART_STAT_BR        (1 << 3)  /* Break Received */
#define UART_STAT_OV        (1 << 4)  /* Overrun Error */
#define UART_STAT_PE        (1 << 5)  /* Parity Error */
#define UART_STAT_FE        (1 << 6)  /* Framing Error */
#define UART_STAT_TH        (1 << 7)  /* Transmitter FIFO Half-full */
#define UART_STAT_RH        (1 << 8)  /* Receiver FIFO Half-full */
#define UART_STAT_TF        (1 << 9)  /* Transmitter FIFO Full */
#define UART_STAT_RF        (1 << 10) /* Receiver FIFO Full */
#define UART_STAT_TCNT_MASK (0x3F << 20)  /* TX FIFO Count */
#define UART_STAT_RCNT_MASK (0x3F << 26)  /* RX FIFO Count */

/* UART Control Register Bits */
#define UART_CTRL_RE        (1 << 0)  /* Receiver Enable */
#define UART_CTRL_TE        (1 << 1)  /* Transmitter Enable */
#define UART_CTRL_RI        (1 << 2)  /* Receiver Interrupt Enable */
#define UART_CTRL_TI        (1 << 3)  /* Transmitter Interrupt Enable */
#define UART_CTRL_PS        (1 << 4)  /* Parity Select (0=even, 1=odd) */
#define UART_CTRL_PE        (1 << 5)  /* Parity Enable */
#define UART_CTRL_FL        (1 << 6)  /* Flow Control Enable */
#define UART_CTRL_LB        (1 << 7)  /* Loopback Enable */
#define UART_CTRL_EC        (1 << 8)  /* External Clock */
#define UART_CTRL_TF        (1 << 9)  /* Transmitter FIFO Interrupt Enable */
#define UART_CTRL_RF        (1 << 10) /* Receiver FIFO Interrupt Enable */
#define UART_CTRL_DB        (1 << 11) /* Debug Enable */
#define UART_CTRL_BI        (1 << 12) /* Break Interrupt Enable */
#define UART_CTRL_DI        (1 << 13) /* Delayed Interrupt Enable */
#define UART_CTRL_FA        (1 << 31) /* FIFO Available */

/*===========================================================================
 * GPIO (General Purpose I/O) - Based on GRLIB GRGPIO
 * Base Address: 0x80000400
 *===========================================================================*/

#define GPIO_BASE           0x80000400

#define GPIO_DATA           (GPIO_BASE + 0x00)  /* Data Register */
#define GPIO_OUTPUT         (GPIO_BASE + 0x04)  /* Output Register */
#define GPIO_DIRECTION      (GPIO_BASE + 0x08)  /* Direction Register */
#define GPIO_IRQ_MASK       (GPIO_BASE + 0x0C)  /* Interrupt Mask */
#define GPIO_IRQ_POLARITY   (GPIO_BASE + 0x10)  /* Interrupt Polarity */
#define GPIO_IRQ_EDGE       (GPIO_BASE + 0x14)  /* Interrupt Edge */
#define GPIO_BYPASS         (GPIO_BASE + 0x18)  /* Bypass Register */
#define GPIO_CAPABILITY     (GPIO_BASE + 0x1C)  /* Capability Register */

/*===========================================================================
 * Memory Controller (MCTRL) - Based on GRLIB MCTRL
 * Base Address: 0x80000000
 *===========================================================================*/

#define MCTRL_BASE          0x80000000

#define MCTRL_CFG1          (MCTRL_BASE + 0x00)  /* Memory Config 1 */
#define MCTRL_CFG2          (MCTRL_BASE + 0x04)  /* Memory Config 2 */
#define MCTRL_CFG3          (MCTRL_BASE + 0x08)  /* Memory Config 3 */

/*===========================================================================
 * Peripheral State Structures
 *===========================================================================*/

/* Timer Unit State */
struct gptimer_unit {
    word_t scaler_counter;    /* Current scaler value */
    word_t scaler_reload;     /* Scaler reload value */
    word_t config;            /* Configuration register */
    
    /* Individual timers */
    struct {
        word_t counter;       /* Counter value */
        word_t reload;        /* Reload value */
        word_t control;       /* Control register */
        word_t latch;         /* Latched counter value */
    } timer[2];
};

/* UART State */
struct uart_unit {
    word_t data;              /* Data register (RX/TX) */
    word_t status;            /* Status register */
    word_t control;           /* Control register */
    word_t scaler;            /* Baud rate scaler */
    
    /* RX FIFO */
    unsigned char rx_fifo[16];
    int rx_head;
    int rx_tail;
    int rx_count;
    
    /* TX FIFO */
    unsigned char tx_fifo[16];
    int tx_head;
    int tx_tail;
    int tx_count;
    
    /* Backend file descriptors */
    int rx_fd;                /* Input source (-1 = stdin) */
    int tx_fd;                /* Output destination (-1 = stdout) */
};

/* GPIO State */
struct gpio_unit {
    word_t data;              /* Input data */
    word_t output;            /* Output data */
    word_t direction;         /* Direction (0=input, 1=output) */
    word_t irq_mask;          /* Interrupt mask */
    word_t irq_polarity;      /* Interrupt polarity */
    word_t irq_edge;          /* Interrupt edge select */
};

/* Complete Peripheral State */
struct peripheral_state {
    struct gptimer_unit timer;
    struct uart_unit uart1;
    struct uart_unit uart2;
    struct gpio_unit gpio;
    int initialized;
};

/*===========================================================================
 * Function Prototypes
 *===========================================================================*/

/* Initialize all peripherals */
void peripheral_init(struct peripheral_state *periph);

/* Reset all peripherals */
void peripheral_reset(struct peripheral_state *periph);

/* MMIO Read/Write Functions */
word_t mmio_read(struct peripheral_state *periph, md_addr_t addr, int size);
void mmio_write(struct peripheral_state *periph, md_addr_t addr, word_t value, int size);

/* Timer Functions */
void timer_init(struct gptimer_unit *timer);
void timer_tick(struct gptimer_unit *timer, int cycles);
word_t timer_read(struct gptimer_unit *timer, md_addr_t addr);
void timer_write(struct gptimer_unit *timer, md_addr_t addr, word_t value);

/* UART Functions */
void uart_init(struct uart_unit *uart, int rx_fd, int tx_fd);
void uart_tick(struct uart_unit *uart);
word_t uart_read(struct uart_unit *uart, md_addr_t offset);
void uart_write(struct uart_unit *uart, md_addr_t offset, word_t value);
int uart_rx_ready(struct uart_unit *uart);
int uart_tx_ready(struct uart_unit *uart);

/* GPIO Functions */
void gpio_init(struct gpio_unit *gpio);
word_t gpio_read(struct gpio_unit *gpio, md_addr_t addr);
void gpio_write(struct gpio_unit *gpio, md_addr_t addr, word_t value);

#endif /* PERIPHERALS_H */