peripherals.c

/* peripherals.c - LEON3/UT699 Memory-Mapped I/O Peripheral Implementation */

/*
 * SPARC V8 UT699/LEON3FT Simulator - Peripheral Emulation
 * 
 * This file implements memory-mapped I/O (MMIO) access to UT699/LEON3
 * peripherals including Timer, UART, and GPIO units.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include <errno.h>

#include "host.h"
#include "misc.h"
#include "machine.h"
#include "peripherals.h"

/* Enable debug output */
#ifndef PERIPH_DEBUG
#define PERIPH_DEBUG 0
#endif

#if PERIPH_DEBUG
#define DPRINTF(fmt, ...) fprintf(stderr, "PERIPH: " fmt, ##__VA_ARGS__)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#endif

/*===========================================================================
 * Peripheral Initialization
 *===========================================================================*/

void peripheral_init(struct peripheral_state *periph)
{
    memset(periph, 0, sizeof(*periph));
    
    timer_init(&periph->timer);
    uart_init(&periph->uart1, -1, -1);  /* Use stdin/stdout */
    uart_init(&periph->uart2, -1, -1);
    gpio_init(&periph->gpio);
    
    periph->initialized = 1;
    
    DPRINTF("Peripherals initialized\n");
}

void peripheral_reset(struct peripheral_state *periph)
{
    timer_init(&periph->timer);
    
    /* Reset UARTs but preserve file descriptors */
    int rx1 = periph->uart1.rx_fd, tx1 = periph->uart1.tx_fd;
    int rx2 = periph->uart2.rx_fd, tx2 = periph->uart2.tx_fd;
    uart_init(&periph->uart1, rx1, tx1);
    uart_init(&periph->uart2, rx2, tx2);
    
    gpio_init(&periph->gpio);
    
    DPRINTF("Peripherals reset\n");
}

/*===========================================================================
 * MMIO Dispatch
 *===========================================================================*/

word_t mmio_read(struct peripheral_state *periph, md_addr_t addr, int size)
{
    word_t value = 0;
    
    /* Timer Unit: 0x80000300 - 0x8000033F */
    if (addr >= TIMER_BASE && addr < TIMER_BASE + 0x40) {
        value = timer_read(&periph->timer, addr);
        DPRINTF("TIMER READ: addr=0x%08x size=%d value=0x%08x\n", 
                (unsigned)addr, size, (unsigned)value);
    }
    /* UART 1: 0x80000100 - 0x8000011F */
    else if (addr >= UART1_BASE && addr < UART1_BASE + 0x20) {
        value = uart_read(&periph->uart1, addr - UART1_BASE);
        DPRINTF("UART1 READ: addr=0x%08x offset=0x%02x value=0x%08x\n", 
                (unsigned)addr, (unsigned)(addr - UART1_BASE), (unsigned)value);
    }
    /* UART 2: 0x80100100 - 0x8010011F */
    else if (addr >= UART2_BASE && addr < UART2_BASE + 0x20) {
        value = uart_read(&periph->uart2, addr - UART2_BASE);
        DPRINTF("UART2 READ: addr=0x%08x offset=0x%02x value=0x%08x\n", 
                (unsigned)addr, (unsigned)(addr - UART2_BASE), (unsigned)value);
    }
    /* GPIO: 0x80000400 - 0x8000041F */
    else if (addr >= GPIO_BASE && addr < GPIO_BASE + 0x20) {
        value = gpio_read(&periph->gpio, addr);
        DPRINTF("GPIO READ: addr=0x%08x value=0x%08x\n", 
                (unsigned)addr, (unsigned)value);
    }
    /* Interrupt Controller: 0x80000200 - 0x800002FF */
    else if (addr >= IRQ_BASE && addr < IRQ_BASE + 0x100) {
        /* Interrupt controller is handled separately in interrupt.c */
        DPRINTF("IRQ READ: addr=0x%08x (handled by interrupt controller)\n", 
                (unsigned)addr);
        value = 0;
    }
    /* Memory Controller: 0x80000000 - 0x800000FF */
    else if (addr >= MCTRL_BASE && addr < MCTRL_BASE + 0x100) {
        /* Return default memory config */
        DPRINTF("MCTRL READ: addr=0x%08x returning 0\n", (unsigned)addr);
        value = 0;
    }
    else {
        /* Unknown MMIO region - return 0 */
        DPRINTF("MMIO READ: unknown addr=0x%08x returning 0\n", (unsigned)addr);
        value = 0;
    }
    
    return value;
}

void mmio_write(struct peripheral_state *periph, md_addr_t addr, word_t value, int size)
{
    /* Timer Unit: 0x80000300 - 0x8000033F */
    if (addr >= TIMER_BASE && addr < TIMER_BASE + 0x40) {
        DPRINTF("TIMER WRITE: addr=0x%08x size=%d value=0x%08x\n", 
                (unsigned)addr, size, (unsigned)value);
        timer_write(&periph->timer, addr, value);
    }
    /* UART 1: 0x80000100 - 0x8000011F */
    else if (addr >= UART1_BASE && addr < UART1_BASE + 0x20) {
        DPRINTF("UART1 WRITE: addr=0x%08x offset=0x%02x value=0x%08x\n", 
                (unsigned)addr, (unsigned)(addr - UART1_BASE), (unsigned)value);
        uart_write(&periph->uart1, addr - UART1_BASE, value);
    }
    /* UART 2: 0x80100100 - 0x8010011F */
    else if (addr >= UART2_BASE && addr < UART2_BASE + 0x20) {
        DPRINTF("UART2 WRITE: addr=0x%08x offset=0x%02x value=0x%08x\n", 
                (unsigned)addr, (unsigned)(addr - UART2_BASE), (unsigned)value);
        uart_write(&periph->uart2, addr - UART2_BASE, value);
    }
    /* GPIO: 0x80000400 - 0x8000041F */
    else if (addr >= GPIO_BASE && addr < GPIO_BASE + 0x20) {
        DPRINTF("GPIO WRITE: addr=0x%08x value=0x%08x\n", 
                (unsigned)addr, (unsigned)value);
        gpio_write(&periph->gpio, addr, value);
    }
    /* Interrupt Controller: 0x80000200 - 0x800002FF */
    else if (addr >= IRQ_BASE && addr < IRQ_BASE + 0x100) {
        /* Interrupt controller is handled separately in interrupt.c */
        DPRINTF("IRQ WRITE: addr=0x%08x value=0x%08x (handled by interrupt controller)\n", 
                (unsigned)addr, (unsigned)value);
    }
    /* Memory Controller: 0x80000000 - 0x800000FF */
    else if (addr >= MCTRL_BASE && addr < MCTRL_BASE + 0x100) {
        DPRINTF("MCTRL WRITE: addr=0x%08x value=0x%08x (ignored)\n", 
                (unsigned)addr, (unsigned)value);
    }
    else {
        DPRINTF("MMIO WRITE: unknown addr=0x%08x value=0x%08x (ignored)\n", 
                (unsigned)addr, (unsigned)value);
    }
}

/*===========================================================================
 * Timer Implementation
 *===========================================================================*/

void timer_init(struct gptimer_unit *timer)
{
    memset(timer, 0, sizeof(*timer));
    
    /* Set default configuration: 2 timers, IRQ 8 */
    timer->config = 2 | (IRQ_LEVEL_TIMER1 << 3);
    
    /* Default scaler reload (typical: system_clock / 1000000 for 1us tick) */
    timer->scaler_reload = 39;  /* Assuming 40 MHz clock */
    timer->scaler_counter = timer->scaler_reload;
}

void timer_tick(struct gptimer_unit *timer, int cycles)
{
    int i;
    
    /* Process scaler first */
    while (cycles > 0) {
        if (timer->scaler_counter == 0) {
            timer->scaler_counter = timer->scaler_reload;
            
            /* Tick each enabled timer */
            for (i = 0; i < 2; i++) {
                if (!(timer->timer[i].control & TIMER_CTRL_EN))
                    continue;
                
                /* Chain mode - only tick if chained timer underflowed */
                if ((timer->timer[i].control & TIMER_CTRL_CH) && i > 0) {
                    if (!(timer->timer[i-1].control & TIMER_CTRL_IP))
                        continue;
                }
                
                if (timer->timer[i].counter == 0) {
                    /* Underflow */
                    timer->timer[i].control |= TIMER_CTRL_IP;
                    
                    if (timer->timer[i].control & TIMER_CTRL_RS) {
                        /* Restart mode - reload counter */
                        timer->timer[i].counter = timer->timer[i].reload;
                    } else {
                        /* One-shot mode - disable timer */
                        timer->timer[i].control &= ~TIMER_CTRL_EN;
                    }
                    
                    /* TODO: Generate interrupt if IE set */
                    if (timer->timer[i].control & TIMER_CTRL_IE) {
                        DPRINTF("Timer %d interrupt pending\n", i);
                    }
                } else {
                    timer->timer[i].counter--;
                }
            }
        } else {
            timer->scaler_counter--;
        }
        cycles--;
    }
}

word_t timer_read(struct gptimer_unit *timer, md_addr_t addr)
{
    switch (addr) {
    case TIMER_SCALER_CNT:
        return timer->scaler_counter;
    case TIMER_SCALER_RLD:
        return timer->scaler_reload;
    case TIMER_CONFIG:
        return timer->config;
        
    case TIMER1_COUNTER:
        return timer->timer[0].counter;
    case TIMER1_RELOAD:
        return timer->timer[0].reload;
    case TIMER1_CONTROL:
        return timer->timer[0].control;
    case TIMER1_LATCH:
        return timer->timer[0].latch;
        
    case TIMER2_COUNTER:
        return timer->timer[1].counter;
    case TIMER2_RELOAD:
        return timer->timer[1].reload;
    case TIMER2_CONTROL:
        return timer->timer[1].control;
    case TIMER2_LATCH:
        return timer->timer[1].latch;
        
    default:
        return 0;
    }
}

void timer_write(struct gptimer_unit *timer, md_addr_t addr, word_t value)
{
    switch (addr) {
    case TIMER_SCALER_CNT:
        timer->scaler_counter = value;
        break;
    case TIMER_SCALER_RLD:
        timer->scaler_reload = value;
        break;
    case TIMER_CONFIG:
        /* Config register is mostly read-only, some bits writable */
        timer->config = (timer->config & 0xFF) | (value & ~0xFF);
        break;
        
    case TIMER1_COUNTER:
        timer->timer[0].counter = value;
        break;
    case TIMER1_RELOAD:
        timer->timer[0].reload = value;
        break;
    case TIMER1_CONTROL:
        /* Handle load bit */
        if (value & TIMER_CTRL_LD) {
            timer->timer[0].counter = timer->timer[0].reload;
            value &= ~TIMER_CTRL_LD;  /* LD is write-only */
        }
        /* Clear interrupt pending if writing 0 to IP */
        if (!(value & TIMER_CTRL_IP)) {
            timer->timer[0].control &= ~TIMER_CTRL_IP;
        }
        timer->timer[0].control = (value & ~TIMER_CTRL_IP) | 
                                   (timer->timer[0].control & TIMER_CTRL_IP);
        break;
    case TIMER1_LATCH:
        /* Latching counter value */
        timer->timer[0].latch = timer->timer[0].counter;
        break;
        
    case TIMER2_COUNTER:
        timer->timer[1].counter = value;
        break;
    case TIMER2_RELOAD:
        timer->timer[1].reload = value;
        break;
    case TIMER2_CONTROL:
        if (value & TIMER_CTRL_LD) {
            timer->timer[1].counter = timer->timer[1].reload;
            value &= ~TIMER_CTRL_LD;
        }
        if (!(value & TIMER_CTRL_IP)) {
            timer->timer[1].control &= ~TIMER_CTRL_IP;
        }
        timer->timer[1].control = (value & ~TIMER_CTRL_IP) | 
                                   (timer->timer[1].control & TIMER_CTRL_IP);
        break;
    case TIMER2_LATCH:
        timer->timer[1].latch = timer->timer[1].counter;
        break;
    }
}

/*===========================================================================
 * UART Implementation
 *===========================================================================*/

void uart_init(struct uart_unit *uart, int rx_fd, int tx_fd)
{
    memset(uart, 0, sizeof(*uart));
    
    /* Set default status: transmitter empty */
    uart->status = UART_STAT_TE | UART_STAT_TS;
    
    /* Default scaler for 115200 baud at 40 MHz */
    uart->scaler = 21;  /* (40000000 / (115200 * 8)) - 1 */
    
    /* Set file descriptors */
    uart->rx_fd = rx_fd;
    uart->tx_fd = tx_fd;
    
    /* Set stdin to non-blocking if using for RX */
    if (rx_fd == -1) {
        int flags = fcntl(STDIN_FILENO, F_GETFL, 0);
        if (flags != -1) {
            fcntl(STDIN_FILENO, F_SETFL, flags | O_NONBLOCK);
        }
    }
}

void uart_tick(struct uart_unit *uart)
{
    /* Check for incoming data on RX */
    if (uart->control & UART_CTRL_RE) {
        if (uart->rx_count < 16) {
            int fd = (uart->rx_fd == -1) ? STDIN_FILENO : uart->rx_fd;
            unsigned char ch;
            ssize_t n = read(fd, &ch, 1);
            
            if (n > 0) {
                uart->rx_fifo[uart->rx_tail] = ch;
                uart->rx_tail = (uart->rx_tail + 1) & 15;
                uart->rx_count++;
                uart->status |= UART_STAT_DR;
                
                if (uart->rx_count >= 8) {
                    uart->status |= UART_STAT_RH;
                }
                if (uart->rx_count >= 16) {
                    uart->status |= UART_STAT_RF;
                }
                
                DPRINTF("UART RX: received byte 0x%02x '%c'\n", 
                        ch, (ch >= 32 && ch < 127) ? ch : '.');
            }
        }
    }
    
    /* Process TX FIFO */
    if ((uart->control & UART_CTRL_TE) && uart->tx_count > 0) {
        int fd = (uart->tx_fd == -1) ? STDOUT_FILENO : uart->tx_fd;
        unsigned char ch = uart->tx_fifo[uart->tx_head];
        
        if (write(fd, &ch, 1) > 0) {
            uart->tx_head = (uart->tx_head + 1) & 15;
            uart->tx_count--;
            
            DPRINTF("UART TX: sent byte 0x%02x '%c'\n", 
                    ch, (ch >= 32 && ch < 127) ? ch : '.');
            
            if (uart->tx_count == 0) {
                uart->status |= UART_STAT_TE | UART_STAT_TS;
            } else if (uart->tx_count < 8) {
                uart->status &= ~UART_STAT_TH;
            }
        }
    }
}

word_t uart_read(struct uart_unit *uart, md_addr_t offset)
{
    switch (offset) {
    case UART_DATA_OFF:
        /* Read from RX FIFO */
        if (uart->rx_count > 0) {
            word_t data = uart->rx_fifo[uart->rx_head];
            uart->rx_head = (uart->rx_head + 1) & 15;
            uart->rx_count--;
            
            if (uart->rx_count == 0) {
                uart->status &= ~UART_STAT_DR;
            }
            uart->status &= ~(UART_STAT_RH | UART_STAT_RF);
            if (uart->rx_count >= 8) {
                uart->status |= UART_STAT_RH;
            }
            
            DPRINTF("UART DATA READ: 0x%02x\n", (unsigned)data);
            return data;
        }
        return 0;
        
    case UART_STATUS_OFF:
        return uart->status;
        
    case UART_CONTROL_OFF:
        return uart->control;
        
    case UART_SCALER_OFF:
        return uart->scaler;
        
    case UART_FIFO_DBG_OFF:
        /* Return FIFO counts */
        return (uart->rx_count << 26) | (uart->tx_count << 20);
        
    default:
        return 0;
    }
}

void uart_write(struct uart_unit *uart, md_addr_t offset, word_t value)
{
    switch (offset) {
    case UART_DATA_OFF:
        /* Write to TX FIFO */
        if (uart->tx_count < 16) {
            uart->tx_fifo[uart->tx_tail] = value & 0xFF;
            uart->tx_tail = (uart->tx_tail + 1) & 15;
            uart->tx_count++;
            
            uart->status &= ~(UART_STAT_TE | UART_STAT_TS);
            if (uart->tx_count >= 8) {
                uart->status |= UART_STAT_TH;
            }
            if (uart->tx_count >= 16) {
                uart->status |= UART_STAT_TF;
            }
            
            DPRINTF("UART DATA WRITE: 0x%02x '%c'\n", 
                    (unsigned)(value & 0xFF),
                    ((value & 0xFF) >= 32 && (value & 0xFF) < 127) ? (char)(value & 0xFF) : '.');
            
            /* Immediately try to send if transmitter enabled */
            if (uart->control & UART_CTRL_TE) {
                uart_tick(uart);
            }
        } else {
            uart->status |= UART_STAT_OV;  /* Overrun */
        }
        break;
        
    case UART_STATUS_OFF:
        /* Status register is mostly read-only, but some bits can be cleared */
        uart->status &= ~(value & (UART_STAT_BR | UART_STAT_OV | 
                                   UART_STAT_PE | UART_STAT_FE));
        break;
        
    case UART_CONTROL_OFF:
        uart->control = value;
        break;
        
    case UART_SCALER_OFF:
        uart->scaler = value & 0xFFF;  /* 12-bit scaler */
        break;
    }
}

int uart_rx_ready(struct uart_unit *uart)
{
    return uart->rx_count > 0;
}

int uart_tx_ready(struct uart_unit *uart)
{
    return uart->tx_count < 16;
}

/*===========================================================================
 * GPIO Implementation
 *===========================================================================*/

void gpio_init(struct gpio_unit *gpio)
{
    memset(gpio, 0, sizeof(*gpio));
}

word_t gpio_read(struct gpio_unit *gpio, md_addr_t addr)
{
    switch (addr) {
    case GPIO_DATA:
        /* Return input data (masked by direction) OR output data */
        return (gpio->data & ~gpio->direction) | (gpio->output & gpio->direction);
        
    case GPIO_OUTPUT:
        return gpio->output;
        
    case GPIO_DIRECTION:
        return gpio->direction;
        
    case GPIO_IRQ_MASK:
        return gpio->irq_mask;
        
    case GPIO_IRQ_POLARITY:
        return gpio->irq_polarity;
        
    case GPIO_IRQ_EDGE:
        return gpio->irq_edge;
        
    case GPIO_CAPABILITY:
        /* Return capabilities: 32 GPIO lines, interrupt support */
        return 0x0000001F;  /* 32 lines, IRQ capable */
        
    default:
        return 0;
    }
}

void gpio_write(struct gpio_unit *gpio, md_addr_t addr, word_t value)
{
    switch (addr) {
    case GPIO_DATA:
        /* Writing to data register sets input simulation value */
        gpio->data = value;
        break;
        
    case GPIO_OUTPUT:
        gpio->output = value;
        break;
        
    case GPIO_DIRECTION:
        gpio->direction = value;
        break;
        
    case GPIO_IRQ_MASK:
        gpio->irq_mask = value;
        break;
        
    case GPIO_IRQ_POLARITY:
        gpio->irq_polarity = value;
        break;
        
    case GPIO_IRQ_EDGE:
        gpio->irq_edge = value;
        break;
    }
}