Feasibility check on NPU

[kamalasubha]

Hi,
I tried running the repository and observed that the configuration testing is only for TPUs in examples. Will it work for other NPU architectures like AMD XDNA etc? Kindly let me know.

[XZman]

Thanks for your interest in NeuSim!

We currently do not explicitly target AMD XDNA architecture out of the box, but you can configure the simulator to approximate the XDNA architecture by configuring the ICI as a 2D mesh to emulate XDNA's on-chip network, and the vector unit/SRAM setting to match each compute tile in XDNA. There are two main caveats:

1. NeuSim assumes that systolic arrays (SA) are present, but the AI Engine in XDNA only uses vector units. We recommend configuring num_sa, num_vu, and sa_dim such that the combined throughput (total FLOPS or number of PEs) of the SA and VU models matches the performance of an XDNA compute tile. This allows you to create an "equivalent" compute unit that mimics the AI Engine's capabilities.
2. We currently do not model the "memory tile" specific to the XDNA architecture. However, if it is ok to assume the memory tiles are used as an aggregated "last-level cache" for all compute tiles, you can approximate their effect by flattening the local scratchpad in each compute tile and the aggregated memory tiles: (a) set the vmem_size_MB to be the total on-chip SRAM size divided by the number of compute tiles (assuming the tensor partitioning is even across all compute tiles); (b) adjust num_vu_ports so that the effective "vmem_bw_GBps" (see neusim.configs.chips.ChipConfig) reflects the aggregated SRAM bandwidth you want to model for the XDNA architecture.

We hope this helps you get started with modeling XDNA on NeuSim! We welcome any contributions if you decide to implement more specific support for the XDNA architecture.