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usb: Handle CRC errors on control OUT.
1 parent 7d5d341 commit d096575

3 files changed

Lines changed: 17 additions & 28 deletions

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deps/luna

Submodule luna updated 53 files

orbtrace/dfu.py

Lines changed: 1 addition & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -61,22 +61,11 @@ def handle_dnload(self, m):
6161

6262
last_addr = Signal(24)
6363

64-
#endpoint_number_matches = (tokenizer.endpoint == self._endpoint_number)
65-
#targeting_endpoint = endpoint_number_matches & tokenizer.is_out
66-
#okay_to_receive = targeting_endpoint & expected_pid_match & ~overflow
67-
#targeting_endpoint = endpoint_number_matches & tokenizer.is_out
68-
#expected_pid_match = (interface.rx_pid_toggle == expected_data_toggle)
69-
7064
m.d.comb += [
7165
fifo.write_data.eq(rx.payload),
72-
#fifo.write_en.eq(okay_to_receive & rx.next & rx.valid),
7366
fifo.write_en.eq(rx.next & rx.valid),
7467

75-
# We'll keep data if our packet finishes with a valid CRC and no overflow; and discard it otherwise.
76-
#fifo.write_commit .eq(targeting_endpoint & boundary_detector.complete_out & ~overflow),
77-
#fifo.write_discard .eq(targeting_endpoint & (boundary_detector.invalid_out | (boundary_detector.complete_out & overflow))),
78-
#fifo.write_commit.eq(interface.rx_complete),
79-
#fifo.write_discard.eq(interface.rx_invalid),
68+
fifo.write_discard.eq(interface.rx_invalid),
8069
fifo.write_commit.eq(interface.rx_ready_for_response),
8170

8271
self.source.data.eq(fifo.read_data),

orbtrace/usb_mem_bridge.py

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -16,14 +16,15 @@ def handle_write(self, m, address):
1616
w = self.axi_lite.w
1717
b = self.axi_lite.b
1818

19+
data = Array(Signal(8) for i in range(4))
20+
idx = Signal(range(5))
21+
1922
m.d.comb += [
2023
w.strb.eq(0b1111),
24+
w.data.eq(Cat(data)),
2125
b.ready.eq(1),
2226
]
2327

24-
data = Array(Signal(8) for i in range(3))
25-
idx = Signal(range(4))
26-
2728
with m.FSM(domain = 'usb') as fsm:
2829

2930
with m.State('IDLE'):
@@ -39,26 +40,25 @@ def handle_write(self, m, address):
3940
m.next = 'RECEIVE'
4041

4142
with m.State('RECEIVE'):
42-
with m.If(self.interface.rx.valid & self.interface.rx.next):
43-
with m.If(idx < 3):
44-
m.d.usb += [
45-
data[idx].eq(self.interface.rx.payload),
46-
idx.eq(idx + 1),
47-
]
43+
with m.If(self.interface.rx.valid & self.interface.rx.next & (idx < 4)):
44+
m.d.usb += [
45+
data[idx].eq(self.interface.rx.payload),
46+
idx.eq(idx + 1),
47+
]
48+
49+
with m.If(self.interface.rx_ready_for_response):
50+
m.d.comb += self.interface.handshakes_out.ack.eq(1)
51+
m.next = 'WRITE'
4852

49-
with m.Else():
50-
m.d.usb += w.data.eq(Cat(data, self.interface.rx.payload))
51-
m.next = 'WRITE'
53+
with m.If(self.interface.rx_invalid):
54+
m.d.usb += idx.eq(0)
5255

5356
with m.State('WRITE'):
5457
m.d.comb += w.valid.eq(1)
5558

5659
with m.If(w.ready):
5760
m.next = 'IDLE'
5861

59-
with m.If(self.interface.rx_ready_for_response):
60-
m.d.comb += self.interface.handshakes_out.ack.eq(1)
61-
6262
with m.If(self.interface.status_requested):
6363
m.d.comb += self.send_zlp()
6464

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