@@ -1715,6 +1715,8 @@ bool Matcher::match_rule_supported(int opcode) {
17151715 switch (opcode) {
17161716 case Op_ReverseBytesI:
17171717 case Op_ReverseBytesL:
1718+ case Op_ReverseBytesS:
1719+ case Op_ReverseBytesUS:
17181720 return UseByteReverseInstruction;
17191721 case Op_PopCountI:
17201722 case Op_PopCountL:
@@ -11615,6 +11617,38 @@ instruct vround2D_reg(vecX dst, vecX src, immI8 rmode) %{
1161511617
1161611618// Byte reverse
1161711619
11620+ instruct bytes_reverse_short(iRegI dst, iRegI src) %{
11621+ match(Set dst (ReverseBytesS src));
11622+ predicate(UseByteReverseInstruction);
11623+ ins_cost(2 * DEFAULT_COST);
11624+ size(8);
11625+
11626+ format %{ "LRVR $dst, $src\n\t # byte reverse int"
11627+ "SRA $dst, 0x0010\t # right shift by 16, sign extended" %}
11628+
11629+ ins_encode %{
11630+ __ z_lrvr($dst$$Register, $src$$Register);
11631+ __ z_sra($dst$$Register, 0x0010);
11632+ %}
11633+ ins_pipe(pipe_class_dummy);
11634+ %}
11635+
11636+ instruct bytes_reverse_unsigned_short(iRegI dst, iRegI src) %{
11637+ match(Set dst (ReverseBytesUS src));
11638+ predicate(UseByteReverseInstruction);
11639+ ins_cost(2 * DEFAULT_COST);
11640+ size(8);
11641+
11642+ format %{ "LRVR $dst, $src\n\t # byte reverse int"
11643+ "SRL $dst, 0x0010\t # right shift by 16, zero extended" %}
11644+
11645+ ins_encode %{
11646+ __ z_lrvr($dst$$Register, $src$$Register);
11647+ __ z_srl($dst$$Register, 0x0010);
11648+ %}
11649+ ins_pipe(pipe_class_dummy);
11650+ %}
11651+
1161811652instruct bytes_reverse_int(iRegI dst, iRegI src) %{
1161911653 match(Set dst (ReverseBytesI src));
1162011654 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
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