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<section id="open-nvdla-repository-updates">
<span id="updates"></span><h1>Open NVDLA Repository Updates<a class="headerlink" href="#open-nvdla-repository-updates" title="Link to this heading">¶</a></h1>
<p>This document is a quick reference guide to changes in the NVDLA repository. Most recent updates are at the top of the document. Detailed information can be obtained from the <code class="docutils literal notranslate"><span class="pre">git</span></code> list of commits.</p>
<section id="id1">
<h2>5/15/2018<a class="headerlink" href="#id1" title="Link to this heading">¶</a></h2>
<p>Release NVDLA Virtual platform on Amazon Web Services (AWS) FPGA which supports HW regression and SW tests. See <a class="reference internal" href="vp_fpga.html"><span class="doc">Virtual Platform On AWS FPGA</span></a> section. Support “nv_small” configuration.</p>
</section>
<section id="id2">
<h2>4/19/2018<a class="headerlink" href="#id2" title="Link to this heading">¶</a></h2>
<p>First release of NVDLA V2 – the configurable NVDLA. This release also includes
a new testbench which can be used to validate the design. However,
the only tested configuration is the “nv_small” configuration. See
the <a class="reference internal" href="hw/v2/scalability.html"><span class="doc">Scalability parameters and ConfigROM</span></a> document for details on the nv_small
design configuration parameters. While the nv_small config passes many
tests, coverage isn’t yet to tapeout quality levels.</p>
</section>
<section id="id3">
<h2>12/1/2017<a class="headerlink" href="#id3" title="Link to this heading">¶</a></h2>
<p>Released a SystemC model of the NVDLA hardware, suitable for simulation and
verification. This SystemC model lives in <code class="docutils literal notranslate"><span class="pre">cmod/</span></code>, and information on
building it is in the <a class="reference internal" href="hw/v1/integration_guide.html#tree-build"><span class="std std-ref">Tree Build</span></a> section.</p>
<p>Additionally, this release contains experiemental support for building the
NVDLA RTL using Verilator; for more information on this, see the
<a class="reference internal" href="hw/v1/integration_guide.html#verilator-testbench"><span class="std std-ref">Verilator Testbench</span></a> section.</p>
</section>
<section id="id4">
<h2>11/21/2017<a class="headerlink" href="#id4" title="Link to this heading">¶</a></h2>
<p>A few updates in the nvdla hardware tree, most notably moving further
development on the non-configurable NVDLA implementation to its own stable
branch, <code class="docutils literal notranslate"><span class="pre">nvdlav1</span></code>, and renaming the full-precision non-configurable
implementation to <code class="docutils literal notranslate"><span class="pre">nv_full</span></code>. The <code class="docutils literal notranslate"><span class="pre">master</span></code> branch, from now on, will
contain potentially-destabilizing ongoing effort for a configurable NVDLA.
Note that the default branch has changed, and users may wish to modify which
upstream branch they are tracking.</p>
<p>This release includes bugfixes for Xilinx Vivado and Mentor Questa simulators.</p>
</section>
<section id="id5">
<h2>11/1/2017<a class="headerlink" href="#id5" title="Link to this heading">¶</a></h2>
<p>First drop of RTL build system to be used for creating multiple NVDLA configurations. The
configurations themselves will be checked in as features become available. All configuration
parameters to create a small config NVDLA with 64 MACs is expected before the end 2017.</p>
</section>
<section id="id6">
<h2>10/24/2017<a class="headerlink" href="#id6" title="Link to this heading">¶</a></h2>
<p>Initial release of the NVDLA Kernel Mode Driver (KMD) for Linux.</p>
</section>
<section id="id7">
<h2>10/18/2017<a class="headerlink" href="#id7" title="Link to this heading">¶</a></h2>
<p>The traceplayer testbench has been updated to split the memory model into two logically separate region. Support was added to the axi_slave and memory model for non-zero burst lengths which is used by the cvsram interface. Added cvsram form of sanity tests. Added sdp and pdp sanity tests. Added googlenet_conv2_3x3_int16 and cc_alexnet_conv5_relu5_int16_dtest_cvsram layer tests.</p>
<p>Changes to address issues #16, #23, #24 on the NVDLA GitHub site.</p>
</section>
<section id="id8">
<h2>10/6/2017<a class="headerlink" href="#id8" title="Link to this heading">¶</a></h2>
<p>The large configuration RTL is updated to a 64-bit address bus on the DBBIF and RAMIF busses. The previous design was 32-bit externally and 40-bit internally. This reflects the final size for the large configuration.</p>
<p>Changes to address issues #6, #7, #9 on the NVDLA GitHub site.</p>
</section>
<section id="id9">
<h2>9/25/2017<a class="headerlink" href="#id9" title="Link to this heading">¶</a></h2>
<p>Initial release of large configuration RTL, trace player testbench, synthesis scripts, performance model spreadsheet, and documentation.</p>
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<li><a class="reference internal" href="#">Open NVDLA Repository Updates</a><ul>
<li><a class="reference internal" href="#id1">5/15/2018</a></li>
<li><a class="reference internal" href="#id2">4/19/2018</a></li>
<li><a class="reference internal" href="#id3">12/1/2017</a></li>
<li><a class="reference internal" href="#id4">11/21/2017</a></li>
<li><a class="reference internal" href="#id5">11/1/2017</a></li>
<li><a class="reference internal" href="#id6">10/24/2017</a></li>
<li><a class="reference internal" href="#id7">10/18/2017</a></li>
<li><a class="reference internal" href="#id8">10/6/2017</a></li>
<li><a class="reference internal" href="#id9">9/25/2017</a></li>
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