Currently the sdram_dqmh and sdram_dqml signals are hard-wired to zero. I assume that these two signals can be used for implementing "byte select" during write operations.
For my application (a custom soft CPU with 8/16/32-bit word writing capabilities), byte select functionality in the SDRAM controller would simplify the interface significantly (otherwise I'd need to do a full 32-bit read-modify-write cycle to support writing of individual bytes, for instance).
Would it be hard to implement?
Currently the
sdram_dqmhandsdram_dqmlsignals are hard-wired to zero. I assume that these two signals can be used for implementing "byte select" during write operations.For my application (a custom soft CPU with 8/16/32-bit word writing capabilities), byte select functionality in the SDRAM controller would simplify the interface significantly (otherwise I'd need to do a full 32-bit read-modify-write cycle to support writing of individual bytes, for instance).
Would it be hard to implement?