From f9ff4ed54e2cc399eee431a29294337da30d135d Mon Sep 17 00:00:00 2001 From: "renovate[bot]" <29139614+renovate[bot]@users.noreply.github.com> Date: Mon, 6 Jul 2026 11:01:22 +0000 Subject: [PATCH] Update module github.com/klauspost/cpuid/v2 to v2.4.0 Signed-off-by: renovate[bot] <29139614+renovate[bot]@users.noreply.github.com> --- go.mod | 2 +- go.sum | 5 +- go.work.sum | 1 + .../klauspost/cpuid/v2/.goreleaser.yml | 25 +- .../github.com/klauspost/cpuid/v2/README.md | 99 +- vendor/github.com/klauspost/cpuid/v2/cpuid.go | 873 +++++++++++++----- .../klauspost/cpuid/v2/cpuid_arm64.s | 10 + .../klauspost/cpuid/v2/detect_arm64.go | 26 +- .../klauspost/cpuid/v2/detect_ref.go | 5 +- .../klauspost/cpuid/v2/detect_ref_arm64.go | 19 + .../klauspost/cpuid/v2/detect_riscv64.go | 16 + .../klauspost/cpuid/v2/detect_x86.go | 10 +- .../klauspost/cpuid/v2/featureid_string.go | 516 ++++++----- .../klauspost/cpuid/v2/os_darwin_arm64.go | 87 +- .../klauspost/cpuid/v2/os_linux_arm64.go | 160 +++- .../klauspost/cpuid/v2/os_linux_riscv64.go | 225 +++++ .../klauspost/cpuid/v2/os_other_arm64.go | 1 - .../klauspost/cpuid/v2/os_other_riscv64.go | 14 + .../klauspost/cpuid/v2/os_safe_linux_arm64.go | 1 - .../cpuid/v2/os_unsafe_linux_arm64.go | 1 - .../klauspost/cpuid/v2/riscv_isa.go | 93 ++ vendor/modules.txt | 4 +- 22 files changed, 1656 insertions(+), 537 deletions(-) create mode 100644 vendor/github.com/klauspost/cpuid/v2/detect_ref_arm64.go create mode 100644 vendor/github.com/klauspost/cpuid/v2/detect_riscv64.go create mode 100644 vendor/github.com/klauspost/cpuid/v2/os_linux_riscv64.go create mode 100644 vendor/github.com/klauspost/cpuid/v2/os_other_riscv64.go create mode 100644 vendor/github.com/klauspost/cpuid/v2/riscv_isa.go diff --git a/go.mod b/go.mod index 810b83a30..ecd9db28c 100644 --- a/go.mod +++ b/go.mod @@ -11,7 +11,7 @@ require ( github.com/golang/protobuf v1.5.4 github.com/google/go-cmp v0.7.0 github.com/google/uuid v1.6.0 - github.com/klauspost/cpuid/v2 v2.2.5 + github.com/klauspost/cpuid/v2 v2.4.0 github.com/mitchellh/mapstructure v1.5.0 github.com/nginxinc/nginx-prometheus-exporter v1.2.0 github.com/nxadm/tail v1.4.11 diff --git a/go.sum b/go.sum index bf44f5a18..ab5749a4b 100644 --- a/go.sum +++ b/go.sum @@ -61,8 +61,8 @@ github.com/jstemmer/go-junit-report v1.0.0 h1:8X1gzZpR+nVQLAht+L/foqOeX2l9DTZoaI github.com/jstemmer/go-junit-report v1.0.0/go.mod h1:Brl9GWCQeLvo8nXZwPNNblvFj/XSXhF0NWZEnDohbsk= github.com/kisielk/errcheck v1.5.0/go.mod h1:pFxgyoBC7bSaBwPgfKdkLd5X25qrDl4LWUI2bnpBCr8= github.com/kisielk/gotool v1.0.0/go.mod h1:XhKaO+MFFWcvkIS/tQcRk01m1F5IRFswLeQ+oQHNcck= -github.com/klauspost/cpuid/v2 v2.2.5 h1:0E5MSMDEoAulmXNFquVs//DdoomxaoTY1kUhbc/qbZg= -github.com/klauspost/cpuid/v2 v2.2.5/go.mod h1:Lcz8mBdAVJIBVzewtcLocK12l3Y+JytZYpaMropDUws= +github.com/klauspost/cpuid/v2 v2.4.0 h1:S6Hrbc7+ywsr0r+RLapfGBHfyefhCTwEh3A0tV913Dw= +github.com/klauspost/cpuid/v2 v2.4.0/go.mod h1:19jmZ9mjzoF//ddRSUsv0zfBTJWh3QJh9FNxZTMrGxU= github.com/konsorten/go-windows-terminal-sequences v1.0.1/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ= github.com/kr/pretty v0.1.0/go.mod h1:dAy3ld7l9f0ibDNOQOHHMYYIIbhfbHSm3C4ZsoJORNo= github.com/kr/pretty v0.3.1 h1:flRD4NNwYAUpkphVc1HcthR4KEIFJ65n8Mw5qdRn3LE= @@ -233,7 +233,6 @@ golang.org/x/sys v0.0.0-20211025201205-69cdffdb9359/go.mod h1:oPkhp1MJrh7nUepCBc golang.org/x/sys v0.0.0-20220715151400-c0bba94af5f8/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg= golang.org/x/sys v0.0.0-20220908164124-27713097b956/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg= golang.org/x/sys v0.1.0/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg= -golang.org/x/sys v0.5.0/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg= golang.org/x/sys v0.8.0/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg= golang.org/x/sys v0.11.0/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg= golang.org/x/sys v0.45.0 h1:dO4czNzziLiiXplLQgBCEpCvXQ3dnkn0SdaZSYdQ+FY= diff --git a/go.work.sum b/go.work.sum index bc9ee442f..15113fe09 100644 --- a/go.work.sum +++ b/go.work.sum @@ -4957,6 +4957,7 @@ golang.org/x/sys v0.28.0/go.mod h1:/VUhepiaJMQUp4+oa/7Zr1D23ma6VTLIYjOOTFZPUcA= golang.org/x/sys v0.30.0/go.mod h1:/VUhepiaJMQUp4+oa/7Zr1D23ma6VTLIYjOOTFZPUcA= golang.org/x/sys v0.32.0/go.mod h1:BJP2sWEmIv4KK5OTEluFJCKSidICx8ciO85XgH3Ak8k= golang.org/x/sys v0.37.0/go.mod h1:OgkHotnGiDImocRcuBABYBEXf8A9a87e/uXjp9XT3ks= +golang.org/x/sys v0.41.0/go.mod h1:OgkHotnGiDImocRcuBABYBEXf8A9a87e/uXjp9XT3ks= golang.org/x/sys v0.43.0/go.mod h1:4GL1E5IUh+htKOUEOaiffhrAeqysfVGipDYzABqnCmw= golang.org/x/sys v0.44.0/go.mod h1:4GL1E5IUh+htKOUEOaiffhrAeqysfVGipDYzABqnCmw= golang.org/x/telemetry v0.0.0-20240521205824-bda55230c457 h1:zf5N6UOrA487eEFacMePxjXAJctxKmyjKUsjA11Uzuk= diff --git a/vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml b/vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml index 944cc0007..14712fe0d 100644 --- a/vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml +++ b/vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml @@ -1,5 +1,4 @@ -# This is an example goreleaser.yaml file with some sane defaults. -# Make sure to check the documentation at http://goreleaser.com +version: 2 builds: - @@ -27,25 +26,14 @@ builds: archives: - id: cpuid - name_template: "cpuid-{{ .Os }}_{{ .Arch }}_{{ .Version }}" - replacements: - aix: AIX - darwin: OSX - linux: Linux - windows: Windows - 386: i386 - amd64: x86_64 - freebsd: FreeBSD - netbsd: NetBSD + name_template: "cpuid-{{ .Os }}_{{ .Arch }}{{ if .Arm }}v{{ .Arm }}{{ end }}" format_overrides: - goos: windows - format: zip + formats: [ 'zip' ] files: - LICENSE checksum: name_template: 'checksums.txt' -snapshot: - name_template: "{{ .Tag }}-next" changelog: sort: asc filters: @@ -58,7 +46,7 @@ changelog: nfpms: - - file_name_template: "cpuid_package_{{ .Version }}_{{ .Os }}_{{ .Arch }}" + file_name_template: "cpuid_package_{{ .Os }}_{{ .Arch }}{{ if .Arm }}v{{ .Arm }}{{ end }}" vendor: Klaus Post homepage: https://github.com/klauspost/cpuid maintainer: Klaus Post @@ -67,8 +55,3 @@ nfpms: formats: - deb - rpm - replacements: - darwin: Darwin - linux: Linux - freebsd: FreeBSD - amd64: x86_64 diff --git a/vendor/github.com/klauspost/cpuid/v2/README.md b/vendor/github.com/klauspost/cpuid/v2/README.md index accd7abaf..a99bbdba3 100644 --- a/vendor/github.com/klauspost/cpuid/v2/README.md +++ b/vendor/github.com/klauspost/cpuid/v2/README.md @@ -2,17 +2,14 @@ Package cpuid provides information about the CPU running the current program. CPU features are detected on startup, and kept for fast access through the life of the application. -Currently x86 / x64 (AMD64/i386) and ARM (ARM64) is supported, and no external C (cgo) code is used, which should make the library very easy to use. +Currently x86 / x64 (AMD64/i386), ARM (ARM64), and RISC-V (RV64) are supported, and no external C (cgo) code is used, which should make the library very easy to use. You can access the CPU information by accessing the shared CPU variable of the cpuid library. Package home: https://github.com/klauspost/cpuid [![PkgGoDev](https://pkg.go.dev/badge/github.com/klauspost/cpuid)](https://pkg.go.dev/github.com/klauspost/cpuid/v2) -[![Build Status][3]][4] - -[3]: https://travis-ci.org/klauspost/cpuid.svg?branch=master -[4]: https://travis-ci.org/klauspost/cpuid +[![Go](https://github.com/klauspost/cpuid/actions/workflows/go.yml/badge.svg)](https://github.com/klauspost/cpuid/actions/workflows/go.yml) ## installing @@ -284,8 +281,17 @@ Exit Code 1 | AMXBF16 | Tile computational operations on BFLOAT16 numbers | | AMXINT8 | Tile computational operations on 8-bit integers | | AMXFP16 | Tile computational operations on FP16 numbers | +| AMXFP8 | Tile computational operations on FP8 numbers | +| AMXCOMPLEX | Tile computational operations on complex numbers | | AMXTILE | Tile architecture | +| AMXTF32 | Matrix Multiplication of TF32 Tiles into Packed Single Precision Tile | +| AMXTRANSPOSE | Tile multiply where the first operand is transposed | +| APX_F | Intel APX | | AVX | AVX functions | +| AVX10 | If set the Intel AVX10 Converged Vector ISA is supported | +| AVX10_128 | If set indicates that AVX10 128-bit vector support is present | +| AVX10_256 | If set indicates that AVX10 256-bit vector support is present | +| AVX10_512 | If set indicates that AVX10 512-bit vector support is present | | AVX2 | AVX2 functions | | AVX512BF16 | AVX-512 BFLOAT16 Instructions | | AVX512BITALG | AVX-512 Bit Algorithms | @@ -308,6 +314,7 @@ Exit Code 1 | AVXSLOW | Indicates the CPU performs 2 128 bit operations instead of one | | AVXVNNI | AVX (VEX encoded) VNNI neural network instructions | | AVXVNNIINT8 | AVX-VNNI-INT8 instructions | +| AVXVNNIINT16 | AVX-VNNI-INT16 instructions | | BHI_CTRL | Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598 | | BMI1 | Bit Manipulation Instruction Set 1 | | BMI2 | Bit Manipulation Instruction Set 2 | @@ -365,6 +372,8 @@ Exit Code 1 | IDPRED_CTRL | IPRED_DIS | | INT_WBINVD | WBINVD/WBNOINVD are interruptible. | | INVLPGB | NVLPGB and TLBSYNC instruction supported | +| KEYLOCKER | Key locker | +| KEYLOCKERW | Key locker wide | | LAHF | LAHF/SAHF in long mode | | LAM | If set, CPU supports Linear Address Masking | | LBRVIRT | LBR virtualization | @@ -380,7 +389,7 @@ Exit Code 1 | MOVDIRI | Move Doubleword as Direct Store | | MOVSB_ZL | Fast Zero-Length MOVSB | | MPX | Intel MPX (Memory Protection Extensions) | -| MOVU | MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD | +| MOVU | MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD | | MSRIRC | Instruction Retired Counter MSR available | | MSRLIST | Read/Write List of Model Specific Registers | | MSR_PAGEFLUSH | Page Flush MSR available | @@ -409,9 +418,12 @@ Exit Code 1 | SEV_SNP | AMD SEV Secure Nested Paging supported | | SGX | Software Guard Extensions | | SGXLC | Software Guard Extensions Launch Control | +| SGXPQC | Software Guard Extensions 256-bit Encryption | | SHA | Intel SHA Extensions | | SME | AMD Secure Memory Encryption supported | | SME_COHERENT | AMD Hardware cache coherency across encryption domains enforced | +| SM3_X86 | SM3 instructions | +| SM4_X86 | SM4 instructions | | SPEC_CTRL_SSBD | Speculative Store Bypass Disable | | SRBDS_CTRL | SRBDS mitigation MSR available | | SSE | SSE functions | @@ -439,6 +451,9 @@ Exit Code 1 | TLB_FLUSH_NESTED | AMD: Flushing includes all the nested translations for guest translations | | TME | Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. | | TOPEXT | TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX. | +| TSA_L1_NO | AMD only: Not vulnerable to TSA-L1 | +| TSA_SQ_NO | AMD only: Not vulnerable to TSA-SQ | +| TSA_VERW_CLEAR | AMD: If set, the memory form of the VERW instruction may be used to help mitigate TSA | | TSCRATEMSR | MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104 | | TSXLDTRK | Intel TSX Suspend Load Address Tracking | | VAES | Vector AES. AVX(512) versions requires additional checks. | @@ -474,12 +489,16 @@ Exit Code 1 | DCPOP | Data cache clean to Point of Persistence (DC CVAP) | | EVTSTRM | Generic timer | | FCMA | Floatin point complex number addition and multiplication | +| FHM | FMLAL and FMLSL instructions | | FP | Single-precision and double-precision floating point | | FPHP | Half-precision floating point | | GPA | Generic Pointer Authentication | | JSCVT | Javascript-style double->int convert (FJCVTZS) | | LRCPC | Weaker release consistency (LDAPR, etc) | | PMULL | Polynomial Multiply instructions (PMULL/PMULL2) | +| RNDR | Random Number instructions | +| TLB | Outer Shareable and TLB range maintenance instructions | +| TS | Flag manipulation instructions | | SHA1 | SHA-1 instructions (SHA1C, etc) | | SHA2 | SHA-2 instructions (SHA256H, etc) | | SHA3 | SHA-3 instructions (EOR3, RAXI, XAR, BCAX) | @@ -487,6 +506,74 @@ Exit Code 1 | SM3 | SM3 instructions | | SM4 | SM4 instructions | | SVE | Scalable Vector Extension | +| SVE2 | Scalable Vector Extension 2 | +| SB | Speculation barrier (SB instruction) | +| SSBS | Speculative Store Bypass Safe (PSTATE.SSBS) | +| BTI | Branch Target Identification | +| FLAGM2 | Condition flag manipulation version 2 (AXFLAG, XAFLAG) | +| FRINTTS | Floating-point to integer rounding (FRINT32Z, FRINT64Z, etc) | +| DCPODP | Data cache clean to Point of Deep Persistence (DC CVADP) | +| BF16 | BFloat16 instructions (BFDOT, BFMMLA, etc) | +| I8MM | Int8 matrix multiplication (SMMLA, UMMLA, USMMLA) | +| WFXT | WFE/WFI with timeout (WFET, WFIT) | +| MOPS | Memory copy and set instructions (CPYF, SETP, etc) | +| HBC | Hinted conditional branches (BC.cond) | +| CSSC | Common short sequence compression (ABS, SMAX, UMAX, etc) | + +## riscv64 feature detection + +On `riscv64/linux`, CPU features are detected using the `riscv_hwprobe` syscall (Linux 6.4+). +For older kernels, detection falls back to parsing `/proc/cpuinfo` for the ISA string. + +Cache line size is detected via `riscv_hwprobe` (Zicbom block size) or sysfs fallback. +Other cache and topology information is not yet available. + +# RISC-V features: + +| Feature Flag | Description | +|----------------|----------------------------------------------------| +| RV_IMA | IMA base (Integer, Multiply, Atomic) | +| RV_C | Compressed instructions | +| RV_F | Single-precision FP | +| RV_D | Double-precision FP | +| RV_V | Vector extension (V) | +| RV_ZBA | Address generation | +| RV_ZBB | Basic bit manipulation | +| RV_ZBC | Carry-less multiplication | +| RV_ZBS | Single-bit manipulation | +| RV_ZICOND | Integer conditional operations | +| RV_ZIHINTPAUSE | Pause hint | +| RV_ZICBOM | Cache block management operations | +| RV_ZICBOZ | Cache block zero | +| RV_ZICBOP | Cache block prefetch | +| RV_ZFA | Additional floating-point | +| RV_ZFH | Half-precision FP | +| RV_ZFHMIN | Minimal half-precision FP | +| RV_ZTSO | Total store ordering | +| RV_ZACAS | Atomic CAS | +| RV_ZBKB | Bit-manipulation for crypto | +| RV_ZBKC | Carry-less multiply for crypto | +| RV_ZBKX | Crossbar permutations | +| RV_ZKND | NIST Suite: AES decrypt | +| RV_ZKNE | NIST Suite: AES encrypt | +| RV_ZKNH | NIST Suite: SHA-2 (SHA-256/SHA-512) | +| RV_ZKSED | ShangMi Suite: SM4 block cipher | +| RV_ZKSH | ShangMi Suite: SM3 hash | +| RV_ZKT | Data-independent execution latency (Crypto) | +| RV_ZKN | NIST Algorithm Suite (combined from individual) | +| RV_ZKS | ShangMi Algorithm Suite (combined from individual) | +| RV_ZVBB | Vector Basic Bit-manipulation | +| RV_ZVBC | Vector Carry-less multiply | +| RV_ZVKB | Vector Bit-manipulation for crypto | +| RV_ZVKG | Vector GCM/GMAC | +| RV_ZVKNED | NIST Suite: Vector AES encrypt+decrypt | +| RV_ZVKNHA | NIST Suite: Vector SHA-2 (SHA-256) | +| RV_ZVKNHB | NIST Suite: Vector SHA-2 (SHA-512) | +| RV_ZVKSED | ShangMi Suite: Vector SM4 | +| RV_ZVKSH | ShangMi Suite: Vector SM3 hash | +| RV_ZVKT | Vector Data-independent execution latency | +| RV_ZVKNG | NIST Suite with GCM (combined from individual) | +| RV_ZVKSG | ShangMi Suite with GCM (combined from individual) | # license diff --git a/vendor/github.com/klauspost/cpuid/v2/cpuid.go b/vendor/github.com/klauspost/cpuid/v2/cpuid.go index d015c744e..db903f46a 100644 --- a/vendor/github.com/klauspost/cpuid/v2/cpuid.go +++ b/vendor/github.com/klauspost/cpuid/v2/cpuid.go @@ -3,7 +3,7 @@ // Package cpuid provides information about the CPU running the current program. // // CPU features are detected on startup, and kept for fast access through the life of the application. -// Currently x86 / x64 (AMD64) as well as arm64 is supported. +// Currently x86 / x64 (AMD64), arm64, and riscv64 are supported. // // You can access the CPU information by accessing the shared CPU variable of the cpuid library. // @@ -17,6 +17,7 @@ import ( "math/bits" "os" "runtime" + "slices" "strings" ) @@ -55,6 +56,19 @@ const ( Qualcomm Marvell + QEMU + QNX + ACRN + SRE + Apple + + // RISC-V vendors + SiFive + StarFive + THead + Andes + SpacemiT + lastVendor ) @@ -67,188 +81,213 @@ const ( // Keep index -1 as unknown UNKNOWN = -1 - // Add features - ADX FeatureID = iota // Intel ADX (Multi-Precision Add-Carry Instruction Extensions) - AESNI // Advanced Encryption Standard New Instructions - AMD3DNOW // AMD 3DNOW - AMD3DNOWEXT // AMD 3DNowExt - AMXBF16 // Tile computational operations on BFLOAT16 numbers - AMXFP16 // Tile computational operations on FP16 numbers - AMXINT8 // Tile computational operations on 8-bit integers - AMXTILE // Tile architecture - AVX // AVX functions - AVX2 // AVX2 functions - AVX512BF16 // AVX-512 BFLOAT16 Instructions - AVX512BITALG // AVX-512 Bit Algorithms - AVX512BW // AVX-512 Byte and Word Instructions - AVX512CD // AVX-512 Conflict Detection Instructions - AVX512DQ // AVX-512 Doubleword and Quadword Instructions - AVX512ER // AVX-512 Exponential and Reciprocal Instructions - AVX512F // AVX-512 Foundation - AVX512FP16 // AVX-512 FP16 Instructions - AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions - AVX512PF // AVX-512 Prefetch Instructions - AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions - AVX512VBMI2 // AVX-512 Vector Bit Manipulation Instructions, Version 2 - AVX512VL // AVX-512 Vector Length Extensions - AVX512VNNI // AVX-512 Vector Neural Network Instructions - AVX512VP2INTERSECT // AVX-512 Intersect for D/Q - AVX512VPOPCNTDQ // AVX-512 Vector Population Count Doubleword and Quadword - AVXIFMA // AVX-IFMA instructions - AVXNECONVERT // AVX-NE-CONVERT instructions - AVXSLOW // Indicates the CPU performs 2 128 bit operations instead of one - AVXVNNI // AVX (VEX encoded) VNNI neural network instructions - AVXVNNIINT8 // AVX-VNNI-INT8 instructions - BHI_CTRL // Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598 - BMI1 // Bit Manipulation Instruction Set 1 - BMI2 // Bit Manipulation Instruction Set 2 - CETIBT // Intel CET Indirect Branch Tracking - CETSS // Intel CET Shadow Stack - CLDEMOTE // Cache Line Demote - CLMUL // Carry-less Multiplication - CLZERO // CLZERO instruction supported - CMOV // i686 CMOV - CMPCCXADD // CMPCCXADD instructions - CMPSB_SCADBS_SHORT // Fast short CMPSB and SCASB - CMPXCHG8 // CMPXCHG8 instruction - CPBOOST // Core Performance Boost - CPPC // AMD: Collaborative Processor Performance Control - CX16 // CMPXCHG16B Instruction - EFER_LMSLE_UNS // AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ - ENQCMD // Enqueue Command - ERMS // Enhanced REP MOVSB/STOSB - F16C // Half-precision floating-point conversion - FLUSH_L1D // Flush L1D cache - FMA3 // Intel FMA 3. Does not imply AVX. - FMA4 // Bulldozer FMA4 functions - FP128 // AMD: When set, the internal FP/SIMD execution datapath is no more than 128-bits wide - FP256 // AMD: When set, the internal FP/SIMD execution datapath is no more than 256-bits wide - FSRM // Fast Short Rep Mov - FXSR // FXSAVE, FXRESTOR instructions, CR4 bit 9 - FXSROPT // FXSAVE/FXRSTOR optimizations - GFNI // Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage. - HLE // Hardware Lock Elision - HRESET // If set CPU supports history reset and the IA32_HRESET_ENABLE MSR - HTT // Hyperthreading (enabled) - HWA // Hardware assert supported. Indicates support for MSRC001_10 - HYBRID_CPU // This part has CPUs of more than one type. - HYPERVISOR // This bit has been reserved by Intel & AMD for use by hypervisors - IA32_ARCH_CAP // IA32_ARCH_CAPABILITIES MSR (Intel) - IA32_CORE_CAP // IA32_CORE_CAPABILITIES MSR - IBPB // Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB) - IBRS // AMD: Indirect Branch Restricted Speculation - IBRS_PREFERRED // AMD: IBRS is preferred over software solution - IBRS_PROVIDES_SMP // AMD: IBRS provides Same Mode Protection - IBS // Instruction Based Sampling (AMD) - IBSBRNTRGT // Instruction Based Sampling Feature (AMD) - IBSFETCHSAM // Instruction Based Sampling Feature (AMD) - IBSFFV // Instruction Based Sampling Feature (AMD) - IBSOPCNT // Instruction Based Sampling Feature (AMD) - IBSOPCNTEXT // Instruction Based Sampling Feature (AMD) - IBSOPSAM // Instruction Based Sampling Feature (AMD) - IBSRDWROPCNT // Instruction Based Sampling Feature (AMD) - IBSRIPINVALIDCHK // Instruction Based Sampling Feature (AMD) - IBS_FETCH_CTLX // AMD: IBS fetch control extended MSR supported - IBS_OPDATA4 // AMD: IBS op data 4 MSR supported - IBS_OPFUSE // AMD: Indicates support for IbsOpFuse - IBS_PREVENTHOST // Disallowing IBS use by the host supported - IBS_ZEN4 // AMD: Fetch and Op IBS support IBS extensions added with Zen4 - IDPRED_CTRL // IPRED_DIS - INT_WBINVD // WBINVD/WBNOINVD are interruptible. - INVLPGB // NVLPGB and TLBSYNC instruction supported - LAHF // LAHF/SAHF in long mode - LAM // If set, CPU supports Linear Address Masking - LBRVIRT // LBR virtualization - LZCNT // LZCNT instruction - MCAOVERFLOW // MCA overflow recovery support. - MCDT_NO // Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it. - MCOMMIT // MCOMMIT instruction supported - MD_CLEAR // VERW clears CPU buffers - MMX // standard MMX - MMXEXT // SSE integer functions or AMD MMX ext - MOVBE // MOVBE instruction (big-endian) - MOVDIR64B // Move 64 Bytes as Direct Store - MOVDIRI // Move Doubleword as Direct Store - MOVSB_ZL // Fast Zero-Length MOVSB - MOVU // AMD: MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD - MPX // Intel MPX (Memory Protection Extensions) - MSRIRC // Instruction Retired Counter MSR available - MSRLIST // Read/Write List of Model Specific Registers - MSR_PAGEFLUSH // Page Flush MSR available - NRIPS // Indicates support for NRIP save on VMEXIT - NX // NX (No-Execute) bit - OSXSAVE // XSAVE enabled by OS - PCONFIG // PCONFIG for Intel Multi-Key Total Memory Encryption - POPCNT // POPCNT instruction - PPIN // AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled - PREFETCHI // PREFETCHIT0/1 instructions - PSFD // Predictive Store Forward Disable - RDPRU // RDPRU instruction supported - RDRAND // RDRAND instruction is available - RDSEED // RDSEED instruction is available - RDTSCP // RDTSCP Instruction - RRSBA_CTRL // Restricted RSB Alternate - RTM // Restricted Transactional Memory - RTM_ALWAYS_ABORT // Indicates that the loaded microcode is forcing RTM abort. - SERIALIZE // Serialize Instruction Execution - SEV // AMD Secure Encrypted Virtualization supported - SEV_64BIT // AMD SEV guest execution only allowed from a 64-bit host - SEV_ALTERNATIVE // AMD SEV Alternate Injection supported - SEV_DEBUGSWAP // Full debug state swap supported for SEV-ES guests - SEV_ES // AMD SEV Encrypted State supported - SEV_RESTRICTED // AMD SEV Restricted Injection supported - SEV_SNP // AMD SEV Secure Nested Paging supported - SGX // Software Guard Extensions - SGXLC // Software Guard Extensions Launch Control - SHA // Intel SHA Extensions - SME // AMD Secure Memory Encryption supported - SME_COHERENT // AMD Hardware cache coherency across encryption domains enforced - SPEC_CTRL_SSBD // Speculative Store Bypass Disable - SRBDS_CTRL // SRBDS mitigation MSR available - SSE // SSE functions - SSE2 // P4 SSE functions - SSE3 // Prescott SSE3 functions - SSE4 // Penryn SSE4.1 functions - SSE42 // Nehalem SSE4.2 functions - SSE4A // AMD Barcelona microarchitecture SSE4a instructions - SSSE3 // Conroe SSSE3 functions - STIBP // Single Thread Indirect Branch Predictors - STIBP_ALWAYSON // AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On - STOSB_SHORT // Fast short STOSB - SUCCOR // Software uncorrectable error containment and recovery capability. - SVM // AMD Secure Virtual Machine - SVMDA // Indicates support for the SVM decode assists. - SVMFBASID // SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control - SVML // AMD SVM lock. Indicates support for SVM-Lock. - SVMNP // AMD SVM nested paging - SVMPF // SVM pause intercept filter. Indicates support for the pause intercept filter - SVMPFT // SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold - SYSCALL // System-Call Extension (SCE): SYSCALL and SYSRET instructions. - SYSEE // SYSENTER and SYSEXIT instructions - TBM // AMD Trailing Bit Manipulation - TDX_GUEST // Intel Trust Domain Extensions Guest - TLB_FLUSH_NESTED // AMD: Flushing includes all the nested translations for guest translations - TME // Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. - TOPEXT // TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX. - TSCRATEMSR // MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104 - TSXLDTRK // Intel TSX Suspend Load Address Tracking - VAES // Vector AES. AVX(512) versions requires additional checks. - VMCBCLEAN // VMCB clean bits. Indicates support for VMCB clean bits. - VMPL // AMD VM Permission Levels supported - VMSA_REGPROT // AMD VMSA Register Protection supported - VMX // Virtual Machine Extensions - VPCLMULQDQ // Carry-Less Multiplication Quadword. Requires AVX for 3 register versions. - VTE // AMD Virtual Transparent Encryption supported - WAITPKG // TPAUSE, UMONITOR, UMWAIT - WBNOINVD // Write Back and Do Not Invalidate Cache - WRMSRNS // Non-Serializing Write to Model Specific Register - X87 // FPU - XGETBV1 // Supports XGETBV with ECX = 1 - XOP // Bulldozer XOP functions - XSAVE // XSAVE, XRESTOR, XSETBV, XGETBV - XSAVEC // Supports XSAVEC and the compacted form of XRSTOR. - XSAVEOPT // XSAVEOPT available - XSAVES // Supports XSAVES/XRSTORS and IA32_XSS + // x86 features + ADX FeatureID = iota // Intel ADX (Multi-Precision Add-Carry Instruction Extensions) + AESNI // Advanced Encryption Standard New Instructions + AMD3DNOW // AMD 3DNOW + AMD3DNOWEXT // AMD 3DNowExt + AMXBF16 // Tile computational operations on BFLOAT16 numbers + AMXFP16 // Tile computational operations on FP16 numbers + AMXINT8 // Tile computational operations on 8-bit integers + AMXFP8 // Tile computational operations on FP8 numbers + AMXTILE // Tile architecture + AMXTF32 // Tile architecture + AMXCOMPLEX // Matrix Multiplication of TF32 Tiles into Packed Single Precision Tile + AMXTRANSPOSE // Tile multiply where the first operand is transposed + APX_F // Intel APX + AVX // AVX functions + AVX10 // If set the Intel AVX10 Converged Vector ISA is supported + AVX10_128 // If set indicates that AVX10 128-bit vector support is present + AVX10_256 // If set indicates that AVX10 256-bit vector support is present + AVX10_512 // If set indicates that AVX10 512-bit vector support is present + AVX2 // AVX2 functions + AVX512BF16 // AVX-512 BFLOAT16 Instructions + AVX512BITALG // AVX-512 Bit Algorithms + AVX512BMM // AVX-512 Bit Manipulation Instructions + AVX512BW // AVX-512 Byte and Word Instructions + AVX512CD // AVX-512 Conflict Detection Instructions + AVX512DQ // AVX-512 Doubleword and Quadword Instructions + AVX512ER // AVX-512 Exponential and Reciprocal Instructions + AVX512F // AVX-512 Foundation + AVX512FP16 // AVX-512 FP16 Instructions + AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions + AVX512PF // AVX-512 Prefetch Instructions + AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions + AVX512VBMI2 // AVX-512 Vector Bit Manipulation Instructions, Version 2 + AVX512VL // AVX-512 Vector Length Extensions + AVX512VNNI // AVX-512 Vector Neural Network Instructions + AVX512VP2INTERSECT // AVX-512 Intersect for D/Q + AVX512VPOPCNTDQ // AVX-512 Vector Population Count Doubleword and Quadword + AVXIFMA // AVX-IFMA instructions + AVXNECONVERT // AVX-NE-CONVERT instructions + AVXSLOW // Indicates the CPU performs 2 128 bit operations instead of one + AVXVNNI // AVX (VEX encoded) VNNI neural network instructions + AVXVNNIINT8 // AVX-VNNI-INT8 instructions + AVXVNNIINT16 // AVX-VNNI-INT16 instructions + BHI_CTRL // Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598 + BMI1 // Bit Manipulation Instruction Set 1 + BMI2 // Bit Manipulation Instruction Set 2 + CETIBT // Intel CET Indirect Branch Tracking + CETSS // Intel CET Shadow Stack + CLDEMOTE // Cache Line Demote + CLMUL // Carry-less Multiplication + CLZERO // CLZERO instruction supported + CMOV // i686 CMOV + CMPCCXADD // CMPCCXADD instructions + CMPSB_SCADBS_SHORT // Fast short CMPSB and SCASB + CMPXCHG8 // CMPXCHG8 instruction + CPBOOST // Core Performance Boost + CPPC // AMD: Collaborative Processor Performance Control + CX16 // CMPXCHG16B Instruction + EFER_LMSLE_UNS // AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ + ENQCMD // Enqueue Command + ERMS // Enhanced REP MOVSB/STOSB + F16C // Half-precision floating-point conversion + FLUSH_L1D // Flush L1D cache + FMA3 // Intel FMA 3. Does not imply AVX. + FMA4 // Bulldozer FMA4 functions + FP128 // AMD: When set, the internal FP/SIMD execution datapath is no more than 128-bits wide + FP256 // AMD: When set, the internal FP/SIMD execution datapath is no more than 256-bits wide + FRED // Flexible Return and Event Delivery + FSRM // Fast Short Rep Mov + FXSR // FXSAVE, FXRESTOR instructions, CR4 bit 9 + FXSROPT // FXSAVE/FXRSTOR optimizations + GFNI // Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage. + HLE // Hardware Lock Elision + HRESET // If set CPU supports history reset and the IA32_HRESET_ENABLE MSR + HTT // Hyperthreading (enabled) + HWA // Hardware assert supported. Indicates support for MSRC001_10 + HYBRID_CPU // This part has CPUs of more than one type. + HYPERVISOR // This bit has been reserved by Intel & AMD for use by hypervisors + IA32_ARCH_CAP // IA32_ARCH_CAPABILITIES MSR (Intel) + IA32_CORE_CAP // IA32_CORE_CAPABILITIES MSR + IBPB // Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB) + IBPB_BRTYPE // Indicates that MSR 49h (PRED_CMD) bit 0 (IBPB) flushes all branch type predictions from the CPU branch predictor + IBRS // AMD: Indirect Branch Restricted Speculation + IBRS_PREFERRED // AMD: IBRS is preferred over software solution + IBRS_PROVIDES_SMP // AMD: IBRS provides Same Mode Protection + IBS // Instruction Based Sampling (AMD) + IBSBRNTRGT // Instruction Based Sampling Feature (AMD) + IBSFETCHSAM // Instruction Based Sampling Feature (AMD) + IBSFFV // Instruction Based Sampling Feature (AMD) + IBSOPCNT // Instruction Based Sampling Feature (AMD) + IBSOPCNTEXT // Instruction Based Sampling Feature (AMD) + IBSOPSAM // Instruction Based Sampling Feature (AMD) + IBSRDWROPCNT // Instruction Based Sampling Feature (AMD) + IBSRIPINVALIDCHK // Instruction Based Sampling Feature (AMD) + IBS_FETCH_CTLX // AMD: IBS fetch control extended MSR supported + IBS_OPDATA4 // AMD: IBS op data 4 MSR supported + IBS_OPFUSE // AMD: Indicates support for IbsOpFuse + IBS_PREVENTHOST // Disallowing IBS use by the host supported + IBS_ZEN4 // AMD: Fetch and Op IBS support IBS extensions added with Zen4 + IDPRED_CTRL // IPRED_DIS + INT_WBINVD // WBINVD/WBNOINVD are interruptible. + INVLPGB // NVLPGB and TLBSYNC instruction supported + KEYLOCKER // Key locker + KEYLOCKERW // Key locker wide + LAHF // LAHF/SAHF in long mode + LAM // If set, CPU supports Linear Address Masking + LBRVIRT // LBR virtualization + LZCNT // LZCNT instruction + MCAOVERFLOW // MCA overflow recovery support. + MCDT_NO // Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it. + MCOMMIT // MCOMMIT instruction supported + MD_CLEAR // VERW clears CPU buffers + MMX // standard MMX + MMXEXT // SSE integer functions or AMD MMX ext + MOVBE // MOVBE instruction (big-endian) + MOVDIR64B // Move 64 Bytes as Direct Store + MOVDIRI // Move Doubleword as Direct Store + MOVSB_ZL // Fast Zero-Length MOVSB + MOVU // AMD: MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD + MPX // Intel MPX (Memory Protection Extensions) + MSRIRC // Instruction Retired Counter MSR available + MSRLIST // Read/Write List of Model Specific Registers + MSR_PAGEFLUSH // Page Flush MSR available + NRIPS // Indicates support for NRIP save on VMEXIT + NX // NX (No-Execute) bit + OSXSAVE // XSAVE enabled by OS + PCONFIG // PCONFIG for Intel Multi-Key Total Memory Encryption + POPCNT // POPCNT instruction + PPIN // AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled + PREFETCHI // PREFETCHIT0/1 instructions + PSFD // Predictive Store Forward Disable + RDPRU // RDPRU instruction supported + RDRAND // RDRAND instruction is available + RDSEED // RDSEED instruction is available + RDTSCP // RDTSCP Instruction + RRSBA_CTRL // Restricted RSB Alternate + RTM // Restricted Transactional Memory + RTM_ALWAYS_ABORT // Indicates that the loaded microcode is forcing RTM abort. + SBPB // Indicates support for the Selective Branch Predictor Barrier + SERIALIZE // Serialize Instruction Execution + SEV // AMD Secure Encrypted Virtualization supported + SEV_64BIT // AMD SEV guest execution only allowed from a 64-bit host + SEV_ALTERNATIVE // AMD SEV Alternate Injection supported + SEV_DEBUGSWAP // Full debug state swap supported for SEV-ES guests + SEV_ES // AMD SEV Encrypted State supported + SEV_RESTRICTED // AMD SEV Restricted Injection supported + SEV_SNP // AMD SEV Secure Nested Paging supported + SGX // Software Guard Extensions + SGXLC // Software Guard Extensions Launch Control + SGXPQC // Software Guard Extensions 256-bit Encryption + SHA // Intel SHA Extensions + SME // AMD Secure Memory Encryption supported + SME_COHERENT // AMD Hardware cache coherency across encryption domains enforced + SM3_X86 // SM3 instructions + SM4_X86 // SM4 instructions + SPEC_CTRL_SSBD // Speculative Store Bypass Disable + SRBDS_CTRL // SRBDS mitigation MSR available + SRSO_MSR_FIX // Indicates that software may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO. + SRSO_NO // Indicates the CPU is not subject to the SRSO vulnerability + SRSO_USER_KERNEL_NO // Indicates the CPU is not subject to the SRSO vulnerability across user/kernel boundaries + SSE // SSE functions + SSE2 // P4 SSE functions + SSE3 // Prescott SSE3 functions + SSE4 // Penryn SSE4.1 functions + SSE42 // Nehalem SSE4.2 functions + SSE4A // AMD Barcelona microarchitecture SSE4a instructions + SSSE3 // Conroe SSSE3 functions + STIBP // Single Thread Indirect Branch Predictors + STIBP_ALWAYSON // AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On + STOSB_SHORT // Fast short STOSB + SUCCOR // Software uncorrectable error containment and recovery capability. + SVM // AMD Secure Virtual Machine + SVMDA // Indicates support for the SVM decode assists. + SVMFBASID // SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control + SVML // AMD SVM lock. Indicates support for SVM-Lock. + SVMNP // AMD SVM nested paging + SVMPF // SVM pause intercept filter. Indicates support for the pause intercept filter + SVMPFT // SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold + SYSCALL // System-Call Extension (SCE): SYSCALL and SYSRET instructions. + SYSEE // SYSENTER and SYSEXIT instructions + TBM // AMD Trailing Bit Manipulation + TDX_GUEST // Intel Trust Domain Extensions Guest + TLB_FLUSH_NESTED // AMD: Flushing includes all the nested translations for guest translations + TME // Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. + TOPEXT // TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX. + TSA_L1_NO // AMD only: Not vulnerable to TSA-L1 + TSA_SQ_NO // AM onlyD: Not vulnerable to TSA-SQ + TSA_VERW_CLEAR // If set, the memory form of the VERW instruction may be used to help mitigate TSA + TSCRATEMSR // MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104 + TSXLDTRK // Intel TSX Suspend Load Address Tracking + VAES // Vector AES. AVX(512) versions requires additional checks. + VMCBCLEAN // VMCB clean bits. Indicates support for VMCB clean bits. + VMPL // AMD VM Permission Levels supported + VMSA_REGPROT // AMD VMSA Register Protection supported + VMX // Virtual Machine Extensions + VPCLMULQDQ // Carry-Less Multiplication Quadword. Requires AVX for 3 register versions. + VTE // AMD Virtual Transparent Encryption supported + WAITPKG // TPAUSE, UMONITOR, UMWAIT + WBNOINVD // Write Back and Do Not Invalidate Cache + WRMSRNS // Non-Serializing Write to Model Specific Register + X87 // FPU + XGETBV1 // Supports XGETBV with ECX = 1 + XOP // Bulldozer XOP functions + XSAVE // XSAVE, XRESTOR, XSETBV, XGETBV + XSAVEC // Supports XSAVEC and the compacted form of XRSTOR. + XSAVEOPT // XSAVEOPT available + XSAVES // Supports XSAVES/XRSTORS and IA32_XSS // ARM features: AESARM // AES instructions @@ -261,13 +300,17 @@ const ( CRC32 // CRC32/CRC32C instructions DCPOP // Data cache clean to Point of Persistence (DC CVAP) EVTSTRM // Generic timer - FCMA // Floatin point complex number addition and multiplication + FCMA // Floating point complex number addition and multiplication + FHM // FMLAL and FMLSL instructions FP // Single-precision and double-precision floating point FPHP // Half-precision floating point GPA // Generic Pointer Authentication JSCVT // Javascript-style double->int convert (FJCVTZS) LRCPC // Weaker release consistency (LDAPR, etc) PMULL // Polynomial Multiply instructions (PMULL/PMULL2) + RNDR // Random Number instructions + TLB // Outer Shareable and TLB range maintenance instructions + TS // Flag manipulation instructions SHA1 // SHA-1 instructions (SHA1C, etc) SHA2 // SHA-2 instructions (SHA256H, etc) SHA3 // SHA-3 instructions (EOR3, RAXI, XAR, BCAX) @@ -275,6 +318,77 @@ const ( SM3 // SM3 instructions SM4 // SM4 instructions SVE // Scalable Vector Extension + SVE2 // Scalable Vector Extension 2 + SB // Speculation barrier (SB instruction) + SSBS // Speculative Store Bypass Safe (PSTATE.SSBS) + BTI // Branch Target Identification + FLAGM2 // Condition flag manipulation version 2 (AXFLAG, XAFLAG) + FRINTTS // Floating-point to integer rounding (FRINT32Z, FRINT64Z, etc) + DCPODP // Data cache clean to Point of Deep Persistence (DC CVADP) + BF16 // BFloat16 instructions (BFDOT, BFMMLA, etc) + I8MM // Int8 matrix multiplication (SMMLA, UMMLA, USMMLA) + WFXT // WFE/WFI with timeout (WFET, WFIT) + MOPS // Memory copy and set instructions (CPYF, SETP, etc) + HBC // Hinted conditional branches (BC.cond) + CSSC // Common short sequence compression (ABS, SMAX, UMAX, etc) + + // PMU + PMU_FIXEDCOUNTER_CYCLES + PMU_FIXEDCOUNTER_REFCYCLES + PMU_FIXEDCOUNTER_INSTRUCTIONS + PMU_FIXEDCOUNTER_TOPDOWN_SLOTS + + // RISC-V features + RV_IMA // IMA base (Integer, Multiply, Atomic) + RV_C // Compressed instructions + RV_F // Single-precision FP + RV_D // Double-precision FP + RV_V // Vector extension (V) + RV_ZBA // Address generation + RV_ZBB // Basic bit manipulation + RV_ZBC // Carry-less multiplication + RV_ZBS // Single-bit manipulation + RV_ZICOND // Integer conditional operations + RV_ZIHINTPAUSE // Pause hint + RV_ZICBOM // Cache block management operations + RV_ZICBOZ // Cache block zero + RV_ZICBOP // Cache block prefetch + RV_ZFA // Additional floating-point + RV_ZFH // Half-precision FP + RV_ZFHMIN // Minimal half-precision FP + RV_ZTSO // Total store ordering + RV_ZACAS // Atomic CAS + // Scalar cryptography + RV_ZBKB // Bit-manipulation for crypto + RV_ZBKC // Carry-less multiply for crypto + RV_ZBKX // Crossbar permutations + RV_ZKND // NIST Suite: AES decrypt + RV_ZKNE // NIST Suite: AES encrypt + RV_ZKNH // NIST Suite: SHA-2 (SHA-256/SHA-512) + RV_ZKSED // ShangMi Suite: SM4 block cipher + RV_ZKSH // ShangMi Suite: SM3 hash + RV_ZKT // Data-independent execution latency (Crypto) + + // Scalar crypto suites (combined from individual extensions) + RV_ZKN // NIST Algorithm Suite (Zknd+Zkne+Zknh+Zbkb+Zbkc+Zbkx+Zkt) + RV_ZKS // ShangMi Algorithm Suite (Zksed+Zksh+Zbkb+Zbkc+Zbkx+Zkt) + + // Vector cryptography + RV_ZVBB // Vector Basic Bit-manipulation + RV_ZVBC // Vector Carry-less multiply + RV_ZVKB // Vector Bit-manipulation for crypto + RV_ZVKG // Vector GCM/GMAC + RV_ZVKNED // NIST Suite: Vector AES encrypt+decrypt + RV_ZVKNHA // NIST Suite: Vector SHA-2 (SHA-256) + RV_ZVKNHB // NIST Suite: Vector SHA-2 (SHA-512) + RV_ZVKSED // ShangMi Suite: Vector SM4 + RV_ZVKSH // ShangMi Suite: Vector SM3 hash + RV_ZVKT // Vector Data-independent execution latency + + // Vector crypto suites (combined from individual extensions) + RV_ZVKNG // NIST Suite with GCM (Zvkned+Zvknhb+Zvkg+Zvkb+Zvkt) + RV_ZVKSG // ShangMi Suite with GCM (Zvksed+Zvksh+Zvkg+Zvkb+Zvkt) + // Keep it last. It automatically defines the size of []flagSet lastID @@ -283,30 +397,60 @@ const ( // CPUInfo contains information about the detected system CPU. type CPUInfo struct { - BrandName string // Brand name reported by the CPU - VendorID Vendor // Comparable CPU vendor ID - VendorString string // Raw vendor string. - featureSet flagSet // Features of the CPU - PhysicalCores int // Number of physical processor cores in your CPU. Will be 0 if undetectable. - ThreadsPerCore int // Number of threads per physical core. Will be 1 if undetectable. - LogicalCores int // Number of physical cores times threads that can run on each core through the use of hyperthreading. Will be 0 if undetectable. - Family int // CPU family number - Model int // CPU model number - Stepping int // CPU stepping info - CacheLine int // Cache line size in bytes. Will be 0 if undetectable. - Hz int64 // Clock speed, if known, 0 otherwise. Will attempt to contain base clock speed. - BoostFreq int64 // Max clock speed, if known, 0 otherwise - Cache struct { + BrandName string // Brand name reported by the CPU + VendorID Vendor // Comparable CPU vendor ID + VendorString string // Raw vendor string. + HypervisorVendorID Vendor // Hypervisor vendor + HypervisorVendorString string // Raw hypervisor vendor string + featureSet flagSet // Features of the CPU + PhysicalCores int // Number of physical processor cores in your CPU. Will be 0 if undetectable. + ThreadsPerCore int // Number of threads per physical core. Will be 1 if undetectable. + LogicalCores int // Number of physical cores times threads that can run on each core through the use of hyperthreading. Will be 0 if undetectable. + Family int // CPU family number + Model int // CPU model number + Stepping int // CPU stepping info + CacheLine int // Cache line size in bytes. Will be 0 if undetectable. + Hz int64 // Clock speed, if known, 0 otherwise. Will attempt to contain base clock speed. + BoostFreq int64 // Max clock speed, if known, 0 otherwise + Cache struct { L1I int // L1 Instruction Cache (per core or shared). Will be -1 if undetected L1D int // L1 Data Cache (per core or shared). Will be -1 if undetected L2 int // L2 Cache (per core or shared). Will be -1 if undetected L3 int // L3 Cache (per core, per ccx or shared). Will be -1 if undetected } - SGX SGXSupport + SGX SGXSupport + AMDMemEncryption AMDMemEncryptionSupport + AVX10Level uint8 + PMU PerformanceMonitoringInfo // holds information about the PMU + maxFunc uint32 maxExFunc uint32 } +// PerformanceMonitoringInfo holds information about CPU performance monitoring capabilities. +// This is primarily populated from CPUID leaf 0xAh on x86 +type PerformanceMonitoringInfo struct { + // VersionID (x86 only): Version ID of architectural performance monitoring. + // A value of 0 means architectural performance monitoring is not supported or information is unavailable. + VersionID uint8 + // NumGPPMC: Number of General-Purpose Performance Monitoring Counters per logical processor. + // On ARM, this is derived from PMCR_EL0.N (number of event counters). + NumGPCounters uint8 + // GPPMCWidth: Bit width of General-Purpose Performance Monitoring Counters. + // On ARM, typically 64 for PMU event counters. + GPPMCWidth uint8 + // NumFixedPMC: Number of Fixed-Function Performance Counters. + // Valid on x86 if VersionID > 1. On ARM, this typically includes at least the cycle counter (PMCCNTR_EL0). + NumFixedPMC uint8 + // FixedPMCWidth: Bit width of Fixed-Function Performance Counters. + // Valid on x86 if VersionID > 1. On ARM, the cycle counter (PMCCNTR_EL0) is 64-bit. + FixedPMCWidth uint8 + // Raw register output from CPUID leaf 0xAh. + RawEBX uint32 + RawEAX uint32 + RawEDX uint32 +} + var cpuid func(op uint32) (eax, ebx, ecx, edx uint32) var cpuidex func(op, op2 uint32) (eax, ebx, ecx, edx uint32) var xgetbv func(index uint32) (eax, edx uint32) @@ -349,8 +493,8 @@ func Detect() { os.Exit(1) } if disableFlag != nil { - s := strings.Split(*disableFlag, ",") - for _, feat := range s { + s := strings.SplitSeq(*disableFlag, ",") + for feat := range s { feat := ParseFeature(strings.TrimSpace(feat)) if feat != UNKNOWN { CPU.featureSet.unset(feat) @@ -401,12 +545,7 @@ func (c *CPUInfo) Has(id FeatureID) bool { // AnyOf returns whether the CPU supports one or more of the requested features. func (c CPUInfo) AnyOf(ids ...FeatureID) bool { - for _, id := range ids { - if c.featureSet.inSet(id) { - return true - } - } - return false + return slices.ContainsFunc(ids, c.featureSet.inSet) } // Features contains several features combined for a fast check using @@ -426,6 +565,11 @@ func (c *CPUInfo) HasAll(f Features) bool { return c.featureSet.hasSetP(f) } +// HasOneOf returns whether the CPU supports one or more of the requested features. +func (c *CPUInfo) HasOneOf(f Features) bool { + return c.featureSet.hasOneOf(f) +} + // https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels var oneOfLevel = CombineFeatures(SYSEE, SYSCALL) var level1Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2) @@ -433,6 +577,56 @@ var level2Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, var level3Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE) var level4Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE, AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL) +// RV_CRYPTO_FEATS contains all RISC-V scalar cryptography instruction extensions (excludes Zkt since it is a timing guarantee, not a computational instruction). +var RV_CRYPTO_FEATS = CombineFeatures(RV_ZBKB, RV_ZBKC, RV_ZBKX, RV_ZKND, RV_ZKNE, RV_ZKNH, RV_ZKSED, RV_ZKSH) + +// RV_VECTOR_CRYPTO_FEATS contains all RISC-V vector cryptography extensions. +var RV_VECTOR_CRYPTO_FEATS = CombineFeatures(RV_ZVBB, RV_ZVBC, RV_ZVKB, RV_ZVKG, RV_ZVKNED, RV_ZVKNHA, RV_ZVKNHB, RV_ZVKSED, RV_ZVKSH) + +// RISC-V application profile feature sets. +// https://github.com/riscv/riscv-profiles +var rvProfile20Features = CombineFeatures(RV_IMA, RV_C, RV_F, RV_D) +var rvProfile22Features = CombineFeatures(RV_IMA, RV_C, RV_F, RV_D, RV_ZBA, RV_ZBB, RV_ZBS, RV_ZFHMIN, RV_ZICBOM, RV_ZICBOP, RV_ZICBOZ, RV_ZIHINTPAUSE) +var rvProfile23Features = CombineFeatures(RV_IMA, RV_C, RV_F, RV_D, RV_ZBA, RV_ZBB, RV_ZBS, RV_ZFHMIN, RV_ZICBOM, RV_ZICBOP, RV_ZICBOZ, RV_ZIHINTPAUSE, RV_V, RV_ZFA, RV_ZICOND, RV_ZVBB, RV_ZVKB) + +// RISC-V crypto suites — combined from individual extensions. +var rvZKNFeatures = CombineFeatures(RV_ZKND, RV_ZKNE, RV_ZKNH, RV_ZBKB, RV_ZBKC, RV_ZBKX, RV_ZKT) +var rvZKSFeatures = CombineFeatures(RV_ZKSED, RV_ZKSH, RV_ZBKB, RV_ZBKC, RV_ZBKX, RV_ZKT) +var rvZVKNFeatures = CombineFeatures(RV_ZVKNED, RV_ZVKNHB, RV_ZVKG, RV_ZVKB, RV_ZVKT) +var rvZVKSFeatures = CombineFeatures(RV_ZVKSED, RV_ZVKSH, RV_ZVKG, RV_ZVKB, RV_ZVKT) + +// ARM64 architecture levels. armV8Levels[m] is the cumulative set of mandatory +// user-space instruction features added up to and including ARMv8.m that this +// package can detect. EL1/system-only features (PAN, VHE, CSV2/CSV3, ECV, ...) +// are excluded since they are irrelevant to user-space code generation, exactly +// as X64Level ignores non-instruction features. +// +// FEAT_SSBS and FEAT_BTI, although mandatory from ARMv8.5, are intentionally NOT +// required. Both are OS-policy-gated security features (speculative store bypass +// safety and branch-target identification) that Go code generation never depends +// on: their HWCAP/sysctl bits are set only when the OS or hypervisor enables the +// protection, not purely from CPU capability, so they are routinely hidden even +// on capable silicon (neither a Neoverse N2 Linux guest nor Apple Silicon reports +// them). Requiring them would cap such CPUs at v8.4. Both are still detected and +// reported through FeatureSet when present. +// https://go.dev/wiki/MinimumRequirements#arm64 +var armV8Levels = [...]Features{ + CombineFeatures(FP, ASIMD), // v8.0 + CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM), // v8.1 + CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP), // v8.2 + CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC), // v8.3 + CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC, TS), // v8.4 + CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC, TS, SB, FRINTTS, FLAGM2, DCPODP), // v8.5 + CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC, TS, SB, FRINTTS, FLAGM2, DCPODP, BF16, I8MM), // v8.6 + CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC, TS, SB, FRINTTS, FLAGM2, DCPODP, BF16, I8MM, WFXT), // v8.7 + CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC, TS, SB, FRINTTS, FLAGM2, DCPODP, BF16, I8MM, WFXT, MOPS, HBC), // v8.8 + CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC, TS, SB, FRINTTS, FLAGM2, DCPODP, BF16, I8MM, WFXT, MOPS, HBC, CSSC), // v8.9 +} + +// armCrypto matches the GOARM64 ",crypto" option: FEAT_AES, FEAT_PMULL, +// FEAT_SHA1 and FEAT_SHA256. +var armCrypto = CombineFeatures(AESARM, PMULL, SHA1, SHA2) + // X64Level returns the microarchitecture level detected on the CPU. // If features are lacking or non x64 mode, 0 is returned. // See https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels @@ -455,6 +649,67 @@ func (c CPUInfo) X64Level() int { return 0 } +// RVProfile returns the RISC-V application profile level. +// 0 = unknown / base ISA only, 20 = RVA20, 22 = RVA22, 23 = RVA23. +// Returns 0 on non-RISC-V architectures or if not detected. +// https://github.com/riscv/riscv-profiles +func (c CPUInfo) RVProfile() int { + switch { + case c.featureSet.hasSetP(rvProfile23Features): + return 23 + case c.featureSet.hasSetP(rvProfile22Features): + return 22 + case c.featureSet.hasSetP(rvProfile20Features): + return 20 + default: + return 0 + } +} + +// ARM64Level returns the ARMv8/ARMv9 architecture version supported by the CPU +// as (major, minor), e.g. 8, 4 for ARMv8.4-A or 9, 0 for ARMv9.0-A. +// Only mandatory user-space instruction features are considered, so the result +// is the highest level whose required instructions are all present. +// Returns 0, 0 on non-arm64 CPUs or when feature detection was unavailable. +func (c CPUInfo) ARM64Level() (major, minor int) { + if !c.featureSet.hasSetP(armV8Levels[0]) { + return 0, 0 + } + m8 := 0 + for m := len(armV8Levels) - 1; m >= 1; m-- { + if c.featureSet.hasSetP(armV8Levels[m]) { + m8 = m + break + } + } + // ARMv9.x mandates everything in ARMv8.(x+5) plus SVE2. + if m8 >= 5 && c.featureSet.inSet(SVE2) { + return 9, m8 - 5 + } + return 8, m8 +} + +// GOARM64 returns a value usable as the GOARM64 build setting for the detected +// CPU, e.g. "v8.4" or "v9.0,crypto". The ",crypto" suffix is appended when AES, +// PMULL, SHA1 and SHA256 are all present; the ",lse" suffix is appended in the +// rare case LSE is present without the rest of the ARMv8.1 feature set. +// Returns "" on non-arm64 CPUs or when feature detection was unavailable. +// See https://go.dev/wiki/MinimumRequirements#arm64 +func (c CPUInfo) GOARM64() string { + major, minor := c.ARM64Level() + if major == 0 { + return "" + } + v := fmt.Sprintf("v%d.%d", major, minor) + if major == 8 && minor == 0 && c.featureSet.inSet(ATOMICS) { + v += ",lse" + } + if c.featureSet.hasSetP(armCrypto) { + v += ",crypto" + } + return v +} + // Disable will disable one or several features. func (c *CPUInfo) Disable(ids ...FeatureID) bool { for _, id := range ids { @@ -488,7 +743,7 @@ func (c CPUInfo) FeatureSet() []string { // Uses the RDTSCP instruction. The value 0 is returned // if the CPU does not support the instruction. func (c CPUInfo) RTCounter() uint64 { - if !c.Supports(RDTSCP) { + if !c.Has(RDTSCP) { return 0 } a, _, _, d := rdtscpAsm() @@ -500,13 +755,22 @@ func (c CPUInfo) RTCounter() uint64 { // about the current cpu/core the code is running on. // If the RDTSCP instruction isn't supported on the CPU, the value 0 is returned. func (c CPUInfo) Ia32TscAux() uint32 { - if !c.Supports(RDTSCP) { + if !c.Has(RDTSCP) { return 0 } _, _, ecx, _ := rdtscpAsm() return ecx } +// SveLengths returns arm SVE vector and predicate lengths in bits. +// Will return 0, 0 if SVE is not enabled or otherwise unable to detect. +func (c CPUInfo) SveLengths() (vl, pl uint64) { + if !c.Has(SVE) { + return 0, 0 + } + return getVectorLength() +} + // LogicalCPU will return the Logical CPU the code is currently executing on. // This is likely to change when the OS re-schedules the running thread // to another CPU. @@ -692,7 +956,7 @@ func flagSetWith(feat ...FeatureID) flagSet { // Will return UNKNOWN if not found. func ParseFeature(s string) FeatureID { s = strings.ToUpper(s) - for i := firstID; i < lastID; i++ { + for i := range lastID { if i.String() == s { return i } @@ -706,7 +970,7 @@ func (s flagSet) Strings() []string { return []string{""} } r := make([]string, 0) - for i := firstID; i < lastID; i++ { + for i := range lastID { if s.inSet(i) { r = append(r, i.String()) } @@ -727,7 +991,7 @@ func maxFunctionID() uint32 { func brandName() string { if maxExtendedFunction() >= 0x80000004 { v := make([]uint32, 0, 48) - for i := uint32(0); i < 3; i++ { + for i := range uint32(3) { a, b, c, d := cpuid(0x80000002 + i) v = append(v, a, b, c, d) } @@ -766,11 +1030,16 @@ func threadsPerCore() int { _, b, _, _ := cpuidex(0xb, 0) if b&0xffff == 0 { if vend == AMD { - // Workaround for AMD returning 0, assume 2 if >= Zen 2 - // It will be more correct than not. + // if >= Zen 2 0x8000001e EBX 15-8 bits means threads per core. + // The number of threads per core is ThreadsPerCore+1 + // See PPR for AMD Family 17h Models 00h-0Fh (page 82) fam, _, _ := familyModel() _, _, _, d := cpuid(1) if (d&(1<<28)) != 0 && fam >= 23 { + if maxExtendedFunction() >= 0x8000001e { + _, b, _, _ := cpuid(0x8000001e) + return int((b>>8)&0xff) + 1 + } return 2 } } @@ -833,7 +1102,12 @@ func physicalCores() int { v, _ := vendorID() switch v { case Intel: - return logicalCores() / threadsPerCore() + lc := logicalCores() + tpc := threadsPerCore() + if lc > 0 && tpc > 0 { + return lc / tpc + } + return 0 case AMD, Hygon: lc := logicalCores() tpc := threadsPerCore() @@ -862,7 +1136,9 @@ var vendorMapping = map[string]Vendor{ "GenuineTMx86": Transmeta, "Geode by NSC": NSC, "VIA VIA VIA ": VIA, - "KVMKVMKVMKVM": KVM, + "KVMKVMKVM": KVM, + "Linux KVM Hv": KVM, + "TCGTCGTCGTCG": QEMU, "Microsoft Hv": MSVM, "VMwareVMware": VMware, "XenVMMXenVMM": XenHVM, @@ -872,6 +1148,10 @@ var vendorMapping = map[string]Vendor{ "SiS SiS SiS ": SiS, "RiseRiseRise": SiS, "Genuine RDC": RDC, + "QNXQVMBSQG": QNX, + "ACRNACRNACRN": ACRN, + "SRESRESRESRE": SRE, + "Apple VZ": Apple, } func vendorID() (Vendor, string) { @@ -884,6 +1164,17 @@ func vendorID() (Vendor, string) { return vend, v } +func hypervisorVendorID() (Vendor, string) { + // https://lwn.net/Articles/301888/ + _, b, c, d := cpuid(0x40000000) + v := string(valAsString(b, c, d)) + vend, ok := vendorMapping[v] + if !ok { + return VendorUnknown, v + } + return vend, v +} + func cacheLine() int { if maxFunctionID() < 0x1 { return 0 @@ -969,7 +1260,7 @@ func (c *CPUInfo) cacheSize() { // Hack: When we encounter the same entry 100 times we break. nSame := 0 var last uint32 - for i := uint32(0); i < math.MaxUint32; i++ { + for i := range uint32(math.MaxUint32) { eax, ebx, ecx, _ := cpuidex(0x8000001D, i) level := (eax >> 5) & 7 @@ -1071,6 +1362,32 @@ func hasSGX(available, lc bool) (rval SGXSupport) { return } +type AMDMemEncryptionSupport struct { + Available bool + CBitPossition uint32 + NumVMPL uint32 + PhysAddrReduction uint32 + NumEntryptedGuests uint32 + MinSevNoEsAsid uint32 +} + +func hasAMDMemEncryption(available bool) (rval AMDMemEncryptionSupport) { + rval.Available = available + if !available { + return + } + + _, b, c, d := cpuidex(0x8000001f, 0) + + rval.CBitPossition = b & 0x3f + rval.PhysAddrReduction = (b >> 6) & 0x3F + rval.NumVMPL = (b >> 12) & 0xf + rval.NumEntryptedGuests = c + rval.MinSevNoEsAsid = d + + return +} + func support() flagSet { var fs flagSet mfi := maxFunctionID() @@ -1165,6 +1482,7 @@ func support() flagSet { fs.setIf(ecx&(1<<10) != 0, VPCLMULQDQ) fs.setIf(ecx&(1<<13) != 0, TME) fs.setIf(ecx&(1<<25) != 0, CLDEMOTE) + fs.setIf(ecx&(1<<23) != 0, KEYLOCKER) fs.setIf(ecx&(1<<27) != 0, MOVDIRI) fs.setIf(ecx&(1<<28) != 0, MOVDIR64B) fs.setIf(ecx&(1<<29) != 0, ENQCMD) @@ -1190,10 +1508,13 @@ func support() flagSet { // CPUID.(EAX=7, ECX=1).EAX eax1, _, _, edx1 := cpuidex(7, 1) fs.setIf(fs.inSet(AVX) && eax1&(1<<4) != 0, AVXVNNI) + fs.setIf(eax1&(1<<1) != 0, SM3_X86) + fs.setIf(eax1&(1<<2) != 0, SM4_X86) fs.setIf(eax1&(1<<7) != 0, CMPCCXADD) fs.setIf(eax1&(1<<10) != 0, MOVSB_ZL) fs.setIf(eax1&(1<<11) != 0, STOSB_SHORT) fs.setIf(eax1&(1<<12) != 0, CMPSB_SCADBS_SHORT) + fs.setIf(eax1&(1<<17) != 0, FRED) fs.setIf(eax1&(1<<22) != 0, HRESET) fs.setIf(eax1&(1<<23) != 0, AVXIFMA) fs.setIf(eax1&(1<<26) != 0, LAM) @@ -1201,7 +1522,13 @@ func support() flagSet { // CPUID.(EAX=7, ECX=1).EDX fs.setIf(edx1&(1<<4) != 0, AVXVNNIINT8) fs.setIf(edx1&(1<<5) != 0, AVXNECONVERT) + fs.setIf(edx1&(1<<6) != 0, AMXTRANSPOSE) + fs.setIf(edx1&(1<<7) != 0, AMXTF32) + fs.setIf(edx1&(1<<8) != 0, AMXCOMPLEX) + fs.setIf(edx1&(1<<10) != 0, AVXVNNIINT16) fs.setIf(edx1&(1<<14) != 0, PREFETCHI) + fs.setIf(edx1&(1<<19) != 0, AVX10) + fs.setIf(edx1&(1<<21) != 0, APX_F) // Only detect AVX-512 features if XGETBV is supported if c&((1<<26)|(1<<27)) == (1<<26)|(1<<27) { @@ -1226,6 +1553,7 @@ func support() flagSet { fs.setIf(ebx&(1<<31) != 0, AVX512VL) // ecx fs.setIf(ecx&(1<<1) != 0, AVX512VBMI) + fs.setIf(ecx&(1<<3) != 0, AMXFP8) fs.setIf(ecx&(1<<6) != 0, AVX512VBMI2) fs.setIf(ecx&(1<<11) != 0, AVX512VNNI) fs.setIf(ecx&(1<<12) != 0, AVX512BITALG) @@ -1252,6 +1580,25 @@ func support() flagSet { fs.setIf(edx&(1<<4) != 0, BHI_CTRL) fs.setIf(edx&(1<<5) != 0, MCDT_NO) + if fs.inSet(SGX) { + eax, _, _, _ := cpuidex(0x12, 0) + fs.setIf(eax&(1<<12) != 0, SGXPQC) + } + + // Add keylocker features. + if fs.inSet(KEYLOCKER) && mfi >= 0x19 { + _, ebx, _, _ := cpuidex(0x19, 0) + fs.setIf(ebx&5 == 5, KEYLOCKERW) // Bit 0 and 2 (1+4) + } + + // Add AVX10 features. + if fs.inSet(AVX10) && mfi >= 0x24 { + _, ebx, _, _ := cpuidex(0x24, 0) + fs.setIf(ebx&(1<<16) != 0, AVX10_128) + fs.setIf(ebx&(1<<17) != 0, AVX10_256) + fs.setIf(ebx&(1<<18) != 0, AVX10_512) + } + } // Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1) @@ -1394,6 +1741,46 @@ func support() flagSet { fs.setIf((a>>24)&1 == 1, VMSA_REGPROT) } + if maxExtendedFunction() >= 0x80000021 && vend == AMD { + a, _, c, _ := cpuid(0x80000021) + fs.setIf((a>>31)&1 == 1, SRSO_MSR_FIX) + fs.setIf((a>>30)&1 == 1, SRSO_USER_KERNEL_NO) + fs.setIf((a>>29)&1 == 1, SRSO_NO) + fs.setIf((a>>28)&1 == 1, IBPB_BRTYPE) + fs.setIf((a>>27)&1 == 1, SBPB) + fs.setIf((a>>23)&1 == 1, AVX512BMM) + fs.setIf((c>>1)&1 == 1, TSA_L1_NO) + fs.setIf((c>>2)&1 == 1, TSA_SQ_NO) + fs.setIf((a>>5)&1 == 1, TSA_VERW_CLEAR) + } + if vend == AMD { + if family < 0x19 { + // AMD CPUs that are older than Family 19h are not vulnerable to TSA but do not set TSA_L1_NO or TSA_SQ_NO. + // Source: https://www.amd.com/content/dam/amd/en/documents/resources/bulletin/technical-guidance-for-mitigating-transient-scheduler-attacks.pdf + fs.set(TSA_L1_NO) + fs.set(TSA_SQ_NO) + } else if family == 0x1a { + // AMD Family 1Ah models 00h-4Fh and 60h-7Fh are also not vulnerable to TSA but do not set TSA_L1_NO or TSA_SQ_NO. + // Future AMD CPUs will set these CPUID bits if appropriate. CPUs will be designed to set these CPUID bits if appropriate. + notVuln := model <= 0x4f || (model >= 0x60 && model <= 0x7f) + fs.setIf(notVuln, TSA_L1_NO, TSA_SQ_NO) + } + } + + if mfi >= 0x20 { + // Microsoft has decided to purposefully hide the information + // of the guest TEE when VMs are being created using Hyper-V. + // + // This leads us to check for the Hyper-V cpuid features + // (0x4000000C), and then for the `ebx` value set. + // + // For Intel TDX, `ebx` is set as `0xbe3`, being 3 the part + // we're mostly interested about,according to: + // https://github.com/torvalds/linux/blob/d2f51b3516dade79269ff45eae2a7668ae711b25/arch/x86/include/asm/hyperv-tlfs.h#L169-L174 + _, ebx, _, _ := cpuid(0x4000000C) + fs.setIf(ebx == 0xbe3, TDX_GUEST) + } + if mfi >= 0x21 { // Intel Trusted Domain Extensions Guests have their own cpuid leaf (0x21). _, ebx, ecx, edx := cpuid(0x21) @@ -1404,6 +1791,14 @@ func support() flagSet { return fs } +func (c *CPUInfo) supportAVX10() uint8 { + if c.maxFunc >= 0x24 && c.featureSet.inSet(AVX10) { + _, ebx, _, _ := cpuidex(0x24, 0) + return uint8(ebx) + } + return 0 +} + func valAsString(values ...uint32) []byte { r := make([]byte, 4*len(values)) for i, v := range values { @@ -1425,3 +1820,47 @@ func valAsString(values ...uint32) []byte { } return r } + +func parseLeaf0AH(c *CPUInfo, eax, ebx, edx uint32) (info PerformanceMonitoringInfo) { + info.VersionID = uint8(eax & 0xFF) + info.NumGPCounters = uint8((eax >> 8) & 0xFF) + info.GPPMCWidth = uint8((eax >> 16) & 0xFF) + + info.RawEBX = ebx + info.RawEAX = eax + info.RawEDX = edx + + if info.VersionID > 1 { // This information is only valid if VersionID > 1 + info.NumFixedPMC = uint8(edx & 0x1F) // Bits 4:0 + info.FixedPMCWidth = uint8((edx >> 5) & 0xFF) // Bits 12:5 + } + if info.VersionID > 0 { + // first 4 fixed events are always instructions retired, cycles, ref cycles and topdown slots + if ebx == 0x0 && info.NumFixedPMC == 3 { + c.featureSet.set(PMU_FIXEDCOUNTER_INSTRUCTIONS) + c.featureSet.set(PMU_FIXEDCOUNTER_CYCLES) + c.featureSet.set(PMU_FIXEDCOUNTER_REFCYCLES) + } + if ebx == 0x0 && info.NumFixedPMC == 4 { + c.featureSet.set(PMU_FIXEDCOUNTER_INSTRUCTIONS) + c.featureSet.set(PMU_FIXEDCOUNTER_CYCLES) + c.featureSet.set(PMU_FIXEDCOUNTER_REFCYCLES) + c.featureSet.set(PMU_FIXEDCOUNTER_TOPDOWN_SLOTS) + } + if ebx != 0x0 { + if ((ebx >> 0) & 1) == 0 { + c.featureSet.set(PMU_FIXEDCOUNTER_INSTRUCTIONS) + } + if ((ebx >> 1) & 1) == 0 { + c.featureSet.set(PMU_FIXEDCOUNTER_CYCLES) + } + if ((ebx >> 2) & 1) == 0 { + c.featureSet.set(PMU_FIXEDCOUNTER_REFCYCLES) + } + if ((ebx >> 3) & 1) == 0 { + c.featureSet.set(PMU_FIXEDCOUNTER_TOPDOWN_SLOTS) + } + } + } + return info +} diff --git a/vendor/github.com/klauspost/cpuid/v2/cpuid_arm64.s b/vendor/github.com/klauspost/cpuid/v2/cpuid_arm64.s index b31d6aec4..b196f78eb 100644 --- a/vendor/github.com/klauspost/cpuid/v2/cpuid_arm64.s +++ b/vendor/github.com/klauspost/cpuid/v2/cpuid_arm64.s @@ -24,3 +24,13 @@ TEXT ·getInstAttributes(SB), 7, $0 MOVD R1, instAttrReg1+8(FP) RET +TEXT ·getVectorLength(SB), 7, $0 + WORD $0xd2800002 // mov x2, #0 + WORD $0x04225022 // addvl x2, x2, #1 + WORD $0xd37df042 // lsl x2, x2, #3 + WORD $0xd2800003 // mov x3, #0 + WORD $0x04635023 // addpl x3, x3, #1 + WORD $0xd37df063 // lsl x3, x3, #3 + MOVD R2, vl+0(FP) + MOVD R3, pl+8(FP) + RET diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go b/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go index 9a53504a0..e615b10be 100644 --- a/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go +++ b/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go @@ -1,7 +1,6 @@ // Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. //go:build arm64 && !gccgo && !noasm && !appengine -// +build arm64,!gccgo,!noasm,!appengine package cpuid @@ -10,6 +9,7 @@ import "runtime" func getMidr() (midr uint64) func getProcFeatures() (procFeatures uint64) func getInstAttributes() (instAttrReg0, instAttrReg1 uint64) +func getVectorLength() (vl, pl uint64) func initCPU() { cpuid = func(uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 } @@ -24,7 +24,7 @@ func addInfo(c *CPUInfo, safe bool) { detectOS(c) // ARM64 disabled since it may crash if interrupt is not intercepted by OS. - if safe && !c.Supports(ARMCPUID) && runtime.GOOS != "freebsd" { + if safe && !c.Has(ARMCPUID) && runtime.GOOS != "freebsd" { return } midr := getMidr() @@ -156,6 +156,10 @@ func addInfo(c *CPUInfo, safe bool) { // x--------------------------------------------------x // | Name | bits | visible | // |--------------------------------------------------| + // | RNDR | [63-60] | y | + // |--------------------------------------------------| + // | TLB | [59-56] | y | + // |--------------------------------------------------| // | TS | [55-52] | y | // |--------------------------------------------------| // | FHM | [51-48] | y | @@ -181,12 +185,11 @@ func addInfo(c *CPUInfo, safe bool) { // | AES | [7-4] | y | // x--------------------------------------------------x - // if instAttrReg0&(0xf<<52) != 0 { - // fmt.Println("TS") - // } - // if instAttrReg0&(0xf<<48) != 0 { - // fmt.Println("FHM") - // } + f.setIf(instAttrReg0&(0xf<<60) != 0, RNDR) + f.setIf(instAttrReg0&(0xf<<56) != 0, TLB) + f.setIf(instAttrReg0&(0xf<<52) != 0, TS) + f.setIf(instAttrReg0&(0xf<<52) == 2<<52, FLAGM2) // TS == 0b0010 (FEAT_FlagM2) + f.setIf(instAttrReg0&(0xf<<48) != 0, FHM) f.setIf(instAttrReg0&(0xf<<44) != 0, ASIMDDP) f.setIf(instAttrReg0&(0xf<<40) != 0, SM4) f.setIf(instAttrReg0&(0xf<<36) != 0, SM3) @@ -241,6 +244,13 @@ func addInfo(c *CPUInfo, safe bool) { // fmt.Println("APA") // } f.setIf(instAttrReg1&(0xf<<0) != 0, DCPOP) + f.setIf(instAttrReg1&(0xf<<0) == 2<<0, DCPODP) // DPB == 0b0010 (FEAT_DPB2) + + // Upper ID_AA64ISAR1_EL1 fields, not in the table above. + f.setIf(instAttrReg1&(0xf<<32) != 0, FRINTTS) // bits [35:32] + f.setIf(instAttrReg1&(0xf<<36) != 0, SB) // bits [39:36] + f.setIf(instAttrReg1&(0xf<<44) != 0, BF16) // bits [47:44] + f.setIf(instAttrReg1&(0xf<<52) != 0, I8MM) // bits [55:52] // Store c.featureSet.or(f) diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_ref.go b/vendor/github.com/klauspost/cpuid/v2/detect_ref.go index 9636c2bc1..38699f4d7 100644 --- a/vendor/github.com/klauspost/cpuid/v2/detect_ref.go +++ b/vendor/github.com/klauspost/cpuid/v2/detect_ref.go @@ -1,7 +1,6 @@ // Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. -//go:build (!amd64 && !386 && !arm64) || gccgo || noasm || appengine -// +build !amd64,!386,!arm64 gccgo noasm appengine +//go:build (!amd64 && !386 && !arm64 && !riscv64) || ((amd64 || 386) && (gccgo || noasm || appengine)) package cpuid @@ -10,6 +9,8 @@ func initCPU() { cpuidex = func(x, y uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 } xgetbv = func(uint32) (a, b uint32) { return 0, 0 } rdtscpAsm = func() (a, b, c, d uint32) { return 0, 0, 0, 0 } + } func addInfo(info *CPUInfo, safe bool) {} +func getVectorLength() (vl, pl uint64) { return 0, 0 } diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_ref_arm64.go b/vendor/github.com/klauspost/cpuid/v2/detect_ref_arm64.go new file mode 100644 index 000000000..d2ea76ba8 --- /dev/null +++ b/vendor/github.com/klauspost/cpuid/v2/detect_ref_arm64.go @@ -0,0 +1,19 @@ +// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. + +//go:build arm64 && (gccgo || noasm || appengine) + +package cpuid + +func initCPU() { + cpuid = func(uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 } + cpuidex = func(x, y uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 } + xgetbv = func(uint32) (a, b uint32) { return 0, 0 } + rdtscpAsm = func() (a, b, c, d uint32) { return 0, 0, 0, 0 } +} + +func addInfo(c *CPUInfo, safe bool) { + c.CacheLine = 64 + detectOS(c) +} + +func getVectorLength() (vl, pl uint64) { return 0, 0 } diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_riscv64.go b/vendor/github.com/klauspost/cpuid/v2/detect_riscv64.go new file mode 100644 index 000000000..25381f089 --- /dev/null +++ b/vendor/github.com/klauspost/cpuid/v2/detect_riscv64.go @@ -0,0 +1,16 @@ +// Copyright (c) 2026 Klaus Post, released under MIT License. See LICENSE file. + +package cpuid + +func getVectorLength() (vl, pl uint64) { return 0, 0 } + +func initCPU() { + cpuid = func(uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 } + cpuidex = func(x, y uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 } + xgetbv = func(uint32) (a, b uint32) { return 0, 0 } + rdtscpAsm = func() (a, b, c, d uint32) { return 0, 0, 0, 0 } +} + +func addInfo(c *CPUInfo, safe bool) { + detectOS(c) +} diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_x86.go b/vendor/github.com/klauspost/cpuid/v2/detect_x86.go index c946824ec..22819ce4a 100644 --- a/vendor/github.com/klauspost/cpuid/v2/detect_x86.go +++ b/vendor/github.com/klauspost/cpuid/v2/detect_x86.go @@ -1,7 +1,6 @@ // Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. //go:build (386 && !gccgo && !noasm && !appengine) || (amd64 && !gccgo && !noasm && !appengine) -// +build 386,!gccgo,!noasm,!appengine amd64,!gccgo,!noasm,!appengine package cpuid @@ -27,10 +26,19 @@ func addInfo(c *CPUInfo, safe bool) { c.Family, c.Model, c.Stepping = familyModel() c.featureSet = support() c.SGX = hasSGX(c.featureSet.inSet(SGX), c.featureSet.inSet(SGXLC)) + c.AMDMemEncryption = hasAMDMemEncryption(c.featureSet.inSet(SME) || c.featureSet.inSet(SEV)) c.ThreadsPerCore = threadsPerCore() c.LogicalCores = logicalCores() c.PhysicalCores = physicalCores() c.VendorID, c.VendorString = vendorID() + c.HypervisorVendorID, c.HypervisorVendorString = hypervisorVendorID() + c.AVX10Level = c.supportAVX10() c.cacheSize() c.frequencies() + if c.maxFunc >= 0x0A { + eax, ebx, _, edx := cpuid(0x0A) + c.PMU = parseLeaf0AH(c, eax, ebx, edx) + } } + +func getVectorLength() (vl, pl uint64) { return 0, 0 } diff --git a/vendor/github.com/klauspost/cpuid/v2/featureid_string.go b/vendor/github.com/klauspost/cpuid/v2/featureid_string.go index 024c706af..f88ead130 100644 --- a/vendor/github.com/klauspost/cpuid/v2/featureid_string.go +++ b/vendor/github.com/klauspost/cpuid/v2/featureid_string.go @@ -15,217 +15,306 @@ func _() { _ = x[AMXBF16-5] _ = x[AMXFP16-6] _ = x[AMXINT8-7] - _ = x[AMXTILE-8] - _ = x[AVX-9] - _ = x[AVX2-10] - _ = x[AVX512BF16-11] - _ = x[AVX512BITALG-12] - _ = x[AVX512BW-13] - _ = x[AVX512CD-14] - _ = x[AVX512DQ-15] - _ = x[AVX512ER-16] - _ = x[AVX512F-17] - _ = x[AVX512FP16-18] - _ = x[AVX512IFMA-19] - _ = x[AVX512PF-20] - _ = x[AVX512VBMI-21] - _ = x[AVX512VBMI2-22] - _ = x[AVX512VL-23] - _ = x[AVX512VNNI-24] - _ = x[AVX512VP2INTERSECT-25] - _ = x[AVX512VPOPCNTDQ-26] - _ = x[AVXIFMA-27] - _ = x[AVXNECONVERT-28] - _ = x[AVXSLOW-29] - _ = x[AVXVNNI-30] - _ = x[AVXVNNIINT8-31] - _ = x[BHI_CTRL-32] - _ = x[BMI1-33] - _ = x[BMI2-34] - _ = x[CETIBT-35] - _ = x[CETSS-36] - _ = x[CLDEMOTE-37] - _ = x[CLMUL-38] - _ = x[CLZERO-39] - _ = x[CMOV-40] - _ = x[CMPCCXADD-41] - _ = x[CMPSB_SCADBS_SHORT-42] - _ = x[CMPXCHG8-43] - _ = x[CPBOOST-44] - _ = x[CPPC-45] - _ = x[CX16-46] - _ = x[EFER_LMSLE_UNS-47] - _ = x[ENQCMD-48] - _ = x[ERMS-49] - _ = x[F16C-50] - _ = x[FLUSH_L1D-51] - _ = x[FMA3-52] - _ = x[FMA4-53] - _ = x[FP128-54] - _ = x[FP256-55] - _ = x[FSRM-56] - _ = x[FXSR-57] - _ = x[FXSROPT-58] - _ = x[GFNI-59] - _ = x[HLE-60] - _ = x[HRESET-61] - _ = x[HTT-62] - _ = x[HWA-63] - _ = x[HYBRID_CPU-64] - _ = x[HYPERVISOR-65] - _ = x[IA32_ARCH_CAP-66] - _ = x[IA32_CORE_CAP-67] - _ = x[IBPB-68] - _ = x[IBRS-69] - _ = x[IBRS_PREFERRED-70] - _ = x[IBRS_PROVIDES_SMP-71] - _ = x[IBS-72] - _ = x[IBSBRNTRGT-73] - _ = x[IBSFETCHSAM-74] - _ = x[IBSFFV-75] - _ = x[IBSOPCNT-76] - _ = x[IBSOPCNTEXT-77] - _ = x[IBSOPSAM-78] - _ = x[IBSRDWROPCNT-79] - _ = x[IBSRIPINVALIDCHK-80] - _ = x[IBS_FETCH_CTLX-81] - _ = x[IBS_OPDATA4-82] - _ = x[IBS_OPFUSE-83] - _ = x[IBS_PREVENTHOST-84] - _ = x[IBS_ZEN4-85] - _ = x[IDPRED_CTRL-86] - _ = x[INT_WBINVD-87] - _ = x[INVLPGB-88] - _ = x[LAHF-89] - _ = x[LAM-90] - _ = x[LBRVIRT-91] - _ = x[LZCNT-92] - _ = x[MCAOVERFLOW-93] - _ = x[MCDT_NO-94] - _ = x[MCOMMIT-95] - _ = x[MD_CLEAR-96] - _ = x[MMX-97] - _ = x[MMXEXT-98] - _ = x[MOVBE-99] - _ = x[MOVDIR64B-100] - _ = x[MOVDIRI-101] - _ = x[MOVSB_ZL-102] - _ = x[MOVU-103] - _ = x[MPX-104] - _ = x[MSRIRC-105] - _ = x[MSRLIST-106] - _ = x[MSR_PAGEFLUSH-107] - _ = x[NRIPS-108] - _ = x[NX-109] - _ = x[OSXSAVE-110] - _ = x[PCONFIG-111] - _ = x[POPCNT-112] - _ = x[PPIN-113] - _ = x[PREFETCHI-114] - _ = x[PSFD-115] - _ = x[RDPRU-116] - _ = x[RDRAND-117] - _ = x[RDSEED-118] - _ = x[RDTSCP-119] - _ = x[RRSBA_CTRL-120] - _ = x[RTM-121] - _ = x[RTM_ALWAYS_ABORT-122] - _ = x[SERIALIZE-123] - _ = x[SEV-124] - _ = x[SEV_64BIT-125] - _ = x[SEV_ALTERNATIVE-126] - _ = x[SEV_DEBUGSWAP-127] - _ = x[SEV_ES-128] - _ = x[SEV_RESTRICTED-129] - _ = x[SEV_SNP-130] - _ = x[SGX-131] - _ = x[SGXLC-132] - _ = x[SHA-133] - _ = x[SME-134] - _ = x[SME_COHERENT-135] - _ = x[SPEC_CTRL_SSBD-136] - _ = x[SRBDS_CTRL-137] - _ = x[SSE-138] - _ = x[SSE2-139] - _ = x[SSE3-140] - _ = x[SSE4-141] - _ = x[SSE42-142] - _ = x[SSE4A-143] - _ = x[SSSE3-144] - _ = x[STIBP-145] - _ = x[STIBP_ALWAYSON-146] - _ = x[STOSB_SHORT-147] - _ = x[SUCCOR-148] - _ = x[SVM-149] - _ = x[SVMDA-150] - _ = x[SVMFBASID-151] - _ = x[SVML-152] - _ = x[SVMNP-153] - _ = x[SVMPF-154] - _ = x[SVMPFT-155] - _ = x[SYSCALL-156] - _ = x[SYSEE-157] - _ = x[TBM-158] - _ = x[TDX_GUEST-159] - _ = x[TLB_FLUSH_NESTED-160] - _ = x[TME-161] - _ = x[TOPEXT-162] - _ = x[TSCRATEMSR-163] - _ = x[TSXLDTRK-164] - _ = x[VAES-165] - _ = x[VMCBCLEAN-166] - _ = x[VMPL-167] - _ = x[VMSA_REGPROT-168] - _ = x[VMX-169] - _ = x[VPCLMULQDQ-170] - _ = x[VTE-171] - _ = x[WAITPKG-172] - _ = x[WBNOINVD-173] - _ = x[WRMSRNS-174] - _ = x[X87-175] - _ = x[XGETBV1-176] - _ = x[XOP-177] - _ = x[XSAVE-178] - _ = x[XSAVEC-179] - _ = x[XSAVEOPT-180] - _ = x[XSAVES-181] - _ = x[AESARM-182] - _ = x[ARMCPUID-183] - _ = x[ASIMD-184] - _ = x[ASIMDDP-185] - _ = x[ASIMDHP-186] - _ = x[ASIMDRDM-187] - _ = x[ATOMICS-188] - _ = x[CRC32-189] - _ = x[DCPOP-190] - _ = x[EVTSTRM-191] - _ = x[FCMA-192] - _ = x[FP-193] - _ = x[FPHP-194] - _ = x[GPA-195] - _ = x[JSCVT-196] - _ = x[LRCPC-197] - _ = x[PMULL-198] - _ = x[SHA1-199] - _ = x[SHA2-200] - _ = x[SHA3-201] - _ = x[SHA512-202] - _ = x[SM3-203] - _ = x[SM4-204] - _ = x[SVE-205] - _ = x[lastID-206] + _ = x[AMXFP8-8] + _ = x[AMXTILE-9] + _ = x[AMXTF32-10] + _ = x[AMXCOMPLEX-11] + _ = x[AMXTRANSPOSE-12] + _ = x[APX_F-13] + _ = x[AVX-14] + _ = x[AVX10-15] + _ = x[AVX10_128-16] + _ = x[AVX10_256-17] + _ = x[AVX10_512-18] + _ = x[AVX2-19] + _ = x[AVX512BF16-20] + _ = x[AVX512BITALG-21] + _ = x[AVX512BMM-22] + _ = x[AVX512BW-23] + _ = x[AVX512CD-24] + _ = x[AVX512DQ-25] + _ = x[AVX512ER-26] + _ = x[AVX512F-27] + _ = x[AVX512FP16-28] + _ = x[AVX512IFMA-29] + _ = x[AVX512PF-30] + _ = x[AVX512VBMI-31] + _ = x[AVX512VBMI2-32] + _ = x[AVX512VL-33] + _ = x[AVX512VNNI-34] + _ = x[AVX512VP2INTERSECT-35] + _ = x[AVX512VPOPCNTDQ-36] + _ = x[AVXIFMA-37] + _ = x[AVXNECONVERT-38] + _ = x[AVXSLOW-39] + _ = x[AVXVNNI-40] + _ = x[AVXVNNIINT8-41] + _ = x[AVXVNNIINT16-42] + _ = x[BHI_CTRL-43] + _ = x[BMI1-44] + _ = x[BMI2-45] + _ = x[CETIBT-46] + _ = x[CETSS-47] + _ = x[CLDEMOTE-48] + _ = x[CLMUL-49] + _ = x[CLZERO-50] + _ = x[CMOV-51] + _ = x[CMPCCXADD-52] + _ = x[CMPSB_SCADBS_SHORT-53] + _ = x[CMPXCHG8-54] + _ = x[CPBOOST-55] + _ = x[CPPC-56] + _ = x[CX16-57] + _ = x[EFER_LMSLE_UNS-58] + _ = x[ENQCMD-59] + _ = x[ERMS-60] + _ = x[F16C-61] + _ = x[FLUSH_L1D-62] + _ = x[FMA3-63] + _ = x[FMA4-64] + _ = x[FP128-65] + _ = x[FP256-66] + _ = x[FRED-67] + _ = x[FSRM-68] + _ = x[FXSR-69] + _ = x[FXSROPT-70] + _ = x[GFNI-71] + _ = x[HLE-72] + _ = x[HRESET-73] + _ = x[HTT-74] + _ = x[HWA-75] + _ = x[HYBRID_CPU-76] + _ = x[HYPERVISOR-77] + _ = x[IA32_ARCH_CAP-78] + _ = x[IA32_CORE_CAP-79] + _ = x[IBPB-80] + _ = x[IBPB_BRTYPE-81] + _ = x[IBRS-82] + _ = x[IBRS_PREFERRED-83] + _ = x[IBRS_PROVIDES_SMP-84] + _ = x[IBS-85] + _ = x[IBSBRNTRGT-86] + _ = x[IBSFETCHSAM-87] + _ = x[IBSFFV-88] + _ = x[IBSOPCNT-89] + _ = x[IBSOPCNTEXT-90] + _ = x[IBSOPSAM-91] + _ = x[IBSRDWROPCNT-92] + _ = x[IBSRIPINVALIDCHK-93] + _ = x[IBS_FETCH_CTLX-94] + _ = x[IBS_OPDATA4-95] + _ = x[IBS_OPFUSE-96] + _ = x[IBS_PREVENTHOST-97] + _ = x[IBS_ZEN4-98] + _ = x[IDPRED_CTRL-99] + _ = x[INT_WBINVD-100] + _ = x[INVLPGB-101] + _ = x[KEYLOCKER-102] + _ = x[KEYLOCKERW-103] + _ = x[LAHF-104] + _ = x[LAM-105] + _ = x[LBRVIRT-106] + _ = x[LZCNT-107] + _ = x[MCAOVERFLOW-108] + _ = x[MCDT_NO-109] + _ = x[MCOMMIT-110] + _ = x[MD_CLEAR-111] + _ = x[MMX-112] + _ = x[MMXEXT-113] + _ = x[MOVBE-114] + _ = x[MOVDIR64B-115] + _ = x[MOVDIRI-116] + _ = x[MOVSB_ZL-117] + _ = x[MOVU-118] + _ = x[MPX-119] + _ = x[MSRIRC-120] + _ = x[MSRLIST-121] + _ = x[MSR_PAGEFLUSH-122] + _ = x[NRIPS-123] + _ = x[NX-124] + _ = x[OSXSAVE-125] + _ = x[PCONFIG-126] + _ = x[POPCNT-127] + _ = x[PPIN-128] + _ = x[PREFETCHI-129] + _ = x[PSFD-130] + _ = x[RDPRU-131] + _ = x[RDRAND-132] + _ = x[RDSEED-133] + _ = x[RDTSCP-134] + _ = x[RRSBA_CTRL-135] + _ = x[RTM-136] + _ = x[RTM_ALWAYS_ABORT-137] + _ = x[SBPB-138] + _ = x[SERIALIZE-139] + _ = x[SEV-140] + _ = x[SEV_64BIT-141] + _ = x[SEV_ALTERNATIVE-142] + _ = x[SEV_DEBUGSWAP-143] + _ = x[SEV_ES-144] + _ = x[SEV_RESTRICTED-145] + _ = x[SEV_SNP-146] + _ = x[SGX-147] + _ = x[SGXLC-148] + _ = x[SGXPQC-149] + _ = x[SHA-150] + _ = x[SME-151] + _ = x[SME_COHERENT-152] + _ = x[SM3_X86-153] + _ = x[SM4_X86-154] + _ = x[SPEC_CTRL_SSBD-155] + _ = x[SRBDS_CTRL-156] + _ = x[SRSO_MSR_FIX-157] + _ = x[SRSO_NO-158] + _ = x[SRSO_USER_KERNEL_NO-159] + _ = x[SSE-160] + _ = x[SSE2-161] + _ = x[SSE3-162] + _ = x[SSE4-163] + _ = x[SSE42-164] + _ = x[SSE4A-165] + _ = x[SSSE3-166] + _ = x[STIBP-167] + _ = x[STIBP_ALWAYSON-168] + _ = x[STOSB_SHORT-169] + _ = x[SUCCOR-170] + _ = x[SVM-171] + _ = x[SVMDA-172] + _ = x[SVMFBASID-173] + _ = x[SVML-174] + _ = x[SVMNP-175] + _ = x[SVMPF-176] + _ = x[SVMPFT-177] + _ = x[SYSCALL-178] + _ = x[SYSEE-179] + _ = x[TBM-180] + _ = x[TDX_GUEST-181] + _ = x[TLB_FLUSH_NESTED-182] + _ = x[TME-183] + _ = x[TOPEXT-184] + _ = x[TSA_L1_NO-185] + _ = x[TSA_SQ_NO-186] + _ = x[TSA_VERW_CLEAR-187] + _ = x[TSCRATEMSR-188] + _ = x[TSXLDTRK-189] + _ = x[VAES-190] + _ = x[VMCBCLEAN-191] + _ = x[VMPL-192] + _ = x[VMSA_REGPROT-193] + _ = x[VMX-194] + _ = x[VPCLMULQDQ-195] + _ = x[VTE-196] + _ = x[WAITPKG-197] + _ = x[WBNOINVD-198] + _ = x[WRMSRNS-199] + _ = x[X87-200] + _ = x[XGETBV1-201] + _ = x[XOP-202] + _ = x[XSAVE-203] + _ = x[XSAVEC-204] + _ = x[XSAVEOPT-205] + _ = x[XSAVES-206] + _ = x[AESARM-207] + _ = x[ARMCPUID-208] + _ = x[ASIMD-209] + _ = x[ASIMDDP-210] + _ = x[ASIMDHP-211] + _ = x[ASIMDRDM-212] + _ = x[ATOMICS-213] + _ = x[CRC32-214] + _ = x[DCPOP-215] + _ = x[EVTSTRM-216] + _ = x[FCMA-217] + _ = x[FHM-218] + _ = x[FP-219] + _ = x[FPHP-220] + _ = x[GPA-221] + _ = x[JSCVT-222] + _ = x[LRCPC-223] + _ = x[PMULL-224] + _ = x[RNDR-225] + _ = x[TLB-226] + _ = x[TS-227] + _ = x[SHA1-228] + _ = x[SHA2-229] + _ = x[SHA3-230] + _ = x[SHA512-231] + _ = x[SM3-232] + _ = x[SM4-233] + _ = x[SVE-234] + _ = x[SVE2-235] + _ = x[SB-236] + _ = x[SSBS-237] + _ = x[BTI-238] + _ = x[FLAGM2-239] + _ = x[FRINTTS-240] + _ = x[DCPODP-241] + _ = x[BF16-242] + _ = x[I8MM-243] + _ = x[WFXT-244] + _ = x[MOPS-245] + _ = x[HBC-246] + _ = x[CSSC-247] + _ = x[PMU_FIXEDCOUNTER_CYCLES-248] + _ = x[PMU_FIXEDCOUNTER_REFCYCLES-249] + _ = x[PMU_FIXEDCOUNTER_INSTRUCTIONS-250] + _ = x[PMU_FIXEDCOUNTER_TOPDOWN_SLOTS-251] + _ = x[RV_IMA-252] + _ = x[RV_C-253] + _ = x[RV_F-254] + _ = x[RV_D-255] + _ = x[RV_V-256] + _ = x[RV_ZBA-257] + _ = x[RV_ZBB-258] + _ = x[RV_ZBC-259] + _ = x[RV_ZBS-260] + _ = x[RV_ZICOND-261] + _ = x[RV_ZIHINTPAUSE-262] + _ = x[RV_ZICBOM-263] + _ = x[RV_ZICBOZ-264] + _ = x[RV_ZICBOP-265] + _ = x[RV_ZFA-266] + _ = x[RV_ZFH-267] + _ = x[RV_ZFHMIN-268] + _ = x[RV_ZTSO-269] + _ = x[RV_ZACAS-270] + _ = x[RV_ZBKB-271] + _ = x[RV_ZBKC-272] + _ = x[RV_ZBKX-273] + _ = x[RV_ZKND-274] + _ = x[RV_ZKNE-275] + _ = x[RV_ZKNH-276] + _ = x[RV_ZKSED-277] + _ = x[RV_ZKSH-278] + _ = x[RV_ZKT-279] + _ = x[RV_ZKN-280] + _ = x[RV_ZKS-281] + _ = x[RV_ZVBB-282] + _ = x[RV_ZVBC-283] + _ = x[RV_ZVKB-284] + _ = x[RV_ZVKG-285] + _ = x[RV_ZVKNED-286] + _ = x[RV_ZVKNHA-287] + _ = x[RV_ZVKNHB-288] + _ = x[RV_ZVKSED-289] + _ = x[RV_ZVKSH-290] + _ = x[RV_ZVKT-291] + _ = x[RV_ZVKNG-292] + _ = x[RV_ZVKSG-293] + _ = x[lastID-294] _ = x[firstID-0] } -const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXFP16AMXINT8AMXTILEAVXAVX2AVX512BF16AVX512BITALGAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXIFMAAVXNECONVERTAVXSLOWAVXVNNIAVXVNNIINT8BHI_CTRLBMI1BMI2CETIBTCETSSCLDEMOTECLMULCLZEROCMOVCMPCCXADDCMPSB_SCADBS_SHORTCMPXCHG8CPBOOSTCPPCCX16EFER_LMSLE_UNSENQCMDERMSF16CFLUSH_L1DFMA3FMA4FP128FP256FSRMFXSRFXSROPTGFNIHLEHRESETHTTHWAHYBRID_CPUHYPERVISORIA32_ARCH_CAPIA32_CORE_CAPIBPBIBRSIBRS_PREFERREDIBRS_PROVIDES_SMPIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKIBS_FETCH_CTLXIBS_OPDATA4IBS_OPFUSEIBS_PREVENTHOSTIBS_ZEN4IDPRED_CTRLINT_WBINVDINVLPGBLAHFLAMLBRVIRTLZCNTMCAOVERFLOWMCDT_NOMCOMMITMD_CLEARMMXMMXEXTMOVBEMOVDIR64BMOVDIRIMOVSB_ZLMOVUMPXMSRIRCMSRLISTMSR_PAGEFLUSHNRIPSNXOSXSAVEPCONFIGPOPCNTPPINPREFETCHIPSFDRDPRURDRANDRDSEEDRDTSCPRRSBA_CTRLRTMRTM_ALWAYS_ABORTSERIALIZESEVSEV_64BITSEV_ALTERNATIVESEV_DEBUGSWAPSEV_ESSEV_RESTRICTEDSEV_SNPSGXSGXLCSHASMESME_COHERENTSPEC_CTRL_SSBDSRBDS_CTRLSSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSTIBP_ALWAYSONSTOSB_SHORTSUCCORSVMSVMDASVMFBASIDSVMLSVMNPSVMPFSVMPFTSYSCALLSYSEETBMTDX_GUESTTLB_FLUSH_NESTEDTMETOPEXTTSCRATEMSRTSXLDTRKVAESVMCBCLEANVMPLVMSA_REGPROTVMXVPCLMULQDQVTEWAITPKGWBNOINVDWRMSRNSX87XGETBV1XOPXSAVEXSAVECXSAVEOPTXSAVESAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFPFPHPGPAJSCVTLRCPCPMULLSHA1SHA2SHA3SHA512SM3SM4SVElastID" +const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXFP16AMXINT8AMXFP8AMXTILEAMXTF32AMXCOMPLEXAMXTRANSPOSEAPX_FAVXAVX10AVX10_128AVX10_256AVX10_512AVX2AVX512BF16AVX512BITALGAVX512BMMAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXIFMAAVXNECONVERTAVXSLOWAVXVNNIAVXVNNIINT8AVXVNNIINT16BHI_CTRLBMI1BMI2CETIBTCETSSCLDEMOTECLMULCLZEROCMOVCMPCCXADDCMPSB_SCADBS_SHORTCMPXCHG8CPBOOSTCPPCCX16EFER_LMSLE_UNSENQCMDERMSF16CFLUSH_L1DFMA3FMA4FP128FP256FREDFSRMFXSRFXSROPTGFNIHLEHRESETHTTHWAHYBRID_CPUHYPERVISORIA32_ARCH_CAPIA32_CORE_CAPIBPBIBPB_BRTYPEIBRSIBRS_PREFERREDIBRS_PROVIDES_SMPIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKIBS_FETCH_CTLXIBS_OPDATA4IBS_OPFUSEIBS_PREVENTHOSTIBS_ZEN4IDPRED_CTRLINT_WBINVDINVLPGBKEYLOCKERKEYLOCKERWLAHFLAMLBRVIRTLZCNTMCAOVERFLOWMCDT_NOMCOMMITMD_CLEARMMXMMXEXTMOVBEMOVDIR64BMOVDIRIMOVSB_ZLMOVUMPXMSRIRCMSRLISTMSR_PAGEFLUSHNRIPSNXOSXSAVEPCONFIGPOPCNTPPINPREFETCHIPSFDRDPRURDRANDRDSEEDRDTSCPRRSBA_CTRLRTMRTM_ALWAYS_ABORTSBPBSERIALIZESEVSEV_64BITSEV_ALTERNATIVESEV_DEBUGSWAPSEV_ESSEV_RESTRICTEDSEV_SNPSGXSGXLCSGXPQCSHASMESME_COHERENTSM3_X86SM4_X86SPEC_CTRL_SSBDSRBDS_CTRLSRSO_MSR_FIXSRSO_NOSRSO_USER_KERNEL_NOSSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSTIBP_ALWAYSONSTOSB_SHORTSUCCORSVMSVMDASVMFBASIDSVMLSVMNPSVMPFSVMPFTSYSCALLSYSEETBMTDX_GUESTTLB_FLUSH_NESTEDTMETOPEXTTSA_L1_NOTSA_SQ_NOTSA_VERW_CLEARTSCRATEMSRTSXLDTRKVAESVMCBCLEANVMPLVMSA_REGPROTVMXVPCLMULQDQVTEWAITPKGWBNOINVDWRMSRNSX87XGETBV1XOPXSAVEXSAVECXSAVEOPTXSAVESAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFHMFPFPHPGPAJSCVTLRCPCPMULLRNDRTLBTSSHA1SHA2SHA3SHA512SM3SM4SVESVE2SBSSBSBTIFLAGM2FRINTTSDCPODPBF16I8MMWFXTMOPSHBCCSSCPMU_FIXEDCOUNTER_CYCLESPMU_FIXEDCOUNTER_REFCYCLESPMU_FIXEDCOUNTER_INSTRUCTIONSPMU_FIXEDCOUNTER_TOPDOWN_SLOTSRV_IMARV_CRV_FRV_DRV_VRV_ZBARV_ZBBRV_ZBCRV_ZBSRV_ZICONDRV_ZIHINTPAUSERV_ZICBOMRV_ZICBOZRV_ZICBOPRV_ZFARV_ZFHRV_ZFHMINRV_ZTSORV_ZACASRV_ZBKBRV_ZBKCRV_ZBKXRV_ZKNDRV_ZKNERV_ZKNHRV_ZKSEDRV_ZKSHRV_ZKTRV_ZKNRV_ZKSRV_ZVBBRV_ZVBCRV_ZVKBRV_ZVKGRV_ZVKNEDRV_ZVKNHARV_ZVKNHBRV_ZVKSEDRV_ZVKSHRV_ZVKTRV_ZVKNGRV_ZVKSGlastID" -var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 62, 65, 69, 79, 91, 99, 107, 115, 123, 130, 140, 150, 158, 168, 179, 187, 197, 215, 230, 237, 249, 256, 263, 274, 282, 286, 290, 296, 301, 309, 314, 320, 324, 333, 351, 359, 366, 370, 374, 388, 394, 398, 402, 411, 415, 419, 424, 429, 433, 437, 444, 448, 451, 457, 460, 463, 473, 483, 496, 509, 513, 517, 531, 548, 551, 561, 572, 578, 586, 597, 605, 617, 633, 647, 658, 668, 683, 691, 702, 712, 719, 723, 726, 733, 738, 749, 756, 763, 771, 774, 780, 785, 794, 801, 809, 813, 816, 822, 829, 842, 847, 849, 856, 863, 869, 873, 882, 886, 891, 897, 903, 909, 919, 922, 938, 947, 950, 959, 974, 987, 993, 1007, 1014, 1017, 1022, 1025, 1028, 1040, 1054, 1064, 1067, 1071, 1075, 1079, 1084, 1089, 1094, 1099, 1113, 1124, 1130, 1133, 1138, 1147, 1151, 1156, 1161, 1167, 1174, 1179, 1182, 1191, 1207, 1210, 1216, 1226, 1234, 1238, 1247, 1251, 1263, 1266, 1276, 1279, 1286, 1294, 1301, 1304, 1311, 1314, 1319, 1325, 1333, 1339, 1345, 1353, 1358, 1365, 1372, 1380, 1387, 1392, 1397, 1404, 1408, 1410, 1414, 1417, 1422, 1427, 1432, 1436, 1440, 1444, 1450, 1453, 1456, 1459, 1465} +var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 61, 68, 75, 85, 97, 102, 105, 110, 119, 128, 137, 141, 151, 163, 172, 180, 188, 196, 204, 211, 221, 231, 239, 249, 260, 268, 278, 296, 311, 318, 330, 337, 344, 355, 367, 375, 379, 383, 389, 394, 402, 407, 413, 417, 426, 444, 452, 459, 463, 467, 481, 487, 491, 495, 504, 508, 512, 517, 522, 526, 530, 534, 541, 545, 548, 554, 557, 560, 570, 580, 593, 606, 610, 621, 625, 639, 656, 659, 669, 680, 686, 694, 705, 713, 725, 741, 755, 766, 776, 791, 799, 810, 820, 827, 836, 846, 850, 853, 860, 865, 876, 883, 890, 898, 901, 907, 912, 921, 928, 936, 940, 943, 949, 956, 969, 974, 976, 983, 990, 996, 1000, 1009, 1013, 1018, 1024, 1030, 1036, 1046, 1049, 1065, 1069, 1078, 1081, 1090, 1105, 1118, 1124, 1138, 1145, 1148, 1153, 1159, 1162, 1165, 1177, 1184, 1191, 1205, 1215, 1227, 1234, 1253, 1256, 1260, 1264, 1268, 1273, 1278, 1283, 1288, 1302, 1313, 1319, 1322, 1327, 1336, 1340, 1345, 1350, 1356, 1363, 1368, 1371, 1380, 1396, 1399, 1405, 1414, 1423, 1437, 1447, 1455, 1459, 1468, 1472, 1484, 1487, 1497, 1500, 1507, 1515, 1522, 1525, 1532, 1535, 1540, 1546, 1554, 1560, 1566, 1574, 1579, 1586, 1593, 1601, 1608, 1613, 1618, 1625, 1629, 1632, 1634, 1638, 1641, 1646, 1651, 1656, 1660, 1663, 1665, 1669, 1673, 1677, 1683, 1686, 1689, 1692, 1696, 1698, 1702, 1705, 1711, 1718, 1724, 1728, 1732, 1736, 1740, 1743, 1747, 1770, 1796, 1825, 1855, 1861, 1865, 1869, 1873, 1877, 1883, 1889, 1895, 1901, 1910, 1924, 1933, 1942, 1951, 1957, 1963, 1972, 1979, 1987, 1994, 2001, 2008, 2015, 2022, 2029, 2037, 2044, 2050, 2056, 2062, 2069, 2076, 2083, 2090, 2099, 2108, 2117, 2126, 2134, 2141, 2149, 2157, 2163} func (i FeatureID) String() string { - if i < 0 || i >= FeatureID(len(_FeatureID_index)-1) { + idx := int(i) - 0 + if i < 0 || idx >= len(_FeatureID_index)-1 { return "FeatureID(" + strconv.FormatInt(int64(i), 10) + ")" } - return _FeatureID_name[_FeatureID_index[i]:_FeatureID_index[i+1]] + return _FeatureID_name[_FeatureID_index[idx]:_FeatureID_index[idx+1]] } func _() { // An "invalid array index" compiler error signifies that the constant values have changed. @@ -257,16 +346,27 @@ func _() { _ = x[AMCC-23] _ = x[Qualcomm-24] _ = x[Marvell-25] - _ = x[lastVendor-26] + _ = x[QEMU-26] + _ = x[QNX-27] + _ = x[ACRN-28] + _ = x[SRE-29] + _ = x[Apple-30] + _ = x[SiFive-31] + _ = x[StarFive-32] + _ = x[THead-33] + _ = x[Andes-34] + _ = x[SpacemiT-35] + _ = x[lastVendor-36] } -const _Vendor_name = "VendorUnknownIntelAMDVIATransmetaNSCKVMMSVMVMwareXenHVMBhyveHygonSiSRDCAmpereARMBroadcomCaviumDECFujitsuInfineonMotorolaNVIDIAAMCCQualcommMarvelllastVendor" +const _Vendor_name = "VendorUnknownIntelAMDVIATransmetaNSCKVMMSVMVMwareXenHVMBhyveHygonSiSRDCAmpereARMBroadcomCaviumDECFujitsuInfineonMotorolaNVIDIAAMCCQualcommMarvellQEMUQNXACRNSREAppleSiFiveStarFiveTHeadAndesSpacemiTlastVendor" -var _Vendor_index = [...]uint8{0, 13, 18, 21, 24, 33, 36, 39, 43, 49, 55, 60, 65, 68, 71, 77, 80, 88, 94, 97, 104, 112, 120, 126, 130, 138, 145, 155} +var _Vendor_index = [...]uint8{0, 13, 18, 21, 24, 33, 36, 39, 43, 49, 55, 60, 65, 68, 71, 77, 80, 88, 94, 97, 104, 112, 120, 126, 130, 138, 145, 149, 152, 156, 159, 164, 170, 178, 183, 188, 196, 206} func (i Vendor) String() string { - if i < 0 || i >= Vendor(len(_Vendor_index)-1) { + idx := int(i) - 0 + if i < 0 || idx >= len(_Vendor_index)-1 { return "Vendor(" + strconv.FormatInt(int64(i), 10) + ")" } - return _Vendor_name[_Vendor_index[i]:_Vendor_index[i+1]] + return _Vendor_name[_Vendor_index[idx]:_Vendor_index[idx+1]] } diff --git a/vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go index 84b1acd21..addbfc67b 100644 --- a/vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go +++ b/vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go @@ -65,9 +65,16 @@ func sysctlGetInt64(unknown int, names ...string) int { return unknown } -func setFeature(c *CPUInfo, name string, feature FeatureID) { - c.featureSet.setIf(sysctlGetBool(name), feature) +func setFeature(c *CPUInfo, feature FeatureID, aliases ...string) { + for _, alias := range aliases { + set := sysctlGetBool(alias) + c.featureSet.setIf(set, feature) + if set { + break + } + } } + func tryToFillCPUInfoFomSysctl(c *CPUInfo) { c.BrandName = sysctlGetString("machdep.cpu.brand_string") @@ -87,35 +94,49 @@ func tryToFillCPUInfoFomSysctl(c *CPUInfo) { c.Cache.L2 = sysctlGetInt64(-1, "hw.l2cachesize") c.Cache.L3 = sysctlGetInt64(-1, "hw.l3cachesize") - // from https://developer.arm.com/downloads/-/exploration-tools/feature-names-for-a-profile - setFeature(c, "hw.optional.arm.FEAT_AES", AESARM) - setFeature(c, "hw.optional.AdvSIMD", ASIMD) - setFeature(c, "hw.optional.arm.FEAT_DotProd", ASIMDDP) - setFeature(c, "hw.optional.arm.FEAT_RDM", ASIMDRDM) - setFeature(c, "hw.optional.FEAT_CRC32", CRC32) - setFeature(c, "hw.optional.arm.FEAT_DPB", DCPOP) - // setFeature(c, "", EVTSTRM) - setFeature(c, "hw.optional.arm.FEAT_FCMA", FCMA) - setFeature(c, "hw.optional.arm.FEAT_FP", FP) - setFeature(c, "hw.optional.arm.FEAT_FP16", FPHP) - setFeature(c, "hw.optional.arm.FEAT_PAuth", GPA) - setFeature(c, "hw.optional.arm.FEAT_JSCVT", JSCVT) - setFeature(c, "hw.optional.arm.FEAT_LRCPC", LRCPC) - setFeature(c, "hw.optional.arm.FEAT_PMULL", PMULL) - setFeature(c, "hw.optional.arm.FEAT_SHA1", SHA1) - setFeature(c, "hw.optional.arm.FEAT_SHA256", SHA2) - setFeature(c, "hw.optional.arm.FEAT_SHA3", SHA3) - setFeature(c, "hw.optional.arm.FEAT_SHA512", SHA512) - // setFeature(c, "", SM3) - // setFeature(c, "", SM4) - setFeature(c, "hw.optional.arm.FEAT_SVE", SVE) - - // from empirical observation - setFeature(c, "hw.optional.AdvSIMD_HPFPCvt", ASIMDHP) - setFeature(c, "hw.optional.armv8_1_atomics", ATOMICS) - setFeature(c, "hw.optional.floatingpoint", FP) - setFeature(c, "hw.optional.armv8_2_sha3", SHA3) - setFeature(c, "hw.optional.armv8_2_sha512", SHA512) - setFeature(c, "hw.optional.armv8_3_compnum", FCMA) - setFeature(c, "hw.optional.armv8_crc32", CRC32) + // ARM features: + // + // Note: On some Apple Silicon system, some feats have aliases. See: + // https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_instruction_set_characteristics + // When so, we look at all aliases and consider a feature available when at least one identifier matches. + setFeature(c, AESARM, "hw.optional.arm.FEAT_AES") // AES instructions + setFeature(c, ASIMD, "hw.optional.arm.AdvSIMD", "hw.optional.neon") // Advanced SIMD + setFeature(c, ASIMDDP, "hw.optional.arm.FEAT_DotProd") // SIMD Dot Product + setFeature(c, ASIMDHP, "hw.optional.arm.AdvSIMD_HPFPCvt", "hw.optional.neon_hpfp") // Advanced SIMD half-precision floating point + setFeature(c, ASIMDRDM, "hw.optional.arm.FEAT_RDM") // Rounding Double Multiply Accumulate/Subtract + setFeature(c, ATOMICS, "hw.optional.arm.FEAT_LSE", "hw.optional.armv8_1_atomics") // Large System Extensions (LSE) + setFeature(c, CRC32, "hw.optional.arm.FEAT_CRC32", "hw.optional.armv8_crc32") // CRC32/CRC32C instructions + setFeature(c, DCPOP, "hw.optional.arm.FEAT_DPB") // Data cache clean to Point of Persistence (DC CVAP) + setFeature(c, EVTSTRM, "hw.optional.arm.FEAT_ECV") // Generic timer + setFeature(c, FCMA, "hw.optional.arm.FEAT_FCMA", "hw.optional.armv8_3_compnum") // Floating point complex number addition and multiplication + setFeature(c, FHM, "hw.optional.armv8_2_fhm", "hw.optional.arm.FEAT_FHM") // FMLAL and FMLSL instructions + setFeature(c, FP, "hw.optional.floatingpoint") // Single-precision and double-precision floating point + setFeature(c, FPHP, "hw.optional.arm.FEAT_FP16", "hw.optional.neon_fp16") // Half-precision floating point + setFeature(c, GPA, "hw.optional.arm.FEAT_PAuth") // Generic Pointer Authentication + setFeature(c, JSCVT, "hw.optional.arm.FEAT_JSCVT") // Javascript-style double->int convert (FJCVTZS) + setFeature(c, LRCPC, "hw.optional.arm.FEAT_LRCPC") // Weaker release consistency (LDAPR, etc) + setFeature(c, PMULL, "hw.optional.arm.FEAT_PMULL") // Polynomial Multiply instructions (PMULL/PMULL2) + setFeature(c, RNDR, "hw.optional.arm.FEAT_RNG") // Random Number instructions + setFeature(c, TLB, "hw.optional.arm.FEAT_TLBIOS", "hw.optional.arm.FEAT_TLBIRANGE") // Outer Shareable and TLB range maintenance instructions + setFeature(c, TS, "hw.optional.arm.FEAT_FlagM", "hw.optional.arm.FEAT_FlagM2") // Flag manipulation instructions + setFeature(c, SHA1, "hw.optional.arm.FEAT_SHA1") // SHA-1 instructions (SHA1C, etc) + setFeature(c, SHA2, "hw.optional.arm.FEAT_SHA256") // SHA-2 instructions (SHA256H, etc) + setFeature(c, SHA3, "hw.optional.arm.FEAT_SHA3") // SHA-3 instructions (EOR3, RAXI, XAR, BCAX) + setFeature(c, SHA512, "hw.optional.arm.FEAT_SHA512") // SHA512 instructions + setFeature(c, SM3, "hw.optional.arm.FEAT_SM3") // SM3 instructions + setFeature(c, SM4, "hw.optional.arm.FEAT_SM4") // SM4 instructions + setFeature(c, SVE, "hw.optional.arm.FEAT_SVE") // Scalable Vector Extension + setFeature(c, SVE2, "hw.optional.arm.FEAT_SVE2") // Scalable Vector Extension 2 + setFeature(c, SB, "hw.optional.arm.FEAT_SB") // Speculation barrier + setFeature(c, SSBS, "hw.optional.arm.FEAT_SSBS") // Speculative Store Bypass Safe + setFeature(c, BTI, "hw.optional.arm.FEAT_BTI") // Branch Target Identification + setFeature(c, FLAGM2, "hw.optional.arm.FEAT_FlagM2") // Condition flag manipulation version 2 + setFeature(c, FRINTTS, "hw.optional.arm.FEAT_FRINTTS") // Floating-point to integer rounding + setFeature(c, DCPODP, "hw.optional.arm.FEAT_DPB2") // Data cache clean to Point of Deep Persistence + setFeature(c, BF16, "hw.optional.arm.FEAT_BF16") // BFloat16 instructions + setFeature(c, I8MM, "hw.optional.arm.FEAT_I8MM") // Int8 matrix multiplication + setFeature(c, WFXT, "hw.optional.arm.FEAT_WFxT") // WFE/WFI with timeout + setFeature(c, MOPS, "hw.optional.arm.FEAT_MOPS") // Memory copy and set instructions + setFeature(c, HBC, "hw.optional.arm.FEAT_HBC") // Hinted conditional branches + setFeature(c, CSSC, "hw.optional.arm.FEAT_CSSC") // Common short sequence compression } diff --git a/vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go index ee278b9e4..ea9da404c 100644 --- a/vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go +++ b/vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go @@ -39,17 +39,95 @@ const ( hwcap_SHA512 = 1 << 21 hwcap_SVE = 1 << 22 hwcap_ASIMDFHM = 1 << 23 + hwcap_DIT = 1 << 24 + hwcap_USCAT = 1 << 25 + hwcap_ILRCPC = 1 << 26 + hwcap_FLAGM = 1 << 27 + hwcap_SSBS = 1 << 28 + hwcap_SB = 1 << 29 + hwcap_PACA = 1 << 30 + hwcap_PACG = 1 << 31 + hwcap_GCS = 1 << 32 + + hwcap2_DCPODP = 1 << 0 + hwcap2_SVE2 = 1 << 1 + hwcap2_SVEAES = 1 << 2 + hwcap2_SVEPMULL = 1 << 3 + hwcap2_SVEBITPERM = 1 << 4 + hwcap2_SVESHA3 = 1 << 5 + hwcap2_SVESM4 = 1 << 6 + hwcap2_FLAGM2 = 1 << 7 + hwcap2_FRINT = 1 << 8 + hwcap2_SVEI8MM = 1 << 9 + hwcap2_SVEF32MM = 1 << 10 + hwcap2_SVEF64MM = 1 << 11 + hwcap2_SVEBF16 = 1 << 12 + hwcap2_I8MM = 1 << 13 + hwcap2_BF16 = 1 << 14 + hwcap2_DGH = 1 << 15 + hwcap2_RNG = 1 << 16 + hwcap2_BTI = 1 << 17 + hwcap2_MTE = 1 << 18 + hwcap2_ECV = 1 << 19 + hwcap2_AFP = 1 << 20 + hwcap2_RPRES = 1 << 21 + hwcap2_MTE3 = 1 << 22 + hwcap2_SME = 1 << 23 + hwcap2_SME_I16I64 = 1 << 24 + hwcap2_SME_F64F64 = 1 << 25 + hwcap2_SME_I8I32 = 1 << 26 + hwcap2_SME_F16F32 = 1 << 27 + hwcap2_SME_B16F32 = 1 << 28 + hwcap2_SME_F32F32 = 1 << 29 + hwcap2_SME_FA64 = 1 << 30 + hwcap2_WFXT = 1 << 31 + hwcap2_EBF16 = 1 << 32 + hwcap2_SVE_EBF16 = 1 << 33 + hwcap2_CSSC = 1 << 34 + hwcap2_RPRFM = 1 << 35 + hwcap2_SVE2P1 = 1 << 36 + hwcap2_SME2 = 1 << 37 + hwcap2_SME2P1 = 1 << 38 + hwcap2_SME_I16I32 = 1 << 39 + hwcap2_SME_BI32I32 = 1 << 40 + hwcap2_SME_B16B16 = 1 << 41 + hwcap2_SME_F16F16 = 1 << 42 + hwcap2_MOPS = 1 << 43 + hwcap2_HBC = 1 << 44 + hwcap2_SVE_B16B16 = 1 << 45 + hwcap2_LRCPC3 = 1 << 46 + hwcap2_LSE128 = 1 << 47 + hwcap2_FPMR = 1 << 48 + hwcap2_LUT = 1 << 49 + hwcap2_FAMINMAX = 1 << 50 + hwcap2_F8CVT = 1 << 51 + hwcap2_F8FMA = 1 << 52 + hwcap2_F8DP4 = 1 << 53 + hwcap2_F8DP2 = 1 << 54 + hwcap2_F8E4M3 = 1 << 55 + hwcap2_F8E5M2 = 1 << 56 + hwcap2_SME_LUTV2 = 1 << 57 + hwcap2_SME_F8F16 = 1 << 58 + hwcap2_SME_F8F32 = 1 << 59 + hwcap2_SME_SF8FMA = 1 << 60 + hwcap2_SME_SF8DP4 = 1 << 61 + hwcap2_SME_SF8DP2 = 1 << 62 + hwcap2_POE = 1 << 63 ) +// hwcap2 holds AT_HWCAP2. Unlike hwcap, the arm64 runtime does not expose it +// through internal/cpu, so detectOS reads it from the auxiliary vector. +var hwcap2 uint + func detectOS(c *CPUInfo) bool { // For now assuming no hyperthreading is reasonable. c.LogicalCores = runtime.NumCPU() c.PhysicalCores = c.LogicalCores c.ThreadsPerCore = 1 - if hwcap == 0 { - // We did not get values from the runtime. - // Try reading /proc/self/auxv - + // hwcap is provided by the runtime through the internal/cpu.HWCap linkname, + // but the runtime does not expose HWCAP2 on arm64. Read the auxiliary vector + // directly to obtain hwcap2 (and hwcap when the linkname is unavailable). + if hwcap == 0 || hwcap2 == 0 { // From https://github.com/golang/sys const ( _AT_HWCAP = 16 @@ -58,38 +136,35 @@ func detectOS(c *CPUInfo) bool { uintSize = int(32 << (^uint(0) >> 63)) ) - buf, err := ioutil.ReadFile("/proc/self/auxv") - if err != nil { - // e.g. on android /proc/self/auxv is not accessible, so silently - // ignore the error and leave Initialized = false. On some - // architectures (e.g. arm64) doinit() implements a fallback - // readout and will set Initialized = true again. - return false - } - bo := binary.LittleEndian - for len(buf) >= 2*(uintSize/8) { - var tag, val uint - switch uintSize { - case 32: - tag = uint(bo.Uint32(buf[0:])) - val = uint(bo.Uint32(buf[4:])) - buf = buf[8:] - case 64: - tag = uint(bo.Uint64(buf[0:])) - val = uint(bo.Uint64(buf[8:])) - buf = buf[16:] + // e.g. on android /proc/self/auxv is not accessible, so silently ignore + // the error and fall back to whatever the runtime provided. + if buf, err := ioutil.ReadFile("/proc/self/auxv"); err == nil { + bo := binary.LittleEndian + for len(buf) >= 2*(uintSize/8) { + var tag, val uint + switch uintSize { + case 32: + tag = uint(bo.Uint32(buf[0:])) + val = uint(bo.Uint32(buf[4:])) + buf = buf[8:] + case 64: + tag = uint(bo.Uint64(buf[0:])) + val = uint(bo.Uint64(buf[8:])) + buf = buf[16:] + } + switch tag { + case _AT_HWCAP: + hwcap = val + case _AT_HWCAP2: + hwcap2 = val + } } - switch tag { - case _AT_HWCAP: - hwcap = val - case _AT_HWCAP2: - // Not used - } - } - if hwcap == 0 { - return false } } + if hwcap == 0 { + // Nothing detected, e.g. on android or a restricted environment. + return false + } // HWCap was populated by the runtime from the auxiliary vector. // Use HWCap information since reading aarch64 system registers @@ -104,11 +179,15 @@ func detectOS(c *CPUInfo) bool { c.featureSet.setIf(isSet(hwcap, hwcap_DCPOP), DCPOP) c.featureSet.setIf(isSet(hwcap, hwcap_EVTSTRM), EVTSTRM) c.featureSet.setIf(isSet(hwcap, hwcap_FCMA), FCMA) + c.featureSet.setIf(isSet(hwcap, hwcap_ASIMDFHM), FHM) c.featureSet.setIf(isSet(hwcap, hwcap_FP), FP) c.featureSet.setIf(isSet(hwcap, hwcap_FPHP), FPHP) c.featureSet.setIf(isSet(hwcap, hwcap_JSCVT), JSCVT) c.featureSet.setIf(isSet(hwcap, hwcap_LRCPC), LRCPC) c.featureSet.setIf(isSet(hwcap, hwcap_PMULL), PMULL) + c.featureSet.setIf(isSet(hwcap2, hwcap2_RNG), RNDR) + // TLB (FEAT_TLBIOS/TLBIRANGE) has no HWCAP bit; only detectable via ID registers. + c.featureSet.setIf(isSet(hwcap, hwcap_FLAGM), TS) c.featureSet.setIf(isSet(hwcap, hwcap_SHA1), SHA1) c.featureSet.setIf(isSet(hwcap, hwcap_SHA2), SHA2) c.featureSet.setIf(isSet(hwcap, hwcap_SHA3), SHA3) @@ -116,6 +195,21 @@ func detectOS(c *CPUInfo) bool { c.featureSet.setIf(isSet(hwcap, hwcap_SM3), SM3) c.featureSet.setIf(isSet(hwcap, hwcap_SM4), SM4) c.featureSet.setIf(isSet(hwcap, hwcap_SVE), SVE) + c.featureSet.setIf(isSet(hwcap, hwcap_SB), SB) + c.featureSet.setIf(isSet(hwcap, hwcap_SSBS), SSBS) + + // Features reported through the second hardware capability word (HWCAP2). + c.featureSet.setIf(isSet(hwcap2, hwcap2_SVE2), SVE2) + c.featureSet.setIf(isSet(hwcap2, hwcap2_BTI), BTI) + c.featureSet.setIf(isSet(hwcap2, hwcap2_FLAGM2), FLAGM2) + c.featureSet.setIf(isSet(hwcap2, hwcap2_FRINT), FRINTTS) + c.featureSet.setIf(isSet(hwcap2, hwcap2_DCPODP), DCPODP) + c.featureSet.setIf(isSet(hwcap2, hwcap2_BF16), BF16) + c.featureSet.setIf(isSet(hwcap2, hwcap2_I8MM), I8MM) + c.featureSet.setIf(isSet(hwcap2, hwcap2_WFXT), WFXT) + c.featureSet.setIf(isSet(hwcap2, hwcap2_MOPS), MOPS) + c.featureSet.setIf(isSet(hwcap2, hwcap2_HBC), HBC) + c.featureSet.setIf(isSet(hwcap2, hwcap2_CSSC), CSSC) // The Samsung S9+ kernel reports support for atomics, but not all cores // actually support them, resulting in SIGILL. See issue #28431. diff --git a/vendor/github.com/klauspost/cpuid/v2/os_linux_riscv64.go b/vendor/github.com/klauspost/cpuid/v2/os_linux_riscv64.go new file mode 100644 index 000000000..71919a49b --- /dev/null +++ b/vendor/github.com/klauspost/cpuid/v2/os_linux_riscv64.go @@ -0,0 +1,225 @@ +// Copyright (c) 2026 Klaus Post, released under MIT License. See LICENSE file. + +package cpuid + +import ( + "bufio" + "os" + "runtime" + "strconv" + "strings" + "unsafe" + + "golang.org/x/sys/unix" +) + +const __NR_riscv_hwprobe = 258 + +type riscvHWProbePair struct { + key int64 + value uint64 +} + +// Keys from linux/include/uapi/asm/hwprobe.h +const ( + riscv_hwprobe_key_mvendorid = 0 + riscv_hwprobe_key_marchid = 1 + riscv_hwprobe_key_mimpid = 2 + riscv_hwprobe_key_base_behavior = 3 + riscv_hwprobe_key_ima_ext_0 = 4 + riscv_hwprobe_key_cpuperf_0 = 5 + riscv_hwprobe_key_zicbom_block_size = 12 +) + +// Bits from linux/arch/riscv/include/uapi/asm/hwprobe.h +const ( + riscv_hwprobe_ima_fd = 1 << 0 + riscv_hwprobe_ima_c = 1 << 1 + riscv_hwprobe_ima_v = 1 << 2 + riscv_hwprobe_ext_zba = 1 << 3 + riscv_hwprobe_ext_zbb = 1 << 4 + riscv_hwprobe_ext_zbs = 1 << 5 + riscv_hwprobe_ext_zicboz = 1 << 6 + riscv_hwprobe_ext_zbc = 1 << 7 + riscv_hwprobe_ext_zbkb = 1 << 8 + riscv_hwprobe_ext_zbkc = 1 << 9 + riscv_hwprobe_ext_zbkx = 1 << 10 + riscv_hwprobe_ext_zknd = 1 << 11 + riscv_hwprobe_ext_zkne = 1 << 12 + riscv_hwprobe_ext_zknh = 1 << 13 + riscv_hwprobe_ext_zksed = 1 << 14 + riscv_hwprobe_ext_zksh = 1 << 15 + riscv_hwprobe_ext_zkt = 1 << 16 + riscv_hwprobe_ext_zvbb = 1 << 17 + riscv_hwprobe_ext_zvbc = 1 << 18 + riscv_hwprobe_ext_zvkb = 1 << 19 + riscv_hwprobe_ext_zvkg = 1 << 20 + riscv_hwprobe_ext_zvkned = 1 << 21 + riscv_hwprobe_ext_zvknha = 1 << 22 + riscv_hwprobe_ext_zvknhb = 1 << 23 + riscv_hwprobe_ext_zvksed = 1 << 24 + riscv_hwprobe_ext_zvksh = 1 << 25 + riscv_hwprobe_ext_zvkt = 1 << 26 + riscv_hwprobe_ext_zfh = 1 << 27 + riscv_hwprobe_ext_zfhmin = 1 << 28 + riscv_hwprobe_ext_zihintntl = 1 << 29 + riscv_hwprobe_ext_zvfh = 1 << 30 + riscv_hwprobe_ext_zvfhmin = 1 << 31 + riscv_hwprobe_ext_zfa = 1 << 32 + riscv_hwprobe_ext_ztso = 1 << 33 + riscv_hwprobe_ext_zacas = 1 << 34 + riscv_hwprobe_ext_zicond = 1 << 35 + riscv_hwprobe_ext_zihintpause = 1 << 36 + riscv_hwprobe_ext_zicbom = 1 << 55 + riscv_hwprobe_ext_zicbop = 1 << 60 +) + +func riscvHWProbe(pairs []riscvHWProbePair) int64 { + if len(pairs) == 0 { + return -1 + } + ret, _, _ := unix.Syscall6(__NR_riscv_hwprobe, + uintptr(unsafe.Pointer(&pairs[0])), + uintptr(len(pairs)), + 0, 0, 0, 0) + return int64(ret) +} + +func detectOS(c *CPUInfo) bool { + c.LogicalCores = runtime.NumCPU() + c.PhysicalCores = c.LogicalCores + c.ThreadsPerCore = 1 + + pairs := []riscvHWProbePair{ + {key: riscv_hwprobe_key_mvendorid}, + {key: riscv_hwprobe_key_marchid}, + {key: riscv_hwprobe_key_mimpid}, + {key: riscv_hwprobe_key_ima_ext_0}, + {key: riscv_hwprobe_key_zicbom_block_size}, + } + ret := riscvHWProbe(pairs) + if ret == 0 && pairs[3].value != ^uint64(0) { + detectFromHWProbe(c, pairs) + if pairs[4].value != ^uint64(0) && pairs[4].value > 0 { + c.CacheLine = int(pairs[4].value) + } + return true + } + + c.CacheLine = detectCacheLine() + return detectFromCPUInfo(c) +} + +func detectFromHWProbe(c *CPUInfo, pairs []riscvHWProbePair) { + if pairs[0].value != ^uint64(0) { + c.VendorID = riscvVendorID(pairs[0].value) + c.VendorString = c.VendorID.String() + } + if pairs[1].value != ^uint64(0) { + c.Model = int(pairs[1].value) + } + if pairs[2].value != ^uint64(0) { + c.Family = int(pairs[2].value) + } + + imaExt := pairs[3].value + + if imaExt&riscv_hwprobe_ima_fd != 0 { + c.featureSet.set(RV_D) + c.featureSet.set(RV_F) + } + c.featureSet.setIf(imaExt&riscv_hwprobe_ima_c != 0, RV_C) + c.featureSet.setIf(imaExt&riscv_hwprobe_ima_v != 0, RV_V) + + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zba != 0, RV_ZBA) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zbb != 0, RV_ZBB) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zbc != 0, RV_ZBC) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zbs != 0, RV_ZBS) + + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zicbom != 0, RV_ZICBOM) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zicboz != 0, RV_ZICBOZ) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zicbop != 0, RV_ZICBOP) + + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zicond != 0, RV_ZICOND) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zihintpause != 0, RV_ZIHINTPAUSE) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zfa != 0, RV_ZFA) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zfh != 0, RV_ZFH) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zfhmin != 0, RV_ZFHMIN) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_ztso != 0, RV_ZTSO) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zacas != 0, RV_ZACAS) + + // Scalar cryptography + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zbkb != 0, RV_ZBKB) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zbkc != 0, RV_ZBKC) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zbkx != 0, RV_ZBKX) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zknd != 0, RV_ZKND) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zkne != 0, RV_ZKNE) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zknh != 0, RV_ZKNH) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zksed != 0, RV_ZKSED) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zksh != 0, RV_ZKSH) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zkt != 0, RV_ZKT) + + // Vector cryptography + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvbb != 0, RV_ZVBB) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvbc != 0, RV_ZVBC) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvkb != 0, RV_ZVKB) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvkg != 0, RV_ZVKG) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvkned != 0, RV_ZVKNED) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvknha != 0, RV_ZVKNHA) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvknhb != 0, RV_ZVKNHB) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvksed != 0, RV_ZVKSED) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvksh != 0, RV_ZVKSH) + c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvkt != 0, RV_ZVKT) + + // Crypto suites (combined from individual features) + c.featureSet.setIf(c.featureSet.hasSetP(rvZKNFeatures), RV_ZKN) + c.featureSet.setIf(c.featureSet.hasSetP(rvZKSFeatures), RV_ZKS) + c.featureSet.setIf(c.featureSet.hasSetP(rvZVKNFeatures), RV_ZVKNG) + c.featureSet.setIf(c.featureSet.hasSetP(rvZVKSFeatures), RV_ZVKSG) + + // Every Linux-capable riscv64 core has I, M, A base. + c.featureSet.set(RV_IMA) +} + +func detectFromCPUInfo(c *CPUInfo) bool { + f, err := os.Open("/proc/cpuinfo") + if err != nil { + return false + } + defer f.Close() + + scanner := bufio.NewScanner(f) + for scanner.Scan() { + line := scanner.Text() + fields := strings.SplitN(line, ":", 2) + if len(fields) < 2 { + continue + } + key := strings.TrimSpace(fields[0]) + value := strings.TrimSpace(fields[1]) + + switch key { + case "isa": + parseISAString(c, value) + case "mvendorid": + if vid, err := strconv.ParseUint(value, 0, 64); err == nil { + c.VendorID = riscvVendorID(vid) + c.VendorString = c.VendorID.String() + } + case "uarch": + c.BrandName = value + } + } + return scanner.Err() == nil +} + +func detectCacheLine() int { + data, err := os.ReadFile("/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size") + if err != nil { + return 0 + } + if n, err := strconv.Atoi(strings.TrimSpace(string(data))); err == nil && n > 0 { + return n + } + return 0 +} diff --git a/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go index 8733ba343..debc12392 100644 --- a/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go +++ b/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go @@ -1,7 +1,6 @@ // Copyright (c) 2020 Klaus Post, released under MIT License. See LICENSE file. //go:build arm64 && !linux && !darwin -// +build arm64,!linux,!darwin package cpuid diff --git a/vendor/github.com/klauspost/cpuid/v2/os_other_riscv64.go b/vendor/github.com/klauspost/cpuid/v2/os_other_riscv64.go new file mode 100644 index 000000000..fd86f7d05 --- /dev/null +++ b/vendor/github.com/klauspost/cpuid/v2/os_other_riscv64.go @@ -0,0 +1,14 @@ +// Copyright (c) 2026 Klaus Post, released under MIT License. See LICENSE file. + +//go:build riscv64 && !linux + +package cpuid + +import "runtime" + +func detectOS(c *CPUInfo) bool { + c.PhysicalCores = runtime.NumCPU() + c.ThreadsPerCore = 1 + c.LogicalCores = c.PhysicalCores + return false +} diff --git a/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go index f8f201b5f..5b4e8a1b3 100644 --- a/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go +++ b/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go @@ -1,7 +1,6 @@ // Copyright (c) 2021 Klaus Post, released under MIT License. See LICENSE file. //go:build nounsafe -// +build nounsafe package cpuid diff --git a/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go index 92af622eb..00158c21c 100644 --- a/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go +++ b/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go @@ -1,7 +1,6 @@ // Copyright (c) 2021 Klaus Post, released under MIT License. See LICENSE file. //go:build !nounsafe -// +build !nounsafe package cpuid diff --git a/vendor/github.com/klauspost/cpuid/v2/riscv_isa.go b/vendor/github.com/klauspost/cpuid/v2/riscv_isa.go new file mode 100644 index 000000000..5a87679bd --- /dev/null +++ b/vendor/github.com/klauspost/cpuid/v2/riscv_isa.go @@ -0,0 +1,93 @@ +// Copyright (c) 2026 Klaus Post, released under MIT License. See LICENSE file. + +package cpuid + +import "strings" + +func parseISAString(c *CPUInfo, isa string) { + isa = strings.ToLower(isa) + extMap := make(map[string]bool) + for ext := range strings.SplitSeq(isa, "_") { + ext = strings.TrimSpace(ext) + if strings.HasPrefix(ext, "rv64") { + extMap["i"] = true + for _, ch := range ext[4:] { + extMap[string(ch)] = true + } + } else if ext != "" { + extMap[ext] = true + } + } + + if extMap["g"] { + extMap["i"] = true + extMap["m"] = true + extMap["a"] = true + extMap["f"] = true + extMap["d"] = true + } + + c.featureSet.setIf(extMap["i"] && extMap["m"] && extMap["a"], RV_IMA) + c.featureSet.setIf(extMap["c"], RV_C) + c.featureSet.setIf(extMap["f"], RV_F) + c.featureSet.setIf(extMap["d"], RV_D) + c.featureSet.setIf(extMap["v"], RV_V) + c.featureSet.setIf(extMap["zihintpause"], RV_ZIHINTPAUSE) + c.featureSet.setIf(extMap["zba"], RV_ZBA) + c.featureSet.setIf(extMap["zbb"], RV_ZBB) + c.featureSet.setIf(extMap["zbc"], RV_ZBC) + c.featureSet.setIf(extMap["zbs"], RV_ZBS) + c.featureSet.setIf(extMap["zicond"], RV_ZICOND) + c.featureSet.setIf(extMap["zicbom"], RV_ZICBOM) + c.featureSet.setIf(extMap["zicboz"], RV_ZICBOZ) + c.featureSet.setIf(extMap["zicbop"], RV_ZICBOP) + c.featureSet.setIf(extMap["zfa"], RV_ZFA) + c.featureSet.setIf(extMap["zfh"], RV_ZFH) + c.featureSet.setIf(extMap["zfhmin"], RV_ZFHMIN) + c.featureSet.setIf(extMap["ztso"], RV_ZTSO) + c.featureSet.setIf(extMap["zacas"], RV_ZACAS) + + // Scalar cryptography + c.featureSet.setIf(extMap["zbkb"], RV_ZBKB) + c.featureSet.setIf(extMap["zbkc"], RV_ZBKC) + c.featureSet.setIf(extMap["zbkx"], RV_ZBKX) + c.featureSet.setIf(extMap["zknd"], RV_ZKND) + c.featureSet.setIf(extMap["zkne"], RV_ZKNE) + c.featureSet.setIf(extMap["zknh"], RV_ZKNH) + c.featureSet.setIf(extMap["zksed"], RV_ZKSED) + c.featureSet.setIf(extMap["zksh"], RV_ZKSH) + c.featureSet.setIf(extMap["zkt"], RV_ZKT) + + // Vector cryptography + c.featureSet.setIf(extMap["zvbb"], RV_ZVBB) + c.featureSet.setIf(extMap["zvbc"], RV_ZVBC) + c.featureSet.setIf(extMap["zvkb"], RV_ZVKB) + c.featureSet.setIf(extMap["zvkg"], RV_ZVKG) + c.featureSet.setIf(extMap["zvkned"], RV_ZVKNED) + c.featureSet.setIf(extMap["zvknha"], RV_ZVKNHA) + c.featureSet.setIf(extMap["zvknhb"], RV_ZVKNHB) + c.featureSet.setIf(extMap["zvksed"], RV_ZVKSED) + c.featureSet.setIf(extMap["zvksh"], RV_ZVKSH) + c.featureSet.setIf(extMap["zvkt"], RV_ZVKT) + + // Crypto suites (combined from individual features or bundle tokens) + c.featureSet.setIf(extMap["zkn"] || c.featureSet.hasSetP(rvZKNFeatures), RV_ZKN) + c.featureSet.setIf(extMap["zks"] || c.featureSet.hasSetP(rvZKSFeatures), RV_ZKS) + c.featureSet.setIf(extMap["zvkng"] || c.featureSet.hasSetP(rvZVKNFeatures), RV_ZVKNG) + c.featureSet.setIf(extMap["zvksg"] || c.featureSet.hasSetP(rvZVKSFeatures), RV_ZVKSG) +} + +var riscvVendorMap = map[uint64]Vendor{ + 0x489: SiFive, + 0x5b7: StarFive, + 0x5b1: THead, + 0x31e: Andes, + 0x710: SpacemiT, +} + +func riscvVendorID(mvendorid uint64) Vendor { + if v, ok := riscvVendorMap[mvendorid]; ok { + return v + } + return VendorUnknown +} diff --git a/vendor/modules.txt b/vendor/modules.txt index 929f0e234..6a76c1ae2 100644 --- a/vendor/modules.txt +++ b/vendor/modules.txt @@ -171,7 +171,9 @@ github.com/klauspost/compress/s2 github.com/klauspost/compress/zstd github.com/klauspost/compress/zstd/internal/xxhash # github.com/klauspost/cpuid/v2 v2.2.5 -## explicit; go 1.15 +## explicit; go 1.24.0 +# github.com/klauspost/cpuid/v2 v2.4.0 +## explicit; go 1.24.0 github.com/klauspost/cpuid/v2 # github.com/lufia/plan9stats v0.0.0-20231016141302-07b5767bb0ed ## explicit; go 1.16