Risque is going to be a decent RISC-V core. It is currently under development, and not ready for meaningful use at all.
- Unprivileged RV32IM support.
- Extendable memory mapping system for peripherals and memory.
- Adequate testbench for every module in the system.
- Pipelined design
- RV32GC/RV64GC support
- Multicore support
alu.py- ALU capable of un/signed addition, OR, AND, XOR, un/signed less than, un/signed right shift, left shift, un/signed multiplication, and un/signed floor division.isa.py- ISA definition.memmap.py- Memory mapping module, inspired by Vivonomicon's "RISC-V Memories" moduleram.py- Internal RAM module, basically Vivonomicon's RAM modulerom.py- Internal ROM module, basicall Vivonomicon's ROM module