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Enhance cfg routing in pci express hierarchy to support 1/2/4 bytes#3560

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Enhance cfg routing in pci express hierarchy to support 1/2/4 bytes#3560
shenw0000 wants to merge 1 commit into
microsoft:mainfrom
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Copilot AI review requested due to automatic review settings May 24, 2026 16:25
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Pull request overview

This PR updates the PCIe ECAM/config-space routing path so that configuration accesses can be handled using naturally aligned 1-, 2-, or 4-byte transfers instead of assuming only 4-byte dword operations. This is primarily implemented by adding byte-slice read/write APIs on the PCI config space emulators and plumbing those through the PCIe root/port/switch forwarding paths.

Changes:

  • Add read(offset, &mut [u8]) / write(offset, &[u8]) helpers to Type 0/Type 1 config space emulators to support 1/2/4-byte accesses.
  • Switch ECAM MMIO handling in the root complex from “read/modify/shift dword” to directly forwarding 1/2/4-byte buffers.
  • Update PCIe port/switch forwarding and tests to pass byte slices rather than u32.

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 5 comments.

Show a summary per file
File Description
vm/devices/pci/pcie/src/switch.rs Updates switch routing helpers to use byte-slice config reads/writes and adapt tests.
vm/devices/pci/pcie/src/root.rs Simplifies ECAM MMIO read/write paths to directly forward 1/2/4-byte buffers.
vm/devices/pci/pcie/src/port.rs Changes downstream port forwarding APIs to accept byte slices and adds access-size/alignment validation.
vm/devices/pci/pci_core/src/cfg_space_emu.rs Introduces config-space read/write APIs that accept 1/2/4-byte buffers for Type0/Type1 emulators.
vm/devices/cxl/src/test/cxl_test_device.rs Updates CXL test endpoint config-space implementation to use the new byte-slice APIs.

Comment on lines +1034 to +1035
let write_dword = u32::from_le_bytes(bytes) << byte_shift;

bytes[..data.len()].copy_from_slice(data);
let write_dword = u32::from_le_bytes(bytes) << byte_shift;

self.write_u32(dword_offset, write_dword)
Comment on lines 670 to +689
@@ -680,6 +685,8 @@ impl PcieDownstreamPort {
res => return res,
}
}

data.copy_from_slice(&dword_value.to_le_bytes()[..data.len()]);
Comment on lines +724 to 732
let mut bytes = [0u8; 4];
bytes[..data.len()].copy_from_slice(data);
let write_dword = u32::from_le_bytes(bytes);

let result = device.pci_cfg_write_with_routing(
secondary_bus,
*bus,
*function,
cfg_offset,
match self.decode_ecam_access(dword_aligned_addr) {
match self.decode_ecam_access(addr) {
DecodedEcamAccess::UnexpectedIntercept => {
tracing::error!("unexpected intercept at address 0x{:16x}", addr);
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2 participants