Immunity to electromagnetic interference EMI

[JosefJezek]

Could you improve immunity to electromagnetic interference of the Jacdac bus?

1. Using twisted pair cabling, see https://en.wikipedia.org/wiki/Twisted_pair
2. See Physical layer of CAN bus https://en.wikipedia.org/wiki/CAN_bus#Layers
3. See the differential I2C bus using PCA9615

source: https://www.digikey.com/en/articles/issues-with-the-i2c-bus-and-how-to-solve-them

EMI + I2C issue https://electronics.stackexchange.com/questions/187345/i2c-bus-is-not-responsive-when-engine-is-running-how-to-diagnose-and-fix

@pelikhan

[pelikhan]

@jamesadevine @sehodges @mmoskal

[jamesadevine]

Hi @JosefJezek,

We will not be employing differential signalling in our hardware. A key benefit we see to Jacdac is the lower connection requirement: just power, data, and ground.

Across longer distances, communications will be subject to interference and greater voltage drops. The best way to address this in Jacdac would be to create a dedicated module that employs differential signalling for interconnecting jacdac networks across greater distances. For example, an ethernet converter module might be an interesting route to pursue.

[JosefJezek]

@jamesadevine Do you test Jacdac with any DC motors?

see the links

• https://electronics.stackexchange.com/questions/443301/raspberry-pi-i2c-with-multiple-slaves-behaves-erratically
• https://www.fpaynter.com/2019/07/mpu6050-imu-motor-noise-troubleshooting/

[mmoskal]

Thank you for the hints! We should surely try that!

If the interference is only intermittent, Jacdac should be able to deal with loss of a few packets - we do not assume the transport to be loss-less. Note that this is much unlike i2c which can be completely locked by a single glitch.

[JosefJezek]

Ok, please write any result after a test here. Thank you.

[JosefJezek]

Is there any progress?

[pelikhan]

@sehodges this is for you

[sehodges]

Hi @JosefJezek - just catching up on this discussion. Not sure exactly what you were asking for progress on? It's always possible to improve EMC immunity, but we are also mindful of cost so we have tried to make a sensible tradeoff between these two characteristics (among others). That's why the Jacdac spec uses single-ended signalling, not differential - like @jamesadevine mentioned above. We have a low-pass filter on the data line which we actively drive both high and low (unlike I2C). We have allowed for a certain amount of voltage drop along the bus by including margin for this in the power supply and data signal voltages. We have not run tests with DC motors, but when I look at the two links you shared it seems that the problems they describe were mostly due to switching regulators/motor drivers rather than inherent in the use of motors? So I believe that DC motors would be fine given the same mitigations the authors of those two links recommend. Does that answer your question?