-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathCacheSimulator.py
More file actions
executable file
·120 lines (97 loc) · 4.07 KB
/
CacheSimulator.py
File metadata and controls
executable file
·120 lines (97 loc) · 4.07 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
#!/usr/bin/python3.5
'''
MIT License
Copyright (c) 2018 Reza Baharani
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
A simple cache simulator developed by Reza Baharani
This code is developed for Computer Architecture subject
University of North Carolina, Charlotte, USA
'''
import re
from Cache import Cache
import argparse
import gzip
parser = argparse.ArgumentParser()
parser.add_argument("cache_trace", help="Memory address trace in gzip format")
parser.add_argument("cache_size", help="Cache size in KB.", type=int)
parser.add_argument("block_size", help="Block size in B.", type=int)
parser.add_argument("set_number", help="set number", type=int)
parser.add_argument("address_bit_size", help="set number", type=int, default=32, action='store', nargs='?')
args = parser.parse_args()
regex = re.compile('[0-9]+')
'''
def readFile(fileAddr):
instructions=[]
dataAddr=[]
with open(fileAddr) as f:
lines = f.readlines()
for line in lines:
data = line.split(' ')
type = int(data[0], 10)
addr = int(data[1], 16)
if(type == 2):
instructions.append(addr)
elif(type == 0 or type == 1):
dataAddr.append(addr)
else:
print(data[0])
return [instructions, dataAddr]
'''
def simulateCaches(file_handler, i_ch, d_ch):
for line in file_handler:
data = line.split(' ')
type = int(data[0], 10)
addr = int(data[1], 16)
if (type == 2): # Instruction fetch
i_ch.read(addr) # Data read (0) or Data write (1)
elif (type == 0 or type == 1):
d_ch.read(addr)
try:
miss_rate_d = '{0:.2f}'.format(float(d_ch.miss) * 100 / d_ch.access)
except ZeroDivisionError:
miss_rate_d = 'N/A'
try:
miss_rate_i = '{0:.2f}'.format(float(i_ch.miss) * 100 / i_ch.access)
except ZeroDivisionError:
miss_rate_i = 'N/A'
print("{} miss rate : {}, access : {} and {} miss rate : {}, access : {}"
.format(i_ch.name, miss_rate_i, i_ch.access,
d_ch.name, miss_rate_d, d_ch.access), flush=True, end='\r')
print()
printResult(i_ch)
printResult(d_ch)
def printResult(ch):
print
print("-----------------------------")
print("\tResult for " + ch.name +":")
print("\tTotal : " + str(ch.access))
print("\tMisses : " + str(ch.miss))
print("\tHit : " + str(ch.access - ch.miss))
print("\tHit Rate : {0:.5}".format(float(ch.access - ch.miss)*100/ch.access))
print("-----------------------------")
if __name__ == '__main__':
filePath = args.cache_trace
cacheSize = args.cache_size * 1024
blockSize = args.block_size
setNumber = args.set_number
address_bit_size = args.address_bit_size
file_handler = gzip.open(filePath, 'rt')
l1_ins = Cache(address_bit_size, 'l1_icache', cacheSize, blockSize, setNumber)
l1_d = Cache(address_bit_size, 'l1_dcache', cacheSize, blockSize, setNumber)
l1_ins.construct()
l1_d.construct()
simulateCaches(file_handler, l1_ins, l1_d)