fix instruction formats

Author: mathis-s

core_descs/SelectTests.core_desc

@@ -4,8 +4,8 @@
 // CHECK-RV64: Pattern for SEXT_BIT23: (i64 (sra (i64 (i64 (shl (i64 GPR:$rs1), (i64 (i64 40))))), (i64 (i64 63))))
 // CHECK-RV32: Pattern for SEXT_BIT23: (i32 (sra (i32 (i32 (shl (i32 GPR:$rs1), (i32 (i32 8))))), (i32 (i32 31))))
 SEXT_BIT23 {
-    encoding: 5'b00000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
-    assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
+    encoding: 5'b00000 :: 1'b0 :: 1'b0 :: 5'd0 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
+    assembly: "{name(rd)}, {name(rs1)}";
     behavior: {
         if (rd != 0) {
             X[rd] = (signed)(X[rs1][23+:1]);
@@ -17,8 +17,8 @@ SEXT_BIT23 {
 // CHECK-RV64: Pattern for ZEXT_BIT23: (and (i64 (srl (i64 GPR:$rs1), (i64 (i64 23)))), (i64 1))
 // CHECK-RV32: Pattern for ZEXT_BIT23: (and (i32 (srl (i32 GPR:$rs1), (i32 (i32 23)))), (i32 1))
 ZEXT_BIT23 {
-    encoding: 5'b00000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
-    assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
+    encoding: 5'b00000 :: 1'b0 :: 1'b0 :: 5'd1 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
+    assembly: "{name(rd)}, {name(rs1)}";
     behavior: {
         if (rd != 0) {
             X[rd] = (unsigned)(X[rs1][23+:1]);
@@ -29,8 +29,8 @@ ZEXT_BIT23 {
 // CHECK-RV64: Pattern for ZEXT_UNALIGNED_BYTE: (and (i64 (srl (i64 GPR:$rs1), (i64 (i64 11)))), (i64 255))
 // CHECK-RV32: Pattern for ZEXT_UNALIGNED_BYTE: (and (i32 (srl (i32 GPR:$rs1), (i32 (i32 11)))), (i32 255))
 ZEXT_UNALIGNED_BYTE {
-    encoding: 5'b00000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
-    assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
+    encoding: 5'b00000 :: 1'b0 :: 1'b0 :: 5'd2 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
+    assembly: "{name(rd)}, {name(rs1)}";
     behavior: {
         if (rd != 0) {
             X[rd] = (unsigned)(X[rs1][11+:8]);
@@ -41,8 +41,8 @@ ZEXT_UNALIGNED_BYTE {
 // CHECK-RV64: Pattern for SEXT_UNALIGNED_BYTE: (i64 (sra (i64 (i64 (shl (i64 GPR:$rs1), (i64 (i64 45))))), (i64 (i64 56))))
 // CHECK-RV32: Pattern for SEXT_UNALIGNED_BYTE: (i32 (sra (i32 (i32 (shl (i32 GPR:$rs1), (i32 (i32 13))))), (i32 (i32 24))))
 SEXT_UNALIGNED_BYTE {
-    encoding: 5'b00000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
-    assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
+    encoding: 5'b00000 :: 1'b0 :: 1'b0 :: 5'd3 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
+    assembly: "{name(rd)}, {name(rs1)}";
     behavior: {
         if (rd != 0) {
             X[rd] = (signed)(X[rs1][11+:8]);
@@ -53,8 +53,8 @@ SEXT_UNALIGNED_BYTE {
 // CHECK-RV64: Pattern for ZEXT_ALIGNED_WORD: (and (i64 (srl (i64 GPR:$rs1), (i64 (i64 16)))), (i64 65535))
 // CHECK-RV32: Pattern for ZEXT_ALIGNED_WORD: (i32 (srl (i32 GPR:$rs1), (i32 (i32 16))))
 ZEXT_ALIGNED_WORD {
-    encoding: 5'b00000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
-    assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
+    encoding: 5'b00000 :: 1'b0 :: 1'b0 :: 5'd4 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
+    assembly: "{name(rd)}, {name(rs1)}";
     behavior: {
         if (rd != 0) {
             X[rd] = (unsigned)(X[rs1][16+:16]);
@@ -65,8 +65,8 @@ ZEXT_ALIGNED_WORD {
 // CHECK-RV64: Pattern for SEXT_ALIGNED_WORD: (i64 (sra (i64 (i64 (shl (i64 GPR:$rs1), (i64 (i64 32))))), (i64 (i64 48))))
 // CHECK-RV32: Pattern for SEXT_ALIGNED_WORD: (i32 (sra (i32 GPR:$rs1), (i32 (i32 16))))
 SEXT_ALIGNED_WORD {
-    encoding: 5'b00000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
-    assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
+    encoding: 5'b00000 :: 1'b0 :: 1'b0 :: 5'd5 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
+    assembly: "{name(rd)}, {name(rs1)}";
     behavior: {
         if (rd != 0) {
             X[rd] = (signed)(X[rs1][16+:16]);