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This is the implementation of the Design (programming the firmware)
No due date•3/7 issues closedThis is the design of the firmware architecture of the Timer Clock.
No due date•3/3 issues closedWith the collected experience of the PT1 (V1.0) some improvements can be implemented
No due date•0/2 issues closedAll bugs of PT1 (V1.0) have been recorded. This milestone represents the bugfixing stage of the the redesign PT1 -> PT2
No due date•22/25 issues closed