From a577948dda80e910027ddc09dbef4f5b57ea5699 Mon Sep 17 00:00:00 2001 From: Lubomir Bogdanov Date: Sun, 31 Mar 2019 21:30:46 +0300 Subject: [PATCH 1/3] Add support for Texas Instruments EK-LM3S6965 board. The board is old but gold. The target chip is the Stellaris LM3S6965 (ARM Cortex-M3) with 256k flash and 64k RAM. Currently the toggle pin was chosen to be PB6. --- config/arm/boards/ek-lm3s6965/board.cfg | 27 ++++ config/arm/boards/ek-lm3s6965/boardsupport.c | 35 +++++ config/arm/boards/ek-lm3s6965/calibration | 85 +++++++++++++ config/arm/chips/lm3s6965/chip.cfg | 29 +++++ config/arm/chips/lm3s6965/chip.ld | 88 +++++++++++++ config/arm/chips/lm3s6965/chipsupport.c | 127 +++++++++++++++++++ config/arm/chips/lm3s6965/chipsupport.h | 78 ++++++++++++ 7 files changed, 469 insertions(+) create mode 100644 config/arm/boards/ek-lm3s6965/board.cfg create mode 100644 config/arm/boards/ek-lm3s6965/boardsupport.c create mode 100644 config/arm/boards/ek-lm3s6965/calibration create mode 100644 config/arm/chips/lm3s6965/chip.cfg create mode 100644 config/arm/chips/lm3s6965/chip.ld create mode 100644 config/arm/chips/lm3s6965/chipsupport.c create mode 100644 config/arm/chips/lm3s6965/chipsupport.h diff --git a/config/arm/boards/ek-lm3s6965/board.cfg b/config/arm/boards/ek-lm3s6965/board.cfg new file mode 100644 index 00000000..168373b4 --- /dev/null +++ b/config/arm/boards/ek-lm3s6965/board.cfg @@ -0,0 +1,27 @@ +# Board configuration for Stellaris LM3S6965 Evaluation Kit + +# Copyright (C) 2018-2019 Technical University - Sofia + +# Contributor Lubomir Bogdanov + +# This file is part of BEEBS + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . + +# This file should be suitable for sourcing by configure + +# Default to the tm4c123g chip +if test $chip == none; then + chip=lm3s6965 +fi diff --git a/config/arm/boards/ek-lm3s6965/boardsupport.c b/config/arm/boards/ek-lm3s6965/boardsupport.c new file mode 100644 index 00000000..5ebbf09d --- /dev/null +++ b/config/arm/boards/ek-lm3s6965/boardsupport.c @@ -0,0 +1,35 @@ +/* Copyright (C) 2019 Technical University - Sofia + + Contributor Lubomir Bogdanov + + This file is part of the Bristol/Embecosm Embedded Benchmark Suite. + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include + +void initialise_board() +{ + PIN_INIT(6); +} + +void start_trigger() +{ + PIN_SET(6); +} + +void stop_trigger() +{ + PIN_CLEAR(6); +} diff --git a/config/arm/boards/ek-lm3s6965/calibration b/config/arm/boards/ek-lm3s6965/calibration new file mode 100644 index 00000000..d132f33e --- /dev/null +++ b/config/arm/boards/ek-lm3s6965/calibration @@ -0,0 +1,85 @@ +2dfir 4 +adpcm 9 +aha-compress 4 +aha-mont64 4 +blowfish 11 +bubblesort 7 +cnt 3 +compress 2 +cover 1 +crc 1 +crc32 5 +ctl-stack 4 +ctl-string 4 +ctl-vector 4 +cubic 9 +dhrystone 12 +dijkstra 10 +dtoa 3 +duff 0 +edn 7 +expint 2 +fac 0 +fasta 12 +fdct 2 +fft 6 +fir 8 +frac 7 +huffbench 12 +insertsort 0 +jfdctint 3 +levenshtein 6 +lms 11 +ludcmp 4 +matmult-int 8 +matmult-float 7 +mergesort 9 +miniz 12 +minver 3 +nbody 12 +ndes 6 +nettle-arcfour 5 +nettle-cast128 1 +nettle-des 2 +nettle-md5 0 +newlib-exp 3 +newlib-log 2 +newlib-sqrt 2 +ns 4 +nsichneu 3 +picojpeg 10 +prime 5 +qrduino 10 +qsort 1 +qurt 4 +recursion 1 +rijndael 10 +select 2 +sglib-arraybinsearch 4 +sglib-arrayheapsort 5 +sglib-arrayquicksort 5 +sglib-dllist 5 +sglib-hashtable 5 +sglib-listinsertsort 6 +sglib-listsort 5 +sglib-queue 6 +sglib-rbtree 6 +slre 5 +stringsearch1 2 +strstr 0 +sqrt 11 +st 9 +statemate 0 +stb_perlin 9 +trio-snprintf 4 +trio-sscanf 4 +ud 3 +wikisort 12 +whetstone 11 +bs 0 +fibcall 0 +janne_complex 0 +lcdnum 0 +newlib-mod 0 +sha 12 +tarai 0 diff --git a/config/arm/chips/lm3s6965/chip.cfg b/config/arm/chips/lm3s6965/chip.cfg new file mode 100644 index 00000000..1334dac8 --- /dev/null +++ b/config/arm/chips/lm3s6965/chip.cfg @@ -0,0 +1,29 @@ +# Chip configuration for ARM LM3S6965. + +# Copyright (C) 2018-2019 Technical University - Sofia + +# Contributor Lubomir Bogdanov + +# This file is part of BEEBS + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . + +# SPDX-License-Identifier: GPL-3.0-or-later + +# This file should be suitable for sourcing by configure + +chipdir=`readlink -m $srcdir/config/$arch/chips/$chip/` + +export CHIP_CFLAGS="--static -mcpu=cortex-m3 -O0 -g -gdwarf-3 -gstrict-dwarf" +export CHIP_LDFLAGS="-T $chipdir/chip.ld -Wl,--start-group -lc -specs=nano.specs -specs=nosys.specs -nostartfiles -Wl,--end-group" diff --git a/config/arm/chips/lm3s6965/chip.ld b/config/arm/chips/lm3s6965/chip.ld new file mode 100644 index 00000000..10de4cf8 --- /dev/null +++ b/config/arm/chips/lm3s6965/chip.ld @@ -0,0 +1,88 @@ +/* +* Copyright (c) 2018, Shawn D'silva +* All rights reserved. +* +* This file is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . +* +* File: TM4C123GH6PHM.ld +* Author: Shawn D'silva . +* Version: 1.0.0. +* Description: linker file for the TM4C Launchpad +* +* Modified by lbogdanov@tu-sofia.bg to support heap +*/ + +/* The entry point is not strictly the beginning of the vector table, but + * setting it as the entry point at least forces it and all relocations present + * in it to be included. The entry point is not used by the board/loader so it + * doesn't cause execution to start at the wrong address. + */ +ENTRY(vector_table) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K /* FLASH size 256KB */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K /* RAM size 64KB */ + +} + +SECTIONS +{ + + + /* + * initial stack pointer pointing to top of stack,starts from higher addresses + * i.e ORIGIN(RAM) + LENGTH(RAM)-1 in this case 0x20007FFF to lower addesses i.e + * those lesser than 0x20007FFF to 0x2000000,which is the origina address of RAM, + * until it comes in contact with .bss or .data in which case a buffer overflow occurs + */ + PROVIDE( _stack_ptr = ORIGIN(RAM) + LENGTH(RAM)); + + /* constants and other code stored in FLASH */ + .text : + { + _text = .; /* beginning of .text segment,also called code memory */ + KEEP(*(.vector_table)) /* vector table defined in startup.c to be included */ + *(.text*) /* other code */ + *(.rodata*) /* constants go here */ + _etext = .; /* end of .text segment */ + } > FLASH + + /* data, initialized variables, to be copied to RAM upon by startup.c */ + .data : + { + _data = .; /* beginning of .data segment */ + *(.data*) /* data goes here */ + _edata = .; /* end of .data segment */ + } > RAM AT >FLASH /* .data segment starts directly after the .text section in FLASH */ + + /* uninitialized data which is initialized to 0 upon by startup.c */ + .bss : + { + _bss = .; /* beginning of .bss segment */ + *(.bss*) /* .bss content goes here */ + *(COMMON) + _ebss = .; /* end of .bss segment */ + } > RAM + + .heap : + { + _heap = .; /* beginning of .heap segment */ + end = _heap; /* for the _sbrk function */ + *(.heap*) /* .heap content goes here */ + _eheap = .; /* end of .heap segment */ + } > RAM + + +} diff --git a/config/arm/chips/lm3s6965/chipsupport.c b/config/arm/chips/lm3s6965/chipsupport.c new file mode 100644 index 00000000..89001c3e --- /dev/null +++ b/config/arm/chips/lm3s6965/chipsupport.c @@ -0,0 +1,127 @@ +/* Copyright (C) 2019 Technical University - Sofia + + Contributor Lubomir Bogdanov + + This file is part of the Bristol/Embecosm Embedded Benchmark Suite. + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ +#include + +void software_init_hook(void); +static void nmi_handler(void); +static void hard_fault_handler(void); +static void default_int_handler(void); + +extern int _stack_ptr; +extern int _etext; +extern int _data; +extern int _edata; +extern int _bss; +extern int _ebss; + +extern int main(void); + +__attribute__ ((section(".vector_table"))) +void (* const vector_table[])(void) = { + (void (*)(void))((uint32_t)&_stack_ptr), // The initial stack pointer + software_init_hook, // Reset handler + nmi_handler, // NMI handler + hard_fault_handler, // Hard fault + default_int_handler, // MPU fault + default_int_handler, // Bus fault + default_int_handler, // Usage fault + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + default_int_handler, // SVCall + default_int_handler, // Debug monitor + 0, // Reserved + default_int_handler, // PendSV + default_int_handler, // SysTick + default_int_handler, // GPIOA + default_int_handler, // GPIOB + default_int_handler, // GPIOC + default_int_handler, // GPIOD + default_int_handler, // GPIOE + default_int_handler, // UART0 + default_int_handler, // UART1 + default_int_handler, // SSI0 + default_int_handler, // I2C0 + default_int_handler, // PWM Fault + default_int_handler, // PWM0 + default_int_handler, // PWM1 + default_int_handler, // PWM2 + default_int_handler, // QEI0 + default_int_handler, // ADC0 + default_int_handler, // ADC1 + default_int_handler, // ADC2 + default_int_handler, // ADC3 + default_int_handler, // WDT + default_int_handler, // Timer0_A + default_int_handler, // Timer0_B + default_int_handler, // Timer1_A + default_int_handler, // Timer1_B + default_int_handler, // Timer2_A + default_int_handler, // Timer2_B + default_int_handler, // A_Comp0 + default_int_handler, // A_Comp1 + default_int_handler, // A_Comp2 + default_int_handler, // SC + default_int_handler, // FLASH + default_int_handler, // GPIOF + default_int_handler, // GPIOG + default_int_handler, // GPIOH + default_int_handler, // UART2 + default_int_handler, // SSI1 + default_int_handler, // Timer3_A + default_int_handler, // Timer3_B + default_int_handler, // I2C1 + default_int_handler, // QEI_1 + default_int_handler, // CAN0 + default_int_handler, // CAN1 + default_int_handler, // CAN2 + default_int_handler, // Eth + default_int_handler // HIB +}; + +void software_init_hook(){ + int *src, *dest; + + src = &_etext; + for(dest = &_data; dest < &_edata; ){ + *dest++ = *src++; + } + + for(dest = &_bss; dest < &_ebss; ){ + *dest++ = 0x00000000; + } + + main(); + + while(1){ } +} + +static void nmi_handler(void){ + while(1){ } +} + +static void hard_fault_handler(void){ + while(1){ } +} + +static void default_int_handler(void){ + while(1){ } +} + diff --git a/config/arm/chips/lm3s6965/chipsupport.h b/config/arm/chips/lm3s6965/chipsupport.h new file mode 100644 index 00000000..ff3aba0b --- /dev/null +++ b/config/arm/chips/lm3s6965/chipsupport.h @@ -0,0 +1,78 @@ +/* Chip support for ARM LM3S6965. + + Copyright (C) 2019 Technical University - Sofia + + Contributor Lubomir Bogdanov + + This file is part of BEEBS + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along with + this program. If not, see . */ + +#ifndef CHIPSUPPORT_H +#define CHIPSUPPORT_H + +// Define the registers we need to do a pin toggle //////////////////////////// +#define ADDR(x) (*((unsigned long*)(x))) +#define SYSCTL_GPIO_ENABLE *(volatile unsigned long *)0x400FE108 + +#define SYSCTL_GPIOB_MASK 0x0002 +#define GPIO_PORTB_DIR *(volatile unsigned long *)0x40005400 //GPIO Port B direction register base address +#define GPIO_PORTB_DATA *(volatile unsigned long *)0x400053FC //GPIO Port B data register base address +#define GPIO_PORTB_DIG_PIN *(volatile unsigned long *)0x4000551C //GPIO Port B digital pin enable register base address +#define GPIO_PINMASK_6 0x40 //GPIO pin PB6 mask + + +// Provide macros to do the pin toggling //////////////////////////////////// + +// Initialize the pin + clocks +#define PIN_INIT(number) \ + do { \ + switch(number){ \ + case 6: \ + /* Turn on GPIO B Clock */ \ + SYSCTL_GPIO_ENABLE |= SYSCTL_GPIOB_MASK; \ + /* Do a dummy read to wait for GPIO B ready */ \ + volatile long i = SYSCTL_GPIO_ENABLE; \ + /* Set as output GPIO PB6 */ \ + GPIO_PORTB_DIR |= GPIO_PINMASK_6; \ + GPIO_PORTB_DIG_PIN |= GPIO_PINMASK_6; \ + /* Pull low GPIO PB6 */ \ + GPIO_PORTB_DATA &= ~GPIO_PINMASK_6; \ + break; \ + } \ + } while(0) + +// Set the pin to high +#define PIN_SET(number) \ + do { \ + switch(number){ \ + case 6: \ + /* Set PB6 */ \ + GPIO_PORTB_DATA |= GPIO_PINMASK_6; \ + break; \ + } \ + } while(0) \ + +// Set the pin to low +#define PIN_CLEAR(number) \ + do { \ + switch(number){ \ + case 6: \ + /* Clear PB6 */ \ + GPIO_PORTB_DATA &= ~GPIO_PINMASK_6; \ + break; \ + } \ + } while(0) \ + +#endif /* CHIPSUPPORT_H */ From da508c0ac422b122a0f55d9c419d4e45539c024d Mon Sep 17 00:00:00 2001 From: Lubomir Bogdanov Date: Sun, 31 Mar 2019 21:37:36 +0300 Subject: [PATCH 2/3] Add entry point to the linker script of TM4C123G. The entry point should be the vector table. Another way to set an entry point is to pass -Wl,-evector_table to GCC. Both ways have been tested and are working. If you do not set this you'll get empty binary files. --- config/arm/chips/tm4c123g/chip.ld | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/config/arm/chips/tm4c123g/chip.ld b/config/arm/chips/tm4c123g/chip.ld index b7bb5185..f86f294f 100644 --- a/config/arm/chips/tm4c123g/chip.ld +++ b/config/arm/chips/tm4c123g/chip.ld @@ -23,6 +23,13 @@ * Modified by lbogdanov@tu-sofia.bg to support heap */ +/* The entry point is not strictly the beginning of the vector table, but + * setting it as the entry point at least forces it and all relocations present + * in it to be included. The entry point is not used by the board/loader so it + * doesn't cause execution to start at the wrong address. + */ +ENTRY(vector_table) + MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K /* FLASH size 256KB */ From 8375f444a32315e7c2c115d0a43ce97d679e68ce Mon Sep 17 00:00:00 2001 From: Lubomir Bogdanov Date: Mon, 8 Apr 2019 00:12:12 +0300 Subject: [PATCH 3/3] Add support for STM32F769I-DISCO board. The ST Microelectronics' discovery board for STM32F769 uses an ARM Cortex-M7 based target with lots of features. The board itself has rich peripherals. Currently the toggle pin chosen is PA4 (designated as Arduino A1 at the back of the board). The operating frequency is 216MHz, I- and D-caches are on, the FPU is on (during init and with the proper compiler parameters) for maximum performance. The GPIO capability is quite good - I can see ~43MHz toggle frequency on my oscillo- scope if I do a toggle without delays. An interesting thing to note is that the board cannot be programmed with openocd v.0.10.0 but the AC6's SW4STM32 succeeds in doing so. You just have to make an empty project with the correct chip selected (STM32F769NIH) and select the BEEBs elf files from the Debug configuration window. --- config/arm/boards/stm32f769i-disco/board.cfg | 27 ++ .../boards/stm32f769i-disco/boardsupport.c | 35 ++ .../arm/boards/stm32f769i-disco/calibration | 85 +++++ config/arm/chips/stm32f769/chip.cfg | 27 ++ config/arm/chips/stm32f769/chip.ld | 87 +++++ config/arm/chips/stm32f769/chipsupport.c | 359 ++++++++++++++++++ config/arm/chips/stm32f769/chipsupport.h | 316 +++++++++++++++ 7 files changed, 936 insertions(+) create mode 100644 config/arm/boards/stm32f769i-disco/board.cfg create mode 100644 config/arm/boards/stm32f769i-disco/boardsupport.c create mode 100644 config/arm/boards/stm32f769i-disco/calibration create mode 100644 config/arm/chips/stm32f769/chip.cfg create mode 100644 config/arm/chips/stm32f769/chip.ld create mode 100644 config/arm/chips/stm32f769/chipsupport.c create mode 100644 config/arm/chips/stm32f769/chipsupport.h diff --git a/config/arm/boards/stm32f769i-disco/board.cfg b/config/arm/boards/stm32f769i-disco/board.cfg new file mode 100644 index 00000000..a79cefa2 --- /dev/null +++ b/config/arm/boards/stm32f769i-disco/board.cfg @@ -0,0 +1,27 @@ +# Board configuration for STM32F769I-DISCO development board + +# Copyright (C) 2018-2019 Technical University - Sofia + +# Contributor Lubomir Bogdanov + +# This file is part of BEEBS + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . + +# This file should be suitable for sourcing by configure + +# Default to the stm32f769 chip +if test $chip == none; then + chip=stm32f769 +fi diff --git a/config/arm/boards/stm32f769i-disco/boardsupport.c b/config/arm/boards/stm32f769i-disco/boardsupport.c new file mode 100644 index 00000000..6b5b75cd --- /dev/null +++ b/config/arm/boards/stm32f769i-disco/boardsupport.c @@ -0,0 +1,35 @@ +/* Copyright (C) 2019 Technical University - Sofia + + Contributor Lubomir Bogdanov + + This file is part of the Bristol/Embecosm Embedded Benchmark Suite. + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include + +void initialise_board() +{ + PIN_INIT(4); +} + +void start_trigger() +{ + PIN_SET(4); +} + +void stop_trigger() +{ + PIN_CLEAR(4); +} diff --git a/config/arm/boards/stm32f769i-disco/calibration b/config/arm/boards/stm32f769i-disco/calibration new file mode 100644 index 00000000..a1af0574 --- /dev/null +++ b/config/arm/boards/stm32f769i-disco/calibration @@ -0,0 +1,85 @@ +2dfir 1 +adpcm 1 +aha-compress 1 +aha-mont64 1 +blowfish 1 +bubblesort 1 +cnt 1 +compress 1 +cover 1 +crc 1 +crc32 1 +ctl-stack 1 +ctl-string 1 +ctl-vector 1 +cubic 1 +dhrystone 1 +dijkstra 1 +dtoa 1 +duff 1 +edn 1 +expint 1 +fac 1 +fasta 1 +fdct 1 +fft 1 +fir 1 +frac 1 +huffbench 1 +insertsort 1 +jfdctint 1 +levenshtein 1 +lms 1 +ludcmp 1 +matmult-int 1 +matmult-float 1 +mergesort 1 +miniz 1 +minver 1 +nbody 1 +ndes 1 +nettle-arcfour 1 +nettle-cast128 1 +nettle-des 1 +nettle-md5 1 +newlib-exp 1 +newlib-log 1 +newlib-sqrt 1 +ns 1 +nsichneu 1 +picojpeg 1 +prime 1 +qrduino 1 +qsort 1 +qurt 1 +recursion 1 +rijndael 1 +select 1 +sglib-arraybinsearch 1 +sglib-arrayheapsort 1 +sglib-arrayquicksort 1 +sglib-dllist 1 +sglib-hashtable 1 +sglib-listinsertsort 1 +sglib-listsort 1 +sglib-queue 1 +sglib-rbtree 1 +slre 1 +stringsearch1 1 +strstr 1 +sqrt 1 +st 1 +statemate 1 +stb_perlin 1 +trio-snprintf 1 +trio-sscanf 1 +ud 1 +wikisort 1 +whetstone 1 +bs 1 +fibcall 1 +janne_complex 1 +lcdnum 1 +newlib-mod 1 +sha 1 +tarai 1 diff --git a/config/arm/chips/stm32f769/chip.cfg b/config/arm/chips/stm32f769/chip.cfg new file mode 100644 index 00000000..ccb3dc50 --- /dev/null +++ b/config/arm/chips/stm32f769/chip.cfg @@ -0,0 +1,27 @@ +# Chip configuration for STM32F769NIH (ARM Cortex-M7). + +# Copyright (C) 2018-2019 Technical University - Sofia + +# Contributor Lubomir Bogdanov + +# This file is part of BEEBS + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . + +# This file should be suitable for sourcing by configure + +chipdir=`readlink -m $srcdir/config/$arch/chips/$chip/` + +export CHIP_CFLAGS="--static -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 -fmessage-length=0 -ffunction-sections -MMD -MP -O0 -g -gdwarf-3 -gstrict-dwarf" +export CHIP_LDFLAGS="-T $chipdir/chip.ld -Wl,--gc-sections -Wl,--start-group -lc -lm -specs=nano.specs -specs=nosys.specs -nostartfiles -Wl,--end-group" diff --git a/config/arm/chips/stm32f769/chip.ld b/config/arm/chips/stm32f769/chip.ld new file mode 100644 index 00000000..0076e89e --- /dev/null +++ b/config/arm/chips/stm32f769/chip.ld @@ -0,0 +1,87 @@ +/* +* Copyright (c) 2018, Shawn D'silva +* All rights reserved. +* +* This file is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . +* +* File: TM4C123GH6PHM.ld +* Author: Shawn D'silva . +* Version: 1.0.0. +* Description: linker file for the TM4C Launchpad +* +* Modified by lbogdanov@tu-sofia.bg to support heap +*/ + +/* The entry point is not strictly the beginning of the vector table, but + * setting it as the entry point at least forces it and all relocations present + * in it to be included. The entry point is not used by the board/loader so it + * doesn't cause execution to start at the wrong address. + */ +ENTRY(vector_table) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K /* FLASH size 2MB */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 512K /* RAM size 256KB */ +} + +SECTIONS +{ + + + /* + * initial stack pointer pointing to top of stack,starts from higher addresses + * i.e ORIGIN(RAM) + LENGTH(RAM)-1 in this case 0x20007FFF to lower addesses i.e + * those lesser than 0x20007FFF to 0x2000000,which is the origina address of RAM, + * until it comes in contact with .bss or .data in which case a buffer overflow occurs + */ + PROVIDE( _stack_ptr = ORIGIN(RAM) + LENGTH(RAM)); + + /* constants and other code stored in FLASH */ + .text : + { + _text = .; /* beginning of .text segment,also called code memory */ + KEEP(*(.vector_table)) /* vector table defined in startup.c to be included */ + *(.text*) /* other code */ + *(.rodata*) /* constants go here */ + _etext = .; /* end of .text segment */ + } > FLASH + + /* data, initialized variables, to be copied to RAM upon by startup.c */ + .data : + { + _data = .; /* beginning of .data segment */ + *(.data*) /* data goes here */ + _edata = .; /* end of .data segment */ + } > RAM AT >FLASH /* .data segment starts directly after the .text section in FLASH */ + + /* uninitialized data which is initialized to 0 upon by startup.c */ + .bss : + { + _bss = .; /* beginning of .bss segment */ + *(.bss*) /* .bss content goes here */ + *(COMMON) + _ebss = .; /* end of .bss segment */ + } > RAM + + .heap : + { + _heap = .; /* beginning of .heap segment */ + end = _heap; /* for the _sbrk function */ + *(.heap*) /* .heap content goes here */ + _eheap = .; /* end of .bss segment */ + } > RAM + + +} diff --git a/config/arm/chips/stm32f769/chipsupport.c b/config/arm/chips/stm32f769/chipsupport.c new file mode 100644 index 00000000..0a240b57 --- /dev/null +++ b/config/arm/chips/stm32f769/chipsupport.c @@ -0,0 +1,359 @@ +/* Copyright (C) 2019 Technical University - Sofia + + Contributor Lubomir Bogdanov + + This file is part of the Bristol/Embecosm Embedded Benchmark Suite. + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ +#include +#include "chipsupport.h" + +void software_init_hook(void); +static void nmi_handler(void); +static void hard_fault_handler(void); +static void default_int_handler(void); + +extern int _stack_ptr; +extern int _etext; +extern int _data; +extern int _edata; +extern int _bss; +extern int _ebss; + +extern int main(void); + +__attribute__ ((section(".vector_table"))) +void (* const vector_table[])(void) = { + (void (*)(void))((uint32_t)&_stack_ptr),// The initial stack pointer + software_init_hook, // The reset handler + nmi_handler, // The NMI handler + hard_fault_handler, // The hard fault handler + default_int_handler, // The MPU fault handler + default_int_handler, // The bus fault handler + default_int_handler, // The usage fault handler + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + default_int_handler, /* SVC handler */ + default_int_handler, /* DebugMon handler */ + 0, /* Reserved */ + default_int_handler, /* PendSV handler */ + default_int_handler, /* SysTick handler */ + default_int_handler, /* Window Watchdog interrupt */ + default_int_handler, /* PVD through EXTI line detection */ + default_int_handler, /* Tamper and TimeStamp interrupts through the EXTI line */ + default_int_handler, /* RTC Tamper or TimeStamp /CSS on LSE through EXTI line 19 interrupts */ + default_int_handler, /* Flash global interrupt */ + default_int_handler, /* RCC global interrupt */ + default_int_handler, /* EXTI Line0 interrupt */ + default_int_handler, /* EXTI Line1 interrupt */ + default_int_handler, /* EXTI Line2 interrupt */ + default_int_handler, /* EXTI Line3 interrupt */ + default_int_handler, /* EXTI Line4 interrupt */ + default_int_handler, /* DMA1 Stream0 global interrupt */ + default_int_handler, /* DMA1 Stream1 global interrupt */ + default_int_handler, /* DMA1 Stream2 global interrupt */ + default_int_handler, /* DMA1 Stream3 global interrupt */ + default_int_handler, /* DMA1 Stream4 global interrupt */ + default_int_handler, /* DMA1 Stream5 global interrupt */ + default_int_handler, /* DMA1 Stream6 global interrupt */ + default_int_handler, /* ADC1 global interrupt */ + default_int_handler, /* CAN1 TX interrupts */ + default_int_handler, /* CAN1 RX0 interrupts */ + default_int_handler, /* CAN1 RX1 interrupts */ + default_int_handler, /* CAN1 SCE interrupt */ + default_int_handler, /* EXTI Line[9:5] interrupts */ + default_int_handler, /* TIM1 Break interrupt and TIM9 global interrupt */ + 0, /* Reserved */ + default_int_handler, /* TIM1 Trigger and Commutation interrupts and TIM11 global interrupt */ + 0, /* Reserved */ + default_int_handler, /* TIM2 global interrupt */ + default_int_handler, /* TIM3 global interrupt */ + default_int_handler, /* TIM4 global interrupt */ + default_int_handler, /* I2C1 event interrupt */ + default_int_handler, /* I2C1 error interrupt */ + 0, /* Reserved */ + 0, /* Reserved */ + default_int_handler, /* SPI1 global interrupt */ + default_int_handler, /* SPI2 global interrupt */ + default_int_handler, /* USART1 global interrupt */ + default_int_handler, /* USART2 global interrupt */ + default_int_handler, /* USART3 global interrupt */ + default_int_handler, /* EXTI Line[15:10] interrupts */ + default_int_handler, /* RTC alarms through EXTI line 18 interrupts */ + default_int_handler, /* USB On-The-Go FS Wakeup through EXTI line interrupt */ + default_int_handler, /* TIM8 Break interrupt and TIM12 global interrupt */ + default_int_handler, /* TIM8 Update interrupt and TIM13 global interrupt */ + default_int_handler, /* TIM8 Trigger and Commutation interrupts and TIM14 global interrupt */ + default_int_handler, /* TIM8 Capture Compare interrupt */ + default_int_handler, /* DMA1 Stream7 global interrupt */ + default_int_handler, /* FMC global interrupt */ + default_int_handler, /* SDMMC1 global interrupt */ + default_int_handler, /* TIM5 global interrupt */ + default_int_handler, /* SPI3 global interrupt */ + default_int_handler, /* UART4 global interrupt */ + default_int_handler, /* UART5 global interrupt */ + default_int_handler, /* TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt */ + default_int_handler, /* TIM7 global interrupt */ + default_int_handler, /* DMA2 Stream0 global interrupt */ + default_int_handler, /* DMA2 Stream1 global interrupt */ + default_int_handler, /* DMA2 Stream2 global interrupt */ + default_int_handler, /* DMA2 Stream3 global interrupt */ + default_int_handler, /* DMA2 Stream4 global interrupt */ + default_int_handler, /* Ethernet global interrupt */ + default_int_handler, /* Ethernet Wakeup through EXTI line */ + default_int_handler, /* CAN2 TX interrupts */ + default_int_handler, /* CAN2 RX0 interrupts */ + default_int_handler, /* CAN2 RX1 interrupts */ + default_int_handler, /* CAN2 SCE interrupt */ + default_int_handler, /* USB On The Go FS global interrupt */ + default_int_handler, /* DMA2 Stream5 global interrupt */ + default_int_handler, /* DMA2 Stream6 global interrupt */ + default_int_handler, /* DMA2 Stream7 global interrupt */ + default_int_handler, /* USART6 global interrupt */ + default_int_handler, /* I2C3 event interrupt */ + default_int_handler, /* I2C3 error interrupt */ + default_int_handler, /* USB On The Go HS End Point 1 Out global interrupt */ + default_int_handler, /* USB On The Go HS End Point 1 In global interrupt */ + default_int_handler, /* USB On The Go HS Wakeup through EXTI interrupt */ + default_int_handler, /* USB On The Go HS global interrupt */ + default_int_handler, /* DCMI global interrupt */ + 0, /* Reserved */ + default_int_handler, /* Hash and Rng global interrupt */ + default_int_handler, /* Floating point unit interrupt */ + default_int_handler, /* UART 7 global interrupt */ + default_int_handler, /* UART 8 global interrupt */ + default_int_handler, /* SPI 4 global interrupt */ + default_int_handler, /* SPI 5 global interrupt */ + default_int_handler, /* SPI 6 global interrupt */ + default_int_handler, /* SAI1 global interrupt */ + default_int_handler, /* LTDC global interrupt */ + default_int_handler, /* LCD-TFT global Error interrupt */ + default_int_handler, /* DMA2D global interrupt */ + default_int_handler, /* SAI2 global interrupt */ + default_int_handler, /* QuadSPI global interrupt */ + default_int_handler, /* LP Timer1 global interrupt */ + default_int_handler, /* HDMI-CEC global interrupt */ + default_int_handler, /* I2C4 event interrupt */ + default_int_handler, /* I2C4 Error interrupt */ + default_int_handler, /* SPDIFRX global interrupt */ + default_int_handler, /* DSI host global interrupt */ + default_int_handler, /* DFSDM1 Filter 0 global interrupt */ + default_int_handler, /* DFSDM1 Filter 1 global interrupt */ + default_int_handler, /* DFSDM1 Filter 2 global interrupt */ + default_int_handler, /* DFSDM1 Filter 3 global interrupt */ + default_int_handler, /* SDMMC2 global interrupt */ + default_int_handler, /* CAN3 TX interrupt */ + default_int_handler, /* CAN3 RX0 interrupt */ + default_int_handler, /* CAN3 RX1 interrupt */ + default_int_handler, /* CAN3 SCE interrupt */ + default_int_handler, /* JPEG global interrupt */ + default_int_handler /* MDIO slave global interrupt */ +}; + +/*! + \brief Sets CPU frequency to 216 MHz, enables icache and dcache, configures flash for + high-speed operation, uses external 25MHz input for the HSE module to feed the PLL. + This function also enables the FPU. + + \param None. + \return None. +*/ +void init_mcu(void){ + /* FPU settings ------------------------------------------------------------*/ + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Enable I-Cache */ + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + /* Enable D-Cache */ + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + ccsidr = SCB->CCSIDR; + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << 5) & SCB_DCISW_SET_Msk) | + ((ways << 30) & SCB_DCISW_WAY_Msk) ); + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + __DSB(); + __ISB(); + + /*Enable the FLASH Adaptive Real-Time memory accelerator.*/ + SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN); + /*Enable the FLASH prefetch buffer.*/ + FLASH->ACR |= FLASH_ACR_PRFTEN; + + /* Enable Power Control clock */ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); + + /* Configure voltage scaling */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (PWR_REGULATOR_VOLTAGE_SCALE1)); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); + + /*Set clock to 216 MHz */ + /* Turn on HSE osc */ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); + SET_BIT(RCC->CR, RCC_CR_HSEON); + /* Wait for HSE to turn on */ + while((RCC->CR & RCC_FLAG_HSERDY) == RESET){ } + /* Configure the PLL */ + /* First disable the main PLL. */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET){ } + + /* Configure the main PLL clock source, multiplication and division factors.*/ + __HAL_RCC_PLL_CONFIG(RCC_PLLSOURCE_HSE, 25, 432, RCC_PLLP_DIV2, 9, 7); + + /* Enable the main PLL. */ + SET_BIT(RCC->CR, RCC_CR_PLLON); + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET){ } + + /* Activate the Over-Drive mode. */ + /*Enable the Over drive mode.*/ + PWR->CR1 |= (uint32_t)PWR_CR1_ODEN; + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)){ } + + /* Enable the Over-drive switch */ + PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN; + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)){ } + + /* Configure clock gating and dividers */ + + /* Increasing the CPU frequency */ + if(FLASH_LATENCY_7 > __HAL_FLASH_GET_LATENCY()){ + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_7)); + if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_7){ + while(1){ } + } + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_7){ + while(1){ } + } + } + + /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); + + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET){ + while(1){ } + } + + /* PLL is selected as System Clock Source */ + __HAL_RCC_SYSCLK_CONFIG(RCC_SYSCLKSOURCE_PLLCLK); + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_SYSCLKSOURCE_PLLCLK << RCC_CFGR_SWS_Pos)){ } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLASH_LATENCY_7 < __HAL_FLASH_GET_LATENCY()){ + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_7)); + if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_7){ + while(1){ } + } + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_7){ + while(1){ } + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV4); + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_HCLK_DIV2) << 3)); + + UNUSED(tmpreg); +} + +void software_init_hook(){ + int *src, *dest; + + src = &_etext; + for(dest = &_data; dest < &_edata; ){ + *dest++ = *src++; + } + + for(dest = &_bss; dest < &_ebss; ){ + *dest++ = 0x00000000; + } + + init_mcu(); + + main(); + + while(1){ } +} + +static void nmi_handler(void){ + while(1){ } +} + +static void hard_fault_handler(void){ + while(1){ } +} + +static void default_int_handler(void){ + while(1){ } +} + diff --git a/config/arm/chips/stm32f769/chipsupport.h b/config/arm/chips/stm32f769/chipsupport.h new file mode 100644 index 00000000..f7e29657 --- /dev/null +++ b/config/arm/chips/stm32f769/chipsupport.h @@ -0,0 +1,316 @@ +/* Chip support for STM32F769NIH (ARM Cortex-M7). + + Copyright (C) 2019 Technical University - Sofia + + Contributor Lubomir Bogdanov + + This file is part of BEEBS + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along with + this program. If not, see . */ + +#ifndef CHIPSUPPORT_H +#define CHIPSUPPORT_H + +#include + +// Define the registers we need to do a pin toggle //////////////////////////// +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#define __I volatile const /*!< Defines 'read only' permissions */ +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) +#define READ_BIT(REG, BIT) ((REG) & (BIT)) +#define CLEAR_REG(REG) ((REG) = (0x0)) +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) +#define READ_REG(REG) ((REG)) +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + +typedef enum{ + RESET = 0U, + SET = !RESET +} FlagStatus, ITStatus; + +typedef struct{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +typedef struct{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */ + __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */ + +} RCC_TypeDef; + +typedef struct{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ +} PWR_TypeDef; + +typedef struct{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */ +} FLASH_TypeDef; + +typedef struct{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + + +#define SCB_CCR_IC_Msk (1UL << 17UL) /*!< SCB CCR: Instruction cache enable bit Mask */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << 3UL) /*!< SCB CCSIDR: Associativity Mask */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << 13UL) /*!< SCB CCSIDR: NumSets Mask */ +#define SCB_DCISW_SET_Msk (0x1FFUL << 5UL) /*!< SCB DCISW: Set Mask */ +#define SCB_DCISW_WAY_Msk (3UL << 30UL) /*!< SCB DCISW: Way Mask */ +#define SCB_CCR_DC_Msk (1UL << 16UL) /*!< SCB CCR: Cache enable bit Mask */ +#define FLASH_ACR_ARTEN (1UL << 9U) +#define FLASH_ACR_PRFTEN (1UL << 8UL) +#define RCC_APB1ENR_PWREN (1UL << 28UL) +#define PWR_REGULATOR_VOLTAGE_SCALE1 (3UL << 14UL) +#define PWR_CR1_VOS (3UL << 14UL) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ +#define RCC_CR_HSEON (1UL << 16UL) +#define RCC_FLAG_HSERDY ((uint8_t)0x17U) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39U) +#define RCC_CR_PLLON (1UL << 24UL) +#define RCC_PLLSOURCE_HSE (1UL << 22UL) +#define RCC_PLLCFGR_PLLN_Pos (6UL) +#define RCC_PLLP_DIV2 ((uint32_t)0x00000002UL) +#define RCC_PLLCFGR_PLLP_Pos (16UL) +#define RCC_PLLCFGR_PLLQ_Pos (24UL) +#define RCC_PLLCFGR_PLLR_Pos (28UL) +#define PWR_CR1_ODEN (1UL << 16UL) +#define PWR_FLAG_ODRDY (1UL << 16UL) +#define PWR_CR1_ODSWEN (1UL << 17UL) +#define PWR_FLAG_ODSWRDY (1UL << 17UL) +#define FLASH_LATENCY_7 0x00000007UL /*!< FLASH Seven Latency cycles */ +#define FLASH_ACR_LATENCY (15UL << 0UL) +#define RCC_CFGR_PPRE1 (7UL << 10UL) +#define RCC_HCLK_DIV16 0x00001C00UL +#define RCC_CFGR_PPRE2 (7UL << 13UL) +#define RCC_CFGR_HPRE (15UL << 4UL) +#define RCC_SYSCLK_DIV1 0x00000000UL +#define RCC_CFGR_SW (3UL << 0UL) +#define RCC_SYSCLKSOURCE_PLLCLK 0x00000002UL +#define RCC_CFGR_SWS (3UL << 2UL) +#define RCC_CFGR_SWS_Pos (2UL) +#define RCC_HCLK_DIV4 0x00001400UL +#define RCC_HCLK_DIV2 0x00001000UL +#define RCC_AHB1ENR_GPIOAEN (1UL << 0UL) +#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define RCC_CR_HSEBYP (1UL << 18UL) +#define GPIO_PIN_4 (uint16_t)0x0010U +#define GPIO_MODER_MODER0 (3UL << 0UL) +#define GPIO_RESET_OFFSET ((uint32_t)16UL) +#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001UL) /*!< Output Push Pull Mode */ +#define GPIO_MODE ((uint32_t)0x00000003U) +#define GPIO_SPEED_HIGH ((uint32_t)0x00000003U) +#define GPIO_OSPEEDER_OSPEEDR0 (3UL << 0UL) +#define GPIO_OTYPER_OT_0 0x00000001UL +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U) + +#define SCB ((SCB_Type *) 0xE000ED00UL) +#define RCC ((RCC_TypeDef *) 0x40023800UL) +#define FLASH ((FLASH_TypeDef *) 0x40023C00UL) +#define PWR ((PWR_TypeDef *) 0x40007000UL) +#define GPIOA ((GPIO_TypeDef *) 0x40020000UL) + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> 3UL) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> 13UL) + +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) +#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) +#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ + (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) + + +/* Data Synchronization Barrier */ +__attribute__((always_inline)) static inline void __DSB(void){ + __asm volatile ("dsb 0xF":::"memory"); +} + +/* Instruction Synchronization Barrier */ +__attribute__((always_inline)) static inline void __ISB(void){ + __asm volatile ("isb 0xF":::"memory"); +} + + +// Provide macros to do the pin toggling //////////////////////////////////// + +// Initialize the pin +#define PIN_INIT(number) \ + do { \ + __IO uint32_t tmpreg; \ + uint32_t temp = 0x00; \ + uint32_t position = 0x04; \ + \ + switch(number){ \ + case 4: \ + /* Enable GPIO A */ \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN); \ + UNUSED(tmpreg); \ + \ + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ \ + temp = GPIOA->MODER; \ + temp &= ~(GPIO_MODER_MODER0 << (position * 2)); \ + temp |= ((GPIO_MODE_OUTPUT_PP & GPIO_MODE) << (position * 2)); \ + GPIOA->MODER = temp; \ + \ + /* Configure the IO Speed */ \ + temp = GPIOA->OSPEEDR; \ + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); \ + temp |= (GPIO_SPEED_HIGH << (position * 2)); \ + GPIOA->OSPEEDR = temp; \ + \ + /* Configure the IO Output Type */ \ + temp = GPIOA->OTYPER; \ + temp &= ~(GPIO_OTYPER_OT_0 << position) ; \ + temp |= (((GPIO_MODE_OUTPUT_PP & GPIO_OUTPUT_TYPE) >> 4) << position); \ + GPIOA->OTYPER = temp; \ + break; \ + } \ + } while(0) \ + +// Set the pin to high +#define PIN_SET(number) \ + do { \ + switch(number){ \ + case 4: \ + /* Set PA4 */ \ + GPIOA->BSRR = GPIO_PIN_4; \ + break; \ + } \ + } while(0) \ + +// Set the pin to low +#define PIN_CLEAR(number) \ + do { \ + switch(number){ \ + case 4: \ + /* Clear PA4 */ \ + GPIOA->BSRR = GPIO_PIN_4 << GPIO_RESET_OFFSET; \ + break; \ + } \ + } while(0) \ + +#endif /* CHIPSUPPORT_H */