Commit abbced1
v0.2.15: FP8 I/O GEMM, Pure NVF4 (446 TFLOPS), New Math Ops (#117)
* chore: bump version to 0.2.15
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* feat(asr): add Whisper audio preprocessing (#103)
Implement GPU-accelerated audio preprocessing for Whisper models:
- Pad/trim audio to 30 seconds (480,000 samples)
- Whisper normalization: (log_mel + 4.0) / 4.0
- Output shape: [n_mels, n_frames] = [80, 3000]
Uses existing audio ops (STFT, Mel filterbank) with Whisper-specific
parameters (n_fft=400, hop_length=160, n_mels=80).
Closes #103
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* feat(asr): add Whisper model loader (#100)
Implement SafeTensors loader for Whisper architecture models:
- WhisperConfig: Parse config.json with all model parameters
- WhisperWeights: Load and organize encoder/decoder weights
- Support for distilled models (kotoba-whisper with 2 decoder layers)
- Predefined configs for tiny/base/small/medium/large/large-v3
- HuggingFace Hub download support
Tensor mapping covers:
- Encoder: conv1/conv2, positional embeddings, 32 transformer layers
- Decoder: token/position embeddings, 2-32 transformer layers
- Cross-attention for encoder-decoder connection
Closes #100
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* feat(asr): add Whisper encoder (#101)
Implements full Whisper encoder with:
- Conv1d stem (2 layers with GELU)
- Multi-head self-attention
- FFN with GELU activation
- Layer normalization
- Positional embeddings
Includes CPU fallback implementations for:
- _softmax_4d: N-D softmax with axis support
- _conv1d: im2col + matmul convolution
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* feat(asr): add Whisper decoder (#102)
Implements full Whisper decoder with:
- Token embedding lookup
- Causal self-attention with masking
- Cross-attention to encoder outputs
- FFN with GELU activation
- Layer normalization
- Output projection to vocabulary
Includes autoregressive generation with:
- Greedy decoding
- Temperature-based sampling
- Top-k sampling
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* feat(asr): add WhisperModel with streaming inference (#104)
Implements high-level WhisperModel API with:
- from_pretrained() for loading models from local/HuggingFace
- transcribe() for single-file transcription
- transcribe_streaming() for chunked long audio processing
Features:
- TranscriptionResult with segments and timestamps
- WhisperTokenizer wrapper for HuggingFace tokenizers
- Audio file loading with soundfile
- Mel spectrogram computation (librosa or numpy fallback)
- Automatic resampling to 16kHz
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* docs: update project structure with ASR module
- Add detailed src/pygpukit/ directory structure
- Add Module Separation Policy explaining llm/ vs asr/ split
- Document rationale: separation by modality, not architecture
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* feat(examples): add real-time STT demo with Whisper
Demo supports:
- Microphone input (real-time transcription)
- WAV file input
- Raw PCM file input (any format)
- Configurable chunk size and language
- Real-time simulation mode for files
Usage:
python examples/whisper_realtime_stt.py # Microphone
python examples/whisper_realtime_stt.py -i audio.wav # WAV file
python examples/whisper_realtime_stt.py -i audio.pcm --pcm # PCM file
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* fix(asr): handle bfloat16 tensors without PyTorch
Implement native bfloat16 to float32 conversion:
- bfloat16 is upper 16 bits of float32
- Shift uint16 left by 16 bits, view as float32
- Parse safetensors header directly for raw bytes access
No PyTorch dependency required.
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* fix(asr): handle optional bias weights in encoder/decoder
Some Whisper models (e.g., kotoba-whisper) don't have bias terms
for K projection. Handle None weights gracefully with _to_gpu helper.
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* feat(examples): add microphone device selection options
New options for whisper_realtime_stt.py:
- --list-devices: List available audio input devices
- --select-device (-s): Interactively select device at startup
- --device (-d): Specify device by index
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* fix(asr): use to_numpy() instead of numpy() for GPUArray
GPUArray uses to_numpy() method, not numpy().
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* fix(asr): convert GPUArray to numpy before mel spectrogram computation
pad_or_trim returns GPUArray but _compute_mel_spectrogram expects numpy.
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* feat(core): add scalar arithmetic support to GPUArray
GPUArray now supports scalar (int/float) operands for +, -, *, / operators.
Added __radd__, __rsub__, __rmul__, __rtruediv__ for reverse operations.
This enables expressions like `(mel + 4.0) / 4.0` directly on GPUArray.
Updated normalize_mel to use GPUArray scalar ops instead of numpy fallback.
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* feat(core): add transpose and reshape methods to GPUArray
- transpose(*axes): Permute array axes (e.g., transpose(0, 2, 1))
- T property: Transpose shorthand for 2D matrices
- reshape(*shape): Reshape array with -1 dimension inference
Required for Whisper encoder/decoder attention computations.
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* feat(core): add __getitem__ for array indexing and slicing
Supports NumPy-style indexing:
- Integer indexing: arr[0]
- Slicing: arr[:10], arr[1:5]
- Multi-dimensional: arr[0, :, 1:3]
Required for positional embedding slicing in Whisper encoder/decoder.
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* fix(asr): fix positional embedding shape mismatch in encoder/decoder
- Clamp seq_len to max available positions in encoder
- Add explicit batch dimension reshape for positions before add
- GPUArray.add() doesn't support broadcasting, so explicit reshape needed
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* fix(asr): complete Whisper inference pipeline
- Add scalar arithmetic ops to GPUArray (__add__, __sub__, __mul__, __truediv__)
- Add GPUArray.transpose(), .T, .reshape(), __getitem__ for tensor ops
- Add broadcasting support in GPUArray.__add__
- Fix layernorm to support 3D input [batch, seq_len, features]
- Fix encoder/decoder _linear to handle 3D tensors properly
- Add _batched_matmul for 4D attention computation
- Fix temperature=0 divide-by-zero in decoder.generate()
- Add sample_rate param to WhisperModel.transcribe()
- Add generic linear interpolation GPU resampler for arbitrary sample rates
Tested: examples/haru_Info_04.wav -> "いらっしゃいませ" (correct)
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* feat(ops): add GPU kernels for 4D tensor operations
- Add CUTLASS-based batched_matmul for 4D tensors (TF32)
- Uses strided batched GEMM for attention operations
- TF32 precision with ~1e-2 tolerance
- Add GPU softmax for 2D/3D/4D tensors (axis=-1)
- Flattens leading dimensions, reuses existing kernel
- Add transpose_4d_0213 for attention transpose pattern
- [batch, seq, heads, dim] -> [batch, heads, seq, dim]
- Supports float32/float16/bfloat16
- Update GPUArray.reshape() to use native reshape_copy
- Avoids CPU roundtrip for reshape operations
- Handles -1 dimension inference on Python side
Correctness verified with NumPy reference.
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* fix(ops): SM 120 (Blackwell) compatibility for CUTLASS/cuBLASLt
SM 120 (RTX 5090) has compatibility issues with current CUTLASS/cuBLASLt:
- CUTLASS 2.x/3.x FP32/FP16/BF16 kernels fail on SM 120
- cuBLASLt AlgoGetHeuristic returns NOT_SUPPORTED (status 15)
Changes:
- native/ops/matmul_cutlass.cuh: Disable CUTLASS for SM >= 120
- native/ops/matmul/matmul.cu: Auto-enable TF32 TensorCore on SM 120
- native/jit/cublaslt_loader.cpp: Disable cuBLASLt on SM >= 120
Whisper ASR GPU kernel integration:
- encoder.py/decoder.py: Use GPU softmax() and batched_matmul()
- matmul.py: Add CPU fallback for batched_matmul when CUTLASS fails
Benchmark (RTX 5090, SM 120):
- Whisper encoder: 19484ms -> 8181ms (2.4x speedup)
- RTF: ~40x -> ~22x (1.8x improvement)
- Remaining bottleneck: batched_matmul CPU fallback
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* feat(build): default to CUDA 13.1, add FP8 SM120 infrastructure
- Update build.sh default: CUDA 12.9 -> 13.1, SM 120 -> 120a
- Add FP8 SM120 GEMM implementation (disabled due to CUTLASS bug #2902)
- Add Python bindings and API for FP8 SM120 matmul
- Update CMakeLists.txt to include matmul_fp8_sm120.cu
Note: FP8 SM120 code is disabled via PYGPUKIT_ENABLE_FP8_SM120 macro.
CUTLASS has a misalignment bug (partition_S drops alignment from 1024->8
bytes, LDSM requires 16). Will re-enable when CUTLASS fixes issue #2902.
Tracking:
- Upstream: NVIDIA/cutlass#2902
- Local: #107
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* fix(ci): use SM 120a for full accelerated features
Update CMAKE_CUDA_ARCHITECTURES from 120 to 120a in CI/CD workflows.
SM 120a enables tensor cores and block-scaled MMA for Blackwell GeForce.
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* feat(fp8): add SM90 (Hopper) FP8 GEMM fallback for SM120
Add FP8 GEMM implementation for SM90 (Hopper) as fallback path.
SM120 (Blackwell GeForce) is blocked by CUTLASS bug #2902.
Changes:
- Add native/ops/matmul/matmul_fp8_sm90.cu with Hopper TMA-based FP8
- Enable CUTLASS_ARCH_MMA_SM90_SUPPORTED for SM100/SM120 builds
- Add fp8_available(), fp8_sm90_available() availability checks
- Add matmul_fp8() auto-dispatch function
- Add matmul_fp8_sm90() for explicit SM90 backend
Note: SM90 FP8 is restricted to actual Hopper GPUs (SM90-99) because
Hopper TMA-based kernels cause initialization failures on Blackwell.
FP8 support for RTX 5090 awaits CUTLASS fix for #2902.
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* feat(fp8): add SM100 FP8 GEMM (Blackwell datacenter)
Add FP8 GEMM implementation for SM100 (Blackwell datacenter B100/B200):
- Based on CUTLASS example 81 (blackwell_gemm_blockwise)
- Uses tcgen05 tensor cores with blockwise scaling
- FP32 input -> FP8 E4M3 quantization -> GEMM -> BF16 -> FP32 output
Note: SM100 kernel does NOT work on SM120 (RTX 5090) - fails with
"initialize failed: 7" (kErrorInternal). The tcgen05-based schedules
are specific to datacenter Blackwell, not GeForce Blackwell.
API:
- fp8_sm100_available(): Check SM100 FP8 availability
- matmul_fp8_sm100(A, B): FP8 GEMM for SM100
Tested on RTX 5090 (SM120):
- SM100 kernel compiles but fails at runtime
- FP8 on SM120 still blocked by CUTLASS bug #2902
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* fix(cutlass): SM120 fallback to CUTLASS 2.x TensorCore kernels
SM120 (Blackwell GeForce / RTX 5090) now uses CUTLASS 2.x (SM86 tier)
kernels as fallback since:
- CUTLASS 4.x SM120 kernels only support FP8, not FP32/FP16/BF16
- SM100/SM90 specific kernels don't work on SM120 (different tensor gen)
Changes:
- is_sm_supported() now returns true for SM120+
- gemm_tf32/fp16/bf16 dispatch: SM120 uses SM86 5-stage kernel
- Removed SM89 6-stage special case (use SM86 for stability)
Tested on RTX 5090 (SM120):
- FP32 matmul: PASS (TensorCore TF32, rel_err < 4e-4)
- batched_matmul: PASS (TensorCore TF32, rel_err < 3e-4)
- BF16 matmul: PASS (TensorCore BF16, rel_err < 4e-3)
No cuBLAS/cuBLASLt fallback, no CPU fallback - pure CUTLASS TensorCore.
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* feat(gemv): add CUTLASS-based GEMV kernel for M=1 decode path
Initial implementation of GEMV (matrix-vector multiply) optimized for LLM
decode (M=1). This provides a cuBLASLt-free fallback for GEMV operations.
Implementation details:
- BF16, FP16, FP32 kernels with FP32 accumulation
- Batched GEMV for continuous batching support
- Block size 256 (8 warps), TILE_N=256, UNROLL_K=8
- Uses __ldg() for read-only cache optimization
- FMA accumulation with proper alpha/beta scaling
Test results (RTX 5090 SM120):
- BF16 GEMV: 6/6 PASS (max_rel_err < 0.4%)
- FP16 GEMV: 3/3 PASS (max_rel_err < 0.05%)
- FP32 GEMV: 3/3 PASS (max_rel_err < 0.2%)
- Batched BF16: 3/3 PASS
Benchmark vs cuBLASLt:
- Current: 16-44% of cuBLASLt performance
- cuBLASLt uses hand-tuned assembly, our naive scalar FMA is slower
- Optimization opportunities identified: vectorized loads, shared memory
tiling, warp specialization
Files:
- gemv_cutlass.cuh: Main kernel implementation
- test_gemv.cu: Correctness tests vs CPU reference
- benchmark_gemv.cu: Performance comparison vs cuBLASLt
- build_test.bat, build_benchmark.bat: Build scripts
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* perf(gemv): add vectorized BF16x2 loads for 25-40% speedup
Optimization: Use __nv_bfloat162 vectorized loads for the A vector
instead of scalar BF16 loads. This reduces memory transactions
since A is broadcast to all threads.
Changes:
- Added ldg_bf16x2() helper for vectorized 32-bit loads
- Updated gemv_bf16_kernel to use 4x BF16x2 loads per iteration
- Updated gemv_bf16_batched_kernel with same optimization
Benchmark results (RTX 5090 SM120):
- 768x768: 20.51 -> 15.31 us (25% faster)
- 4096x4096: 94.97 -> 63.80 us (33% faster)
- 8192x8192: 384.19 -> 231.12 us (40% faster)
- 16384x16384: 802.14 -> 501.77 us (37% faster)
Gap to cuBLASLt improved: 16-44% -> 25-69%
All correctness tests still pass (15/15).
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* feat(gemv): add per-size tuning with if constexpr template dispatch
Add configuration structs for different matrix size ranges:
- GemvConfigSmallK (K < 2048): UNROLL_K=4
- GemvConfig (default): UNROLL_K=8
- GemvConfigLargeK (K > 8192): UNROLL_K=16
- GemvConfigSmallN (N < 1024): BLOCK_SIZE=128
- GemvConfigLarge (K > 8192 && N > 8192): UNROLL_K=16
Use if constexpr for proper template-based unrolling:
- UNROLL_K=4: 2 bfloat162 loads (4 values)
- UNROLL_K=8: 4 bfloat162 loads (8 values)
- UNROLL_K=16: 8 bfloat162 loads (16 values)
Applied to both gemv_bf16_kernel and gemv_bf16_batched_kernel.
Test results (RTX 5090 SM120): 15/15 PASS
Benchmark (RTX 5090):
- 16384x16384: 0.93x cuBLASLt (720us vs 670us)
- 8192x8192: 0.41x cuBLASLt (235us vs 97us)
- cuBLASLt still faster due to hand-tuned assembly
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* feat(transpose): add native GPU transpose kernels for issue #106
Add native CUDA transpose kernels for common axis permutation patterns:
- 3D (0,2,1): transpose_3d_012 - swaps last two axes
- 4D (0,1,3,2): transpose_4d_0132 - swaps last two axes (K^T in attention)
GPUArray.transpose() now uses native GPU kernels for:
- 2D (1,0): matmul.transpose()
- 3D (1,0,2): tensor.transpose_3d_021()
- 3D (0,2,1): tensor.transpose_3d_012() [NEW]
- 4D (0,2,1,3): tensor.transpose_4d_0213()
- 4D (0,1,3,2): tensor.transpose_4d_0132() [NEW]
- Other patterns: CPU fallback
Closes #106
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* feat(fp8): SM120 FP8 GEMM with CUTLASS alignment workarounds
- Fix CUTLASS Issue #2902: LDSM alignment workaround with runtime check
- Fix CUTLASS Issue #2905: TMA descriptor 64-byte alignment
- Add FP8 E4M3 test with CPU-side quantization simulation
- Update matmul_fp8_sm120.cu with trivial blockwise scale config
Test results (RTX 5090, SM120a):
- 128x128x128: PASS (rel_err < 10%)
- 256x256x256: PASS
- 512x512x512: PASS
Note: CUTLASS patches applied locally in third_party/cutlass
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* wip(fp8): add BF16 I/O FP8 GEMM for SM120 (not working yet)
Add FP8 GEMM kernel that takes BF16 inputs and produces BF16 output:
- BF16 -> FP8 E4M3 quantize -> CUTLASS GEMM -> BF16
Data flow: BF16 input -> FP8 quantize -> [FP8xFP8, FP32 accum] -> BF16 output
Status: CUTLASS run() returns kInvalid (status=7) - needs debugging.
The FP32 version works correctly, issue likely in kernel instantiation.
Files added:
- matmul_fp8_bf16_sm120.cu: BF16 I/O kernel
- test_fp8_bf16_sm120.cu: Test file
- build_fp8_bf16_test.bat: Build script
- Python bindings and wrappers
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* chore(deps): switch CUTLASS to fork with SM120 alignment fixes
Switch from NVIDIA/cutlass to m96-chan/cutlass fork with fixes for
"misaligned address" crashes on SM120 (RTX 5090).
Branch: fix/sm120-alignment (based on v4.3.4)
Fixes applied to CUTLASS:
- alignas(64) for TMA descriptors (prefetch.tensormap requirement)
- alignas(128) for smem_SFA/SFB scale factor storage
- Applies to SM90/SM100/SM120 epilogue and mainloop collectives
Related upstream issues:
- NVIDIA/cutlass#2902
- NVIDIA/cutlass#2905
- NVIDIA/cutlass#2906
* feat(nvf4): add NVF4 BF16 GEMM kernel for SM120
Add NVF4 (4-bit float_e2m1_t) GEMM with BF16 I/O for Blackwell GeForce.
Based on CUTLASS example 79a with alignment fixes from forked CUTLASS.
Features:
- matmul_nvf4_bf16_sm120(): Python API for NVF4 GEMM
- nvf4_bf16_sm120_available(): Runtime availability check
- 128KB minimum allocation for Blackwell TMA driver workaround
- Alignment checks for TMA descriptor requirements
Current status:
- Kernel executes without crash (alignment fixes working)
- Skeleton implementation (internal test data, not using input)
- Performance: ~1 TFLOPS (vs 3 TFLOPS for optimized 79a)
TODO for production use:
- Implement GPU-side BF16 -> NVF4 quantization
- Use actual input data instead of internal buffers
- Buffer reuse to avoid per-call allocation
- Remove debug output
Tested on RTX 5090 (SM120a) with CUDA 13.1.
* refactor(fp8): remove redundant FP8 BF16 SM120 variant
Remove matmul_fp8_bf16_sm120 and related code. The FP8 with BF16 I/O
variant is redundant - the existing FP8 SM120 kernel (matmul_fp8_sm120)
already handles FP32 I/O which is more practical.
For BF16 I/O with reduced precision, use NVF4 (matmul_nvf4_bf16_sm120)
which provides 2x memory bandwidth advantage.
Removed:
- native/ops/matmul/matmul_fp8_bf16_sm120.cu
- native/ops/matmul/build_fp8_bf16_test.bat
- native/ops/matmul/test_fp8_bf16_sm120.cu
- native/ops/matmul/test_fp8_patched.cu
- Python bindings for fp8_bf16_sm120
* chore: add missing SM120 alignment header and FP8 test
- Add aligned_copy_sm120.cuh (required by matmul_fp8_sm120.cu)
- Add tests/test_fp8_sm120.py for FP8 GEMM validation
- Remove unused development files (batch scripts, old headers)
* feat(gemv): add NVF4 GEMV kernel for SM120 with pre-scaled LUT optimization
NVF4 GEMV for memory-efficient LLM decode (M=1):
- 4-bit NVF4 weights with UE4M3 block scaling (32 elements/scale)
- Pre-scaled LUT optimization: 16 multiplies vs 32 per scale block
- BF16 input/output for compatibility
Benchmark results (RTX 5090):
- LLaMA-7B (K=4096): 1.48-1.57x vs BF16 (acceptable)
- LLaMA-70B (K=8192): 0.92x vs BF16 (NVF4 FASTER)
- Memory reduction: 73% less bandwidth than BF16
API:
- gemv_nvf4_bf16(a, b_data, b_scale) -> output
- quantize_bf16_to_nvf4(input, out_data, out_scale)
- gemv_nvf4_available() -> bool
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* perf(gemv): add UE4M3 scale LUT for NVF4 GEMV
Add 256-entry constant memory LUT for UE4M3 scale factor decoding.
Replaces runtime bit manipulation with single memory access.
Also added experimental multi-column kernel (not used by default)
which showed divergence issues - kept for future reference.
Performance impact: minimal (~1% on some cases)
Large K (8192): NVF4 now 0.98x of BF16 (slightly faster)
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* docs: add GEMV benchmark comparison to README
Add performance comparison table for LLM decode (M=1):
- cuBLASLt vs BF16 GEMV vs NVF4 GEMV
- RTX 5090 (SM120a) benchmark results
- BF16 GEMV: 4-6x faster than cuBLASLt
- NVF4 GEMV: 73% memory reduction, matches BF16 for large K
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* perf(linear): use GEMV for M=1 decode with zero-copy views
Linear layer now uses gemv_bf16 for single-token decode (M=1) with BF16,
bypassing cuBLASLt/matmul for significant speedup.
Benchmark results (RTX 5090, SM120a):
| Layer | K | N | GEMV | matmul | Speedup |
|------------------------|------|-------|--------|---------|---------|
| Qwen-7B hidden | 4096 | 4096 | 101us | 148us | 1.46x |
| Qwen-7B MLP gate/up | 4096 | 11008 | 102us | 135us | 1.33x |
| Qwen-7B MLP down |11008 | 4096 | 238us | 310us | 1.30x |
| Qwen-72B hidden | 8192 | 8192 | 284us | 444us | 1.56x |
| Qwen-72B MLP gate/up | 8192 | 29568 | 427us | 1022us | 2.39x |
| Qwen-72B MLP down |29568 | 8192 | 1058us | 1649us | 1.56x |
Key changes:
- Use view() instead of reshape() for zero-copy tensor manipulation
- GEMV path automatically enabled for M=1 with BF16 dtype
- Can be disabled via Linear._use_gemv = False
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* fix(view): keep source reference to prevent use-after-free
Fixed memory corruption bug in view operations (view(), narrow(), slice_rows())
where the source array's memory was freed when going out of scope, leaving
the view pointing to invalid memory.
Bug symptoms:
- "Failed to copy device to host: invalid argument" on to_numpy()
- NaN values in decode output
Root cause:
- Native GPUArray.narrow() creates a non-owning view
- Python garbage collector freed source before view was done
Fix:
- Add _source_ref attribute to views to keep source alive
- Updated view(), narrow(), and slice_rows() methods
Also fixed Linear GEMV path to skip when out= is provided (CUDA Graph mode)
since GEMV allocates memory internally.
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* feat(cublaslt): add PYGPUKIT_CUBLASLT_SM120 env var for testing
cuBLASLt returns NOT_SUPPORTED (status=15) on SM120 (Blackwell GeForce).
Added environment variable to force-enable for debugging purposes.
Default behavior unchanged: cuBLASLt disabled on SM120, falls back to CUTLASS.
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* feat(nvf4): GPU-side quantization for 170x speedup on SM120
Implemented GPU kernels for BF16→NVF4 quantization directly on device,
eliminating costly D2H→CPU→H2D round-trip copies.
New GPU kernels:
- quantize_A_gpu_kernel: BF16 [M,K] RowMajor → packed NVF4
- quantize_B_gpu_kernel: BF16 [K,N] RowMajor → NVF4 [N,K] ColMajor
- init_scale_factors_kernel: Initialize UE4M3 scale factors to 1.0
Performance (RTX 5090, SM120a):
- Before (CPU quant): 0.81 TFLOPS @ 8K, 1352ms
- After (GPU quant): 141 TFLOPS @ 8K, 7.8ms
- Peak: 252 TFLOPS @ 16K
Also added:
- tests/test_nvf4_bf16_sm120.py with BF16 conversion utilities
- benchmarks/benchmark_nvf4_bf16.py for performance testing
- README.md updated with NVF4-BF16 benchmark results
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* feat(nvf4): add pure NVF4 GEMM benchmark kernel for SM120
Added matmul_nvf4_nvf4_sm120.cu for benchmarking NVF4 tensor core
performance without BF16 quantization overhead.
Pure NVF4 GEMM Performance (RTX 5090, SM120a):
| Size | TFLOPS (median) | TFLOPS (max) |
|------|-----------------|--------------|
| 4096 | 70.63 | 75.13 |
| 8192 | 193.03 | 197.78 |
| 12288 | 293.50 | 304.01 |
| 16384 | 322.84 | 332.77 |
Comparison with BF16 I/O version:
- Pure NVF4: 332 TFLOPS @ 16K
- NVF4-BF16 (with GPU quantization): 252 TFLOPS @ 16K
- Quantization overhead: ~24%
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* perf(nvf4): optimize BF16->NVF4 quantization with branchless + vectorized loads
- Replaced 7-way if-else chain with branchless comparison accumulation
- Added vectorized uint4 loads (8 BF16 elements per thread) for quantize_A
- Updated quantize_B to use 2D tiled grid (16x16) for better cache behavior
Performance improvement (RTX 5090, SM120a):
| Size | Before | After | Improvement |
|------|--------|-------|-------------|
| 8K | 137.65 | 145.04 | +5.4% |
| 16K | 246 | 254.40 | +3.4% |
Quantization overhead reduced from 24% to 21% vs pure NVF4 GEMM.
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* perf(nvf4): eliminate D2D copy by writing to user buffer directly
Benchmark results (RTX 5090 SM120a):
Pure NVF4:
- 4096x4096: 94 TFLOPS (was 65, +45%)
- 8192x8192: 272 TFLOPS (was 191, +42%)
- 16384x16384: 416 TFLOPS (was 332, +25%)
BF16 I/O (with GPU quantization):
- 4096x4096: 65 TFLOPS
- 8192x8192: 174 TFLOPS
- 16384x16384: 314 TFLOPS (was 254, +24%)
Quantization overhead: 24.5%
Key change:
- CUTLASS now writes directly to user-provided D buffer
- Eliminated intermediate dev_D_out allocation and cudaMemcpyAsync D2D copy
- Removed redundant cudaStreamSynchronize at function end
Tile size experiments (all worse):
- 256x128x128: 90 TFLOPS (regression)
- 128x256x128: 94 TFLOPS (regression)
- Stream-K scheduler: 320 TFLOPS (slight regression)
Optimal config remains 128x128x128 with Pingpong schedule.
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* perf(nvf4): use 3-stage pipeline for Pure NVF4 (446 TFLOPS)
Benchmark results (RTX 5090 SM120a):
Pure NVF4 (3-stage pipeline):
- 4096x4096: 96 TFLOPS
- 8192x8192: 270 TFLOPS
- 16384x16384: 446 TFLOPS (+7% from 416)
BF16 I/O (auto stage count - explicit 3 causes init failure):
- 4096x4096: 68 TFLOPS
- 8192x8192: 174 TFLOPS
- 16384x16384: 316 TFLOPS
Total session improvement:
- Pure NVF4: 332 -> 446 TFLOPS (+34%)
- BF16 I/O: 254 -> 316 TFLOPS (+24%)
Stage count experiments:
- 2 (auto): 416 TFLOPS
- 3: 438-446 TFLOPS (optimal)
- 4: 404 TFLOPS (too much smem pressure)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* perf(nvf4): vectorize quantize_B + stream overlap (+5% BF16 I/O)
- quantize_B: shared memory transpose + uint32 packed writes
- Stream overlap: A/B quantization in parallel on 2 streams
- BF16 I/O @ 8K: 169 -> 177 TFLOPS (+4.8%)
- BF16 I/O @ 16K: 310 -> 320 TFLOPS (+3.3%)
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* feat(ops): add missing GPU kernels for inference completeness (#109)
High Priority additions:
- argmax: greedy decode, validation (FP32/FP16/BF16)
- clamp/clip: value clipping (FP32/FP16/BF16)
- where/select: conditional selection (FP32/FP16/BF16)
- ReLU: activation (FP32/FP16/BF16)
- tanh/sigmoid: activation (FP32/FP16/BF16)
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* feat(ops): add Medium Priority kernels (#109)
Reduction:
- min: counterpart to max (FP32/FP16/BF16)
Unary (exp/log already existed):
- sqrt: square root (FP32/FP16/BF16)
- rsqrt: reciprocal sqrt (FP32/FP16/BF16)
- abs: absolute value (FP32/FP16/BF16)
- neg: negate (FP32/FP16/BF16)
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* feat(ops): add remaining Medium and Low Priority kernels (#109)
Medium Priority:
- sum_axis0/sum_axis1: axis-specified reduction (FP32/FP16/BF16)
Low Priority:
- sin/cos: RoPE computation (FP32/FP16/BF16)
- arange: sequence generation (FP32/I32/I64)
- scatter_add: indexed accumulation (FP32/FP16/BF16)
- conv1d: 1D convolution for audio (FP32/FP16)
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* feat(ops): add Python bindings for Issue #109 kernels
Add complete pybind11 bindings and Python wrappers for all new GPU kernels:
- Unary: sin, cos, sqrt, rsqrt, abs, neg
- Reduction: min, argmax, sum_axis
- Elementwise: clamp, where
- NN activation: sigmoid, tanh
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* feat(v0.2.15): FP8 I/O GEMM, Pure NVF4, new math ops
## FP8 I/O GEMM (SM120)
- matmul_fp8_fp8_sm120: FP8 E4M3 input -> FP8 E4M3 output
- matmul_fp8_fp8_blockwise_sm120: FP8 with block-wise scale_A/scale_B
- fp8_fp8_get_scale_sizes: Get required scale factor sizes
- Renamed matmul_fp8_sm120.cu -> matmul_fp8_fp32_sm120.cu for clarity
## Pure NVF4 GEMM
- 3-stage async pipeline (446 TFLOPS on RTX 5090)
- GPU-side BF16->NVF4 quantization
- Branchless vectorized loads
## New Operations
- Math: sin, cos, sqrt, rsqrt, abs, neg
- Comparison: clamp, where
- Activation: sigmoid, tanh
- Reduction: argmax, min, sum_axis
## Other
- uint8/int8 NumPy support in from_numpy
- Updated README.md and docs/api.md
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
---------
Co-authored-by: Claude Opus 4.5 <noreply@anthropic.com>1 parent 17f4831 commit abbced1
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