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Add WaveReadLaneFirst tests #432

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fee4c87
write wavereadlanefirst tests
bob80905 Sep 8, 2025
bc0f73d
add warp bug to fp16/64, and int64. Use bug verbage
bob80905 Sep 8, 2025
e962c17
remove warp bug, add requires statements
bob80905 Sep 8, 2025
4e923d9
add back the xfail for warp
bob80905 Sep 9, 2025
f5fd22c
update wavereadlanefirst tests according to waveactivemaax format
bob80905 Oct 27, 2025
fef4787
add warp xfail bug
bob80905 Oct 27, 2025
c30eb8a
add Intel XFAIL
bob80905 Nov 5, 2025
28fb5ea
add 128 thread test
bob80905 Dec 4, 2025
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272 changes: 272 additions & 0 deletions test/WaveOps/WaveReadLaneFirst.128Threads.test
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Original file line number Diff line number Diff line change
@@ -0,0 +1,272 @@
#--- source.hlsl
#define NUM_MASKS 1
#define NUM_THREADS 128

struct MaskStruct {
int mask[NUM_THREADS];
};

StructuredBuffer<int4> In : register(t0);
RWStructuredBuffer<int4> Out4 : register(u4); // test int4
RWStructuredBuffer<int4> Out5 : register(u5); // constant folding
StructuredBuffer<MaskStruct> Masks : register(t6);

[WaveSize(32)]
[numthreads(NUM_THREADS,1,1)]
void main(uint3 tid : SV_GroupThreadID)
{

for (uint MaskIdx = 0; MaskIdx < NUM_MASKS; MaskIdx++) {
int4 v = In[MaskIdx * NUM_THREADS + tid.x];
const uint OutIdx = MaskIdx * NUM_THREADS + tid.x;
if (Masks[MaskIdx].mask[tid.x]) {
Out4[OutIdx] = WaveReadLaneFirst( v );
}
}

// constant folding case
Out5[0] = WaveReadLaneFirst(int4(1,2,3,4));
}


//--- pipeline.yaml

---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: In
Format: Int32
Stride: 16
# 1 value set, 1 mask, 128 threads, each thread supplies int4(tid, tid+1, tid+2, tid+3)
Data: [
0,1,2,3, 1,2,3,4, 2,3,4,5, 3,4,5,6, 4,5,6,7, 5,6,7,8, 6,7,8,9, 7,8,9,10,
8,9,10,11, 9,10,11,12, 10,11,12,13, 11,12,13,14, 12,13,14,15, 13,14,15,16,
14,15,16,17, 15,16,17,18, 16,17,18,19, 17,18,19,20, 18,19,20,21, 19,20,21,22,
20,21,22,23, 21,22,23,24, 22,23,24,25, 23,24,25,26, 24,25,26,27, 25,26,27,28,
26,27,28,29, 27,28,29,30, 28,29,30,31, 29,30,31,32, 30,31,32,33, 31,32,33,34,
32,33,34,35, 33,34,35,36, 34,35,36,37, 35,36,37,38, 36,37,38,39, 37,38,39,40,
38,39,40,41, 39,40,41,42, 40,41,42,43, 41,42,43,44, 42,43,44,45, 43,44,45,46,
44,45,46,47, 45,46,47,48, 46,47,48,49, 47,48,49,50, 48,49,50,51, 49,50,51,52,
50,51,52,53, 51,52,53,54, 52,53,54,55, 53,54,55,56, 54,55,56,57, 55,56,57,58,
56,57,58,59, 57,58,59,60, 58,59,60,61, 59,60,61,62, 60,61,62,63, 61,62,63,64,
62,63,64,65, 63,64,65,66, 64,65,66,67, 65,66,67,68, 66,67,68,69, 67,68,69,70,
68,69,70,71, 69,70,71,72, 70,71,72,73, 71,72,73,74, 72,73,74,75, 73,74,75,76,
74,75,76,77, 75,76,77,78, 76,77,78,79, 77,78,79,80, 78,79,80,81, 79,80,81,82,
80,81,82,83, 81,82,83,84, 82,83,84,85, 83,84,85,86, 84,85,86,87, 85,86,87,88,
86,87,88,89, 87,88,89,90, 88,89,90,91, 89,90,91,92, 90,91,92,93, 91,92,93,94,
92,93,94,95, 93,94,95,96, 94,95,96,97, 95,96,97,98, 96,97,98,99, 97,98,99,100,
98,99,100,101, 99,100,101,102, 100,101,102,103, 101,102,103,104, 102,103,104,105,
103,104,105,106, 104,105,106,107, 105,106,107,108, 106,107,108,109, 107,108,109,110,
108,109,110,111, 109,110,111,112, 110,111,112,113, 111,112,113,114, 112,113,114,115,
113,114,115,116, 114,115,116,117, 115,116,117,118, 116,117,118,119, 117,118,119,120,
118,119,120,121, 119,120,121,122, 120,121,122,123, 121,122,123,124, 122,123,124,125,
123,124,125,126, 124,125,126,127, 125,126,127,128, 126,127,128,129, 127,128,129,130
]

- Name: Out4
Format: Int32
Stride: 16
FillSize: 2048
- Name: Out5
Format: Int32
Stride: 16
FillSize: 16
- Name: Masks
Format: Int32
Stride: 16
Data: [
0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0,
0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0,
0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0,
0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0 ]

- Name: ExpectedOut4
Format: Int32
Stride: 16
Data: [ 0, 0, 0, 0,
1, 2, 3, 4,
1, 2, 3, 4,
0, 0, 0, 0,
0, 0, 0, 0,
1, 2, 3, 4,
1, 2, 3, 4,
0, 0, 0, 0,
0, 0, 0, 0,
1, 2, 3, 4,
1, 2, 3, 4,
0, 0, 0, 0,
0, 0, 0, 0,
1, 2, 3, 4,
1, 2, 3, 4,
0, 0, 0, 0,
0, 0, 0, 0,
1, 2, 3, 4,
1, 2, 3, 4,
0, 0, 0, 0,
0, 0, 0, 0,
1, 2, 3, 4,
1, 2, 3, 4,
0, 0, 0, 0,
0, 0, 0, 0,
1, 2, 3, 4,
1, 2, 3, 4,
0, 0, 0, 0,
0, 0, 0, 0,
1, 2, 3, 4,
1, 2, 3, 4,
0, 0, 0, 0,
0, 0, 0, 0,
33, 34, 35, 36,
33, 34, 35, 36,
0, 0, 0, 0,
0, 0, 0, 0,
33, 34, 35, 36,
33, 34, 35, 36,
0, 0, 0, 0,
0, 0, 0, 0,
33, 34, 35, 36,
33, 34, 35, 36,
0, 0, 0, 0,
0, 0, 0, 0,
33, 34, 35, 36,
33, 34, 35, 36,
0, 0, 0, 0,
0, 0, 0, 0,
33, 34, 35, 36,
33, 34, 35, 36,
0, 0, 0, 0,
0, 0, 0, 0,
33, 34, 35, 36,
33, 34, 35, 36,
0, 0, 0, 0,
0, 0, 0, 0,
33, 34, 35, 36,
33, 34, 35, 36,
0, 0, 0, 0,
0, 0, 0, 0,
33, 34, 35, 36,
33, 34, 35, 36,
0, 0, 0, 0,
0, 0, 0, 0,
65, 66, 67, 68,
65, 66, 67, 68,
0, 0, 0, 0,
0, 0, 0, 0,
65, 66, 67, 68,
65, 66, 67, 68,
0, 0, 0, 0,
0, 0, 0, 0,
65, 66, 67, 68,
65, 66, 67, 68,
0, 0, 0, 0,
0, 0, 0, 0,
65, 66, 67, 68,
65, 66, 67, 68,
0, 0, 0, 0,
0, 0, 0, 0,
65, 66, 67, 68,
65, 66, 67, 68,
0, 0, 0, 0,
0, 0, 0, 0,
65, 66, 67, 68,
65, 66, 67, 68,
0, 0, 0, 0,
0, 0, 0, 0,
65, 66, 67, 68,
65, 66, 67, 68,
0, 0, 0, 0,
0, 0, 0, 0,
65, 66, 67, 68,
65, 66, 67, 68,
0, 0, 0, 0,
0, 0, 0, 0,
97, 98, 99, 100,
97, 98, 99, 100,
0, 0, 0, 0,
0, 0, 0, 0,
97, 98, 99, 100,
97, 98, 99, 100,
0, 0, 0, 0,
0, 0, 0, 0,
97, 98, 99, 100,
97, 98, 99, 100,
0, 0, 0, 0,
0, 0, 0, 0,
97, 98, 99, 100,
97, 98, 99, 100,
0, 0, 0, 0,
0, 0, 0, 0,
97, 98, 99, 100,
97, 98, 99, 100,
0, 0, 0, 0,
0, 0, 0, 0,
97, 98, 99, 100,
97, 98, 99, 100,
0, 0, 0, 0,
0, 0, 0, 0,
97, 98, 99, 100,
97, 98, 99, 100,
0, 0, 0, 0,
0, 0, 0, 0,
97, 98, 99, 100,
97, 98, 99, 100,
0, 0, 0, 0 ]
- Name: ExpectedOut5
Format: Int32
Stride: 8
Data: [ 1, 2, 3, 4 ]
Results:
- Result: ExpectedOut4
Rule: BufferExact
Actual: Out4
Expected: ExpectedOut4
- Result: ExpectedOut5
Rule: BufferExact
Actual: Out5
Expected: ExpectedOut5
DescriptorSets:
- Resources:
- Name: In
Kind: StructuredBuffer
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
- Name: Out4
Kind: RWStructuredBuffer
DirectXBinding:
Register: 4
Space: 0
VulkanBinding:
Binding: 4
- Name: Out5
Kind: RWStructuredBuffer
DirectXBinding:
Register: 5
Space: 0
VulkanBinding:
Binding: 5
- Name: Masks
Kind: StructuredBuffer
DirectXBinding:
Register: 6
Space: 0
VulkanBinding:
Binding: 6

...
#--- end

# Bug https://github.com/llvm/llvm-project/issues/156775
# XFAIL: Clang

# Bug https://github.com/llvm/offload-test-suite/issues/393
# XFAIL: Metal

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
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