From fee4c8791f4d596910358083927ac78c895f237d Mon Sep 17 00:00:00 2001 From: Joshua Batista Date: Mon, 8 Sep 2025 15:41:26 -0700 Subject: [PATCH 01/10] write wavereadlanefirst tests --- test/WaveOps/WaveReadLaneFirst.fp16.test | 185 ++++++++++++ test/WaveOps/WaveReadLaneFirst.fp32.test | 179 ++++++++++++ test/WaveOps/WaveReadLaneFirst.fp64.test | 179 ++++++++++++ test/WaveOps/WaveReadLaneFirst.int16.test | 331 ++++++++++++++++++++++ test/WaveOps/WaveReadLaneFirst.int32.test | 331 ++++++++++++++++++++++ test/WaveOps/WaveReadLaneFirst.int64.test | 331 ++++++++++++++++++++++ 6 files changed, 1536 insertions(+) create mode 100644 test/WaveOps/WaveReadLaneFirst.fp16.test create mode 100644 test/WaveOps/WaveReadLaneFirst.fp32.test create mode 100644 test/WaveOps/WaveReadLaneFirst.fp64.test create mode 100644 test/WaveOps/WaveReadLaneFirst.int16.test create mode 100644 test/WaveOps/WaveReadLaneFirst.int32.test create mode 100644 test/WaveOps/WaveReadLaneFirst.int64.test diff --git a/test/WaveOps/WaveReadLaneFirst.fp16.test b/test/WaveOps/WaveReadLaneFirst.fp16.test new file mode 100644 index 000000000..be4148ab1 --- /dev/null +++ b/test/WaveOps/WaveReadLaneFirst.fp16.test @@ -0,0 +1,185 @@ +#--- source.hlsl +StructuredBuffer In : register(t0); +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test half2 +RWStructuredBuffer Out3 : register(u3); // test half3 +RWStructuredBuffer Out4 : register(u4); // test half4 +RWStructuredBuffer Out5 : register(u5); // constant folding + +[numthreads(4,1,1)] +void main(uint3 tid : SV_GroupThreadID) +{ + half4 v = In[tid.x]; + + // Mask per "active lane set": only >= N lanes contribute + half s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0; + half s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0; + half s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0; + half s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0; + + half2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : half2(0,0); + half2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : half2(0,0); + half2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : half2(0,0); + half2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : half2(0,0); + + half3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : half3(0,0,0); + half3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : half3(0,0,0); + half3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : half3(0,0,0); + half3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : half3(0,0,0); + + half4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : half4(0,0,0,0); + half4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : half4(0,0,0,0); + half4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : half4(0,0,0,0); + half4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : half4(0,0,0,0); + + half scalars[4] = { s4, s3, s2, s1 }; + half2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; + half3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; + half4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; + + Out1[tid.x].x = scalars[tid.x]; + Out2[tid.x].xy = vec2s[tid.x]; + Out3[tid.x].xyz = vec3s[tid.x]; + Out4[tid.x] = vec4s[tid.x]; + + // constant folding case + Out5[0] = WaveReadLaneFirst(half4(1,2,3,4)); +} + +//--- pipeline.yaml + +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [1, 1, 1] +Buffers: + - Name: In + Format: Float16 + Stride: 8 + # 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 + Data: [ 0x3c00, 0x4900, 0x5640, 0x63d0, 0x4000, 0x4d00, 0x5a40, 0x67d0, 0x4200, 0x4f80, 0x5cb0, 0x69dc, 0x4400, 0x5100, 0x5e40, 0x6bd0 ] + - Name: Out1 + Format: Float16 + Stride: 8 + ZeroInitSize: 32 + - Name: Out2 + Format: Float16 + Stride: 8 + ZeroInitSize: 32 + - Name: Out3 + Format: Float16 + Stride: 8 + ZeroInitSize: 32 + - Name: Out4 + Format: Float16 + Stride: 8 + ZeroInitSize: 32 + - Name: Out5 + Format: Float16 + Stride: 8 + ZeroInitSize: 8 + - Name: ExpectedOut1 + Format: Float16 + Stride: 8 + # 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 + Data: [ 0x3c00, 0x0, 0x0, 0x0, 0x4000, 0x0, 0x0, 0x0, 0x4200, 0x0, 0x0, 0x0, 0x4400, 0x0, 0x0, 0x0 ] + - Name: ExpectedOut2 + Format: Float16 + Stride: 8 + # 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 + Data: [ 0x3c00, 0x4900, 0x0, 0x0, 0x4000, 0x4d00, 0x0, 0x0, 0x4200, 0x4f80, 0x0, 0x0, 0x4400, 0x5100, 0x0, 0x0 ] + - Name: ExpectedOut3 + Format: Float16 + Stride: 8 + # 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 + Data: [ 0x3c00, 0x4900, 0x5640, 0x0, 0x4000, 0x4d00, 0x5a40, 0x0, 0x4200, 0x4f80, 0x5cb0, 0x0, 0x4400, 0x5100, 0x5e40, 0x0 ] + - Name: ExpectedOut4 + Format: Float16 + Stride: 8 + # 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 + Data: [ 0x3c00, 0x4900, 0x5640, 0x63d0, 0x4000, 0x4d00, 0x5a40, 0x67d0, 0x4200, 0x4f80, 0x5cb0, 0x69dc, 0x4400, 0x5100, 0x5e40, 0x6bd0 ] + - Name: ExpectedOut5 + Format: Float16 + Stride: 8 + # 1, 2, 3, 4 + Data: [ 0x3C00, 0x4000, 0x4200, 0x4400 ] +Results: + - Result: ExpectedOut1 + Rule: BufferExact + Actual: Out1 + Expected: ExpectedOut1 + - Result: ExpectedOut2 + Rule: BufferExact + Actual: Out2 + Expected: ExpectedOut2 + - Result: ExpectedOut3 + Rule: BufferExact + Actual: Out3 + Expected: ExpectedOut3 + - Result: ExpectedOut4 + Rule: BufferExact + Actual: Out4 + Expected: ExpectedOut4 + - Result: ExpectedOut5 + Rule: BufferExact + Actual: Out5 + Expected: ExpectedOut5 + +DescriptorSets: + - Resources: + - Name: In + Kind: StructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: Out1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 + - Name: Out2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 2 + Space: 0 + VulkanBinding: + Binding: 2 + - Name: Out3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 3 + Space: 0 + VulkanBinding: + Binding: 3 + - Name: Out4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 4 + Space: 0 + VulkanBinding: + Binding: 4 + - Name: Out5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 5 + Space: 0 + VulkanBinding: + Binding: 5 +... +#--- end + + +# Tracked by https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal + +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang + +# RUN: split-file %s %t +# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.fp32.test b/test/WaveOps/WaveReadLaneFirst.fp32.test new file mode 100644 index 000000000..304802a50 --- /dev/null +++ b/test/WaveOps/WaveReadLaneFirst.fp32.test @@ -0,0 +1,179 @@ +#--- source.hlsl +StructuredBuffer In : register(t0); +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test float2 +RWStructuredBuffer Out3 : register(u3); // test float3 +RWStructuredBuffer Out4 : register(u4); // test float4 +RWStructuredBuffer Out5 : register(u5); // constant folding + +[numthreads(4,1,1)] +void main(uint3 tid : SV_GroupThreadID) +{ + float4 v = In[tid.x]; + + // Mask per "active lane set": only >= N lanes contribute + float s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0; + float s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0; + float s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0; + float s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0; + + float2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : float2(0,0); + float2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : float2(0,0); + float2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : float2(0,0); + float2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : float2(0,0); + + float3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : float3(0,0,0); + float3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : float3(0,0,0); + float3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : float3(0,0,0); + float3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : float3(0,0,0); + + float4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : float4(0,0,0,0); + float4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : float4(0,0,0,0); + float4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : float4(0,0,0,0); + float4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : float4(0,0,0,0); + + float scalars[4] = { s4, s3, s2, s1 }; + float2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; + float3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; + float4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; + + Out1[tid.x].x = scalars[tid.x]; + Out2[tid.x].xy = vec2s[tid.x]; + Out3[tid.x].xyz = vec3s[tid.x]; + Out4[tid.x] = vec4s[tid.x]; + + // constant folding case + Out5[0] = WaveReadLaneFirst(float4(1,2,3,4)); +} + +//--- pipeline.yaml + +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [1, 1, 1] +Buffers: + - Name: In + Format: Float32 + Stride: 16 + Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ] + - Name: Out1 + Format: Float32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out2 + Format: Float32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out3 + Format: Float32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out4 + Format: Float32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out5 + Format: Float32 + Stride: 16 + ZeroInitSize: 16 + - Name: ExpectedOut1 + Format: Float32 + Stride: 16 + Data: [ 1.0, 0.0, 0.0, 0.0, 2.0, 0.0, 0.0, 0.0, 3.0, 0.0, 0.0, 0.0, 4.0, 0.0, 0.0, 0.0 ] + - Name: ExpectedOut2 + Format: Float32 + Stride: 16 + Data: [ 1.0, 10.0, 0.0, 0.0, 2.0, 20.0, 0.0, 0.0, 3.0, 30.0, 0.0, 0.0, 4.0, 40.0, 0.0, 0.0 ] + - Name: ExpectedOut3 + Format: Float32 + Stride: 16 + Data: [ 1.0, 10.0, 100.0, 0.0, 2.0, 20.0, 200.0, 0.0, 3.0, 30.0, 300.0, 0.0, 4.0, 40.0, 400.0, 0.0 ] + - Name: ExpectedOut4 + Format: Float32 + Stride: 16 + Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ] + - Name: ExpectedOut5 + Format: Float32 + Stride: 16 + Data: [ 1, 2, 3, 4 ] +Results: + - Result: ExpectedOut1 + Rule: BufferExact + Actual: Out1 + Expected: ExpectedOut1 + - Result: ExpectedOut2 + Rule: BufferExact + Actual: Out2 + Expected: ExpectedOut2 + - Result: ExpectedOut3 + Rule: BufferExact + Actual: Out3 + Expected: ExpectedOut3 + - Result: ExpectedOut4 + Rule: BufferExact + Actual: Out4 + Expected: ExpectedOut4 + - Result: ExpectedOut5 + Rule: BufferExact + Actual: Out5 + Expected: ExpectedOut5 + +DescriptorSets: + - Resources: + - Name: In + Kind: StructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: Out1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 + - Name: Out2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 2 + Space: 0 + VulkanBinding: + Binding: 2 + - Name: Out3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 3 + Space: 0 + VulkanBinding: + Binding: 3 + - Name: Out4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 4 + Space: 0 + VulkanBinding: + Binding: 4 + - Name: Out5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 5 + Space: 0 + VulkanBinding: + Binding: 5 +... +#--- end + + +# Tracked by https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal + +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang + +# RUN: split-file %s %t +# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.fp64.test b/test/WaveOps/WaveReadLaneFirst.fp64.test new file mode 100644 index 000000000..6d33f9316 --- /dev/null +++ b/test/WaveOps/WaveReadLaneFirst.fp64.test @@ -0,0 +1,179 @@ +#--- source.hlsl +StructuredBuffer In : register(t0); +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test double2 +RWStructuredBuffer Out3 : register(u3); // test double3 +RWStructuredBuffer Out4 : register(u4); // test double4 +RWStructuredBuffer Out5 : register(u5); // constant folding + +[numthreads(4,1,1)] +void main(uint3 tid : SV_GroupThreadID) +{ + double4 v = In[tid.x]; + + // Mask per "active lane set": only >= N lanes contribute + double s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0; + double s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0; + double s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0; + double s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0; + + double2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : double2(0,0); + double2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : double2(0,0); + double2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : double2(0,0); + double2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : double2(0,0); + + double3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : double3(0,0,0); + double3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : double3(0,0,0); + double3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : double3(0,0,0); + double3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : double3(0,0,0); + + double4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : double4(0,0,0,0); + double4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : double4(0,0,0,0); + double4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : double4(0,0,0,0); + double4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : double4(0,0,0,0); + + double scalars[4] = { s4, s3, s2, s1 }; + double2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; + double3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; + double4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; + + Out1[tid.x].x = scalars[tid.x]; + Out2[tid.x].xy = vec2s[tid.x]; + Out3[tid.x].xyz = vec3s[tid.x]; + Out4[tid.x] = vec4s[tid.x]; + + // constant folding case + Out5[0] = WaveReadLaneFirst(double4(1,2,3,4)); +} + +//--- pipeline.yaml + +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [1, 1, 1] +Buffers: + - Name: In + Format: Float64 + Stride: 32 + Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ] + - Name: Out1 + Format: Float64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out2 + Format: Float64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out3 + Format: Float64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out4 + Format: Float64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out5 + Format: Float64 + Stride: 32 + ZeroInitSize: 32 + - Name: ExpectedOut1 + Format: Float64 + Stride: 32 + Data: [ 1.0, 0.0, 0.0, 0.0, 2.0, 0.0, 0.0, 0.0, 3.0, 0.0, 0.0, 0.0, 4.0, 0.0, 0.0, 0.0 ] + - Name: ExpectedOut2 + Format: Float64 + Stride: 32 + Data: [ 1.0, 10.0, 0.0, 0.0, 2.0, 20.0, 0.0, 0.0, 3.0, 30.0, 0.0, 0.0, 4.0, 40.0, 0.0, 0.0 ] + - Name: ExpectedOut3 + Format: Float64 + Stride: 32 + Data: [ 1.0, 10.0, 100.0, 0.0, 2.0, 20.0, 200.0, 0.0, 3.0, 30.0, 300.0, 0.0, 4.0, 40.0, 400.0, 0.0 ] + - Name: ExpectedOut4 + Format: Float64 + Stride: 32 + Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ] + - Name: ExpectedOut5 + Format: Float64 + Stride: 32 + Data: [ 1, 2, 3, 4 ] +Results: + - Result: ExpectedOut1 + Rule: BufferExact + Actual: Out1 + Expected: ExpectedOut1 + - Result: ExpectedOut2 + Rule: BufferExact + Actual: Out2 + Expected: ExpectedOut2 + - Result: ExpectedOut3 + Rule: BufferExact + Actual: Out3 + Expected: ExpectedOut3 + - Result: ExpectedOut4 + Rule: BufferExact + Actual: Out4 + Expected: ExpectedOut4 + - Result: ExpectedOut5 + Rule: BufferExact + Actual: Out5 + Expected: ExpectedOut5 + +DescriptorSets: + - Resources: + - Name: In + Kind: StructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: Out1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 + - Name: Out2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 2 + Space: 0 + VulkanBinding: + Binding: 2 + - Name: Out3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 3 + Space: 0 + VulkanBinding: + Binding: 3 + - Name: Out4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 4 + Space: 0 + VulkanBinding: + Binding: 4 + - Name: Out5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 5 + Space: 0 + VulkanBinding: + Binding: 5 +... +#--- end + + +# Tracked by https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal + +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang + +# RUN: split-file %s %t +# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.int16.test b/test/WaveOps/WaveReadLaneFirst.int16.test new file mode 100644 index 000000000..ccf57ed11 --- /dev/null +++ b/test/WaveOps/WaveReadLaneFirst.int16.test @@ -0,0 +1,331 @@ +#--- source.hlsl +StructuredBuffer In : register(t0); +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test int16_t2 +RWStructuredBuffer Out3 : register(u3); // test int16_t3 +RWStructuredBuffer Out4 : register(u4); // test int16_t4 +RWStructuredBuffer Out5 : register(u5); // constant folding + +// uint16_ts +StructuredBuffer UIn : register(t6); +RWStructuredBuffer UOut1 : register(u7); +RWStructuredBuffer UOut2 : register(u8); +RWStructuredBuffer UOut3 : register(u9); +RWStructuredBuffer UOut4 : register(u10); +RWStructuredBuffer UOut5 : register(u11); + +[numthreads(4,1,1)] +void main(uint3 tid : SV_GroupThreadID) +{ + int16_t4 v = In[tid.x]; + + // Mask per "active lane set": only >= N lanes contribute + int16_t s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0; + int16_t s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0; + int16_t s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0; + int16_t s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0; + + int16_t2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : int16_t2(0,0); + int16_t2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : int16_t2(0,0); + int16_t2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : int16_t2(0,0); + int16_t2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : int16_t2(0,0); + + int16_t3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : int16_t3(0,0,0); + int16_t3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : int16_t3(0,0,0); + int16_t3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : int16_t3(0,0,0); + int16_t3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : int16_t3(0,0,0); + + int16_t4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : int16_t4(0,0,0,0); + int16_t4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : int16_t4(0,0,0,0); + int16_t4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : int16_t4(0,0,0,0); + int16_t4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : int16_t4(0,0,0,0); + + int16_t scalars[4] = { s4, s3, s2, s1 }; + int16_t2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; + int16_t3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; + int16_t4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; + + Out1[tid.x].x = scalars[tid.x]; + Out2[tid.x].xy = vec2s[tid.x]; + Out3[tid.x].xyz = vec3s[tid.x]; + Out4[tid.x] = vec4s[tid.x]; + + // constant folding case + Out5[0] = WaveReadLaneFirst(int16_t4(1,2,3,4)); + + // UINT16_t case + + uint16_t4 uv = UIn[tid.x]; + + // Mask per "active lane set": only >= N lanes contribute + uint16_t us1 = tid.x >= 3 ? WaveReadLaneFirst( uv.x ) : 0; + uint16_t us2 = tid.x >= 2 ? WaveReadLaneFirst( uv.x ) : 0; + uint16_t us3 = tid.x >= 1 ? WaveReadLaneFirst( uv.x ) : 0; + uint16_t us4 = tid.x >= 0 ? WaveReadLaneFirst( uv.x ) : 0; + + uint16_t2 uv2_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xy ) : uint16_t2(0,0); + uint16_t2 uv2_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xy ) : uint16_t2(0,0); + uint16_t2 uv2_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xy ) : uint16_t2(0,0); + uint16_t2 uv2_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xy ) : uint16_t2(0,0); + + uint16_t3 uv3_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xyz ) : uint16_t3(0,0,0); + uint16_t3 uv3_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xyz ) : uint16_t3(0,0,0); + uint16_t3 uv3_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xyz ) : uint16_t3(0,0,0); + uint16_t3 uv3_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xyz ) : uint16_t3(0,0,0); + + uint16_t4 uv4_1 = tid.x >= 3 ? WaveReadLaneFirst( uv ) : uint16_t4(0,0,0,0); + uint16_t4 uv4_2 = tid.x >= 2 ? WaveReadLaneFirst( uv ) : uint16_t4(0,0,0,0); + uint16_t4 uv4_3 = tid.x >= 1 ? WaveReadLaneFirst( uv ) : uint16_t4(0,0,0,0); + uint16_t4 uv4_4 = tid.x >= 0 ? WaveReadLaneFirst( uv ) : uint16_t4(0,0,0,0); + + uint16_t uscalars[4] = { us4, us3, us2, us1 }; + uint16_t2 uvec2s [4] = { uv2_4, uv2_3, uv2_2, uv2_1 }; + uint16_t3 uvec3s [4] = { uv3_4, uv3_3, uv3_2, uv3_1 }; + uint16_t4 uvec4s [4] = { uv4_4, uv4_3, uv4_2, uv4_1 }; + + UOut1[tid.x].x = uscalars[tid.x]; + UOut2[tid.x].xy = uvec2s[tid.x]; + UOut3[tid.x].xyz = uvec3s[tid.x]; + UOut4[tid.x] = uvec4s[tid.x]; + + // constant folding case + UOut5[0] = WaveReadLaneFirst(uint16_t4(1,2,3,4)); +} + +//--- pipeline.yaml + +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [1, 1, 1] +Buffers: + - Name: In + Format: Int16 + Stride: 8 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: Out1 + Format: Int16 + Stride: 8 + ZeroInitSize: 32 + - Name: Out2 + Format: Int16 + Stride: 8 + ZeroInitSize: 32 + - Name: Out3 + Format: Int16 + Stride: 8 + ZeroInitSize: 32 + - Name: Out4 + Format: Int16 + Stride: 8 + ZeroInitSize: 32 + - Name: Out5 + Format: Int16 + Stride: 8 + ZeroInitSize: 8 + - Name: ExpectedOut1 + Format: Int16 + Stride: 8 + Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + - Name: ExpectedOut2 + Format: Int16 + Stride: 8 + Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + - Name: ExpectedOut3 + Format: Int16 + Stride: 8 + Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + - Name: ExpectedOut4 + Format: Int16 + Stride: 8 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: ExpectedOut5 + Format: Int16 + Stride: 8 + Data: [ 1, 2, 3, 4 ] + - Name: UIn + Format: UInt16 + Stride: 8 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: UOut1 + Format: UInt16 + Stride: 8 + ZeroInitSize: 32 + - Name: UOut2 + Format: UInt16 + Stride: 8 + ZeroInitSize: 32 + - Name: UOut3 + Format: UInt16 + Stride: 8 + ZeroInitSize: 32 + - Name: UOut4 + Format: UInt16 + Stride: 8 + ZeroInitSize: 32 + - Name: UOut5 + Format: UInt16 + Stride: 8 + ZeroInitSize: 8 + - Name: UExpectedOut1 + Format: UInt16 + Stride: 8 + Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + - Name: UExpectedOut2 + Format: UInt16 + Stride: 8 + Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + - Name: UExpectedOut3 + Format: UInt16 + Stride: 8 + Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + - Name: UExpectedOut4 + Format: UInt16 + Stride: 8 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: UExpectedOut5 + Format: UInt16 + Stride: 8 + Data: [ 1, 2, 3, 4 ] +Results: + - Result: ExpectedOut1 + Rule: BufferExact + Actual: Out1 + Expected: ExpectedOut1 + - Result: ExpectedOut2 + Rule: BufferExact + Actual: Out2 + Expected: ExpectedOut2 + - Result: ExpectedOut3 + Rule: BufferExact + Actual: Out3 + Expected: ExpectedOut3 + - Result: ExpectedOut4 + Rule: BufferExact + Actual: Out4 + Expected: ExpectedOut4 + - Result: ExpectedOut5 + Rule: BufferExact + Actual: Out5 + Expected: ExpectedOut5 + - Result: UExpectedOut1 + Rule: BufferExact + Actual: UOut1 + Expected: UExpectedOut1 + - Result: UExpectedOut2 + Rule: BufferExact + Actual: UOut2 + Expected: UExpectedOut2 + - Result: UExpectedOut3 + Rule: BufferExact + Actual: UOut3 + Expected: UExpectedOut3 + - Result: UExpectedOut4 + Rule: BufferExact + Actual: UOut4 + Expected: UExpectedOut4 + - Result: UExpectedOut5 + Rule: BufferExact + Actual: UOut5 + Expected: UExpectedOut5 +DescriptorSets: + - Resources: + - Name: In + Kind: StructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: Out1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 + - Name: Out2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 2 + Space: 0 + VulkanBinding: + Binding: 2 + - Name: Out3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 3 + Space: 0 + VulkanBinding: + Binding: 3 + - Name: Out4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 4 + Space: 0 + VulkanBinding: + Binding: 4 + - Name: Out5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 5 + Space: 0 + VulkanBinding: + Binding: 5 + - Name: UIn + Kind: StructuredBuffer + DirectXBinding: + Register: 6 + Space: 0 + VulkanBinding: + Binding: 6 + - Name: UOut1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 7 + Space: 0 + VulkanBinding: + Binding: 7 + - Name: UOut2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 8 + Space: 0 + VulkanBinding: + Binding: 8 + - Name: UOut3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 9 + Space: 0 + VulkanBinding: + Binding: 9 + - Name: UOut4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 10 + Space: 0 + VulkanBinding: + Binding: 10 + - Name: UOut5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 11 + Space: 0 + VulkanBinding: + Binding: 11 + +... +#--- end + + +# Tracked by https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal + +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang + +# RUN: split-file %s %t +# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.int32.test b/test/WaveOps/WaveReadLaneFirst.int32.test new file mode 100644 index 000000000..ba5876689 --- /dev/null +++ b/test/WaveOps/WaveReadLaneFirst.int32.test @@ -0,0 +1,331 @@ +#--- source.hlsl +StructuredBuffer In : register(t0); +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test int2 +RWStructuredBuffer Out3 : register(u3); // test int3 +RWStructuredBuffer Out4 : register(u4); // test int4 +RWStructuredBuffer Out5 : register(u5); // constant folding + +// uints +StructuredBuffer UIn : register(t6); +RWStructuredBuffer UOut1 : register(u7); +RWStructuredBuffer UOut2 : register(u8); +RWStructuredBuffer UOut3 : register(u9); +RWStructuredBuffer UOut4 : register(u10); +RWStructuredBuffer UOut5 : register(u11); + +[numthreads(4,1,1)] +void main(uint3 tid : SV_GroupThreadID) +{ + int4 v = In[tid.x]; + + // Mask per "active lane set": only >= N lanes contribute + int s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0; + int s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0; + int s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0; + int s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0; + + int2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : int2(0,0); + int2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : int2(0,0); + int2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : int2(0,0); + int2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : int2(0,0); + + int3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : int3(0,0,0); + int3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : int3(0,0,0); + int3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : int3(0,0,0); + int3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : int3(0,0,0); + + int4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : int4(0,0,0,0); + int4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : int4(0,0,0,0); + int4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : int4(0,0,0,0); + int4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : int4(0,0,0,0); + + int scalars[4] = { s4, s3, s2, s1 }; + int2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; + int3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; + int4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; + + Out1[tid.x].x = scalars[tid.x]; + Out2[tid.x].xy = vec2s[tid.x]; + Out3[tid.x].xyz = vec3s[tid.x]; + Out4[tid.x] = vec4s[tid.x]; + + // constant folding case + Out5[0] = WaveReadLaneFirst(int4(1,2,3,4)); + + // UINT case + + uint4 uv = UIn[tid.x]; + + // Mask per "active lane set": only >= N lanes contribute + uint us1 = tid.x >= 3 ? WaveReadLaneFirst( uv.x ) : 0; + uint us2 = tid.x >= 2 ? WaveReadLaneFirst( uv.x ) : 0; + uint us3 = tid.x >= 1 ? WaveReadLaneFirst( uv.x ) : 0; + uint us4 = tid.x >= 0 ? WaveReadLaneFirst( uv.x ) : 0; + + uint2 uv2_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xy ) : uint2(0,0); + uint2 uv2_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xy ) : uint2(0,0); + uint2 uv2_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xy ) : uint2(0,0); + uint2 uv2_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xy ) : uint2(0,0); + + uint3 uv3_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xyz ) : uint3(0,0,0); + uint3 uv3_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xyz ) : uint3(0,0,0); + uint3 uv3_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xyz ) : uint3(0,0,0); + uint3 uv3_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xyz ) : uint3(0,0,0); + + uint4 uv4_1 = tid.x >= 3 ? WaveReadLaneFirst( uv ) : uint4(0,0,0,0); + uint4 uv4_2 = tid.x >= 2 ? WaveReadLaneFirst( uv ) : uint4(0,0,0,0); + uint4 uv4_3 = tid.x >= 1 ? WaveReadLaneFirst( uv ) : uint4(0,0,0,0); + uint4 uv4_4 = tid.x >= 0 ? WaveReadLaneFirst( uv ) : uint4(0,0,0,0); + + uint uscalars[4] = { us4, us3, us2, us1 }; + uint2 uvec2s [4] = { uv2_4, uv2_3, uv2_2, uv2_1 }; + uint3 uvec3s [4] = { uv3_4, uv3_3, uv3_2, uv3_1 }; + uint4 uvec4s [4] = { uv4_4, uv4_3, uv4_2, uv4_1 }; + + UOut1[tid.x].x = uscalars[tid.x]; + UOut2[tid.x].xy = uvec2s[tid.x]; + UOut3[tid.x].xyz = uvec3s[tid.x]; + UOut4[tid.x] = uvec4s[tid.x]; + + // constant folding case + UOut5[0] = WaveReadLaneFirst(uint4(1,2,3,4)); +} + +//--- pipeline.yaml + +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [1, 1, 1] +Buffers: + - Name: In + Format: Int32 + Stride: 16 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: Out1 + Format: Int32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out2 + Format: Int32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out3 + Format: Int32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out4 + Format: Int32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out5 + Format: Int32 + Stride: 16 + ZeroInitSize: 16 + - Name: ExpectedOut1 + Format: Int32 + Stride: 16 + Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + - Name: ExpectedOut2 + Format: Int32 + Stride: 16 + Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + - Name: ExpectedOut3 + Format: Int32 + Stride: 16 + Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + - Name: ExpectedOut4 + Format: Int32 + Stride: 16 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: ExpectedOut5 + Format: Int32 + Stride: 16 + Data: [ 1, 2, 3, 4 ] + - Name: UIn + Format: UInt32 + Stride: 16 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: UOut1 + Format: UInt32 + Stride: 16 + ZeroInitSize: 64 + - Name: UOut2 + Format: UInt32 + Stride: 16 + ZeroInitSize: 64 + - Name: UOut3 + Format: UInt32 + Stride: 16 + ZeroInitSize: 64 + - Name: UOut4 + Format: UInt32 + Stride: 16 + ZeroInitSize: 64 + - Name: UOut5 + Format: UInt32 + Stride: 16 + ZeroInitSize: 16 + - Name: UExpectedOut1 + Format: UInt32 + Stride: 16 + Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + - Name: UExpectedOut2 + Format: UInt32 + Stride: 16 + Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + - Name: UExpectedOut3 + Format: UInt32 + Stride: 16 + Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + - Name: UExpectedOut4 + Format: UInt32 + Stride: 16 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: UExpectedOut5 + Format: UInt32 + Stride: 16 + Data: [ 1, 2, 3, 4 ] +Results: + - Result: ExpectedOut1 + Rule: BufferExact + Actual: Out1 + Expected: ExpectedOut1 + - Result: ExpectedOut2 + Rule: BufferExact + Actual: Out2 + Expected: ExpectedOut2 + - Result: ExpectedOut3 + Rule: BufferExact + Actual: Out3 + Expected: ExpectedOut3 + - Result: ExpectedOut4 + Rule: BufferExact + Actual: Out4 + Expected: ExpectedOut4 + - Result: ExpectedOut5 + Rule: BufferExact + Actual: Out5 + Expected: ExpectedOut5 + - Result: UExpectedOut1 + Rule: BufferExact + Actual: UOut1 + Expected: UExpectedOut1 + - Result: UExpectedOut2 + Rule: BufferExact + Actual: UOut2 + Expected: UExpectedOut2 + - Result: UExpectedOut3 + Rule: BufferExact + Actual: UOut3 + Expected: UExpectedOut3 + - Result: UExpectedOut4 + Rule: BufferExact + Actual: UOut4 + Expected: UExpectedOut4 + - Result: UExpectedOut5 + Rule: BufferExact + Actual: UOut5 + Expected: UExpectedOut5 +DescriptorSets: + - Resources: + - Name: In + Kind: StructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: Out1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 + - Name: Out2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 2 + Space: 0 + VulkanBinding: + Binding: 2 + - Name: Out3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 3 + Space: 0 + VulkanBinding: + Binding: 3 + - Name: Out4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 4 + Space: 0 + VulkanBinding: + Binding: 4 + - Name: Out5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 5 + Space: 0 + VulkanBinding: + Binding: 5 + - Name: UIn + Kind: StructuredBuffer + DirectXBinding: + Register: 6 + Space: 0 + VulkanBinding: + Binding: 6 + - Name: UOut1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 7 + Space: 0 + VulkanBinding: + Binding: 7 + - Name: UOut2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 8 + Space: 0 + VulkanBinding: + Binding: 8 + - Name: UOut3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 9 + Space: 0 + VulkanBinding: + Binding: 9 + - Name: UOut4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 10 + Space: 0 + VulkanBinding: + Binding: 10 + - Name: UOut5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 11 + Space: 0 + VulkanBinding: + Binding: 11 + +... +#--- end + + +# Tracked by https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal + +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang + +# RUN: split-file %s %t +# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.int64.test b/test/WaveOps/WaveReadLaneFirst.int64.test new file mode 100644 index 000000000..b2a3770b1 --- /dev/null +++ b/test/WaveOps/WaveReadLaneFirst.int64.test @@ -0,0 +1,331 @@ +#--- source.hlsl +StructuredBuffer In : register(t0); +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test int64_t2 +RWStructuredBuffer Out3 : register(u3); // test int64_t3 +RWStructuredBuffer Out4 : register(u4); // test int64_t4 +RWStructuredBuffer Out5 : register(u5); // constant folding + +// uint64_ts +StructuredBuffer UIn : register(t6); +RWStructuredBuffer UOut1 : register(u7); +RWStructuredBuffer UOut2 : register(u8); +RWStructuredBuffer UOut3 : register(u9); +RWStructuredBuffer UOut4 : register(u10); +RWStructuredBuffer UOut5 : register(u11); + +[numthreads(4,1,1)] +void main(uint3 tid : SV_GroupThreadID) +{ + int64_t4 v = In[tid.x]; + + // Mask per "active lane set": only >= N lanes contribute + int64_t s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0; + int64_t s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0; + int64_t s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0; + int64_t s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0; + + int64_t2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : int64_t2(0,0); + int64_t2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : int64_t2(0,0); + int64_t2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : int64_t2(0,0); + int64_t2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : int64_t2(0,0); + + int64_t3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : int64_t3(0,0,0); + int64_t3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : int64_t3(0,0,0); + int64_t3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : int64_t3(0,0,0); + int64_t3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : int64_t3(0,0,0); + + int64_t4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : int64_t4(0,0,0,0); + int64_t4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : int64_t4(0,0,0,0); + int64_t4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : int64_t4(0,0,0,0); + int64_t4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : int64_t4(0,0,0,0); + + int64_t scalars[4] = { s4, s3, s2, s1 }; + int64_t2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; + int64_t3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; + int64_t4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; + + Out1[tid.x].x = scalars[tid.x]; + Out2[tid.x].xy = vec2s[tid.x]; + Out3[tid.x].xyz = vec3s[tid.x]; + Out4[tid.x] = vec4s[tid.x]; + + // constant folding case + Out5[0] = WaveReadLaneFirst(int64_t4(1,2,3,4)); + + // UINT64_t case + + uint64_t4 uv = UIn[tid.x]; + + // Mask per "active lane set": only >= N lanes contribute + uint64_t us1 = tid.x >= 3 ? WaveReadLaneFirst( uv.x ) : 0; + uint64_t us2 = tid.x >= 2 ? WaveReadLaneFirst( uv.x ) : 0; + uint64_t us3 = tid.x >= 1 ? WaveReadLaneFirst( uv.x ) : 0; + uint64_t us4 = tid.x >= 0 ? WaveReadLaneFirst( uv.x ) : 0; + + uint64_t2 uv2_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xy ) : uint64_t2(0,0); + uint64_t2 uv2_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xy ) : uint64_t2(0,0); + uint64_t2 uv2_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xy ) : uint64_t2(0,0); + uint64_t2 uv2_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xy ) : uint64_t2(0,0); + + uint64_t3 uv3_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xyz ) : uint64_t3(0,0,0); + uint64_t3 uv3_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xyz ) : uint64_t3(0,0,0); + uint64_t3 uv3_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xyz ) : uint64_t3(0,0,0); + uint64_t3 uv3_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xyz ) : uint64_t3(0,0,0); + + uint64_t4 uv4_1 = tid.x >= 3 ? WaveReadLaneFirst( uv ) : uint64_t4(0,0,0,0); + uint64_t4 uv4_2 = tid.x >= 2 ? WaveReadLaneFirst( uv ) : uint64_t4(0,0,0,0); + uint64_t4 uv4_3 = tid.x >= 1 ? WaveReadLaneFirst( uv ) : uint64_t4(0,0,0,0); + uint64_t4 uv4_4 = tid.x >= 0 ? WaveReadLaneFirst( uv ) : uint64_t4(0,0,0,0); + + uint64_t uscalars[4] = { us4, us3, us2, us1 }; + uint64_t2 uvec2s [4] = { uv2_4, uv2_3, uv2_2, uv2_1 }; + uint64_t3 uvec3s [4] = { uv3_4, uv3_3, uv3_2, uv3_1 }; + uint64_t4 uvec4s [4] = { uv4_4, uv4_3, uv4_2, uv4_1 }; + + UOut1[tid.x].x = uscalars[tid.x]; + UOut2[tid.x].xy = uvec2s[tid.x]; + UOut3[tid.x].xyz = uvec3s[tid.x]; + UOut4[tid.x] = uvec4s[tid.x]; + + // constant folding case + UOut5[0] = WaveReadLaneFirst(uint64_t4(1,2,3,4)); +} + +//--- pipeline.yaml + +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [1, 1, 1] +Buffers: + - Name: In + Format: Int64 + Stride: 32 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: Out1 + Format: Int64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out2 + Format: Int64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out3 + Format: Int64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out4 + Format: Int64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out5 + Format: Int64 + Stride: 32 + ZeroInitSize: 32 + - Name: ExpectedOut1 + Format: Int64 + Stride: 32 + Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + - Name: ExpectedOut2 + Format: Int64 + Stride: 32 + Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + - Name: ExpectedOut3 + Format: Int64 + Stride: 32 + Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + - Name: ExpectedOut4 + Format: Int64 + Stride: 32 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: ExpectedOut5 + Format: Int64 + Stride: 32 + Data: [ 1, 2, 3, 4 ] + - Name: UIn + Format: UInt64 + Stride: 32 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: UOut1 + Format: UInt64 + Stride: 32 + ZeroInitSize: 128 + - Name: UOut2 + Format: UInt64 + Stride: 32 + ZeroInitSize: 128 + - Name: UOut3 + Format: UInt64 + Stride: 32 + ZeroInitSize: 128 + - Name: UOut4 + Format: UInt64 + Stride: 32 + ZeroInitSize: 128 + - Name: UOut5 + Format: UInt64 + Stride: 32 + ZeroInitSize: 32 + - Name: UExpectedOut1 + Format: UInt64 + Stride: 32 + Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + - Name: UExpectedOut2 + Format: UInt64 + Stride: 32 + Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + - Name: UExpectedOut3 + Format: UInt64 + Stride: 32 + Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + - Name: UExpectedOut4 + Format: UInt64 + Stride: 32 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: UExpectedOut5 + Format: UInt64 + Stride: 32 + Data: [ 1, 2, 3, 4 ] +Results: + - Result: ExpectedOut1 + Rule: BufferExact + Actual: Out1 + Expected: ExpectedOut1 + - Result: ExpectedOut2 + Rule: BufferExact + Actual: Out2 + Expected: ExpectedOut2 + - Result: ExpectedOut3 + Rule: BufferExact + Actual: Out3 + Expected: ExpectedOut3 + - Result: ExpectedOut4 + Rule: BufferExact + Actual: Out4 + Expected: ExpectedOut4 + - Result: ExpectedOut5 + Rule: BufferExact + Actual: Out5 + Expected: ExpectedOut5 + - Result: UExpectedOut1 + Rule: BufferExact + Actual: UOut1 + Expected: UExpectedOut1 + - Result: UExpectedOut2 + Rule: BufferExact + Actual: UOut2 + Expected: UExpectedOut2 + - Result: UExpectedOut3 + Rule: BufferExact + Actual: UOut3 + Expected: UExpectedOut3 + - Result: UExpectedOut4 + Rule: BufferExact + Actual: UOut4 + Expected: UExpectedOut4 + - Result: UExpectedOut5 + Rule: BufferExact + Actual: UOut5 + Expected: UExpectedOut5 +DescriptorSets: + - Resources: + - Name: In + Kind: StructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: Out1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 + - Name: Out2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 2 + Space: 0 + VulkanBinding: + Binding: 2 + - Name: Out3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 3 + Space: 0 + VulkanBinding: + Binding: 3 + - Name: Out4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 4 + Space: 0 + VulkanBinding: + Binding: 4 + - Name: Out5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 5 + Space: 0 + VulkanBinding: + Binding: 5 + - Name: UIn + Kind: StructuredBuffer + DirectXBinding: + Register: 6 + Space: 0 + VulkanBinding: + Binding: 6 + - Name: UOut1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 7 + Space: 0 + VulkanBinding: + Binding: 7 + - Name: UOut2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 8 + Space: 0 + VulkanBinding: + Binding: 8 + - Name: UOut3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 9 + Space: 0 + VulkanBinding: + Binding: 9 + - Name: UOut4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 10 + Space: 0 + VulkanBinding: + Binding: 10 + - Name: UOut5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 11 + Space: 0 + VulkanBinding: + Binding: 11 + +... +#--- end + + +# Tracked by https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal + +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang + +# RUN: split-file %s %t +# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o From bc0f73d53ff59e1649b4fadc3b73f8c83ad9388c Mon Sep 17 00:00:00 2001 From: Joshua Batista Date: Mon, 8 Sep 2025 16:48:00 -0700 Subject: [PATCH 02/10] add warp bug to fp16/64, and int64. Use bug verbage --- test/WaveOps/WaveReadLaneFirst.fp16.test | 5 ++++- test/WaveOps/WaveReadLaneFirst.fp32.test | 2 +- test/WaveOps/WaveReadLaneFirst.fp64.test | 5 ++++- test/WaveOps/WaveReadLaneFirst.int16.test | 2 +- test/WaveOps/WaveReadLaneFirst.int32.test | 2 +- test/WaveOps/WaveReadLaneFirst.int64.test | 6 +++++- 6 files changed, 16 insertions(+), 6 deletions(-) diff --git a/test/WaveOps/WaveReadLaneFirst.fp16.test b/test/WaveOps/WaveReadLaneFirst.fp16.test index be4148ab1..2492b5efc 100644 --- a/test/WaveOps/WaveReadLaneFirst.fp16.test +++ b/test/WaveOps/WaveReadLaneFirst.fp16.test @@ -174,12 +174,15 @@ DescriptorSets: #--- end -# Tracked by https://github.com/llvm/offload-test-suite/issues/393 +# Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal # Bug https://github.com/llvm/llvm-project/issues/156775 # XFAIL: Clang +# Bug https://github.com/llvm/offload-test-suite/issues/433 +# XFAIL: DirectX-WARP + # RUN: split-file %s %t # RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.fp32.test b/test/WaveOps/WaveReadLaneFirst.fp32.test index 304802a50..8d2c774a7 100644 --- a/test/WaveOps/WaveReadLaneFirst.fp32.test +++ b/test/WaveOps/WaveReadLaneFirst.fp32.test @@ -168,7 +168,7 @@ DescriptorSets: #--- end -# Tracked by https://github.com/llvm/offload-test-suite/issues/393 +# Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal # Bug https://github.com/llvm/llvm-project/issues/156775 diff --git a/test/WaveOps/WaveReadLaneFirst.fp64.test b/test/WaveOps/WaveReadLaneFirst.fp64.test index 6d33f9316..786efaf76 100644 --- a/test/WaveOps/WaveReadLaneFirst.fp64.test +++ b/test/WaveOps/WaveReadLaneFirst.fp64.test @@ -168,12 +168,15 @@ DescriptorSets: #--- end -# Tracked by https://github.com/llvm/offload-test-suite/issues/393 +# Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal # Bug https://github.com/llvm/llvm-project/issues/156775 # XFAIL: Clang +# Bug https://github.com/llvm/offload-test-suite/issues/433 +# XFAIL: DirectX-WARP + # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.int16.test b/test/WaveOps/WaveReadLaneFirst.int16.test index ccf57ed11..e6f4725bb 100644 --- a/test/WaveOps/WaveReadLaneFirst.int16.test +++ b/test/WaveOps/WaveReadLaneFirst.int16.test @@ -320,7 +320,7 @@ DescriptorSets: #--- end -# Tracked by https://github.com/llvm/offload-test-suite/issues/393 +# Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal # Bug https://github.com/llvm/llvm-project/issues/156775 diff --git a/test/WaveOps/WaveReadLaneFirst.int32.test b/test/WaveOps/WaveReadLaneFirst.int32.test index ba5876689..284ff82c3 100644 --- a/test/WaveOps/WaveReadLaneFirst.int32.test +++ b/test/WaveOps/WaveReadLaneFirst.int32.test @@ -320,7 +320,7 @@ DescriptorSets: #--- end -# Tracked by https://github.com/llvm/offload-test-suite/issues/393 +# Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal # Bug https://github.com/llvm/llvm-project/issues/156775 diff --git a/test/WaveOps/WaveReadLaneFirst.int64.test b/test/WaveOps/WaveReadLaneFirst.int64.test index b2a3770b1..b9e101abb 100644 --- a/test/WaveOps/WaveReadLaneFirst.int64.test +++ b/test/WaveOps/WaveReadLaneFirst.int64.test @@ -320,12 +320,16 @@ DescriptorSets: #--- end -# Tracked by https://github.com/llvm/offload-test-suite/issues/393 +# Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal # Bug https://github.com/llvm/llvm-project/issues/156775 # XFAIL: Clang +# Bug https://github.com/llvm/offload-test-suite/issues/433 +# XFAIL: DirectX-WARP + + # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o From e962c17e61060fbc1dfaa7a844368ba740e2662b Mon Sep 17 00:00:00 2001 From: Joshua Batista Date: Mon, 8 Sep 2025 16:51:20 -0700 Subject: [PATCH 03/10] remove warp bug, add requires statements --- test/WaveOps/WaveReadLaneFirst.fp16.test | 4 +--- test/WaveOps/WaveReadLaneFirst.fp64.test | 4 +--- test/WaveOps/WaveReadLaneFirst.int64.test | 4 +--- 3 files changed, 3 insertions(+), 9 deletions(-) diff --git a/test/WaveOps/WaveReadLaneFirst.fp16.test b/test/WaveOps/WaveReadLaneFirst.fp16.test index 2492b5efc..e56fc723c 100644 --- a/test/WaveOps/WaveReadLaneFirst.fp16.test +++ b/test/WaveOps/WaveReadLaneFirst.fp16.test @@ -173,6 +173,7 @@ DescriptorSets: ... #--- end +# REQUIRES: Half # Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal @@ -180,9 +181,6 @@ DescriptorSets: # Bug https://github.com/llvm/llvm-project/issues/156775 # XFAIL: Clang -# Bug https://github.com/llvm/offload-test-suite/issues/433 -# XFAIL: DirectX-WARP - # RUN: split-file %s %t # RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.fp64.test b/test/WaveOps/WaveReadLaneFirst.fp64.test index 786efaf76..d7e8a1dc4 100644 --- a/test/WaveOps/WaveReadLaneFirst.fp64.test +++ b/test/WaveOps/WaveReadLaneFirst.fp64.test @@ -167,6 +167,7 @@ DescriptorSets: ... #--- end +# REQUIRES: Double # Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal @@ -174,9 +175,6 @@ DescriptorSets: # Bug https://github.com/llvm/llvm-project/issues/156775 # XFAIL: Clang -# Bug https://github.com/llvm/offload-test-suite/issues/433 -# XFAIL: DirectX-WARP - # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.int64.test b/test/WaveOps/WaveReadLaneFirst.int64.test index b9e101abb..dca5271f5 100644 --- a/test/WaveOps/WaveReadLaneFirst.int64.test +++ b/test/WaveOps/WaveReadLaneFirst.int64.test @@ -319,6 +319,7 @@ DescriptorSets: ... #--- end +# REQUIRES: Int64 # Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal @@ -326,9 +327,6 @@ DescriptorSets: # Bug https://github.com/llvm/llvm-project/issues/156775 # XFAIL: Clang -# Bug https://github.com/llvm/offload-test-suite/issues/433 -# XFAIL: DirectX-WARP - # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl From 4e923d9c56b955aa1b6c923ca149c48bfa0b33cc Mon Sep 17 00:00:00 2001 From: Joshua Batista Date: Mon, 8 Sep 2025 20:12:51 -0700 Subject: [PATCH 04/10] add back the xfail for warp --- test/WaveOps/WaveReadLaneFirst.fp16.test | 3 +++ test/WaveOps/WaveReadLaneFirst.fp64.test | 3 +++ test/WaveOps/WaveReadLaneFirst.int64.test | 3 +++ 3 files changed, 9 insertions(+) diff --git a/test/WaveOps/WaveReadLaneFirst.fp16.test b/test/WaveOps/WaveReadLaneFirst.fp16.test index e56fc723c..985599689 100644 --- a/test/WaveOps/WaveReadLaneFirst.fp16.test +++ b/test/WaveOps/WaveReadLaneFirst.fp16.test @@ -181,6 +181,9 @@ DescriptorSets: # Bug https://github.com/llvm/llvm-project/issues/156775 # XFAIL: Clang +# Bug https://github.com/llvm/offload-test-suite/issues/433 +# XFAIL: DirectX-WARP + # RUN: split-file %s %t # RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.fp64.test b/test/WaveOps/WaveReadLaneFirst.fp64.test index d7e8a1dc4..1129646db 100644 --- a/test/WaveOps/WaveReadLaneFirst.fp64.test +++ b/test/WaveOps/WaveReadLaneFirst.fp64.test @@ -175,6 +175,9 @@ DescriptorSets: # Bug https://github.com/llvm/llvm-project/issues/156775 # XFAIL: Clang +# Bug https://github.com/llvm/offload-test-suite/issues/433 +# XFAIL: DirectX-WARP + # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.int64.test b/test/WaveOps/WaveReadLaneFirst.int64.test index dca5271f5..09c8bce57 100644 --- a/test/WaveOps/WaveReadLaneFirst.int64.test +++ b/test/WaveOps/WaveReadLaneFirst.int64.test @@ -327,6 +327,9 @@ DescriptorSets: # Bug https://github.com/llvm/llvm-project/issues/156775 # XFAIL: Clang +# Bug https://github.com/llvm/offload-test-suite/issues/433 +# XFAIL: DirectX-WARP + # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl From f5fd22cc1fa71f8f96d7ec132ebf4c47f5435f89 Mon Sep 17 00:00:00 2001 From: Joshua Batista Date: Mon, 27 Oct 2025 15:42:19 -0700 Subject: [PATCH 05/10] update wavereadlanefirst tests according to waveactivemaax format --- test/WaveOps/WaveReadLaneFirst.fp16.test | 250 ++++++++++---- test/WaveOps/WaveReadLaneFirst.fp32.test | 246 ++++++++++---- test/WaveOps/WaveReadLaneFirst.fp64.test | 262 +++++++++++---- test/WaveOps/WaveReadLaneFirst.int16.test | 378 ++++++++++----------- test/WaveOps/WaveReadLaneFirst.int32.test | 380 ++++++++++----------- test/WaveOps/WaveReadLaneFirst.int64.test | 383 ++++++++++------------ 6 files changed, 1121 insertions(+), 778 deletions(-) diff --git a/test/WaveOps/WaveReadLaneFirst.fp16.test b/test/WaveOps/WaveReadLaneFirst.fp16.test index 985599689..95f88382a 100644 --- a/test/WaveOps/WaveReadLaneFirst.fp16.test +++ b/test/WaveOps/WaveReadLaneFirst.fp16.test @@ -1,51 +1,43 @@ #--- source.hlsl +#define VALUE_SETS 2 +#define NUM_MASKS 4 +#define NUM_THREADS 4 + +struct MaskStruct { + int mask[NUM_THREADS]; +}; + StructuredBuffer In : register(t0); -RWStructuredBuffer Out1 : register(u1); // test scalar -RWStructuredBuffer Out2 : register(u2); // test half2 +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test half2 RWStructuredBuffer Out3 : register(u3); // test half3 RWStructuredBuffer Out4 : register(u4); // test half4 RWStructuredBuffer Out5 : register(u5); // constant folding +StructuredBuffer Masks : register(t6); + -[numthreads(4,1,1)] +[numthreads(NUM_THREADS,1,1)] void main(uint3 tid : SV_GroupThreadID) { - half4 v = In[tid.x]; - - // Mask per "active lane set": only >= N lanes contribute - half s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0; - half s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0; - half s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0; - half s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0; - - half2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : half2(0,0); - half2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : half2(0,0); - half2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : half2(0,0); - half2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : half2(0,0); - - half3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : half3(0,0,0); - half3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : half3(0,0,0); - half3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : half3(0,0,0); - half3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : half3(0,0,0); - - half4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : half4(0,0,0,0); - half4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : half4(0,0,0,0); - half4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : half4(0,0,0,0); - half4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : half4(0,0,0,0); - - half scalars[4] = { s4, s3, s2, s1 }; - half2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; - half3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; - half4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; - - Out1[tid.x].x = scalars[tid.x]; - Out2[tid.x].xy = vec2s[tid.x]; - Out3[tid.x].xyz = vec3s[tid.x]; - Out4[tid.x] = vec4s[tid.x]; + for (uint ValueSet = 0; ValueSet < VALUE_SETS; ValueSet++) { + const uint ValueSetOffset = ValueSet * NUM_MASKS * NUM_THREADS; + for (uint MaskIdx = 0; MaskIdx < NUM_MASKS; MaskIdx++) { + half4 v = In[ValueSet * ValueSetOffset + MaskIdx * NUM_THREADS + tid.x]; + const uint OutIdx = ValueSetOffset + MaskIdx * NUM_THREADS + tid.x; + if (Masks[MaskIdx].mask[tid.x]) { + Out1[OutIdx] = WaveReadLaneFirst( v.x ); + Out2[OutIdx].xy = WaveReadLaneFirst( v.xy ); + Out3[OutIdx].xyz = WaveReadLaneFirst( v.xyz ); + Out4[OutIdx] = WaveReadLaneFirst( v ); + } + } + } // constant folding case - Out5[0] = WaveReadLaneFirst(half4(1,2,3,4)); + Out5[0] = WaveReadLaneFirst(half4(1,2,3,4)); } + //--- pipeline.yaml --- @@ -57,52 +49,184 @@ Buffers: - Name: In Format: Float16 Stride: 8 - # 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 - Data: [ 0x3c00, 0x4900, 0x5640, 0x63d0, 0x4000, 0x4d00, 0x5a40, 0x67d0, 0x4200, 0x4f80, 0x5cb0, 0x69dc, 0x4400, 0x5100, 0x5e40, 0x6bd0 ] + # 2 value sets + # For each value set, + # and for each specific one of the 4 thread masks in that value set, + # and for each of the 4 threads in that thread mask, + # there will be a unique set of 4 values, such that + # none of the other threads in that thread mask share any values + Data: [ + 0x2000, 0x2200, 0x2400, 0x2800, # <-- Value set 0, thread mask 0, thread id 0 will read these In values + 0x2A00, 0x2C00, 0x2E00, 0x3000, # <-- Value set 0, thread mask 0, thread id 1 will read these In values + 0x3200, 0x3400, 0x3600, 0x3800, + 0x3900, 0x3A00, 0x3B00, 0x3BC0, + 0x2200, 0x2400, 0x2800, 0x2A00, # <-- Value set 0, thread mask 1, thread id 0 will read these In values + 0x2C00, 0x2E00, 0x3000, 0x3200, + 0x3400, 0x3600, 0x3800, 0x3900, + 0x3A00, 0x3B00, 0x3BC0, 0x2000, + 0x2400, 0x2800, 0x2A00, 0x2C00, + 0x2E00, 0x3000, 0x3200, 0x3400, + 0x3600, 0x3800, 0x3900, 0x3A00, + 0x3B00, 0x3BC0, 0x2000, 0x2200, + 0x2800, 0x2A00, 0x2C00, 0x2E00, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x3800, 0x3900, 0x3A00, 0x3B00, + 0x3BC0, 0x2000, 0x2200, 0x2400, + 0x2800, 0x2400, 0x2200, 0x2000, # <-- Value set 1, thread mask 0, thread id 0 will read these In values + 0x3000, 0x2E00, 0x2C00, 0x2A00, + 0x3800, 0x3600, 0x3400, 0x3200, + 0x3BC0, 0x3B00, 0x3A00, 0x3900, + 0x2A00, 0x2800, 0x2400, 0x2200, + 0x3200, 0x3000, 0x2E00, 0x2C00, + 0x3900, 0x3800, 0x3600, 0x3400, + 0x2000, 0x3BC0, 0x3B00, 0x3A00, + 0x2C00, 0x2A00, 0x2800, 0x2400, + 0x3400, 0x3200, 0x3000, 0x2E00, + 0x3A00, 0x3900, 0x3800, 0x3600, + 0x2200, 0x2000, 0x3BC0, 0x3B00, + 0x2E00, 0x2C00, 0x2A00, 0x2800, + 0x3600, 0x3400, 0x3200, 0x3000, + 0x3B00, 0x3A00, 0x3900, 0x3800, + 0x2400, 0x2200, 0x2000, 0x3BC0 ] + - Name: Out1 Format: Float16 - Stride: 8 - ZeroInitSize: 32 + Stride: 2 + # 1 half is 2 bytes, * 4 halves for 4 threads, * 4 thread masks, * 2 value sets + FillSize: 64 - Name: Out2 Format: Float16 - Stride: 8 - ZeroInitSize: 32 + Stride: 4 + FillSize: 128 - Name: Out3 Format: Float16 Stride: 8 - ZeroInitSize: 32 + FillSize: 256 - Name: Out4 Format: Float16 Stride: 8 - ZeroInitSize: 32 + FillSize: 256 - Name: Out5 Format: Float16 Stride: 8 - ZeroInitSize: 8 + FillSize: 8 + - Name: Masks + Format: Int32 + Stride: 16 + # 4 active mask sets for threads 0, 1, 2, 3: + # 0 0 0 0 + # 1 1 1 1 + # 1 0 0 0 + # 0 1 1 0 + Data: [ + 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0] - Name: ExpectedOut1 Format: Float16 Stride: 8 - # 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 - Data: [ 0x3c00, 0x0, 0x0, 0x0, 0x4000, 0x0, 0x0, 0x0, 0x4200, 0x0, 0x0, 0x0, 0x4400, 0x0, 0x0, 0x0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0x0, 0x0, 0x0, 0x0, + 0x2200, 0x2200, 0x2200, 0x2200, + 0x2400, 0x0, 0x0, 0x0, + 0x0, 0x3000, 0x3000, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x2A00, 0x2A00, 0x2A00, 0x2A00, + 0x2C00, 0x0, 0x0, 0x0, + 0x0, 0x3600, 0x3600, 0x0] - Name: ExpectedOut2 Format: Float16 Stride: 8 - # 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 - Data: [ 0x3c00, 0x4900, 0x0, 0x0, 0x4000, 0x4d00, 0x0, 0x0, 0x4200, 0x4f80, 0x0, 0x0, 0x4400, 0x5100, 0x0, 0x0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x2200, 0x2400, 0x2200, 0x2400, + 0x2200, 0x2400, 0x2200, 0x2400, + 0x2400, 0x2800, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3000, 0x3200, + 0x3000, 0x3200, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x2A00, 0x2800, 0x2A00, 0x2800, + 0x2A00, 0x2800, 0x2A00, 0x2800, + 0x2C00, 0x2A00, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3600, 0x3400, + 0x3600, 0x3400, 0x0, 0x0 ] - Name: ExpectedOut3 Format: Float16 Stride: 8 - # 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 - Data: [ 0x3c00, 0x4900, 0x5640, 0x0, 0x4000, 0x4d00, 0x5a40, 0x0, 0x4200, 0x4f80, 0x5cb0, 0x0, 0x4400, 0x5100, 0x5e40, 0x0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 4 result values per thread + # Note, vecs of 3 must be aligned, so the 3 result values are placed into a 4 element vec + Data: [ 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x2200, 0x2400, 0x2800, 0x0, + 0x2200, 0x2400, 0x2800, 0x0, + 0x2200, 0x2400, 0x2800, 0x0, + 0x2200, 0x2400, 0x2800, 0x0, + 0x2400, 0x2800, 0x2A00, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3000, 0x3200, 0x3400, 0x0, + 0x3000, 0x3200, 0x3400, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x2A00, 0x2800, 0x2400, 0x0, + 0x2A00, 0x2800, 0x2400, 0x0, + 0x2A00, 0x2800, 0x2400, 0x0, + 0x2A00, 0x2800, 0x2400, 0x0, + 0x2C00, 0x2A00, 0x2800, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3600, 0x3400, 0x3200, 0x0, + 0x3600, 0x3400, 0x3200, 0x0, + 0x0, 0x0, 0x0, 0x0 ] - Name: ExpectedOut4 Format: Float16 Stride: 8 - # 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 - Data: [ 0x3c00, 0x4900, 0x5640, 0x63d0, 0x4000, 0x4d00, 0x5a40, 0x67d0, 0x4200, 0x4f80, 0x5cb0, 0x69dc, 0x4400, 0x5100, 0x5e40, 0x6bd0 ] + Data: [ 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x2200, 0x2400, 0x2800, 0x2A00, + 0x2200, 0x2400, 0x2800, 0x2A00, + 0x2200, 0x2400, 0x2800, 0x2A00, + 0x2200, 0x2400, 0x2800, 0x2A00, + 0x2400, 0x2800, 0x2A00, 0x2C00, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x2A00, 0x2800, 0x2400, 0x2200, + 0x2A00, 0x2800, 0x2400, 0x2200, + 0x2A00, 0x2800, 0x2400, 0x2200, + 0x2A00, 0x2800, 0x2400, 0x2200, + 0x2C00, 0x2A00, 0x2800, 0x2400, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3600, 0x3400, 0x3200, 0x3000, + 0x3600, 0x3400, 0x3200, 0x3000, + 0x0, 0x0, 0x0, 0x0 ] - Name: ExpectedOut5 Format: Float16 Stride: 8 - # 1, 2, 3, 4 Data: [ 0x3C00, 0x4000, 0x4200, 0x4400 ] Results: - Result: ExpectedOut1 @@ -125,7 +249,6 @@ Results: Rule: BufferExact Actual: Out5 Expected: ExpectedOut5 - DescriptorSets: - Resources: - Name: In @@ -170,19 +293,22 @@ DescriptorSets: Space: 0 VulkanBinding: Binding: 5 + - Name: Masks + Kind: StructuredBuffer + DirectXBinding: + Register: 6 + Space: 0 + VulkanBinding: + Binding: 6 + ... #--- end -# REQUIRES: Half - -# Bug https://github.com/llvm/offload-test-suite/issues/393 -# XFAIL: Metal - # Bug https://github.com/llvm/llvm-project/issues/156775 # XFAIL: Clang -# Bug https://github.com/llvm/offload-test-suite/issues/433 -# XFAIL: DirectX-WARP +# Bug https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal # RUN: split-file %s %t # RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl diff --git a/test/WaveOps/WaveReadLaneFirst.fp32.test b/test/WaveOps/WaveReadLaneFirst.fp32.test index 8d2c774a7..7e417a2de 100644 --- a/test/WaveOps/WaveReadLaneFirst.fp32.test +++ b/test/WaveOps/WaveReadLaneFirst.fp32.test @@ -1,51 +1,43 @@ #--- source.hlsl +#define VALUE_SETS 2 +#define NUM_MASKS 4 +#define NUM_THREADS 4 + +struct MaskStruct { + int mask[NUM_THREADS]; +}; + StructuredBuffer In : register(t0); -RWStructuredBuffer Out1 : register(u1); // test scalar -RWStructuredBuffer Out2 : register(u2); // test float2 +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test float2 RWStructuredBuffer Out3 : register(u3); // test float3 RWStructuredBuffer Out4 : register(u4); // test float4 RWStructuredBuffer Out5 : register(u5); // constant folding +StructuredBuffer Masks : register(t6); -[numthreads(4,1,1)] + +[numthreads(NUM_THREADS,1,1)] void main(uint3 tid : SV_GroupThreadID) { - float4 v = In[tid.x]; - - // Mask per "active lane set": only >= N lanes contribute - float s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0; - float s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0; - float s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0; - float s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0; - - float2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : float2(0,0); - float2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : float2(0,0); - float2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : float2(0,0); - float2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : float2(0,0); - - float3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : float3(0,0,0); - float3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : float3(0,0,0); - float3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : float3(0,0,0); - float3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : float3(0,0,0); - - float4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : float4(0,0,0,0); - float4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : float4(0,0,0,0); - float4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : float4(0,0,0,0); - float4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : float4(0,0,0,0); - - float scalars[4] = { s4, s3, s2, s1 }; - float2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; - float3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; - float4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; - - Out1[tid.x].x = scalars[tid.x]; - Out2[tid.x].xy = vec2s[tid.x]; - Out3[tid.x].xyz = vec3s[tid.x]; - Out4[tid.x] = vec4s[tid.x]; + for (uint ValueSet = 0; ValueSet < VALUE_SETS; ValueSet++) { + const uint ValueSetOffset = ValueSet * NUM_MASKS * NUM_THREADS; + for (uint MaskIdx = 0; MaskIdx < NUM_MASKS; MaskIdx++) { + float4 v = In[ValueSet * ValueSetOffset + MaskIdx * NUM_THREADS + tid.x]; + const uint OutIdx = ValueSetOffset + MaskIdx * NUM_THREADS + tid.x; + if (Masks[MaskIdx].mask[tid.x]) { + Out1[OutIdx] = WaveReadLaneFirst( v.x ); + Out2[OutIdx].xy = WaveReadLaneFirst( v.xy ); + Out3[OutIdx].xyz = WaveReadLaneFirst( v.xyz ); + Out4[OutIdx] = WaveReadLaneFirst( v ); + } + } + } // constant folding case - Out5[0] = WaveReadLaneFirst(float4(1,2,3,4)); + Out5[0] = WaveReadLaneFirst(float4(1.5,2.5,3.5,4.5)); } + //--- pipeline.yaml --- @@ -56,48 +48,186 @@ Shaders: Buffers: - Name: In Format: Float32 - Stride: 16 - Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ] + Stride: 16 + # 2 value sets + # For each value set, + # and for each specific one of the 4 thread masks in that value set, + # and for each of the 4 threads in that thread mask, + # there will be a unique set of 4 values, such that + # none of the other threads in that thread mask share any values + Data: [ + 1.5, 2.5, 3.5, 4.5, # <-- Value set 0, thread mask 0, thread id 0 will read these In values + 5.5, 6.5, 7.5, 8.5, # <-- Value set 0, thread mask 0, thread id 1 will read these In values + 9.5, 10.5, 11.5, 12.5, + 13.5, 14.5, 15.5, 16.5, + 2.5, 3.5, 4.5, 5.5, # <-- Value set 0, thread mask 1, thread id 0 will read these In values + 6.5, 7.5, 8.5, 9.5, + 10.5, 11.5, 12.5, 13.5, + 14.5, 15.5, 16.5, 1.5, + 3.5, 4.5, 5.5, 6.5, + 7.5, 8.5, 9.5, 10.5, + 11.5, 12.5, 13.5, 14.5, + 15.5, 16.5, 1.5, 2.5, + 4.5, 5.5, 6.5, 7.5, + 8.5, 9.5, 10.5, 11.5, + 12.5, 13.5, 14.5, 15.5, + 16.5, 1.5, 2.5, 3.5, + 4.5, 3.5, 2.5, 1.5, # <-- Value set 1, thread mask 0, thread id 0 will read these In values + 8.5, 7.5, 6.5, 5.5, + 12.5, 11.5, 10.5, 9.5, + 16.5, 15.5, 14.5, 13.5, + 5.5, 4.5, 3.5, 2.5, + 9.5, 8.5, 7.5, 6.5, + 13.5, 12.5, 11.5, 10.5, + 1.5, 16.5, 15.5, 14.5, + 6.5, 5.5, 4.5, 3.5, + 10.5, 9.5, 8.5, 7.5, + 14.5, 13.5, 12.5, 11.5, + 2.5, 1.5, 16.5, 15.5, + 7.5, 6.5, 5.5, 4.5, + 11.5, 10.5, 9.5, 8.5, + 15.5, 14.5, 13.5, 12.5, + 3.5, 2.5, 1.5, 16 ] + - Name: Out1 Format: Float32 - Stride: 16 - ZeroInitSize: 64 + Stride: 4 + # 1 float is 4 bytes, * 4 halves for 4 threads, * 4 thread masks, * 2 value sets + FillSize: 128 - Name: Out2 Format: Float32 - Stride: 16 - ZeroInitSize: 64 + Stride: 8 + FillSize: 256 - Name: Out3 Format: Float32 Stride: 16 - ZeroInitSize: 64 + FillSize: 512 - Name: Out4 Format: Float32 Stride: 16 - ZeroInitSize: 64 + FillSize: 512 - Name: Out5 Format: Float32 Stride: 16 - ZeroInitSize: 16 + FillSize: 16 + - Name: Masks + Format: Int32 + Stride: 16 + # 4 active mask sets for threads 0, 1, 2, 3: + # 0 0 0 0 + # 1 1 1 1 + # 1 0 0 0 + # 0 1 1 0 + Data: [ + 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0] - Name: ExpectedOut1 Format: Float32 Stride: 16 - Data: [ 1.0, 0.0, 0.0, 0.0, 2.0, 0.0, 0.0, 0.0, 3.0, 0.0, 0.0, 0.0, 4.0, 0.0, 0.0, 0.0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0, 0, 0, 0, + 2.5, 2.5, 2.5, 2.5, + 3.5, 0, 0, 0, + 0, 8.5, 8.5, 0, + 0, 0, 0, 0, + 5.5, 5.5, 5.5, 5.5, + 6.5, 0, 0, 0, + 0, 11.5, 11.5, 0 ] - Name: ExpectedOut2 Format: Float32 Stride: 16 - Data: [ 1.0, 10.0, 0.0, 0.0, 2.0, 20.0, 0.0, 0.0, 3.0, 30.0, 0.0, 0.0, 4.0, 40.0, 0.0, 0.0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 2.5, 3.5, 2.5, 3.5, + 2.5, 3.5, 2.5, 3.5, + 3.5, 4.5, 0, 0, + 0, 0, 0, 0, + 0, 0, 8.5, 9.5, + 8.5, 9.5, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5.5, 4.5, 5.5, 4.5, + 5.5, 4.5, 5.5, 4.5, + 6.5, 5.5, 0, 0, + 0, 0, 0, 0, + 0, 0, 11.5, 10.5, + 11.5, 10.5, 0, 0 ] - Name: ExpectedOut3 Format: Float32 Stride: 16 - Data: [ 1.0, 10.0, 100.0, 0.0, 2.0, 20.0, 200.0, 0.0, 3.0, 30.0, 300.0, 0.0, 4.0, 40.0, 400.0, 0.0 ] + # 2 value sets.5, 4 masks per value set, 4 threads per mask, 4 result values per thread + # Note, vecs of 3 must be aligned, so the 3 result values are placed into a 4 element vec + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2.5, 3.5, 4.5, 0, + 2.5, 3.5, 4.5, 0, + 2.5, 3.5, 4.5, 0, + 2.5, 3.5, 4.5, 0, + 3.5, 4.5, 5.5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 8.5, 9.5, 10.5, 0, + 8.5, 9.5, 10.5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5.5, 4.5, 3.5, 0, + 5.5, 4.5, 3.5, 0, + 5.5, 4.5, 3.5, 0, + 5.5, 4.5, 3.5, 0, + 6.5, 5.5, 4.5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 11.5, 10.5, 9.5, 0, + 11.5, 10.5, 9.5, 0, + 0, 0, 0, 0] - Name: ExpectedOut4 Format: Float32 Stride: 16 - Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ] + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2.5, 3.5, 4.5, 5.5, + 2.5, 3.5, 4.5, 5.5, + 2.5, 3.5, 4.5, 5.5, + 2.5, 3.5, 4.5, 5.5, + 3.5, 4.5, 5.5, 6.5, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 8.5, 9.5, 10.5, 11.5, + 8.5, 9.5, 10.5, 11.5, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5.5, 4.5, 3.5, 2.5, + 5.5, 4.5, 3.5, 2.5, + 5.5, 4.5, 3.5, 2.5, + 5.5, 4.5, 3.5, 2.5, + 6.5, 5.5, 4.5, 3.5, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 11.5, 10.5, 9.5, 8.5, + 11.5, 10.5, 9.5, 8.5, + 0, 0, 0, 0] - Name: ExpectedOut5 Format: Float32 - Stride: 16 - Data: [ 1, 2, 3, 4 ] + Stride: 8 + Data: [ 1.5, 2.5, 3.5, 4.5 ] Results: - Result: ExpectedOut1 Rule: BufferExact @@ -119,7 +249,6 @@ Results: Rule: BufferExact Actual: Out5 Expected: ExpectedOut5 - DescriptorSets: - Resources: - Name: In @@ -164,16 +293,23 @@ DescriptorSets: Space: 0 VulkanBinding: Binding: 5 + - Name: Masks + Kind: StructuredBuffer + DirectXBinding: + Register: 6 + Space: 0 + VulkanBinding: + Binding: 6 + ... #--- end +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang # Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal -# Bug https://github.com/llvm/llvm-project/issues/156775 -# XFAIL: Clang - # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.fp64.test b/test/WaveOps/WaveReadLaneFirst.fp64.test index 1129646db..f2053fb0d 100644 --- a/test/WaveOps/WaveReadLaneFirst.fp64.test +++ b/test/WaveOps/WaveReadLaneFirst.fp64.test @@ -1,51 +1,43 @@ #--- source.hlsl +#define VALUE_SETS 2 +#define NUM_MASKS 4 +#define NUM_THREADS 4 + +struct MaskStruct { + int mask[NUM_THREADS]; +}; + StructuredBuffer In : register(t0); -RWStructuredBuffer Out1 : register(u1); // test scalar -RWStructuredBuffer Out2 : register(u2); // test double2 +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test double2 RWStructuredBuffer Out3 : register(u3); // test double3 RWStructuredBuffer Out4 : register(u4); // test double4 RWStructuredBuffer Out5 : register(u5); // constant folding +StructuredBuffer Masks : register(t6); -[numthreads(4,1,1)] + +[numthreads(NUM_THREADS,1,1)] void main(uint3 tid : SV_GroupThreadID) { - double4 v = In[tid.x]; - - // Mask per "active lane set": only >= N lanes contribute - double s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0; - double s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0; - double s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0; - double s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0; - - double2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : double2(0,0); - double2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : double2(0,0); - double2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : double2(0,0); - double2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : double2(0,0); - - double3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : double3(0,0,0); - double3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : double3(0,0,0); - double3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : double3(0,0,0); - double3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : double3(0,0,0); - - double4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : double4(0,0,0,0); - double4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : double4(0,0,0,0); - double4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : double4(0,0,0,0); - double4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : double4(0,0,0,0); - - double scalars[4] = { s4, s3, s2, s1 }; - double2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; - double3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; - double4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; - - Out1[tid.x].x = scalars[tid.x]; - Out2[tid.x].xy = vec2s[tid.x]; - Out3[tid.x].xyz = vec3s[tid.x]; - Out4[tid.x] = vec4s[tid.x]; + for (uint ValueSet = 0; ValueSet < VALUE_SETS; ValueSet++) { + const uint ValueSetOffset = ValueSet * NUM_MASKS * NUM_THREADS; + for (uint MaskIdx = 0; MaskIdx < NUM_MASKS; MaskIdx++) { + double4 v = In[ValueSet * ValueSetOffset + MaskIdx * NUM_THREADS + tid.x]; + const uint OutIdx = ValueSetOffset + MaskIdx * NUM_THREADS + tid.x; + if (Masks[MaskIdx].mask[tid.x]) { + Out1[OutIdx] = WaveReadLaneFirst( v.x ); + Out2[OutIdx].xy = WaveReadLaneFirst( v.xy ); + Out3[OutIdx].xyz = WaveReadLaneFirst( v.xyz ); + Out4[OutIdx] = WaveReadLaneFirst( v ); + } + } + } // constant folding case - Out5[0] = WaveReadLaneFirst(double4(1,2,3,4)); + Out5[0] = WaveReadLaneFirst(double4(1.5,2.5,3.5,4.5)); } + //--- pipeline.yaml --- @@ -56,48 +48,186 @@ Shaders: Buffers: - Name: In Format: Float64 - Stride: 32 - Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ] + Stride: 32 + # 2 value sets + # For each value set, + # and for each specific one of the 4 thread masks in that value set, + # and for each of the 4 threads in that thread mask, + # there will be a unique set of 4 values, such that + # none of the other threads in that thread mask share any values + Data: [ + 1.5, 2.5, 3.5, 4.5, # <-- Value set 0, thread mask 0, thread id 0 will read these In values + 5.5, 6.5, 7.5, 8.5, # <-- Value set 0, thread mask 0, thread id 1 will read these In values + 9.5, 10.5, 11.5, 12.5, + 13.5, 14.5, 15.5, 16.5, + 2.5, 3.5, 4.5, 5.5, # <-- Value set 0, thread mask 1, thread id 0 will read these In values + 6.5, 7.5, 8.5, 9.5, + 10.5, 11.5, 12.5, 13.5, + 14.5, 15.5, 16.5, 1.5, + 3.5, 4.5, 5.5, 6.5, + 7.5, 8.5, 9.5, 10.5, + 11.5, 12.5, 13.5, 14.5, + 15.5, 16.5, 1.5, 2.5, + 4.5, 5.5, 6.5, 7.5, + 8.5, 9.5, 10.5, 11.5, + 12.5, 13.5, 14.5, 15.5, + 16.5, 1.5, 2.5, 3.5, + 4.5, 3.5, 2.5, 1.5, # <-- Value set 1, thread mask 0, thread id 0 will read these In values + 8.5, 7.5, 6.5, 5.5, + 12.5, 11.5, 10.5, 9.5, + 16.5, 15.5, 14.5, 13.5, + 5.5, 4.5, 3.5, 2.5, + 9.5, 8.5, 7.5, 6.5, + 13.5, 12.5, 11.5, 10.5, + 1.5, 16.5, 15.5, 14.5, + 6.5, 5.5, 4.5, 3.5, + 10.5, 9.5, 8.5, 7.5, + 14.5, 13.5, 12.5, 11.5, + 2.5, 1.5, 16.5, 15.5, + 7.5, 6.5, 5.5, 4.5, + 11.5, 10.5, 9.5, 8.5, + 15.5, 14.5, 13.5, 12.5, + 3.5, 2.5, 1.5, 16 ] + - Name: Out1 Format: Float64 - Stride: 32 - ZeroInitSize: 128 + Stride: 4 + # 1 double is 8 bytes, * 4 halves for 4 threads, * 4 thread masks, * 2 value sets + FillSize: 256 - Name: Out2 Format: Float64 - Stride: 32 - ZeroInitSize: 128 + Stride: 8 + FillSize: 512 - Name: Out3 Format: Float64 - Stride: 32 - ZeroInitSize: 128 + Stride: 16 + FillSize: 1024 - Name: Out4 Format: Float64 - Stride: 32 - ZeroInitSize: 128 + Stride: 16 + FillSize: 1024 - Name: Out5 Format: Float64 Stride: 32 - ZeroInitSize: 32 + FillSize: 32 + - Name: Masks + Format: Int32 + Stride: 16 + # 4 active mask sets for threads 0, 1, 2, 3: + # 0 0 0 0 + # 1 1 1 1 + # 1 0 0 0 + # 0 1 1 0 + Data: [ + 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0] - Name: ExpectedOut1 Format: Float64 - Stride: 32 - Data: [ 1.0, 0.0, 0.0, 0.0, 2.0, 0.0, 0.0, 0.0, 3.0, 0.0, 0.0, 0.0, 4.0, 0.0, 0.0, 0.0 ] + Stride: 16 + # 2 value sets, 4 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0, 0, 0, 0, + 2.5, 2.5, 2.5, 2.5, + 3.5, 0, 0, 0, + 0, 8.5, 8.5, 0, + 0, 0, 0, 0, + 5.5, 5.5, 5.5, 5.5, + 6.5, 0, 0, 0, + 0, 11.5, 11.5, 0 ] - Name: ExpectedOut2 Format: Float64 - Stride: 32 - Data: [ 1.0, 10.0, 0.0, 0.0, 2.0, 20.0, 0.0, 0.0, 3.0, 30.0, 0.0, 0.0, 4.0, 40.0, 0.0, 0.0 ] + Stride: 16 + # 2 value sets, 4 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 2.5, 3.5, 2.5, 3.5, + 2.5, 3.5, 2.5, 3.5, + 3.5, 4.5, 0, 0, + 0, 0, 0, 0, + 0, 0, 8.5, 9.5, + 8.5, 9.5, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5.5, 4.5, 5.5, 4.5, + 5.5, 4.5, 5.5, 4.5, + 6.5, 5.5, 0, 0, + 0, 0, 0, 0, + 0, 0, 11.5, 10.5, + 11.5, 10.5, 0, 0 ] - Name: ExpectedOut3 Format: Float64 - Stride: 32 - Data: [ 1.0, 10.0, 100.0, 0.0, 2.0, 20.0, 200.0, 0.0, 3.0, 30.0, 300.0, 0.0, 4.0, 40.0, 400.0, 0.0 ] + Stride: 16 + # 2 value sets.5, 4 masks per value set, 4 threads per mask, 4 result values per thread + # Note, vecs of 3 must be aligned.5, so the 3 result values are placed doubleo a 4 element vec + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2.5, 3.5, 4.5, 0, + 2.5, 3.5, 4.5, 0, + 2.5, 3.5, 4.5, 0, + 2.5, 3.5, 4.5, 0, + 3.5, 4.5, 5.5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 8.5, 9.5, 10.5, 0, + 8.5, 9.5, 10.5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5.5, 4.5, 3.5, 0, + 5.5, 4.5, 3.5, 0, + 5.5, 4.5, 3.5, 0, + 5.5, 4.5, 3.5, 0, + 6.5, 5.5, 4.5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 11.5, 10.5, 9.5, 0, + 11.5, 10.5, 9.5, 0, + 0, 0, 0, 0] - Name: ExpectedOut4 Format: Float64 - Stride: 32 - Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ] + Stride: 16 + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2.5, 3.5, 4.5, 5.5, + 2.5, 3.5, 4.5, 5.5, + 2.5, 3.5, 4.5, 5.5, + 2.5, 3.5, 4.5, 5.5, + 3.5, 4.5, 5.5, 6.5, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 8.5, 9.5, 10.5, 11.5, + 8.5, 9.5, 10.5, 11.5, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5.5, 4.5, 3.5, 2.5, + 5.5, 4.5, 3.5, 2.5, + 5.5, 4.5, 3.5, 2.5, + 5.5, 4.5, 3.5, 2.5, + 6.5, 5.5, 4.5, 3.5, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 11.5, 10.5, 9.5, 8.5, + 11.5, 10.5, 9.5, 8.5, + 0, 0, 0, 0] - Name: ExpectedOut5 Format: Float64 - Stride: 32 - Data: [ 1, 2, 3, 4 ] + Stride: 8 + Data: [ 1.5, 2.5, 3.5, 4.5 ] Results: - Result: ExpectedOut1 Rule: BufferExact @@ -119,7 +249,6 @@ Results: Rule: BufferExact Actual: Out5 Expected: ExpectedOut5 - DescriptorSets: - Resources: - Name: In @@ -164,19 +293,22 @@ DescriptorSets: Space: 0 VulkanBinding: Binding: 5 + - Name: Masks + Kind: StructuredBuffer + DirectXBinding: + Register: 6 + Space: 0 + VulkanBinding: + Binding: 6 + ... #--- end -# REQUIRES: Double - -# Bug https://github.com/llvm/offload-test-suite/issues/393 -# XFAIL: Metal - # Bug https://github.com/llvm/llvm-project/issues/156775 # XFAIL: Clang -# Bug https://github.com/llvm/offload-test-suite/issues/433 -# XFAIL: DirectX-WARP +# Bug https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl diff --git a/test/WaveOps/WaveReadLaneFirst.int16.test b/test/WaveOps/WaveReadLaneFirst.int16.test index e6f4725bb..29f1b0ae1 100644 --- a/test/WaveOps/WaveReadLaneFirst.int16.test +++ b/test/WaveOps/WaveReadLaneFirst.int16.test @@ -1,97 +1,43 @@ #--- source.hlsl +#define VALUE_SETS 2 +#define NUM_MASKS 4 +#define NUM_THREADS 4 + +struct MaskStruct { + int mask[NUM_THREADS]; +}; + StructuredBuffer In : register(t0); -RWStructuredBuffer Out1 : register(u1); // test scalar -RWStructuredBuffer Out2 : register(u2); // test int16_t2 +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test int16_t2 RWStructuredBuffer Out3 : register(u3); // test int16_t3 RWStructuredBuffer Out4 : register(u4); // test int16_t4 RWStructuredBuffer Out5 : register(u5); // constant folding +StructuredBuffer Masks : register(t6); -// uint16_ts -StructuredBuffer UIn : register(t6); -RWStructuredBuffer UOut1 : register(u7); -RWStructuredBuffer UOut2 : register(u8); -RWStructuredBuffer UOut3 : register(u9); -RWStructuredBuffer UOut4 : register(u10); -RWStructuredBuffer UOut5 : register(u11); -[numthreads(4,1,1)] +[numthreads(NUM_THREADS,1,1)] void main(uint3 tid : SV_GroupThreadID) { - int16_t4 v = In[tid.x]; - - // Mask per "active lane set": only >= N lanes contribute - int16_t s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0; - int16_t s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0; - int16_t s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0; - int16_t s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0; - - int16_t2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : int16_t2(0,0); - int16_t2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : int16_t2(0,0); - int16_t2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : int16_t2(0,0); - int16_t2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : int16_t2(0,0); - - int16_t3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : int16_t3(0,0,0); - int16_t3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : int16_t3(0,0,0); - int16_t3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : int16_t3(0,0,0); - int16_t3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : int16_t3(0,0,0); - - int16_t4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : int16_t4(0,0,0,0); - int16_t4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : int16_t4(0,0,0,0); - int16_t4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : int16_t4(0,0,0,0); - int16_t4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : int16_t4(0,0,0,0); - - int16_t scalars[4] = { s4, s3, s2, s1 }; - int16_t2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; - int16_t3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; - int16_t4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; - - Out1[tid.x].x = scalars[tid.x]; - Out2[tid.x].xy = vec2s[tid.x]; - Out3[tid.x].xyz = vec3s[tid.x]; - Out4[tid.x] = vec4s[tid.x]; - - // constant folding case - Out5[0] = WaveReadLaneFirst(int16_t4(1,2,3,4)); - - // UINT16_t case - - uint16_t4 uv = UIn[tid.x]; - - // Mask per "active lane set": only >= N lanes contribute - uint16_t us1 = tid.x >= 3 ? WaveReadLaneFirst( uv.x ) : 0; - uint16_t us2 = tid.x >= 2 ? WaveReadLaneFirst( uv.x ) : 0; - uint16_t us3 = tid.x >= 1 ? WaveReadLaneFirst( uv.x ) : 0; - uint16_t us4 = tid.x >= 0 ? WaveReadLaneFirst( uv.x ) : 0; - - uint16_t2 uv2_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xy ) : uint16_t2(0,0); - uint16_t2 uv2_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xy ) : uint16_t2(0,0); - uint16_t2 uv2_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xy ) : uint16_t2(0,0); - uint16_t2 uv2_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xy ) : uint16_t2(0,0); - - uint16_t3 uv3_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xyz ) : uint16_t3(0,0,0); - uint16_t3 uv3_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xyz ) : uint16_t3(0,0,0); - uint16_t3 uv3_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xyz ) : uint16_t3(0,0,0); - uint16_t3 uv3_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xyz ) : uint16_t3(0,0,0); - - uint16_t4 uv4_1 = tid.x >= 3 ? WaveReadLaneFirst( uv ) : uint16_t4(0,0,0,0); - uint16_t4 uv4_2 = tid.x >= 2 ? WaveReadLaneFirst( uv ) : uint16_t4(0,0,0,0); - uint16_t4 uv4_3 = tid.x >= 1 ? WaveReadLaneFirst( uv ) : uint16_t4(0,0,0,0); - uint16_t4 uv4_4 = tid.x >= 0 ? WaveReadLaneFirst( uv ) : uint16_t4(0,0,0,0); - - uint16_t uscalars[4] = { us4, us3, us2, us1 }; - uint16_t2 uvec2s [4] = { uv2_4, uv2_3, uv2_2, uv2_1 }; - uint16_t3 uvec3s [4] = { uv3_4, uv3_3, uv3_2, uv3_1 }; - uint16_t4 uvec4s [4] = { uv4_4, uv4_3, uv4_2, uv4_1 }; - - UOut1[tid.x].x = uscalars[tid.x]; - UOut2[tid.x].xy = uvec2s[tid.x]; - UOut3[tid.x].xyz = uvec3s[tid.x]; - UOut4[tid.x] = uvec4s[tid.x]; + for (uint ValueSet = 0; ValueSet < VALUE_SETS; ValueSet++) { + const uint ValueSetOffset = ValueSet * NUM_MASKS * NUM_THREADS; + for (uint MaskIdx = 0; MaskIdx < NUM_MASKS; MaskIdx++) { + int16_t4 v = In[ValueSet * ValueSetOffset + MaskIdx * NUM_THREADS + tid.x]; + const uint OutIdx = ValueSetOffset + MaskIdx * NUM_THREADS + tid.x; + if (Masks[MaskIdx].mask[tid.x]) { + Out1[OutIdx] = WaveReadLaneFirst( v.x ); + Out2[OutIdx].xy = WaveReadLaneFirst( v.xy ); + Out3[OutIdx].xyz = WaveReadLaneFirst( v.xyz ); + Out4[OutIdx] = WaveReadLaneFirst( v ); + } + } + } // constant folding case - UOut5[0] = WaveReadLaneFirst(uint16_t4(1,2,3,4)); + Out5[0] = WaveReadLaneFirst(int16_t4(1,2,3,4)); } + //--- pipeline.yaml --- @@ -102,92 +48,186 @@ Shaders: Buffers: - Name: In Format: Int16 - Stride: 8 - Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + Stride: 8 + # 2 value sets + # For each value set, + # and for each specific one of the 4 thread masks in that value set, + # and for each of the 4 threads in that thread mask, + # there will be a unique set of 4 values, such that + # none of the other threads in that thread mask share any values + Data: [ + 1, 2, 3, 4, # <-- Value set 0, thread mask 0, thread id 0 will read these In values + 5, 6, 7, 8, # <-- Value set 0, thread mask 0, thread id 1 will read these In values + 9, 10, 11, 12, + 13, 14, 15, 16, + 2, 3, 4, 5, # <-- Value set 0, thread mask 1, thread id 0 will read these In values + 6, 7, 8, 9, + 10, 11, 12, 13, + 14, 15, 16, 1, + 3, 4, 5, 6, + 7, 8, 9, 10, + 11, 12, 13, 14, + 15, 16, 1, 2, + 4, 5, 6, 7, + 8, 9, 10, 11, + 12, 13, 14, 15, + 16, 1, 2, 3, + 4, 3, 2, 1, # <-- Value set 1, thread mask 0, thread id 0 will read these In values + 8, 7, 6, 5, + 12, 11, 10, 9, + 16, 15, 14, 13, + 5, 4, 3, 2, + 9, 8, 7, 6, + 13, 12, 11, 10, + 1, 16, 15, 14, + 6, 5, 4, 3, + 10, 9, 8, 7, + 14, 13, 12, 11, + 2, 1, 16, 15, + 7, 6, 5, 4, + 11, 10, 9, 8, + 15, 14, 13, 12, + 3, 2, 1, 16 ] + - Name: Out1 Format: Int16 - Stride: 8 - ZeroInitSize: 32 + Stride: 2 + # 1 int16_t is 2 bytes, * 4 halves for 4 threads, * 4 thread masks, * 2 value sets + FillSize: 64 - Name: Out2 Format: Int16 - Stride: 8 - ZeroInitSize: 32 + Stride: 4 + FillSize: 128 - Name: Out3 Format: Int16 Stride: 8 - ZeroInitSize: 32 + FillSize: 256 - Name: Out4 Format: Int16 Stride: 8 - ZeroInitSize: 32 + FillSize: 256 - Name: Out5 Format: Int16 Stride: 8 - ZeroInitSize: 8 + FillSize: 8 + - Name: Masks + Format: Int32 + Stride: 16 + # 4 active mask sets for threads 0, 1, 2, 3: + # 0 0 0 0 + # 1 1 1 1 + # 1 0 0 0 + # 0 1 1 0 + Data: [ + 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0] - Name: ExpectedOut1 Format: Int16 Stride: 8 - Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0, 0, 0, 0, + 2, 2, 2, 2, + 3, 0, 0, 0, + 0, 8, 8, 0, + 0, 0, 0, 0, + 5, 5, 5, 5, + 6, 0, 0, 0, + 0, 11, 11, 0 ] - Name: ExpectedOut2 Format: Int16 Stride: 8 - Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 3, 2, 3, + 2, 3, 2, 3, + 3, 4, 0, 0, + 0, 0, 0, 0, + 0, 0, 8, 9, + 8, 9, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5, 4, 5, 4, + 5, 4, 5, 4, + 6, 5, 0, 0, + 0, 0, 0, 0, + 0, 0, 11, 10, + 11, 10, 0, 0 ] - Name: ExpectedOut3 Format: Int16 Stride: 8 - Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 4 result values per thread + # Note, vecs of 3 must be aligned, so the 3 result values are placed into a 4 element vec + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 3, 4, 0, + 2, 3, 4, 0, + 2, 3, 4, 0, + 2, 3, 4, 0, + 3, 4, 5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 8, 9, 10, 0, + 8, 9, 10, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5, 4, 3, 0, + 5, 4, 3, 0, + 5, 4, 3, 0, + 5, 4, 3, 0, + 6, 5, 4, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 11, 10, 9, 0, + 11, 10, 9, 0, + 0, 0, 0, 0 ] - Name: ExpectedOut4 Format: Int16 Stride: 8 - Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 3, 4, 5, + 2, 3, 4, 5, + 2, 3, 4, 5, + 2, 3, 4, 5, + 3, 4, 5, 6, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 8, 9, 10, 11, + 8, 9, 10, 11, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5, 4, 3, 2, + 5, 4, 3, 2, + 5, 4, 3, 2, + 5, 4, 3, 2, + 6, 5, 4, 3, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 11, 10, 9, 8, + 11, 10, 9, 8, + 0, 0, 0, 0 ] - Name: ExpectedOut5 Format: Int16 Stride: 8 Data: [ 1, 2, 3, 4 ] - - Name: UIn - Format: UInt16 - Stride: 8 - Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] - - Name: UOut1 - Format: UInt16 - Stride: 8 - ZeroInitSize: 32 - - Name: UOut2 - Format: UInt16 - Stride: 8 - ZeroInitSize: 32 - - Name: UOut3 - Format: UInt16 - Stride: 8 - ZeroInitSize: 32 - - Name: UOut4 - Format: UInt16 - Stride: 8 - ZeroInitSize: 32 - - Name: UOut5 - Format: UInt16 - Stride: 8 - ZeroInitSize: 8 - - Name: UExpectedOut1 - Format: UInt16 - Stride: 8 - Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] - - Name: UExpectedOut2 - Format: UInt16 - Stride: 8 - Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] - - Name: UExpectedOut3 - Format: UInt16 - Stride: 8 - Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] - - Name: UExpectedOut4 - Format: UInt16 - Stride: 8 - Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] - - Name: UExpectedOut5 - Format: UInt16 - Stride: 8 - Data: [ 1, 2, 3, 4 ] Results: - Result: ExpectedOut1 Rule: BufferExact @@ -209,26 +249,6 @@ Results: Rule: BufferExact Actual: Out5 Expected: ExpectedOut5 - - Result: UExpectedOut1 - Rule: BufferExact - Actual: UOut1 - Expected: UExpectedOut1 - - Result: UExpectedOut2 - Rule: BufferExact - Actual: UOut2 - Expected: UExpectedOut2 - - Result: UExpectedOut3 - Rule: BufferExact - Actual: UOut3 - Expected: UExpectedOut3 - - Result: UExpectedOut4 - Rule: BufferExact - Actual: UOut4 - Expected: UExpectedOut4 - - Result: UExpectedOut5 - Rule: BufferExact - Actual: UOut5 - Expected: UExpectedOut5 DescriptorSets: - Resources: - Name: In @@ -273,59 +293,23 @@ DescriptorSets: Space: 0 VulkanBinding: Binding: 5 - - Name: UIn + - Name: Masks Kind: StructuredBuffer DirectXBinding: Register: 6 Space: 0 VulkanBinding: Binding: 6 - - Name: UOut1 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 7 - Space: 0 - VulkanBinding: - Binding: 7 - - Name: UOut2 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 8 - Space: 0 - VulkanBinding: - Binding: 8 - - Name: UOut3 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 9 - Space: 0 - VulkanBinding: - Binding: 9 - - Name: UOut4 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 10 - Space: 0 - VulkanBinding: - Binding: 10 - - Name: UOut5 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 11 - Space: 0 - VulkanBinding: - Binding: 11 ... #--- end +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang # Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal -# Bug https://github.com/llvm/llvm-project/issues/156775 -# XFAIL: Clang - # RUN: split-file %s %t # RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.int32.test b/test/WaveOps/WaveReadLaneFirst.int32.test index 284ff82c3..29680fc85 100644 --- a/test/WaveOps/WaveReadLaneFirst.int32.test +++ b/test/WaveOps/WaveReadLaneFirst.int32.test @@ -1,97 +1,43 @@ #--- source.hlsl +#define VALUE_SETS 2 +#define NUM_MASKS 4 +#define NUM_THREADS 4 + +struct MaskStruct { + int mask[NUM_THREADS]; +}; + StructuredBuffer In : register(t0); -RWStructuredBuffer Out1 : register(u1); // test scalar -RWStructuredBuffer Out2 : register(u2); // test int2 +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test int2 RWStructuredBuffer Out3 : register(u3); // test int3 RWStructuredBuffer Out4 : register(u4); // test int4 RWStructuredBuffer Out5 : register(u5); // constant folding +StructuredBuffer Masks : register(t6); -// uints -StructuredBuffer UIn : register(t6); -RWStructuredBuffer UOut1 : register(u7); -RWStructuredBuffer UOut2 : register(u8); -RWStructuredBuffer UOut3 : register(u9); -RWStructuredBuffer UOut4 : register(u10); -RWStructuredBuffer UOut5 : register(u11); -[numthreads(4,1,1)] +[numthreads(NUM_THREADS,1,1)] void main(uint3 tid : SV_GroupThreadID) { - int4 v = In[tid.x]; - - // Mask per "active lane set": only >= N lanes contribute - int s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0; - int s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0; - int s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0; - int s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0; - - int2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : int2(0,0); - int2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : int2(0,0); - int2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : int2(0,0); - int2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : int2(0,0); - - int3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : int3(0,0,0); - int3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : int3(0,0,0); - int3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : int3(0,0,0); - int3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : int3(0,0,0); - - int4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : int4(0,0,0,0); - int4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : int4(0,0,0,0); - int4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : int4(0,0,0,0); - int4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : int4(0,0,0,0); - - int scalars[4] = { s4, s3, s2, s1 }; - int2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; - int3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; - int4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; - - Out1[tid.x].x = scalars[tid.x]; - Out2[tid.x].xy = vec2s[tid.x]; - Out3[tid.x].xyz = vec3s[tid.x]; - Out4[tid.x] = vec4s[tid.x]; - - // constant folding case - Out5[0] = WaveReadLaneFirst(int4(1,2,3,4)); - - // UINT case - - uint4 uv = UIn[tid.x]; - - // Mask per "active lane set": only >= N lanes contribute - uint us1 = tid.x >= 3 ? WaveReadLaneFirst( uv.x ) : 0; - uint us2 = tid.x >= 2 ? WaveReadLaneFirst( uv.x ) : 0; - uint us3 = tid.x >= 1 ? WaveReadLaneFirst( uv.x ) : 0; - uint us4 = tid.x >= 0 ? WaveReadLaneFirst( uv.x ) : 0; - - uint2 uv2_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xy ) : uint2(0,0); - uint2 uv2_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xy ) : uint2(0,0); - uint2 uv2_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xy ) : uint2(0,0); - uint2 uv2_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xy ) : uint2(0,0); - - uint3 uv3_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xyz ) : uint3(0,0,0); - uint3 uv3_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xyz ) : uint3(0,0,0); - uint3 uv3_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xyz ) : uint3(0,0,0); - uint3 uv3_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xyz ) : uint3(0,0,0); - - uint4 uv4_1 = tid.x >= 3 ? WaveReadLaneFirst( uv ) : uint4(0,0,0,0); - uint4 uv4_2 = tid.x >= 2 ? WaveReadLaneFirst( uv ) : uint4(0,0,0,0); - uint4 uv4_3 = tid.x >= 1 ? WaveReadLaneFirst( uv ) : uint4(0,0,0,0); - uint4 uv4_4 = tid.x >= 0 ? WaveReadLaneFirst( uv ) : uint4(0,0,0,0); - - uint uscalars[4] = { us4, us3, us2, us1 }; - uint2 uvec2s [4] = { uv2_4, uv2_3, uv2_2, uv2_1 }; - uint3 uvec3s [4] = { uv3_4, uv3_3, uv3_2, uv3_1 }; - uint4 uvec4s [4] = { uv4_4, uv4_3, uv4_2, uv4_1 }; - - UOut1[tid.x].x = uscalars[tid.x]; - UOut2[tid.x].xy = uvec2s[tid.x]; - UOut3[tid.x].xyz = uvec3s[tid.x]; - UOut4[tid.x] = uvec4s[tid.x]; + for (uint ValueSet = 0; ValueSet < VALUE_SETS; ValueSet++) { + const uint ValueSetOffset = ValueSet * NUM_MASKS * NUM_THREADS; + for (uint MaskIdx = 0; MaskIdx < NUM_MASKS; MaskIdx++) { + int4 v = In[ValueSet * ValueSetOffset + MaskIdx * NUM_THREADS + tid.x]; + const uint OutIdx = ValueSetOffset + MaskIdx * NUM_THREADS + tid.x; + if (Masks[MaskIdx].mask[tid.x]) { + Out1[OutIdx] = WaveReadLaneFirst( v.x ); + Out2[OutIdx].xy = WaveReadLaneFirst( v.xy ); + Out3[OutIdx].xyz = WaveReadLaneFirst( v.xyz ); + Out4[OutIdx] = WaveReadLaneFirst( v ); + } + } + } // constant folding case - UOut5[0] = WaveReadLaneFirst(uint4(1,2,3,4)); + Out5[0] = WaveReadLaneFirst(int4(1,2,3,4)); } + //--- pipeline.yaml --- @@ -102,91 +48,185 @@ Shaders: Buffers: - Name: In Format: Int32 - Stride: 16 - Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + Stride: 16 + # 2 value sets + # For each value set, + # and for each specific one of the 4 thread masks in that value set, + # and for each of the 4 threads in that thread mask, + # there will be a unique set of 4 values, such that + # none of the other threads in that thread mask share any values + Data: [ + 1, 2, 3, 4, # <-- Value set 0, thread mask 0, thread id 0 will read these In values + 5, 6, 7, 8, # <-- Value set 0, thread mask 0, thread id 1 will read these In values + 9, 10, 11, 12, + 13, 14, 15, 16, + 2, 3, 4, 5, # <-- Value set 0, thread mask 1, thread id 0 will read these In values + 6, 7, 8, 9, + 10, 11, 12, 13, + 14, 15, 16, 1, + 3, 4, 5, 6, + 7, 8, 9, 10, + 11, 12, 13, 14, + 15, 16, 1, 2, + 4, 5, 6, 7, + 8, 9, 10, 11, + 12, 13, 14, 15, + 16, 1, 2, 3, + 4, 3, 2, 1, # <-- Value set 1, thread mask 0, thread id 0 will read these In values + 8, 7, 6, 5, + 12, 11, 10, 9, + 16, 15, 14, 13, + 5, 4, 3, 2, + 9, 8, 7, 6, + 13, 12, 11, 10, + 1, 16, 15, 14, + 6, 5, 4, 3, + 10, 9, 8, 7, + 14, 13, 12, 11, + 2, 1, 16, 15, + 7, 6, 5, 4, + 11, 10, 9, 8, + 15, 14, 13, 12, + 3, 2, 1, 16 ] + - Name: Out1 Format: Int32 - Stride: 16 - ZeroInitSize: 64 + Stride: 4 + # 1 int is 4 bytes, * 4 halves for 4 threads, * 4 thread masks, * 2 value sets + FillSize: 128 - Name: Out2 Format: Int32 - Stride: 16 - ZeroInitSize: 64 + Stride: 8 + FillSize: 256 - Name: Out3 Format: Int32 Stride: 16 - ZeroInitSize: 64 + FillSize: 512 - Name: Out4 Format: Int32 Stride: 16 - ZeroInitSize: 64 + FillSize: 512 - Name: Out5 Format: Int32 Stride: 16 - ZeroInitSize: 16 + FillSize: 16 + - Name: Masks + Format: Int32 + Stride: 16 + # 4 active mask sets for threads 0, 1, 2, 3: + # 0 0 0 0 + # 1 1 1 1 + # 1 0 0 0 + # 0 1 1 0 + Data: [ + 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0] - Name: ExpectedOut1 Format: Int32 Stride: 16 - Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0, 0, 0, 0, + 2, 2, 2, 2, + 3, 0, 0, 0, + 0, 8, 8, 0, + 0, 0, 0, 0, + 5, 5, 5, 5, + 6, 0, 0, 0, + 0, 11, 11, 0 ] - Name: ExpectedOut2 Format: Int32 Stride: 16 - Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 3, 2, 3, + 2, 3, 2, 3, + 3, 4, 0, 0, + 0, 0, 0, 0, + 0, 0, 8, 9, + 8, 9, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5, 4, 5, 4, + 5, 4, 5, 4, + 6, 5, 0, 0, + 0, 0, 0, 0, + 0, 0, 11, 10, + 11, 10, 0, 0 ] - Name: ExpectedOut3 Format: Int32 Stride: 16 - Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 4 result values per thread + # Note, vecs of 3 must be aligned, so the 3 result values are placed into a 4 element vec + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 3, 4, 0, + 2, 3, 4, 0, + 2, 3, 4, 0, + 2, 3, 4, 0, + 3, 4, 5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 8, 9, 10, 0, + 8, 9, 10, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5, 4, 3, 0, + 5, 4, 3, 0, + 5, 4, 3, 0, + 5, 4, 3, 0, + 6, 5, 4, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 11, 10, 9, 0, + 11, 10, 9, 0, + 0, 0, 0, 0 ] - Name: ExpectedOut4 Format: Int32 Stride: 16 - Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 3, 4, 5, + 2, 3, 4, 5, + 2, 3, 4, 5, + 2, 3, 4, 5, + 3, 4, 5, 6, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 8, 9, 10, 11, + 8, 9, 10, 11, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5, 4, 3, 2, + 5, 4, 3, 2, + 5, 4, 3, 2, + 5, 4, 3, 2, + 6, 5, 4, 3, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 11, 10, 9, 8, + 11, 10, 9, 8, + 0, 0, 0, 0 ] - Name: ExpectedOut5 Format: Int32 - Stride: 16 - Data: [ 1, 2, 3, 4 ] - - Name: UIn - Format: UInt32 - Stride: 16 - Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] - - Name: UOut1 - Format: UInt32 - Stride: 16 - ZeroInitSize: 64 - - Name: UOut2 - Format: UInt32 - Stride: 16 - ZeroInitSize: 64 - - Name: UOut3 - Format: UInt32 - Stride: 16 - ZeroInitSize: 64 - - Name: UOut4 - Format: UInt32 - Stride: 16 - ZeroInitSize: 64 - - Name: UOut5 - Format: UInt32 - Stride: 16 - ZeroInitSize: 16 - - Name: UExpectedOut1 - Format: UInt32 - Stride: 16 - Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] - - Name: UExpectedOut2 - Format: UInt32 - Stride: 16 - Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] - - Name: UExpectedOut3 - Format: UInt32 - Stride: 16 - Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] - - Name: UExpectedOut4 - Format: UInt32 - Stride: 16 - Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] - - Name: UExpectedOut5 - Format: UInt32 - Stride: 16 + Stride: 8 Data: [ 1, 2, 3, 4 ] Results: - Result: ExpectedOut1 @@ -209,26 +249,6 @@ Results: Rule: BufferExact Actual: Out5 Expected: ExpectedOut5 - - Result: UExpectedOut1 - Rule: BufferExact - Actual: UOut1 - Expected: UExpectedOut1 - - Result: UExpectedOut2 - Rule: BufferExact - Actual: UOut2 - Expected: UExpectedOut2 - - Result: UExpectedOut3 - Rule: BufferExact - Actual: UOut3 - Expected: UExpectedOut3 - - Result: UExpectedOut4 - Rule: BufferExact - Actual: UOut4 - Expected: UExpectedOut4 - - Result: UExpectedOut5 - Rule: BufferExact - Actual: UOut5 - Expected: UExpectedOut5 DescriptorSets: - Resources: - Name: In @@ -273,59 +293,23 @@ DescriptorSets: Space: 0 VulkanBinding: Binding: 5 - - Name: UIn + - Name: Masks Kind: StructuredBuffer DirectXBinding: Register: 6 Space: 0 VulkanBinding: Binding: 6 - - Name: UOut1 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 7 - Space: 0 - VulkanBinding: - Binding: 7 - - Name: UOut2 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 8 - Space: 0 - VulkanBinding: - Binding: 8 - - Name: UOut3 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 9 - Space: 0 - VulkanBinding: - Binding: 9 - - Name: UOut4 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 10 - Space: 0 - VulkanBinding: - Binding: 10 - - Name: UOut5 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 11 - Space: 0 - VulkanBinding: - Binding: 11 ... #--- end +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang # Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal -# Bug https://github.com/llvm/llvm-project/issues/156775 -# XFAIL: Clang - # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.int64.test b/test/WaveOps/WaveReadLaneFirst.int64.test index 09c8bce57..58d4d55c3 100644 --- a/test/WaveOps/WaveReadLaneFirst.int64.test +++ b/test/WaveOps/WaveReadLaneFirst.int64.test @@ -1,97 +1,43 @@ #--- source.hlsl +#define VALUE_SETS 2 +#define NUM_MASKS 4 +#define NUM_THREADS 4 + +struct MaskStruct { + int mask[NUM_THREADS]; +}; + StructuredBuffer In : register(t0); -RWStructuredBuffer Out1 : register(u1); // test scalar -RWStructuredBuffer Out2 : register(u2); // test int64_t2 +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test int64_t2 RWStructuredBuffer Out3 : register(u3); // test int64_t3 RWStructuredBuffer Out4 : register(u4); // test int64_t4 RWStructuredBuffer Out5 : register(u5); // constant folding +StructuredBuffer Masks : register(t6); -// uint64_ts -StructuredBuffer UIn : register(t6); -RWStructuredBuffer UOut1 : register(u7); -RWStructuredBuffer UOut2 : register(u8); -RWStructuredBuffer UOut3 : register(u9); -RWStructuredBuffer UOut4 : register(u10); -RWStructuredBuffer UOut5 : register(u11); -[numthreads(4,1,1)] +[numthreads(NUM_THREADS,1,1)] void main(uint3 tid : SV_GroupThreadID) { - int64_t4 v = In[tid.x]; - - // Mask per "active lane set": only >= N lanes contribute - int64_t s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0; - int64_t s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0; - int64_t s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0; - int64_t s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0; - - int64_t2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : int64_t2(0,0); - int64_t2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : int64_t2(0,0); - int64_t2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : int64_t2(0,0); - int64_t2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : int64_t2(0,0); - - int64_t3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : int64_t3(0,0,0); - int64_t3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : int64_t3(0,0,0); - int64_t3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : int64_t3(0,0,0); - int64_t3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : int64_t3(0,0,0); - - int64_t4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : int64_t4(0,0,0,0); - int64_t4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : int64_t4(0,0,0,0); - int64_t4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : int64_t4(0,0,0,0); - int64_t4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : int64_t4(0,0,0,0); - - int64_t scalars[4] = { s4, s3, s2, s1 }; - int64_t2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; - int64_t3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; - int64_t4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; - - Out1[tid.x].x = scalars[tid.x]; - Out2[tid.x].xy = vec2s[tid.x]; - Out3[tid.x].xyz = vec3s[tid.x]; - Out4[tid.x] = vec4s[tid.x]; + for (uint ValueSet = 0; ValueSet < VALUE_SETS; ValueSet++) { + const uint ValueSetOffset = ValueSet * NUM_MASKS * NUM_THREADS; + for (uint MaskIdx = 0; MaskIdx < NUM_MASKS; MaskIdx++) { + int64_t4 v = In[ValueSet * ValueSetOffset + MaskIdx * NUM_THREADS + tid.x]; + const uint OutIdx = ValueSetOffset + MaskIdx * NUM_THREADS + tid.x; + if (Masks[MaskIdx].mask[tid.x]) { + Out1[OutIdx] = WaveReadLaneFirst( v.x ); + Out2[OutIdx].xy = WaveReadLaneFirst( v.xy ); + Out3[OutIdx].xyz = WaveReadLaneFirst( v.xyz ); + Out4[OutIdx] = WaveReadLaneFirst( v ); + } + } + } // constant folding case - Out5[0] = WaveReadLaneFirst(int64_t4(1,2,3,4)); - - // UINT64_t case - - uint64_t4 uv = UIn[tid.x]; - - // Mask per "active lane set": only >= N lanes contribute - uint64_t us1 = tid.x >= 3 ? WaveReadLaneFirst( uv.x ) : 0; - uint64_t us2 = tid.x >= 2 ? WaveReadLaneFirst( uv.x ) : 0; - uint64_t us3 = tid.x >= 1 ? WaveReadLaneFirst( uv.x ) : 0; - uint64_t us4 = tid.x >= 0 ? WaveReadLaneFirst( uv.x ) : 0; - - uint64_t2 uv2_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xy ) : uint64_t2(0,0); - uint64_t2 uv2_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xy ) : uint64_t2(0,0); - uint64_t2 uv2_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xy ) : uint64_t2(0,0); - uint64_t2 uv2_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xy ) : uint64_t2(0,0); - - uint64_t3 uv3_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xyz ) : uint64_t3(0,0,0); - uint64_t3 uv3_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xyz ) : uint64_t3(0,0,0); - uint64_t3 uv3_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xyz ) : uint64_t3(0,0,0); - uint64_t3 uv3_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xyz ) : uint64_t3(0,0,0); - - uint64_t4 uv4_1 = tid.x >= 3 ? WaveReadLaneFirst( uv ) : uint64_t4(0,0,0,0); - uint64_t4 uv4_2 = tid.x >= 2 ? WaveReadLaneFirst( uv ) : uint64_t4(0,0,0,0); - uint64_t4 uv4_3 = tid.x >= 1 ? WaveReadLaneFirst( uv ) : uint64_t4(0,0,0,0); - uint64_t4 uv4_4 = tid.x >= 0 ? WaveReadLaneFirst( uv ) : uint64_t4(0,0,0,0); - - uint64_t uscalars[4] = { us4, us3, us2, us1 }; - uint64_t2 uvec2s [4] = { uv2_4, uv2_3, uv2_2, uv2_1 }; - uint64_t3 uvec3s [4] = { uv3_4, uv3_3, uv3_2, uv3_1 }; - uint64_t4 uvec4s [4] = { uv4_4, uv4_3, uv4_2, uv4_1 }; - - UOut1[tid.x].x = uscalars[tid.x]; - UOut2[tid.x].xy = uvec2s[tid.x]; - UOut3[tid.x].xyz = uvec3s[tid.x]; - UOut4[tid.x] = uvec4s[tid.x]; - - // constant folding case - UOut5[0] = WaveReadLaneFirst(uint64_t4(1,2,3,4)); + Out5[0] = WaveReadLaneFirst(int64_t4(1,2,3,4)); } + //--- pipeline.yaml --- @@ -102,91 +48,185 @@ Shaders: Buffers: - Name: In Format: Int64 - Stride: 32 - Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + Stride: 32 + # 2 value sets + # For each value set, + # and for each specific one of the 4 thread masks in that value set, + # and for each of the 4 threads in that thread mask, + # there will be a unique set of 4 values, such that + # none of the other threads in that thread mask share any values + Data: [ + 1, 2, 3, 4, # <-- Value set 0, thread mask 0, thread id 0 will read these In values + 5, 6, 7, 8, # <-- Value set 0, thread mask 0, thread id 1 will read these In values + 9, 10, 11, 12, + 13, 14, 15, 16, + 2, 3, 4, 5, # <-- Value set 0, thread mask 1, thread id 0 will read these In values + 6, 7, 8, 9, + 10, 11, 12, 13, + 14, 15, 16, 1, + 3, 4, 5, 6, + 7, 8, 9, 10, + 11, 12, 13, 14, + 15, 16, 1, 2, + 4, 5, 6, 7, + 8, 9, 10, 11, + 12, 13, 14, 15, + 16, 1, 2, 3, + 4, 3, 2, 1, # <-- Value set 1, thread mask 0, thread id 0 will read these In values + 8, 7, 6, 5, + 12, 11, 10, 9, + 16, 15, 14, 13, + 5, 4, 3, 2, + 9, 8, 7, 6, + 13, 12, 11, 10, + 1, 16, 15, 14, + 6, 5, 4, 3, + 10, 9, 8, 7, + 14, 13, 12, 11, + 2, 1, 16, 15, + 7, 6, 5, 4, + 11, 10, 9, 8, + 15, 14, 13, 12, + 3, 2, 1, 16 ] + - Name: Out1 Format: Int64 - Stride: 32 - ZeroInitSize: 128 + Stride: 8 + # 1 int is 8 bytes, * 4 ints for 4 threads, * 4 thread masks, * 2 value sets + FillSize: 256 - Name: Out2 Format: Int64 - Stride: 32 - ZeroInitSize: 128 + Stride: 16 + FillSize: 512 - Name: Out3 Format: Int64 Stride: 32 - ZeroInitSize: 128 + FillSize: 1024 - Name: Out4 Format: Int64 Stride: 32 - ZeroInitSize: 128 + FillSize: 1024 - Name: Out5 Format: Int64 Stride: 32 - ZeroInitSize: 32 + FillSize: 32 + - Name: Masks + Format: Int32 + Stride: 16 + # 4 active mask sets for threads 0, 1, 2, 3: + # 0 0 0 0 + # 1 1 1 1 + # 1 0 0 0 + # 0 1 1 0 + Data: [ + 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0] - Name: ExpectedOut1 Format: Int64 Stride: 32 - Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0, 0, 0, 0, + 2, 2, 2, 2, + 3, 0, 0, 0, + 0, 8, 8, 0, + 0, 0, 0, 0, + 5, 5, 5, 5, + 6, 0, 0, 0, + 0, 11, 11, 0 ] - Name: ExpectedOut2 Format: Int64 Stride: 32 - Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 3, 2, 3, + 2, 3, 2, 3, + 3, 4, 0, 0, + 0, 0, 0, 0, + 0, 0, 8, 9, + 8, 9, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5, 4, 5, 4, + 5, 4, 5, 4, + 6, 5, 0, 0, + 0, 0, 0, 0, + 0, 0, 11, 10, + 11, 10, 0, 0 ] - Name: ExpectedOut3 Format: Int64 Stride: 32 - Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + # 2 value sets, 4 masks per value set, 4 threads per mask, 4 result values per thread + # Note, vecs of 3 must be aligned, so the 3 result values are placed into a 4 element vec + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 3, 4, 0, + 2, 3, 4, 0, + 2, 3, 4, 0, + 2, 3, 4, 0, + 3, 4, 5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 8, 9, 10, 0, + 8, 9, 10, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5, 4, 3, 0, + 5, 4, 3, 0, + 5, 4, 3, 0, + 5, 4, 3, 0, + 6, 5, 4, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 11, 10, 9, 0, + 11, 10, 9, 0, + 0, 0, 0, 0 ] - Name: ExpectedOut4 Format: Int64 Stride: 32 - Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + Data: [ 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 3, 4, 5, + 2, 3, 4, 5, + 2, 3, 4, 5, + 2, 3, 4, 5, + 3, 4, 5, 6, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 8, 9, 10, 11, + 8, 9, 10, 11, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 5, 4, 3, 2, + 5, 4, 3, 2, + 5, 4, 3, 2, + 5, 4, 3, 2, + 6, 5, 4, 3, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 11, 10, 9, 8, + 11, 10, 9, 8, + 0, 0, 0, 0 ] - Name: ExpectedOut5 Format: Int64 - Stride: 32 - Data: [ 1, 2, 3, 4 ] - - Name: UIn - Format: UInt64 - Stride: 32 - Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] - - Name: UOut1 - Format: UInt64 - Stride: 32 - ZeroInitSize: 128 - - Name: UOut2 - Format: UInt64 - Stride: 32 - ZeroInitSize: 128 - - Name: UOut3 - Format: UInt64 - Stride: 32 - ZeroInitSize: 128 - - Name: UOut4 - Format: UInt64 - Stride: 32 - ZeroInitSize: 128 - - Name: UOut5 - Format: UInt64 - Stride: 32 - ZeroInitSize: 32 - - Name: UExpectedOut1 - Format: UInt64 - Stride: 32 - Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] - - Name: UExpectedOut2 - Format: UInt64 - Stride: 32 - Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] - - Name: UExpectedOut3 - Format: UInt64 - Stride: 32 - Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] - - Name: UExpectedOut4 - Format: UInt64 - Stride: 32 - Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] - - Name: UExpectedOut5 - Format: UInt64 - Stride: 32 + Stride: 16 Data: [ 1, 2, 3, 4 ] Results: - Result: ExpectedOut1 @@ -209,26 +249,6 @@ Results: Rule: BufferExact Actual: Out5 Expected: ExpectedOut5 - - Result: UExpectedOut1 - Rule: BufferExact - Actual: UOut1 - Expected: UExpectedOut1 - - Result: UExpectedOut2 - Rule: BufferExact - Actual: UOut2 - Expected: UExpectedOut2 - - Result: UExpectedOut3 - Rule: BufferExact - Actual: UOut3 - Expected: UExpectedOut3 - - Result: UExpectedOut4 - Rule: BufferExact - Actual: UOut4 - Expected: UExpectedOut4 - - Result: UExpectedOut5 - Rule: BufferExact - Actual: UOut5 - Expected: UExpectedOut5 DescriptorSets: - Resources: - Name: In @@ -273,63 +293,24 @@ DescriptorSets: Space: 0 VulkanBinding: Binding: 5 - - Name: UIn + - Name: Masks Kind: StructuredBuffer DirectXBinding: Register: 6 Space: 0 VulkanBinding: Binding: 6 - - Name: UOut1 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 7 - Space: 0 - VulkanBinding: - Binding: 7 - - Name: UOut2 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 8 - Space: 0 - VulkanBinding: - Binding: 8 - - Name: UOut3 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 9 - Space: 0 - VulkanBinding: - Binding: 9 - - Name: UOut4 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 10 - Space: 0 - VulkanBinding: - Binding: 10 - - Name: UOut5 - Kind: RWStructuredBuffer - DirectXBinding: - Register: 11 - Space: 0 - VulkanBinding: - Binding: 11 ... #--- end # REQUIRES: Int64 -# Bug https://github.com/llvm/offload-test-suite/issues/393 -# XFAIL: Metal - # Bug https://github.com/llvm/llvm-project/issues/156775 # XFAIL: Clang -# Bug https://github.com/llvm/offload-test-suite/issues/433 -# XFAIL: DirectX-WARP - +# Bug https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl From fef4787737c8c9af11bd520ac8893c23e42275c3 Mon Sep 17 00:00:00 2001 From: Joshua Batista Date: Mon, 27 Oct 2025 16:27:04 -0700 Subject: [PATCH 06/10] add warp xfail bug --- test/WaveOps/WaveReadLaneFirst.fp16.test | 3 +++ test/WaveOps/WaveReadLaneFirst.fp64.test | 3 +++ test/WaveOps/WaveReadLaneFirst.int64.test | 3 +++ 3 files changed, 9 insertions(+) diff --git a/test/WaveOps/WaveReadLaneFirst.fp16.test b/test/WaveOps/WaveReadLaneFirst.fp16.test index 95f88382a..f098e8065 100644 --- a/test/WaveOps/WaveReadLaneFirst.fp16.test +++ b/test/WaveOps/WaveReadLaneFirst.fp16.test @@ -310,6 +310,9 @@ DescriptorSets: # Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal +# XFAIL: WARP +# Bug https://github.com/llvm/offload-test-suite/issues/433 + # RUN: split-file %s %t # RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.fp64.test b/test/WaveOps/WaveReadLaneFirst.fp64.test index f2053fb0d..f9bfdc39f 100644 --- a/test/WaveOps/WaveReadLaneFirst.fp64.test +++ b/test/WaveOps/WaveReadLaneFirst.fp64.test @@ -310,6 +310,9 @@ DescriptorSets: # Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal +# XFAIL: WARP +# Bug https://github.com/llvm/offload-test-suite/issues/433 + # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveReadLaneFirst.int64.test b/test/WaveOps/WaveReadLaneFirst.int64.test index 58d4d55c3..f8afaf05a 100644 --- a/test/WaveOps/WaveReadLaneFirst.int64.test +++ b/test/WaveOps/WaveReadLaneFirst.int64.test @@ -312,6 +312,9 @@ DescriptorSets: # Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal +# XFAIL: WARP +# Bug https://github.com/llvm/offload-test-suite/issues/433 + # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o From c30eb8a4729ad98f1c9360364d8cfaf7e95b0707 Mon Sep 17 00:00:00 2001 From: Joshua Batista Date: Wed, 5 Nov 2025 10:57:58 -0800 Subject: [PATCH 07/10] add Intel XFAIL --- .../WaveOps/WaveReadLaneFirst.128Threads.test | 149 ++++++++++++++++++ 1 file changed, 149 insertions(+) create mode 100644 test/WaveOps/WaveReadLaneFirst.128Threads.test diff --git a/test/WaveOps/WaveReadLaneFirst.128Threads.test b/test/WaveOps/WaveReadLaneFirst.128Threads.test new file mode 100644 index 000000000..aa5639985 --- /dev/null +++ b/test/WaveOps/WaveReadLaneFirst.128Threads.test @@ -0,0 +1,149 @@ +#--- source.hlsl +#define NUM_MASKS 1 +#define NUM_THREADS 128 + +struct MaskStruct { + int mask[NUM_THREADS]; +}; + +StructuredBuffer In : register(t0); +RWStructuredBuffer Out4 : register(u4); // test int4 +RWStructuredBuffer Out5 : register(u5); // constant folding +StructuredBuffer Masks : register(t6); + + +[numthreads(NUM_THREADS,1,1)] +void main(uint3 tid : SV_GroupThreadID) +{ + + for (uint MaskIdx = 0; MaskIdx < NUM_MASKS; MaskIdx++) { + int4 v = In[MaskIdx * NUM_THREADS + tid.x]; + const uint OutIdx = MaskIdx * NUM_THREADS + tid.x; + if (Masks[MaskIdx].mask[tid.x]) { + Out4[OutIdx] = WaveReadLaneFirst( v ); + } + } + + // constant folding case + Out5[0] = WaveReadLaneFirst(int4(1,2,3,4)); +} + + +//--- pipeline.yaml + +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [1, 1, 1] +Buffers: + - Name: In + Format: Int32 + Stride: 16 + # 1 value set, 1 mask, 128 threads, each thread supplies int4(tid, tid+1, tid+2, tid+3) + Data: [ + 0,1,2,3, 1,2,3,4, 2,3,4,5, 3,4,5,6, 4,5,6,7, 5,6,7,8, 6,7,8,9, 7,8,9,10, + 8,9,10,11, 9,10,11,12, 10,11,12,13, 11,12,13,14, 12,13,14,15, 13,14,15,16, + 14,15,16,17, 15,16,17,18, 16,17,18,19, 17,18,19,20, 18,19,20,21, 19,20,21,22, + 20,21,22,23, 21,22,23,24, 22,23,24,25, 23,24,25,26, 24,25,26,27, 25,26,27,28, + 26,27,28,29, 27,28,29,30, 28,29,30,31, 29,30,31,32, 30,31,32,33, 31,32,33,34, + 32,33,34,35, 33,34,35,36, 34,35,36,37, 35,36,37,38, 36,37,38,39, 37,38,39,40, + 38,39,40,41, 39,40,41,42, 40,41,42,43, 41,42,43,44, 42,43,44,45, 43,44,45,46, + 44,45,46,47, 45,46,47,48, 46,47,48,49, 47,48,49,50, 48,49,50,51, 49,50,51,52, + 50,51,52,53, 51,52,53,54, 52,53,54,55, 53,54,55,56, 54,55,56,57, 55,56,57,58, + 56,57,58,59, 57,58,59,60, 58,59,60,61, 59,60,61,62, 60,61,62,63, 61,62,63,64, + 62,63,64,65, 63,64,65,66, 64,65,66,67, 65,66,67,68, 66,67,68,69, 67,68,69,70, + 68,69,70,71, 69,70,71,72, 70,71,72,73, 71,72,73,74, 72,73,74,75, 73,74,75,76, + 74,75,76,77, 75,76,77,78, 76,77,78,79, 77,78,79,80, 78,79,80,81, 79,80,81,82, + 80,81,82,83, 81,82,83,84, 82,83,84,85, 83,84,85,86, 84,85,86,87, 85,86,87,88, + 86,87,88,89, 87,88,89,90, 88,89,90,91, 89,90,91,92, 90,91,92,93, 91,92,93,94, + 92,93,94,95, 93,94,95,96, 94,95,96,97, 95,96,97,98, 96,97,98,99, 97,98,99,100, + 98,99,100,101, 99,100,101,102, 100,101,102,103, 101,102,103,104, 102,103,104,105, + 103,104,105,106, 104,105,106,107, 105,106,107,108, 106,107,108,109, 107,108,109,110, + 108,109,110,111, 109,110,111,112, 110,111,112,113, 111,112,113,114, 112,113,114,115, + 113,114,115,116, 114,115,116,117, 115,116,117,118, 116,117,118,119, 117,118,119,120, + 118,119,120,121, 119,120,121,122, 120,121,122,123, 121,122,123,124, 122,123,124,125, + 123,124,125,126, 124,125,126,127, 125,126,127,128, 126,127,128,129, 127,128,129,130 + ] + + - Name: Out4 + Format: Int32 + Stride: 16 + FillSize: 2048 + - Name: Out5 + Format: Int32 + Stride: 16 + FillSize: 16 + - Name: Masks + Format: Int32 + Stride: 16 + Data: [ + 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, + 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, + 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, + 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0 ] + + - Name: ExpectedOut4 + Format: Int32 + Stride: 16 + Data: [ 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, + 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, + 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, + 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0 + ] + - Name: ExpectedOut5 + Format: Int32 + Stride: 8 + Data: [ 1, 2, 3, 4 ] +Results: + - Result: ExpectedOut4 + Rule: BufferExact + Actual: Out4 + Expected: ExpectedOut4 + - Result: ExpectedOut5 + Rule: BufferExact + Actual: Out5 + Expected: ExpectedOut5 +DescriptorSets: + - Resources: + - Name: In + Kind: StructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: Out4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 4 + Space: 0 + VulkanBinding: + Binding: 4 + - Name: Out5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 5 + Space: 0 + VulkanBinding: + Binding: 5 + - Name: Masks + Kind: StructuredBuffer + DirectXBinding: + Register: 6 + Space: 0 + VulkanBinding: + Binding: 6 + +... +#--- end + +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang + +# Bug https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal + +# RUN: split-file %s %t +# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o From 28fb5ea34ef618d96eca43e694d189e2340c38db Mon Sep 17 00:00:00 2001 From: Joshua Batista Date: Thu, 4 Dec 2025 13:01:55 -0800 Subject: [PATCH 08/10] add 128 thread test --- .../WaveOps/WaveReadLaneFirst.128Threads.test | 137 +++++++++++++++++- 1 file changed, 130 insertions(+), 7 deletions(-) diff --git a/test/WaveOps/WaveReadLaneFirst.128Threads.test b/test/WaveOps/WaveReadLaneFirst.128Threads.test index aa5639985..42c526f26 100644 --- a/test/WaveOps/WaveReadLaneFirst.128Threads.test +++ b/test/WaveOps/WaveReadLaneFirst.128Threads.test @@ -11,7 +11,7 @@ RWStructuredBuffer Out4 : register(u4); // test int4 RWStructuredBuffer Out5 : register(u5); // constant folding StructuredBuffer Masks : register(t6); - +[WaveSize(32)] [numthreads(NUM_THREADS,1,1)] void main(uint3 tid : SV_GroupThreadID) { @@ -86,11 +86,134 @@ Buffers: - Name: ExpectedOut4 Format: Int32 Stride: 16 - Data: [ 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, - 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, - 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, - 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0 - ] + Data: [ 0, 0, 0, 0, + 1, 2, 3, 4, + 1, 2, 3, 4, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 2, 3, 4, + 1, 2, 3, 4, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 2, 3, 4, + 1, 2, 3, 4, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 2, 3, 4, + 1, 2, 3, 4, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 2, 3, 4, + 1, 2, 3, 4, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 2, 3, 4, + 1, 2, 3, 4, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 2, 3, 4, + 1, 2, 3, 4, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 2, 3, 4, + 1, 2, 3, 4, + 0, 0, 0, 0, + 0, 0, 0, 0, + 33, 34, 35, 36, + 33, 34, 35, 36, + 0, 0, 0, 0, + 0, 0, 0, 0, + 33, 34, 35, 36, + 33, 34, 35, 36, + 0, 0, 0, 0, + 0, 0, 0, 0, + 33, 34, 35, 36, + 33, 34, 35, 36, + 0, 0, 0, 0, + 0, 0, 0, 0, + 33, 34, 35, 36, + 33, 34, 35, 36, + 0, 0, 0, 0, + 0, 0, 0, 0, + 33, 34, 35, 36, + 33, 34, 35, 36, + 0, 0, 0, 0, + 0, 0, 0, 0, + 33, 34, 35, 36, + 33, 34, 35, 36, + 0, 0, 0, 0, + 0, 0, 0, 0, + 33, 34, 35, 36, + 33, 34, 35, 36, + 0, 0, 0, 0, + 0, 0, 0, 0, + 33, 34, 35, 36, + 33, 34, 35, 36, + 0, 0, 0, 0, + 0, 0, 0, 0, + 65, 66, 67, 68, + 65, 66, 67, 68, + 0, 0, 0, 0, + 0, 0, 0, 0, + 65, 66, 67, 68, + 65, 66, 67, 68, + 0, 0, 0, 0, + 0, 0, 0, 0, + 65, 66, 67, 68, + 65, 66, 67, 68, + 0, 0, 0, 0, + 0, 0, 0, 0, + 65, 66, 67, 68, + 65, 66, 67, 68, + 0, 0, 0, 0, + 0, 0, 0, 0, + 65, 66, 67, 68, + 65, 66, 67, 68, + 0, 0, 0, 0, + 0, 0, 0, 0, + 65, 66, 67, 68, + 65, 66, 67, 68, + 0, 0, 0, 0, + 0, 0, 0, 0, + 65, 66, 67, 68, + 65, 66, 67, 68, + 0, 0, 0, 0, + 0, 0, 0, 0, + 65, 66, 67, 68, + 65, 66, 67, 68, + 0, 0, 0, 0, + 0, 0, 0, 0, + 97, 98, 99, 100, + 97, 98, 99, 100, + 0, 0, 0, 0, + 0, 0, 0, 0, + 97, 98, 99, 100, + 97, 98, 99, 100, + 0, 0, 0, 0, + 0, 0, 0, 0, + 97, 98, 99, 100, + 97, 98, 99, 100, + 0, 0, 0, 0, + 0, 0, 0, 0, + 97, 98, 99, 100, + 97, 98, 99, 100, + 0, 0, 0, 0, + 0, 0, 0, 0, + 97, 98, 99, 100, + 97, 98, 99, 100, + 0, 0, 0, 0, + 0, 0, 0, 0, + 97, 98, 99, 100, + 97, 98, 99, 100, + 0, 0, 0, 0, + 0, 0, 0, 0, + 97, 98, 99, 100, + 97, 98, 99, 100, + 0, 0, 0, 0, + 0, 0, 0, 0, + 97, 98, 99, 100, + 97, 98, 99, 100, + 0, 0, 0, 0 ] - Name: ExpectedOut5 Format: Int32 Stride: 8 @@ -145,5 +268,5 @@ DescriptorSets: # XFAIL: Metal # RUN: split-file %s %t -# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o From ee23a1d0aa3dd5777853484ea113d81c44815384 Mon Sep 17 00:00:00 2001 From: Joshua Batista Date: Mon, 8 Dec 2025 13:22:59 -0800 Subject: [PATCH 09/10] xfail vulkan, infra problems --- .../WaveOps/WaveReadLaneFirst.128Threads.test | 69 ++++++++++--------- 1 file changed, 36 insertions(+), 33 deletions(-) diff --git a/test/WaveOps/WaveReadLaneFirst.128Threads.test b/test/WaveOps/WaveReadLaneFirst.128Threads.test index 42c526f26..85b8d7f73 100644 --- a/test/WaveOps/WaveReadLaneFirst.128Threads.test +++ b/test/WaveOps/WaveReadLaneFirst.128Threads.test @@ -11,7 +11,7 @@ RWStructuredBuffer Out4 : register(u4); // test int4 RWStructuredBuffer Out5 : register(u5); // constant folding StructuredBuffer Masks : register(t6); -[WaveSize(32)] +[WaveSize(16)] [numthreads(NUM_THREADS,1,1)] void main(uint3 tid : SV_GroupThreadID) { @@ -103,20 +103,20 @@ Buffers: 1, 2, 3, 4, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 2, 3, 4, - 1, 2, 3, 4, + 17, 18, 19, 20, + 17, 18, 19, 20, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 2, 3, 4, - 1, 2, 3, 4, + 17, 18, 19, 20, + 17, 18, 19, 20, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 2, 3, 4, - 1, 2, 3, 4, + 17, 18, 19, 20, + 17, 18, 19, 20, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 2, 3, 4, - 1, 2, 3, 4, + 17, 18, 19, 20, + 17, 18, 19, 20, 0, 0, 0, 0, 0, 0, 0, 0, 33, 34, 35, 36, @@ -135,20 +135,20 @@ Buffers: 33, 34, 35, 36, 0, 0, 0, 0, 0, 0, 0, 0, - 33, 34, 35, 36, - 33, 34, 35, 36, + 49, 50, 51, 52, + 49, 50, 51, 52, 0, 0, 0, 0, 0, 0, 0, 0, - 33, 34, 35, 36, - 33, 34, 35, 36, + 49, 50, 51, 52, + 49, 50, 51, 52, 0, 0, 0, 0, 0, 0, 0, 0, - 33, 34, 35, 36, - 33, 34, 35, 36, + 49, 50, 51, 52, + 49, 50, 51, 52, 0, 0, 0, 0, 0, 0, 0, 0, - 33, 34, 35, 36, - 33, 34, 35, 36, + 49, 50, 51, 52, + 49, 50, 51, 52, 0, 0, 0, 0, 0, 0, 0, 0, 65, 66, 67, 68, @@ -167,20 +167,20 @@ Buffers: 65, 66, 67, 68, 0, 0, 0, 0, 0, 0, 0, 0, - 65, 66, 67, 68, - 65, 66, 67, 68, + 81, 82, 83, 84, + 81, 82, 83, 84, 0, 0, 0, 0, 0, 0, 0, 0, - 65, 66, 67, 68, - 65, 66, 67, 68, + 81, 82, 83, 84, + 81, 82, 83, 84, 0, 0, 0, 0, 0, 0, 0, 0, - 65, 66, 67, 68, - 65, 66, 67, 68, + 81, 82, 83, 84, + 81, 82, 83, 84, 0, 0, 0, 0, 0, 0, 0, 0, - 65, 66, 67, 68, - 65, 66, 67, 68, + 81, 82, 83, 84, + 81, 82, 83, 84, 0, 0, 0, 0, 0, 0, 0, 0, 97, 98, 99, 100, @@ -199,20 +199,20 @@ Buffers: 97, 98, 99, 100, 0, 0, 0, 0, 0, 0, 0, 0, - 97, 98, 99, 100, - 97, 98, 99, 100, + 113, 114, 115, 116, + 113, 114, 115, 116, 0, 0, 0, 0, 0, 0, 0, 0, - 97, 98, 99, 100, - 97, 98, 99, 100, + 113, 114, 115, 116, + 113, 114, 115, 116, 0, 0, 0, 0, 0, 0, 0, 0, - 97, 98, 99, 100, - 97, 98, 99, 100, + 113, 114, 115, 116, + 113, 114, 115, 116, 0, 0, 0, 0, 0, 0, 0, 0, - 97, 98, 99, 100, - 97, 98, 99, 100, + 113, 114, 115, 116, + 113, 114, 115, 116, 0, 0, 0, 0 ] - Name: ExpectedOut5 Format: Int32 @@ -267,6 +267,9 @@ DescriptorSets: # Bug https://github.com/llvm/offload-test-suite/issues/393 # XFAIL: Metal +# Bug https://github.com/llvm/offload-test-suite/issues/611 +# XFAIL: Vulkan + # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl # RUN: %offloader %t/pipeline.yaml %t.o From f4074f517e83fa0316f314f3d278f0381309a10f Mon Sep 17 00:00:00 2001 From: Joshua Batista Date: Mon, 8 Dec 2025 15:24:21 -0800 Subject: [PATCH 10/10] add unsupported instaed of xfail --- .../WaveOps/WaveReadLaneFirst.128Threads.test | 68 +++++++++---------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/test/WaveOps/WaveReadLaneFirst.128Threads.test b/test/WaveOps/WaveReadLaneFirst.128Threads.test index 85b8d7f73..e92d32e40 100644 --- a/test/WaveOps/WaveReadLaneFirst.128Threads.test +++ b/test/WaveOps/WaveReadLaneFirst.128Threads.test @@ -11,7 +11,7 @@ RWStructuredBuffer Out4 : register(u4); // test int4 RWStructuredBuffer Out5 : register(u5); // constant folding StructuredBuffer Masks : register(t6); -[WaveSize(16)] +[WaveSize(32)] [numthreads(NUM_THREADS,1,1)] void main(uint3 tid : SV_GroupThreadID) { @@ -103,20 +103,20 @@ Buffers: 1, 2, 3, 4, 0, 0, 0, 0, 0, 0, 0, 0, - 17, 18, 19, 20, - 17, 18, 19, 20, + 1, 2, 3, 4, + 1, 2, 3, 4, 0, 0, 0, 0, 0, 0, 0, 0, - 17, 18, 19, 20, - 17, 18, 19, 20, + 1, 2, 3, 4, + 1, 2, 3, 4, 0, 0, 0, 0, 0, 0, 0, 0, - 17, 18, 19, 20, - 17, 18, 19, 20, + 1, 2, 3, 4, + 1, 2, 3, 4, 0, 0, 0, 0, 0, 0, 0, 0, - 17, 18, 19, 20, - 17, 18, 19, 20, + 1, 2, 3, 4, + 1, 2, 3, 4, 0, 0, 0, 0, 0, 0, 0, 0, 33, 34, 35, 36, @@ -135,20 +135,20 @@ Buffers: 33, 34, 35, 36, 0, 0, 0, 0, 0, 0, 0, 0, - 49, 50, 51, 52, - 49, 50, 51, 52, + 33, 34, 35, 36, + 33, 34, 35, 36, 0, 0, 0, 0, 0, 0, 0, 0, - 49, 50, 51, 52, - 49, 50, 51, 52, + 33, 34, 35, 36, + 33, 34, 35, 36, 0, 0, 0, 0, 0, 0, 0, 0, - 49, 50, 51, 52, - 49, 50, 51, 52, + 33, 34, 35, 36, + 33, 34, 35, 36, 0, 0, 0, 0, 0, 0, 0, 0, - 49, 50, 51, 52, - 49, 50, 51, 52, + 33, 34, 35, 36, + 33, 34, 35, 36, 0, 0, 0, 0, 0, 0, 0, 0, 65, 66, 67, 68, @@ -167,20 +167,20 @@ Buffers: 65, 66, 67, 68, 0, 0, 0, 0, 0, 0, 0, 0, - 81, 82, 83, 84, - 81, 82, 83, 84, + 65, 66, 67, 68, + 65, 66, 67, 68, 0, 0, 0, 0, 0, 0, 0, 0, - 81, 82, 83, 84, - 81, 82, 83, 84, + 65, 66, 67, 68, + 65, 66, 67, 68, 0, 0, 0, 0, 0, 0, 0, 0, - 81, 82, 83, 84, - 81, 82, 83, 84, + 65, 66, 67, 68, + 65, 66, 67, 68, 0, 0, 0, 0, 0, 0, 0, 0, - 81, 82, 83, 84, - 81, 82, 83, 84, + 65, 66, 67, 68, + 65, 66, 67, 68, 0, 0, 0, 0, 0, 0, 0, 0, 97, 98, 99, 100, @@ -199,20 +199,20 @@ Buffers: 97, 98, 99, 100, 0, 0, 0, 0, 0, 0, 0, 0, - 113, 114, 115, 116, - 113, 114, 115, 116, + 97, 98, 99, 100, + 97, 98, 99, 100, 0, 0, 0, 0, 0, 0, 0, 0, - 113, 114, 115, 116, - 113, 114, 115, 116, + 97, 98, 99, 100, + 97, 98, 99, 100, 0, 0, 0, 0, 0, 0, 0, 0, - 113, 114, 115, 116, - 113, 114, 115, 116, + 97, 98, 99, 100, + 97, 98, 99, 100, 0, 0, 0, 0, 0, 0, 0, 0, - 113, 114, 115, 116, - 113, 114, 115, 116, + 97, 98, 99, 100, + 97, 98, 99, 100, 0, 0, 0, 0 ] - Name: ExpectedOut5 Format: Int32 @@ -268,7 +268,7 @@ DescriptorSets: # XFAIL: Metal # Bug https://github.com/llvm/offload-test-suite/issues/611 -# XFAIL: Vulkan +# UNSUPPORTED: Vulkan # RUN: split-file %s %t # RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl