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add Intel XFAIL
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‎test/WaveOps/WaveReadLaneFirst.128Threads.test‎

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#--- source.hlsl
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#define NUM_MASKS 1
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#define NUM_THREADS 128
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struct MaskStruct {
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int mask[NUM_THREADS];
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};
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StructuredBuffer<int4> In : register(t0);
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RWStructuredBuffer<int4> Out4 : register(u4); // test int4
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RWStructuredBuffer<int4> Out5 : register(u5); // constant folding
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StructuredBuffer<MaskStruct> Masks : register(t6);
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[numthreads(NUM_THREADS,1,1)]
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void main(uint3 tid : SV_GroupThreadID)
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{
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for (uint MaskIdx = 0; MaskIdx < NUM_MASKS; MaskIdx++) {
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int4 v = In[MaskIdx * NUM_THREADS + tid.x];
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const uint OutIdx = MaskIdx * NUM_THREADS + tid.x;
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if (Masks[MaskIdx].mask[tid.x]) {
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Out4[OutIdx] = WaveReadLaneFirst( v );
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}
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}
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// constant folding case
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Out5[0] = WaveReadLaneFirst(int4(1,2,3,4));
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1, 1, 1]
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Buffers:
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- Name: In
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Format: Int32
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Stride: 16
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# 1 value set, 1 mask, 128 threads, each thread supplies int4(tid, tid+1, tid+2, tid+3)
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Data: [
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0,1,2,3, 1,2,3,4, 2,3,4,5, 3,4,5,6, 4,5,6,7, 5,6,7,8, 6,7,8,9, 7,8,9,10,
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8,9,10,11, 9,10,11,12, 10,11,12,13, 11,12,13,14, 12,13,14,15, 13,14,15,16,
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14,15,16,17, 15,16,17,18, 16,17,18,19, 17,18,19,20, 18,19,20,21, 19,20,21,22,
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20,21,22,23, 21,22,23,24, 22,23,24,25, 23,24,25,26, 24,25,26,27, 25,26,27,28,
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26,27,28,29, 27,28,29,30, 28,29,30,31, 29,30,31,32, 30,31,32,33, 31,32,33,34,
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32,33,34,35, 33,34,35,36, 34,35,36,37, 35,36,37,38, 36,37,38,39, 37,38,39,40,
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38,39,40,41, 39,40,41,42, 40,41,42,43, 41,42,43,44, 42,43,44,45, 43,44,45,46,
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44,45,46,47, 45,46,47,48, 46,47,48,49, 47,48,49,50, 48,49,50,51, 49,50,51,52,
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50,51,52,53, 51,52,53,54, 52,53,54,55, 53,54,55,56, 54,55,56,57, 55,56,57,58,
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56,57,58,59, 57,58,59,60, 58,59,60,61, 59,60,61,62, 60,61,62,63, 61,62,63,64,
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62,63,64,65, 63,64,65,66, 64,65,66,67, 65,66,67,68, 66,67,68,69, 67,68,69,70,
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68,69,70,71, 69,70,71,72, 70,71,72,73, 71,72,73,74, 72,73,74,75, 73,74,75,76,
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74,75,76,77, 75,76,77,78, 76,77,78,79, 77,78,79,80, 78,79,80,81, 79,80,81,82,
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80,81,82,83, 81,82,83,84, 82,83,84,85, 83,84,85,86, 84,85,86,87, 85,86,87,88,
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86,87,88,89, 87,88,89,90, 88,89,90,91, 89,90,91,92, 90,91,92,93, 91,92,93,94,
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92,93,94,95, 93,94,95,96, 94,95,96,97, 95,96,97,98, 96,97,98,99, 97,98,99,100,
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98,99,100,101, 99,100,101,102, 100,101,102,103, 101,102,103,104, 102,103,104,105,
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103,104,105,106, 104,105,106,107, 105,106,107,108, 106,107,108,109, 107,108,109,110,
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108,109,110,111, 109,110,111,112, 110,111,112,113, 111,112,113,114, 112,113,114,115,
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113,114,115,116, 114,115,116,117, 115,116,117,118, 116,117,118,119, 117,118,119,120,
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118,119,120,121, 119,120,121,122, 120,121,122,123, 121,122,123,124, 122,123,124,125,
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123,124,125,126, 124,125,126,127, 125,126,127,128, 126,127,128,129, 127,128,129,130
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]
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- Name: Out4
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Format: Int32
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Stride: 16
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FillSize: 2048
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- Name: Out5
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Format: Int32
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Stride: 16
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FillSize: 16
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- Name: Masks
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Format: Int32
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Stride: 16
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Data: [
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0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0,
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0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0,
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0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0,
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0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0 ]
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- Name: ExpectedOut4
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Format: Int32
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Stride: 16
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Data: [ 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0,
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0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0,
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0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0,
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0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0, 0,0,0,0, 1,2,3,4, 1,2,3,4, 0,0,0,0
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]
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- Name: ExpectedOut5
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Format: Int32
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Stride: 8
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Data: [ 1, 2, 3, 4 ]
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Results:
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- Result: ExpectedOut4
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Rule: BufferExact
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Actual: Out4
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Expected: ExpectedOut4
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- Result: ExpectedOut5
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Rule: BufferExact
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Actual: Out5
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Expected: ExpectedOut5
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DescriptorSets:
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- Resources:
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- Name: In
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 0
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Space: 0
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VulkanBinding:
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Binding: 0
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- Name: Out4
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 4
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Space: 0
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VulkanBinding:
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Binding: 4
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- Name: Out5
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 5
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Space: 0
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VulkanBinding:
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Binding: 5
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- Name: Masks
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 6
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Space: 0
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VulkanBinding:
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Binding: 6
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...
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#--- end
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# Bug https://github.com/llvm/llvm-project/issues/156775
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# XFAIL: Clang
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# Bug https://github.com/llvm/offload-test-suite/issues/393
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# XFAIL: Metal
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# RUN: split-file %s %t
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# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o

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