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topperctru
topperc
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[RISCV] Correct copyPhysReg for GPRPF64. (#70419)
GPRF64 represents a pair of registers. We were only copying the even part. We need to copy the odd part too.
1 parent 615beae commit 8c8abe6

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3 files changed

+34
-5
lines changed

3 files changed

+34
-5
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -299,18 +299,27 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
299299
MCRegister SrcReg, bool KillSrc) const {
300300
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
301301

302-
if (RISCV::GPRPF64RegClass.contains(DstReg))
303-
DstReg = TRI->getSubReg(DstReg, RISCV::sub_32);
304-
if (RISCV::GPRPF64RegClass.contains(SrcReg))
305-
SrcReg = TRI->getSubReg(SrcReg, RISCV::sub_32);
306-
307302
if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
308303
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
309304
.addReg(SrcReg, getKillRegState(KillSrc))
310305
.addImm(0);
311306
return;
312307
}
313308

309+
if (RISCV::GPRPF64RegClass.contains(DstReg, SrcReg)) {
310+
// Emit an ADDI for both parts of GPRPF64.
311+
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI),
312+
TRI->getSubReg(DstReg, RISCV::sub_32))
313+
.addReg(TRI->getSubReg(SrcReg, RISCV::sub_32), getKillRegState(KillSrc))
314+
.addImm(0);
315+
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI),
316+
TRI->getSubReg(DstReg, RISCV::sub_32_hi))
317+
.addReg(TRI->getSubReg(SrcReg, RISCV::sub_32_hi),
318+
getKillRegState(KillSrc))
319+
.addImm(0);
320+
return;
321+
}
322+
314323
// Handle copy from csr
315324
if (RISCV::VCSRRegClass.contains(SrcReg) &&
316325
RISCV::GPRRegClass.contains(DstReg)) {

‎llvm/test/CodeGen/RISCV/double-maximum-minimum.ll‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,14 +47,17 @@ define double @fminimum_f64(double %a, double %b) nounwind {
4747
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
4848
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
4949
; RV32IZFINXZDINX-NEXT: mv a4, a2
50+
; RV32IZFINXZDINX-NEXT: mv a5, a3
5051
; RV32IZFINXZDINX-NEXT: bnez a6, .LBB0_2
5152
; RV32IZFINXZDINX-NEXT: # %bb.1:
5253
; RV32IZFINXZDINX-NEXT: mv a4, a0
54+
; RV32IZFINXZDINX-NEXT: mv a5, a1
5355
; RV32IZFINXZDINX-NEXT: .LBB0_2:
5456
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
5557
; RV32IZFINXZDINX-NEXT: bnez a6, .LBB0_4
5658
; RV32IZFINXZDINX-NEXT: # %bb.3:
5759
; RV32IZFINXZDINX-NEXT: mv a0, a2
60+
; RV32IZFINXZDINX-NEXT: mv a1, a3
5861
; RV32IZFINXZDINX-NEXT: .LBB0_4:
5962
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
6063
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
@@ -121,14 +124,17 @@ define double @fmaximum_f64(double %a, double %b) nounwind {
121124
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
122125
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
123126
; RV32IZFINXZDINX-NEXT: mv a4, a2
127+
; RV32IZFINXZDINX-NEXT: mv a5, a3
124128
; RV32IZFINXZDINX-NEXT: bnez a6, .LBB1_2
125129
; RV32IZFINXZDINX-NEXT: # %bb.1:
126130
; RV32IZFINXZDINX-NEXT: mv a4, a0
131+
; RV32IZFINXZDINX-NEXT: mv a5, a1
127132
; RV32IZFINXZDINX-NEXT: .LBB1_2:
128133
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
129134
; RV32IZFINXZDINX-NEXT: bnez a6, .LBB1_4
130135
; RV32IZFINXZDINX-NEXT: # %bb.3:
131136
; RV32IZFINXZDINX-NEXT: mv a0, a2
137+
; RV32IZFINXZDINX-NEXT: mv a1, a3
132138
; RV32IZFINXZDINX-NEXT: .LBB1_4:
133139
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
134140
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)

‎llvm/test/CodeGen/RISCV/double-select-fcmp.ll‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,7 @@ define double @select_fcmp_oeq(double %a, double %b) nounwind {
5454
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB1_2
5555
; CHECKRV32ZDINX-NEXT: # %bb.1:
5656
; CHECKRV32ZDINX-NEXT: mv a0, a2
57+
; CHECKRV32ZDINX-NEXT: mv a1, a3
5758
; CHECKRV32ZDINX-NEXT: .LBB1_2:
5859
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
5960
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
@@ -100,6 +101,7 @@ define double @select_fcmp_ogt(double %a, double %b) nounwind {
100101
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB2_2
101102
; CHECKRV32ZDINX-NEXT: # %bb.1:
102103
; CHECKRV32ZDINX-NEXT: mv a0, a2
104+
; CHECKRV32ZDINX-NEXT: mv a1, a3
103105
; CHECKRV32ZDINX-NEXT: .LBB2_2:
104106
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
105107
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
@@ -146,6 +148,7 @@ define double @select_fcmp_oge(double %a, double %b) nounwind {
146148
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB3_2
147149
; CHECKRV32ZDINX-NEXT: # %bb.1:
148150
; CHECKRV32ZDINX-NEXT: mv a0, a2
151+
; CHECKRV32ZDINX-NEXT: mv a1, a3
149152
; CHECKRV32ZDINX-NEXT: .LBB3_2:
150153
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
151154
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
@@ -192,6 +195,7 @@ define double @select_fcmp_olt(double %a, double %b) nounwind {
192195
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB4_2
193196
; CHECKRV32ZDINX-NEXT: # %bb.1:
194197
; CHECKRV32ZDINX-NEXT: mv a0, a2
198+
; CHECKRV32ZDINX-NEXT: mv a1, a3
195199
; CHECKRV32ZDINX-NEXT: .LBB4_2:
196200
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
197201
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
@@ -238,6 +242,7 @@ define double @select_fcmp_ole(double %a, double %b) nounwind {
238242
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB5_2
239243
; CHECKRV32ZDINX-NEXT: # %bb.1:
240244
; CHECKRV32ZDINX-NEXT: mv a0, a2
245+
; CHECKRV32ZDINX-NEXT: mv a1, a3
241246
; CHECKRV32ZDINX-NEXT: .LBB5_2:
242247
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
243248
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
@@ -288,6 +293,7 @@ define double @select_fcmp_one(double %a, double %b) nounwind {
288293
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB6_2
289294
; CHECKRV32ZDINX-NEXT: # %bb.1:
290295
; CHECKRV32ZDINX-NEXT: mv a0, a2
296+
; CHECKRV32ZDINX-NEXT: mv a1, a3
291297
; CHECKRV32ZDINX-NEXT: .LBB6_2:
292298
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
293299
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
@@ -340,6 +346,7 @@ define double @select_fcmp_ord(double %a, double %b) nounwind {
340346
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB7_2
341347
; CHECKRV32ZDINX-NEXT: # %bb.1:
342348
; CHECKRV32ZDINX-NEXT: mv a0, a2
349+
; CHECKRV32ZDINX-NEXT: mv a1, a3
343350
; CHECKRV32ZDINX-NEXT: .LBB7_2:
344351
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
345352
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
@@ -392,6 +399,7 @@ define double @select_fcmp_ueq(double %a, double %b) nounwind {
392399
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB8_2
393400
; CHECKRV32ZDINX-NEXT: # %bb.1:
394401
; CHECKRV32ZDINX-NEXT: mv a0, a2
402+
; CHECKRV32ZDINX-NEXT: mv a1, a3
395403
; CHECKRV32ZDINX-NEXT: .LBB8_2:
396404
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
397405
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
@@ -440,6 +448,7 @@ define double @select_fcmp_ugt(double %a, double %b) nounwind {
440448
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB9_2
441449
; CHECKRV32ZDINX-NEXT: # %bb.1:
442450
; CHECKRV32ZDINX-NEXT: mv a0, a2
451+
; CHECKRV32ZDINX-NEXT: mv a1, a3
443452
; CHECKRV32ZDINX-NEXT: .LBB9_2:
444453
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
445454
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
@@ -486,6 +495,7 @@ define double @select_fcmp_uge(double %a, double %b) nounwind {
486495
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB10_2
487496
; CHECKRV32ZDINX-NEXT: # %bb.1:
488497
; CHECKRV32ZDINX-NEXT: mv a0, a2
498+
; CHECKRV32ZDINX-NEXT: mv a1, a3
489499
; CHECKRV32ZDINX-NEXT: .LBB10_2:
490500
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
491501
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
@@ -532,6 +542,7 @@ define double @select_fcmp_ult(double %a, double %b) nounwind {
532542
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB11_2
533543
; CHECKRV32ZDINX-NEXT: # %bb.1:
534544
; CHECKRV32ZDINX-NEXT: mv a0, a2
545+
; CHECKRV32ZDINX-NEXT: mv a1, a3
535546
; CHECKRV32ZDINX-NEXT: .LBB11_2:
536547
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
537548
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
@@ -578,6 +589,7 @@ define double @select_fcmp_ule(double %a, double %b) nounwind {
578589
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB12_2
579590
; CHECKRV32ZDINX-NEXT: # %bb.1:
580591
; CHECKRV32ZDINX-NEXT: mv a0, a2
592+
; CHECKRV32ZDINX-NEXT: mv a1, a3
581593
; CHECKRV32ZDINX-NEXT: .LBB12_2:
582594
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
583595
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
@@ -624,6 +636,7 @@ define double @select_fcmp_une(double %a, double %b) nounwind {
624636
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB13_2
625637
; CHECKRV32ZDINX-NEXT: # %bb.1:
626638
; CHECKRV32ZDINX-NEXT: mv a0, a2
639+
; CHECKRV32ZDINX-NEXT: mv a1, a3
627640
; CHECKRV32ZDINX-NEXT: .LBB13_2:
628641
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
629642
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
@@ -674,6 +687,7 @@ define double @select_fcmp_uno(double %a, double %b) nounwind {
674687
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB14_2
675688
; CHECKRV32ZDINX-NEXT: # %bb.1:
676689
; CHECKRV32ZDINX-NEXT: mv a0, a2
690+
; CHECKRV32ZDINX-NEXT: mv a1, a3
677691
; CHECKRV32ZDINX-NEXT: .LBB14_2:
678692
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
679693
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)

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