@@ -6924,19 +6924,26 @@ genSubAdd2SubSub(MachineFunction &MF, MachineRegisterInfo &MRI,
69246924 assert ((Opcode == AArch64::SUBWrr || Opcode == AArch64::SUBXrr) &&
69256925 " Unexpected instruction opcode." );
69266926
6927+ uint32_t Flags = Root.mergeFlagsWith (*AddMI);
6928+ Flags &= ~MachineInstr::NoSWrap;
6929+ Flags &= ~MachineInstr::NoUWrap;
6930+
69276931 MachineInstrBuilder MIB1 =
69286932 BuildMI (MF, MIMetadata (Root), TII->get (Opcode), NewVR)
69296933 .addReg (RegA, getKillRegState (RegAIsKill))
6930- .addReg (RegB, getKillRegState (RegBIsKill));
6934+ .addReg (RegB, getKillRegState (RegBIsKill))
6935+ .setMIFlags (Flags);
69316936 MachineInstrBuilder MIB2 =
69326937 BuildMI (MF, MIMetadata (Root), TII->get (Opcode), ResultReg)
69336938 .addReg (NewVR, getKillRegState (true ))
6934- .addReg (RegC, getKillRegState (RegCIsKill));
6939+ .addReg (RegC, getKillRegState (RegCIsKill))
6940+ .setMIFlags (Flags);
69356941
69366942 InstrIdxForVirtReg.insert (std::make_pair (NewVR, 0 ));
69376943 InsInstrs.push_back (MIB1);
69386944 InsInstrs.push_back (MIB2);
69396945 DelInstrs.push_back (AddMI);
6946+ DelInstrs.push_back (&Root);
69406947}
69416948
69426949// / When getMachineCombinerPatterns() finds potential patterns,
@@ -6966,13 +6973,13 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
69666973 // ==> (A - B) - C
69676974 genSubAdd2SubSub (MF, MRI, TII, Root, InsInstrs, DelInstrs, 1 ,
69686975 InstrIdxForVirtReg);
6969- break ;
6976+ return ;
69706977 case AArch64MachineCombinerPattern::SUBADD_OP2:
69716978 // A - (B + C)
69726979 // ==> (A - C) - B
69736980 genSubAdd2SubSub (MF, MRI, TII, Root, InsInstrs, DelInstrs, 2 ,
69746981 InstrIdxForVirtReg);
6975- break ;
6982+ return ;
69766983 case AArch64MachineCombinerPattern::MULADDW_OP1:
69776984 case AArch64MachineCombinerPattern::MULADDX_OP1:
69786985 // MUL I=A,B,0
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