Project plan for CPSWeek submission

[lsk567]

Relocating the TODO list here so that we can modify it without changing the commit history.

Tooling

• Setup interpret repository
• Make Bootloader
  • Could be the same on all FPs and connect to SAME GPIO pin
  • Use ip-contribution UART and wrap it into a WB device.

Precise timing (serial device) benchmark

• Prototype a precision timed serial device for RX/TX
• (optional) Add a UART device (e.g. Martins) to the Top.scala and see that it works
• Evaluate on FPGA

Throughput/latency benchmark

• (Peter) Find out which NoC benchmarks to run
• Make throughput test program
• Evaluate on FPGA

Multithreaded benchmark

• (Erling) Implement HW locks
• (Shaokai) Get HW locks tested and merged
• (Shaokai) Standardize multithreaded execution via a threading library
• (Shaokai) Making the hardware and software consistent (via read-only CSRs?)
• (Chadlia & Shaokai) Figure out what benchmark to run...
• Run in emulation
• Run on FPGA

Area/Resources evaluation

• Synthesize to FPGA

[erlingrj]

I think next big step is getting the Quad-core InterPRET with Bootloader on the FPGA