From f3fe9b6eb5ff4eed3abc85f0fdc5f2e8e21d2d84 Mon Sep 17 00:00:00 2001 From: Class Account Date: Sun, 13 Dec 2020 16:42:15 -0800 Subject: [PATCH 1/7] creating new branch --- src/ALU.v | 1 + src/ALUdec.v | 1 + src/ASel.v | 1 + src/Adder.v | 2 + src/BSel.v | 2 + src/BrUn.v | 6 +- src/CSR.v | 2 +- src/Cache.v | 205 ++++++++++++++++++++-------------------------- src/LdSel.v | 3 +- src/LdSelMux.v | 2 +- src/MemRW.v | 1 + src/PCSel.v | 1 + src/StoreSel.v | 3 +- src/StoreSelMux.v | 3 +- src/WBSel.v | 3 +- src/WBSelMux.v | 3 +- syn.yml | 2 +- 17 files changed, 114 insertions(+), 127 deletions(-) diff --git a/src/ALU.v b/src/ALU.v index 702afe6..82228f7 100755 --- a/src/ALU.v +++ b/src/ALU.v @@ -17,6 +17,7 @@ module ALU( output reg [31:0] Out ); +initial Out = 32'd0; // Implement your ALU here, then delete this comment always @(*) begin case (ALUop) diff --git a/src/ALUdec.v b/src/ALUdec.v index e1517cf..4fa5c66 100755 --- a/src/ALUdec.v +++ b/src/ALUdec.v @@ -16,6 +16,7 @@ module ALUdec( output reg [3:0] ALUop ); +initial ALUop = 4'd0; // Implement your ALU decoder here, then delete this comment always @(*) begin case (opcode) diff --git a/src/ASel.v b/src/ASel.v index fc48243..285ca89 100644 --- a/src/ASel.v +++ b/src/ASel.v @@ -15,6 +15,7 @@ assign funct3 = inst[14:12]; wire uses_pc; assign uses_pc = (opcode == `OPC_AUIPC || opcode == `OPC_JAL || opcode == `OPC_BRANCH)? 1'b1: 1'b0; +initial ASelSignal = 1'b0; always @(*) begin case (uses_pc) 1'b1: ASelSignal = 1'b1; diff --git a/src/Adder.v b/src/Adder.v index ff5dcd2..e74f9ea 100644 --- a/src/Adder.v +++ b/src/Adder.v @@ -9,6 +9,8 @@ module Adder ( output reg [31:0] stage1_pc4 ); +initial stage1_pc4 = stage1_pc + 32'd4; + always @(*) begin case (PCAddSelect) 2'b01: stage1_pc4 = stage1_pc + stage1_imm; diff --git a/src/BSel.v b/src/BSel.v index 52dba61..fbe02c6 100644 --- a/src/BSel.v +++ b/src/BSel.v @@ -16,6 +16,8 @@ assign funct3 = inst[14:12]; wire uses_imm; assign uses_imm = (opcode == `OPC_ARI_ITYPE || opcode == `OPC_LUI || opcode == `OPC_AUIPC || opcode == `OPC_JAL || opcode == `OPC_JALR || opcode == `OPC_BRANCH || opcode == `OPC_STORE || opcode == `OPC_LOAD || opcode == `OPC_CSR)? 1'b1: 1'b0; +initial BSelSignal = 1'b0; + always @(*) begin case (uses_imm) 1'b1: BSelSignal = 1'b1; diff --git a/src/BrUn.v b/src/BrUn.v index 8650182..b067e97 100644 --- a/src/BrUn.v +++ b/src/BrUn.v @@ -8,6 +8,8 @@ module BrUn ( wire [6:0] opcode = inst[6:0]; wire [2:0] funct3 = inst[14:12]; +initial BrUnSignal = 1'b0; + always @(*) begin case(opcode) `OPC_BRANCH: begin @@ -16,10 +18,10 @@ always @(*) begin `FNC_BGEU: BrUnSignal = 1'b1; `FNC_BLT: BrUnSignal = 1'b0; `FNC_BGE: BrUnSignal = 1'b0; - default: BrUnSignal = 1'bx; + default: BrUnSignal = 1'b0; endcase end - default: BrUnSignal = 1'bx; + default: BrUnSignal = 1'b0; endcase end diff --git a/src/CSR.v b/src/CSR.v index 925a98e..9b5f835 100644 --- a/src/CSR.v +++ b/src/CSR.v @@ -12,7 +12,7 @@ module CSR ( always @(posedge clk) begin if (reset) begin - csr <= 32'dx; + csr <= 32'd0; end else begin if (CSRSel) begin csr <= rs1_to_csr; diff --git a/src/Cache.v b/src/Cache.v index 6662f5f..b4b91a2 100755 --- a/src/Cache.v +++ b/src/Cache.v @@ -17,14 +17,14 @@ module cache # input [CPU_WIDTH-1:0] cpu_req_data, // 32 bits // done input [3:0] cpu_req_write, // done - output reg cpu_resp_valid, // done + output cpu_resp_valid, // done output reg [CPU_WIDTH-1:0] cpu_resp_data, // done - output reg mem_req_valid, // done + output mem_req_valid, // done input mem_req_ready, // done output reg [WORD_ADDR_BITS-1:`ceilLog2(`MEM_DATA_BITS/CPU_WIDTH)] mem_req_addr, // done - output reg mem_req_rw, // done - output reg mem_req_data_valid, // done + output mem_req_rw, // done + output mem_req_data_valid, // done input mem_req_data_ready, // done output reg [`MEM_DATA_BITS-1:0] mem_req_data_bits, // done // byte level masking @@ -37,20 +37,23 @@ module cache # reg [2:0] STATE; reg [2:0] NEXT_STATE; -wire [2:0] IDLE; -assign IDLE = 3'b000; +//initial cpu_resp_valid = 1'b0; +// initial cpu_resp_data = {32{1'b0}}; +// initial mem_req_valid = 1'b0; +initial mem_req_addr = {28{1'b0}}; +// initial mem_req_rw = 1'b0; +// initial mem_req_data_valid = 1'b0; +initial mem_req_data_bits = {128{1'b0}}; +initial mem_req_data_mask = {16{1'b0}}; + +localparam IDLE = 3'b000; +localparam READ = 3'b001; +localparam MISS = 3'b010; +localparam WRITE = 3'b011; +localparam DONE = 3'b100; -wire [2:0] READ; -assign READ = 3'b001; - -wire [2:0] MISS; -assign MISS = 3'b010; - -wire [2:0] WRITE; -assign WRITE = 3'b011; - -wire [2:0] DONE; -assign DONE = 3'b100; +initial STATE = IDLE; +initial NEXT_STATE = IDLE; //-----------------------------------// @@ -59,26 +62,41 @@ reg [22:0] tag; reg [2:0] index; reg [3:0] offset; -reg [3:0] tag_valid_addr; +initial original_addr = 30'd0; +initial tag = 23'd0; +initial index = 3'd0; +initial offset = 4'd0; + +wire [3:0] tag_valid_addr; reg [5:0] data_addr; reg write_enable_tag_valid; reg write_enable_data; +// initial tag_valid_addr = 4'd0; +initial data_addr = 6'd0; +initial write_enable_tag_valid = 1'b1; +initial write_enable_data = 1'b1; + wire [31:0] tag_valid_out; wire [127:0] data_out; reg [31:0] tag_valid_in; reg [127:0] data_in; +initial tag_valid_in = 32'd0; +initial data_in = 128'd0; + reg [31:0] original_data; reg [3:0] original_write; +initial original_data = 32'd0; +initial original_write = 4'd0; + reg [31:0] mask; -initial STATE = IDLE; -initial NEXT_STATE = IDLE; +initial mask = 32'd0; -integer clk_counter; +integer clk_counter = 0; localparam WORDS = `MEM_DATA_BITS/CPU_WIDTH; wire [`ceilLog2(WORDS)-1:0] lower_addr; @@ -86,6 +104,21 @@ assign lower_addr = original_addr[`ceilLog2(WORDS)-1:0]; assign cpu_req_ready = (STATE == IDLE || STATE == WRITE)? 1'b1 : 1'b0; +assign cpu_resp_valid = (STATE == READ && tag_valid_out[22:0] == tag && tag_valid_out[31])? 1'b1: 1'b0; +assign mem_req_valid = ((STATE == IDLE && cpu_req_valid && cpu_req_write != 4'b0000) + || (STATE == READ && !(tag_valid_out[22:0] == tag && tag_valid_out[31]) && mem_req_ready))? 1'b1: 1'b0; +assign mem_req_rw = (STATE == IDLE && cpu_req_valid && cpu_req_write != 4'b0000)? 1'b1: 1'b0; +assign mem_req_data_valid = (STATE == IDLE && cpu_req_valid && cpu_req_write != 4'b0000)? 1'b1: 1'b0; + +assign tag_valid_addr = {1'b0, index}; + +// assign cpu_resp_data = (STATE == READ && tag_valid_out[22:0] == tag && tag_valid_out[31])? +// (offset[1:0] == 2'b00)? data_out[31:0]: +// (offset[1:0] == 2'b01)? data_out[63:32]: +// (offset[1:0] == 2'b10)? data_out[95:64]: +// (offset[1:0] == 2'b11)? data_out[127:96]: 32'd0 +// : 32'd0; + // You should include a separate SRAM per way for the tags. Implement the valid bits as part of the tag SRAM. SRAM2RW16x32 tag_valid_sram ( .CE1(clk), // clock edge (clock signal) @@ -105,13 +138,6 @@ SRAM2RW16x32 tag_valid_sram ( .O2() ); - -//////////////////////////////////////////////////// -// DONT FORGET TO CHANGE NECESSARY OUTPUTS TO REG // -//////////////////////////////////////////////////// - - -// You should include a SRAM per way for data. SRAM1RW64x128 data_sram ( .CE(clk), .WEB(write_enable_data), @@ -123,12 +149,10 @@ SRAM1RW64x128 data_sram ( .O(data_out) ); -// mealy state machine? -// sequential logic always @(posedge clk) begin if (reset) begin STATE <= IDLE; - //NEXT_STATE <= IDLE; + NEXT_STATE <= IDLE; end else begin STATE <= NEXT_STATE; end @@ -147,41 +171,37 @@ always @(*) begin case (STATE) IDLE: begin if (cpu_req_valid) begin - cpu_resp_valid = 1'b0; - mem_req_valid = 1'b0; - mem_req_data_valid = 1'b0; + + //cpu_resp_valid = 1'b0; + // mem_req_valid = 1'b0; + // mem_req_data_valid = 1'b0; - // I added this - // cpu_req_ready = 1'b1; - mem_req_rw = 1'b0; + // mem_req_rw = 1'b0; - original_data = cpu_req_data; - original_write = cpu_req_write; + original_data = cpu_req_data; + original_write = cpu_req_write; - original_addr = cpu_req_addr; // 30 bits - tag = cpu_req_addr[29:7]; // 23 bits - index = cpu_req_addr[6:4]; // 3 bits - offset = cpu_req_addr[3:0]; // 4 bits + original_addr = cpu_req_addr; // 30 bits + tag = cpu_req_addr[29:7]; // 23 bits + index = cpu_req_addr[6:4]; // 3 bits + offset = cpu_req_addr[3:0]; // 4 bits - tag_valid_addr = {{1{1'b0}}, index}; // 4 bits - data_addr = (index*4) + offset[3:2]; // 6 bits + // tag_valid_addr = {{1{1'b0}}, index}; // 4 bits + data_addr = (index*4) + offset[3:2]; // 6 bits - write_enable_tag_valid = 1'b1; // SRAM -> READ - write_enable_data = 1'b1; // SRAM -> READ + write_enable_tag_valid = 1'b1; // SRAM -> READ + write_enable_data = 1'b1; // SRAM -> READ - mask = {{8{cpu_req_write[3]}}, - {8{cpu_req_write[2]}}, - {8{cpu_req_write[1]}}, - {8{cpu_req_write[0]}}}; + mask = {{8{cpu_req_write[3]}}, + {8{cpu_req_write[2]}}, + {8{cpu_req_write[1]}}, + {8{cpu_req_write[0]}}}; if (cpu_req_write == 4'b0000) begin NEXT_STATE = READ; end else if (cpu_req_write != 4'b0000) begin NEXT_STATE = WRITE; - // mem_req_addr = original_addr[29:2]; - //mem_req_rw = 1'b1; - // mem_req_valid = 1'b1; - mem_req_rw = 1'b1; + // mem_req_rw = 1'b1; case (offset[1:0]) 2'b11: begin @@ -205,12 +225,12 @@ always @(*) begin end endcase - mem_req_data_valid = 1'b1; + // mem_req_data_valid = 1'b1; mem_req_addr = original_addr[29:2]; - mem_req_valid = 1'b1; // it means the address provided above is valid + // mem_req_valid = 1'b1; // it means the address provided above is valid end - end + end end READ: begin @@ -221,17 +241,17 @@ always @(*) begin 2'b10: cpu_resp_data = data_out[95:64]; 2'b11: cpu_resp_data = data_out[127:96]; endcase - cpu_resp_valid = 1'b1; + //cpu_resp_valid = 1'b1; NEXT_STATE = IDLE; end else begin if (mem_req_ready) begin write_enable_tag_valid = 1'b0; // SRAM -> WRITE mem_req_addr = original_addr[29:2]; - mem_req_valid = 1'b1; - mem_req_rw = 1'b0; + // mem_req_valid = 1'b1; + // mem_req_rw = 1'b0; - tag_valid_addr = {{1{1'b0}}, index}; + // tag_valid_addr = {{1{1'b0}}, index}; tag_valid_in = {1'b1, {8{1'b0}}, tag}; NEXT_STATE = MISS; @@ -247,87 +267,38 @@ always @(*) begin data_in = mem_resp_data; data_addr = (index*4) + clk_counter; end -//count = count + 1; - - //$display("COUNT: %d AT CLK: %d", clk_counter, clk_counter); if (clk_counter < 3) begin - //write_enable_data = 1'b0; - - //data_in = mem_resp_data; - //data_addr = (index*4) + clk_counter; - NEXT_STATE = MISS; mem_req_addr = original_addr[29:2] + clk_counter + 1; - //mem_req_addr = mem_req_addr + 1; - //$display("MEM_REQ_ADDR: %b", mem_req_addr); end else if (clk_counter == 3) begin - // done = 1'b1; - // added the following//////////// - mem_req_valid = 1'b0; + // mem_req_valid = 1'b0; NEXT_STATE = DONE; - //end else if (clk_counter == 3) begin - // NEXT_STATE = MISS; - end + end + end else if (!mem_resp_valid) begin NEXT_STATE = MISS; end end + DONE: begin - //if (done) begin - tag_valid_addr = {{1{1'b0}}, index}; + // tag_valid_addr = {{1{1'b0}}, index}; write_enable_tag_valid = 1'b1; write_enable_data = 1'b1; // SRAM -> READ data_addr = (index*4) + offset[3:2]; NEXT_STATE = READ; - //end - - end + WRITE: begin - //mem_req_data_ready && mem_req_ready - //if (mem_req_data_ready) begin if (tag_valid_out[22:0] == tag && tag_valid_out[31] == 1'b1) begin // this is for SRAM write_enable_data = 1'b0; data_in = (data_out & ~({{`MEM_DATA_BITS-CPU_WIDTH{1'b0}}, mask} << CPU_WIDTH*lower_addr)) | ((cpu_req_data & mask) << CPU_WIDTH*lower_addr); data_addr = (index*4) + offset[3:2]; end - - // mem_req_rw = 1'b1; - - // case (offset[1:0]) - // 2'b11: begin - // mem_req_data_mask = {original_write, {12{1'b0}}}; - // mem_req_data_bits = {original_data, 96'd0}; - // end - - // 2'b10: begin - // mem_req_data_mask = {4'd0, original_write, 8'd0}; - // mem_req_data_bits = {32'd0, original_data, 64'd0}; - // end - - // 2'b01: begin - // mem_req_data_mask = {8'd0, original_write, 4'd0}; - // mem_req_data_bits = {64'd0, original_data, 32'd0}; - // end - - // 2'b00: begin - // mem_req_data_mask = {12'd0, original_write}; - // mem_req_data_bits = {96'd0, original_data}; - // end - // endcase - - // mem_req_data_valid = 1'b1; - - // mem_req_addr = original_addr[29:2]; - // mem_req_valid = 1'b1; // it means the address provided above is valid NEXT_STATE = IDLE; - // end else begin - // NEXT_STATE = WRITE; - //end end endcase end diff --git a/src/LdSel.v b/src/LdSel.v index 5dc0077..51a51d4 100644 --- a/src/LdSel.v +++ b/src/LdSel.v @@ -21,9 +21,10 @@ always @(*) begin `FNC_LW: LdSelect = 3'b010; `FNC_LBU: LdSelect = 3'b011; `FNC_LHU: LdSelect = 3'b100; + default: LdSelect = 3'b111; endcase end - default: LdSelect = 3'bxxx; + default: LdSelect = 3'b111; endcase end diff --git a/src/LdSelMux.v b/src/LdSelMux.v index 110600d..8507e3b 100644 --- a/src/LdSelMux.v +++ b/src/LdSelMux.v @@ -102,7 +102,7 @@ always @(*) begin 3'b010: wb_dmem = raw_dmem; - default: wb_dmem = 32'dx; + default: wb_dmem = 32'd0; endcase end diff --git a/src/MemRW.v b/src/MemRW.v index 3f6049d..7fff058 100644 --- a/src/MemRW.v +++ b/src/MemRW.v @@ -39,6 +39,7 @@ always @(*) begin endcase end `FNC_SW: MemRWSelect = 4'b1111; + default: MemRWSelect = 4'b0000; endcase end default: MemRWSelect = 4'b0000; diff --git a/src/PCSel.v b/src/PCSel.v index 4553d61..c7d4cd8 100644 --- a/src/PCSel.v +++ b/src/PCSel.v @@ -96,6 +96,7 @@ always @(*) begin take_branch = 1'b0; end end + default: take_branch = 1'b0; endcase end default: take_branch = 1'b0; diff --git a/src/StoreSel.v b/src/StoreSel.v index 1234b5b..a8c7ec5 100644 --- a/src/StoreSel.v +++ b/src/StoreSel.v @@ -24,9 +24,10 @@ always @(*) begin `FNC_SB: StoreSelect = 2'b00; `FNC_SH: StoreSelect = 2'b01; `FNC_SW: StoreSelect = 2'b10; + default: StoreSelect = 2'b11; endcase end - default: StoreSelect = 2'bxx; + default: StoreSelect = 2'b11; endcase end diff --git a/src/StoreSelMux.v b/src/StoreSelMux.v index 2948c9e..0b427bd 100644 --- a/src/StoreSelMux.v +++ b/src/StoreSelMux.v @@ -10,6 +10,7 @@ module StoreSelMux ( reg [31:0] shift_extended; +initial dmem_write_data = 32'd0; always @(*) begin case (StoreSel) 2'b01: // SH @@ -40,7 +41,7 @@ always @(*) begin 2'b10: dmem_write_data = stage2_rs2_data; // SW - default: dmem_write_data = 32'dx; // idc + default: dmem_write_data = 32'd0; // idc endcase end diff --git a/src/WBSel.v b/src/WBSel.v index 2d2c4a7..0fdb876 100644 --- a/src/WBSel.v +++ b/src/WBSel.v @@ -15,6 +15,7 @@ module WBSel ( wire [6:0] opcode; assign opcode = stage3_inst[6:0]; +initial WBSelect = 2'b11; always @(*) begin case (opcode) `OPC_LOAD: WBSelect = 2'b00; @@ -24,7 +25,7 @@ always @(*) begin `OPC_LUI: WBSelect = 2'b01; `OPC_JALR: WBSelect = 2'b10; `OPC_JAL: WBSelect = 2'b10; - default: WBSelect = 2'bxx; + default: WBSelect = 2'b11; endcase end diff --git a/src/WBSelMux.v b/src/WBSelMux.v index 555c51e..e106016 100644 --- a/src/WBSelMux.v +++ b/src/WBSelMux.v @@ -9,12 +9,13 @@ module WBSelMux ( output reg [31:0] wb_data ); +initial wb_data = 32'd0; always @(*) begin case (WBSel) 2'b00: wb_data = wb_dmem; 2'b01: wb_data = stage3_alu_out; 2'b10: wb_data = stage3_pc4; - default: wb_data = 32'dx; + default: wb_data = 32'd0; endcase end diff --git a/syn.yml b/syn.yml index e3bf31e..0d0a026 100755 --- a/syn.yml +++ b/syn.yml @@ -16,7 +16,7 @@ verilogSrc: &VERILOG_SRC - "src/Riscv151.v" - "src/Memory151.v" # - "src/ExtMemModel.v" - - "src/no_cache_mem.v" + # - "src/no_cache_mem.v" - "src/Cache.v" - "src/riscv_top.v" - "src/riscv_arbiter.v" From 784a5556a966c90c5d959fb0ac07516546ce7000 Mon Sep 17 00:00:00 2001 From: Class Account Date: Mon, 14 Dec 2020 13:09:19 -0800 Subject: [PATCH 2/7] created new cache --- src/Cache.v | 494 +++++++++++++++++++++++++++------------------------- 1 file changed, 259 insertions(+), 235 deletions(-) diff --git a/src/Cache.v b/src/Cache.v index b4b91a2..ab314eb 100755 --- a/src/Cache.v +++ b/src/Cache.v @@ -8,126 +8,88 @@ module cache # parameter WORD_ADDR_BITS = `CPU_ADDR_BITS-`ceilLog2(`CPU_INST_BITS/8) // 30 bits ) ( - input clk, // done - input reset, // done - - input cpu_req_valid, // done - output cpu_req_ready, // done - input [WORD_ADDR_BITS-1:0] cpu_req_addr, // 30 bits // done - input [CPU_WIDTH-1:0] cpu_req_data, // 32 bits // done - input [3:0] cpu_req_write, // done - - output cpu_resp_valid, // done - output reg [CPU_WIDTH-1:0] cpu_resp_data, // done - - output mem_req_valid, // done - input mem_req_ready, // done - output reg [WORD_ADDR_BITS-1:`ceilLog2(`MEM_DATA_BITS/CPU_WIDTH)] mem_req_addr, // done - output mem_req_rw, // done - output mem_req_data_valid, // done - input mem_req_data_ready, // done - output reg [`MEM_DATA_BITS-1:0] mem_req_data_bits, // done + input clk, + input reset, + + input cpu_req_valid, + output reg cpu_req_ready, + input [WORD_ADDR_BITS-1:0] cpu_req_addr, // 30 bits + input [CPU_WIDTH-1:0] cpu_req_data, // 32 bits + input [3:0] cpu_req_write, + + output reg cpu_resp_valid, + output reg [CPU_WIDTH-1:0] cpu_resp_data, + + output reg mem_req_valid, + input mem_req_ready, + output reg [WORD_ADDR_BITS-1:`ceilLog2(`MEM_DATA_BITS/CPU_WIDTH)] mem_req_addr, // 28 bits + output reg mem_req_rw, + output reg mem_req_data_valid, + input mem_req_data_ready, + output reg [`MEM_DATA_BITS-1:0] mem_req_data_bits, // byte level masking - output reg [(`MEM_DATA_BITS/8)-1:0] mem_req_data_mask, // done + output reg [(`MEM_DATA_BITS/8)-1:0] mem_req_data_mask, - input mem_resp_valid, // done - input [`MEM_DATA_BITS-1:0] mem_resp_data // done + input mem_resp_valid, + input [`MEM_DATA_BITS-1:0] mem_resp_data ); -reg [2:0] STATE; -reg [2:0] NEXT_STATE; - -//initial cpu_resp_valid = 1'b0; -// initial cpu_resp_data = {32{1'b0}}; -// initial mem_req_valid = 1'b0; -initial mem_req_addr = {28{1'b0}}; -// initial mem_req_rw = 1'b0; -// initial mem_req_data_valid = 1'b0; -initial mem_req_data_bits = {128{1'b0}}; -initial mem_req_data_mask = {16{1'b0}}; - +// States info localparam IDLE = 3'b000; -localparam READ = 3'b001; -localparam MISS = 3'b010; -localparam WRITE = 3'b011; -localparam DONE = 3'b100; +localparam READ = 3'b001; // Read tag +localparam MISS0 = 3'b010; +localparam MISS1 = 3'b011; +localparam MISS2 = 3'b100; +localparam MISS3 = 3'b101; +localparam WRITE = 3'b110; +localparam DONE = 3'b111; + +// mask for writing to cache +localparam WORDS = `MEM_DATA_BITS/CPU_WIDTH; +wire [`ceilLog2(WORDS)-1:0] lower_addr; +assign lower_addr = cpu_req_addr[`ceilLog2(WORDS)-1:0]; +// reg for FSM +reg [2:0] STATE; +reg [2:0] NEXT_STATE; initial STATE = IDLE; initial NEXT_STATE = IDLE; -//-----------------------------------// - +// reg for input cpu_req_addr reg [29:0] original_addr; -reg [22:0] tag; -reg [2:0] index; -reg [3:0] offset; - -initial original_addr = 30'd0; -initial tag = 23'd0; -initial index = 3'd0; -initial offset = 4'd0; - -wire [3:0] tag_valid_addr; -reg [5:0] data_addr; -reg write_enable_tag_valid; -reg write_enable_data; - -// initial tag_valid_addr = 4'd0; -initial data_addr = 6'd0; -initial write_enable_tag_valid = 1'b1; -initial write_enable_data = 1'b1; +// tag, index and offset fields of cpu_req_addr +wire [21:0] tag; +wire [3:0] index; +wire [3:0] offset; +assign tag = original_addr[29:8]; +assign index = original_addr[7:4]; +assign offset = original_addr[3:0]; + +// input and ouput reg/wire for tag_valid_sram +reg write_en_tag_valid; +reg [3:0] tag_valid_addr; // 4-bit addr to represent 16 rows +reg [31:0] tag_valid_in; wire [31:0] tag_valid_out; -wire [127:0] data_out; -reg [31:0] tag_valid_in; +// input and output reg/wire for data_sram +reg write_en_data; +reg [5:0] data_addr; reg [127:0] data_in; +wire [127:0] data_out; -initial tag_valid_in = 32'd0; -initial data_in = 128'd0; - -reg [31:0] original_data; -reg [3:0] original_write; - -initial original_data = 32'd0; -initial original_write = 4'd0; - +// reg for mask reg [31:0] mask; -initial mask = 32'd0; - -integer clk_counter = 0; - -localparam WORDS = `MEM_DATA_BITS/CPU_WIDTH; -wire [`ceilLog2(WORDS)-1:0] lower_addr; -assign lower_addr = original_addr[`ceilLog2(WORDS)-1:0]; - -assign cpu_req_ready = (STATE == IDLE || STATE == WRITE)? 1'b1 : 1'b0; - -assign cpu_resp_valid = (STATE == READ && tag_valid_out[22:0] == tag && tag_valid_out[31])? 1'b1: 1'b0; -assign mem_req_valid = ((STATE == IDLE && cpu_req_valid && cpu_req_write != 4'b0000) - || (STATE == READ && !(tag_valid_out[22:0] == tag && tag_valid_out[31]) && mem_req_ready))? 1'b1: 1'b0; -assign mem_req_rw = (STATE == IDLE && cpu_req_valid && cpu_req_write != 4'b0000)? 1'b1: 1'b0; -assign mem_req_data_valid = (STATE == IDLE && cpu_req_valid && cpu_req_write != 4'b0000)? 1'b1: 1'b0; - -assign tag_valid_addr = {1'b0, index}; - -// assign cpu_resp_data = (STATE == READ && tag_valid_out[22:0] == tag && tag_valid_out[31])? -// (offset[1:0] == 2'b00)? data_out[31:0]: -// (offset[1:0] == 2'b01)? data_out[63:32]: -// (offset[1:0] == 2'b10)? data_out[95:64]: -// (offset[1:0] == 2'b11)? data_out[127:96]: 32'd0 -// : 32'd0; -// You should include a separate SRAM per way for the tags. Implement the valid bits as part of the tag SRAM. SRAM2RW16x32 tag_valid_sram ( - .CE1(clk), // clock edge (clock signal) + .CE1(clk), .CE2(), - .WEB1(write_enable_tag_valid), // Write Enable Bar (HIGH: Read, LOW: Write) + .WEB1(write_en_tag_valid), // Write Enable Bar (HIGH: Read, LOW: Write) .WEB2(), - .OEB1(1'b0), // Output Enable Bar (always tie to LOW) + .OEB1(1'b0), .OEB2(), - .CSB1(1'b0), // Chip Select Bar (always tie to LOW) + .CSB1(1'b0), .CSB2(), .A1(tag_valid_addr), // Address pin @@ -140,7 +102,7 @@ SRAM2RW16x32 tag_valid_sram ( SRAM1RW64x128 data_sram ( .CE(clk), - .WEB(write_enable_data), + .WEB(write_en_data), // Write Enable Bar (HIGH: Read, LOW: Write) .OEB(1'b0), .CSB(1'b0), @@ -152,155 +114,217 @@ SRAM1RW64x128 data_sram ( always @(posedge clk) begin if (reset) begin STATE <= IDLE; - NEXT_STATE <= IDLE; + // NEXT_STATE <= IDLE; end else begin STATE <= NEXT_STATE; end end -always @(posedge clk) begin - if (reset || (STATE == READ && NEXT_STATE == MISS)) begin - clk_counter <= 0; - end else begin - clk_counter <= clk_counter + 1; - end -end - -// combinational logic +// combinational always @(*) begin - case (STATE) - IDLE: begin - if (cpu_req_valid) begin - - //cpu_resp_valid = 1'b0; - // mem_req_valid = 1'b0; - // mem_req_data_valid = 1'b0; - // mem_req_rw = 1'b0; - - original_data = cpu_req_data; - original_write = cpu_req_write; - - original_addr = cpu_req_addr; // 30 bits - tag = cpu_req_addr[29:7]; // 23 bits - index = cpu_req_addr[6:4]; // 3 bits - offset = cpu_req_addr[3:0]; // 4 bits - - // tag_valid_addr = {{1{1'b0}}, index}; // 4 bits - data_addr = (index*4) + offset[3:2]; // 6 bits - - write_enable_tag_valid = 1'b1; // SRAM -> READ - write_enable_data = 1'b1; // SRAM -> READ - - mask = {{8{cpu_req_write[3]}}, - {8{cpu_req_write[2]}}, - {8{cpu_req_write[1]}}, - {8{cpu_req_write[0]}}}; - - if (cpu_req_write == 4'b0000) begin - NEXT_STATE = READ; - end else if (cpu_req_write != 4'b0000) begin - NEXT_STATE = WRITE; - // mem_req_rw = 1'b1; - - case (offset[1:0]) - 2'b11: begin - mem_req_data_mask = {original_write, {12{1'b0}}}; - mem_req_data_bits = {original_data, 96'd0}; - end - - 2'b10: begin - mem_req_data_mask = {4'd0, original_write, 8'd0}; - mem_req_data_bits = {32'd0, original_data, 64'd0}; - end - - 2'b01: begin - mem_req_data_mask = {8'd0, original_write, 4'd0}; - mem_req_data_bits = {64'd0, original_data, 32'd0}; - end - - 2'b00: begin - mem_req_data_mask = {12'd0, original_write}; - mem_req_data_bits = {96'd0, original_data}; - end - endcase - - // mem_req_data_valid = 1'b1; - - mem_req_addr = original_addr[29:2]; - // mem_req_valid = 1'b1; // it means the address provided above is valid - end - end - end - - READ: begin - if (tag_valid_out[22:0] == tag && tag_valid_out[31]) begin - case (offset[1:0]) - 2'b00: cpu_resp_data = data_out[31:0]; - 2'b01: cpu_resp_data = data_out[63:32]; - 2'b10: cpu_resp_data = data_out[95:64]; - 2'b11: cpu_resp_data = data_out[127:96]; - endcase - //cpu_resp_valid = 1'b1; - NEXT_STATE = IDLE; - end else begin - if (mem_req_ready) begin - write_enable_tag_valid = 1'b0; // SRAM -> WRITE - - mem_req_addr = original_addr[29:2]; - // mem_req_valid = 1'b1; - // mem_req_rw = 1'b0; - - // tag_valid_addr = {{1{1'b0}}, index}; - tag_valid_in = {1'b1, {8{1'b0}}, tag}; - - NEXT_STATE = MISS; - end - end - end - - MISS: begin - if (mem_resp_valid) begin - if (clk_counter < 4) begin - write_enable_data = 1'b0; // SRAM -> WRITE - - data_in = mem_resp_data; - data_addr = (index*4) + clk_counter; - end + // default values for all signals + NEXT_STATE = STATE; + + // read tag by default + write_en_tag_valid = 1'b1; + // index for tag_valid_sram + tag_valid_addr = index; + + // default input data for tag_valid_sram + tag_valid_in = {1'b1, {9{1'b0}}, tag}; + + // read data by default + write_en_data = 1'b1; + // index for data_sram + data_addr = index * 4 + offset[3:2]; + + // default mask for writing to sram + mask = {{8{cpu_req_write[3]}}, + {8{cpu_req_write[2]}}, + {8{cpu_req_write[1]}}, + {8{cpu_req_write[0]}}}; + // default input data for data_sram + data_in = (data_out & ~({{`MEM_DATA_BITS-CPU_WIDTH{1'b0}}, mask} << CPU_WIDTH*lower_addr)) + | ((cpu_req_data & mask) << CPU_WIDTH*lower_addr); + + + + // assign cpu_resp_data + cpu_resp_data = cpu_resp_data; + // case (offset[1:0]) + // 2'b00: cpu_resp_data = data_out[31:0]; + // 2'b01: cpu_resp_data = data_out[63:32]; + // 2'b10: cpu_resp_data = data_out[95:64]; + // 2'b11: cpu_resp_data = data_out[127:96]; + // endcase + + // default ext memory request address + mem_req_addr = cpu_req_addr[29:2]; + // read data from ext mem by default + mem_req_rw = 1'b0; + + // default cpu control bits + cpu_req_ready = 1'b0; + cpu_resp_valid = 1'b0; + + // default ext mem control bits + mem_req_valid = 1'b0; + mem_req_data_valid = 1'b0; + + // assign mem_req_data_bits and mem_req_data_mask + case (offset[1:0]) + 2'b00: + begin + mem_req_data_bits = {96'd0, cpu_req_data}; + mem_req_data_mask = {12'd0, cpu_req_write}; + end + + 2'b01: + begin + mem_req_data_bits = {64'd0, cpu_req_data, 32'd0}; + mem_req_data_mask = {8'd0, cpu_req_write, 4'd0}; + end + + 2'b10: + begin + mem_req_data_bits = {32'd0, cpu_req_data, 64'd0}; + mem_req_data_mask = {4'd0, cpu_req_write, 8'd0}; + end + + 2'b11: + begin + mem_req_data_bits = {cpu_req_data, 96'd0}; + mem_req_data_mask = {cpu_req_write, 12'd0}; + end + endcase - if (clk_counter < 3) begin - NEXT_STATE = MISS; - mem_req_addr = original_addr[29:2] + clk_counter + 1; - end else if (clk_counter == 3) begin - // added the following//////////// - // mem_req_valid = 1'b0; + //assign - NEXT_STATE = DONE; - end - end else if (!mem_resp_valid) begin - NEXT_STATE = MISS; - end + case (STATE) + IDLE: + begin + cpu_req_ready = 1'b1; + original_addr = cpu_req_addr; + if (cpu_req_valid) begin + + if (cpu_req_write == 4'b0000) begin + NEXT_STATE = READ; + end else if (mem_req_ready) begin + NEXT_STATE = WRITE; + mem_req_rw = 1'b1; + mem_req_data_valid = 1'b1; + mem_req_valid = 1'b1; end - DONE: begin - // tag_valid_addr = {{1{1'b0}}, index}; - write_enable_tag_valid = 1'b1; - write_enable_data = 1'b1; // SRAM -> READ - data_addr = (index*4) + offset[3:2]; - NEXT_STATE = READ; - end + end + + end + + READ: + begin + + if (tag_valid_out[21:0] == tag && tag_valid_out[31]) begin + case (offset[1:0]) + 2'b00: cpu_resp_data = data_out[31:0]; + 2'b01: cpu_resp_data = data_out[63:32]; + 2'b10: cpu_resp_data = data_out[95:64]; + 2'b11: cpu_resp_data = data_out[127:96]; + endcase + cpu_resp_valid = 1'b1; + data_addr = index * 4 + offset[3:2]; + NEXT_STATE = IDLE; + end else begin + write_en_tag_valid = 1'b0; + tag_valid_addr = index; + mem_req_valid = 1'b1; + NEXT_STATE = MISS0; + end + + end + + MISS0: + begin + + if (mem_resp_valid) begin + + data_addr = index * 4; + data_in = mem_resp_data; + write_en_data = 1'b0; + + mem_req_addr = cpu_req_addr[29:2] + 1; + mem_req_valid = 1'b1; + NEXT_STATE = MISS1; + end + + end + + MISS1: + begin + + if (mem_resp_valid) begin + data_addr = index * 4 + 1; + data_in = mem_resp_data; + write_en_data = 1'b0; + + mem_req_addr = cpu_req_addr[29:2] + 2; + mem_req_valid = 1'b1; + NEXT_STATE = MISS2; + end + + end + + MISS2: + begin + + if (mem_resp_valid) begin + data_addr = index * 4 + 2; + data_in = mem_resp_data; + write_en_data = 1'b0; + + mem_req_addr = cpu_req_addr[29:2] + 3; + mem_req_valid = 1'b1; + NEXT_STATE = MISS3; + end + + end + + MISS3: + begin + + if (mem_resp_valid) begin + data_addr = index * 4 + 3; + data_in = mem_resp_data; + write_en_data = 1'b0; + mem_req_valid = 1'b0; + NEXT_STATE = DONE; + end + + end + + DONE: + begin + + NEXT_STATE = READ; + end + + WRITE: + begin + mem_req_data_valid = 1'b1; + cpu_req_ready = 1'b1; + + if (tag_valid_out[21:0] == tag && tag_valid_out[31]) begin + write_en_data = 1'b0; + end + + NEXT_STATE = IDLE; + + end - WRITE: begin - if (tag_valid_out[22:0] == tag && tag_valid_out[31] == 1'b1) begin - // this is for SRAM - write_enable_data = 1'b0; - data_in = (data_out & ~({{`MEM_DATA_BITS-CPU_WIDTH{1'b0}}, mask} << CPU_WIDTH*lower_addr)) | ((cpu_req_data & mask) << CPU_WIDTH*lower_addr); - data_addr = (index*4) + offset[3:2]; - end - NEXT_STATE = IDLE; - end endcase + + end -endmodule +endmodule \ No newline at end of file From 6c81e41c8fde0b0113ea7ff6e91acbc963b2005d Mon Sep 17 00:00:00 2001 From: Class Account Date: Mon, 14 Dec 2020 14:59:39 -0800 Subject: [PATCH 3/7] updated the new cache --- src/Cache.v | 49 ++++++++++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/src/Cache.v b/src/Cache.v index ab314eb..ce2df83 100755 --- a/src/Cache.v +++ b/src/Cache.v @@ -57,13 +57,15 @@ initial NEXT_STATE = IDLE; // reg for input cpu_req_addr reg [29:0] original_addr; +reg [3:0] original_write; +reg[31:0] original_data; // tag, index and offset fields of cpu_req_addr wire [21:0] tag; wire [3:0] index; wire [3:0] offset; assign tag = original_addr[29:8]; -assign index = original_addr[7:4]; +assign index = original_addr[7:4]; assign offset = original_addr[3:0]; // input and ouput reg/wire for tag_valid_sram @@ -140,13 +142,13 @@ always @(*) begin data_addr = index * 4 + offset[3:2]; // default mask for writing to sram - mask = {{8{cpu_req_write[3]}}, - {8{cpu_req_write[2]}}, - {8{cpu_req_write[1]}}, - {8{cpu_req_write[0]}}}; + mask = {{8{original_write[3]}}, + {8{original_write[2]}}, + {8{original_write[1]}}, + {8{original_write[0]}}}; // default input data for data_sram data_in = (data_out & ~({{`MEM_DATA_BITS-CPU_WIDTH{1'b0}}, mask} << CPU_WIDTH*lower_addr)) - | ((cpu_req_data & mask) << CPU_WIDTH*lower_addr); + | ((original_data & mask) << CPU_WIDTH*lower_addr); @@ -160,7 +162,7 @@ always @(*) begin // endcase // default ext memory request address - mem_req_addr = cpu_req_addr[29:2]; + mem_req_addr = original_addr[29:2]; // read data from ext mem by default mem_req_rw = 1'b0; @@ -176,40 +178,45 @@ always @(*) begin case (offset[1:0]) 2'b00: begin - mem_req_data_bits = {96'd0, cpu_req_data}; - mem_req_data_mask = {12'd0, cpu_req_write}; + mem_req_data_bits = {96'd0, original_data}; + mem_req_data_mask = {12'd0, original_write}; end 2'b01: begin - mem_req_data_bits = {64'd0, cpu_req_data, 32'd0}; - mem_req_data_mask = {8'd0, cpu_req_write, 4'd0}; + mem_req_data_bits = {64'd0, original_data, 32'd0}; + mem_req_data_mask = {8'd0, original_write, 4'd0}; end 2'b10: begin - mem_req_data_bits = {32'd0, cpu_req_data, 64'd0}; - mem_req_data_mask = {4'd0, cpu_req_write, 8'd0}; + mem_req_data_bits = {32'd0, original_data, 64'd0}; + mem_req_data_mask = {4'd0, original_write, 8'd0}; end 2'b11: begin - mem_req_data_bits = {cpu_req_data, 96'd0}; - mem_req_data_mask = {cpu_req_write, 12'd0}; + mem_req_data_bits = {original_data, 96'd0}; + mem_req_data_mask = {original_write, 12'd0}; end endcase - //assign + original_addr = original_addr; + original_write = original_write; + original_data = original_data; case (STATE) IDLE: begin cpu_req_ready = 1'b1; - original_addr = cpu_req_addr; + if (cpu_req_valid) begin + original_addr = cpu_req_addr; + original_write = cpu_req_write; + original_data = cpu_req_data; - if (cpu_req_write == 4'b0000) begin + if (original_write == 4'b0000) begin NEXT_STATE = READ; end else if (mem_req_ready) begin NEXT_STATE = WRITE; @@ -253,7 +260,7 @@ always @(*) begin data_in = mem_resp_data; write_en_data = 1'b0; - mem_req_addr = cpu_req_addr[29:2] + 1; + mem_req_addr = original_addr[29:2] + 1; mem_req_valid = 1'b1; NEXT_STATE = MISS1; end @@ -268,7 +275,7 @@ always @(*) begin data_in = mem_resp_data; write_en_data = 1'b0; - mem_req_addr = cpu_req_addr[29:2] + 2; + mem_req_addr = original_addr[29:2] + 2; mem_req_valid = 1'b1; NEXT_STATE = MISS2; end @@ -283,7 +290,7 @@ always @(*) begin data_in = mem_resp_data; write_en_data = 1'b0; - mem_req_addr = cpu_req_addr[29:2] + 3; + mem_req_addr = original_addr[29:2] + 3; mem_req_valid = 1'b1; NEXT_STATE = MISS3; end From fab40f1329d1a25342493b8b81dfdac4ac6c8393 Mon Sep 17 00:00:00 2001 From: Class Account Date: Mon, 14 Dec 2020 16:04:22 -0800 Subject: [PATCH 4/7] new cache done --- src/Cache.v | 3 +-- tests/bmark/cachetest.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/Cache.v b/src/Cache.v index ce2df83..d0610e3 100755 --- a/src/Cache.v +++ b/src/Cache.v @@ -242,7 +242,7 @@ always @(*) begin cpu_resp_valid = 1'b1; data_addr = index * 4 + offset[3:2]; NEXT_STATE = IDLE; - end else begin + end else if (mem_req_ready) begin write_en_tag_valid = 1'b0; tag_valid_addr = index; mem_req_valid = 1'b1; @@ -255,7 +255,6 @@ always @(*) begin begin if (mem_resp_valid) begin - data_addr = index * 4; data_in = mem_resp_data; write_en_data = 1'b0; diff --git a/tests/bmark/cachetest.c b/tests/bmark/cachetest.c index 86d8d92..55a3714 100755 --- a/tests/bmark/cachetest.c +++ b/tests/bmark/cachetest.c @@ -7,7 +7,7 @@ asm volatile ("csrw 0x51e,%[v]" :: [v]"r"(csr_val)); \ } -//#define SHORT +// #define SHORT #ifdef SHORT #define PRBS 10 #define CONST 1011556 From d195f77c69745b00dd71c93844ee08cd2b1e44a3 Mon Sep 17 00:00:00 2001 From: Class Account Date: Mon, 14 Dec 2020 16:10:45 -0800 Subject: [PATCH 5/7] all done --- par.yml | 78 ++++++++++++++++++++++++++++++++++++++++----------------- 1 file changed, 55 insertions(+), 23 deletions(-) diff --git a/par.yml b/par.yml index c677d63..518f246 100755 --- a/par.yml +++ b/par.yml @@ -3,9 +3,9 @@ # Source: hammer/src/hammer-vlsi/defaults.yml # - Valid options: # - "r0" (standard orientation) -# - "r90" (rotated 90 degrees clockwise) +# - "r90" (rotated 90 degrees clockwise) # NOT VALID # - "r180" (rotated 180 degrees) -# - "r270" (rotated 270 degrees clockwise; equivalent to -90 degrees counterclockwise) +# - "r270" (rotated 270 degrees clockwise; equivalent to -90 degrees counterclockwise) # NOT VALID # - "mx" (mirrored about the x-axis) # - "mx90" (mirrored about the x-axis, then rotated 90 degrees clockwise) # - "my" (mirrored about the y-axis) @@ -19,6 +19,38 @@ # height (float) - height in um # - Required for all types, but can be auto-filled for hierarchical and hardmacro if left blank + # #SRAM1RW64x32 + # - path: "riscv_top/mem/icache/Cache_Tag" + # type: hardmacro + # x: 95 + # y: 30 + # orientation: "my" + # master: "SRAM1RW64x32" + + # #SRAM1RW64x32 + # - path: "riscv_top/mem/dcache/Cache_Tag" + # type: hardmacro + # x: 250 + # y: 30 + # orientation: "r0" + # master: "SRAM1RW64x32" + + # #SRAM1RW256x128 + # - path: "riscv_top/mem/icache/Cache_Data" + # type: hardmacro + # x: 50 + # y: 120 + # orientation: "my" + # master: "SRAM1RW256x128" + + # #SRAM1RW256x128 + # - path: "riscv_top/mem/dcache/Cache_Data" + # type: hardmacro + # x: 250 + # y: 120 + # orientation: "r0" + # master: "SRAM1RW256x128" + vlsi.inputs.placement_constraints: - path: "riscv_top" type: toplevel @@ -44,37 +76,37 @@ vlsi.inputs.placement_constraints: # You can play around with different options of # orientations and locations to achieve good QoR - #SRAM1RW64x32 - - path: "riscv_top/mem/icache/Cache_Tag" + #SRAM2RW16x32 - ICACHE TAG - A + - path: "riscv_top/mem/icache/tag_valid_sram" type: hardmacro - x: 95 - y: 30 + x: 95.04 + y: 14.04 #30.24 orientation: "my" - master: "SRAM1RW64x32" + master: "SRAM2RW16x32" - #SRAM1RW64x32 - - path: "riscv_top/mem/dcache/Cache_Tag" + #SRAM2RW16x32 - DCACHE TAG - B + - path: "riscv_top/mem/dcache/tag_valid_sram" type: hardmacro - x: 250 - y: 30 + x: 264.6 + y: 9.72 orientation: "r0" - master: "SRAM1RW64x32" + master: "SRAM2RW16x32" - #SRAM1RW256x128 - - path: "riscv_top/mem/icache/Cache_Data" + #SRAM1RW64x128 - ICACHE DATA - C + - path: "riscv_top/mem/icache/data_sram" type: hardmacro - x: 50 - y: 120 + x: 19.44 + y: 139.32 #119.88 orientation: "my" - master: "SRAM1RW256x128" + master: "SRAM1RW64x128" - #SRAM1RW256x128 - - path: "riscv_top/mem/dcache/Cache_Data" + #SRAM1RW64x128 - DCACHE DATA - D + - path: "riscv_top/mem/dcache/data_sram" type: hardmacro - x: 250 - y: 120 + x: 284.04 + y: 140.4 #129.6 orientation: "r0" - master: "SRAM1RW256x128" + master: "SRAM1RW64x128" - path: "riscv_top/place_obs_bottom" type: obstruction @@ -126,4 +158,4 @@ par.innovus.use_cco: true # All the placement constraints specified above will be ignored. # This might lead to poor QoR and more DRVs. -#par.innovus.floorplan_mode: auto +#par.innovus.floorplan_mode: auto \ No newline at end of file From 7265aca3dfe817fed59c683f75b74a1d2650b35a Mon Sep 17 00:00:00 2001 From: Class Account Date: Mon, 14 Dec 2020 23:23:42 -0800 Subject: [PATCH 6/7] [perf] implemented branch prediction --- sim-gl-syn.yml | 2 +- src/Cache.v | 2 +- src/NOPSel.v | 4 ++-- src/PCSel.v | 8 ++++++-- src/Riscv151.v | 18 ++++++++++++++++++ src/Stage1Module.v | 7 +++++-- syn.yml | 4 ++-- 7 files changed, 35 insertions(+), 10 deletions(-) diff --git a/sim-gl-syn.yml b/sim-gl-syn.yml index 8908996..8041868 100755 --- a/sim-gl-syn.yml +++ b/sim-gl-syn.yml @@ -1,5 +1,5 @@ # Specify Global Variables -simClockPeriod : &SIM_CLK_PERIOD "CLOCK_PERIOD=2.00" +simClockPeriod : &SIM_CLK_PERIOD "CLOCK_PERIOD=2.5" simOptions: &SIM_OPTIONS - "-notice" - "-line" diff --git a/src/Cache.v b/src/Cache.v index d0610e3..1517dd0 100755 --- a/src/Cache.v +++ b/src/Cache.v @@ -333,4 +333,4 @@ always @(*) begin end -endmodule \ No newline at end of file +endmodule diff --git a/src/NOPSel.v b/src/NOPSel.v index fb98a2c..bc07dc3 100644 --- a/src/NOPSel.v +++ b/src/NOPSel.v @@ -5,7 +5,7 @@ module NOPSel ( input [31:0] icache_dout, input [31:0] prev_inst, - input stall, + input flush, output NOPSignal ); @@ -22,6 +22,6 @@ assign curr_opcode = icache_dout[6:0]; wire [4:0] curr_rs1; assign curr_rs1 = icache_dout[19:15]; -assign NOPSignal = (prev_opcode == `OPC_BRANCH || (curr_opcode == `OPC_JALR && prev_rd == curr_rs1 && prev_opcode != `OPC_NOOP && prev_opcode != `OPC_BRANCH && prev_opcode != `OPC_STORE))? 1'b1 : 1'b0; +assign NOPSignal = (flush || (curr_opcode == `OPC_JALR && prev_rd == curr_rs1 && prev_opcode != `OPC_NOOP && prev_opcode != `OPC_BRANCH && prev_opcode != `OPC_STORE))? 1'b1 : 1'b0; endmodule \ No newline at end of file diff --git a/src/PCSel.v b/src/PCSel.v index c7d4cd8..9f87604 100644 --- a/src/PCSel.v +++ b/src/PCSel.v @@ -8,7 +8,8 @@ module PCSel ( input stall, input BrEq, input BrLT, - output reg [1:0] PCSignal + output reg [1:0] PCSignal, + output reg flush ); // if R-Type and I-Type, then PC + 4 @@ -106,10 +107,13 @@ end always @(*) begin if (take_branch) begin PCSignal = 2'b01; - end else if (!take_branch && prev_opcode == `OPC_BRANCH || (curr_opcode == `OPC_JALR && prev_rd == curr_rs1 && prev_opcode != `OPC_NOOP && prev_opcode != `OPC_BRANCH && prev_opcode != `OPC_STORE)) begin + flush = 1'b1; + end else if ((curr_opcode == `OPC_JALR && prev_rd == curr_rs1 && prev_opcode != `OPC_NOOP && prev_opcode != `OPC_BRANCH && prev_opcode != `OPC_STORE)) begin PCSignal = 2'b00; + flush = 1'b0; end else begin PCSignal = 2'b10; + flush = 1'b0; end end endmodule diff --git a/src/Riscv151.v b/src/Riscv151.v index bef8f7f..8ac5156 100755 --- a/src/Riscv151.v +++ b/src/Riscv151.v @@ -48,6 +48,8 @@ wire [4:0] wb_addr; wire [31:0] dmem_write_data; +wire [31:0] flush_out; + // controls wire BrLT; wire BrEq; @@ -81,6 +83,7 @@ Stage1Module stage1 ( .icache_dout(icache_dout), .icache_addr(icache_addr), .icache_re(icache_re) + ); FlipFlop s1_to_s2_inst ( @@ -97,6 +100,21 @@ FlipFlop s1_to_s2_inst ( .data_out(stage2_inst) ); +// only need this because instruction fetch takes 2 cycles +// FlipFlop s1_to_s2_inst_flush ( + +// .clk(clk), +// .reset(reset), +// .isPC(1'b0), + +// .stall(stall), + +// .data({{31{1'b0}}, flush}), + +// .data_out(flush_out) + +// ); + FlipFlop s1_to_s2_pc ( // inputs .clk(clk), diff --git a/src/Stage1Module.v b/src/Stage1Module.v index a40b52a..57c9670 100644 --- a/src/Stage1Module.v +++ b/src/Stage1Module.v @@ -45,6 +45,8 @@ wire Data2SelSignal; wire [1:0] PCAddSelect; wire [1:0] PCSelect; +wire flush; + // for testing wire [4:0] writeback_address = wb_addr; wire [31:0] writeback_data = wb_data; @@ -103,7 +105,7 @@ NOPSel nopsel ( // inputs .icache_dout(icache_dout), .prev_inst(stage2_inst), - .stall(stall), + .flush(flush), // outputs .NOPSignal(NOPSignal) @@ -198,7 +200,8 @@ PCSel pcsel ( .BrLT(BrLT), // outputs - .PCSignal(PCSelect) + .PCSignal(PCSelect), + .flush(flush) ); PCSelMux pcselmux ( diff --git a/syn.yml b/syn.yml index 0d0a026..9506f7a 100755 --- a/syn.yml +++ b/syn.yml @@ -1,6 +1,6 @@ # Specify Global Variables -clockPeriod: &CLK_PERIOD "2.0ns" -clockPeriodby5: &CLK_PERIOD_BY_5 "0.4" # used for pin delays, update accordingly +clockPeriod: &CLK_PERIOD "0.9ns" +clockPeriodby5: &CLK_PERIOD_BY_5 "0.18" # used for pin delays, update accordingly verilogSrc: &VERILOG_SRC # - "/home/ff/eecs151/verilog_lib/EECS151.v" # - "src/ALUdec.v" From d745ab0db3a5bb4d33dd460ef7cf1cd97329fb3e Mon Sep 17 00:00:00 2001 From: Class Account Date: Mon, 14 Dec 2020 23:43:15 -0800 Subject: [PATCH 7/7] [chore] outing deliverables --- build/par-rundir/innovus.log | 12482 ++++++++++++++++ .../riscv_top_postRoute.SI_Glitches.rpt | 4 + .../timingReports/riscv_top_postRoute.cap | 11 + .../timingReports/riscv_top_postRoute.fanout | 11 + .../timingReports/riscv_top_postRoute.length | 7 + .../timingReports/riscv_top_postRoute.summary | 36 + .../timingReports/riscv_top_postRoute.tran | 11 + .../riscv_top_postRoute_all.tarpt | 7254 +++++++++ .../riscv_top_postRoute_all_hold.tarpt | 3683 +++++ .../riscv_top_postRoute_default.tarpt | 3115 ++++ .../riscv_top_postRoute_default_hold.tarpt | 2983 ++++ .../riscv_top_postRoute_hold.summary | 36 + .../riscv_top_postRoute_reg2cgate.tarpt | 3230 ++++ .../riscv_top_postRoute_reg2cgate_hold.tarpt | 2892 ++++ .../riscv_top_postRoute_reg2reg.tarpt | 7273 +++++++++ .../riscv_top_postRoute_reg2reg_hold.tarpt | 3683 +++++ .../timingReports/riscv_top_preCTS.cap | 26 + .../timingReports/riscv_top_preCTS.fanout | 11 + .../timingReports/riscv_top_preCTS.length | 7 + .../timingReports/riscv_top_preCTS.summary | 35 + .../timingReports/riscv_top_preCTS.tran | 76 + .../timingReports/riscv_top_preCTS_all.tarpt | 6376 ++++++++ .../riscv_top_preCTS_default.tarpt | 2681 ++++ .../riscv_top_preCTS_reg2cgate.tarpt | 2457 +++ .../riscv_top_preCTS_reg2reg.tarpt | 6376 ++++++++ build/syn-rundir/reports/final.rpt | 51 + build/syn-rundir/reports/final_area.rpt | 122 + build/syn-rundir/reports/final_gates.rpt | 269 + build/syn-rundir/reports/final_qor.rpt | 105 + .../final_time_PVT_0P63V_100C.setup_view.rpt | 3683 +++++ 30 files changed, 68986 insertions(+) create mode 100644 build/par-rundir/innovus.log create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute.SI_Glitches.rpt create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute.cap create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute.fanout create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute.length create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute.summary create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute.tran create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute_all.tarpt create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute_all_hold.tarpt create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute_default.tarpt create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute_default_hold.tarpt create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute_hold.summary create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute_reg2cgate.tarpt create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute_reg2cgate_hold.tarpt create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute_reg2reg.tarpt create mode 100644 build/par-rundir/timingReports/riscv_top_postRoute_reg2reg_hold.tarpt create mode 100644 build/par-rundir/timingReports/riscv_top_preCTS.cap create mode 100644 build/par-rundir/timingReports/riscv_top_preCTS.fanout create mode 100644 build/par-rundir/timingReports/riscv_top_preCTS.length create mode 100644 build/par-rundir/timingReports/riscv_top_preCTS.summary create mode 100644 build/par-rundir/timingReports/riscv_top_preCTS.tran create mode 100644 build/par-rundir/timingReports/riscv_top_preCTS_all.tarpt create mode 100644 build/par-rundir/timingReports/riscv_top_preCTS_default.tarpt create mode 100644 build/par-rundir/timingReports/riscv_top_preCTS_reg2cgate.tarpt create mode 100644 build/par-rundir/timingReports/riscv_top_preCTS_reg2reg.tarpt create mode 100644 build/syn-rundir/reports/final.rpt create mode 100644 build/syn-rundir/reports/final_area.rpt create mode 100644 build/syn-rundir/reports/final_gates.rpt create mode 100644 build/syn-rundir/reports/final_qor.rpt create mode 100644 build/syn-rundir/reports/final_time_PVT_0P63V_100C.setup_view.rpt diff --git a/build/par-rundir/innovus.log b/build/par-rundir/innovus.log new file mode 100644 index 0000000..d2e3340 --- /dev/null +++ b/build/par-rundir/innovus.log @@ -0,0 +1,12482 @@ + +Cadence Innovus(TM) Implementation System. +Copyright 2018 Cadence Design Systems, Inc. All rights reserved worldwide. + +Version: v18.10-p002_1, built Tue May 29 19:19:55 PDT 2018 +Options: -nowin -common_ui -files /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/par.tcl +Date: Mon Dec 14 21:48:32 2020 +Host: c125m-16.EECS.Berkeley.EDU (x86_64 w/Linux 3.10.0-1160.6.1.el7.x86_64) (2cores*4cpus*Intel(R) Core(TM) i5-3470T CPU @ 2.90GHz 3072KB) +OS: CentOS Linux release 7.9.2009 (Core) + +License: + invs Innovus Implementation System 18.1 checkout succeeded + 8 CPU jobs allowed with the current license(s). Use set_multi_cpu_usage to set your required CPU count. + +*************************************************************************************** +*************************************************************************************** + +Create and set the environment variable TMPDIR to /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A. + +Change the soft stacksize limit to 0.2%RAM (31 mbytes). Set global soft_stack_size_limit to change the value. + +**INFO: MMMC transition support version v31-84 + +#@ Processing -files option +@innovus 1> source /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/par.tcl +#@ Begin verbose source /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/par.tcl +@file(par.tcl) 1: puts "set_db design_process_node 7" +set_db design_process_node 7 +@file(par.tcl) 2: set_db design_process_node 7 +Applying the recommended capacitance filtering threshold values for 7nm process node: total_c_th=0, relative_c_th=1 and coupling_c_th=0.1. + These values will be used by all post-route extraction engines, including TQuantus, IQuantus and Quantus QRC extraction. + Capacitance filtering mode(extract_rc_cap_filter_mode option of the set_db) is 'relative_and_coupling' for all engines. + The accuracy mode for post_route extract_rc_effort_level low extraction will be set to 'high'. + Default value for EffortLevel(extract_rc_effort_level option of the set_db) in post_route extraction mode will be 'medium' if Quantus QRC technology file is specified else 'low'. +Updating process node dependent CCOpt properties for the 7nm process node. +@file(par.tcl) 3: puts "set_multi_cpu_usage -local_cpu 4" +set_multi_cpu_usage -local_cpu 4 +@file(par.tcl) 4: set_multi_cpu_usage -local_cpu 4 +@file(par.tcl) 5: puts "set_db timing_analysis_cppr both" +set_db timing_analysis_cppr both +@file(par.tcl) 6: set_db timing_analysis_cppr both +@file(par.tcl) 7: puts "set_db timing_analysis_type ocv" +set_db timing_analysis_type ocv +@file(par.tcl) 8: set_db timing_analysis_type ocv +@file(par.tcl) 9: puts "set_library_unit -time 1ps" +set_library_unit -time 1ps +@file(par.tcl) 10: set_library_unit -time 1ps +@file(par.tcl) 11: puts "read_physical -lef { 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/home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x4_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x16_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x4_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x16_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x22_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x39_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x4_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x16_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x4_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x8_x4.lef }" +read_physical -lef { /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/techlef_misc/asap7_tech_4x_170803.lef /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lef/scaled/asap7sc7p5t_24_R_4x_170912.lef /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lef/scaled/asap7sc7p5t_24_L_4x_170912.lef /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lef/scaled/asap7sc7p5t_24_SL_4x_170912.lef /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lef/scaled/asap7sc7p5t_24_SRAM_4x_170912.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW1024x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW128x46_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW128x48_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW128x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x128_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x46_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x48_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW32x50_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW512x128_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW512x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW512x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW64x128_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW64x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW64x34_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW64x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x16_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x4_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x16_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x4_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x16_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x22_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x39_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x4_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x16_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x4_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x8_x4.lef } +@file(par.tcl) 12: read_physical -lef { /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/techlef_misc/asap7_tech_4x_170803.lef /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lef/scaled/asap7sc7p5t_24_R_4x_170912.lef /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lef/scaled/asap7sc7p5t_24_L_4x_170912.lef /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lef/scaled/asap7sc7p5t_24_SL_4x_170912.lef /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lef/scaled/asap7sc7p5t_24_SRAM_4x_170912.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW1024x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW128x46_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW128x48_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW128x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x128_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x46_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x48_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW32x50_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW512x128_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW512x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW512x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW64x128_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW64x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW64x34_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW64x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x16_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x4_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x16_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x4_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x16_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x22_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x39_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x4_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x8_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x16_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x32_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x4_x4.lef /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x8_x4.lef } + +Loading LEF file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/techlef_misc/asap7_tech_4x_170803.lef ... + +Loading LEF file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lef/scaled/asap7sc7p5t_24_R_4x_170912.lef ... +Set DBUPerIGU to M1 pitch 576. +**WARN: (IMPLF-45): Macro 'A2O1A1Ixp33_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'A2O1A1O1Ixp25_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AND2x2_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AND2x4_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AND2x6_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AND3x1_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AND3x2_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AND3x4_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AND4x1_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AND4x2_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AND5x1_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AND5x2_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AO211x2_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AO21x1_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AO21x2_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AO221x1_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AO221x2_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AO222x2_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AO22x1_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (IMPLF-45): Macro 'AO22x2_ASAP7_75t_R' has no SITE statement and it is a class +CORE macro that requires a SITE statement. The SITE coreSite is +chosen because it is a core site with height 1.0800 that matches the macro +SIZE height. +**WARN: (EMS-27): Message (IMPLF-45) has exceeded the current message display limit of 20. +To increase the message display limit, refer to the product command reference manual. + +Loading LEF file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lef/scaled/asap7sc7p5t_24_L_4x_170912.lef ... + +Loading LEF file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lef/scaled/asap7sc7p5t_24_SL_4x_170912.lef ... + +Loading LEF file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lef/scaled/asap7sc7p5t_24_SRAM_4x_170912.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW1024x8_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW128x46_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW128x48_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW128x8_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x128_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x32_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x46_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x48_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW256x8_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW32x50_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW512x128_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW512x32_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW512x8_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW64x128_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW64x32_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW64x34_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM1RW64x8_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x16_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x32_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x4_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW128x8_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x16_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x32_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x4_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW16x8_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x16_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x22_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x32_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x39_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x4_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW32x8_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x16_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x32_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x4_x4.lef ... + +Loading LEF file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lef/SRAM2RW64x8_x4.lef ... + +viaInitial starts at Mon Dec 14 21:48:47 2020 +viaInitial ends at Mon Dec 14 21:48:47 2020 +@file(par.tcl) 13: puts "read_mmmc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/mmmc.tcl" +read_mmmc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/mmmc.tcl +@file(par.tcl) 14: read_mmmc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/mmmc.tcl +#@ Begin verbose source /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/mmmc.tcl +@file(mmmc.tcl) 1: puts "create_constraint_mode -name my_constraint_mode -sdc_files [list /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/clock_constraints_fragment.sdc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir/riscv_top.mapped.sdc]" +create_constraint_mode -name my_constraint_mode -sdc_files /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/clock_constraints_fragment.sdc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir/riscv_top.mapped.sdc +@file(mmmc.tcl) 2: create_constraint_mode -name my_constraint_mode -sdc_files [list /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/clock_constraints_fragment.sdc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir/riscv_top.mapped.sdc] +@file(mmmc.tcl) 3: puts "create_library_set -name PVT_0P63V_100C.setup_set -timing [list /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SLVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SRAM_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_RVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_LVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_SLVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_SRAM_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_RVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_LVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_SLVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_SRAM_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_RVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_LVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_SLVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_SRAM_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_RVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_LVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_SLVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_SRAM_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW1024x8_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW128x46_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW128x48_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW128x8_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x128_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x32_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x46_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x48_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x8_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW32x50_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW512x128_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW512x32_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW512x8_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW64x128_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW64x32_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW64x34_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW64x8_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW128x16_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW128x32_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW128x4_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW128x8_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW16x16_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW16x32_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW16x4_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW16x8_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x16_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x22_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x32_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x39_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x4_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x8_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x16_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x32_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x4_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x8_PVT_0P63V_100C.lib]" +create_library_set -name PVT_0P63V_100C.setup_set -timing /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_SS.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_SS.lib 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/home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x16_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x32_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x4_PVT_0P63V_100C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x8_PVT_0P63V_100C.lib] +@file(mmmc.tcl) 5: puts "create_library_set -name PVT_0P77V_0C.hold_set -timing [list /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_FF.lib 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/home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_LVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_SLVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_SRAM_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW1024x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW128x46_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW128x48_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW128x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x128_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x46_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x48_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW32x50_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW512x128_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW512x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW512x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW64x128_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW64x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW64x34_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW64x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW128x16_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW128x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW128x4_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW128x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW16x16_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW16x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW16x4_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW16x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x16_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x22_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x39_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x4_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x16_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x4_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x8_PVT_0P77V_0C.lib +@file(mmmc.tcl) 6: create_library_set -name PVT_0P77V_0C.hold_set -timing [list /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SLVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SRAM_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_RVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_LVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_SLVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_SRAM_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_RVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_LVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_SLVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_SRAM_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_RVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_LVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_SLVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_SRAM_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_RVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_LVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_SLVT_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_SRAM_FF.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW1024x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW128x46_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW128x48_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW128x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x128_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x46_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x48_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW256x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW32x50_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW512x128_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW512x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW512x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW64x128_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW64x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW64x34_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM1RW64x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW128x16_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW128x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW128x4_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW128x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW16x16_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW16x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW16x4_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW16x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x16_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x22_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x39_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x4_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW32x8_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x16_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x32_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x4_PVT_0P77V_0C.lib /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/SRAM2RW64x8_PVT_0P77V_0C.lib] +@file(mmmc.tcl) 7: puts "create_timing_condition -name PVT_0P63V_100C.setup_cond -library_sets [list PVT_0P63V_100C.setup_set]" +create_timing_condition -name PVT_0P63V_100C.setup_cond -library_sets PVT_0P63V_100C.setup_set +@file(mmmc.tcl) 8: create_timing_condition -name PVT_0P63V_100C.setup_cond -library_sets [list PVT_0P63V_100C.setup_set] +@file(mmmc.tcl) 9: puts "create_timing_condition -name PVT_0P77V_0C.hold_cond -library_sets [list PVT_0P77V_0C.hold_set]" +create_timing_condition -name PVT_0P77V_0C.hold_cond -library_sets PVT_0P77V_0C.hold_set +@file(mmmc.tcl) 10: create_timing_condition -name PVT_0P77V_0C.hold_cond -library_sets [list PVT_0P77V_0C.hold_set] +@file(mmmc.tcl) 11: puts "create_rc_corner -name PVT_0P63V_100C.setup_rc -temperature 100.0 -qrc_tech /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06" +create_rc_corner -name PVT_0P63V_100C.setup_rc -temperature 100.0 -qrc_tech /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 +@file(mmmc.tcl) 12: create_rc_corner -name PVT_0P63V_100C.setup_rc -temperature 100.0 -qrc_tech /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 +@file(mmmc.tcl) 13: puts "create_rc_corner -name PVT_0P77V_0C.hold_rc -temperature 0.0 -qrc_tech /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06" +create_rc_corner -name PVT_0P77V_0C.hold_rc -temperature 0.0 -qrc_tech /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 +@file(mmmc.tcl) 14: create_rc_corner -name PVT_0P77V_0C.hold_rc -temperature 0.0 -qrc_tech /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 +@file(mmmc.tcl) 15: puts "create_delay_corner -name PVT_0P63V_100C.setup_delay -timing_condition PVT_0P63V_100C.setup_cond -rc_corner PVT_0P63V_100C.setup_rc" +create_delay_corner -name PVT_0P63V_100C.setup_delay -timing_condition PVT_0P63V_100C.setup_cond -rc_corner PVT_0P63V_100C.setup_rc +@file(mmmc.tcl) 16: create_delay_corner -name PVT_0P63V_100C.setup_delay -timing_condition PVT_0P63V_100C.setup_cond -rc_corner PVT_0P63V_100C.setup_rc +@file(mmmc.tcl) 17: puts "create_delay_corner -name PVT_0P77V_0C.hold_delay -timing_condition PVT_0P77V_0C.hold_cond -rc_corner PVT_0P77V_0C.hold_rc" +create_delay_corner -name PVT_0P77V_0C.hold_delay -timing_condition PVT_0P77V_0C.hold_cond -rc_corner PVT_0P77V_0C.hold_rc +@file(mmmc.tcl) 18: create_delay_corner -name PVT_0P77V_0C.hold_delay -timing_condition PVT_0P77V_0C.hold_cond -rc_corner PVT_0P77V_0C.hold_rc +@file(mmmc.tcl) 19: puts "create_analysis_view -name PVT_0P63V_100C.setup_view -delay_corner PVT_0P63V_100C.setup_delay -constraint_mode my_constraint_mode" +create_analysis_view -name PVT_0P63V_100C.setup_view -delay_corner PVT_0P63V_100C.setup_delay -constraint_mode my_constraint_mode +@file(mmmc.tcl) 20: create_analysis_view -name PVT_0P63V_100C.setup_view -delay_corner PVT_0P63V_100C.setup_delay -constraint_mode my_constraint_mode +@file(mmmc.tcl) 21: puts "create_analysis_view -name PVT_0P77V_0C.hold_view -delay_corner PVT_0P77V_0C.hold_delay -constraint_mode my_constraint_mode" +create_analysis_view -name PVT_0P77V_0C.hold_view -delay_corner PVT_0P77V_0C.hold_delay -constraint_mode my_constraint_mode +@file(mmmc.tcl) 22: create_analysis_view -name PVT_0P77V_0C.hold_view -delay_corner PVT_0P77V_0C.hold_delay -constraint_mode my_constraint_mode +@file(mmmc.tcl) 23: puts "set_analysis_view -setup { PVT_0P63V_100C.setup_view } -hold { PVT_0P77V_0C.hold_view }" +set_analysis_view -setup { PVT_0P63V_100C.setup_view } -hold { PVT_0P77V_0C.hold_view } +@file(mmmc.tcl) 24: set_analysis_view -setup { PVT_0P63V_100C.setup_view } -hold { PVT_0P77V_0C.hold_view } +#@ End verbose source /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/mmmc.tcl +Starting library reading in 'Multi-threaded flow' (with '4' threads) + +Threads Configured:4 +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_SS.lib. +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2x2_ASAP7_75t_R' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2x4_ASAP7_75t_R' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2x6_ASAP7_75t_R' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND3x1_ASAP7_75t_R' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND3x2_ASAP7_75t_R' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND3x4_ASAP7_75t_R' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND4x1_ASAP7_75t_R' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND4x2_ASAP7_75t_R' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_SS.lib) +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_SS.lib, Line 11230) +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_SS.lib, Line 14483) +Read 56 cells in library asap7sc7p5t_22b_SIMPLE_RVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_SS.lib. +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2x2_ASAP7_75t_L' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2x4_ASAP7_75t_L' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2x6_ASAP7_75t_L' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND3x1_ASAP7_75t_L' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND3x2_ASAP7_75t_L' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_SS.lib) +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_SS.lib, Line 11230) +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_SS.lib, Line 14483) +Read 56 cells in library asap7sc7p5t_22b_SIMPLE_LVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SLVT_SS.lib. +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2x2_ASAP7_75t_SL' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SLVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2x4_ASAP7_75t_SL' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SLVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2x6_ASAP7_75t_SL' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SLVT_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND3x1_ASAP7_75t_SL' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SLVT_SS.lib) +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SLVT_SS.lib, Line 14483) +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SLVT_SS.lib, Line 11230) +Read 56 cells in library asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SRAM_SS.lib. +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2x2_ASAP7_75t_SRAM' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SRAM_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2x4_ASAP7_75t_SRAM' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SRAM_SS.lib) +**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2x6_ASAP7_75t_SRAM' is not defined in the library. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SRAM_SS.lib) +Message has exceeded the message display limit of '20'. Use 'set_message -no_limit -id list_of_msgIDs' to reset the message limit. +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SRAM_SS.lib, Line 11230) +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SRAM_SS.lib, Line 14483) +Read 56 cells in library asap7sc7p5t_22b_SIMPLE_SRAM_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_RVT_SS.lib. +Read 42 cells in library asap7sc7p5t_22b_AO_RVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_LVT_SS.lib. +Read 42 cells in library asap7sc7p5t_22b_AO_LVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_SLVT_SS.lib. +Read 42 cells in library asap7sc7p5t_22b_AO_SLVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_SRAM_SS.lib. +Read 42 cells in library asap7sc7p5t_22b_AO_SRAM_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_RVT_SS.lib. +Read 34 cells in library asap7sc7p5t_22b_OA_RVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_LVT_SS.lib. +Read 34 cells in library asap7sc7p5t_22b_OA_LVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_SLVT_SS.lib. +Read 34 cells in library asap7sc7p5t_22b_OA_SLVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_SRAM_SS.lib. +Read 34 cells in library asap7sc7p5t_22b_OA_SRAM_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_RVT_SS.lib. +Read 26 cells in library asap7sc7p5t_22b_SEQ_RVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_LVT_SS.lib. +Read 26 cells in library asap7sc7p5t_22b_SEQ_LVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_SLVT_SS.lib. +Read 26 cells in library asap7sc7p5t_22b_SEQ_SLVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_SRAM_SS.lib. +Read 26 cells in library asap7sc7p5t_22b_SEQ_SRAM_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_RVT_SS.lib. +Read 27 cells in library asap7sc7p5t_22b_INVBUF_RVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_LVT_SS.lib. +Read 27 cells in library asap7sc7p5t_22b_INVBUF_LVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_SLVT_SS.lib. +Read 27 cells in library asap7sc7p5t_22b_INVBUF_SLVT_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_SRAM_SS.lib. +Read 27 cells in library asap7sc7p5t_22b_INVBUF_SRAM_SS_170906. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW1024x8_lib/SRAM1RW1024x8_PVT_0P63V_100C.lib. +**WARN: (TECHLIB-9108): 'input_threshold_pct_rise' not specified in the library, using .lib default of '50%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW1024x8_lib/SRAM1RW1024x8_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'input_threshold_pct_fall' not specified in the library, using .lib default of '50%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW1024x8_lib/SRAM1RW1024x8_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'output_threshold_pct_rise' not specified in the library, using .lib default of '50%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW1024x8_lib/SRAM1RW1024x8_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'output_threshold_pct_fall' not specified in the library, using .lib default of '50%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW1024x8_lib/SRAM1RW1024x8_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'slew_lower_threshold_pct_rise' not specified in the library, using .lib default of '20%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW1024x8_lib/SRAM1RW1024x8_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'slew_lower_threshold_pct_fall' not specified in the library, using .lib default of '20%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW1024x8_lib/SRAM1RW1024x8_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'slew_upper_threshold_pct_rise' not specified in the library, using .lib default of '80%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW1024x8_lib/SRAM1RW1024x8_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'slew_upper_threshold_pct_fall' not specified in the library, using .lib default of '80%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW1024x8_lib/SRAM1RW1024x8_PVT_0P63V_100C.lib, Line 1) +Read 1 cells in library SRAM1RW1024x8_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x46_lib/SRAM1RW128x46_PVT_0P63V_100C.lib. +**WARN: (TECHLIB-9108): 'input_threshold_pct_rise' not specified in the library, using .lib default of '50%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x46_lib/SRAM1RW128x46_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'input_threshold_pct_fall' not specified in the library, using .lib default of '50%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x46_lib/SRAM1RW128x46_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'output_threshold_pct_rise' not specified in the library, using .lib default of '50%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x46_lib/SRAM1RW128x46_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'output_threshold_pct_fall' not specified in the library, using .lib default of '50%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x46_lib/SRAM1RW128x46_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'slew_lower_threshold_pct_rise' not specified in the library, using .lib default of '20%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x46_lib/SRAM1RW128x46_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'slew_lower_threshold_pct_fall' not specified in the library, using .lib default of '20%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x46_lib/SRAM1RW128x46_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'slew_upper_threshold_pct_rise' not specified in the library, using .lib default of '80%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x46_lib/SRAM1RW128x46_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'slew_upper_threshold_pct_fall' not specified in the library, using .lib default of '80%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x46_lib/SRAM1RW128x46_PVT_0P63V_100C.lib, Line 1) +Read 1 cells in library SRAM1RW128x46_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x48_lib/SRAM1RW128x48_PVT_0P63V_100C.lib. +**WARN: (TECHLIB-9108): 'input_threshold_pct_rise' not specified in the library, using .lib default of '50%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x48_lib/SRAM1RW128x48_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'input_threshold_pct_fall' not specified in the library, using .lib default of '50%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x48_lib/SRAM1RW128x48_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'output_threshold_pct_rise' not specified in the library, using .lib default of '50%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x48_lib/SRAM1RW128x48_PVT_0P63V_100C.lib, Line 1) +**WARN: (TECHLIB-9108): 'output_threshold_pct_fall' not specified in the library, using .lib default of '50%'. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x48_lib/SRAM1RW128x48_PVT_0P63V_100C.lib, Line 1) +Message has exceeded the message display limit of '20'. Use 'set_message -no_limit -id list_of_msgIDs' to reset the message limit. +Read 1 cells in library SRAM1RW128x48_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x8_lib/SRAM1RW128x8_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW128x8_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW256x128_lib/SRAM1RW256x128_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW256x128_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW256x32_lib/SRAM1RW256x32_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW256x32_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW256x46_lib/SRAM1RW256x46_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW256x46_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW256x48_lib/SRAM1RW256x48_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW256x48_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW256x8_lib/SRAM1RW256x8_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW256x8_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW32x50_lib/SRAM1RW32x50_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW32x50_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW512x128_lib/SRAM1RW512x128_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW512x128_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW512x32_lib/SRAM1RW512x32_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW512x32_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW512x8_lib/SRAM1RW512x8_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW512x8_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW64x128_lib/SRAM1RW64x128_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW64x128_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW64x32_lib/SRAM1RW64x32_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW64x32_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW64x34_lib/SRAM1RW64x34_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW64x34_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW64x8_lib/SRAM1RW64x8_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM1RW64x8_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW128x16_lib/SRAM2RW128x16_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW128x16_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW128x32_lib/SRAM2RW128x32_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW128x32_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW128x4_lib/SRAM2RW128x4_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW128x4_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW128x8_lib/SRAM2RW128x8_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW128x8_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW16x16_lib/SRAM2RW16x16_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW16x16_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW16x32_lib/SRAM2RW16x32_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW16x32_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW16x4_lib/SRAM2RW16x4_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW16x4_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW16x8_lib/SRAM2RW16x8_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW16x8_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW32x16_lib/SRAM2RW32x16_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW32x16_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW32x22_lib/SRAM2RW32x22_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW32x22_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW32x32_lib/SRAM2RW32x32_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW32x32_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW32x39_lib/SRAM2RW32x39_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW32x39_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW32x4_lib/SRAM2RW32x4_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW32x4_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW32x8_lib/SRAM2RW32x8_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW32x8_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW64x16_lib/SRAM2RW64x16_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW64x16_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW64x32_lib/SRAM2RW64x32_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW64x32_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW64x4_lib/SRAM2RW64x4_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW64x4_PVT_0P63V_100C. +Reading PVT_0P63V_100C.setup_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW64x8_lib/SRAM2RW64x8_PVT_0P63V_100C.lib. +Read 1 cells in library SRAM2RW64x8_PVT_0P63V_100C. +Library reading multithread flow ended. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW64x4_lib/SRAM2RW64x4_PVT_0P63V_100C.lib) +Starting library reading in 'Multi-threaded flow' (with '4' threads) + +Threads Configured:4 +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_FF.lib. +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_FF.lib, Line 11230) +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_RVT_FF.lib, Line 14483) +Read 56 cells in library asap7sc7p5t_22b_SIMPLE_RVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_FF.lib. +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_FF.lib, Line 11230) +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_LVT_FF.lib, Line 14483) +Read 56 cells in library asap7sc7p5t_22b_SIMPLE_LVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SLVT_FF.lib. +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SLVT_FF.lib, Line 11230) +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SLVT_FF.lib, Line 14483) +Read 56 cells in library asap7sc7p5t_22b_SIMPLE_SLVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SRAM_FF.lib. +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SRAM_FF.lib, Line 11230) +**WARN: (TECHLIB-1277): The attribute 'input_signal_level' has been defined for output pin 'CON'. 'input_signal_level' cannot be defined at this level and is being ignored. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SIMPLE_SRAM_FF.lib, Line 14483) +Read 56 cells in library asap7sc7p5t_22b_SIMPLE_SRAM_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_RVT_FF.lib. +Read 42 cells in library asap7sc7p5t_22b_AO_RVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_LVT_FF.lib. +Read 42 cells in library asap7sc7p5t_22b_AO_LVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_SLVT_FF.lib. +Read 42 cells in library asap7sc7p5t_22b_AO_SLVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_AO_SRAM_FF.lib. +Read 42 cells in library asap7sc7p5t_22b_AO_SRAM_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_RVT_FF.lib. +Read 34 cells in library asap7sc7p5t_22b_OA_RVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_LVT_FF.lib. +Read 34 cells in library asap7sc7p5t_22b_OA_LVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_SLVT_FF.lib. +Read 34 cells in library asap7sc7p5t_22b_OA_SLVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_OA_SRAM_FF.lib. +Read 34 cells in library asap7sc7p5t_22b_OA_SRAM_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_RVT_FF.lib. +Read 26 cells in library asap7sc7p5t_22b_SEQ_RVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_LVT_FF.lib. +Read 26 cells in library asap7sc7p5t_22b_SEQ_LVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_SLVT_FF.lib. +Read 26 cells in library asap7sc7p5t_22b_SEQ_SLVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_SEQ_SRAM_FF.lib. +Read 26 cells in library asap7sc7p5t_22b_SEQ_SRAM_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_RVT_FF.lib. +Read 27 cells in library asap7sc7p5t_22b_INVBUF_RVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_LVT_FF.lib. +Read 27 cells in library asap7sc7p5t_22b_INVBUF_LVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_SLVT_FF.lib. +Read 27 cells in library asap7sc7p5t_22b_INVBUF_SLVT_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/lib/asap7sc7p5t_24_INVBUF_SRAM_FF.lib. +Read 27 cells in library asap7sc7p5t_22b_INVBUF_SRAM_FF_170906. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW1024x8_lib/SRAM1RW1024x8_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW1024x8_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x46_lib/SRAM1RW128x46_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW128x46_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x48_lib/SRAM1RW128x48_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW128x48_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW128x8_lib/SRAM1RW128x8_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW128x8_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW256x128_lib/SRAM1RW256x128_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW256x128_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW256x32_lib/SRAM1RW256x32_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW256x32_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW256x46_lib/SRAM1RW256x46_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW256x46_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW256x48_lib/SRAM1RW256x48_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW256x48_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW256x8_lib/SRAM1RW256x8_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW256x8_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW32x50_lib/SRAM1RW32x50_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW32x50_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW512x128_lib/SRAM1RW512x128_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW512x128_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW512x32_lib/SRAM1RW512x32_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW512x32_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW512x8_lib/SRAM1RW512x8_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW512x8_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW64x128_lib/SRAM1RW64x128_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW64x128_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW64x32_lib/SRAM1RW64x32_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW64x32_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW64x34_lib/SRAM1RW64x34_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW64x34_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM1RW64x8_lib/SRAM1RW64x8_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM1RW64x8_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW128x16_lib/SRAM2RW128x16_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW128x16_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW128x32_lib/SRAM2RW128x32_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW128x32_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW128x4_lib/SRAM2RW128x4_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW128x4_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW128x8_lib/SRAM2RW128x8_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW128x8_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW16x16_lib/SRAM2RW16x16_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW16x16_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW16x32_lib/SRAM2RW16x32_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW16x32_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW16x4_lib/SRAM2RW16x4_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW16x4_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW16x8_lib/SRAM2RW16x8_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW16x8_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW32x16_lib/SRAM2RW32x16_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW32x16_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW32x22_lib/SRAM2RW32x22_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW32x22_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW32x32_lib/SRAM2RW32x32_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW32x32_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW32x39_lib/SRAM2RW32x39_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW32x39_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW32x4_lib/SRAM2RW32x4_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW32x4_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW32x8_lib/SRAM2RW32x8_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW32x8_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW64x16_lib/SRAM2RW64x16_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW64x16_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW64x32_lib/SRAM2RW64x32_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW64x32_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW64x4_lib/SRAM2RW64x4_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW64x4_PVT_0P77V_0C. +Reading PVT_0P77V_0C.hold_set timing library /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW64x8_lib/SRAM2RW64x8_PVT_0P77V_0C.lib. +Read 1 cells in library SRAM2RW64x8_PVT_0P77V_0C. +Library reading multithread flow ended. (File /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/lib/SRAM2RW64x8_lib/SRAM2RW64x8_PVT_0P77V_0C.lib) +@file(par.tcl) 15: puts "read_netlist { /home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir/riscv_top.mapped.v } -top riscv_top" +read_netlist { /home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir/riscv_top.mapped.v } -top riscv_top +@file(par.tcl) 16: read_netlist { /home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir/riscv_top.mapped.v } -top riscv_top +#% Begin Load netlist data ... (date=12/14 21:48:58, mem=479.1M) +*** Begin netlist parsing (mem=725.3M) *** +Created 775 new cells from 110 timing libraries. +Reading netlist ... +Backslashed names will retain backslash and a trailing blank character. +Reading verilog netlist '/home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir/riscv_top.mapped.v' + +*** Memory Usage v#1 (Current mem = 725.301M, initial mem = 267.492M) *** +*** End netlist parsing (cpu=0:00:00.1, real=0:00:00.0, mem=725.3M) *** +#% End Load netlist data ... (date=12/14 21:48:58, total cpu=0:00:00.1, real=0:00:00.0, peak res=505.8M, current mem=505.8M) +Set top cell to riscv_top. +Hooked 1550 DB cells to tlib cells. +Starting recursive module instantiation check. +No recursion found. +Building hierarchical netlist for Cell riscv_top ... +*** Netlist is unique. +Set DBUPerIGU to techSite coreSite width 864. +** info: there are 1691 modules. +** info: there are 9612 stdCell insts. +** info: there are 4 macros. + +*** Memory Usage v#1 (Current mem = 788.215M, initial mem = 267.492M) *** +@file(par.tcl) 17: puts "init_design" +init_design +@file(par.tcl) 18: init_design +Set Default Net Delay as 1000 ps. +Set Default Net Load as 0.5 pF. +Set Default Input Pin Transition as 0.1 ps. +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +**WARN: (EMS-27): Message (IMPTS-17) has exceeded the current message display limit of 1. +To increase the message display limit, refer to the product command reference manual. +PVT_0P63V_100C.setup_view PVT_0P77V_0C.hold_view +PVT_0P63V_100C.setup_view PVT_0P77V_0C.hold_view +Extraction setup Started +Initializing multi-corner RC extraction with 2 active RC Corners ... +Process node set using 'set_design_mode' is less than or equal to 32nm, for which captable file(s) would be ignored as preRoute extraction would instead use technology file. For post_route extraction, default value for effort level would be 'medium' and effort level 'low' would not be allowed. +Generating auto layer map file. +Importing multi-corner technology file(s) for preRoute extraction... +/home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 +Generating auto layer map file. +Completed (cpu: 0:00:04.1 real: 0:00:04.0) +Set Shrink Factor to 1.00000 +Summary of Active RC-Corners : + + Analysis View: PVT_0P63V_100C.setup_view + RC-Corner Name : PVT_0P63V_100C.setup_rc + RC-Corner Index : 0 + RC-Corner Temperature : 100 Celsius + RC-Corner Cap Table : '' + RC-Corner PreRoute Res Factor : 1 + RC-Corner PreRoute Cap Factor : 1 + RC-Corner PostRoute Res Factor : 1 {1 1 1} + RC-Corner PostRoute Cap Factor : 1 {1 1 1} + RC-Corner PostRoute XCap Factor : 1 {1 1 1} + RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)] + RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)] + RC-Corner PostRoute Clock Cap Factor : 1 {1 1 1} [Derived from postRoute_cap (effortLevel low)] + RC-Corner PostRoute Clock Res Factor : 1 {1 1 1} [Derived from postRoute_res (effortLevel low)] + RC-Corner Technology file: '/home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06' + + Analysis View: PVT_0P77V_0C.hold_view + RC-Corner Name : PVT_0P77V_0C.hold_rc + RC-Corner Index : 1 + RC-Corner Temperature : 0 Celsius + RC-Corner Cap Table : '' + RC-Corner PreRoute Res Factor : 1 + RC-Corner PreRoute Cap Factor : 1 + RC-Corner PostRoute Res Factor : 1 {1 1 1} + RC-Corner PostRoute Cap Factor : 1 {1 1 1} + RC-Corner PostRoute XCap Factor : 1 {1 1 1} + RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)] + RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)] + RC-Corner PostRoute Clock Cap Factor : 1 {1 1 1} [Derived from postRoute_cap (effortLevel low)] + RC-Corner PostRoute Clock Res Factor : 1 {1 1 1} [Derived from postRoute_res (effortLevel low)] + RC-Corner Technology file: '/home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06' +Updating RC grid for preRoute extraction ... +Initializing multi-corner resistance tables ... +Default value for post_route extraction mode's extract_rc_effort_level (extract_rc_effort_level option of set_db) changed to 'medium'. +*Info: initialize multi-corner CTS. +Reading timing constraints file '/home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/clock_constraints_fragment.sdc' ... +Current (total cpu=0:00:57.9, real=0:00:33.0, peak res=1365.4M, current mem=866.3M) +INFO (CTE): Constraints read successfully. +Ending "Constraint file reading stats" (total cpu=0:00:00.1, real=0:00:00.0, peak res=881.3M, current mem=881.3M) +Current (total cpu=0:00:58.0, real=0:00:33.0, peak res=1365.4M, current mem=881.3M) +Reading timing constraints file '/home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc' ... +Current (total cpu=0:00:58.0, real=0:00:33.0, peak res=1365.4M, current mem=881.3M) +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_valid' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_rw' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[27]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[26]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[25]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[24]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[23]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[22]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[21]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[20]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[19]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[18]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[17]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[16]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[15]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[14]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[13]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[12]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[11]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +**ERROR: (TCLCMD-979): Cannot apply the 'set_input_delay' command to port 'mem_req_addr[10]' because it is an invalid port for this command. Fix the timing constraint command so that it is applied to the correct type of port. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +Message has exceeded the message display limit of '20'. Use 'set_message -no_limit -id list_of_msgIDs' to reset the message limit. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc, Line 2). + +INFO (CTE): Reading of timing constraints file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/pin_constraints_fragment.sdc completed, with 0 Warnings and 20 Errors. +Ending "Constraint file reading stats" (total cpu=0:00:00.0, real=0:00:00.0, peak res=881.7M, current mem=881.7M) +Current (total cpu=0:00:58.0, real=0:00:33.0, peak res=1365.4M, current mem=881.7M) +Reading timing constraints file '/home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir/riscv_top.mapped.sdc' ... +Current (total cpu=0:00:58.0, real=0:00:33.0, peak res=1365.4M, current mem=881.7M) +**WARN: (TCLCMD-1461): Skipped unsupported command: set_units (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir/riscv_top.mapped.sdc, Line 9). + +**WARN: (TCLCMD-1461): Skipped unsupported command: set_units (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir/riscv_top.mapped.sdc, Line 10). + +riscv_top +**WARN: (TCLCMD-958): Previously defined source objects for clock 'clk' have been overwritten. To avoid overwrite, ensure that all source objects are passed to the 'create_clock' command at once. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir/riscv_top.mapped.sdc, Line 15). + +**WARN: (TCLCMD-958): Previously defined source objects for clock 'clk' have been overwritten. To avoid overwrite, ensure that all source objects are passed to the 'create_clock' command at once. (File /home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir/riscv_top.mapped.sdc, Line 15). + +INFO (CTE): Reading of timing constraints file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir/riscv_top.mapped.sdc completed, with 4 WARNING +Ending "Constraint file reading stats" (total cpu=0:00:00.0, real=0:00:00.0, peak res=882.9M, current mem=882.9M) +Current (total cpu=0:00:58.1, real=0:00:33.0, peak res=1365.4M, current mem=882.9M) +**WARN: (TA-976): Path groups asserted by the group_path constraint are considered by the software to be global in nature - they cannot be restricted to specific constraint modes. Due to this restriction, the group_path constraint is not supported directly in the constraint files which are configured in mode-specific commands such as create_constraint_mode. The current group_path entry will be ignored. You can enter the group_path constraint interactively or as part of a general command script - where it will be interpreted as global and will be in effect for all modes. +Total number of combinational cells: 636 +Total number of sequential cells: 104 +Total number of tristate cells: 0 +Total number of level shifter cells: 0 +Total number of power gating cells: 0 +Total number of isolation cells: 0 +Total number of power switch cells: 0 +Total number of pulse generator cells: 0 +Total number of always on buffers: 0 +Total number of retention cells: 0 +List of usable buffers: BUFx10_ASAP7_75t_SRAM BUFx12f_ASAP7_75t_SRAM BUFx2_ASAP7_75t_SRAM BUFx3_ASAP7_75t_SRAM BUFx5_ASAP7_75t_SRAM BUFx4f_ASAP7_75t_SRAM BUFx6f_ASAP7_75t_SRAM HB1xp67_ASAP7_75t_SRAM BUFx10_ASAP7_75t_SL BUFx12_ASAP7_75t_SL BUFx12f_ASAP7_75t_SL BUFx24_ASAP7_75t_SL BUFx2_ASAP7_75t_SL BUFx3_ASAP7_75t_SL BUFx4_ASAP7_75t_SL BUFx5_ASAP7_75t_SL BUFx4f_ASAP7_75t_SL BUFx6f_ASAP7_75t_SL BUFx8_ASAP7_75t_SL HB1xp67_ASAP7_75t_SL HB2xp67_ASAP7_75t_SL HB3xp67_ASAP7_75t_SL BUFx10_ASAP7_75t_L BUFx12_ASAP7_75t_L BUFx12f_ASAP7_75t_L BUFx24_ASAP7_75t_L BUFx2_ASAP7_75t_L BUFx3_ASAP7_75t_L BUFx4_ASAP7_75t_L BUFx5_ASAP7_75t_L BUFx4f_ASAP7_75t_L BUFx6f_ASAP7_75t_L BUFx8_ASAP7_75t_L HB1xp67_ASAP7_75t_L HB2xp67_ASAP7_75t_L HB3xp67_ASAP7_75t_L BUFx10_ASAP7_75t_R BUFx12_ASAP7_75t_R BUFx12f_ASAP7_75t_R BUFx24_ASAP7_75t_R BUFx2_ASAP7_75t_R BUFx3_ASAP7_75t_R BUFx4_ASAP7_75t_R BUFx5_ASAP7_75t_R BUFx4f_ASAP7_75t_R BUFx6f_ASAP7_75t_R BUFx8_ASAP7_75t_R HB1xp67_ASAP7_75t_R HB2xp67_ASAP7_75t_R +Total number of usable buffers: 49 +List of unusable buffers: BUFx16f_ASAP7_75t_SRAM BUFx16f_ASAP7_75t_SL BUFx16f_ASAP7_75t_L BUFx16f_ASAP7_75t_R +Total number of unusable buffers: 4 +List of usable inverters: INVx11_ASAP7_75t_SRAM INVx13_ASAP7_75t_SRAM INVx1_ASAP7_75t_SRAM INVx2_ASAP7_75t_SRAM INVx3_ASAP7_75t_SRAM INVx4_ASAP7_75t_SRAM INVx5_ASAP7_75t_SRAM INVx6_ASAP7_75t_SRAM INVx8_ASAP7_75t_SRAM INVxp67_ASAP7_75t_SRAM INVxp33_ASAP7_75t_SRAM INVx11_ASAP7_75t_SL INVx13_ASAP7_75t_SL INVx1_ASAP7_75t_SL INVx2_ASAP7_75t_SL INVx3_ASAP7_75t_SL INVx4_ASAP7_75t_SL INVx5_ASAP7_75t_SL INVx6_ASAP7_75t_SL INVx8_ASAP7_75t_SL INVxp67_ASAP7_75t_SL INVxp33_ASAP7_75t_SL INVx11_ASAP7_75t_L INVx13_ASAP7_75t_L INVx1_ASAP7_75t_L INVx2_ASAP7_75t_L INVx3_ASAP7_75t_L INVx4_ASAP7_75t_L INVx5_ASAP7_75t_L INVx6_ASAP7_75t_L INVx8_ASAP7_75t_L INVxp67_ASAP7_75t_L INVxp33_ASAP7_75t_L INVx11_ASAP7_75t_R INVx13_ASAP7_75t_R INVx1_ASAP7_75t_R INVx2_ASAP7_75t_R INVx3_ASAP7_75t_R INVx4_ASAP7_75t_R INVx5_ASAP7_75t_R INVx6_ASAP7_75t_R INVx8_ASAP7_75t_R INVxp67_ASAP7_75t_R INVxp33_ASAP7_75t_R +Total number of usable inverters: 44 +List of unusable inverters: +Total number of unusable inverters: 0 +List of identified usable delay cells: BUFx12_ASAP7_75t_SRAM BUFx24_ASAP7_75t_SRAM BUFx4_ASAP7_75t_SRAM BUFx8_ASAP7_75t_SRAM HB2xp67_ASAP7_75t_SRAM HB3xp67_ASAP7_75t_SRAM HB4xp67_ASAP7_75t_SRAM HB4xp67_ASAP7_75t_SL HB4xp67_ASAP7_75t_L HB3xp67_ASAP7_75t_R HB4xp67_ASAP7_75t_R +Total number of identified usable delay cells: 11 +List of identified unusable delay cells: +Total number of identified unusable delay cells: 0 +PVT_0P63V_100C.setup_view PVT_0P77V_0C.hold_view +PVT_0P63V_100C.setup_view PVT_0P77V_0C.hold_view +PVT_0P63V_100C.setup_view PVT_0P77V_0C.hold_view +@file(par.tcl) 19: puts "read_power_intent -cpf /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/power_spec.cpf" +read_power_intent -cpf /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/power_spec.cpf +@file(par.tcl) 20: read_power_intent -cpf /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/power_spec.cpf +Loading CPF file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/power_spec.cpf ... +INFO: processed 12 CPF commands in 12 lines from file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/power_spec.cpf, with 0 errors +Checking CPF file ... +PVT_0P63V_100C.setup_view PVT_0P77V_0C.hold_view +INFO: The CPF has only one domain defined. +Domain-based global connection will be applied to top cell. Other domain-related CPF commands will be ignored. +PVT_0P77V_0C.hold_set PVT_0P63V_100C.setup_set +PVT_0P77V_0C.hold_set PVT_0P63V_100C.setup_set +@file(par.tcl) 21: puts "commit_power_intent" +commit_power_intent +@file(par.tcl) 22: commit_power_intent +CPF_RUNTIME: clean_up_msv: cpu=0:00:00.00 real=0:00:00.00 +CPF_RUNTIME: commit_pg_nets: cpu=0:00:00.00 real=0:00:00.00 +CPF_RUNTIME: switchable_pg_nets: cpu=0:00:00.00 real=0:00:00.00 +CPF_RUNTIME: virtual_ports: cpu=0:00:00.01 real=0:00:00.00 +**WARN: (IMPCPF-980): Power domain AO is not bound to any library. Power domain library binding is through 'update_delay_corner -power_domain' in the MMMC file viewDefinition.tcl. Please make sure that 'update_delay_corner -power_domain AO' is specified for each delay corner in the MMMC file. +CPF_RUNTIME: commit_power_domain: cpu=0:00:00.05 real=0:00:00.00 +CPF_RUNTIME: assignSNetVoltages: cpu=0:00:00.04 real=0:00:00.00 +CPF_RUNTIME: define_low_power_cells: cpu=0:00:00.00 real=0:00:00.00 +CPF_RUNTIME: freeTimingGraph: cpu=0:00:00.07 real=0:00:00.00 +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +**WARN: (EMS-27): Message (IMPTS-17) has exceeded the current message display limit of 1. +To increase the message display limit, refer to the product command reference manual. +Current (total cpu=0:00:58.5, real=0:00:34.0, peak res=1365.4M, current mem=922.4M) +Ending "Constraint file reading stats" (total cpu=0:00:00.0, real=0:00:00.0, peak res=934.6M, current mem=934.6M) +Current (total cpu=0:00:58.6, real=0:00:34.0, peak res=1365.4M, current mem=934.6M) +Current (total cpu=0:00:58.6, real=0:00:34.0, peak res=1365.4M, current mem=934.6M) +Ending "Constraint file reading stats" (total cpu=0:00:00.0, real=0:00:00.0, peak res=935.0M, current mem=935.0M) +Current (total cpu=0:00:58.6, real=0:00:34.0, peak res=1365.4M, current mem=935.0M) +Current (total cpu=0:00:58.6, real=0:00:34.0, peak res=1365.4M, current mem=935.0M) +riscv_top +Ending "Constraint file reading stats" (total cpu=0:00:00.0, real=0:00:00.0, peak res=935.4M, current mem=935.4M) +Current (total cpu=0:00:58.7, real=0:00:34.0, peak res=1365.4M, current mem=935.4M) +CPF_RUNTIME: buildTimingGraph: cpu=0:00:00.28 real=0:00:01.00 +CPF_RUNTIME: commit_retention: cpu=0:00:00.00 real=0:00:00.00 +CPF_RUNTIME: applyDefaultGncRules: cpu=0:00:00.00 real=0:00:00.00 +CPF_RUNTIME: commit_global_connect: cpu=0:00:00.07 real=0:00:00.00 +CPF_RUNTIME: replaceWithAlwaysOnBuffer: cpu=0:00:00.01 real=0:00:00.00 +CPF_RUNTIME: commit_iso: cpu=0:00:00.00 real=0:00:00.00 +CPF_RUNTIME: commitEnbConn: cpu=0:00:00.00 real=0:00:00.00 +CPF_RUNTIME: commit_shifter: cpu=0:00:00.00 real=0:00:00.00 +CPF_RUNTIME: commit_pso: cpu=0:00:00.00 real=0:00:00.00 +Total number of combinational cells: 636 +Total number of sequential cells: 104 +Total number of tristate cells: 0 +Total number of level shifter cells: 0 +Total number of power gating cells: 0 +Total number of isolation cells: 0 +Total number of power switch cells: 0 +Total number of pulse generator cells: 0 +Total number of always on buffers: 0 +Total number of retention cells: 0 +List of usable buffers: BUFx10_ASAP7_75t_SRAM BUFx12f_ASAP7_75t_SRAM BUFx2_ASAP7_75t_SRAM BUFx3_ASAP7_75t_SRAM BUFx5_ASAP7_75t_SRAM BUFx4f_ASAP7_75t_SRAM BUFx6f_ASAP7_75t_SRAM HB1xp67_ASAP7_75t_SRAM BUFx10_ASAP7_75t_SL BUFx12_ASAP7_75t_SL BUFx12f_ASAP7_75t_SL BUFx24_ASAP7_75t_SL BUFx2_ASAP7_75t_SL BUFx3_ASAP7_75t_SL BUFx4_ASAP7_75t_SL BUFx5_ASAP7_75t_SL BUFx4f_ASAP7_75t_SL BUFx6f_ASAP7_75t_SL BUFx8_ASAP7_75t_SL HB1xp67_ASAP7_75t_SL HB2xp67_ASAP7_75t_SL HB3xp67_ASAP7_75t_SL BUFx10_ASAP7_75t_L BUFx12_ASAP7_75t_L BUFx12f_ASAP7_75t_L BUFx24_ASAP7_75t_L BUFx2_ASAP7_75t_L BUFx3_ASAP7_75t_L BUFx4_ASAP7_75t_L BUFx5_ASAP7_75t_L BUFx4f_ASAP7_75t_L BUFx6f_ASAP7_75t_L BUFx8_ASAP7_75t_L HB1xp67_ASAP7_75t_L HB2xp67_ASAP7_75t_L HB3xp67_ASAP7_75t_L BUFx10_ASAP7_75t_R BUFx12_ASAP7_75t_R BUFx12f_ASAP7_75t_R BUFx24_ASAP7_75t_R BUFx2_ASAP7_75t_R BUFx3_ASAP7_75t_R BUFx4_ASAP7_75t_R BUFx5_ASAP7_75t_R BUFx4f_ASAP7_75t_R BUFx6f_ASAP7_75t_R BUFx8_ASAP7_75t_R HB1xp67_ASAP7_75t_R HB2xp67_ASAP7_75t_R +Total number of usable buffers: 49 +List of unusable buffers: BUFx16f_ASAP7_75t_SRAM BUFx16f_ASAP7_75t_SL BUFx16f_ASAP7_75t_L BUFx16f_ASAP7_75t_R +Total number of unusable buffers: 4 +List of usable inverters: INVx11_ASAP7_75t_SRAM INVx13_ASAP7_75t_SRAM INVx1_ASAP7_75t_SRAM INVx2_ASAP7_75t_SRAM INVx3_ASAP7_75t_SRAM INVx4_ASAP7_75t_SRAM INVx5_ASAP7_75t_SRAM INVx6_ASAP7_75t_SRAM INVx8_ASAP7_75t_SRAM INVxp67_ASAP7_75t_SRAM INVxp33_ASAP7_75t_SRAM INVx11_ASAP7_75t_SL INVx13_ASAP7_75t_SL INVx1_ASAP7_75t_SL INVx2_ASAP7_75t_SL INVx3_ASAP7_75t_SL INVx4_ASAP7_75t_SL INVx5_ASAP7_75t_SL INVx6_ASAP7_75t_SL INVx8_ASAP7_75t_SL INVxp67_ASAP7_75t_SL INVxp33_ASAP7_75t_SL INVx11_ASAP7_75t_L INVx13_ASAP7_75t_L INVx1_ASAP7_75t_L INVx2_ASAP7_75t_L INVx3_ASAP7_75t_L INVx4_ASAP7_75t_L INVx5_ASAP7_75t_L INVx6_ASAP7_75t_L INVx8_ASAP7_75t_L INVxp67_ASAP7_75t_L INVxp33_ASAP7_75t_L INVx11_ASAP7_75t_R INVx13_ASAP7_75t_R INVx1_ASAP7_75t_R INVx2_ASAP7_75t_R INVx3_ASAP7_75t_R INVx4_ASAP7_75t_R INVx5_ASAP7_75t_R INVx6_ASAP7_75t_R INVx8_ASAP7_75t_R INVxp67_ASAP7_75t_R INVxp33_ASAP7_75t_R +Total number of usable inverters: 44 +List of unusable inverters: +Total number of unusable inverters: 0 +List of identified usable delay cells: BUFx12_ASAP7_75t_SRAM BUFx24_ASAP7_75t_SRAM BUFx4_ASAP7_75t_SRAM BUFx8_ASAP7_75t_SRAM HB2xp67_ASAP7_75t_SRAM HB3xp67_ASAP7_75t_SRAM HB4xp67_ASAP7_75t_SRAM HB4xp67_ASAP7_75t_SL HB4xp67_ASAP7_75t_L HB3xp67_ASAP7_75t_R HB4xp67_ASAP7_75t_R +Total number of identified usable delay cells: 11 +List of identified unusable delay cells: +Total number of identified unusable delay cells: 0 +-noImplicitRules false # bool, default=false, private +No isolation cell in libraries. +No level shifter cell in libraries. +PVT_0P63V_100C.setup_view PVT_0P77V_0C.hold_view +PVT_0P63V_100C.setup_view PVT_0P77V_0C.hold_view +PVT_0P63V_100C.setup_view PVT_0P77V_0C.hold_view +@file(par.tcl) 23: puts "set_db design_flow_effort standard" +set_db design_flow_effort standard +@file(par.tcl) 24: set_db design_flow_effort standard + +@file(par.tcl) 26: puts "set_dont_use \[get_db lib_cells */BUFx16f_ASAP7_75t_R\]" +set_dont_use [get_db lib_cells */BUFx16f_ASAP7_75t_R] +@file(par.tcl) 27: if { [get_db lib_cells */BUFx16f_ASAP7_75t_R] ne "" } { + set_dont_use [get_db lib_cells */BUFx16f_ASAP7_75t_R] +} else { + puts "WARNING: cell */BUFx16f_ASAP7_75t_R was not found for set_dont_use" +} +@file(par.tcl) 34: puts "set_dont_use \[get_db lib_cells */BUFx16f_ASAP7_75t_L\]" +set_dont_use [get_db lib_cells */BUFx16f_ASAP7_75t_L] +@file(par.tcl) 35: if { [get_db lib_cells */BUFx16f_ASAP7_75t_L] ne "" } { + set_dont_use [get_db lib_cells */BUFx16f_ASAP7_75t_L] +} else { + puts "WARNING: cell */BUFx16f_ASAP7_75t_L was not found for set_dont_use" +} +@file(par.tcl) 42: puts "set_dont_use \[get_db lib_cells */BUFx16f_ASAP7_75t_SL\]" +set_dont_use [get_db lib_cells */BUFx16f_ASAP7_75t_SL] +@file(par.tcl) 43: if { [get_db lib_cells */BUFx16f_ASAP7_75t_SL] ne "" } { + set_dont_use [get_db lib_cells */BUFx16f_ASAP7_75t_SL] +} else { + puts "WARNING: cell */BUFx16f_ASAP7_75t_SL was not found for set_dont_use" +} +@file(par.tcl) 50: puts "set_dont_use \[get_db lib_cells */BUFx16f_ASAP7_75t_SRAM\]" +set_dont_use [get_db lib_cells */BUFx16f_ASAP7_75t_SRAM] +@file(par.tcl) 51: if { [get_db lib_cells */BUFx16f_ASAP7_75t_SRAM] ne "" } { + set_dont_use [get_db lib_cells */BUFx16f_ASAP7_75t_SRAM] +} else { + puts "WARNING: cell */BUFx16f_ASAP7_75t_SRAM was not found for set_dont_use" +} +@file(par.tcl) 58: set_db route_design_bottom_routing_layer 2 +@file(par.tcl) 59: set_db route_design_top_routing_layer 7 +@file(par.tcl) 61: puts "write_db pre_floorplan_design" +write_db pre_floorplan_design +@file(par.tcl) 62: write_db pre_floorplan_design +#% Begin write_db save design ... (date=12/14 21:49:06, mem=936.2M) +% Begin Save ccopt configuration ... (date=12/14 21:49:06, mem=936.5M) +% End Save ccopt configuration ... (date=12/14 21:49:06, total cpu=0:00:00.0, real=0:00:00.0, peak res=937.5M, current mem=937.5M) +% Begin Save netlist data ... (date=12/14 21:49:06, mem=937.5M) +Writing Binary DB to pre_floorplan_design/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 21:49:06, total cpu=0:00:00.0, real=0:00:00.0, peak res=942.4M, current mem=942.4M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file pre_floorplan_design/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 21:49:06, mem=943.5M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 21:49:06, total cpu=0:00:00.0, real=0:00:00.0, peak res=943.5M, current mem=943.5M) +% Begin Save clock tree data ... (date=12/14 21:49:06, mem=943.6M) +2020/12/14 21:49:06 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:06 For more info, please run CheckSysConf in +2020/12/14 21:49:06 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:06 For more info, please run CheckSysConf in +% End Save clock tree data ... (date=12/14 21:49:06, total cpu=0:00:00.0, real=0:00:00.0, peak res=943.6M, current mem=943.6M) +Saving preference file pre_floorplan_design/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 21:49:07 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:07 For more info, please run CheckSysConf in +Saving Drc markers ... +... No Drc file written since there is no markers found. +% Begin Save routing data ... (date=12/14 21:49:07, mem=944.9M) +Saving route file ... +2020/12/14 21:49:07 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:07 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.0 real=0:00:00.0 mem=1027.0M) *** +% End Save routing data ... (date=12/14 21:49:07, total cpu=0:00:00.0, real=0:00:00.0, peak res=946.0M, current mem=946.0M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 21:49:07 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:07 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file pre_floorplan_design/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=1035.0M) *** +% Begin Save power constraints data ... (date=12/14 21:49:07, mem=948.5M) +% End Save power constraints data ... (date=12/14 21:49:07, total cpu=0:00:00.0, real=0:00:00.0, peak res=948.6M, current mem=948.6M) +Saving preRoute extracted patterns in file 'pre_floorplan_design/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.01 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design pre_floorplan_design +#% End write_db save design ... (date=12/14 21:49:09, total cpu=0:00:01.5, real=0:00:03.0, peak res=948.6M, current mem=946.6M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 63: puts "ln -sfn pre_floorplan_design latest" +ln -sfn pre_floorplan_design latest +@file(par.tcl) 64: ln -sfn pre_floorplan_design latest +@file(par.tcl) 65: puts "source -echo -verbose /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/floorplan.tcl" +source -echo -verbose /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/floorplan.tcl +@file(par.tcl) 66: source -echo -verbose /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/floorplan.tcl +#@ Begin verbose source /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/floorplan.tcl +@file(floorplan.tcl) 1: create_floorplan -core_margins_by die -flip f -die_size_by_io_height max -site coreSite -die_size { 350 400 0 0 0 0 } +Adjusting die size togrid(PlacementGrid): width :350.064 height : 400.032 +**WARN: (IMPFP-325): Floorplan of the design is resized. All current create_floorplan objects are automatically derived based on specified new create_floorplan. This may change blocks, fixed standard cells, existing routes and blockages. +@file(floorplan.tcl) 3: place_inst mem/icache/tag_valid_sram 95.04 14.04 my +@file(floorplan.tcl) 4: place_inst mem/dcache/tag_valid_sram 264.6 9.72 r0 +@file(floorplan.tcl) 5: place_inst mem/icache/data_sram 19.44 139.32 my +@file(floorplan.tcl) 6: place_inst mem/dcache/data_sram 284.04 140.4 r0 +@file(floorplan.tcl) 7: create_place_blockage -area {0 0 350 1.08} +#@ End verbose source /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/floorplan.tcl +@file(par.tcl) 67: puts "write_db pre_place_bumps" +write_db pre_place_bumps +@file(par.tcl) 68: write_db pre_place_bumps +#% Begin write_db save design ... (date=12/14 21:49:09, mem=947.0M) +% Begin Save ccopt configuration ... (date=12/14 21:49:09, mem=947.0M) +% End Save ccopt configuration ... (date=12/14 21:49:09, total cpu=0:00:00.0, real=0:00:00.0, peak res=947.0M, current mem=947.0M) +% Begin Save netlist data ... (date=12/14 21:49:09, mem=947.0M) +Writing Binary DB to pre_place_bumps/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 21:49:09, total cpu=0:00:00.0, real=0:00:00.0, peak res=951.6M, current mem=951.6M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file pre_place_bumps/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 21:49:09, mem=951.8M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 21:49:09, total cpu=0:00:00.0, real=0:00:00.0, peak res=951.8M, current mem=951.8M) +2020/12/14 21:49:10 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:10 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 21:49:10, mem=951.8M) +2020/12/14 21:49:10 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:10 For more info, please run CheckSysConf in +% End Save clock tree data ... (date=12/14 21:49:10, total cpu=0:00:00.0, real=0:00:00.0, peak res=951.8M, current mem=951.8M) +Saving preference file pre_place_bumps/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 21:49:10 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:10 For more info, please run CheckSysConf in +Saving Drc markers ... +... No Drc file written since there is no markers found. +% Begin Save routing data ... (date=12/14 21:49:10, mem=952.3M) +Saving route file ... +2020/12/14 21:49:10 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:10 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.0 real=0:00:00.0 mem=1070.2M) *** +% End Save routing data ... (date=12/14 21:49:10, total cpu=0:00:00.0, real=0:00:00.0, peak res=953.3M, current mem=953.3M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 21:49:10 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:10 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file pre_place_bumps/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=1078.3M) *** +% Begin Save power constraints data ... (date=12/14 21:49:10, mem=954.4M) +% End Save power constraints data ... (date=12/14 21:49:10, total cpu=0:00:00.0, real=0:00:00.0, peak res=954.4M, current mem=954.4M) +Saving preRoute extracted patterns in file 'pre_place_bumps/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.01 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design pre_place_bumps +#% End write_db save design ... (date=12/14 21:49:12, total cpu=0:00:01.3, real=0:00:03.0, peak res=954.4M, current mem=949.6M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 69: puts "ln -sfn pre_place_bumps latest" +ln -sfn pre_place_bumps latest +@file(par.tcl) 70: ln -sfn pre_place_bumps latest +@file(par.tcl) 71: puts "write_db pre_place_tap_cells" +write_db pre_place_tap_cells +@file(par.tcl) 72: write_db pre_place_tap_cells +#% Begin write_db save design ... (date=12/14 21:49:12, mem=949.6M) +% Begin Save ccopt configuration ... (date=12/14 21:49:12, mem=949.6M) +% End Save ccopt configuration ... (date=12/14 21:49:12, total cpu=0:00:00.0, real=0:00:00.0, peak res=949.6M, current mem=949.6M) +% Begin Save netlist data ... (date=12/14 21:49:12, mem=949.6M) +Writing Binary DB to pre_place_tap_cells/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 21:49:12, total cpu=0:00:00.0, real=0:00:00.0, peak res=954.3M, current mem=954.3M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file pre_place_tap_cells/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 21:49:12, mem=954.3M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 21:49:12, total cpu=0:00:00.0, real=0:00:00.0, peak res=954.3M, current mem=954.3M) +2020/12/14 21:49:12 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:12 For more info, please run CheckSysConf in +2020/12/14 21:49:12 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:12 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 21:49:12, mem=954.3M) +% End Save clock tree data ... (date=12/14 21:49:12, total cpu=0:00:00.0, real=0:00:00.0, peak res=954.3M, current mem=954.3M) +Saving preference file pre_place_tap_cells/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 21:49:13 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:13 For more info, please run CheckSysConf in +Saving Drc markers ... +... No Drc file written since there is no markers found. +% Begin Save routing data ... (date=12/14 21:49:13, mem=954.5M) +Saving route file ... +2020/12/14 21:49:13 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:13 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.0 real=0:00:00.0 mem=1095.4M) *** +% End Save routing data ... (date=12/14 21:49:13, total cpu=0:00:00.0, real=0:00:00.0, peak res=955.5M, current mem=955.5M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 21:49:13 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:13 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file pre_place_tap_cells/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=1103.4M) *** +% Begin Save power constraints data ... (date=12/14 21:49:13, mem=956.3M) +% End Save power constraints data ... (date=12/14 21:49:13, total cpu=0:00:00.0, real=0:00:00.0, peak res=956.3M, current mem=956.3M) +Saving preRoute extracted patterns in file 'pre_place_tap_cells/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.00 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design pre_place_tap_cells +#% End write_db save design ... (date=12/14 21:49:15, total cpu=0:00:01.4, real=0:00:03.0, peak res=956.3M, current mem=951.4M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 73: puts "ln -sfn pre_place_tap_cells latest" +ln -sfn pre_place_tap_cells latest +@file(par.tcl) 74: ln -sfn pre_place_tap_cells latest +@file(par.tcl) 75: set_db add_well_taps_cell TAPCELL_ASAP7_75t_L +@file(par.tcl) 76: add_well_taps -cell_interval 50 -in_row_offset 10.564 +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +**WARN: (IMPSP-362): Site 'coreSite' has one std.Cell height, so ignoring its X-symmetry. +Type 'man IMPSP-362' for more detail. +Estimated cell power/ground rail width = 0.135 um +**WARN: (IMPSP-5134): Setting cellInterval to 49.896 (microns) as a multiple of cell TAPCELL_ASAP7_75t_L's techSite 'coreSite' width of 0.216 microns +Type 'man IMPSP-5134' for more detail. +**WARN: (IMPSP-5134): Setting inRowOffset to 10.368 (microns) as a multiple of cell TAPCELL_ASAP7_75t_L's techSite 'coreSite' width of 0.216 microns +Type 'man IMPSP-5134' for more detail. +For 2823 new insts, *** Applied 2 GNC rules (cpu = 0:00:00.0) +Inserted 2823 well-taps cells (prefix WELLTAP_AO). +@file(par.tcl) 77: puts "write_db pre_power_straps" +write_db pre_power_straps +@file(par.tcl) 78: write_db pre_power_straps +#% Begin write_db save design ... (date=12/14 21:49:16, mem=1000.8M) +% Begin Save ccopt configuration ... (date=12/14 21:49:16, mem=1000.8M) +% End Save ccopt configuration ... (date=12/14 21:49:16, total cpu=0:00:00.0, real=0:00:00.0, peak res=1000.8M, current mem=1000.8M) +% Begin Save netlist data ... (date=12/14 21:49:16, mem=1000.8M) +Writing Binary DB to pre_power_straps/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 21:49:16, total cpu=0:00:00.0, real=0:00:00.0, peak res=1003.0M, current mem=1003.0M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file pre_power_straps/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 21:49:16, mem=1003.0M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 21:49:16, total cpu=0:00:00.0, real=0:00:00.0, peak res=1003.0M, current mem=1003.0M) +2020/12/14 21:49:16 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:16 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 21:49:16, mem=1003.0M) +2020/12/14 21:49:16 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:16 For more info, please run CheckSysConf in +% End Save clock tree data ... (date=12/14 21:49:16, total cpu=0:00:00.0, real=0:00:00.0, peak res=1003.0M, current mem=1003.0M) +Saving preference file pre_power_straps/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 21:49:16 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:16 For more info, please run CheckSysConf in +Saving Drc markers ... +... No Drc file written since there is no markers found. +% Begin Save routing data ... (date=12/14 21:49:16, mem=1003.1M) +Saving route file ... +2020/12/14 21:49:16 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:16 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.0 real=0:00:00.0 mem=1152.4M) *** +% End Save routing data ... (date=12/14 21:49:16, total cpu=0:00:00.0, real=0:00:00.0, peak res=1004.0M, current mem=1004.0M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 21:49:17 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:17 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 1 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file pre_power_straps/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=1168.4M) *** +% Begin Save power constraints data ... (date=12/14 21:49:17, mem=1005.1M) +% End Save power constraints data ... (date=12/14 21:49:17, total cpu=0:00:00.0, real=0:00:00.0, peak res=1005.1M, current mem=1005.1M) +Saving preRoute extracted patterns in file 'pre_power_straps/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.00 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design pre_power_straps +#% End write_db save design ... (date=12/14 21:49:19, total cpu=0:00:01.4, real=0:00:03.0, peak res=1005.1M, current mem=999.1M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 79: puts "ln -sfn pre_power_straps latest" +ln -sfn pre_power_straps latest +@file(par.tcl) 80: ln -sfn pre_power_straps latest +@file(par.tcl) 81: puts "source -echo -verbose /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/power_straps.tcl" +source -echo -verbose /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/power_straps.tcl +@file(par.tcl) 82: source -echo -verbose /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/power_straps.tcl +#@ Begin verbose source /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/power_straps.tcl +@file(power_straps.tcl) 3: reset_db -category add_stripes +@file(power_straps.tcl) 4: set_db add_stripes_stacked_via_bottom_layer M1 +@file(power_straps.tcl) 5: set_db add_stripes_stacked_via_top_layer M1 +@file(power_straps.tcl) 6: set_db add_stripes_spacing_from_block 2.000 +Global stripes will break 2.000000 user units from obstructed blocks. +@file(power_straps.tcl) 7: add_stripes -pin_layer M1 -layer M1 -over_pins 1 -master "{TAPCELL*}" -block_ring_bottom_layer_limit M1 -block_ring_top_layer_limit M1 -pad_core_ring_bottom_layer_limit M1 -pad_core_ring_top_layer_limit M1 -direction horizontal -width pin_width -nets { VSS VDD } +#% Begin add_stripes (date=12/14 21:49:19, mem=999.2M) +set_db generate_special_vai_use_fgc 1 is set by default for this design under 20nm node. +set_db add_stripes_use_fgc 1 is set by default for this design under 20nm node. +Setting -use_cce to 1. ViaGen will call CCE to colorize via and may re-colorize surrounding vias to resolve color conflict within the local range. +set_db generate_special_via_use_cce 1 is set by default for this design of 12nm node or under. +Setting generate_special_via_opt_cross_via to 1. ViaGen will try to generate vias with the minimum enclosure. +set_db generate_special_via_optimize_cross_via true is set by default for this design of 12nm node or under. +Setting generate_special_via_disable_via_merge to 1. ViaGen disables via merging with the via created earlier. +set_db generate_special_via_disable_via_merging true is set by default for this design of 12nm node or under. +Setting generate_special_via_keep_existing_via to 1. ViaGen will keep the existing vias. +set_db generate_special_via_keep_existing_via 1 is set by default for this design of 12nm node or under. +set_db add_stripes_preventive_color_opt false is set by default for this design of 12nm node or under. +set_db add_stripes_area_based_stripe true is set by default for this design of 12nm node or under. + +initialize fgc environment ... done +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_1' was increased to (10.368 1.044) (10.800 2.196) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2' was increased to (60.264 1.044) (60.696 2.196) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_3' was increased to (110.160 1.044) (110.592 2.196) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_4' was increased to (160.056 1.044) (160.488 2.196) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_5' was increased to (209.952 1.044) (210.384 2.196) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_6' was increased to (259.848 1.044) (260.280 2.196) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_7' was increased to (309.744 1.044) (310.176 2.196) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_8' was increased to (349.488 1.044) (349.920 2.196) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_9' was increased to (10.368 2.124) (10.800 3.276) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_10' was increased to (60.264 2.124) (60.696 3.276) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_11' was increased to (110.160 2.124) (110.592 3.276) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_12' was increased to (160.056 2.124) (160.488 3.276) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_13' was increased to (209.952 2.124) (210.384 3.276) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_14' was increased to (259.848 2.124) (260.280 3.276) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_15' was increased to (309.744 2.124) (310.176 3.276) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_16' was increased to (349.488 2.124) (349.920 3.276) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_17' was increased to (10.368 3.204) (10.800 4.356) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_18' was increased to (60.264 3.204) (60.696 4.356) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_19' was increased to (110.160 3.204) (110.592 4.356) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_20' was increased to (160.056 3.204) (160.488 4.356) because pins or obstructions were outside the original block boundary. +**WARN: (EMS-27): Message (IMPPP-133) has exceeded the current message display limit of 20. +To increase the message display limit, refer to the product command reference manual. +Starting stripe generation ... +Non-Default Mode Option Settings : + -spacing_from_block 2.00 + -use_exact_spacing 1 + -preventive_color_opt false + -use_fgc true +The core ring for VSS is incomplete. The core ring will not be used as a boundary for stripes. In this situation, the power planner will generate stripes only within the core area. +The core ring for VDD is incomplete. The core ring will not be used as a boundary for stripes. In this situation, the power planner will generate stripes only within the core area. +Stripe generation is complete. +add_stripes created 858 wires. +ViaGen created 0 via, deleted 0 via to avoid violation. ++--------+----------------+----------------+ +| Layer | Created | Deleted | ++--------+----------------+----------------+ +| M1 | 858 | NA | ++--------+----------------+----------------+ +#% End add_stripes (date=12/14 21:49:20, total cpu=0:00:00.6, real=0:00:01.0, peak res=1008.0M, current mem=1008.0M) +@file(power_straps.tcl) 11: reset_db -category add_stripes +@file(power_straps.tcl) 12: set_db add_stripes_stacked_via_top_layer M3 +@file(power_straps.tcl) 13: set_db add_stripes_stacked_via_bottom_layer M1 +@file(power_straps.tcl) 14: set_db add_stripes_trim_antenna_back_to_shape {stripe} +The power planner will set stripe antenna targets to stripe. +@file(power_straps.tcl) 15: set_db add_stripes_spacing_from_block 2.000 +Global stripes will break 2.000000 user units from obstructed blocks. +@file(power_straps.tcl) 16: add_stripes -create_pins 0 -block_ring_bottom_layer_limit M3 -block_ring_top_layer_limit M1 -direction vertical -layer M3 -nets {VSS VDD} -pad_core_ring_bottom_layer_limit M1 -set_to_set_distance 8.640 -spacing 0.216 -switch_layer_over_obs 0 -width 0.936 -area [get_db designs .core_bbox] -start [expr [lindex [lindex [get_db designs .core_bbox] 0] 0] + 1.548] +#% Begin add_stripes (date=12/14 21:49:20, mem=1008.0M) +set_db add_stripes_use_fgc 1 is set by default for this design under 20nm node. + +**WARN: (IMPPP-2030): Layer M3 allows on grid right way wires only. Snap wire center to routing grid automatically. +initialize fgc environment ... done +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2807' was increased to (349.488 396.324) (349.920 397.476) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2815' was increased to (349.488 397.404) (349.920 398.556) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2823' was increased to (349.488 398.484) (349.920 399.636) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2722' was increased to (283.608 383.364) (284.040 384.516) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2673' was increased to (283.608 375.804) (284.040 376.956) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2680' was increased to (283.608 376.884) (284.040 378.036) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2687' was increased to (283.608 377.964) (284.040 379.116) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2694' was increased to (283.608 379.044) (284.040 380.196) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2701' was increased to (283.608 380.124) (284.040 381.276) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2708' was increased to (283.608 381.204) (284.040 382.356) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2715' was increased to (283.608 382.284) (284.040 383.436) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2729' was increased to (283.608 384.444) (284.040 385.596) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2736' was increased to (283.608 385.524) (284.040 386.676) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2743' was increased to (283.608 386.604) (284.040 387.756) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2750' was increased to (283.608 387.684) (284.040 388.836) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2757' was increased to (283.608 388.764) (284.040 389.916) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2764' was increased to (283.608 389.844) (284.040 390.996) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2771' was increased to (283.608 390.924) (284.040 392.076) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2778' was increased to (283.608 392.004) (284.040 393.156) because pins or obstructions were outside the original block boundary. +**WARN: (IMPPP-133): The block boundary of instance 'WELLTAP_AO_2785' was increased to (283.608 393.084) (284.040 394.236) because pins or obstructions were outside the original block boundary. +**WARN: (EMS-27): Message (IMPPP-133) has exceeded the current message display limit of 20. +To increase the message display limit, refer to the product command reference manual. +Starting stripe generation ... +**WARN: (IMPPP-358): The left edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The right edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The bottom edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The top edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +Non-Default Mode Option Settings : + -spacing_from_block 2.00 + -trim_antenna_back_to_shape stripe + -trim_antenna_max_distance 0.00 + -use_exact_spacing 1 + -preventive_color_opt false + -use_fgc true +Multi-CPU acceleration using 4 CPU(s). +*** Stripes and vias are being generated (current mem: 1149.391)*** + Generate VSS stripes and vias + Completing 10% (cpu time: 0:00:00.1, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.1, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VSS stripes and vias are completed(total cpu time: 0:00:00.3, peak mem: 1149.391M) + Generate VDD stripes and vias + Completing 10% (cpu time: 0:00:00.1, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VDD stripes and vias are completed(total cpu time: 0:00:00.3, peak mem: 1149.391M) +Stripe generation is complete. +add_stripes created 121 wires. +ViaGen created 21350 vias, deleted 0 via to avoid violation. ++--------+----------------+----------------+ +| Layer | Created | Deleted | ++--------+----------------+----------------+ +| V1 | 10675 | 0 | +| V2 | 10675 | 0 | +| M3 | 121 | NA | ++--------+----------------+----------------+ +#% End add_stripes (date=12/14 21:49:20, total cpu=0:00:00.7, real=0:00:00.0, peak res=1008.0M, current mem=1007.9M) +@file(power_straps.tcl) 20: reset_db -category add_stripes +@file(power_straps.tcl) 21: set_db add_stripes_stacked_via_top_layer M4 +@file(power_straps.tcl) 22: set_db add_stripes_stacked_via_bottom_layer M3 +@file(power_straps.tcl) 23: set_db add_stripes_trim_antenna_back_to_shape {stripe} +The power planner will set stripe antenna targets to stripe. +@file(power_straps.tcl) 24: set_db add_stripes_spacing_from_block 2.000 +Global stripes will break 2.000000 user units from obstructed blocks. +@file(power_straps.tcl) 25: add_stripes -create_pins 0 -block_ring_bottom_layer_limit M4 -block_ring_top_layer_limit M3 -direction horizontal -layer M4 -nets {VSS VDD} -pad_core_ring_bottom_layer_limit M3 -set_to_set_distance 10.752 -spacing 0.288 -switch_layer_over_obs 0 -width 0.864 -area [get_db designs .core_bbox] -start [expr [lindex [lindex [get_db designs .core_bbox] 0] 1] + 2.268] +#% Begin add_stripes (date=12/14 21:49:20, mem=1007.9M) +set_db add_stripes_use_fgc 1 is set by default for this design under 20nm node. + +**WARN: (IMPPP-2030): Layer M4 allows on grid right way wires only. Snap wire center to routing grid automatically. +initialize fgc environment ... done +Starting stripe generation ... +**WARN: (IMPPP-358): The left edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The right edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The bottom edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The top edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +Non-Default Mode Option Settings : + -spacing_from_block 2.00 + -trim_antenna_back_to_shape stripe + -trim_antenna_max_distance 0.00 + -use_exact_spacing 1 + -preventive_color_opt false + -use_fgc true +Multi-CPU acceleration using 4 CPU(s). +*** Stripes and vias are being generated (current mem: 1149.391)*** + Generate VDD stripes and vias + Completing 10% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VDD stripes and vias are completed(total cpu time: 0:00:00.0, peak mem: 1149.391M) + Generate VSS stripes and vias + Completing 10% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VSS stripes and vias are completed(total cpu time: 0:00:00.0, peak mem: 1149.391M) +Stripe generation is complete. +add_stripes created 171 wires. +ViaGen created 2135 vias, deleted 0 via to avoid violation. ++--------+----------------+----------------+ +| Layer | Created | Deleted | ++--------+----------------+----------------+ +| V3 | 2135 | 0 | +| M4 | 171 | NA | ++--------+----------------+----------------+ +#% End add_stripes (date=12/14 21:49:21, total cpu=0:00:00.2, real=0:00:01.0, peak res=1007.9M, current mem=1007.9M) +@file(power_straps.tcl) 29: reset_db -category add_stripes +@file(power_straps.tcl) 30: set_db add_stripes_stacked_via_top_layer M5 +@file(power_straps.tcl) 31: set_db add_stripes_stacked_via_bottom_layer M4 +@file(power_straps.tcl) 32: set_db add_stripes_trim_antenna_back_to_shape {stripe} +The power planner will set stripe antenna targets to stripe. +@file(power_straps.tcl) 33: set_db add_stripes_spacing_from_block 2.000 +Global stripes will break 2.000000 user units from obstructed blocks. +@file(power_straps.tcl) 34: add_stripes -create_pins 0 -block_ring_bottom_layer_limit M5 -block_ring_top_layer_limit M4 -direction vertical -layer M5 -nets {VSS VDD} -pad_core_ring_bottom_layer_limit M4 -set_to_set_distance 10.752 -spacing 0.288 -switch_layer_over_obs 0 -width 0.864 -area [get_db designs .core_bbox] -start [expr [lindex [lindex [get_db designs .core_bbox] 0] 0] + 2.256] +#% Begin add_stripes (date=12/14 21:49:21, mem=1007.9M) +set_db add_stripes_use_fgc 1 is set by default for this design under 20nm node. + +**WARN: (IMPPP-2030): Layer M5 allows on grid right way wires only. Snap wire center to routing grid automatically. +initialize fgc environment ... done +Starting stripe generation ... +**WARN: (IMPPP-358): The left edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The right edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The bottom edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The top edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +Non-Default Mode Option Settings : + -spacing_from_block 2.00 + -trim_antenna_back_to_shape stripe + -trim_antenna_max_distance 0.00 + -use_exact_spacing 1 + -preventive_color_opt false + -use_fgc true +Multi-CPU acceleration using 4 CPU(s). +*** Stripes and vias are being generated (current mem: 1149.391)*** + Generate VSS stripes and vias + Completing 10% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VSS stripes and vias are completed(total cpu time: 0:00:00.0, peak mem: 1149.391M) + Generate VDD stripes and vias + Completing 10% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VDD stripes and vias are completed(total cpu time: 0:00:00.0, peak mem: 1149.391M) +Stripe generation is complete. +add_stripes created 66 wires. +ViaGen created 2677 vias, deleted 0 via to avoid violation. ++--------+----------------+----------------+ +| Layer | Created | Deleted | ++--------+----------------+----------------+ +| V4 | 2677 | 0 | +| M5 | 66 | NA | ++--------+----------------+----------------+ +#% End add_stripes (date=12/14 21:49:21, total cpu=0:00:00.2, real=0:00:00.0, peak res=1008.0M, current mem=1008.0M) +@file(power_straps.tcl) 38: reset_db -category add_stripes +@file(power_straps.tcl) 39: set_db add_stripes_stacked_via_top_layer M6 +@file(power_straps.tcl) 40: set_db add_stripes_stacked_via_bottom_layer M5 +@file(power_straps.tcl) 41: set_db add_stripes_trim_antenna_back_to_shape {stripe} +The power planner will set stripe antenna targets to stripe. +@file(power_straps.tcl) 42: set_db add_stripes_spacing_from_block 2.000 +Global stripes will break 2.000000 user units from obstructed blocks. +@file(power_straps.tcl) 43: add_stripes -create_pins 0 -block_ring_bottom_layer_limit M6 -block_ring_top_layer_limit M5 -direction horizontal -layer M6 -nets {VSS VDD} -pad_core_ring_bottom_layer_limit M5 -set_to_set_distance 14.336 -spacing 0.288 -switch_layer_over_obs 0 -width 1.152 -area [get_db designs .core_bbox] -start [expr [lindex [lindex [get_db designs .core_bbox] 0] 1] + 2.912] +#% Begin add_stripes (date=12/14 21:49:21, mem=1008.0M) +set_db add_stripes_use_fgc 1 is set by default for this design under 20nm node. + +**WARN: (IMPPP-2030): Layer M6 allows on grid right way wires only. Snap wire center to routing grid automatically. +initialize fgc environment ... done +Starting stripe generation ... +**WARN: (IMPPP-358): The left edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The right edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The bottom edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The top edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +Non-Default Mode Option Settings : + -spacing_from_block 2.00 + -trim_antenna_back_to_shape stripe + -trim_antenna_max_distance 0.00 + -use_exact_spacing 1 + -preventive_color_opt false + -use_fgc true +Multi-CPU acceleration using 4 CPU(s). +*** Stripes and vias are being generated (current mem: 1149.391)*** + Generate VDD stripes and vias + Completing 10% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VDD stripes and vias are completed(total cpu time: 0:00:00.0, peak mem: 1149.391M) + Generate VSS stripes and vias + Completing 10% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VSS stripes and vias are completed(total cpu time: 0:00:00.0, peak mem: 1149.391M) +Stripe generation is complete. +add_stripes created 56 wires. +ViaGen created 1848 vias, deleted 0 via to avoid violation. ++--------+----------------+----------------+ +| Layer | Created | Deleted | ++--------+----------------+----------------+ +| V5 | 1848 | 0 | +| M6 | 56 | NA | ++--------+----------------+----------------+ +#% End add_stripes (date=12/14 21:49:21, total cpu=0:00:00.2, real=0:00:00.0, peak res=1008.0M, current mem=1008.0M) +@file(power_straps.tcl) 47: reset_db -category add_stripes +@file(power_straps.tcl) 48: set_db add_stripes_stacked_via_top_layer M7 +@file(power_straps.tcl) 49: set_db add_stripes_stacked_via_bottom_layer M6 +@file(power_straps.tcl) 50: set_db add_stripes_trim_antenna_back_to_shape {stripe} +The power planner will set stripe antenna targets to stripe. +@file(power_straps.tcl) 51: set_db add_stripes_spacing_from_block 2.000 +Global stripes will break 2.000000 user units from obstructed blocks. +@file(power_straps.tcl) 52: add_stripes -create_pins 0 -block_ring_bottom_layer_limit M7 -block_ring_top_layer_limit M6 -direction vertical -layer M7 -nets {VSS VDD} -pad_core_ring_bottom_layer_limit M6 -set_to_set_distance 14.336 -spacing 0.288 -switch_layer_over_obs 0 -width 1.152 -area [get_db designs .core_bbox] -start [expr [lindex [lindex [get_db designs .core_bbox] 0] 0] + 2.912] +#% Begin add_stripes (date=12/14 21:49:21, mem=1008.0M) +set_db add_stripes_use_fgc 1 is set by default for this design under 20nm node. + +**WARN: (IMPPP-2030): Layer M7 allows on grid right way wires only. Snap wire center to routing grid automatically. +initialize fgc environment ... done +Starting stripe generation ... +**WARN: (IMPPP-358): The left edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The right edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The bottom edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The top edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +Non-Default Mode Option Settings : + -spacing_from_block 2.00 + -trim_antenna_back_to_shape stripe + -trim_antenna_max_distance 0.00 + -use_exact_spacing 1 + -preventive_color_opt false + -use_fgc true +Multi-CPU acceleration using 4 CPU(s). +*** Stripes and vias are being generated (current mem: 1149.391)*** + Generate VSS stripes and vias + Completing 10% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VSS stripes and vias are completed(total cpu time: 0:00:00.0, peak mem: 1149.391M) + Generate VDD stripes and vias + Completing 10% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VDD stripes and vias are completed(total cpu time: 0:00:00.0, peak mem: 1149.391M) +Stripe generation is complete. +add_stripes created 50 wires. +ViaGen created 1400 vias, deleted 0 via to avoid violation. ++--------+----------------+----------------+ +| Layer | Created | Deleted | ++--------+----------------+----------------+ +| V6 | 1400 | 0 | +| M7 | 50 | NA | ++--------+----------------+----------------+ +#% End add_stripes (date=12/14 21:49:21, total cpu=0:00:00.2, real=0:00:00.0, peak res=1008.0M, current mem=1008.0M) +@file(power_straps.tcl) 56: reset_db -category add_stripes +@file(power_straps.tcl) 57: set_db add_stripes_stacked_via_top_layer M8 +@file(power_straps.tcl) 58: set_db add_stripes_stacked_via_bottom_layer M7 +@file(power_straps.tcl) 59: set_db add_stripes_trim_antenna_back_to_shape {stripe} +The power planner will set stripe antenna targets to stripe. +@file(power_straps.tcl) 60: set_db add_stripes_spacing_from_block 2.000 +Global stripes will break 2.000000 user units from obstructed blocks. +@file(power_straps.tcl) 61: add_stripes -create_pins 0 -block_ring_bottom_layer_limit M8 -block_ring_top_layer_limit M7 -direction horizontal -layer M8 -nets {VSS VDD} -pad_core_ring_bottom_layer_limit M7 -set_to_set_distance 4.480 -spacing 0.480 -switch_layer_over_obs 0 -width 1.760 -area [get_db designs .core_bbox] -start [expr [lindex [lindex [get_db designs .core_bbox] 0] 1] + 3.760] +#% Begin add_stripes (date=12/14 21:49:21, mem=1008.0M) +set_db add_stripes_use_fgc 1 is set by default for this design under 20nm node. + +initialize fgc environment ... done +Starting stripe generation ... +**WARN: (IMPPP-358): The left edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The right edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The bottom edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The top edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +Non-Default Mode Option Settings : + -spacing_from_block 2.00 + -trim_antenna_back_to_shape stripe + -trim_antenna_max_distance 0.00 + -use_exact_spacing 1 + -preventive_color_opt false + -use_fgc true +Multi-CPU acceleration using 4 CPU(s). +Multi-CPU acceleration using 4 CPU(s). +*** Stripes and vias are being generated (current mem: 1149.391)*** + Generate VDD stripes and vias + Completing 10% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VDD stripes and vias are completed(total cpu time: 0:00:00.0, peak mem: 1149.391M) + Generate VSS stripes and vias + Completing 10% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VSS stripes and vias are completed(total cpu time: 0:00:00.1, peak mem: 1149.391M) +Stripe generation is complete. +add_stripes created 177 wires. +ViaGen created 4425 vias, deleted 0 via to avoid violation. ++--------+----------------+----------------+ +| Layer | Created | Deleted | ++--------+----------------+----------------+ +| V7 | 4425 | 0 | +| M8 | 177 | NA | ++--------+----------------+----------------+ +#% End add_stripes (date=12/14 21:49:22, total cpu=0:00:00.3, real=0:00:01.0, peak res=1008.1M, current mem=1008.1M) +@file(power_straps.tcl) 65: reset_db -category add_stripes +@file(power_straps.tcl) 66: set_db add_stripes_stacked_via_top_layer M9 +@file(power_straps.tcl) 67: set_db add_stripes_stacked_via_bottom_layer M8 +@file(power_straps.tcl) 68: set_db add_stripes_trim_antenna_back_to_shape {stripe} +The power planner will set stripe antenna targets to stripe. +@file(power_straps.tcl) 69: set_db add_stripes_spacing_from_block 2.000 +Global stripes will break 2.000000 user units from obstructed blocks. +@file(power_straps.tcl) 70: add_stripes -create_pins 1 -block_ring_bottom_layer_limit M9 -block_ring_top_layer_limit M8 -direction vertical -layer M9 -nets {VSS VDD} -pad_core_ring_bottom_layer_limit M8 -set_to_set_distance 4.480 -spacing 0.480 -switch_layer_over_obs 0 -width 1.760 -area [get_db designs .core_bbox] -start [expr [lindex [lindex [get_db designs .core_bbox] 0] 0] + 3.760] +#% Begin add_stripes (date=12/14 21:49:22, mem=1008.1M) +set_db add_stripes_use_fgc 1 is set by default for this design under 20nm node. + +initialize fgc environment ... done +Starting stripe generation ... +**WARN: (IMPPP-358): The left edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The right edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The bottom edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +**WARN: (IMPPP-358): The top edge of the area you specified is out of design boundary and only stripes in design boundary will be generated. + Use option add_stripes_extend_to_closest_target {area_boundary} if stripes must be generated in specified area. +Non-Default Mode Option Settings : + -spacing_from_block 2.00 + -trim_antenna_back_to_shape stripe + -trim_antenna_max_distance 0.00 + -use_exact_spacing 1 + -preventive_color_opt false + -use_fgc true +Multi-CPU acceleration using 4 CPU(s). +Multi-CPU acceleration using 4 CPU(s). +*** Stripes and vias are being generated (current mem: 1149.391)*** + Generate VSS stripes and vias + Completing 10% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VSS stripes and vias are completed(total cpu time: 0:00:00.1, peak mem: 1149.391M) + Generate VDD stripes and vias + Completing 10% (cpu time: 0:00:00.1, peak mem: 1149.391M) + Completing 20% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 30% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 40% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 50% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 60% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 70% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 80% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 90% (cpu time: 0:00:00.0, peak mem: 1149.391M) + Completing 100% (cpu time: 0:00:00.0, peak mem: 1149.391M) + VDD stripes and vias are completed(total cpu time: 0:00:00.1, peak mem: 1149.391M) +Stripe generation is complete. +add_stripes created 154 wires. +ViaGen created 13629 vias, deleted 0 via to avoid violation. ++--------+----------------+----------------+ +| Layer | Created | Deleted | ++--------+----------------+----------------+ +| V8 | 13629 | 0 | +| M9 | 154 | NA | ++--------+----------------+----------------+ +#% End add_stripes (date=12/14 21:49:22, total cpu=0:00:00.4, real=0:00:00.0, peak res=1009.3M, current mem=1009.3M) +#@ End verbose source /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/power_straps.tcl +@file(par.tcl) 83: puts "write_db pre_place_pins" +write_db pre_place_pins +@file(par.tcl) 84: write_db pre_place_pins +#% Begin write_db save design ... (date=12/14 21:49:22, mem=1009.3M) +% Begin Save ccopt configuration ... (date=12/14 21:49:22, mem=1009.3M) +% End Save ccopt configuration ... (date=12/14 21:49:22, total cpu=0:00:00.0, real=0:00:00.0, peak res=1009.4M, current mem=1009.4M) +% Begin Save netlist data ... (date=12/14 21:49:22, mem=1009.4M) +Writing Binary DB to pre_place_pins/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 21:49:22, total cpu=0:00:00.0, real=0:00:00.0, peak res=1019.5M, current mem=1019.5M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file pre_place_pins/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 21:49:22, mem=1019.5M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 21:49:22, total cpu=0:00:00.0, real=0:00:00.0, peak res=1019.5M, current mem=1019.5M) +2020/12/14 21:49:22 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:22 For more info, please run CheckSysConf in +2020/12/14 21:49:22 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:22 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 21:49:22, mem=1019.5M) +% End Save clock tree data ... (date=12/14 21:49:22, total cpu=0:00:00.0, real=0:00:00.0, peak res=1019.5M, current mem=1019.5M) +Saving preference file pre_place_pins/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 21:49:23 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:23 For more info, please run CheckSysConf in +Saving Drc markers ... +... No Drc file written since there is no markers found. +% Begin Save routing data ... (date=12/14 21:49:23, mem=1019.6M) +Saving route file ... +2020/12/14 21:49:23 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:23 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.0 real=0:00:00.0 mem=1171.5M) *** +% End Save routing data ... (date=12/14 21:49:23, total cpu=0:00:00.0, real=0:00:00.0, peak res=1020.6M, current mem=1020.6M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 21:49:23 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:23 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file pre_place_pins/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=1187.5M) *** +% Begin Save power constraints data ... (date=12/14 21:49:23, mem=1022.7M) +% End Save power constraints data ... (date=12/14 21:49:23, total cpu=0:00:00.0, real=0:00:00.0, peak res=1022.7M, current mem=1022.7M) +Saving preRoute extracted patterns in file 'pre_place_pins/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.00 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design pre_place_pins +#% End write_db save design ... (date=12/14 21:49:25, total cpu=0:00:01.4, real=0:00:03.0, peak res=1022.7M, current mem=1012.7M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 85: puts "ln -sfn pre_place_pins latest" +ln -sfn pre_place_pins latest +@file(par.tcl) 86: ln -sfn pre_place_pins latest +@file(par.tcl) 87: puts "set_db assign_pins_edit_in_batch true" +set_db assign_pins_edit_in_batch true +@file(par.tcl) 88: set_db assign_pins_edit_in_batch true +@file(par.tcl) 89: puts "edit_pin -fixed_pin -pin * -hinst riscv_top -pattern fill_optimised -layer { M5 M7 } -side bottom -start { 350 0 } -end { 0 0 } " +edit_pin -fixed_pin -pin * -hinst riscv_top -pattern fill_optimised -layer { M5 M7 } -side bottom -start { 350 0 } -end { 0 0 } +@file(par.tcl) 90: edit_pin -fixed_pin -pin * -hinst riscv_top -pattern fill_optimised -layer { M5 M7 } -side bottom -start { 350 0 } -end { 0 0 } +**WARN: (IMPTR-2104): Layer M10: Pitch=1280 is less than min width=640 + min spacing=32000. +**ERROR: (IMPTR-2101): Layer M10: Pitch=11520x9 is still less than min width=32000 + min spacing=640. +**WARN: (IMPTR-2108): For layer M10, the gaps of 1040 out of 1040 tracks are narrower than 8.160um (space 8.000 + width 0.160). +Type 'man IMPTR-2108' for more detail. + As a result, your trialRoute congestion could be incorrect. +Successfully spread [350] pins. +editPin : finished (cpu = 0:00:00.2 real = 0:00:00.0, mem = 1186.4M). +@file(par.tcl) 91: puts "set_db assign_pins_edit_in_batch false" +set_db assign_pins_edit_in_batch false +@file(par.tcl) 92: set_db assign_pins_edit_in_batch false +@file(par.tcl) 93: puts "write_db pre_place_opt_design" +write_db pre_place_opt_design +@file(par.tcl) 94: write_db pre_place_opt_design +#% Begin write_db save design ... (date=12/14 21:49:25, mem=1032.0M) +% Begin Save ccopt configuration ... (date=12/14 21:49:25, mem=1032.0M) +% End Save ccopt configuration ... (date=12/14 21:49:25, total cpu=0:00:00.0, real=0:00:00.0, peak res=1032.0M, current mem=1032.0M) +% Begin Save netlist data ... (date=12/14 21:49:25, mem=1032.0M) +Writing Binary DB to pre_place_opt_design/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 21:49:25, total cpu=0:00:00.1, real=0:00:00.0, peak res=1037.4M, current mem=1037.4M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file pre_place_opt_design/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 21:49:25, mem=1037.4M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 21:49:26, total cpu=0:00:00.0, real=0:00:00.0, peak res=1037.4M, current mem=1037.4M) +2020/12/14 21:49:26 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:26 For more info, please run CheckSysConf in +2020/12/14 21:49:26 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:26 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 21:49:26, mem=1037.4M) +% End Save clock tree data ... (date=12/14 21:49:26, total cpu=0:00:00.0, real=0:00:00.0, peak res=1037.4M, current mem=1037.4M) +Saving preference file pre_place_opt_design/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 21:49:26 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:26 For more info, please run CheckSysConf in +Saving Drc markers ... +... No Drc file written since there is no markers found. +% Begin Save routing data ... (date=12/14 21:49:26, mem=1037.5M) +Saving route file ... +2020/12/14 21:49:26 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:26 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.0 real=0:00:00.0 mem=1210.5M) *** +% End Save routing data ... (date=12/14 21:49:26, total cpu=0:00:00.0, real=0:00:00.0, peak res=1038.4M, current mem=1038.4M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 21:49:26 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:49:26 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file pre_place_opt_design/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=1226.5M) *** +% Begin Save power constraints data ... (date=12/14 21:49:26, mem=1039.6M) +% End Save power constraints data ... (date=12/14 21:49:26, total cpu=0:00:00.0, real=0:00:00.0, peak res=1039.6M, current mem=1039.6M) +Saving preRoute extracted patterns in file 'pre_place_opt_design/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.00 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design pre_place_opt_design +#% End write_db save design ... (date=12/14 21:49:28, total cpu=0:00:01.4, real=0:00:03.0, peak res=1039.6M, current mem=1022.3M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 95: puts "ln -sfn pre_place_opt_design latest" +ln -sfn pre_place_opt_design latest +@file(par.tcl) 96: ln -sfn pre_place_opt_design latest +@file(par.tcl) 97: puts "place_opt_design" +place_opt_design +@file(par.tcl) 98: place_opt_design +No user sequential activity specified, applying default sequential activity of "0.2" for Dynamic Power reporting. +'set_default_switching_activity' finished successfully. +*** Starting GigaPlace *** +**INFO: user set placement options +root: {} +**INFO: user set opt options +root: {} +#optDebug: fT-E +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +*** Start delete_buffer_trees *** +Multithreaded Timing Analysis is initialized with 4 threads + +Info: Detect buffers to remove automatically. +Analyzing netlist ... +Updating netlist +AAE DB initialization (MEM=1333.18 CPU=0:00:00.1 REAL=0:00:00.0) + +**WARN: (EMS-27): Message (IMPTS-17) has exceeded the current message display limit of 1. +To increase the message display limit, refer to the product command reference manual. +*summary: 403 instances (buffers/inverters) removed +*** Finish delete_buffer_trees (0:00:01.1) *** +Deleted 0 physical inst (cell - / prefix -). +Did not delete 2823 physical insts as they were marked preplaced. +Extracting standard cell pins and blockage ...... +Pin and blockage extraction finished +Extracting macro/IO cell pins and blockage ...... +Pin and blockage extraction finished +No user-set net weight. +Options: timingDriven clkGateAware ignoreScan pinGuide congEffort=auto gpeffort=medium +Scan chains were not defined. +#std cell=12111 (2823 fixed + 9288 movable) #block=4 (0 floating + 4 preplaced) +#ioInst=0 #net=8663 #term=31115 #term/net=3.59, #fixedIo=0, #floatIo=0, #fixedPin=349, #floatPin=0 +stdCell: 12111 single + 0 double + 0 multi +Total standard cell length = 16.6851 (mm), area = 0.0180 (mm^2) +Average module density = 0.176. +Density for the design = 0.176. + = stdcell_area 71600 sites (16703 um^2) / alloc_area 406066 sites (94727 um^2). +Pin Density = 0.05191. + = total # of pins 31115 / total area 599400. +Identified 1064 spare or floating instances, with no clusters. + +Enabling multi-CPU acceleration with 4 CPU(s) for placement +=== lastAutoLevel = 10 +Clock gating cells determined by native netlist tracing. +Iteration 1: Total net bbox = 2.075e+05 (8.63e+04 1.21e+05) + Est. stn bbox = 2.166e+05 (8.97e+04 1.27e+05) + cpu = 0:00:00.2 real = 0:00:00.0 mem = 1531.8M +Iteration 2: Total net bbox = 2.075e+05 (8.63e+04 1.21e+05) + Est. stn bbox = 2.166e+05 (8.97e+04 1.27e+05) + cpu = 0:00:00.0 real = 0:00:00.0 mem = 1531.8M +Iteration 3: Total net bbox = 1.785e+05 (7.24e+04 1.06e+05) + Est. stn bbox = 1.922e+05 (7.83e+04 1.14e+05) + cpu = 0:00:37.6 real = 0:00:17.0 mem = 2037.2M +Iteration 4: Total net bbox = 1.838e+05 (8.04e+04 1.03e+05) + Est. stn bbox = 1.989e+05 (8.79e+04 1.11e+05) + cpu = 0:00:01.8 real = 0:00:00.0 mem = 2038.2M +Iteration 5: Total net bbox = 1.838e+05 (8.04e+04 1.03e+05) + Est. stn bbox = 1.989e+05 (8.79e+04 1.11e+05) + cpu = 0:00:00.0 real = 0:00:00.0 mem = 2038.2M +Iteration 6: Total net bbox = 2.264e+05 (9.10e+04 1.35e+05) + Est. stn bbox = 2.633e+05 (1.04e+05 1.59e+05) + cpu = 0:00:04.1 real = 0:00:02.0 mem = 2055.2M + +Iteration 7: Total net bbox = 2.276e+05 (9.20e+04 1.36e+05) + Est. stn bbox = 2.650e+05 (1.06e+05 1.59e+05) + cpu = 0:00:00.0 real = 0:00:00.0 mem = 2007.2M +Iteration 8: Total net bbox = 2.276e+05 (9.20e+04 1.36e+05) + Est. stn bbox = 2.650e+05 (1.06e+05 1.59e+05) + cpu = 0:00:00.0 real = 0:00:00.0 mem = 2007.2M +Iteration 9: Total net bbox = 2.356e+05 (9.61e+04 1.39e+05) + Est. stn bbox = 2.750e+05 (1.11e+05 1.64e+05) + cpu = 0:00:04.7 real = 0:00:03.0 mem = 2009.2M +Iteration 10: Total net bbox = 2.356e+05 (9.61e+04 1.39e+05) + Est. stn bbox = 2.750e+05 (1.11e+05 1.64e+05) + cpu = 0:00:00.0 real = 0:00:00.0 mem = 2009.2M +Iteration 11: Total net bbox = 2.367e+05 (9.74e+04 1.39e+05) + Est. stn bbox = 2.765e+05 (1.12e+05 1.64e+05) + cpu = 0:00:03.5 real = 0:00:01.0 mem = 2009.2M +Iteration 12: Total net bbox = 2.367e+05 (9.74e+04 1.39e+05) + Est. stn bbox = 2.765e+05 (1.12e+05 1.64e+05) + cpu = 0:00:00.0 real = 0:00:00.0 mem = 2009.2M +Iteration 13: Total net bbox = 2.395e+05 (9.88e+04 1.41e+05) + Est. stn bbox = 2.796e+05 (1.14e+05 1.65e+05) + cpu = 0:00:04.0 real = 0:00:02.0 mem = 2013.2M +Iteration 14: Total net bbox = 2.395e+05 (9.88e+04 1.41e+05) + Est. stn bbox = 2.796e+05 (1.14e+05 1.65e+05) + cpu = 0:00:00.0 real = 0:00:01.0 mem = 2013.2M +Iteration 15: Total net bbox = 2.452e+05 (1.02e+05 1.43e+05) + Est. stn bbox = 2.855e+05 (1.17e+05 1.68e+05) + cpu = 0:00:08.4 real = 0:00:04.0 mem = 2013.2M +Iteration 16: Total net bbox = 2.452e+05 (1.02e+05 1.43e+05) + Est. stn bbox = 2.855e+05 (1.17e+05 1.68e+05) + cpu = 0:00:00.0 real = 0:00:00.0 mem = 2013.2M +Finished Global Placement (cpu=0:01:05, real=0:00:31.0, mem=2013.2M) +0 delay mode for cte disabled. +*** Free Virtual Timing Model ...(mem=1949.2M) +SKP cleared! +Info: 43 clock gating cells identified, 43 (on average) moved 344/8 +net ignore based on current view = 0 +**WARN: (IMPSP-9025): No scan chain specified/traced. +Type 'man IMPSP-9025' for more detail. +*** Starting place_detail (0:02:20 mem=1703.6M) *** +Total net bbox length = 2.452e+05 (1.020e+05 1.432e+05) (ext = 3.984e+04) +Move report: Detail placement moves 9288 insts, mean move: 0.98 um, max move: 27.62 um + Max move on inst (cpu/tie_0_cell113): (164.44, 92.62) --> (191.81, 92.88) + Runtime: CPU: 0:00:01.5 REAL: 0:00:01.0 MEM: 1703.6MB +Summary Report: +Instances move: 9288 (out of 9288 movable) +Instances flipped: 0 +Mean displacement: 0.98 um +Max displacement: 27.62 um (Instance: cpu/tie_0_cell113) (164.443, 92.625) -> (191.808, 92.88) + Length: 3 sites, height: 1 rows, site name: coreSite, cell type: TIELOx1_ASAP7_75t_SL +Total net bbox length = 2.401e+05 (9.687e+04 1.432e+05) (ext = 3.977e+04) +Runtime: CPU: 0:00:01.5 REAL: 0:00:01.0 MEM: 1703.6MB +*** Finished place_detail (0:02:21 mem=1703.6M) *** +*** Finished Initial Placement (cpu=0:01:08, real=0:00:33.0, mem=1703.6M) *** +powerDomain AO: bins with density > 0.750 = 25.80 % ( 315 / 1221 ) +UM: flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: final + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: global_place + +Starting congestion repair ... +[NR-eGR] honorMsvRouteConstraint: false +[NR-eGR] honorClockSpecNDR : 0 +[NR-eGR] minRouteLayer : 2 +[NR-eGR] maxRouteLayer : 7 +[NR-eGR] numTracksPerClockWire : 0 +[NR-eGR] M1 has no routable track +[NR-eGR] M2 has non-uniform track structures +[NR-eGR] M3 has single uniform track structure +[NR-eGR] M4 has single uniform track structure +[NR-eGR] M5 has single uniform track structure +[NR-eGR] M6 has single uniform track structure +[NR-eGR] M7 has single uniform track structure +[NR-eGR] Read 53034 PG shapes in 0.010 seconds + +[NR-eGR] numRoutingBlks=0 numInstBlks=2388 numPGBlocks=53034 numBumpBlks=0 numBoundaryFakeBlks=0 +[NR-eGR] Num Prerouted Nets = 0 Num Prerouted Wires = 0 +[NR-eGR] Read numTotalNets=8663 numIgnoredNets=0 +[NR-eGR] There are 44 clock nets ( 0 with NDR ). +[NR-eGR] ============ Routing rule table ============ +[NR-eGR] Rule id: 0 Nets: 8663 +[NR-eGR] ======================================== +[NR-eGR] +[NR-eGR] Layer group 1: route 8663 net(s) in layer range [2, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.11% H + 0.43% V. EstWL: 2.744032e+05um +[NR-eGR] +[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded) +[NR-eGR] OverCon OverCon OverCon +[NR-eGR] #Gcell #Gcell #Gcell %Gcell +[NR-eGR] Layer (1-2) (3-4) (5-6) OverCon +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] M1 (1) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M2 (2) 258( 0.29%) 21( 0.02%) 3( 0.00%) ( 0.32%) +[NR-eGR] M3 (3) 1262( 1.41%) 81( 0.09%) 2( 0.00%) ( 1.50%) +[NR-eGR] M4 (4) 74( 0.07%) 0( 0.00%) 0( 0.00%) ( 0.07%) +[NR-eGR] M5 (5) 61( 0.06%) 0( 0.00%) 0( 0.00%) ( 0.06%) +[NR-eGR] M6 (6) 5( 0.01%) 0( 0.00%) 0( 0.00%) ( 0.01%) +[NR-eGR] M7 (7) 1( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] Total 1661( 0.29%) 102( 0.02%) 5( 0.00%) ( 0.31%) +[NR-eGR] +[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.04% H + 0.31% V +[NR-eGR] Overflow after earlyGlobalRoute 0.05% H + 0.38% V +Early Global Route congestion estimation runtime: 0.37 seconds, mem = 1708.5M +Local HotSpot Analysis: normalized max congestion hotspot area = 1.84, normalized total congestion hotspot area = 6.56 (area is in unit of 4 std-cell row bins) + +=== incrementalPlace Internal Loop 1 === +Skipped repairing congestion. +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] M1 (1F) length: 0.000000e+00um, number of vias: 29980 +[NR-eGR] M2 (2H) length: 6.332933e+04um, number of vias: 45858 +[NR-eGR] M3 (3V) length: 8.224681e+04um, number of vias: 8830 +[NR-eGR] M4 (4H) length: 4.108540e+04um, number of vias: 6182 +[NR-eGR] M5 (5V) length: 4.571195e+04um, number of vias: 1864 +[NR-eGR] M6 (6H) length: 1.876234e+04um, number of vias: 949 +[NR-eGR] M7 (7V) length: 3.016488e+04um, number of vias: 0 +[NR-eGR] Total length: 2.813007e+05um, number of vias: 93663 +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] Total eGR-routed clock nets wire length: 1.748141e+04um +[NR-eGR] -------------------------------------------------------------------------- +Early Global Route wiring runtime: 0.31 seconds, mem = 1703.3M +End of congRepair (cpu=0:00:00.7, real=0:00:01.0) +***** Total cpu 0:1:11 +***** Total real time 0:0:35 +**place_design ... cpu = 0: 1:11, real = 0: 0:35, mem = 1703.3M ** + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: final + + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: 143.21 92 place_design +**INFO: set_db design_flow_effort standard -> setting 'set_db opt_all_end_points true' for the duration of this command. +Enable N7 maxLocalDensity: 0.92 +[GPS-MSV] CPF Flow. Number of Power Domains: 1 +[GPS-MSV] Power Domain 'AO' (tag=1) Default +GigaOpt running with 4 threads. +**WARN: (IMPOPT-3564): The following cells are set dont_use temporarily by the tool because there are no rows defined for their technology site, or they are not placeable in any power domain. To avoid this message, review the create_floorplan, msv setting, the library setting or set manualy those cells as dont_use. + Cell DECAPx10_ASAP7_75t_L, site coreSite. + Cell DECAPx10_ASAP7_75t_R, site coreSite. + Cell DECAPx10_ASAP7_75t_SL, site coreSite. + Cell DECAPx10_ASAP7_75t_SRAM, site coreSite. + Cell DECAPx1_ASAP7_75t_L, site coreSite. + Cell DECAPx1_ASAP7_75t_R, site coreSite. + Cell DECAPx1_ASAP7_75t_SL, site coreSite. + Cell DECAPx1_ASAP7_75t_SRAM, site coreSite. + Cell DECAPx2_ASAP7_75t_L, site coreSite. + Cell DECAPx2_ASAP7_75t_R, site coreSite. + Cell DECAPx2_ASAP7_75t_SL, site coreSite. + Cell DECAPx2_ASAP7_75t_SRAM, site coreSite. + Cell DECAPx4_ASAP7_75t_L, site coreSite. + Cell DECAPx4_ASAP7_75t_R, site coreSite. + Cell DECAPx4_ASAP7_75t_SL, site coreSite. + Cell DECAPx4_ASAP7_75t_SRAM, site coreSite. + Cell DECAPx6_ASAP7_75t_L, site coreSite. + Cell DECAPx6_ASAP7_75t_R, site coreSite. + Cell DECAPx6_ASAP7_75t_SL, site coreSite. + Cell DECAPx6_ASAP7_75t_SRAM, site coreSite. + ... + Reporting only the 20 first cells found... +. +Updating RC grid for preRoute extraction ... +Initializing multi-corner resistance tables ... +Setting timing_disable_library_data_to_data_checks to 'true'. +Setting timing_disable_user_data_to_data_checks to 'true'. +**opt_design ... cpu = 0:00:00, real = 0:00:00, mem = 1220.4M, totSessionCpu=0:02:26 ** +*** opt_design -pre_cts *** +DRC Margin: user margin 0.0; extra margin 0.2 +Setup Target Slack: user slack 0; extra slack 0.0 +Hold Target Slack: user slack 0 +**WARN: (IMPOPT-3195): Analysis mode has changed. +Type 'man IMPOPT-3195' for more detail. +PVT_0P77V_0C.hold_set PVT_0P63V_100C.setup_set +[NR-eGR] Started earlyGlobalRoute kernel +[NR-eGR] Initial Peak syMemory usage = 1709.3 MB +[NR-eGR] honorMsvRouteConstraint: false +[NR-eGR] honorClockSpecNDR : 0 +[NR-eGR] minRouteLayer : 2 +[NR-eGR] maxRouteLayer : 7 +[NR-eGR] numTracksPerClockWire : 0 +[NR-eGR] M1 has no routable track +[NR-eGR] M2 has non-uniform track structures +[NR-eGR] M3 has single uniform track structure +[NR-eGR] M4 has single uniform track structure +[NR-eGR] M5 has single uniform track structure +[NR-eGR] M6 has single uniform track structure +[NR-eGR] M7 has single uniform track structure +[NR-eGR] Read 53034 PG shapes in 0.010 seconds + +[NR-eGR] numRoutingBlks=0 numInstBlks=2388 numPGBlocks=53034 numBumpBlks=0 numBoundaryFakeBlks=0 +[NR-eGR] Num Prerouted Nets = 0 Num Prerouted Wires = 0 +[NR-eGR] Read numTotalNets=8663 numIgnoredNets=0 +[NR-eGR] There are 44 clock nets ( 0 with NDR ). +[NR-eGR] ============ Routing rule table ============ +[NR-eGR] Rule id: 0 Nets: 8663 +[NR-eGR] ======================================== +[NR-eGR] +[NR-eGR] Layer group 1: route 8663 net(s) in layer range [2, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.11% H + 0.39% V. EstWL: 2.767748e+05um +[NR-eGR] +[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded) +[NR-eGR] OverCon OverCon OverCon +[NR-eGR] #Gcell #Gcell #Gcell %Gcell +[NR-eGR] Layer (1-2) (3-4) (5-6) OverCon +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] M1 (1) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M2 (2) 211( 0.24%) 25( 0.03%) 0( 0.00%) ( 0.26%) +[NR-eGR] M3 (3) 1207( 1.35%) 75( 0.08%) 10( 0.01%) ( 1.44%) +[NR-eGR] M4 (4) 80( 0.08%) 1( 0.00%) 0( 0.00%) ( 0.08%) +[NR-eGR] M5 (5) 77( 0.08%) 0( 0.00%) 0( 0.00%) ( 0.08%) +[NR-eGR] M6 (6) 10( 0.01%) 0( 0.00%) 0( 0.00%) ( 0.01%) +[NR-eGR] M7 (7) 6( 0.01%) 0( 0.00%) 0( 0.00%) ( 0.01%) +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] Total 1591( 0.28%) 101( 0.02%) 10( 0.00%) ( 0.30%) +[NR-eGR] +[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.04% H + 0.28% V +[NR-eGR] Overflow after earlyGlobalRoute 0.04% H + 0.33% V +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] M1 (1F) length: 0.000000e+00um, number of vias: 29980 +[NR-eGR] M2 (2H) length: 6.293093e+04um, number of vias: 45938 +[NR-eGR] M3 (3V) length: 8.330006e+04um, number of vias: 8915 +[NR-eGR] M4 (4H) length: 4.099705e+04um, number of vias: 6227 +[NR-eGR] M5 (5V) length: 4.676512e+04um, number of vias: 1865 +[NR-eGR] M6 (6H) length: 1.982246e+04um, number of vias: 949 +[NR-eGR] M7 (7V) length: 2.992613e+04um, number of vias: 0 +[NR-eGR] Total length: 2.837418e+05um, number of vias: 93874 +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] Total eGR-routed clock nets wire length: 1.826972e+04um +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] End Peak syMemory usage = 1709.4 MB +[NR-eGR] Early Global Router Kernel+IO runtime : 0.72 seconds +Updating RC grid for preRoute extraction ... +Initializing multi-corner resistance tables ... +Extraction called for design 'riscv_top' of instances=12115 and nets=9877 using extraction engine 'pre_route' . +pre_route RC Extraction called for design riscv_top. +RC Extraction called in multi-corner(2) mode. +RCMode: PreRoute + RC Corner Indexes 0 1 +Capacitance Scaling Factor : 1.00000 1.00000 +Resistance Scaling Factor : 1.00000 1.00000 +Clock Cap. Scaling Factor : 1.00000 1.00000 +Clock Res. Scaling Factor : 1.00000 1.00000 +Shrink Factor : 1.00000 +PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets. +Using Quantus QRC technology file ... +Updating RC grid for preRoute extraction ... +Initializing multi-corner resistance tables ... +PreRoute RC Extraction DONE (CPU Time: 0:00:00.2 Real Time: 0:00:00.0 MEM: 1709.445M) +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +**WARN: (EMS-27): Message (IMPTS-17) has exceeded the current message display limit of 1. +To increase the message display limit, refer to the product command reference manual. +################################################################################# +# Design Stage: PreRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: No SPEF/RCDB +# Signoff Settings: SI Off +################################################################################# +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=1773.35) +Total number of fetched objects 10100 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +End delay calculation. (MEM=2122.47 CPU=0:00:04.5 REAL=0:00:02.0) +End delay calculation (fullDC). (MEM=2066.77 CPU=0:00:06.0 REAL=0:00:03.0) +*** Done Building Timing Graph (cpu=0:00:07.3 real=0:00:04.0 totSessionCpu=0:02:36 mem=2066.8M) + +------------------------------------------------------------ + Initial Summary +------------------------------------------------------------ + +Setup views included: + PVT_0P63V_100C.setup_view + ++--------------------+---------+ +| Setup mode | all | ++--------------------+---------+ +| WNS (ns):| -12.369 | +| TNS (ns):| -85.403 | +| Violating Paths:| 818 | +| All Paths:| 1344 | ++--------------------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 216 (216) | -1.001 | 216 (216) | +| max_tran | 406 (2299) | -43.533 | 663 (2556) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 16.913% +------------------------------------------------------------ +**opt_design ... cpu = 0:00:10, real = 0:00:07, mem = 1230.3M, totSessionCpu=0:02:36 ** +** INFO : this run is activating medium effort placeOptDesign flow +*** Starting optimizing excluded clock nets MEM= 1775.1M) *** +*info: No excluded clock nets to be optimized. +*** Finished optimizing excluded clock nets (CPU Time= 0:00:00.0 MEM= 1775.1M) *** +The useful skew maximum allowed delay is: 0.18 +Info: 44 clock nets excluded from IPO operation. + +Footprint cell information for calculating maxBufDist +*info: There are 18 candidate Buffer cells +*info: There are 20 candidate Inverter cells + + +Netlist preparation processing... +Removed 1064 instances +*info: Marking 0 isolation instances dont touch +*info: Marking 0 level shifter instances dont touch +Begin: GigaOpt high fanout net optimization +Info: 44 clock nets excluded from IPO operation. ++----------+---------+--------+--------+------------+--------+ +| Density | Commits | WNS | TNS | Real | Mem | ++----------+---------+--------+--------+------------+--------+ +| 16.16%| -| -12.369| -85.405| 0:00:00.0| 1931.5M| +| 16.16%| -| -12.369| -85.405| 0:00:00.0| 1947.5M| ++----------+---------+--------+--------+------------+--------+ + +*** Finish pre-CTS High Fanout Net Fixing (cpu=0:00:00.0 real=0:00:00.0 mem=1947.5M) *** +**** Begin NDR-Layer Usage Statistics **** +0 Ndr or Layer constraints added by optimization +**** End NDR-Layer Usage Statistics **** +End: GigaOpt high fanout net optimization +Begin: GigaOpt DRV Optimization +Info: 44 clock nets excluded from IPO operation. ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +| max-tran | max-cap | max-fanout | max-length | setup | | | | | | | ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +| nets | terms| wViol | nets | terms| wViol | nets | terms| nets | terms| WNS | TNS | #Buf | #Inv | #Resize|Density| Real | Mem | ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 747| 3009| -43.73| 220| 220| -1.00| 0| 0| 0| 0| -12.37| -85.40| 0| 0| 0| 16.16| | | +| 247| 424| -12.08| 209| 209| -0.97| 0| 0| 0| 0| -0.39| -18.55| 365| 0| 200| 17.80| 0:00:11.0| 2163.3M| +| 208| 242| -12.08| 208| 208| -0.97| 0| 0| 0| 0| -0.39| -18.55| 38| 0| 52| 17.94| 0:00:01.0| 2163.3M| ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +**** Begin NDR-Layer Usage Statistics **** +Layer 4 has 39 constrained nets +**** End NDR-Layer Usage Statistics **** + + +======================================================================= + Reasons for remaining drv violations +======================================================================= +*info: Total 162 net(s) have violations which can't be fixed by DRV optimization. + +MultiBuffering failure reasons +------------------------------------------------ +*info: 162 net(s): Could not be fixed because there is no usable buffer or delay cell for buffering. + +*info: Total 47 net(s) were new nets created by previous iteration of DRV buffering. Further DRV fixing might remove some violations. + + +*** Finish DRV Fixing (cpu=0:00:40.3 real=0:00:12.0 mem=2163.3M) *** + +GigaOpt DRV: restore maxLocalDensity to dbgIPOMaxLocalDensity=0.92, optModeMaxLocDen=$0.92 +End: GigaOpt DRV Optimization +**opt_design ... cpu = 0:00:59, real = 0:00:26, mem = 1407.4M, totSessionCpu=0:03:26 ** + +Active setup views: + PVT_0P63V_100C.setup_view + Dominating endpoints: 0 + Dominating TNS: -0.000 + +Begin: GigaOpt Global Optimization +*info: use new DP (enabled) +Global Opt: maxLocalDensity 1.2 (from dbgIPOMaxLocalDensity=0.92, optModeMaxLocDen=0.92) +Info: 44 clock nets excluded from IPO operation. +*info: 44 clock nets excluded +*info: 2 special nets excluded. +*info: 1131 no-driver nets excluded. +** GigaOpt Global Opt WNS Slack -0.389 TNS Slack -18.550 ++--------+--------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| WNS | TNS | Density | Real | Mem | Worst View |Pathgroup| End Point | ++--------+--------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| -0.389| -18.550| 17.94%| 0:00:00.0| 1958.7M|PVT_0P63V_100C.setup_view| default| mem/dcache/STATE_reg[1]/D | +| -0.287| -11.971| 18.24%| 0:00:03.0| 2238.0M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.168| -4.617| 18.37%| 0:00:03.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.137| -2.456| 18.44%| 0:00:02.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.100| -1.382| 18.49%| 0:00:02.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.060| -0.516| 18.53%| 0:00:02.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.056| -0.455| 18.57%| 0:00:02.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.049| -0.345| 18.58%| 0:00:00.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.045| -0.278| 18.60%| 0:00:01.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.035| -0.158| 18.59%| 0:00:02.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.035| -0.143| 18.60%| 0:00:01.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.035| -0.143| 18.61%| 0:00:00.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.030| -0.119| 18.62%| 0:00:00.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.023| -0.077| 18.64%| 0:00:01.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.023| -0.077| 18.67%| 0:00:01.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.023| -0.075| 18.67%| 0:00:00.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.021| -0.057| 18.67%| 0:00:00.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.020| -0.053| 18.68%| 0:00:01.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.019| -0.052| 18.69%| 0:00:00.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.019| -0.050| 18.70%| 0:00:01.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.019| -0.049| 18.70%| 0:00:00.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.017| -0.040| 18.70%| 0:00:01.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.013| -0.029| 18.71%| 0:00:00.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.013| -0.029| 18.71%| 0:00:00.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.012| -0.028| 18.71%| 0:00:00.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | +| -0.010| -0.020| 18.71%| 0:00:01.0| 2257.1M|PVT_0P63V_100C.setup_view| default| cpu/stage1/pcreg/register_reg[31]/D | ++--------+--------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ + +*** Finish pre-CTS Global Setup Fixing (cpu=0:01:13 real=0:00:24.0 mem=2257.1M) *** + +*** Finish pre-CTS Setup Fixing (cpu=0:01:13 real=0:00:24.0 mem=2257.1M) *** +**** Begin NDR-Layer Usage Statistics **** +Layer 4 has 333 constrained nets +Layer 6 has 3 constrained nets +**** End NDR-Layer Usage Statistics **** +** GigaOpt Global Opt End WNS Slack -0.010 TNS Slack -0.020 +Global Opt: restore maxLocalDensity to 0.92 +End: GigaOpt Global Optimization +*** Timing NOT met, worst failing slack is -0.010 +*** Check timing (0:00:00.0) +Info: 44 clock nets excluded from IPO operation. +Begin: Area Reclaim Optimization +Reclaim Optimization WNS Slack -0.010 TNS Slack -0.020 Density 18.71 ++----------+---------+--------+--------+------------+--------+ +| Density | Commits | WNS | TNS | Real | Mem | ++----------+---------+--------+--------+------------+--------+ +| 18.71%| -| -0.010| -0.020| 0:00:00.0| 1962.0M| +| 18.71%| 1| -0.010| -0.020| 0:00:01.0| 2116.1M| +| 18.71%| 250| -0.010| -0.020| 0:00:02.0| 2154.3M| +| 18.52%| 137| -0.009| -0.016| 0:00:01.0| 2173.4M| +| 18.48%| 36| -0.009| -0.016| 0:00:00.0| 2173.4M| +| 18.13%| 623| 0.000| 0.000| 0:00:06.0| 2154.3M| +| 18.08%| 132| -0.000| -0.000| 0:00:01.0| 2154.3M| +| 18.08%| 26| -0.000| -0.000| 0:00:00.0| 2154.3M| +| 18.07%| 7| -0.000| -0.000| 0:00:01.0| 2154.3M| +| 18.07%| 2| -0.000| -0.000| 0:00:00.0| 2154.3M| +| 18.07%| 40| -0.000| -0.000| 0:00:00.0| 2154.3M| ++----------+---------+--------+--------+------------+--------+ +Reclaim Optimization End WNS Slack -0.000 TNS Slack -0.000 Density 18.07 +**** Begin NDR-Layer Usage Statistics **** +Layer 4 has 42 constrained nets +Layer 6 has 2 constrained nets +**** End NDR-Layer Usage Statistics **** +** Finished Core Area Reclaim Optimization (cpu = 0:00:30.6) (real = 0:00:13.0) ** +Executing incremental physical updates +Executing incremental physical updates +*** Finished Area Reclaim Optimization (cpu=0:00:31, real=0:00:13, mem=1854.00M, totSessionCpu=0:05:17). +**WARN: (IMPSP-9025): No scan chain specified/traced. +Type 'man IMPSP-9025' for more detail. + +*** Start incrementalPlace *** +[NR-eGR] honorMsvRouteConstraint: false +[NR-eGR] honorClockSpecNDR : 0 +[NR-eGR] minRouteLayer : 2 +[NR-eGR] maxRouteLayer : 7 +[NR-eGR] numTracksPerClockWire : 0 +[NR-eGR] M1 has no routable track +[NR-eGR] M2 has non-uniform track structures +[NR-eGR] M3 has single uniform track structure +[NR-eGR] M4 has single uniform track structure +[NR-eGR] M5 has single uniform track structure +[NR-eGR] M6 has single uniform track structure +[NR-eGR] M7 has single uniform track structure +[NR-eGR] Read 53034 PG shapes in 0.010 seconds + +[NR-eGR] numRoutingBlks=0 numInstBlks=2389 numPGBlocks=53034 numBumpBlks=0 numBoundaryFakeBlks=0 +[NR-eGR] Num Prerouted Nets = 0 Num Prerouted Wires = 0 +[NR-eGR] Read numTotalNets=9392 numIgnoredNets=0 +[NR-eGR] There are 44 clock nets ( 0 with NDR ). +[NR-eGR] ============ Routing rule table ============ +[NR-eGR] Rule id: 0 Nets: 9371 +[NR-eGR] ======================================== +[NR-eGR] +[NR-eGR] Layer group 1: route 43 net(s) in layer range [4, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.00% H + 0.00% V. EstWL: 5.382720e+03um +[NR-eGR] +[NR-eGR] Layer group 2: route 9328 net(s) in layer range [2, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 2: 0.07% H + 0.35% V. EstWL: 2.717701e+05um +[NR-eGR] +[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded) +[NR-eGR] OverCon OverCon +[NR-eGR] #Gcell #Gcell %Gcell +[NR-eGR] Layer (1) (4) OverCon +[NR-eGR] --------------------------------------------------------------- +[NR-eGR] M1 (1) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M2 (2) 232( 0.26%) 23( 0.03%) ( 0.29%) +[NR-eGR] M3 (3) 1279( 1.43%) 76( 0.08%) ( 1.51%) +[NR-eGR] M4 (4) 94( 0.09%) 3( 0.00%) ( 0.09%) +[NR-eGR] M5 (5) 59( 0.06%) 0( 0.00%) ( 0.06%) +[NR-eGR] M6 (6) 21( 0.02%) 0( 0.00%) ( 0.02%) +[NR-eGR] M7 (7) 1( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] --------------------------------------------------------------- +[NR-eGR] Total 1686( 0.29%) 102( 0.02%) ( 0.31%) +[NR-eGR] +[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.04% H + 0.28% V +[NR-eGR] Overflow after earlyGlobalRoute 0.04% H + 0.32% V +Early Global Route congestion estimation runtime: 0.41 seconds, mem = 1861.0M +Local HotSpot Analysis: normalized max congestion hotspot area = 0.79, normalized total congestion hotspot area = 2.89 (area is in unit of 4 std-cell row bins) + +=== incrementalPlace Internal Loop 1 === +################################################################################# +# Design Stage: PreRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: No SPEF/RCDB +# Signoff Settings: SI Off +################################################################################# +SKP inited! +Iteration 8: Total net bbox = 2.476e+05 (9.93e+04 1.48e+05) + Est. stn bbox = 2.852e+05 (1.12e+05 1.73e+05) + cpu = 0:00:02.6 real = 0:00:01.0 mem = 2295.6M +Iteration 9: Total net bbox = 2.506e+05 (1.01e+05 1.49e+05) + Est. stn bbox = 2.884e+05 (1.15e+05 1.74e+05) + cpu = 0:00:03.6 real = 0:00:02.0 mem = 2283.6M +Iteration 10: Total net bbox = 2.508e+05 (1.02e+05 1.49e+05) + Est. stn bbox = 2.882e+05 (1.15e+05 1.73e+05) + cpu = 0:00:02.3 real = 0:00:01.0 mem = 2290.2M +Iteration 11: Total net bbox = 2.529e+05 (1.02e+05 1.51e+05) + Est. stn bbox = 2.904e+05 (1.16e+05 1.75e+05) + cpu = 0:00:02.0 real = 0:00:01.0 mem = 2295.2M +Iteration 12: Total net bbox = 2.547e+05 (1.04e+05 1.51e+05) + Est. stn bbox = 2.924e+05 (1.17e+05 1.75e+05) + cpu = 0:00:04.1 real = 0:00:02.0 mem = 2303.2M +0 delay mode for cte disabled. +*** Free Virtual Timing Model ...(mem=2191.2M) +SKP cleared! + +*** Starting place_detail (0:06:30 mem=1982.1M) *** +Total net bbox length = 2.556e+05 (1.047e+05 1.509e+05) (ext = 4.061e+04) +Move report: Detail placement moves 8953 insts, mean move: 0.59 um, max move: 18.97 um + Max move on inst (mem/icache/FE_OFC316_n_346): (87.04, 242.09) --> (105.84, 241.92) + Runtime: CPU: 0:00:01.3 REAL: 0:00:01.0 MEM: 1982.1MB +Summary Report: +Instances move: 8953 (out of 8953 movable) +Instances flipped: 0 +Mean displacement: 0.59 um +Max displacement: 18.97 um (Instance: mem/icache/FE_OFC316_n_346) (87.0375, 242.09) -> (105.84, 241.92) + Length: 18 sites, height: 1 rows, site name: coreSite, cell type: BUFx12f_ASAP7_75t_SL +Total net bbox length = 2.504e+05 (9.915e+04 1.512e+05) (ext = 4.044e+04) +Runtime: CPU: 0:00:01.3 REAL: 0:00:01.0 MEM: 1982.1MB +*** Finished place_detail (0:06:31 mem=1982.1M) *** +[NR-eGR] honorMsvRouteConstraint: false +[NR-eGR] honorClockSpecNDR : 0 +[NR-eGR] minRouteLayer : 2 +[NR-eGR] maxRouteLayer : 7 +[NR-eGR] numTracksPerClockWire : 0 +[NR-eGR] M1 has no routable track +[NR-eGR] M2 has non-uniform track structures +[NR-eGR] M3 has single uniform track structure +[NR-eGR] M4 has single uniform track structure +[NR-eGR] M5 has single uniform track structure +[NR-eGR] M6 has single uniform track structure +[NR-eGR] M7 has single uniform track structure +[NR-eGR] Read 53034 PG shapes in 0.010 seconds + +[NR-eGR] numRoutingBlks=0 numInstBlks=2389 numPGBlocks=53034 numBumpBlks=0 numBoundaryFakeBlks=0 +[NR-eGR] Num Prerouted Nets = 0 Num Prerouted Wires = 0 +[NR-eGR] Read numTotalNets=9392 numIgnoredNets=0 +[NR-eGR] There are 44 clock nets ( 0 with NDR ). +[NR-eGR] ============ Routing rule table ============ +[NR-eGR] Rule id: 0 Nets: 9392 +[NR-eGR] ======================================== +[NR-eGR] +[NR-eGR] Layer group 1: route 43 net(s) in layer range [4, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.00% H + 0.00% V. EstWL: 5.760720e+03um +[NR-eGR] +[NR-eGR] Layer group 2: route 9349 net(s) in layer range [2, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 2: 0.03% H + 0.31% V. EstWL: 2.766107e+05um +[NR-eGR] +[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded) +[NR-eGR] OverCon OverCon OverCon +[NR-eGR] #Gcell #Gcell #Gcell %Gcell +[NR-eGR] Layer (1-2) (3-4) (5-5) OverCon +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] M1 (1) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M2 (2) 111( 0.12%) 4( 0.00%) 1( 0.00%) ( 0.13%) +[NR-eGR] M3 (3) 1139( 1.27%) 78( 0.09%) 0( 0.00%) ( 1.36%) +[NR-eGR] M4 (4) 77( 0.07%) 2( 0.00%) 0( 0.00%) ( 0.08%) +[NR-eGR] M5 (5) 49( 0.05%) 0( 0.00%) 0( 0.00%) ( 0.05%) +[NR-eGR] M6 (6) 17( 0.02%) 0( 0.00%) 0( 0.00%) ( 0.02%) +[NR-eGR] M7 (7) 15( 0.02%) 0( 0.00%) 0( 0.00%) ( 0.02%) +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] Total 1408( 0.24%) 84( 0.01%) 1( 0.00%) ( 0.26%) +[NR-eGR] +[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.01% H + 0.22% V +[NR-eGR] Overflow after earlyGlobalRoute 0.01% H + 0.27% V +Early Global Route congestion estimation runtime: 0.42 seconds, mem = 1982.1M +Local HotSpot Analysis: normalized max congestion hotspot area = 0.52, normalized total congestion hotspot area = 0.79 (area is in unit of 4 std-cell row bins) + +=== incrementalPlace Internal Loop 2 === +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] M1 (1F) length: 0.000000e+00um, number of vias: 31428 +[NR-eGR] M2 (2H) length: 6.548878e+04um, number of vias: 47681 +[NR-eGR] M3 (3V) length: 8.707460e+04um, number of vias: 8992 +[NR-eGR] M4 (4H) length: 3.854976e+04um, number of vias: 6704 +[NR-eGR] M5 (5V) length: 4.748915e+04um, number of vias: 1970 +[NR-eGR] M6 (6H) length: 2.065853e+04um, number of vias: 1094 +[NR-eGR] M7 (7V) length: 3.010604e+04um, number of vias: 0 +[NR-eGR] Total length: 2.893669e+05um, number of vias: 97869 +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] Total eGR-routed clock nets wire length: 1.811882e+04um +[NR-eGR] -------------------------------------------------------------------------- +Early Global Route wiring runtime: 0.33 seconds, mem = 1971.7M + +*** Finished incrementalPlace (cpu=0:01:15, real=0:00:33.0)*** +Start to check current routing status for nets... +All nets are already routed correctly. +End to check current routing status for nets (mem=1971.7M) +Extraction called for design 'riscv_top' of instances=11780 and nets=10607 using extraction engine 'pre_route' . +pre_route RC Extraction called for design riscv_top. +RC Extraction called in multi-corner(2) mode. +RCMode: PreRoute + RC Corner Indexes 0 1 +Capacitance Scaling Factor : 1.00000 1.00000 +Resistance Scaling Factor : 1.00000 1.00000 +Clock Cap. Scaling Factor : 1.00000 1.00000 +Clock Res. Scaling Factor : 1.00000 1.00000 +Shrink Factor : 1.00000 +PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets. +Using Quantus QRC technology file ... +Updating RC grid for preRoute extraction ... +Initializing multi-corner resistance tables ... +PreRoute RC Extraction DONE (CPU Time: 0:00:00.2 Real Time: 0:00:00.0 MEM: 1971.727M) +Compute RC Scale Done ... +**opt_design ... cpu = 0:04:07, real = 0:01:46, mem = 1328.7M, totSessionCpu=0:06:33 ** +################################################################################# +# Design Stage: PreRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: No SPEF/RCDB +# Signoff Settings: SI Off +################################################################################# +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=1982.26) +Total number of fetched objects 9729 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +End delay calculation. (MEM=2216.45 CPU=0:00:03.3 REAL=0:00:01.0) +End delay calculation (fullDC). (MEM=2216.45 CPU=0:00:04.2 REAL=0:00:01.0) +Begin: GigaOpt DRV Optimization +Info: 44 clock nets excluded from IPO operation. ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +| max-tran | max-cap | max-fanout | max-length | setup | | | | | | | ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +| nets | terms| wViol | nets | terms| wViol | nets | terms| nets | terms| WNS | TNS | #Buf | #Inv | #Resize|Density| Real | Mem | ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 301| 449| -12.14| 208| 208| -0.97| 0| 0| 0| 0| -0.04| -0.41| 0| 0| 0| 18.07| | | +| 207| 207| -5.08| 208| 208| -0.93| 0| 0| 0| 0| -0.04| -0.39| 240| 38| 117| 18.39| 0:00:02.0| 2329.9M| +| 42| 42| -5.08| 39| 39| -0.93| 0| 0| 0| 0| -0.04| -0.39| 32| 0| 176| 18.87| 0:00:01.0| 2333.9M| +| 6| 6| -5.08| 7| 7| -0.93| 0| 0| 0| 0| -0.04| -0.39| 5| 0| 32| 18.96| 0:00:00.0| 2333.9M| ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +**** Begin NDR-Layer Usage Statistics **** +Layer 4 has 76 constrained nets +Layer 6 has 2 constrained nets +**** End NDR-Layer Usage Statistics **** + + +======================================================================= + Reasons for remaining drv violations +======================================================================= +*info: Total 6 net(s) have violations which can't be fixed by DRV optimization. + +MultiBuffering failure reasons +------------------------------------------------ +*info: 1 net(s): Could not be fixed because the solution degraded timing. +*info: 5 net(s): Could not be fixed because there is no usable buffer or delay cell for buffering. + +*info: Total 1 net(s) were new nets created by previous iteration of DRV buffering. Further DRV fixing might remove some violations. + + +*** Finish DRV Fixing (cpu=0:00:09.7 real=0:00:03.0 mem=2333.9M) *** + +*** Starting place_detail (0:06:53 mem=2333.9M) *** +Total net bbox length = 2.510e+05 (9.975e+04 1.513e+05) (ext = 3.733e+04) +Move report: Detail placement moves 499 insts, mean move: 1.81 um, max move: 9.94 um + Max move on inst (FE_OFC1535_mem_req_data_mask_5): (201.53, 1.08) --> (196.99, 6.48) + Runtime: CPU: 0:00:00.4 REAL: 0:00:00.0 MEM: 2333.9MB +Summary Report: +Instances move: 499 (out of 9268 movable) +Instances flipped: 0 +Mean displacement: 1.81 um +Max displacement: 9.94 um (Instance: FE_OFC1535_mem_req_data_mask_5) (201.528, 1.08) -> (196.992, 6.48) + Length: 30 sites, height: 1 rows, site name: coreSite, cell type: BUFx24_ASAP7_75t_SL +Total net bbox length = 2.515e+05 (9.988e+04 1.516e+05) (ext = 3.757e+04) +Runtime: CPU: 0:00:00.4 REAL: 0:00:00.0 MEM: 2333.9MB +*** Finished place_detail (0:06:53 mem=2333.9M) *** +*** maximum move = 9.94 um *** +*** Finished re-routing un-routed nets (2333.9M) *** + +*** Finish Physical Update (cpu=0:00:00.8 real=0:00:01.0 mem=2333.9M) *** +End: GigaOpt DRV Optimization + +------------------------------------------------------------ + Summary (cpu=0.24min real=0.12min mem=2017.7M) +------------------------------------------------------------ + +Setup views included: + PVT_0P63V_100C.setup_view + ++--------------------+---------+ +| Setup mode | all | ++--------------------+---------+ +| WNS (ns):| -0.035 | +| TNS (ns):| -0.393 | +| Violating Paths:| 28 | +| All Paths:| 1344 | ++--------------------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 7 (7) | -0.909 | 7 (7) | +| max_tran | 6 (6) | -4.878 | 6 (6) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 19.879% +Routing Overflow: 0.01% H and 0.27% V +------------------------------------------------------------ +**opt_design ... cpu = 0:04:28, real = 0:01:55, mem = 1451.9M, totSessionCpu=0:06:54 ** +*** Timing NOT met, worst failing slack is -0.035 +*** Check timing (0:00:00.0) +Begin: GigaOpt Optimization in WNS mode +Info: 44 clock nets excluded from IPO operation. +*info: 44 clock nets excluded +*info: 2 special nets excluded. +*info: 1132 no-driver nets excluded. +** GigaOpt Optimizer WNS Slack -0.035 TNS Slack -0.393 Density 19.88 +Active Path Group: reg2cgate reg2reg ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| WNS | All WNS | TNS | All TNS | Density | Real | Mem | Worst View |Pathgroup| End Point | ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| -0.035| -0.035| -0.393| -0.393| 19.88%| 0:00:00.0| 2118.6M|PVT_0P63V_100C.setup_view| reg2reg| cpu/s1_to_s2_rs2/register_reg[8]/D | +| -0.014| -0.014| -0.055| -0.055| 19.90%| 0:00:03.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.013| -0.013| -0.048| -0.048| 19.90%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.012| -0.012| -0.046| -0.046| 19.90%| 0:00:01.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.011| -0.011| -0.038| -0.038| 19.90%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.011| -0.011| -0.038| -0.038| 19.90%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.010| -0.010| -0.035| -0.035| 19.90%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.009| -0.009| -0.024| -0.024| 19.91%| 0:00:01.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.008| -0.008| -0.023| -0.023| 19.91%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.008| -0.008| -0.020| -0.020| 19.91%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.008| -0.008| -0.019| -0.019| 19.91%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.007| -0.007| -0.017| -0.017| 19.91%| 0:00:01.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.007| -0.007| -0.015| -0.015| 19.91%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.006| -0.006| -0.014| -0.014| 19.92%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.005| -0.005| -0.009| -0.009| 19.92%| 0:00:01.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.004| -0.004| -0.006| -0.006| 19.92%| 0:00:01.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.003| -0.003| -0.004| -0.004| 19.93%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.002| -0.002| -0.003| -0.003| 19.93%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.002| -0.002| -0.003| -0.003| 19.93%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.001| -0.001| -0.001| -0.001| 19.93%| 0:00:01.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.001| -0.001| -0.001| -0.001| 19.94%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| 0.000| 0.000| 0.000| 0.000| 19.94%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| 0.001| 0.001| 0.000| 0.000| 19.94%| 0:00:01.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| 0.001| 0.001| 0.000| 0.000| 19.94%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| 0.001| 0.001| 0.000| 0.000| 19.94%| 0:00:00.0| 2426.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ + +*** Finish Core Optimize Step (cpu=0:00:22.9 real=0:00:10.0 mem=2426.9M) *** + +*** Finished Optimize Step Cumulative (cpu=0:00:22.9 real=0:00:10.0 mem=2426.9M) *** +** GigaOpt Optimizer WNS Slack 0.001 TNS Slack 0.000 Density 19.94 +*** Starting place_detail (0:07:26 mem=2426.9M) *** +Total net bbox length = 2.517e+05 (9.995e+04 1.517e+05) (ext = 3.757e+04) +Move report: Detail placement moves 37 insts, mean move: 0.78 um, max move: 2.16 um + Max move on inst (cpu/stage1/regfile/FE_RC_3_0): (110.59, 225.72) --> (112.75, 225.72) + Runtime: CPU: 0:00:00.3 REAL: 0:00:00.0 MEM: 2426.9MB +Summary Report: +Instances move: 37 (out of 9283 movable) +Instances flipped: 0 +Mean displacement: 0.78 um +Max displacement: 2.16 um (Instance: cpu/stage1/regfile/FE_RC_3_0) (110.592, 225.72) -> (112.752, 225.72) + Length: 10 sites, height: 1 rows, site name: coreSite, cell type: INVx8_ASAP7_75t_SL +Total net bbox length = 2.517e+05 (9.996e+04 1.517e+05) (ext = 3.757e+04) +Runtime: CPU: 0:00:00.3 REAL: 0:00:00.0 MEM: 2426.9MB +*** Finished place_detail (0:07:27 mem=2426.9M) *** +*** maximum move = 2.16 um *** +*** Finished re-routing un-routed nets (2426.9M) *** + +*** Finish Physical Update (cpu=0:00:00.7 real=0:00:00.0 mem=2426.9M) *** +** GigaOpt Optimizer WNS Slack 0.001 TNS Slack 0.000 Density 19.94 +**** Begin NDR-Layer Usage Statistics **** +Layer 4 has 124 constrained nets +Layer 6 has 2 constrained nets +**** End NDR-Layer Usage Statistics **** + +*** Finish pre-CTS Setup Fixing (cpu=0:00:26.1 real=0:00:11.0 mem=2426.9M) *** + +End: GigaOpt Optimization in WNS mode +*** Timing Is met +*** Check timing (0:00:00.0) +Info: 44 clock nets excluded from IPO operation. +Begin: Area Reclaim Optimization +Reclaim Optimization WNS Slack 0.000 TNS Slack 0.000 Density 19.94 ++----------+---------+--------+--------+------------+--------+ +| Density | Commits | WNS | TNS | Real | Mem | ++----------+---------+--------+--------+------------+--------+ +| 19.94%| -| 0.000| 0.000| 0:00:00.0| 2108.7M| +| 19.94%| 84| -0.000| -0.000| 0:00:01.0| 2299.5M| +| 19.73%| 91| -0.002| -0.002| 0:00:01.0| 2299.5M| +| 19.70%| 9| -0.002| -0.002| 0:00:00.0| 2299.5M| +| 19.30%| 347| -0.002| -0.002| 0:00:02.0| 2261.4M| +| 19.29%| 20| -0.002| -0.002| 0:00:00.0| 2261.4M| +| 19.29%| 1| -0.002| -0.002| 0:00:00.0| 2261.4M| +| 19.29%| 0| -0.002| -0.002| 0:00:00.0| 2261.4M| +| 19.29%| 2| -0.002| -0.002| 0:00:00.0| 2261.4M| ++----------+---------+--------+--------+------------+--------+ +Reclaim Optimization End WNS Slack -0.002 TNS Slack -0.002 Density 19.29 +**** Begin NDR-Layer Usage Statistics **** +Layer 4 has 42 constrained nets +**** End NDR-Layer Usage Statistics **** +** Finished Core Area Reclaim Optimization (cpu = 0:00:10.5) (real = 0:00:04.0) ** +*** Starting place_detail (0:07:38 mem=2261.4M) *** +Total net bbox length = 2.521e+05 (1.000e+05 1.520e+05) (ext = 3.758e+04) +Move report: Detail placement moves 0 insts, mean move: 0.00 um, max move: 0.00 um + Runtime: CPU: 0:00:00.2 REAL: 0:00:01.0 MEM: 2261.4MB +Summary Report: +Instances move: 0 (out of 9182 movable) +Instances flipped: 0 +Mean displacement: 0.00 um +Max displacement: 0.00 um +Total net bbox length = 2.521e+05 (1.000e+05 1.520e+05) (ext = 3.758e+04) +Runtime: CPU: 0:00:00.3 REAL: 0:00:01.0 MEM: 2261.4MB +*** Finished place_detail (0:07:38 mem=2261.4M) *** +*** maximum move = 0.00 um *** +*** Finished re-routing un-routed nets (2261.4M) *** + +*** Finish Physical Update (cpu=0:00:00.7 real=0:00:01.0 mem=2261.4M) *** +*** Finished Area Reclaim Optimization (cpu=0:00:11, real=0:00:05, mem=1999.24M, totSessionCpu=0:07:38). + +Active setup views: + PVT_0P63V_100C.setup_view + Dominating endpoints: 0 + Dominating TNS: -0.000 + +Extraction called for design 'riscv_top' of instances=12009 and nets=10836 using extraction engine 'pre_route' . +pre_route RC Extraction called for design riscv_top. +RC Extraction called in multi-corner(2) mode. +RCMode: PreRoute + RC Corner Indexes 0 1 +Capacitance Scaling Factor : 1.00000 1.00000 +Resistance Scaling Factor : 1.00000 1.00000 +Clock Cap. Scaling Factor : 1.00000 1.00000 +Clock Res. Scaling Factor : 1.00000 1.00000 +Shrink Factor : 1.00000 +PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets. +Using Quantus QRC technology file ... +Initializing multi-corner resistance tables ... +PreRoute RC Extraction DONE (CPU Time: 0:00:00.2 Real Time: 0:00:00.0 MEM: 1931.727M) +Skewing Data Summary (End_of_FINAL) +-------------------------------------------------- + Total skewed count:0 +-------------------------------------------------- +[NR-eGR] honorMsvRouteConstraint: false +[NR-eGR] honorClockSpecNDR : 0 +[NR-eGR] minRouteLayer : 2 +[NR-eGR] maxRouteLayer : 7 +[NR-eGR] numTracksPerClockWire : 0 +[NR-eGR] M1 has no routable track +[NR-eGR] M2 has non-uniform track structures +[NR-eGR] M3 has single uniform track structure +[NR-eGR] M4 has single uniform track structure +[NR-eGR] M5 has single uniform track structure +[NR-eGR] M6 has single uniform track structure +[NR-eGR] M7 has single uniform track structure +[NR-eGR] Read 53034 PG shapes in 0.010 seconds + +[NR-eGR] numRoutingBlks=0 numInstBlks=2389 numPGBlocks=53034 numBumpBlks=0 numBoundaryFakeBlks=0 +[NR-eGR] Num Prerouted Nets = 0 Num Prerouted Wires = 0 +[NR-eGR] Read numTotalNets=9621 numIgnoredNets=0 +[NR-eGR] There are 44 clock nets ( 0 with NDR ). +[NR-eGR] ============ Routing rule table ============ +[NR-eGR] Rule id: 0 Nets: 9621 +[NR-eGR] ======================================== +[NR-eGR] +[NR-eGR] Layer group 1: route 41 net(s) in layer range [4, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.00% H + 0.00% V. EstWL: 7.198200e+03um +[NR-eGR] +[NR-eGR] Layer group 2: route 9580 net(s) in layer range [2, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 2: 0.03% H + 0.27% V. EstWL: 2.764465e+05um +[NR-eGR] +[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded) +[NR-eGR] OverCon OverCon +[NR-eGR] #Gcell #Gcell %Gcell +[NR-eGR] Layer (1) (4) OverCon +[NR-eGR] --------------------------------------------------------------- +[NR-eGR] M1 (1) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M2 (2) 84( 0.09%) 1( 0.00%) ( 0.10%) +[NR-eGR] M3 (3) 1195( 1.33%) 71( 0.08%) ( 1.41%) +[NR-eGR] M4 (4) 82( 0.08%) 2( 0.00%) ( 0.08%) +[NR-eGR] M5 (5) 80( 0.08%) 0( 0.00%) ( 0.08%) +[NR-eGR] M6 (6) 14( 0.01%) 0( 0.00%) ( 0.01%) +[NR-eGR] M7 (7) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] --------------------------------------------------------------- +[NR-eGR] Total 1455( 0.25%) 74( 0.01%) ( 0.27%) +[NR-eGR] +[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.01% H + 0.21% V +[NR-eGR] Overflow after earlyGlobalRoute 0.01% H + 0.24% V +[NR-eGR] End Peak syMemory usage = 1968.7 MB +[NR-eGR] Early Global Router Kernel+IO runtime : 0.41 seconds +[hotspot] +------------+---------------+---------------+ +[hotspot] | | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | normalized | 0.26 | 0.79 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis: normalized max congestion hotspot area = 0.26, normalized total congestion hotspot area = 0.79 (area is in unit of 4 std-cell row bins) +[hotspot] top 3 congestion hotspot bounding boxes and scores of normalized hotspot +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | top | hotspot bbox | hotspot score | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 1 | 250.56 112.32 267.84 129.60 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 2 | 250.56 129.60 267.84 146.88 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 3 | 120.96 138.24 138.24 155.52 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +################################################################################# +# Design Stage: PreRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: No SPEF/RCDB +# Signoff Settings: SI Off +################################################################################# +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=1951.39) +Total number of fetched objects 9962 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +End delay calculation. (MEM=2223.73 CPU=0:00:03.6 REAL=0:00:02.0) +End delay calculation (fullDC). (MEM=2223.73 CPU=0:00:04.5 REAL=0:00:02.0) +*** Done Building Timing Graph (cpu=0:00:05.8 real=0:00:02.0 totSessionCpu=0:07:46 mem=2223.7M) +Reported timing to dir ./timingReports +**opt_design ... cpu = 0:05:20, real = 0:02:22, mem = 1455.6M, totSessionCpu=0:07:46 ** +2020/12/14 21:52:29 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:29 For more info, please run CheckSysConf in +2020/12/14 21:52:29 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:29 For more info, please run CheckSysConf in +2020/12/14 21:52:29 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:29 For more info, please run CheckSysConf in +2020/12/14 21:52:30 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:30 For more info, please run CheckSysConf in +2020/12/14 21:52:30 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:30 For more info, please run CheckSysConf in +2020/12/14 21:52:30 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:30 For more info, please run CheckSysConf in +2020/12/14 21:52:30 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:30 For more info, please run CheckSysConf in +2020/12/14 21:52:30 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:30 For more info, please run CheckSysConf in + +------------------------------------------------------------ + opt_design Final Summary +------------------------------------------------------------ + +Setup views included: + PVT_0P63V_100C.setup_view + ++--------------------+---------+---------+---------+---------+ +| Setup mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| -0.001 | -0.001 | 0.050 | 0.208 | +| TNS (ns):| -0.001 | -0.001 | 0.000 | 0.000 | +| Violating Paths:| 1 | 1 | 0 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 7 (7) | -0.909 | 7 (7) | +| max_tran | 8 (8) | -4.881 | 31 (31) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 19.288% +Routing Overflow: 0.01% H and 0.24% V +------------------------------------------------------------ +**opt_design ... cpu = 0:05:21, real = 0:02:23, mem = 1458.6M, totSessionCpu=0:07:47 ** +**WARN: (IMPOPT-3195): Analysis mode has changed. +Type 'man IMPOPT-3195' for more detail. +*** Finished opt_design *** + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: -0.001 ns -0.001 ns final + + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: 324.12 147 -0.001 ns -0.001 ns opt_design_prects +Reset maxLocalDensity to default value from N7/N5 setting. +Removing temporary dont_use automatically set for cells with technology sites with no row. +#optDebug: fT-D +**place_opt_design ... cpu = 0:06:36, real = 0:03:02, mem = 1888.4M ** +*** Finished GigaPlace *** + +*** Summary of all messages that are not suppressed in this session: +Severity ID Count Summary +ERROR IMPTS-17 11 Inconsistency detected in the capacitanc... +WARNING IMPSP-9025 2 No scan chain specified/traced. +WARNING IMPOPT-3195 2 Analysis mode has changed. +WARNING IMPOPT-3564 1 The following cells are set dont_use tem... +*** Message Summary: 5 warning(s), 11 error(s) + +@file(par.tcl) 99: puts "write_db pre_clock_tree" +write_db pre_clock_tree +@file(par.tcl) 100: write_db pre_clock_tree +#% Begin write_db save design ... (date=12/14 21:52:31, mem=1388.7M) +% Begin Save ccopt configuration ... (date=12/14 21:52:31, mem=1388.7M) +% End Save ccopt configuration ... (date=12/14 21:52:31, total cpu=0:00:00.0, real=0:00:00.0, peak res=1389.0M, current mem=1389.0M) +% Begin Save netlist data ... (date=12/14 21:52:31, mem=1389.0M) +Writing Binary DB to pre_clock_tree/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 21:52:31, total cpu=0:00:00.1, real=0:00:00.0, peak res=1392.9M, current mem=1392.9M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file pre_clock_tree/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 21:52:31, mem=1393.5M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 21:52:31, total cpu=0:00:00.0, real=0:00:00.0, peak res=1393.5M, current mem=1393.5M) +2020/12/14 21:52:31 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:31 For more info, please run CheckSysConf in +2020/12/14 21:52:31 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:31 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 21:52:31, mem=1402.7M) +% End Save clock tree data ... (date=12/14 21:52:31, total cpu=0:00:00.0, real=0:00:00.0, peak res=1402.7M, current mem=1402.7M) +Saving preference file pre_clock_tree/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 21:52:32 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:32 For more info, please run CheckSysConf in +Saving Drc markers ... +... No Drc file written since there is no markers found. +% Begin Save routing data ... (date=12/14 21:52:32, mem=1403.3M) +Saving route file ... +2020/12/14 21:52:32 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:32 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.1 real=0:00:00.0 mem=1898.5M) *** +% End Save routing data ... (date=12/14 21:52:32, total cpu=0:00:00.1, real=0:00:00.0, peak res=1404.3M, current mem=1404.3M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 21:52:32 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:32 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file pre_clock_tree/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=1922.5M) *** +% Begin Save power constraints data ... (date=12/14 21:52:32, mem=1406.2M) +% End Save power constraints data ... (date=12/14 21:52:32, total cpu=0:00:00.0, real=0:00:00.0, peak res=1406.2M, current mem=1406.2M) +Saving rc congestion map pre_clock_tree/riscv_top.congmap.gz ... +2020/12/14 21:52:32 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:52:32 For more info, please run CheckSysConf in +Saving preRoute extracted patterns in file 'pre_clock_tree/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.01 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design pre_clock_tree +#% End write_db save design ... (date=12/14 21:52:35, total cpu=0:00:01.9, real=0:00:04.0, peak res=1406.2M, current mem=1402.9M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 101: puts "ln -sfn pre_clock_tree latest" +ln -sfn pre_clock_tree latest +@file(par.tcl) 102: ln -sfn pre_clock_tree latest +@file(par.tcl) 103: puts "create_clock_tree_spec" +create_clock_tree_spec +@file(par.tcl) 104: create_clock_tree_spec +Creating clock tree spec for modes (timing configs): my_constraint_mode +cts_spec_config_create_generator_skew_groups=true: create_clock_tree_spec will generate skew groups with a name prefix of "_clock_gen" to balance clock generator connected flops with the clock generator they drive. +Reset timing graph... +Ignoring AAE DB Resetting ... +Reset timing graph done. +Ignoring AAE DB Resetting ... +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +Analyzing clock structure... +Analyzing clock structure done. +Reset timing graph... +Ignoring AAE DB Resetting ... +Reset timing graph done. +Extracting original clock gating for clk... + clock_tree clk contains 1305 sinks and 43 clock gates. + Found 4 implicit ignore or stop or exclude pins - run report_clock_trees -list_special_pins for more details. + Extraction for clk complete. +Extracting original clock gating for clk done. +The skew group clk/my_constraint_mode was created. It contains 1305 sinks and 1 sources. +Checking clock tree convergence... +Checking clock tree convergence done. +@file(par.tcl) 105: puts "ccopt_design -hold -report_dir hammer_cts_debug -report_prefix hammer_cts" +ccopt_design -hold -report_dir hammer_cts_debug -report_prefix hammer_cts +@file(par.tcl) 106: ccopt_design -hold -report_dir hammer_cts_debug -report_prefix hammer_cts +#% Begin ccopt_design (date=12/14 21:52:35, mem=1389.7M) +Runtime... +(ccopt_design): CTS Engine: auto. Used Spec: pre-existing CCOPT spec. +Preferred extra space for top nets is 0 +Preferred extra space for trunk nets is 1 +Preferred extra space for leaf nets is 1 +Placement constraints of type 'region' or 'fence' will not be downgraded to 'guide' because the attribute cts_change_fences_to_guides has been set to false. +Set place::cacheFPlanSiteMark to 1 +'setDesignMode -flowEffort standard' => 'setOptMode -usefulSkewCCOpt standard' +Using CCOpt effort standard. +CCOpt::Phase::Initialization... +Check Prerequisites... +Leaving CCOpt scope - CheckPlace... + +Begin checking placement ... (start mem=1880.1M, init mem=1880.1M) +Overlapping with other instance: 2 +*info: Placed = 12009 (Fixed = 2827) +*info: Unplaced = 0 +Placement Density:19.28%(19048/98816) +Placement Density (including fixed std cells):20.34%(20365/100133) +PowerDomain Density :17.84%(17630/98816) +Finished check_place (total: cpu=0:00:00.1, real=0:00:01.0; vio checks: cpu=0:00:00.1, real=0:00:00.0; mem=1880.1M) +**WARN: (IMPCCOPT-2030): Found placement violations. Run check_place for more details. +Leaving CCOpt scope - CheckPlace done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Leaving CCOpt scope - CheckPlace +Validating CTS configuration... +CCOpt power management detected and enabled. +Checking module port directions... +Leaving CCOpt scope... +Leaving CCOpt scope done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Leaving CCOpt scope +Checking module port directions done. (took cpu=0:00:00.0 real=0:00:00.0) +Non-default CCOpt properties: +preferred_extra_space is set for at least one key +route_clock_tree_nets_in_length_order: 1 (default: false) +route_type is set for at least one key +Using cell based legalization. +Route type trimming info: + No route type modifications were made. +Rebuilding timing graph... +Rebuilding timing graph done. +Library trimming buffers in power domain AO and half-corner PVT_0P63V_100C.setup_delay:setup.late removed 1 of 8 cells +Original list had 8 cells: +BUFx12f_ASAP7_75t_SRAM BUFx10_ASAP7_75t_SRAM BUFx6f_ASAP7_75t_SRAM BUFx5_ASAP7_75t_SRAM BUFx4f_ASAP7_75t_SRAM BUFx3_ASAP7_75t_SRAM BUFx2_ASAP7_75t_SRAM HB1xp67_ASAP7_75t_SRAM +New trimmed list has 7 cells: +BUFx12f_ASAP7_75t_SRAM BUFx10_ASAP7_75t_SRAM BUFx6f_ASAP7_75t_SRAM BUFx5_ASAP7_75t_SRAM BUFx3_ASAP7_75t_SRAM BUFx2_ASAP7_75t_SRAM HB1xp67_ASAP7_75t_SRAM +Library trimming inverters in power domain AO and half-corner PVT_0P63V_100C.setup_delay:setup.late removed 1 of 11 cells +Original list had 11 cells: +INVx13_ASAP7_75t_SRAM INVx11_ASAP7_75t_SRAM INVx8_ASAP7_75t_SRAM INVx6_ASAP7_75t_SRAM INVx5_ASAP7_75t_SRAM INVx4_ASAP7_75t_SRAM INVx3_ASAP7_75t_SRAM INVx2_ASAP7_75t_SRAM INVx1_ASAP7_75t_SRAM INVxp67_ASAP7_75t_SRAM INVxp33_ASAP7_75t_SRAM +New trimmed list has 10 cells: +INVx13_ASAP7_75t_SRAM INVx11_ASAP7_75t_SRAM INVx8_ASAP7_75t_SRAM INVx6_ASAP7_75t_SRAM INVx5_ASAP7_75t_SRAM INVx4_ASAP7_75t_SRAM INVx3_ASAP7_75t_SRAM INVx2_ASAP7_75t_SRAM INVx1_ASAP7_75t_SRAM INVxp33_ASAP7_75t_SRAM +Clock tree balancer configuration for clock_tree clk: +Non-default CCOpt properties: + route_type (leaf): default_route_type_leaf (default: default) + route_type (trunk): default_route_type_nonleaf (default: default) + route_type (top): default_route_type_nonleaf (default: default) +For power domain AO: + Buffers: {BUFx12f_ASAP7_75t_SRAM BUFx10_ASAP7_75t_SRAM BUFx6f_ASAP7_75t_SRAM BUFx5_ASAP7_75t_SRAM BUFx3_ASAP7_75t_SRAM BUFx2_ASAP7_75t_SRAM HB1xp67_ASAP7_75t_SRAM} + Inverters: {INVx13_ASAP7_75t_SRAM INVx11_ASAP7_75t_SRAM INVx8_ASAP7_75t_SRAM INVx6_ASAP7_75t_SRAM INVx5_ASAP7_75t_SRAM INVx4_ASAP7_75t_SRAM INVx3_ASAP7_75t_SRAM INVx2_ASAP7_75t_SRAM INVx1_ASAP7_75t_SRAM INVxp33_ASAP7_75t_SRAM} + Clock gates: ICGx3_ASAP7_75t_SL ICGx3_ASAP7_75t_L ICGx2_ASAP7_75t_SL ICGx3_ASAP7_75t_R ICGx2_ASAP7_75t_L ICGx3_ASAP7_75t_SRAM ICGx2_ASAP7_75t_R ICGx2_ASAP7_75t_SRAM ICGx1_ASAP7_75t_SL ICGx1_ASAP7_75t_L ICGx1_ASAP7_75t_R ICGx1_ASAP7_75t_SRAM + Unblocked area available for placement of any clock cells in power_domain AO: 99741.197um^2 +Top Routing info: + Route-type name: default_route_type_nonleaf; Top/bottom preferred layer name: M4/M3; + Unshielded; Mask Constraint: 0; Source: cts_route_type. +Trunk Routing info: + Route-type name: default_route_type_nonleaf; Top/bottom preferred layer name: M4/M3; + Unshielded; Preferred extra space: 1; Mask Constraint: 0; Source: cts_route_type. +Leaf Routing info: + Route-type name: default_route_type_leaf; Top/bottom preferred layer name: M4/M3; + Unshielded; Preferred extra space: 1; Mask Constraint: 0; Source: cts_route_type. +For timing_corner PVT_0P63V_100C.setup_delay:setup, late and power domain AO: + Slew time target (leaf): 69.3ps + Slew time target (trunk): 69.3ps + Slew time target (top): 69.3ps (Note: no nets are considered top nets in this clock tree) + Buffer unit delay: 33.6ps + Buffer max distance: 272.774um +Fastest wire driving cells and distances: + Buffer : {lib_cell:BUFx12f_ASAP7_75t_SRAM, fastest_considered_half_corner=PVT_0P63V_100C.setup_delay:setup.late, optimalDrivingDistance=272.774um, saturatedSlew=52.5ps, speed=4906.007um per ns, cellArea=15.394um^2 per 1000um} + Inverter : {lib_cell:INVx6_ASAP7_75t_SRAM, fastest_considered_half_corner=PVT_0P63V_100C.setup_delay:setup.late, optimalDrivingDistance=150.343um, saturatedSlew=35.2ps, speed=5749.254um per ns, cellArea=12.413um^2 per 1000um} + Clock gate: {lib_cell:ICGx3_ASAP7_75t_SL, fastest_considered_half_corner=PVT_0P63V_100C.setup_delay:setup.late, optimalDrivingDistance=222.857um, saturatedSlew=53.9ps, speed=5758.579um per ns, cellArea=20.935um^2 per 1000um} + + +Logic Sizing Table: + +---------------------------------------------------------- +Cell Instance count Source Eligible library cells +---------------------------------------------------------- + (empty table) +---------------------------------------------------------- + + +Clock tree balancer configuration for skew_group clk/my_constraint_mode: + Sources: pin clk + Total number of sinks: 1305 + Delay constrained sinks: 1301 + Non-leaf sinks: 0 + Ignore pins: 0 + Timing corner PVT_0P63V_100C.setup_delay:setup.late: + Skew target: 33.6ps +Primary reporting skew group is skew_group clk/my_constraint_mode with 1305 clock sinks. + +Via Selection for Estimated Routes (rule default): + +-------------------------------------------------------------- +Layer Via Cell Res. Cap. RC Top of Stack +Range (Ohm) (fF) (fs) Only +-------------------------------------------------------------- +M1-M2 VIA12 10.000 0.002 0.018 false +M2-M3 VIA23 10.000 0.002 0.020 false +M3-M4 VIA34 10.000 0.002 0.025 false +M4-M5 VIA45 10.000 0.003 0.033 false +M5-M6 VIA56 10.000 0.004 0.037 false +M6-M7 VIA67 10.000 0.004 0.040 false +M7-M8 VIA78 10.000 0.003 0.034 false +M8-M9 VIA89 10.000 0.003 0.028 false +M9-Pad VIA9Pad 10.000 0.013 0.133 false +-------------------------------------------------------------- + +No ideal or dont_touch nets found in the clock tree +Validating CTS configuration done. (took cpu=0:00:03.0 real=0:00:02.4) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Validating CTS configuration +CCOpt configuration status: all checks passed. +External - Set all clocks to propagated mode... +Innovus will update I/O latencies +External - Set all clocks to propagated mode done. (took cpu=0:00:00.0 real=0:00:00.0) +Check Prerequisites done. (took cpu=0:00:03.2 real=0:00:02.6) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Check Prerequisites +CCOpt::Phase::Initialization done. (took cpu=0:00:03.2 real=0:00:02.6) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: 5.97 7 CCOpt::Phase::Initialization +Executing ccopt post-processing. +Synthesizing clock trees with CCOpt... +CCOpt::Phase::PreparingToBalance... +Leaving CCOpt scope - Initializing power interface... +Leaving CCOpt scope - Initializing power interface done. (took cpu=0:00:00.0 real=0:00:00.0) +Leaving CCOpt scope - optDesignGlobalRouteStep... +[NR-eGR] honorMsvRouteConstraint: false +[NR-eGR] honorClockSpecNDR : 0 +[NR-eGR] minRouteLayer : 2 +[NR-eGR] maxRouteLayer : 7 +[NR-eGR] numTracksPerClockWire : 0 +[NR-eGR] M1 has no routable track +[NR-eGR] M2 has non-uniform track structures +[NR-eGR] M3 has single uniform track structure +[NR-eGR] M4 has single uniform track structure +[NR-eGR] M5 has single uniform track structure +[NR-eGR] M6 has single uniform track structure +[NR-eGR] M7 has single uniform track structure +[NR-eGR] Read 53034 PG shapes in 0.020 seconds + +[NR-eGR] numRoutingBlks=0 numInstBlks=2389 numPGBlocks=53034 numBumpBlks=0 numBoundaryFakeBlks=0 +[NR-eGR] Num Prerouted Nets = 0 Num Prerouted Wires = 0 +[NR-eGR] Read numTotalNets=9621 numIgnoredNets=0 +[NR-eGR] There are 44 clock nets ( 0 with NDR ). +[NR-eGR] ============ Routing rule table ============ +[NR-eGR] Rule id: 0 Nets: 9621 +[NR-eGR] ======================================== +[NR-eGR] +[NR-eGR] Layer group 1: route 41 net(s) in layer range [4, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.00% H + 0.00% V. EstWL: 7.198200e+03um +[NR-eGR] +[NR-eGR] Layer group 2: route 9580 net(s) in layer range [2, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 2: 0.03% H + 0.27% V. EstWL: 2.764465e+05um +[NR-eGR] +[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded) +[NR-eGR] OverCon OverCon +[NR-eGR] #Gcell #Gcell %Gcell +[NR-eGR] Layer (1) (4) OverCon +[NR-eGR] --------------------------------------------------------------- +[NR-eGR] M1 (1) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M2 (2) 84( 0.09%) 1( 0.00%) ( 0.10%) +[NR-eGR] M3 (3) 1195( 1.33%) 71( 0.08%) ( 1.41%) +[NR-eGR] M4 (4) 82( 0.08%) 2( 0.00%) ( 0.08%) +[NR-eGR] M5 (5) 80( 0.08%) 0( 0.00%) ( 0.08%) +[NR-eGR] M6 (6) 14( 0.01%) 0( 0.00%) ( 0.01%) +[NR-eGR] M7 (7) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] --------------------------------------------------------------- +[NR-eGR] Total 1455( 0.25%) 74( 0.01%) ( 0.27%) +[NR-eGR] +[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.01% H + 0.21% V +[NR-eGR] Overflow after earlyGlobalRoute 0.01% H + 0.24% V +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] M1 (1F) length: 0.000000e+00um, number of vias: 31885 +[NR-eGR] M2 (2H) length: 6.544005e+04um, number of vias: 48212 +[NR-eGR] M3 (3V) length: 8.677599e+04um, number of vias: 9227 +[NR-eGR] M4 (4H) length: 4.039671e+04um, number of vias: 6858 +[NR-eGR] M5 (5V) length: 4.811566e+04um, number of vias: 2067 +[NR-eGR] M6 (6H) length: 1.952662e+04um, number of vias: 1128 +[NR-eGR] M7 (7V) length: 3.056102e+04um, number of vias: 0 +[NR-eGR] Total length: 2.908160e+05um, number of vias: 99377 +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] Total eGR-routed clock nets wire length: 1.809911e+04um +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] End Peak syMemory usage = 1875.0 MB +[NR-eGR] Early Global Router Kernel+IO runtime : 0.73 seconds +Leaving CCOpt scope - optDesignGlobalRouteStep done. (took cpu=0:00:00.7 real=0:00:00.6) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Leaving CCOpt scope - optDesignGlobalRouteStep +Legalization setup... +Using cell based legalization. +Legalization setup done. (took cpu=0:00:00.3 real=0:00:00.2) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Legalization setup +Validating CTS configuration... +Checking module port directions... +Leaving CCOpt scope... +Leaving CCOpt scope done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Leaving CCOpt scope +Checking module port directions done. (took cpu=0:00:00.0 real=0:00:00.0) +Non-default CCOpt properties: +cts_merge_clock_gates is set for at least one key +cts_merge_clock_logic is set for at least one key +preferred_extra_space is set for at least one key +route_clock_tree_nets_in_length_order: 1 (default: false) +route_type is set for at least one key +Route type trimming info: + No route type modifications were made. +Updating RC grid for preRoute extraction ... +Initializing multi-corner resistance tables ... +Rebuilding timing graph... +Rebuilding timing graph done. +Library trimming buffers in power domain AO and half-corner PVT_0P63V_100C.setup_delay:setup.late removed 1 of 8 cells +Original list had 8 cells: +BUFx12f_ASAP7_75t_SRAM BUFx10_ASAP7_75t_SRAM BUFx6f_ASAP7_75t_SRAM BUFx5_ASAP7_75t_SRAM BUFx4f_ASAP7_75t_SRAM BUFx3_ASAP7_75t_SRAM BUFx2_ASAP7_75t_SRAM HB1xp67_ASAP7_75t_SRAM +New trimmed list has 7 cells: +BUFx12f_ASAP7_75t_SRAM BUFx10_ASAP7_75t_SRAM BUFx6f_ASAP7_75t_SRAM BUFx5_ASAP7_75t_SRAM BUFx3_ASAP7_75t_SRAM BUFx2_ASAP7_75t_SRAM HB1xp67_ASAP7_75t_SRAM +Library trimming inverters in power domain AO and half-corner PVT_0P63V_100C.setup_delay:setup.late removed 1 of 11 cells +Original list had 11 cells: +INVx13_ASAP7_75t_SRAM INVx11_ASAP7_75t_SRAM INVx8_ASAP7_75t_SRAM INVx6_ASAP7_75t_SRAM INVx5_ASAP7_75t_SRAM INVx4_ASAP7_75t_SRAM INVx3_ASAP7_75t_SRAM INVx2_ASAP7_75t_SRAM INVx1_ASAP7_75t_SRAM INVxp67_ASAP7_75t_SRAM INVxp33_ASAP7_75t_SRAM +New trimmed list has 10 cells: +INVx13_ASAP7_75t_SRAM INVx11_ASAP7_75t_SRAM INVx8_ASAP7_75t_SRAM INVx6_ASAP7_75t_SRAM INVx5_ASAP7_75t_SRAM INVx4_ASAP7_75t_SRAM INVx3_ASAP7_75t_SRAM INVx2_ASAP7_75t_SRAM INVx1_ASAP7_75t_SRAM INVxp33_ASAP7_75t_SRAM +Clock tree balancer configuration for clock_tree clk: +Non-default CCOpt properties: + cts_merge_clock_gates: true (default: false) + cts_merge_clock_logic: true (default: false) + route_type (leaf): default_route_type_leaf (default: default) + route_type (trunk): default_route_type_nonleaf (default: default) + route_type (top): default_route_type_nonleaf (default: default) +For power domain AO: + Buffers: {BUFx12f_ASAP7_75t_SRAM BUFx10_ASAP7_75t_SRAM BUFx6f_ASAP7_75t_SRAM BUFx5_ASAP7_75t_SRAM BUFx3_ASAP7_75t_SRAM BUFx2_ASAP7_75t_SRAM HB1xp67_ASAP7_75t_SRAM} + Inverters: {INVx13_ASAP7_75t_SRAM INVx11_ASAP7_75t_SRAM INVx8_ASAP7_75t_SRAM INVx6_ASAP7_75t_SRAM INVx5_ASAP7_75t_SRAM INVx4_ASAP7_75t_SRAM INVx3_ASAP7_75t_SRAM INVx2_ASAP7_75t_SRAM INVx1_ASAP7_75t_SRAM INVxp33_ASAP7_75t_SRAM} + Clock gates: ICGx3_ASAP7_75t_SL ICGx3_ASAP7_75t_L ICGx2_ASAP7_75t_SL ICGx3_ASAP7_75t_R ICGx2_ASAP7_75t_L ICGx3_ASAP7_75t_SRAM ICGx2_ASAP7_75t_R ICGx2_ASAP7_75t_SRAM ICGx1_ASAP7_75t_SL ICGx1_ASAP7_75t_L ICGx1_ASAP7_75t_R ICGx1_ASAP7_75t_SRAM + Unblocked area available for placement of any clock cells in power_domain AO: 99741.197um^2 +Top Routing info: + Route-type name: default_route_type_nonleaf; Top/bottom preferred layer name: M4/M3; + Unshielded; Mask Constraint: 0; Source: cts_route_type. +Trunk Routing info: + Route-type name: default_route_type_nonleaf; Top/bottom preferred layer name: M4/M3; + Unshielded; Preferred extra space: 1; Mask Constraint: 0; Source: cts_route_type. +Leaf Routing info: + Route-type name: default_route_type_leaf; Top/bottom preferred layer name: M4/M3; + Unshielded; Preferred extra space: 1; Mask Constraint: 0; Source: cts_route_type. +For timing_corner PVT_0P63V_100C.setup_delay:setup, late and power domain AO: + Slew time target (leaf): 69.3ps + Slew time target (trunk): 69.3ps + Slew time target (top): 69.3ps (Note: no nets are considered top nets in this clock tree) + Buffer unit delay: 33.6ps + Buffer max distance: 272.774um +Fastest wire driving cells and distances: + Buffer : {lib_cell:BUFx12f_ASAP7_75t_SRAM, fastest_considered_half_corner=PVT_0P63V_100C.setup_delay:setup.late, optimalDrivingDistance=272.774um, saturatedSlew=52.5ps, speed=4906.007um per ns, cellArea=15.394um^2 per 1000um} + Inverter : {lib_cell:INVx6_ASAP7_75t_SRAM, fastest_considered_half_corner=PVT_0P63V_100C.setup_delay:setup.late, optimalDrivingDistance=150.343um, saturatedSlew=35.2ps, speed=5749.254um per ns, cellArea=12.413um^2 per 1000um} + Clock gate: {lib_cell:ICGx3_ASAP7_75t_SL, fastest_considered_half_corner=PVT_0P63V_100C.setup_delay:setup.late, optimalDrivingDistance=222.857um, saturatedSlew=53.9ps, speed=5758.579um per ns, cellArea=20.935um^2 per 1000um} + + +Logic Sizing Table: + +---------------------------------------------------------- +Cell Instance count Source Eligible library cells +---------------------------------------------------------- + (empty table) +---------------------------------------------------------- + + +Clock tree balancer configuration for skew_group clk/my_constraint_mode: + Sources: pin clk + Total number of sinks: 1305 + Delay constrained sinks: 1301 + Non-leaf sinks: 0 + Ignore pins: 0 + Timing corner PVT_0P63V_100C.setup_delay:setup.late: + Skew target: 33.6ps +Primary reporting skew group is skew_group clk/my_constraint_mode with 1305 clock sinks. + +Via Selection for Estimated Routes (rule default): + +-------------------------------------------------------------- +Layer Via Cell Res. Cap. RC Top of Stack +Range (Ohm) (fF) (fs) Only +-------------------------------------------------------------- +M1-M2 VIA12 10.000 0.002 0.018 false +M2-M3 VIA23 10.000 0.002 0.020 false +M3-M4 VIA34 10.000 0.002 0.025 false +M4-M5 VIA45 10.000 0.003 0.033 false +M5-M6 VIA56 10.000 0.004 0.037 false +M6-M7 VIA67 10.000 0.004 0.040 false +M7-M8 VIA78 10.000 0.003 0.034 false +M8-M9 VIA89 10.000 0.003 0.028 false +M9-Pad VIA9Pad 10.000 0.013 0.133 false +-------------------------------------------------------------- + +No ideal or dont_touch nets found in the clock tree +Validating CTS configuration done. (took cpu=0:00:02.7 real=0:00:02.2) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Validating CTS configuration +CCOpt configuration status: all checks passed. +Adding exclusion drivers (these will be instances of the smallest area library cells). +No exclusion drivers are needed. +Antenna diode management... + Found 0 antenna diodes in the clock trees. + +Antenna diode management done. +Adding driver cells for primary IOs... + + ---------------------------------------------------------------------------------------------- + CCOpt reported the following when adding drivers below input ports and above output ports + ---------------------------------------------------------------------------------------------- + (empty table) + ---------------------------------------------------------------------------------------------- + + +Adding driver cells for primary IOs done. +Adding driver cell for primary IO roots... +Adding driver cell for primary IO roots done. +Maximizing clock DAG abstraction... +Maximizing clock DAG abstraction done. +CCOpt::Phase::PreparingToBalance done. (took cpu=0:00:03.9 real=0:00:03.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: CCOpt::Phase::PreparingToBalance +Synthesizing clock trees... + Preparing To Balance... + Library trimming clock gates in power domain AO and half-corner PVT_0P63V_100C.setup_delay:setup.late removed 8 of 12 cells + Original list had 12 cells: + ICGx3_ASAP7_75t_SL ICGx3_ASAP7_75t_L ICGx2_ASAP7_75t_SL ICGx3_ASAP7_75t_R ICGx2_ASAP7_75t_L ICGx3_ASAP7_75t_SRAM ICGx2_ASAP7_75t_R ICGx2_ASAP7_75t_SRAM ICGx1_ASAP7_75t_SL ICGx1_ASAP7_75t_L ICGx1_ASAP7_75t_R ICGx1_ASAP7_75t_SRAM + New trimmed list has 4 cells: + ICGx3_ASAP7_75t_SL ICGx2_ASAP7_75t_SL ICGx1_ASAP7_75t_SL ICGx1_ASAP7_75t_SRAM + Merging duplicate siblings in DAG... + Clock DAG stats before merging: + cell counts : b=0, i=0, icg=43, nicg=0, l=0, total=43 + cell areas : b=0.000um^2, i=0.000um^2, icg=180.559um^2, nicg=0.000um^2, l=0.000um^2, total=180.559um^2 + Clock DAG library cell distribution before merging {count}: + ICGs: ICGx1_ASAP7_75t_R: 43 + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: before merging + Resynthesising clock tree into netlist... + Reset timing graph... +Ignoring AAE DB Resetting ... + Reset timing graph done. + Resynthesising clock tree into netlist done. + + Clock gate merging summary: + + ---------------------------------------------------------- + Description Number of occurrences + ---------------------------------------------------------- + Total clock gates 43 + Globally unique enables 43 + Potentially mergeable clock gates 0 + Actually merged clock gates 0 + ---------------------------------------------------------- + + -------------------------------------------- + Cannot merge reason Number of occurrences + -------------------------------------------- + GloballyUnique 43 + -------------------------------------------- + + Disconnecting clock tree from netlist... + Disconnecting clock tree from netlist done. + Merging duplicate siblings in DAG done. + Preparing To Balance done. (took cpu=0:00:00.4 real=0:00:00.3) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Preparing To Balance + CCOpt::Phase::Construction... + Stage::Clustering... + Clustering... + Initialize for clustering... + Clock DAG stats before clustering: + cell counts : b=0, i=0, icg=43, nicg=0, l=0, total=43 + cell areas : b=0.000um^2, i=0.000um^2, icg=200.621um^2, nicg=0.000um^2, l=0.000um^2, total=200.621um^2 + Clock DAG library cell distribution before clustering {count}: + ICGs: ICGx3_ASAP7_75t_SL: 43 + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: before clustering + Computing max distances from locked parents... + Computing distance_from_locked_parent_restrictions for 0 nodes driven by 0 locked parents + Computing max distances from locked parents done. + Initialize for clustering done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Initialize for clustering + Bottom-up phase... + Clustering clock_tree clk... + Rebuilding timing graph... + Rebuilding timing graph done. + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late... + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late done. (took cpu=0:00:00.2 real=0:00:00.0) + Clustering clock_tree clk done. + Clock DAG stats after bottom-up phase: + cell counts : b=45, i=0, icg=43, nicg=0, l=0, total=88 + cell areas : b=188.957um^2, i=0.000um^2, icg=199.454um^2, nicg=0.000um^2, l=0.000um^2, total=388.411um^2 + Clock DAG library cell distribution after bottom-up phase {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 45 + ICGs: ICGx3_ASAP7_75t_SL: 40 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SRAM: 2 + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: after bottom-up phase + Bottom-up phase done. (took cpu=0:00:02.2 real=0:00:01.6) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Bottom-up phase + Legalizing clock trees... + Resynthesising clock tree into netlist... + Reset timing graph... +Ignoring AAE DB Resetting ... + Reset timing graph done. + Resynthesising clock tree into netlist done. + Commiting net attributes.... + Commiting net attributes. done. + Leaving CCOpt scope - ClockRefiner... + Performing a single pass refine place with FGC disabled for datapath. +*** Starting place_detail (0:08:00 mem=2093.7M) *** +Total net bbox length = 2.538e+05 (1.008e+05 1.530e+05) (ext = 3.759e+04) +Move report: Detail placement moves 320 insts, mean move: 1.75 um, max move: 15.12 um + Max move on inst (cpu/stage1/regfile/CTS_ccl_a_buf_00119): (152.71, 167.40) --> (152.71, 152.28) + Runtime: CPU: 0:00:00.9 REAL: 0:00:00.0 MEM: 2093.7MB +Summary Report: +Instances move: 320 (out of 9227 movable) +Instances flipped: 1 +Mean displacement: 1.75 um +Max displacement: 15.12 um (Instance: cpu/stage1/regfile/CTS_ccl_a_buf_00119) (152.712, 167.4) -> (152.712, 152.28) + Length: 18 sites, height: 1 rows, site name: coreSite, cell type: BUFx12f_ASAP7_75t_SRAM +Total net bbox length = 2.541e+05 (1.009e+05 1.532e+05) (ext = 3.759e+04) +Runtime: CPU: 0:00:01.0 REAL: 0:00:00.0 MEM: 2093.7MB +*** Finished place_detail (0:08:01 mem=2093.7M) *** + Moved 110, flipped 50 and cell swapped 0 of 1393 clock instance(s) during refinement. + The largest move was 15.1 microns for cpu/stage1/regfile/CTS_ccl_a_buf_00119. + Leaving CCOpt scope - ClockRefiner done. (took cpu=0:00:01.4 real=0:00:01.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Leaving CCOpt scope - ClockRefiner + Disconnecting clock tree from netlist... + Disconnecting clock tree from netlist done. + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late... + Rebuilding timing graph... + Rebuilding timing graph done. + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late done. (took cpu=0:00:00.9 real=0:00:00.3) + + Clock tree legalization - Histogram: + ==================================== + + ---------------------------------- + Movement (um) Number of cells + ---------------------------------- + [1.08,2.484) 16 + [2.484,3.888) 4 + [3.888,5.292) 14 + [5.292,6.696) 4 + [6.696,8.1) 9 + [8.1,9.504) 2 + [9.504,10.908) 3 + [10.908,12.312) 1 + [12.312,13.716) 2 + [13.716,15.12) 1 + ---------------------------------- + + + Clock tree legalization - Top 10 Movements: + =========================================== + + -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Movement (um) Desired Achieved Node + location location + -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 15.12 (152.712,167.400) (152.712,152.280) ccl_a clock buffer, uid:A7b26 (a lib_cell BUFx12f_ASAP7_75t_SRAM) at (152.712,152.280), in power domain AO + 12.96 (150.768,169.560) (160.488,166.320) ccl_a clock buffer, uid:A7b0f (a lib_cell BUFx12f_ASAP7_75t_SRAM) at (160.488,166.320), in power domain AO + 12.96 (153.360,165.240) (166.320,165.240) ccl_a clock buffer, uid:A7af3 (a lib_cell BUFx12f_ASAP7_75t_SRAM) at (166.320,165.240), in power domain AO + 11.88 (153.576,173.880) (161.136,178.200) ccl_a clock buffer, uid:A7af1 (a lib_cell BUFx12f_ASAP7_75t_SRAM) at (161.136,178.200), in power domain AO + 10.8 (149.256,168.480) (139.536,167.400) ccl_a clock buffer, uid:A7aeb (a lib_cell BUFx12f_ASAP7_75t_SRAM) at (139.536,167.400), in power domain AO + 10.152 (150.984,176.040) (161.136,176.040) ccl_a clock buffer, uid:A7b11 (a lib_cell BUFx12f_ASAP7_75t_SRAM) at (161.136,176.040), in power domain AO + 9.504 (153.144,160.920) (160.488,158.760) ccl_a clock buffer, uid:A7b05 (a lib_cell BUFx12f_ASAP7_75t_SRAM) at (160.488,158.760), in power domain AO + 8.208 (152.280,168.480) (160.488,168.480) cell cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CGIC_INST (a lib_cell ICGx3_ASAP7_75t_SL) at (160.488,168.480), in power domain AO + 8.208 (152.280,164.160) (160.488,164.160) cell cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CGIC_INST (a lib_cell ICGx3_ASAP7_75t_SL) at (160.488,164.160), in power domain AO + 7.776 (147.744,165.240) (145.368,159.840) ccl_a clock buffer, uid:A7b13 (a lib_cell BUFx12f_ASAP7_75t_SRAM) at (145.368,159.840), in power domain AO + -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + + Legalizing clock trees done. (took cpu=0:00:02.7 real=0:00:01.7) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Legalizing clock trees + Clock DAG stats after 'Clustering': + cell counts : b=45, i=0, icg=43, nicg=0, l=0, total=88 + cell areas : b=188.957um^2, i=0.000um^2, icg=199.454um^2, nicg=0.000um^2, l=0.000um^2, total=388.411um^2 +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +**WARN: (EMS-27): Message (IMPTS-17) has exceeded the current message display limit of 1. +To increase the message display limit, refer to the product command reference manual. + cell capacitance : b=0.060pF, i=0.000pF, icg=0.072pF, nicg=0.000pF, l=0.000pF, total=0.132pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.044pF, leaf=0.447pF, total=0.491pF + wire lengths : top=0.000um, trunk=1854.376um, leaf=17403.779um, total=19258.154um + Clock DAG net violations after 'Clustering': + Remaining Transition : {count=1, worst=[1.0ps]} avg=1.0ps sd=0.0ps sum=1.0ps + Clock DAG primary half-corner transition distribution after 'Clustering': + Trunk : target=69.3ps count=42 avg=16.8ps sd=13.7ps min=8.8ps max=60.1ps {39 <= 41.6ps, 0 <= 55.4ps, 3 <= 62.4ps, 0 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.5ps sd=0.4ps min=7.0ps max=7.8ps {0 <= 4.8ps, 0 <= 6.4ps, 1 <= 7.2ps, 1 <= 7.6ps, 2 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=52.6ps sd=10.2ps min=24.4ps max=70.3ps {4 <= 41.6ps, 18 <= 55.4ps, 13 <= 62.4ps, 6 <= 65.8ps, 1 <= 69.3ps} {1 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution after 'Clustering' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 45 + ICGs: ICGx3_ASAP7_75t_SL: 40 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Clustering': + skew_group clk/my_constraint_mode: insertion delay [min=111.7, max=171.5, avg=142.4, sd=15.6], skew [59.8 vs 33.6*], 71.3% {131.1, 164.7} (wid=60.2 ws=46.5) (gid=115.5 gs=33.8) + Skew group summary after 'Clustering': + skew_group clk/my_constraint_mode: insertion delay [min=111.7, max=171.5, avg=142.4, sd=15.6], skew [59.8 vs 33.6*], 71.3% {131.1, 164.7} (wid=60.2 ws=46.5) (gid=115.5 gs=33.8) + Clock network insertion delays are now [111.7ps, 171.5ps] average 142.4ps std.dev 15.6ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 1176 succeeded with high effort: 1176 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Clustering done. (took cpu=0:00:05.1 real=0:00:03.5) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Clustering + Update congestion based capacitance... + Resynthesising clock tree into netlist... + Reset timing graph... +Ignoring AAE DB Resetting ... + Reset timing graph done. + Resynthesising clock tree into netlist done. + Updating congestion map to accurately time the clock tree... + Routing unrouted datapath nets connected to clock instances... + Routed 168 unrouted datapath nets connected to clock instances + Routing unrouted datapath nets connected to clock instances done. + Leaving CCOpt scope - extractRC... + Updating RC parasitics by calling: "extract_rc -noRouteCheck"... +Extraction called for design 'riscv_top' of instances=12054 and nets=12071 using extraction engine 'pre_route' . +pre_route RC Extraction called for design riscv_top. +RC Extraction called in multi-corner(2) mode. +RCMode: PreRoute + RC Corner Indexes 0 1 +Capacitance Scaling Factor : 1.00000 1.00000 +Resistance Scaling Factor : 1.00000 1.00000 +Clock Cap. Scaling Factor : 1.00000 1.00000 +Clock Res. Scaling Factor : 1.00000 1.00000 +Shrink Factor : 1.00000 +PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets. +Using Quantus QRC technology file ... +Updating RC grid for preRoute extraction ... +Initializing multi-corner resistance tables ... +PreRoute RC Extraction DONE (CPU Time: 0:00:00.2 Real Time: 0:00:01.0 MEM: 1885.797M) + Updating RC parasitics by calling: "extract_rc -noRouteCheck" done. + Leaving CCOpt scope - extractRC done. (took cpu=0:00:00.2 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Leaving CCOpt scope - extractRC + Updating congestion map to accurately time the clock tree done. + Disconnecting clock tree from netlist... + Disconnecting clock tree from netlist done. + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late... + Rebuilding timing graph... + Rebuilding timing graph done. + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late done. (took cpu=0:00:00.9 real=0:00:00.3) + Clock DAG stats After congestion update: + cell counts : b=45, i=0, icg=43, nicg=0, l=0, total=88 + cell areas : b=188.957um^2, i=0.000um^2, icg=199.454um^2, nicg=0.000um^2, l=0.000um^2, total=388.411um^2 + cell capacitance : b=0.060pF, i=0.000pF, icg=0.072pF, nicg=0.000pF, l=0.000pF, total=0.132pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.045pF, leaf=0.451pF, total=0.496pF + wire lengths : top=0.000um, trunk=1854.376um, leaf=17403.779um, total=19258.154um + Clock DAG net violations After congestion update: + Remaining Transition : {count=1, worst=[1.1ps]} avg=1.1ps sd=0.0ps sum=1.1ps + Clock DAG primary half-corner transition distribution After congestion update: + Trunk : target=69.3ps count=42 avg=16.8ps sd=13.7ps min=8.7ps max=60.2ps {39 <= 41.6ps, 0 <= 55.4ps, 3 <= 62.4ps, 0 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.5ps sd=0.4ps min=7.0ps max=7.8ps {0 <= 4.8ps, 0 <= 6.4ps, 1 <= 7.2ps, 1 <= 7.6ps, 2 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=52.8ps sd=10.3ps min=24.4ps max=70.4ps {4 <= 41.6ps, 18 <= 55.4ps, 12 <= 62.4ps, 7 <= 65.8ps, 1 <= 69.3ps} {1 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution After congestion update {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 45 + ICGs: ICGx3_ASAP7_75t_SL: 40 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group After congestion update: + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.4, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Skew group summary After congestion update: + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.4, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Clock network insertion delays are now [113.2ps, 172.5ps] average 143.4ps std.dev 15.8ps + Update congestion based capacitance done. (took cpu=0:00:01.3 real=0:00:00.6) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Update congestion based capacitance + Stage::Clustering done. (took cpu=0:00:06.4 real=0:00:04.2) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Stage::Clustering + Stage::DRV Fixing... + Fixing clock tree slew time and max cap violations... + Fixing clock tree overload: .. .20% ...40% ...60% ...80% ...100% + Clock DAG stats after 'Fixing clock tree slew time and max cap violations': + cell counts : b=45, i=0, icg=43, nicg=0, l=0, total=88 + cell areas : b=188.957um^2, i=0.000um^2, icg=199.454um^2, nicg=0.000um^2, l=0.000um^2, total=388.411um^2 + cell capacitance : b=0.060pF, i=0.000pF, icg=0.072pF, nicg=0.000pF, l=0.000pF, total=0.132pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1877.632um, leaf=17409.935um, total=19287.567um + Clock DAG net violations after 'Fixing clock tree slew time and max cap violations': none + Clock DAG primary half-corner transition distribution after 'Fixing clock tree slew time and max cap violations': + Trunk : target=69.3ps count=42 avg=16.9ps sd=13.7ps min=8.7ps max=60.2ps {39 <= 41.6ps, 0 <= 55.4ps, 3 <= 62.4ps, 0 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.5ps sd=0.4ps min=7.0ps max=7.8ps {0 <= 4.8ps, 0 <= 6.4ps, 1 <= 7.2ps, 1 <= 7.6ps, 2 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=52.7ps sd=10.1ps min=24.4ps max=68.0ps {4 <= 41.6ps, 18 <= 55.4ps, 12 <= 62.4ps, 8 <= 65.8ps, 1 <= 69.3ps} + Clock DAG library cell distribution after 'Fixing clock tree slew time and max cap violations' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 45 + ICGs: ICGx3_ASAP7_75t_SL: 40 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Fixing clock tree slew time and max cap violations': + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.5, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Skew group summary after 'Fixing clock tree slew time and max cap violations': + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.5, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Clock network insertion delays are now [113.2ps, 172.5ps] average 143.5ps std.dev 15.8ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 10 succeeded with high effort: 10 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Fixing clock tree slew time and max cap violations done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Fixing clock tree slew time and max cap violations + Fixing clock tree slew time and max cap violations - detailed pass... + Fixing clock tree overload: ...20% ...40% ...60% ...80% ...100% + Clock DAG stats after 'Fixing clock tree slew time and max cap violations - detailed pass': + cell counts : b=45, i=0, icg=43, nicg=0, l=0, total=88 + cell areas : b=188.957um^2, i=0.000um^2, icg=199.454um^2, nicg=0.000um^2, l=0.000um^2, total=388.411um^2 + cell capacitance : b=0.060pF, i=0.000pF, icg=0.072pF, nicg=0.000pF, l=0.000pF, total=0.132pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1877.632um, leaf=17409.935um, total=19287.567um + Clock DAG net violations after 'Fixing clock tree slew time and max cap violations - detailed pass': none + Clock DAG primary half-corner transition distribution after 'Fixing clock tree slew time and max cap violations - detailed pass': + Trunk : target=69.3ps count=42 avg=16.9ps sd=13.7ps min=8.7ps max=60.2ps {39 <= 41.6ps, 0 <= 55.4ps, 3 <= 62.4ps, 0 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.5ps sd=0.4ps min=7.0ps max=7.8ps {0 <= 4.8ps, 0 <= 6.4ps, 1 <= 7.2ps, 1 <= 7.6ps, 2 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=52.7ps sd=10.1ps min=24.4ps max=68.0ps {4 <= 41.6ps, 18 <= 55.4ps, 12 <= 62.4ps, 8 <= 65.8ps, 1 <= 69.3ps} + Clock DAG library cell distribution after 'Fixing clock tree slew time and max cap violations - detailed pass' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 45 + ICGs: ICGx3_ASAP7_75t_SL: 40 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Fixing clock tree slew time and max cap violations - detailed pass': + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.5, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Skew group summary after 'Fixing clock tree slew time and max cap violations - detailed pass': + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.5, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Clock network insertion delays are now [113.2ps, 172.5ps] average 143.5ps std.dev 15.8ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Fixing clock tree slew time and max cap violations - detailed pass done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Fixing clock tree slew time and max cap violations - detailed pass + Stage::DRV Fixing done. (took cpu=0:00:00.2 real=0:00:00.2) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Stage::DRV Fixing + Stage::Insertion Delay Reduction... + Removing unnecessary root buffering... + Clock DAG stats after 'Removing unnecessary root buffering': + cell counts : b=45, i=0, icg=43, nicg=0, l=0, total=88 + cell areas : b=188.957um^2, i=0.000um^2, icg=199.454um^2, nicg=0.000um^2, l=0.000um^2, total=388.411um^2 + cell capacitance : b=0.060pF, i=0.000pF, icg=0.072pF, nicg=0.000pF, l=0.000pF, total=0.132pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1877.632um, leaf=17409.935um, total=19287.567um + Clock DAG net violations after 'Removing unnecessary root buffering': none + Clock DAG primary half-corner transition distribution after 'Removing unnecessary root buffering': + Trunk : target=69.3ps count=42 avg=16.9ps sd=13.7ps min=8.7ps max=60.2ps {39 <= 41.6ps, 0 <= 55.4ps, 3 <= 62.4ps, 0 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.5ps sd=0.4ps min=7.0ps max=7.8ps {0 <= 4.8ps, 0 <= 6.4ps, 1 <= 7.2ps, 1 <= 7.6ps, 2 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=52.7ps sd=10.1ps min=24.4ps max=68.0ps {4 <= 41.6ps, 18 <= 55.4ps, 12 <= 62.4ps, 8 <= 65.8ps, 1 <= 69.3ps} + Clock DAG library cell distribution after 'Removing unnecessary root buffering' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 45 + ICGs: ICGx3_ASAP7_75t_SL: 40 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Removing unnecessary root buffering': + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.5, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Skew group summary after 'Removing unnecessary root buffering': + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.5, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Clock network insertion delays are now [113.2ps, 172.5ps] average 143.5ps std.dev 15.8ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Removing unnecessary root buffering done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Removing unnecessary root buffering + Removing unconstrained drivers... + Have 1 candidate drivers for removal. + Removing drivers: ...20% ...40% ...60% ...80% ...100% + Removed 1 unconstrained driver. + Clock DAG stats after 'Removing unconstrained drivers': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=184.758um^2, i=0.000um^2, icg=199.454um^2, nicg=0.000um^2, l=0.000um^2, total=384.212um^2 + cell capacitance : b=0.059pF, i=0.000pF, icg=0.072pF, nicg=0.000pF, l=0.000pF, total=0.131pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.045pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1864.404um, leaf=17423.095um, total=19287.499um + Clock DAG net violations after 'Removing unconstrained drivers': none + Clock DAG primary half-corner transition distribution after 'Removing unconstrained drivers': + Trunk : target=69.3ps count=41 avg=16.8ps sd=13.9ps min=8.7ps max=60.2ps {38 <= 41.6ps, 0 <= 55.4ps, 3 <= 62.4ps, 0 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=52.7ps sd=10.1ps min=24.4ps max=68.0ps {4 <= 41.6ps, 18 <= 55.4ps, 12 <= 62.4ps, 8 <= 65.8ps, 1 <= 69.3ps} + Clock DAG library cell distribution after 'Removing unconstrained drivers' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 44 + ICGs: ICGx3_ASAP7_75t_SL: 40 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Removing unconstrained drivers': + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.5, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Skew group summary after 'Removing unconstrained drivers': + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.5, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Clock network insertion delays are now [113.2ps, 172.5ps] average 143.5ps std.dev 15.8ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 16 succeeded with high effort: 16 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Removing unconstrained drivers done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Removing unconstrained drivers + Reducing insertion delay 1... + Clock DAG stats after 'Reducing insertion delay 1': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=184.758um^2, i=0.000um^2, icg=199.454um^2, nicg=0.000um^2, l=0.000um^2, total=384.212um^2 + cell capacitance : b=0.059pF, i=0.000pF, icg=0.072pF, nicg=0.000pF, l=0.000pF, total=0.131pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.045pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1864.404um, leaf=17423.095um, total=19287.499um + Clock DAG net violations after 'Reducing insertion delay 1': none + Clock DAG primary half-corner transition distribution after 'Reducing insertion delay 1': + Trunk : target=69.3ps count=41 avg=16.8ps sd=13.9ps min=8.7ps max=60.2ps {38 <= 41.6ps, 0 <= 55.4ps, 3 <= 62.4ps, 0 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=52.7ps sd=10.1ps min=24.4ps max=68.0ps {4 <= 41.6ps, 18 <= 55.4ps, 12 <= 62.4ps, 8 <= 65.8ps, 1 <= 69.3ps} + Clock DAG library cell distribution after 'Reducing insertion delay 1' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 44 + ICGs: ICGx3_ASAP7_75t_SL: 40 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Reducing insertion delay 1': + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.5, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Skew group summary after 'Reducing insertion delay 1': + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.5, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Clock network insertion delays are now [113.2ps, 172.5ps] average 143.5ps std.dev 15.8ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 14 succeeded with high effort: 14 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Reducing insertion delay 1 done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Reducing insertion delay 1 + Removing longest path buffering... + Clock DAG stats after 'Removing longest path buffering': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=184.758um^2, i=0.000um^2, icg=199.454um^2, nicg=0.000um^2, l=0.000um^2, total=384.212um^2 + cell capacitance : b=0.059pF, i=0.000pF, icg=0.072pF, nicg=0.000pF, l=0.000pF, total=0.131pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.045pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1864.404um, leaf=17423.095um, total=19287.499um + Clock DAG net violations after 'Removing longest path buffering': none + Clock DAG primary half-corner transition distribution after 'Removing longest path buffering': + Trunk : target=69.3ps count=41 avg=16.8ps sd=13.9ps min=8.7ps max=60.2ps {38 <= 41.6ps, 0 <= 55.4ps, 3 <= 62.4ps, 0 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=52.7ps sd=10.1ps min=24.4ps max=68.0ps {4 <= 41.6ps, 18 <= 55.4ps, 12 <= 62.4ps, 8 <= 65.8ps, 1 <= 69.3ps} + Clock DAG library cell distribution after 'Removing longest path buffering' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 44 + ICGs: ICGx3_ASAP7_75t_SL: 40 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Removing longest path buffering': + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.5, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Skew group summary after 'Removing longest path buffering': + skew_group clk/my_constraint_mode: insertion delay [min=113.2, max=172.5, avg=143.5, sd=15.8], skew [59.3 vs 33.6*], 70.5% {131.2, 164.8} (wid=60.3 ws=46.6) (gid=116.4 gs=33.1) + Clock network insertion delays are now [113.2ps, 172.5ps] average 143.5ps std.dev 15.8ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Removing longest path buffering done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Removing longest path buffering + Reducing insertion delay 2... + Info: CCOpt is analyzing the delay of a net driven by BUFx12f_ASAP7_75t_SRAM/Y using a timing arc from cell BUFx10_ASAP7_75t_SRAM + Info: CCOpt is analyzing the delay of a net driven by ICGx3_ASAP7_75t_SL/GCLK using a timing arc from cell ICGx2_ASAP7_75t_SL + Info: CCOpt is analyzing the delay of a net driven by ICGx2_ASAP7_75t_SL/GCLK using a timing arc from cell ICGx3_ASAP7_75t_SL + Clock DAG stats after 'Reducing insertion delay 2': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=184.758um^2, i=0.000um^2, icg=198.988um^2, nicg=0.000um^2, l=0.000um^2, total=383.746um^2 + cell capacitance : b=0.059pF, i=0.000pF, icg=0.072pF, nicg=0.000pF, l=0.000pF, total=0.131pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.452pF, total=0.498pF + wire lengths : top=0.000um, trunk=1887.680um, leaf=17439.189um, total=19326.869um + Clock DAG net violations after 'Reducing insertion delay 2': none + Clock DAG primary half-corner transition distribution after 'Reducing insertion delay 2': + Trunk : target=69.3ps count=41 avg=16.5ps sd=13.2ps min=8.7ps max=57.9ps {38 <= 41.6ps, 1 <= 55.4ps, 2 <= 62.4ps, 0 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=52.4ps sd=9.9ps min=24.4ps max=68.0ps {4 <= 41.6ps, 19 <= 55.4ps, 12 <= 62.4ps, 7 <= 65.8ps, 1 <= 69.3ps} + Clock DAG library cell distribution after 'Reducing insertion delay 2' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 44 + ICGs: ICGx3_ASAP7_75t_SL: 38 ICGx2_ASAP7_75t_SL: 3 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Reducing insertion delay 2': + skew_group clk/my_constraint_mode: insertion delay [min=111.1, max=160.1, avg=141.9, sd=14.8], skew [49.0 vs 33.6*], 78.6% {127.9, 160.1} (wid=56.6 ws=40.7) (gid=119.0 gs=37.0) + Skew group summary after 'Reducing insertion delay 2': + skew_group clk/my_constraint_mode: insertion delay [min=111.1, max=160.1, avg=141.9, sd=14.8], skew [49.0 vs 33.6*], 78.6% {127.9, 160.1} (wid=56.6 ws=40.7) (gid=119.0 gs=37.0) + Clock network insertion delays are now [111.1ps, 160.1ps] average 141.9ps std.dev 14.8ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 304 succeeded with high effort: 303 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 1 + Reducing insertion delay 2 done. (took cpu=0:00:01.1 real=0:00:01.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Reducing insertion delay 2 + Stage::Insertion Delay Reduction done. (took cpu=0:00:01.5 real=0:00:01.5) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Stage::Insertion Delay Reduction + CCOpt::Phase::Construction done. (took cpu=0:00:08.3 real=0:00:06.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: CCOpt::Phase::Construction + CCOpt::Phase::Implementation... + Stage::Reducing Power... + Improving clock tree routing... + Iteration 1... + Iteration 1 done. + Clock DAG stats after 'Improving clock tree routing': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=184.758um^2, i=0.000um^2, icg=198.988um^2, nicg=0.000um^2, l=0.000um^2, total=383.746um^2 + cell capacitance : b=0.059pF, i=0.000pF, icg=0.072pF, nicg=0.000pF, l=0.000pF, total=0.131pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.452pF, total=0.498pF + wire lengths : top=0.000um, trunk=1887.680um, leaf=17439.189um, total=19326.869um + Clock DAG net violations after 'Improving clock tree routing': none + Clock DAG primary half-corner transition distribution after 'Improving clock tree routing': + Trunk : target=69.3ps count=41 avg=16.5ps sd=13.2ps min=8.7ps max=57.9ps {38 <= 41.6ps, 1 <= 55.4ps, 2 <= 62.4ps, 0 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=52.4ps sd=9.9ps min=24.4ps max=68.0ps {4 <= 41.6ps, 19 <= 55.4ps, 12 <= 62.4ps, 7 <= 65.8ps, 1 <= 69.3ps} + Clock DAG library cell distribution after 'Improving clock tree routing' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 44 + ICGs: ICGx3_ASAP7_75t_SL: 38 ICGx2_ASAP7_75t_SL: 3 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Improving clock tree routing': + skew_group clk/my_constraint_mode: insertion delay [min=111.1, max=160.1, avg=141.9, sd=14.8], skew [49.0 vs 33.6*], 78.6% {127.9, 160.1} (wid=56.6 ws=40.7) (gid=119.0 gs=37.0) + Skew group summary after 'Improving clock tree routing': + skew_group clk/my_constraint_mode: insertion delay [min=111.1, max=160.1, avg=141.9, sd=14.8], skew [49.0 vs 33.6*], 78.6% {127.9, 160.1} (wid=56.6 ws=40.7) (gid=119.0 gs=37.0) + Clock network insertion delays are now [111.1ps, 160.1ps] average 141.9ps std.dev 14.8ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 30 succeeded with high effort: 30 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Improving clock tree routing done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Improving clock tree routing + Reducing clock tree power 1... + Resizing gates: ...20% ...40% ...60% ...80% ...Legalizing clock trees... + Legalizing clock trees done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Legalizing clock trees + 100% + Clock DAG stats after 'Reducing clock tree power 1': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.564um^2, i=0.000um^2, icg=189.890um^2, nicg=0.000um^2, l=0.000um^2, total=349.453um^2 + cell capacitance : b=0.045pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1888.508um, leaf=17410.442um, total=19298.950um + Clock DAG net violations after 'Reducing clock tree power 1': none + Clock DAG primary half-corner transition distribution after 'Reducing clock tree power 1': + Trunk : target=69.3ps count=41 avg=20.0ps sd=15.3ps min=9.1ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after 'Reducing clock tree power 1' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 2 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 13 ICGx2_ASAP7_75t_SL: 14 ICGx1_ASAP7_75t_SL: 14 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Reducing clock tree power 1': + skew_group clk/my_constraint_mode: insertion delay [min=117.1, max=154.5, avg=142.1, sd=10.1], skew [37.4 vs 33.6*], 96.4% {120.9, 154.5} (wid=54.7 ws=40.2) (gid=133.9 gs=38.9) + Skew group summary after 'Reducing clock tree power 1': + skew_group clk/my_constraint_mode: insertion delay [min=117.1, max=154.5, avg=142.1, sd=10.1], skew [37.4 vs 33.6*], 96.4% {120.9, 154.5} (wid=54.7 ws=40.2) (gid=133.9 gs=38.9) + Clock network insertion delays are now [117.1ps, 154.5ps] average 142.1ps std.dev 10.1ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 285 succeeded with high effort: 285 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Reducing clock tree power 1 done. (took cpu=0:00:01.8 real=0:00:00.7) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Reducing clock tree power 1 + Reducing clock tree power 2... + Info: CCOpt is analyzing the delay of a net driven by BUFx6f_ASAP7_75t_SRAM/Y using a timing arc from cell BUFx12f_ASAP7_75t_SRAM + Clock DAG stats after 'Reducing clock tree power 2': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=189.890um^2, nicg=0.000um^2, l=0.000um^2, total=348.987um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.788um, leaf=17410.442um, total=19298.230um + Clock DAG net violations after 'Reducing clock tree power 2': none + Clock DAG primary half-corner transition distribution after 'Reducing clock tree power 2': + Trunk : target=69.3ps count=41 avg=20.1ps sd=15.6ps min=9.1ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after 'Reducing clock tree power 2' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 13 ICGx2_ASAP7_75t_SL: 14 ICGx1_ASAP7_75t_SL: 14 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Reducing clock tree power 2': + skew_group clk/my_constraint_mode: insertion delay [min=124.4, max=154.1, avg=143.0, sd=7.3], skew [29.7 vs 33.6], 100% {124.4, 154.1} (wid=54.6 ws=40.1) (gid=131.9 gs=38.3) + Skew group summary after 'Reducing clock tree power 2': + skew_group clk/my_constraint_mode: insertion delay [min=124.4, max=154.1, avg=143.0, sd=7.3], skew [29.7 vs 33.6], 100% {124.4, 154.1} (wid=54.6 ws=40.1) (gid=131.9 gs=38.3) + Clock network insertion delays are now [124.4ps, 154.1ps] average 143.0ps std.dev 7.3ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 18 succeeded with high effort: 18 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Reducing clock tree power 2 done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Reducing clock tree power 2 + Stage::Reducing Power done. (took cpu=0:00:02.2 real=0:00:01.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Stage::Reducing Power + Stage::Balancing... + Approximately balancing fragments step... + Resolve constraints - Approximately balancing fragments... + Resolving skew group constraints... + Solving LP: 1 skew groups; 3 fragments, 3 fraglets and 4 vertices; 25 variables and 66 constraints; tolerance 1 + Resolving skew group constraints done. + Resolve constraints - Approximately balancing fragments done. (took cpu=0:00:00.2 real=0:00:00.2) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Resolve constraints - Approximately balancing fragments + Estimate delay to be added in balancing - Approximately balancing fragments... + Trial balancer estimated the amount of delay to be added in balancing: 0.0ps + Estimate delay to be added in balancing - Approximately balancing fragments done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Estimate delay to be added in balancing - Approximately balancing fragments + Approximately balancing fragments... + Moving gates to improve sub-tree skew... + Tried: 89 Succeeded: 0 + Topology Tried: 0 Succeeded: 0 + 0 Succeeded with SS ratio + 0 Succeeded with Lollipop: 0 with tier one, 0 with tier two. + Total reducing skew: 0 Average reducing skew for 0 nets : 0 + Clock DAG stats after 'Moving gates to improve sub-tree skew': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=189.890um^2, nicg=0.000um^2, l=0.000um^2, total=348.987um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.788um, leaf=17410.442um, total=19298.230um + Clock DAG net violations after 'Moving gates to improve sub-tree skew': none + Clock DAG primary half-corner transition distribution after 'Moving gates to improve sub-tree skew': + Trunk : target=69.3ps count=41 avg=20.1ps sd=15.6ps min=9.1ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after 'Moving gates to improve sub-tree skew' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 13 ICGx2_ASAP7_75t_SL: 14 ICGx1_ASAP7_75t_SL: 14 ICGx1_ASAP7_75t_SRAM: 2 + Clock network insertion delays are now [124.4ps, 154.1ps] average 143.0ps std.dev 7.3ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Moving gates to improve sub-tree skew done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Moving gates to improve sub-tree skew + Approximately balancing fragments bottom up... + bottom up balancing: Info: CCOpt is analyzing the delay of a net driven by BUFx10_ASAP7_75t_SRAM/Y using a timing arc from cell HB1xp67_ASAP7_75t_SRAM + Info: CCOpt is analyzing the delay of a net driven by ICGx1_ASAP7_75t_SL/GCLK using a timing arc from cell ICGx1_ASAP7_75t_SRAM + Info: CCOpt is analyzing the delay of a net driven by BUFx3_ASAP7_75t_SRAM/Y using a timing arc from cell HB1xp67_ASAP7_75t_SRAM + Info: CCOpt is analyzing the delay of a net driven by BUFx5_ASAP7_75t_SRAM/Y using a timing arc from cell HB1xp67_ASAP7_75t_SRAM + ...20% ...40% ...60% ...80% ...100% + Clock DAG stats after 'Approximately balancing fragments bottom up': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=188.957um^2, nicg=0.000um^2, l=0.000um^2, total=348.054um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.716um, leaf=17410.442um, total=19298.158um + Clock DAG net violations after 'Approximately balancing fragments bottom up': none + Clock DAG primary half-corner transition distribution after 'Approximately balancing fragments bottom up': + Trunk : target=69.3ps count=41 avg=20.6ps sd=15.4ps min=9.1ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after 'Approximately balancing fragments bottom up' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 12 ICGx2_ASAP7_75t_SL: 12 ICGx1_ASAP7_75t_SL: 17 ICGx1_ASAP7_75t_SRAM: 2 + Clock network insertion delays are now [124.4ps, 154.1ps] average 143.3ps std.dev 7.4ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 42 succeeded with high effort: 42 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Approximately balancing fragments bottom up done. (took cpu=0:00:00.5 real=0:00:00.5) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Approximately balancing fragments bottom up + Approximately balancing fragments, wire and cell delays... + Approximately balancing fragments, wire and cell delays, iteration 1... + Clock DAG stats after Approximately balancing fragments, wire and cell delays, iteration 1: + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=188.957um^2, nicg=0.000um^2, l=0.000um^2, total=348.054um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.716um, leaf=17410.442um, total=19298.158um + Clock DAG net violations after Approximately balancing fragments, wire and cell delays, iteration 1: none + Clock DAG primary half-corner transition distribution after Approximately balancing fragments, wire and cell delays, iteration 1: + Trunk : target=69.3ps count=41 avg=20.6ps sd=15.4ps min=9.1ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after Approximately balancing fragments, wire and cell delays, iteration 1 {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 12 ICGx2_ASAP7_75t_SL: 12 ICGx1_ASAP7_75t_SL: 17 ICGx1_ASAP7_75t_SRAM: 2 + Approximately balancing fragments, wire and cell delays, iteration 1 done. + Approximately balancing fragments, wire and cell delays done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Approximately balancing fragments, wire and cell delays + Approximately balancing fragments done. + Clock DAG stats after 'Approximately balancing fragments step': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=188.957um^2, nicg=0.000um^2, l=0.000um^2, total=348.054um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.716um, leaf=17410.442um, total=19298.158um + Clock DAG net violations after 'Approximately balancing fragments step': none + Clock DAG primary half-corner transition distribution after 'Approximately balancing fragments step': + Trunk : target=69.3ps count=41 avg=20.6ps sd=15.4ps min=9.1ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after 'Approximately balancing fragments step' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 12 ICGx2_ASAP7_75t_SL: 12 ICGx1_ASAP7_75t_SL: 17 ICGx1_ASAP7_75t_SRAM: 2 + Clock network insertion delays are now [124.4ps, 154.1ps] average 143.3ps std.dev 7.4ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 42 succeeded with high effort: 42 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Approximately balancing fragments step done. (took cpu=0:00:01.1 real=0:00:01.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Approximately balancing fragments step + Clock DAG stats after Approximately balancing fragments: + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=188.957um^2, nicg=0.000um^2, l=0.000um^2, total=348.054um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.716um, leaf=17410.442um, total=19298.158um + Clock DAG net violations after Approximately balancing fragments: none + Clock DAG primary half-corner transition distribution after Approximately balancing fragments: + Trunk : target=69.3ps count=41 avg=20.6ps sd=15.4ps min=9.1ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after Approximately balancing fragments {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 12 ICGx2_ASAP7_75t_SL: 12 ICGx1_ASAP7_75t_SL: 17 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after Approximately balancing fragments: + skew_group clk/my_constraint_mode: insertion delay [min=124.4, max=154.1, avg=143.3, sd=7.4], skew [29.7 vs 33.6], 100% {124.4, 154.1} (wid=54.6 ws=40.1) (gid=131.9 gs=38.3) + Skew group summary after Approximately balancing fragments: + skew_group clk/my_constraint_mode: insertion delay [min=124.4, max=154.1, avg=143.3, sd=7.4], skew [29.7 vs 33.6], 100% {124.4, 154.1} (wid=54.6 ws=40.1) (gid=131.9 gs=38.3) + Clock network insertion delays are now [124.4ps, 154.1ps] average 143.3ps std.dev 7.4ps + Improving fragments clock skew... + Clock DAG stats after 'Improving fragments clock skew': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=188.957um^2, nicg=0.000um^2, l=0.000um^2, total=348.054um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.716um, leaf=17410.442um, total=19298.158um + Clock DAG net violations after 'Improving fragments clock skew': none + Clock DAG primary half-corner transition distribution after 'Improving fragments clock skew': + Trunk : target=69.3ps count=41 avg=20.6ps sd=15.4ps min=9.1ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after 'Improving fragments clock skew' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 12 ICGx2_ASAP7_75t_SL: 12 ICGx1_ASAP7_75t_SL: 17 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Improving fragments clock skew': + skew_group clk/my_constraint_mode: insertion delay [min=124.4, max=154.1, avg=143.3, sd=7.4], skew [29.7 vs 33.6], 100% {124.4, 154.1} (wid=54.6 ws=40.1) (gid=131.9 gs=38.3) + Skew group summary after 'Improving fragments clock skew': + skew_group clk/my_constraint_mode: insertion delay [min=124.4, max=154.1, avg=143.3, sd=7.4], skew [29.7 vs 33.6], 100% {124.4, 154.1} (wid=54.6 ws=40.1) (gid=131.9 gs=38.3) + Clock network insertion delays are now [124.4ps, 154.1ps] average 143.3ps std.dev 7.4ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Improving fragments clock skew done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Improving fragments clock skew + Approximately balancing step... + Resolve constraints - Approximately balancing... + Resolving skew group constraints... + Solving LP: 1 skew groups; 3 fragments, 3 fraglets and 4 vertices; 25 variables and 66 constraints; tolerance 1 + Resolving skew group constraints done. + Resolve constraints - Approximately balancing done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Resolve constraints - Approximately balancing + Approximately balancing... + Approximately balancing, wire and cell delays... + Approximately balancing, wire and cell delays, iteration 1... + Clock DAG stats after Approximately balancing, wire and cell delays, iteration 1: + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=188.957um^2, nicg=0.000um^2, l=0.000um^2, total=348.054um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.716um, leaf=17410.442um, total=19298.158um + Clock DAG net violations after Approximately balancing, wire and cell delays, iteration 1: none + Clock DAG primary half-corner transition distribution after Approximately balancing, wire and cell delays, iteration 1: + Trunk : target=69.3ps count=41 avg=20.6ps sd=15.4ps min=9.1ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after Approximately balancing, wire and cell delays, iteration 1 {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 12 ICGx2_ASAP7_75t_SL: 12 ICGx1_ASAP7_75t_SL: 17 ICGx1_ASAP7_75t_SRAM: 2 + Approximately balancing, wire and cell delays, iteration 1 done. + Approximately balancing, wire and cell delays done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Approximately balancing, wire and cell delays + Approximately balancing done. + Clock DAG stats after 'Approximately balancing step': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=188.957um^2, nicg=0.000um^2, l=0.000um^2, total=348.054um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.716um, leaf=17410.442um, total=19298.158um + Clock DAG net violations after 'Approximately balancing step': none + Clock DAG primary half-corner transition distribution after 'Approximately balancing step': + Trunk : target=69.3ps count=41 avg=20.6ps sd=15.4ps min=9.1ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after 'Approximately balancing step' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 12 ICGx2_ASAP7_75t_SL: 12 ICGx1_ASAP7_75t_SL: 17 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Approximately balancing step': + skew_group clk/my_constraint_mode: insertion delay [min=124.4, max=154.1, avg=143.3, sd=7.4], skew [29.7 vs 33.6], 100% {124.4, 154.1} (wid=54.6 ws=40.1) (gid=131.9 gs=38.3) + Skew group summary after 'Approximately balancing step': + skew_group clk/my_constraint_mode: insertion delay [min=124.4, max=154.1, avg=143.3, sd=7.4], skew [29.7 vs 33.6], 100% {124.4, 154.1} (wid=54.6 ws=40.1) (gid=131.9 gs=38.3) + Clock network insertion delays are now [124.4ps, 154.1ps] average 143.3ps std.dev 7.4ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Approximately balancing step done. (took cpu=0:00:00.2 real=0:00:00.2) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Approximately balancing step + Fixing clock tree overload... + Fixing clock tree overload: ...20% ...40% ...60% ...80% ...100% + Clock DAG stats after 'Fixing clock tree overload': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=188.957um^2, nicg=0.000um^2, l=0.000um^2, total=348.054um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.716um, leaf=17410.442um, total=19298.158um + Clock DAG net violations after 'Fixing clock tree overload': none + Clock DAG primary half-corner transition distribution after 'Fixing clock tree overload': + Trunk : target=69.3ps count=41 avg=20.6ps sd=15.4ps min=9.1ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after 'Fixing clock tree overload' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 12 ICGx2_ASAP7_75t_SL: 12 ICGx1_ASAP7_75t_SL: 17 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Fixing clock tree overload': + skew_group clk/my_constraint_mode: insertion delay [min=124.4, max=154.1, avg=143.3, sd=7.4], skew [29.7 vs 33.6], 100% {124.4, 154.1} (wid=54.6 ws=40.1) (gid=131.9 gs=38.3) + Skew group summary after 'Fixing clock tree overload': + skew_group clk/my_constraint_mode: insertion delay [min=124.4, max=154.1, avg=143.3, sd=7.4], skew [29.7 vs 33.6], 100% {124.4, 154.1} (wid=54.6 ws=40.1) (gid=131.9 gs=38.3) + Clock network insertion delays are now [124.4ps, 154.1ps] average 143.3ps std.dev 7.4ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Fixing clock tree overload done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Fixing clock tree overload + Approximately balancing paths... + Added 0 buffers. + Clock DAG stats after 'Approximately balancing paths': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=188.957um^2, nicg=0.000um^2, l=0.000um^2, total=348.054um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.716um, leaf=17410.442um, total=19298.158um + Clock DAG net violations after 'Approximately balancing paths': none + Clock DAG primary half-corner transition distribution after 'Approximately balancing paths': + Trunk : target=69.3ps count=41 avg=20.6ps sd=15.4ps min=9.1ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after 'Approximately balancing paths' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 12 ICGx2_ASAP7_75t_SL: 12 ICGx1_ASAP7_75t_SL: 17 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Approximately balancing paths': + skew_group clk/my_constraint_mode: insertion delay [min=124.4, max=154.1, avg=143.3, sd=7.4], skew [29.7 vs 33.6], 100% {124.4, 154.1} (wid=54.6 ws=40.1) (gid=131.9 gs=38.3) + Skew group summary after 'Approximately balancing paths': + skew_group clk/my_constraint_mode: insertion delay [min=124.4, max=154.1, avg=143.3, sd=7.4], skew [29.7 vs 33.6], 100% {124.4, 154.1} (wid=54.6 ws=40.1) (gid=131.9 gs=38.3) + Clock network insertion delays are now [124.4ps, 154.1ps] average 143.3ps std.dev 7.4ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Approximately balancing paths done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Approximately balancing paths + Stage::Balancing done. (took cpu=0:00:01.7 real=0:00:01.7) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Stage::Balancing + Stage::Polishing... + Resynthesising clock tree into netlist... + Reset timing graph... +Ignoring AAE DB Resetting ... + Reset timing graph done. + Resynthesising clock tree into netlist done. + Updating congestion map to accurately time the clock tree... + Routing unrouted datapath nets connected to clock instances... + Routed 168 unrouted datapath nets connected to clock instances + Routing unrouted datapath nets connected to clock instances done. + Leaving CCOpt scope - extractRC... + Updating RC parasitics by calling: "extract_rc -noRouteCheck"... +Extraction called for design 'riscv_top' of instances=12053 and nets=12070 using extraction engine 'pre_route' . +pre_route RC Extraction called for design riscv_top. +RC Extraction called in multi-corner(2) mode. +RCMode: PreRoute + RC Corner Indexes 0 1 +Capacitance Scaling Factor : 1.00000 1.00000 +Resistance Scaling Factor : 1.00000 1.00000 +Clock Cap. Scaling Factor : 1.00000 1.00000 +Clock Res. Scaling Factor : 1.00000 1.00000 +Shrink Factor : 1.00000 +PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets. +Using Quantus QRC technology file ... +Updating RC grid for preRoute extraction ... +Initializing multi-corner resistance tables ... +PreRoute RC Extraction DONE (CPU Time: 0:00:00.2 Real Time: 0:00:00.0 MEM: 1848.324M) + Updating RC parasitics by calling: "extract_rc -noRouteCheck" done. + Leaving CCOpt scope - extractRC done. (took cpu=0:00:00.2 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Leaving CCOpt scope - extractRC + Updating congestion map to accurately time the clock tree done. + Disconnecting clock tree from netlist... + Disconnecting clock tree from netlist done. + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late... + Rebuilding timing graph... + Rebuilding timing graph done. + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late done. (took cpu=0:00:00.9 real=0:00:00.3) + Clock DAG stats After congestion update: + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=188.957um^2, nicg=0.000um^2, l=0.000um^2, total=348.054um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.716um, leaf=17410.442um, total=19298.158um + Clock DAG net violations After congestion update: none + Clock DAG primary half-corner transition distribution After congestion update: + Trunk : target=69.3ps count=41 avg=20.6ps sd=15.4ps min=9.2ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution After congestion update {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 12 ICGx2_ASAP7_75t_SL: 12 ICGx1_ASAP7_75t_SL: 17 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group After congestion update: + skew_group clk/my_constraint_mode: insertion delay [min=126.3, max=154.1, avg=143.1, sd=7.2], skew [27.8 vs 33.6], 100% {126.3, 154.1} (wid=54.5 ws=40.0) (gid=133.1 gs=37.6) + Skew group summary After congestion update: + skew_group clk/my_constraint_mode: insertion delay [min=126.3, max=154.1, avg=143.1, sd=7.2], skew [27.8 vs 33.6], 100% {126.3, 154.1} (wid=54.5 ws=40.0) (gid=133.1 gs=37.6) + Clock network insertion delays are now [126.3ps, 154.1ps] average 143.1ps std.dev 7.2ps + Merging balancing drivers for power... + Tried: 89 Succeeded: 0 + Clock DAG stats after 'Merging balancing drivers for power': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=188.957um^2, nicg=0.000um^2, l=0.000um^2, total=348.054um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.716um, leaf=17410.442um, total=19298.158um + Clock DAG net violations after 'Merging balancing drivers for power': none + Clock DAG primary half-corner transition distribution after 'Merging balancing drivers for power': + Trunk : target=69.3ps count=41 avg=20.6ps sd=15.4ps min=9.2ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after 'Merging balancing drivers for power' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 12 ICGx2_ASAP7_75t_SL: 12 ICGx1_ASAP7_75t_SL: 17 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Merging balancing drivers for power': + skew_group clk/my_constraint_mode: insertion delay [min=126.3, max=154.1, avg=143.1, sd=7.2], skew [27.8 vs 33.6], 100% {126.3, 154.1} (wid=54.5 ws=40.0) (gid=133.1 gs=37.6) + Skew group summary after 'Merging balancing drivers for power': + skew_group clk/my_constraint_mode: insertion delay [min=126.3, max=154.1, avg=143.1, sd=7.2], skew [27.8 vs 33.6], 100% {126.3, 154.1} (wid=54.5 ws=40.0) (gid=133.1 gs=37.6) + Clock network insertion delays are now [126.3ps, 154.1ps] average 143.1ps std.dev 7.2ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Merging balancing drivers for power done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Merging balancing drivers for power + Improving clock skew... + Clock DAG stats after 'Improving clock skew': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=159.097um^2, i=0.000um^2, icg=188.957um^2, nicg=0.000um^2, l=0.000um^2, total=348.054um^2 + cell capacitance : b=0.044pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.116pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1887.716um, leaf=17410.442um, total=19298.158um + Clock DAG net violations after 'Improving clock skew': none + Clock DAG primary half-corner transition distribution after 'Improving clock skew': + Trunk : target=69.3ps count=41 avg=20.6ps sd=15.4ps min=9.2ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=54.6ps sd=9.7ps min=24.8ps max=68.3ps {2 <= 41.6ps, 19 <= 55.4ps, 10 <= 62.4ps, 9 <= 65.8ps, 3 <= 69.3ps} + Clock DAG library cell distribution after 'Improving clock skew' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 23 BUFx10_ASAP7_75t_SRAM: 17 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 12 ICGx2_ASAP7_75t_SL: 12 ICGx1_ASAP7_75t_SL: 17 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Improving clock skew': + skew_group clk/my_constraint_mode: insertion delay [min=126.3, max=154.1, avg=143.1, sd=7.2], skew [27.8 vs 33.6], 100% {126.3, 154.1} (wid=54.5 ws=40.0) (gid=133.1 gs=37.6) + Skew group summary after 'Improving clock skew': + skew_group clk/my_constraint_mode: insertion delay [min=126.3, max=154.1, avg=143.1, sd=7.2], skew [27.8 vs 33.6], 100% {126.3, 154.1} (wid=54.5 ws=40.0) (gid=133.1 gs=37.6) + Clock network insertion delays are now [126.3ps, 154.1ps] average 143.1ps std.dev 7.2ps + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Improving clock skew done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Improving clock skew + Reducing clock tree power 3... + Initial gate capacitance is (rise=0.561pF fall=0.561pF). + Resizing gates: ...20% ...40% ...60% ...80% ...Legalizing clock trees... + Legalizing clock trees done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Legalizing clock trees + 100% + Iteration 1: gate capacitance is (rise=0.551pF fall=0.551pF). + Resizing gates: ...20% ...40% ...60% ...80% ...Legalizing clock trees... + Legalizing clock trees done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Legalizing clock trees + 100% + Stopping in iteration 2: unable to make further power recovery in this step. + Iteration 2: gate capacitance is (rise=0.551pF fall=0.551pF). + Clock DAG stats after 'Reducing clock tree power 3': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=144.167um^2, i=0.000um^2, icg=184.291um^2, nicg=0.000um^2, l=0.000um^2, total=328.458um^2 + cell capacitance : b=0.035pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.106pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1886.472um, leaf=17410.998um, total=19297.471um + Clock DAG net violations after 'Reducing clock tree power 3': none + Clock DAG primary half-corner transition distribution after 'Reducing clock tree power 3': + Trunk : target=69.3ps count=41 avg=21.7ps sd=15.2ps min=11.3ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=56.8ps sd=9.2ps min=24.8ps max=69.3ps {2 <= 41.6ps, 17 <= 55.4ps, 11 <= 62.4ps, 7 <= 65.8ps, 6 <= 69.3ps} + Clock DAG library cell distribution after 'Reducing clock tree power 3' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 8 BUFx10_ASAP7_75t_SRAM: 31 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 7 ICGx2_ASAP7_75t_SL: 2 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Reducing clock tree power 3': + skew_group clk/my_constraint_mode: insertion delay [min=131.9, max=165.4, avg=150.7, sd=8.7], skew [33.5 vs 33.6], 100% {131.9, 165.4} (wid=53.3 ws=40.6) (gid=142.8 gs=40.0) + Skew group summary after 'Reducing clock tree power 3': + skew_group clk/my_constraint_mode: insertion delay [min=131.9, max=165.4, avg=150.7, sd=8.7], skew [33.5 vs 33.6], 100% {131.9, 165.4} (wid=53.3 ws=40.6) (gid=142.8 gs=40.0) + Clock network insertion delays are now [131.9ps, 165.4ps] average 150.7ps std.dev 8.7ps + BalancingStep Reducing clock tree power 3 has increased max latencies (wire and cell) to be greater than the max desired latencies + {clk/my_constraint_mode,WC: 154.5 -> 165.4}Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 403 succeeded with high effort: 403 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Reducing clock tree power 3 done. (took cpu=0:00:02.2 real=0:00:00.9) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Reducing clock tree power 3 + Improving insertion delay... + Clock DAG stats after 'Improving insertion delay': + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=146.033um^2, i=0.000um^2, icg=184.291um^2, nicg=0.000um^2, l=0.000um^2, total=330.324um^2 + cell capacitance : b=0.035pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.106pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.451pF, total=0.497pF + wire lengths : top=0.000um, trunk=1880.732um, leaf=17410.998um, total=19291.731um + Clock DAG net violations after 'Improving insertion delay': none + Clock DAG primary half-corner transition distribution after 'Improving insertion delay': + Trunk : target=69.3ps count=41 avg=21.6ps sd=15.1ps min=11.3ps max=64.1ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.0ps sd=0.1ps min=7.0ps max=7.1ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=56.8ps sd=9.2ps min=24.8ps max=69.3ps {2 <= 41.6ps, 17 <= 55.4ps, 11 <= 62.4ps, 7 <= 65.8ps, 6 <= 69.3ps} + Clock DAG library cell distribution after 'Improving insertion delay' {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 31 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 7 ICGx2_ASAP7_75t_SL: 2 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after 'Improving insertion delay': + skew_group clk/my_constraint_mode: insertion delay [min=123.9, max=159.1, avg=144.1, sd=8.7], skew [35.2 vs 33.6*], 99.9% {126.0, 159.1} (wid=54.6 ws=40.6) (gid=133.6 gs=40.0) + Skew group summary after 'Improving insertion delay': + skew_group clk/my_constraint_mode: insertion delay [min=123.9, max=159.1, avg=144.1, sd=8.7], skew [35.2 vs 33.6*], 99.9% {126.0, 159.1} (wid=54.6 ws=40.6) (gid=133.6 gs=40.0) + Clock network insertion delays are now [123.9ps, 159.1ps] average 144.1ps std.dev 8.7ps + BalancingStep Improving insertion delay has increased max latencies (wire and cell) to be greater than the max desired latencies + {clk/my_constraint_mode,WC: 154.5 -> 159.1}Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 62 succeeded with high effort: 62 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Improving insertion delay done. (took cpu=0:00:00.3 real=0:00:00.3) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Improving insertion delay + Total capacitance is (rise=1.049pF fall=1.049pF), of which (rise=0.497pF fall=0.497pF) is wire, and (rise=0.552pF fall=0.552pF) is gate. + Stage::Polishing done. (took cpu=0:00:04.1 real=0:00:02.2) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Stage::Polishing + Stage::Updating netlist... + Reset timing graph... +Ignoring AAE DB Resetting ... + Reset timing graph done. + Setting non-default rules before calling refine place. + ClockRefiner... + Performing Clock Only Refine Place. +*** Starting place_detail (0:08:14 mem=2044.8M) *** +Total net bbox length = 2.540e+05 (1.010e+05 1.531e+05) (ext = 3.759e+04) +Move report: Detail placement moves 0 insts, mean move: 0.00 um, max move: 0.00 um + Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM: 2044.8MB +Summary Report: +Instances move: 0 (out of 9226 movable) +Instances flipped: 0 +Mean displacement: 0.00 um +Max displacement: 0.00 um +Total net bbox length = 2.540e+05 (1.010e+05 1.531e+05) (ext = 3.759e+04) +Runtime: CPU: 0:00:00.1 REAL: 0:00:00.0 MEM: 2044.8MB +*** Finished place_detail (0:08:15 mem=2044.8M) *** + Moved 0, flipped 0 and cell swapped 0 of 1392 clock instance(s) during refinement. + The largest move was 0 microns for . + ClockRefiner done. (took cpu=0:00:00.4 real=0:00:00.3) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: ClockRefiner + Stage::Updating netlist done. (took cpu=0:00:00.5 real=0:00:00.4) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Stage::Updating netlist + CCOpt::Phase::Implementation done. (took cpu=0:00:08.7 real=0:00:05.5) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: CCOpt::Phase::Implementation + CCOpt::Phase::eGRPC... + eGR Post Conditioning loop iteration 0... + Clock implementation routing... + Leaving CCOpt scope - Routing Tools... +Net route status summary: + Clock: 88 (unrouted=77, trialRouted=0, noStatus=0, routed=0, fixed=11, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)]) + Non-clock: 11982 (unrouted=2491, trialRouted=9491, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=2405, (crossesIlmBoundary AND tooFewTerms=0)]) + Routing using eGR only... + Early Global Route - eGR only step... +(ccopt eGR): There are 88 nets for routing of which 88 have one or more fixed wires. +(ccopt eGR): Start to route 88 all nets +[NR-eGR] honorMsvRouteConstraint: false +[NR-eGR] honorClockSpecNDR : 0 +[NR-eGR] minRouteLayer : 2 +[NR-eGR] maxRouteLayer : 7 +[NR-eGR] numTracksPerClockWire : 0 +[NR-eGR] M1 has no routable track +[NR-eGR] M2 has non-uniform track structures +[NR-eGR] M3 has single uniform track structure +[NR-eGR] M4 has single uniform track structure +[NR-eGR] M5 has single uniform track structure +[NR-eGR] M6 has single uniform track structure +[NR-eGR] M7 has single uniform track structure +[NR-eGR] Read 127360 PG shapes in 0.010 seconds + +[NR-eGR] numRoutingBlks=0 numInstBlks=2389 numPGBlocks=127360 numBumpBlks=0 numBoundaryFakeBlks=0 +[NR-eGR] Num Prerouted Nets = 0 Num Prerouted Wires = 0 +[NR-eGR] Read numTotalNets=9665 numIgnoredNets=9577 +[NR-eGR] Connected 0 must-join pins/ports +[NR-eGR] There are 88 clock nets ( 88 with NDR ). +[NR-eGR] ============ Routing rule table ============ +[NR-eGR] Rule id: 0 Nets: 88 +[NR-eGR] Rule id: 1 Nets: 0 +[NR-eGR] ======================================== +[NR-eGR] +[NR-eGR] Layer group 1: route 88 net(s) in layer range [3, 4] +[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.01% H + 0.00% V. EstWL: 1.950048e+04um +[NR-eGR] +[NR-eGR] Move 40 nets to layer range [3, 6] +[NR-eGR] Layer group 2: route 40 net(s) in layer range [3, 6] +[NR-eGR] earlyGlobalRoute overflow of layer group 2: 0.00% H + 0.00% V. EstWL: 1.669896e+04um +[NR-eGR] +[NR-eGR] Move 37 nets to layer range [3, 7] +[NR-eGR] Layer group 3: route 37 net(s) in layer range [3, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 3: 0.00% H + 0.00% V. EstWL: 1.623672e+04um +[NR-eGR] +[NR-eGR] Move 11 nets to layer range [2, 7] +[NR-eGR] Layer group 4: route 11 net(s) in layer range [2, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 4: 0.00% H + 0.00% V. EstWL: 9.987840e+03um +[NR-eGR] +[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded) +[NR-eGR] OverCon OverCon OverCon +[NR-eGR] #Gcell #Gcell #Gcell %Gcell +[NR-eGR] Layer (1-2) (3-4) (5-6) OverCon +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] M1 (1) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M2 (2) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M3 (3) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M4 (4) 56( 0.19%) 5( 0.02%) 1( 0.00%) ( 0.22%) +[NR-eGR] M5 (5) 3( 0.01%) 0( 0.00%) 0( 0.00%) ( 0.01%) +[NR-eGR] M6 (6) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M7 (7) 3( 0.01%) 0( 0.00%) 0( 0.00%) ( 0.01%) +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] Total 62( 0.04%) 5( 0.00%) 1( 0.00%) ( 0.04%) +[NR-eGR] +[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.00% H + 0.00% V +[NR-eGR] Overflow after earlyGlobalRoute 0.00% H + 0.00% V +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] M1 (1F) length: 0.000000e+00um, number of vias: 31801 +[NR-eGR] M2 (2H) length: 6.122044e+04um, number of vias: 47229 +[NR-eGR] M3 (3V) length: 8.634517e+04um, number of vias: 9654 +[NR-eGR] M4 (4H) length: 4.502572e+04um, number of vias: 6870 +[NR-eGR] M5 (5V) length: 4.945998e+04um, number of vias: 2033 +[NR-eGR] M6 (6H) length: 1.919275e+04um, number of vias: 1101 +[NR-eGR] M7 (7V) length: 3.066611e+04um, number of vias: 0 +[NR-eGR] Total length: 2.919102e+05um, number of vias: 98688 +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] Total eGR-routed clock nets wire length: 1.954334e+04um +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] Report for selected net(s) only. +[NR-eGR] M1 (1V) length: 0.000000e+00um, number of vias: 1432 +[NR-eGR] M2 (2H) length: 9.358000e+02um, number of vias: 1550 +[NR-eGR] M3 (3V) length: 5.601804e+03um, number of vias: 1233 +[NR-eGR] M4 (4H) length: 8.511532e+03um, number of vias: 488 +[NR-eGR] M5 (5V) length: 3.453408e+03um, number of vias: 107 +[NR-eGR] M6 (6H) length: 5.554080e+02um, number of vias: 34 +[NR-eGR] M7 (7V) length: 4.853880e+02um, number of vias: 0 +[NR-eGR] Total length: 1.954334e+04um, number of vias: 4844 +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] Total routed clock nets wire length: 1.954334e+04um, number of vias: 4844 +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] End Peak syMemory usage = 1845.0 MB +[NR-eGR] Early Global Router Kernel+IO runtime : 0.29 seconds + Early Global Route - eGR only step done. (took cpu=0:00:00.3 real=0:00:00.3) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Early Global Route - eGR only step +Set FIXED routing status on 88 net(s) + Routing using eGR only done. +Net route status summary: + Clock: 88 (unrouted=0, trialRouted=0, noStatus=0, routed=0, fixed=88, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)]) + Non-clock: 11982 (unrouted=2491, trialRouted=9491, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=2405, (crossesIlmBoundary AND tooFewTerms=0)]) + +CCOPT: Done with clock implementation routing. + + Leaving CCOpt scope - Routing Tools done. (took cpu=0:00:00.4 real=0:00:00.4) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Leaving CCOpt scope - Routing Tools + Clock implementation routing done. + Leaving CCOpt scope - extractRC... + Updating RC parasitics by calling: "extract_rc -noRouteCheck"... +Extraction called for design 'riscv_top' of instances=12053 and nets=12070 using extraction engine 'pre_route' . +pre_route RC Extraction called for design riscv_top. +RC Extraction called in multi-corner(2) mode. +RCMode: PreRoute + RC Corner Indexes 0 1 +Capacitance Scaling Factor : 1.00000 1.00000 +Resistance Scaling Factor : 1.00000 1.00000 +Clock Cap. Scaling Factor : 1.00000 1.00000 +Clock Res. Scaling Factor : 1.00000 1.00000 +Shrink Factor : 1.00000 +PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets. +Using Quantus QRC technology file ... +Updating RC grid for preRoute extraction ... +Initializing multi-corner resistance tables ... +PreRoute RC Extraction DONE (CPU Time: 0:00:00.2 Real Time: 0:00:00.0 MEM: 1845.004M) + Updating RC parasitics by calling: "extract_rc -noRouteCheck" done. + Leaving CCOpt scope - extractRC done. (took cpu=0:00:00.2 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Leaving CCOpt scope - extractRC + Calling post conditioning for eGRPC... + eGRPC... + eGRPC active optimizations: + - Move Down + - Downsizing before DRV sizing + - DRV fixing with cell sizing + - Move to fanout + - Cloning + + Currently running CTS, using active skew data + Reset bufferability constraints... + Resetting previous bufferability status on all nets so that eGRPC will attempt to fix all clock tree violations. + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late... + Rebuilding timing graph... + Rebuilding timing graph done. + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late done. (took cpu=0:00:00.9 real=0:00:00.3) + Reset bufferability constraints done. (took cpu=0:00:00.9 real=0:00:00.3) + Clock DAG stats eGRPC initial state: + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=146.033um^2, i=0.000um^2, icg=184.291um^2, nicg=0.000um^2, l=0.000um^2, total=330.324um^2 + cell capacitance : b=0.035pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.106pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.464pF, total=0.510pF + wire lengths : top=0.000um, trunk=1900.788um, leaf=17642.552um, total=19543.340um + Clock DAG net violations eGRPC initial state: + Remaining Transition : {count=1, worst=[0.2ps]} avg=0.2ps sd=0.0ps sum=0.2ps + Clock DAG primary half-corner transition distribution eGRPC initial state: + Trunk : target=69.3ps count=41 avg=21.7ps sd=15.2ps min=11.5ps max=64.3ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.2ps sd=0.4ps min=7.0ps max=7.8ps {0 <= 4.8ps, 0 <= 6.4ps, 3 <= 7.2ps, 0 <= 7.6ps, 1 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=55.3ps sd=8.8ps min=24.7ps max=69.5ps {2 <= 41.6ps, 21 <= 55.4ps, 12 <= 62.4ps, 4 <= 65.8ps, 3 <= 69.3ps} {1 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution eGRPC initial state {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 31 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 7 ICGx2_ASAP7_75t_SL: 2 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group eGRPC initial state: + skew_group clk/my_constraint_mode: insertion delay [min=126.6, max=160.5, avg=145.6, sd=8.3], skew [33.9 vs 33.6*], 99.8% {126.6, 160.2} (wid=54.9 ws=40.8) (gid=134.2 gs=34.3) + Skew group summary eGRPC initial state: + skew_group clk/my_constraint_mode: insertion delay [min=126.6, max=160.5, avg=145.6, sd=8.3], skew [33.9 vs 33.6*], 99.8% {126.6, 160.2} (wid=54.9 ws=40.8) (gid=134.2 gs=34.3) + Clock network insertion delays are now [126.6ps, 160.5ps] average 145.6ps std.dev 8.3ps + Moving buffers... + Violation analysis... + Analysising clock tree DRVs: Analysising clock tree DRVs: Done + Violation analysis done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Violation analysis + Clock DAG stats eGRPC after moving buffers: + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=146.033um^2, i=0.000um^2, icg=184.291um^2, nicg=0.000um^2, l=0.000um^2, total=330.324um^2 + cell capacitance : b=0.035pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.106pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.464pF, total=0.510pF + wire lengths : top=0.000um, trunk=1900.788um, leaf=17642.552um, total=19543.340um + Clock DAG net violations eGRPC after moving buffers: + Remaining Transition : {count=1, worst=[0.2ps]} avg=0.2ps sd=0.0ps sum=0.2ps + Clock DAG primary half-corner transition distribution eGRPC after moving buffers: + Trunk : target=69.3ps count=41 avg=21.7ps sd=15.2ps min=11.5ps max=64.3ps {35 <= 41.6ps, 3 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.2ps sd=0.4ps min=7.0ps max=7.8ps {0 <= 4.8ps, 0 <= 6.4ps, 3 <= 7.2ps, 0 <= 7.6ps, 1 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=55.3ps sd=8.8ps min=24.7ps max=69.5ps {2 <= 41.6ps, 21 <= 55.4ps, 12 <= 62.4ps, 4 <= 65.8ps, 3 <= 69.3ps} {1 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution eGRPC after moving buffers {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 31 BUFx6f_ASAP7_75t_SRAM: 1 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 7 ICGx2_ASAP7_75t_SL: 2 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group eGRPC after moving buffers: + skew_group clk/my_constraint_mode: insertion delay [min=126.6, max=160.5, avg=145.6, sd=8.3], skew [33.9 vs 33.6*], 99.8% {126.6, 160.2} (wid=54.9 ws=40.8) (gid=134.2 gs=34.3) + Skew group summary eGRPC after moving buffers: + skew_group clk/my_constraint_mode: insertion delay [min=126.6, max=160.5, avg=145.6, sd=8.3], skew [33.9 vs 33.6*], 99.8% {126.6, 160.2} (wid=54.9 ws=40.8) (gid=134.2 gs=34.3) + Clock network insertion delays are now [126.6ps, 160.5ps] average 145.6ps std.dev 8.3ps + Moving buffers done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Moving buffers + Initial Pass of Downsizing Clock Tree Cells... + Artificially removing long paths... + Artificially shortened 222 long paths. The largest offset applied was 6.6ps. + + + Skew Group Offsets: + + --------------------------------------------------------------------------------------------------- + Skew Group Num. Num. Offset Max Previous Max. Current Max. + Sinks Offsets Percentile Offset Path Delay Path Delay + --------------------------------------------------------------------------------------------------- + clk/my_constraint_mode 1305 222 17.011% 6.6ps 160.5ps 153.9ps + --------------------------------------------------------------------------------------------------- + + Offsets Histogram: + + ------------------------------- + From (ps) To (ps) Count + ------------------------------- + below 0.0 5 + 0.0 5.0 203 + 5.0 and above 14 + ------------------------------- + + Mean=2.3ps Median=2.2ps Std.Dev=1.5ps + + + Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Artificially removing long paths done. (took cpu=0:00:00.0 real=0:00:00.0) + Modifying slew-target multiplier from 1 to 0.9 + Downsizing prefiltering... + Downsizing prefiltering done. + Downsizing: ...20% ...40% ...60% ...80% ...100% + DoDownSizing Summary : numSized = 1, numUnchanged = 60, numSkippedDueToOther = 0, numSkippedDueToCloseToSlewTarget = 27, numSkippedDueToCloseToSkewTarget = 0 + CCOpt-eGRPC Downsizing: considered: 61, tested: 0, violation detected: 0, violation ignored (due to small violation): 0, cannot run: 1, attempted: 60, unsuccessful: 0, sized: 1 + Downsizing prefiltering... + Downsizing prefiltering done. + Downsizing: ...20% ...40% ...60% ...80% ...100% + DoDownSizing Summary : numSized = 0, numUnchanged = 1, numSkippedDueToOther = 0, numSkippedDueToCloseToSlewTarget = 0, numSkippedDueToCloseToSkewTarget = 0 + CCOpt-eGRPC Downsizing: considered: 1, tested: 0, violation detected: 0, violation ignored (due to small violation): 0, cannot run: 0, attempted: 1, unsuccessful: 0, sized: 0 + Reverting slew-target multiplier from 0.9 to 1 + Reverting Artificially removing long paths... + BalancingStep Reverting Artificially removing long paths has increased max latencies (wire and cell) to be greater than the max desired latencies + {clk/my_constraint_mode,WC: 154.5 -> 159.8}Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0 succeeded with window specified: 0 unsuccessful with window specified: 0 + Legalizer new API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0 + Reverting Artificially removing long paths done. (took cpu=0:00:00.0 real=0:00:00.0) + Clock DAG stats eGRPC after downsizing: + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=145.100um^2, i=0.000um^2, icg=184.291um^2, nicg=0.000um^2, l=0.000um^2, total=329.391um^2 + cell capacitance : b=0.035pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.106pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.464pF, total=0.510pF + wire lengths : top=0.000um, trunk=1900.788um, leaf=17642.552um, total=19543.340um + Clock DAG net violations eGRPC after downsizing: + Remaining Transition : {count=1, worst=[0.2ps]} avg=0.2ps sd=0.0ps sum=0.2ps + Clock DAG primary half-corner transition distribution eGRPC after downsizing: + Trunk : target=69.3ps count=41 avg=22.2ps sd=15.7ps min=11.5ps max=64.3ps {34 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.2ps sd=0.4ps min=7.0ps max=7.8ps {0 <= 4.8ps, 0 <= 6.4ps, 3 <= 7.2ps, 0 <= 7.6ps, 1 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=55.3ps sd=8.8ps min=24.7ps max=69.5ps {2 <= 41.6ps, 21 <= 55.4ps, 12 <= 62.4ps, 4 <= 65.8ps, 3 <= 69.3ps} {1 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution eGRPC after downsizing {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 30 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 7 ICGx2_ASAP7_75t_SL: 2 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group eGRPC after downsizing: + skew_group clk/my_constraint_mode: insertion delay [min=126.6, max=159.8, avg=145.2, sd=8.3], skew [33.2 vs 33.6], 100% {126.6, 159.8} (wid=54.5 ws=40.4) (gid=134.2 gs=35.3) + Skew group summary eGRPC after downsizing: + skew_group clk/my_constraint_mode: insertion delay [min=126.6, max=159.8, avg=145.2, sd=8.3], skew [33.2 vs 33.6], 100% {126.6, 159.8} (wid=54.5 ws=40.4) (gid=134.2 gs=35.3) + Clock network insertion delays are now [126.6ps, 159.8ps] average 145.2ps std.dev 8.3ps + Initial Pass of Downsizing Clock Tree Cells done. (took cpu=0:00:01.0 real=0:00:01.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Initial Pass of Downsizing Clock Tree Cells + Fixing DRVs... + Fixing clock tree DRVs: ...20% ...40% ...60% ...80% ...100% + CCOpt-eGRPC: considered: 88, tested: 88, violation detected: 1, violation ignored (due to small violation): 1, cannot run: 0, attempted: 0, unsuccessful: 0, sized: 0 + + PRO Statistics: Fix DRVs (cell sizing): + ======================================= + + Cell changes by Net Type: + + --------------------------------------------------------------------------------------------------------- + Net Type Attempted Upsized Downsized Swapped Same Size Total Changed Not Sized + --------------------------------------------------------------------------------------------------------- + top 0 0 0 0 0 0 + trunk 0 0 0 0 0 0 + leaf 0 0 0 0 0 0 + --------------------------------------------------------------------------------------------------------- + Total - - - - 0 (100%) 0 (100%) + --------------------------------------------------------------------------------------------------------- + + Upsized: 0, Downsized: 0, Sized but same area: 0, Unchanged: 0, Area change: 0.000um^2 (0.000%) + Max. move: 0.000um, Min. move: 0.000um, Avg. move: N/A + + Clock DAG stats eGRPC after DRV fixing: + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=145.100um^2, i=0.000um^2, icg=184.291um^2, nicg=0.000um^2, l=0.000um^2, total=329.391um^2 + cell capacitance : b=0.035pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.106pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.464pF, total=0.510pF + wire lengths : top=0.000um, trunk=1900.788um, leaf=17642.552um, total=19543.340um + Clock DAG net violations eGRPC after DRV fixing: + Remaining Transition : {count=1, worst=[0.2ps]} avg=0.2ps sd=0.0ps sum=0.2ps + Clock DAG primary half-corner transition distribution eGRPC after DRV fixing: + Trunk : target=69.3ps count=41 avg=22.2ps sd=15.7ps min=11.5ps max=64.3ps {34 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.2ps sd=0.4ps min=7.0ps max=7.8ps {0 <= 4.8ps, 0 <= 6.4ps, 3 <= 7.2ps, 0 <= 7.6ps, 1 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=55.3ps sd=8.8ps min=24.7ps max=69.5ps {2 <= 41.6ps, 21 <= 55.4ps, 12 <= 62.4ps, 4 <= 65.8ps, 3 <= 69.3ps} {1 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution eGRPC after DRV fixing {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 30 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 7 ICGx2_ASAP7_75t_SL: 2 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group eGRPC after DRV fixing: + skew_group clk/my_constraint_mode: insertion delay [min=126.6, max=159.8, avg=145.2, sd=8.3], skew [33.2 vs 33.6], 100% {126.6, 159.8} (wid=54.5 ws=40.4) (gid=134.2 gs=35.3) + Skew group summary eGRPC after DRV fixing: + skew_group clk/my_constraint_mode: insertion delay [min=126.6, max=159.8, avg=145.2, sd=8.3], skew [33.2 vs 33.6], 100% {126.6, 159.8} (wid=54.5 ws=40.4) (gid=134.2 gs=35.3) + Clock network insertion delays are now [126.6ps, 159.8ps] average 145.2ps std.dev 8.3ps + Fixing DRVs done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Fixing DRVs + Reconnecting optimized routes... + Reset timing graph... +Ignoring AAE DB Resetting ... + Reset timing graph done. + Reconnecting optimized routes done. (took cpu=0:00:00.0 real=0:00:00.0) + Violation analysis... + Analysising clock tree DRVs: Rebuilding timing graph... + Rebuilding timing graph done. + Analysising clock tree DRVs: Done + Violation analysis done. (took cpu=0:00:00.7 real=0:00:00.3) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Violation analysis + Moving clock insts towards fanout... + Move to sink centre: considered=1, unsuccessful=0, alreadyClose=0, noImprovementFound=1, degradedSlew=0, degradedSkew=0, insufficientImprovement=0, accepted=0 + Moving clock insts towards fanout done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Moving clock insts towards fanout + Reset timing graph... +Ignoring AAE DB Resetting ... + Reset timing graph done. + Set dirty flag on 62 insts, 124 nets + Rebuilding timing graph... + Rebuilding timing graph done. + Clock DAG stats before routing clock trees: + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=145.100um^2, i=0.000um^2, icg=184.291um^2, nicg=0.000um^2, l=0.000um^2, total=329.391um^2 + cell capacitance : b=0.035pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.106pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.464pF, total=0.510pF + wire lengths : top=0.000um, trunk=1900.788um, leaf=17642.552um, total=19543.340um + Clock DAG net violations before routing clock trees: + Remaining Transition : {count=1, worst=[0.2ps]} avg=0.2ps sd=0.0ps sum=0.2ps + Clock DAG primary half-corner transition distribution before routing clock trees: + Trunk : target=69.3ps count=41 avg=22.2ps sd=15.7ps min=11.5ps max=64.3ps {34 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.2ps sd=0.4ps min=7.0ps max=7.8ps {0 <= 4.8ps, 0 <= 6.4ps, 3 <= 7.2ps, 0 <= 7.6ps, 1 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=55.3ps sd=8.8ps min=24.7ps max=69.5ps {2 <= 41.6ps, 21 <= 55.4ps, 12 <= 62.4ps, 4 <= 65.8ps, 3 <= 69.3ps} {1 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution before routing clock trees {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 30 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 7 ICGx2_ASAP7_75t_SL: 2 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group before routing clock trees: + skew_group clk/my_constraint_mode: insertion delay [min=126.6, max=159.8, avg=145.2, sd=8.3], skew [33.2 vs 33.6], 100% {126.6, 159.8} (wid=54.5 ws=40.4) (gid=134.2 gs=35.3) + Skew group summary before routing clock trees: + skew_group clk/my_constraint_mode: insertion delay [min=126.6, max=159.8, avg=145.2, sd=8.3], skew [33.2 vs 33.6], 100% {126.6, 159.8} (wid=54.5 ws=40.4) (gid=134.2 gs=35.3) + Clock network insertion delays are now [126.6ps, 159.8ps] average 145.2ps std.dev 8.3ps + eGRPC done. + Calling post conditioning for eGRPC done. + eGR Post Conditioning loop iteration 0 done. + Refine place not called during Post Conditioning. Calling it now the eGR->PC Loop is complete. + ClockRefiner... + Performing Single Pass Refine Place. +*** Starting place_detail (0:08:20 mem=2049.3M) *** +Total net bbox length = 2.540e+05 (1.010e+05 1.531e+05) (ext = 3.759e+04) +Move report: Detail placement moves 19 insts, mean move: 0.72 um, max move: 1.51 um + Max move on inst (cpu/stage1/pcselmux/g987__8428): (213.41, 91.80) --> (214.92, 91.80) + Runtime: CPU: 0:00:02.3 REAL: 0:00:01.0 MEM: 2049.3MB +Summary Report: +Instances move: 19 (out of 9226 movable) +Instances flipped: 0 +Mean displacement: 0.72 um +Max displacement: 1.51 um (Instance: cpu/stage1/pcselmux/g987__8428) (213.408, 91.8) -> (214.92, 91.8) + Length: 6 sites, height: 1 rows, site name: coreSite, cell type: AO21x1_ASAP7_75t_SL +Total net bbox length = 2.540e+05 (1.010e+05 1.531e+05) (ext = 3.759e+04) +Runtime: CPU: 0:00:02.4 REAL: 0:00:01.0 MEM: 2049.3MB +*** Finished place_detail (0:08:22 mem=2049.3M) *** + Moved 0, flipped 0 and cell swapped 0 of 1392 clock instance(s) during refinement. + The largest move was 0 microns for . + ClockRefiner done. (took cpu=0:00:02.7 real=0:00:01.3) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: ClockRefiner + CCOpt::Phase::eGRPC done. (took cpu=0:00:07.5 real=0:00:04.5) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: CCOpt::Phase::eGRPC + CCOpt::Phase::Routing... + Clock implementation routing... + Leaving CCOpt scope - Routing Tools... +Net route status summary: + Clock: 88 (unrouted=0, trialRouted=0, noStatus=0, routed=0, fixed=88, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)]) + Non-clock: 11982 (unrouted=2491, trialRouted=9491, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=2405, (crossesIlmBoundary AND tooFewTerms=0)]) + Routing using eGR in eGR->NR Step... + Early Global Route - eGR->NR step... +(ccopt eGR): There are 88 nets for routing of which 88 have one or more fixed wires. +(ccopt eGR): Start to route 88 all nets +[NR-eGR] honorMsvRouteConstraint: false +[NR-eGR] honorClockSpecNDR : 0 +[NR-eGR] minRouteLayer : 2 +[NR-eGR] maxRouteLayer : 7 +[NR-eGR] numTracksPerClockWire : 0 +[NR-eGR] M1 has no routable track +[NR-eGR] M2 has non-uniform track structures +[NR-eGR] M3 has single uniform track structure +[NR-eGR] M4 has single uniform track structure +[NR-eGR] M5 has single uniform track structure +[NR-eGR] M6 has single uniform track structure +[NR-eGR] M7 has single uniform track structure +[NR-eGR] Read 127360 PG shapes in 0.010 seconds + +[NR-eGR] numRoutingBlks=0 numInstBlks=2389 numPGBlocks=127360 numBumpBlks=0 numBoundaryFakeBlks=0 +[NR-eGR] Num Prerouted Nets = 0 Num Prerouted Wires = 0 +[NR-eGR] Read numTotalNets=9665 numIgnoredNets=9577 +[NR-eGR] Connected 0 must-join pins/ports +[NR-eGR] There are 88 clock nets ( 88 with NDR ). +[NR-eGR] ============ Routing rule table ============ +[NR-eGR] Rule id: 0 Nets: 88 +[NR-eGR] Rule id: 1 Nets: 0 +[NR-eGR] ======================================== +[NR-eGR] +[NR-eGR] Layer group 1: route 88 net(s) in layer range [3, 4] +[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.01% H + 0.00% V. EstWL: 1.950696e+04um +[NR-eGR] +[NR-eGR] Move 40 nets to layer range [3, 6] +[NR-eGR] Layer group 2: route 40 net(s) in layer range [3, 6] +[NR-eGR] earlyGlobalRoute overflow of layer group 2: 0.00% H + 0.00% V. EstWL: 1.671192e+04um +[NR-eGR] +[NR-eGR] Move 37 nets to layer range [3, 7] +[NR-eGR] Layer group 3: route 37 net(s) in layer range [3, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 3: 0.00% H + 0.00% V. EstWL: 1.623672e+04um +[NR-eGR] +[NR-eGR] Move 11 nets to layer range [2, 7] +[NR-eGR] Layer group 4: route 11 net(s) in layer range [2, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 4: 0.00% H + 0.00% V. EstWL: 9.987840e+03um +[NR-eGR] +[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded) +[NR-eGR] OverCon OverCon OverCon +[NR-eGR] #Gcell #Gcell #Gcell %Gcell +[NR-eGR] Layer (1-2) (3-4) (5-6) OverCon +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] M1 (1) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M2 (2) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M3 (3) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M4 (4) 57( 0.20%) 5( 0.02%) 1( 0.00%) ( 0.22%) +[NR-eGR] M5 (5) 3( 0.01%) 0( 0.00%) 0( 0.00%) ( 0.01%) +[NR-eGR] M6 (6) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M7 (7) 3( 0.01%) 0( 0.00%) 0( 0.00%) ( 0.01%) +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] Total 63( 0.04%) 5( 0.00%) 1( 0.00%) ( 0.04%) +[NR-eGR] +[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.00% H + 0.00% V +[NR-eGR] Overflow after earlyGlobalRoute 0.00% H + 0.00% V +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] M1 (1F) length: 0.000000e+00um, number of vias: 31801 +[NR-eGR] M2 (2H) length: 6.121475e+04um, number of vias: 47227 +[NR-eGR] M3 (3V) length: 8.635045e+04um, number of vias: 9655 +[NR-eGR] M4 (4H) length: 4.502687e+04um, number of vias: 6870 +[NR-eGR] M5 (5V) length: 4.946056e+04um, number of vias: 2033 +[NR-eGR] M6 (6H) length: 1.919275e+04um, number of vias: 1101 +[NR-eGR] M7 (7V) length: 3.066611e+04um, number of vias: 0 +[NR-eGR] Total length: 2.919115e+05um, number of vias: 98687 +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] Total eGR-routed clock nets wire length: 1.954466e+04um +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] Report for selected net(s) only. +[NR-eGR] M1 (1V) length: 0.000000e+00um, number of vias: 1432 +[NR-eGR] M2 (2H) length: 9.301120e+02um, number of vias: 1548 +[NR-eGR] M3 (3V) length: 5.607084e+03um, number of vias: 1234 +[NR-eGR] M4 (4H) length: 8.512684e+03um, number of vias: 488 +[NR-eGR] M5 (5V) length: 3.453984e+03um, number of vias: 107 +[NR-eGR] M6 (6H) length: 5.554080e+02um, number of vias: 34 +[NR-eGR] M7 (7V) length: 4.853880e+02um, number of vias: 0 +[NR-eGR] Total length: 1.954466e+04um, number of vias: 4843 +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] Total routed clock nets wire length: 1.954466e+04um, number of vias: 4843 +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] End Peak syMemory usage = 1884.6 MB +[NR-eGR] Early Global Router Kernel+IO runtime : 0.35 seconds +Generated NR early global route guides for clocks to: /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/.rgfEo25lI + Early Global Route - eGR->NR step done. (took cpu=0:00:00.4 real=0:00:00.4) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Early Global Route - eGR->NR step + Routing using eGR in eGR->NR Step done. + Routing using NR in eGR->NR Step... + +CCOPT: Preparing to route 88 clock nets with NanoRoute. + All net are default rule. + Removed pre-existing routes for 88 nets. + Preferred NanoRoute mode settings: Current +#WARNING (NRIF-47) This option supports a feature that is under development and experimental, use at your own risk. +#WARNING (NRIF-47) This option supports a feature that is under development and experimental, use at your own risk. + Clock detailed routing... + NanoRoute... + +route_global_detail + +#set_db route_design_detail_auto_stop false +#set_db route_design_detail_end_iteration 20 +#set_db route_design_allow_pin_as_feedthru "false" +#set_db route_design_bottom_routing_layer 2 +#set_db route_design_selected_net_only true +#set_db route_design_top_routing_layer 7 +#set_db route_design_with_eco true +#set_db route_design_with_si_driven false +#set_db route_design_with_timing_driven false +#Start route_global_detail on Mon Dec 14 21:52:59 2020 +# +#WARNING (NRIG-1303) Congestion map does not match the GCELL grid, clearing map. +#WARNING (NRDB-976) The TRACK STEP 0.3840 for preferred direction tracks is smaller than the PITCH 8.1600 for LAYER Pad. This will cause routability problems for NanoRoute. +#NanoRoute Version 18.10-p002_1 NR180522-1057/18_10-UB +#Using multithreading with 4 threads. +#Start routing data preparation on Mon Dec 14 21:52:59 2020 +# +#WARNING (NRDB-2077) The below via enclosure for LAYER M1 is not specified for width 0.07200. +#WARNING (NRDB-2078) The above via enclosure for LAYER M2 is not specified for width 0.07200. +#WARNING (NRDB-2077) The below via enclosure for LAYER M1 is not specified for width 0.07200. +#WARNING (NRDB-2078) The above via enclosure for LAYER M2 is not specified for width 0.07200. +#WARNING (NRDB-2077) The below via enclosure for LAYER M2 is not specified for width 0.07200. +#WARNING (NRDB-2078) The above via enclosure for LAYER M3 is not specified for width 0.07200. +#WARNING (NRDB-2077) The below via enclosure for LAYER M2 is not specified for width 0.07200. +#WARNING (NRDB-2078) The above via enclosure for LAYER M3 is not specified for width 0.07200. +#WARNING (NRDB-2077) The below via enclosure for LAYER M3 is not specified for width 0.07200. +#WARNING (NRDB-2078) The above via enclosure for LAYER M4 is not specified for width 0.09600. +#WARNING (NRDB-2077) The below via enclosure for LAYER M3 is not specified for width 0.07200. +#WARNING (NRDB-2078) The above via enclosure for LAYER M4 is not specified for width 0.09600. +#WARNING (NRDB-2077) The below via enclosure for LAYER M5 is not specified for width 0.09600. +#WARNING (NRDB-2078) The above via enclosure for LAYER M6 is not specified for width 0.12800. +#WARNING (NRDB-2077) The below via enclosure for LAYER M5 is not specified for width 0.09600. +#WARNING (NRDB-2078) The above via enclosure for LAYER M6 is not specified for width 0.12800. +#WARNING (NRDB-2077) The below via enclosure for LAYER M7 is not specified for width 0.12800. +#WARNING (NRDB-2078) The above via enclosure for LAYER M8 is not specified for width 0.16000. +#WARNING (NRDB-2077) The below via enclosure for LAYER M7 is not specified for width 0.12800. +#WARNING (NRDB-2078) The above via enclosure for LAYER M8 is not specified for width 0.16000. +#WARNING (NRDB-2077) The below via enclosure for LAYER M8 is not specified for width 0.16000. +#WARNING (NRDB-2078) The above via enclosure for LAYER M9 is not specified for width 0.16000. +#WARNING (NRDB-2077) The below via enclosure for LAYER M8 is not specified for width 0.16000. +#WARNING (NRDB-2078) The above via enclosure for LAYER M9 is not specified for width 0.16000. +#WARNING (NRDB-2077) The below via enclosure for LAYER M9 is not specified for width 0.16000. +#WARNING (NRDB-2078) The above via enclosure for LAYER Pad is not specified for width 0.16000. +#WARNING (NRDB-2077) The below via enclosure for LAYER M9 is not specified for width 0.16000. +#WARNING (NRDB-2078) The above via enclosure for LAYER Pad is not specified for width 0.16000. +#WARNING (NRDB-2040) Rule LEF_DEFAULT doesn't specify any vias that satisfy all of the area rules for layer M2 M3 M4 M5 M6 M7 M8 M9 +#WARNING (NRDB-778) No multicut vias which meet all area rules for LAYER M8 are defined in RULE LEF_DEFAULT. When a LEF MINIMUMCUT rule is defined for a layer, you must define multicut vias for the layer in the LEF file. Edit your LEF file and read it in again. +#WARNING (NRDB-778) No multicut vias which meet all area rules for LAYER M9 are defined in RULE LEF_DEFAULT. When a LEF MINIMUMCUT rule is defined for a layer, you must define multicut vias for the layer in the LEF file. Edit your LEF file and read it in again. +#WARNING (NRDB-778) No multicut vias which meet all area rules for LAYER Pad are defined in RULE LEF_DEFAULT. When a LEF MINIMUMCUT rule is defined for a layer, you must define multicut vias for the layer in the LEF file. Edit your LEF file and read it in again. +#Minimum voltage of a net in the design = 0.000. +#Maximum voltage of a net in the design = 0.770. +#Voltage range [0.000 - 0.000] has 1 net. +#Voltage range [0.630 - 0.630] has 1 net. +#Voltage range [0.000 - 0.630] has 9748 nets. +#Voltage range [0.000 - 0.770] has 2320 nets. +# M1 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M2 H Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M3 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M4 H Track-Pitch = 0.19200 Line-2-Via Pitch = 0.19200 +# M5 V Track-Pitch = 0.21600 Line-2-Via Pitch = 0.19200 +# M6 H Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M7 V Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M8 H Track-Pitch = 0.38400 Line-2-Via Pitch = 0.32000 +# M9 V Track-Pitch = 0.36000 Line-2-Via Pitch = 0.32000 +# Pad H Track-Pitch = 0.38400 Line-2-Via Pitch = 8.28000 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +#Regenerating Ggrids automatically. +#Auto generating G-grids with size=15 tracks, using layer M3's pitch = 0.14400. +#Using automatically generated G-grids. +#Done routing data preparation. +#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1486.67 (MB), peak = 1832.20 (MB) +#Merging special wires using 4 threads... +#Start instance access analysis using 4 threads... +#Instance access analysis statistics: +#Cpu time = 00:00:00 +#Elapsed time = 00:00:00 +#Increased memory = 209.48 (MB) +#Total memory = 1697.92 (MB) +#Peak memory = 1832.20 (MB) +#reading routing guides ...... +# +#Finished routing data preparation on Mon Dec 14 21:53:00 2020 +# +#Cpu time = 00:00:02 +#Elapsed time = 00:00:01 +#Increased memory = 236.71 (MB) +#Total memory = 1698.00 (MB) +#Peak memory = 1832.20 (MB) +# +# +#Start global routing on Mon Dec 14 21:53:00 2020 +# +#Number of eco nets is 0 +# +#Start global routing data preparation on Mon Dec 14 21:53:00 2020 +# +#Start routing resource analysis on Mon Dec 14 21:53:00 2020 +# +#Routing resource analysis is done on Mon Dec 14 21:53:00 2020 +# +# Resource Analysis: +# +# Routing #Avail #Track #Total %Gcell +# Layer Direction Track Blocked Gcell Blocked +# -------------------------------------------------------------- +# M1 V 1801 629 30132 93.77% +# M2 H 1904 682 30132 26.36% +# M3 V 1389 1041 30132 24.53% +# M4 H 1541 498 30132 5.63% +# M5 V 1191 429 30132 5.59% +# M6 H 710 220 30132 11.29% +# M7 V 613 199 30132 10.55% +# M8 H 8 1033 30132 98.92% +# M9 V 13 958 30132 98.15% +# -------------------------------------------------------------- +# Total 9170 43.56% 271188 41.64% +# +# 88 nets (0.73%) with 1 preferred extra spacing. +# +# +# +#Global routing data preparation is done on Mon Dec 14 21:53:00 2020 +# +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1500.02 (MB), peak = 1832.20 (MB) +# +#Routing guide is on. +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1500.03 (MB), peak = 1832.20 (MB) +# +#start global routing iteration 1... +#Initial_route: 0.20995 +#Reroute: 0.21895 +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1505.64 (MB), peak = 1832.20 (MB) +# +#start global routing iteration 2... +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1505.71 (MB), peak = 1832.20 (MB) +# +# +#Total number of trivial nets (e.g. < 2 pins) = 2405 (skipped). +#Total number of selected nets for routing = 88. +#Total number of unselected nets (but routable) for routing = 9577 (skipped). +#Total number of nets in the design = 12070. +# +#9577 skipped nets do not have any wires. +#88 routable nets have only global wires. +#88 global routed or unrouted (routable) nets have been constrained (e.g. have preferred extra spacing, require shielding etc.) +# +#Routed net constraints summary: +#------------------------------------------------ +# Rules Pref Extra Space Unconstrained +#------------------------------------------------ +# Default 88 0 +#------------------------------------------------ +# Total 88 0 +#------------------------------------------------ +# +#Routing constraints summary of the whole design: +#------------------------------------------------------------- +# Rules Pref Extra Space Pref Layer Unconstrained +#------------------------------------------------------------- +# Default 88 41 9536 +#------------------------------------------------------------- +# Total 88 41 9536 +#------------------------------------------------------------- +# +# +# Congestion Analysis: (blocked Gcells are excluded) +# +# OverCon OverCon OverCon +# #Gcell #Gcell #Gcell %Gcell +# Layer (1-2) (3-4) (5-6) OverCon +# ------------------------------------------------------------ +# M2 0(0.00%) 0(0.00%) 0(0.00%) (0.00%) +# M3 0(0.00%) 0(0.00%) 0(0.00%) (0.00%) +# M4 11(0.04%) 1(0.00%) 0(0.00%) (0.04%) +# M5 4(0.01%) 0(0.00%) 0(0.00%) (0.01%) +# M6 14(0.05%) 2(0.01%) 1(0.00%) (0.06%) +# M7 5(0.02%) 3(0.01%) 0(0.00%) (0.03%) +# ------------------------------------------------------------ +# Total 34(0.02%) 6(0.00%) 1(0.00%) (0.03%) +# +# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 6 +# Overflow after GR: 0.02% H + 0.01% V +# +#Complete Global Routing. +#Total number of nets with non-default rule or having extra spacing = 88 +#Total wire length = 19104 um. +#Total half perimeter of net bounding box = 9434 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 734 um. +#Total wire length on LAYER M3 = 5481 um. +#Total wire length on LAYER M4 = 8460 um. +#Total wire length on LAYER M5 = 3418 um. +#Total wire length on LAYER M6 = 531 um. +#Total wire length on LAYER M7 = 479 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 4632 +#Up-Via Summary (total 4632): +# +#----------------------- +# M1 1432 +# M2 1417 +# M3 1204 +# M4 449 +# M5 102 +# M6 28 +#----------------------- +# 4632 +# +#Total number of involved priority nets 88 +#Maximum src to sink distance for priority net 309.8 +#Average of max src_to_sink distance for priority net 72.4 +#Average of ave src_to_sink distance for priority net 45.0 +#Max overcon = 6 tracks. +#Total overcon = 0.03%. +#Worst layer Gcell overcon rate = 0.06%. +# +#Global routing statistics: +#Cpu time = 00:00:01 +#Elapsed time = 00:00:01 +#Increased memory = -189.91 (MB) +#Total memory = 1508.10 (MB) +#Peak memory = 1832.20 (MB) +# +#Finished global routing on Mon Dec 14 21:53:01 2020 +# +# +#reading routing guides ...... +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1498.14 (MB), peak = 1832.20 (MB) +#Start Track Assignment. +#Done with 1464 horizontal wires in 2 hboxes and 1190 vertical wires in 2 hboxes. +#Done with 1354 horizontal wires in 2 hboxes and 1132 vertical wires in 2 hboxes. +#Complete Track Assignment. +#Total number of nets with non-default rule or having extra spacing = 88 +#Total wire length = 19239 um. +#Total half perimeter of net bounding box = 9434 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 722 um. +#Total wire length on LAYER M3 = 5491 um. +#Total wire length on LAYER M4 = 8555 um. +#Total wire length on LAYER M5 = 3433 um. +#Total wire length on LAYER M6 = 547 um. +#Total wire length on LAYER M7 = 490 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 4632 +#Up-Via Summary (total 4632): +# +#----------------------- +# M1 1432 +# M2 1417 +# M3 1204 +# M4 449 +# M5 102 +# M6 28 +#----------------------- +# 4632 +# +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1506.44 (MB), peak = 1832.20 (MB) +# +#Routing data preparation, pin analysis, global routing and track assignment statistics: +#Cpu time = 00:00:04 +#Elapsed time = 00:00:02 +#Increased memory = 45.43 (MB) +#Total memory = 1506.65 (MB) +#Peak memory = 1832.20 (MB) +#Using multithreading with 4 threads. +# +#Start Detail Routing.. +#start initial detail routing ... +# ECO: 6.5% of the total area was rechecked for DRC, and 19.8% required routing. +# number of violations = 20 +# +# By Layer and Type : +# EOLSpc Short CutSpc EolKO CorSpc Totals +# M1 0 0 0 0 0 0 +# M2 0 0 0 0 0 0 +# M3 0 0 1 0 0 1 +# M4 1 1 0 16 1 19 +# Totals 1 1 1 16 1 20 +#cpu time = 00:00:11, elapsed time = 00:00:11, memory = 1607.67 (MB), peak = 1832.20 (MB) +#start 1st optimization iteration ... +# number of violations = 2 +# +# By Layer and Type : +# EolKO Totals +# M1 0 0 +# M2 0 0 +# M3 0 0 +# M4 2 2 +# Totals 2 2 +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1612.70 (MB), peak = 1832.20 (MB) +#start 2nd optimization iteration ... +# number of violations = 1 +# +# By Layer and Type : +# EolKO Totals +# M1 0 0 +# M2 0 0 +# M3 0 0 +# M4 1 1 +# Totals 1 1 +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1612.64 (MB), peak = 1832.20 (MB) +#start 3rd optimization iteration ... +# number of violations = 0 +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1613.14 (MB), peak = 1832.20 (MB) +#Complete Detail Routing. +#Total number of nets with non-default rule or having extra spacing = 88 +#Total wire length = 19846 um. +#Total half perimeter of net bounding box = 9434 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 372 um. +#Total wire length on LAYER M3 = 5880 um. +#Total wire length on LAYER M4 = 9127 um. +#Total wire length on LAYER M5 = 3440 um. +#Total wire length on LAYER M6 = 564 um. +#Total wire length on LAYER M7 = 464 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 5561 +#Up-Via Summary (total 5561): +# +#----------------------- +# M1 1432 +# M2 1518 +# M3 1928 +# M4 530 +# M5 119 +# M6 34 +#----------------------- +# 5561 +# +#Total number of DRC violations = 0 +#Cpu time = 00:00:12 +#Elapsed time = 00:00:12 +#Increased memory = 1.09 (MB) +#Total memory = 1507.74 (MB) +#Peak memory = 1832.20 (MB) +#route_detail Statistics: +#Cpu time = 00:00:12 +#Elapsed time = 00:00:12 +#Increased memory = 1.09 (MB) +#Total memory = 1507.74 (MB) +#Peak memory = 1832.20 (MB) +# +#route_global_detail statistics: +#Cpu time = 00:00:16 +#Elapsed time = 00:00:14 +#Increased memory = 53.18 (MB) +#Total memory = 1513.79 (MB) +#Peak memory = 1832.20 (MB) +#Number of warnings = 37 +#Total number of warnings = 47 +#Number of fails = 0 +#Total number of fails = 0 +#Complete route_global_detail on Mon Dec 14 21:53:13 2020 +# + NanoRoute done. (took cpu=0:00:16.3 real=0:00:14.5) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: NanoRoute + Clock detailed routing done. +Checking guided vs. routed lengths for 88 nets... + + + Guided max path lengths + ======================= + + --------------------------------------- + From (um) To (um) Number of paths + --------------------------------------- + 0.000 50.000 43 + 50.000 100.000 12 + 100.000 150.000 20 + 150.000 200.000 11 + 200.000 250.000 1 + 250.000 300.000 0 + 300.000 350.000 1 + --------------------------------------- + + Deviation of routing from guided max path lengths + ================================================= + + ------------------------------------- + From (%) To (%) Number of paths + ------------------------------------- + below 0.000 46 + 0.000 5.000 28 + 5.000 10.000 6 + 10.000 15.000 3 + 15.000 20.000 2 + 20.000 25.000 0 + 25.000 30.000 2 + 30.000 35.000 0 + 35.000 40.000 0 + 40.000 45.000 1 + ------------------------------------- + + + Top 10 notable deviations of routed length from guided length + ============================================================= + + Net cpu/stage1/regfile/CTS_28 (33 terminals) + Guided length: max path = 126.648um, total = 530.784um + Routed length: max path = 158.724um, total = 532.056um + Deviation: max path = 25.327%, total = 0.240% + + Net cpu/stage1/regfile/CTS_26 (33 terminals) + Guided length: max path = 128.448um, total = 534.528um + Routed length: max path = 144.060um, total = 541.464um + Deviation: max path = 12.154%, total = 1.298% + + Net cpu/stage1/regfile/CTS_45 (33 terminals) + Guided length: max path = 175.860um, total = 563.652um + Routed length: max path = 132.468um, total = 614.556um + Deviation: max path = -24.674%, total = 9.031% + + Net cpu/stage1/regfile/CTS_33 (33 terminals) + Guided length: max path = 93.240um, total = 441.648um + Routed length: max path = 101.244um, total = 440.356um + Deviation: max path = 8.584%, total = -0.292% + + Net cpu/stage1/regfile/CTS_65 (10 terminals) + Guided length: max path = 31.716um, total = 58.212um + Routed length: max path = 31.464um, total = 63.168um + Deviation: max path = -0.795%, total = 8.514% + + Net cpu/s2_to_s3_pc/CLKGATE_rc_gclk (33 terminals) + Guided length: max path = 76.104um, total = 181.511um + Routed length: max path = 74.628um, total = 195.580um + Deviation: max path = -1.939%, total = 7.751% + + Net cpu/stage1/regfile/CTS_63 (33 terminals) + Guided length: max path = 176.615um, total = 561.528um + Routed length: max path = 165.564um, total = 595.516um + Deviation: max path = -6.257%, total = 6.053% + + Net cpu/s2_to_s3_alu/CLKGATE_rc_gclk (33 terminals) + Guided length: max path = 89.568um, total = 192.060um + Routed length: max path = 71.652um, total = 203.276um + Deviation: max path = -20.003%, total = 5.840% + + Net cpu/s2_to_s3_inst/CLKGATE_rc_gclk (16 terminals) + Guided length: max path = 31.464um, total = 62.100um + Routed length: max path = 27.204um, total = 65.512um + Deviation: max path = -13.539%, total = 5.494% + + Net cpu/stage1/regfile/CTS_51 (33 terminals) + Guided length: max path = 167.905um, total = 532.656um + Routed length: max path = 146.316um, total = 561.840um + Deviation: max path = -12.858%, total = 5.479% + +Set FIXED routing status on 88 net(s) +Set FIXED placed status on 87 instance(s) + Routing using NR in eGR->NR Step done. +Net route status summary: + Clock: 88 (unrouted=0, trialRouted=0, noStatus=0, routed=0, fixed=88, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)]) + Non-clock: 11982 (unrouted=11982, trialRouted=0, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=2405, (crossesIlmBoundary AND tooFewTerms=0)]) + +CCOPT: Done with clock implementation routing. + + +CCOpt: Starting congestion repair using flow wrapper. + Congestion Repair... + +Starting congestion repair ... +[NR-eGR] honorMsvRouteConstraint: false +[NR-eGR] honorClockSpecNDR : 0 +[NR-eGR] minRouteLayer : 2 +[NR-eGR] maxRouteLayer : 7 +[NR-eGR] numTracksPerClockWire : 0 +[NR-eGR] M1 has no routable track +[NR-eGR] M2 has non-uniform track structures +[NR-eGR] M3 has single uniform track structure +[NR-eGR] M4 has single uniform track structure +[NR-eGR] M5 has single uniform track structure +[NR-eGR] M6 has single uniform track structure +[NR-eGR] M7 has single uniform track structure +[NR-eGR] Read 53034 PG shapes in 0.010 seconds + +[NR-eGR] numRoutingBlks=0 numInstBlks=2389 numPGBlocks=53034 numBumpBlks=0 numBoundaryFakeBlks=0 +[NR-eGR] Num Prerouted Nets = 88 Num Prerouted Wires = 9614 +[NR-eGR] Read numTotalNets=9665 numIgnoredNets=88 +[NR-eGR] ============ Routing rule table ============ +[NR-eGR] Rule id: 0 Nets: 0 +[NR-eGR] Rule id: 1 Nets: 9577 +[NR-eGR] ======================================== +[NR-eGR] +[NR-eGR] Layer group 1: route 41 net(s) in layer range [4, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.07% H + 0.08% V. EstWL: 7.223040e+03um +[NR-eGR] +[NR-eGR] Layer group 2: route 9536 net(s) in layer range [2, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 2: 0.10% H + 0.57% V. EstWL: 2.596093e+05um +[NR-eGR] +[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded) +[NR-eGR] OverCon OverCon OverCon +[NR-eGR] #Gcell #Gcell #Gcell %Gcell +[NR-eGR] Layer (1-2) (3-4) (5-5) OverCon +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] M1 (1) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M2 (2) 157( 0.18%) 6( 0.01%) 1( 0.00%) ( 0.18%) +[NR-eGR] M3 (3) 1661( 1.85%) 152( 0.17%) 2( 0.00%) ( 2.02%) +[NR-eGR] M4 (4) 547( 0.52%) 24( 0.02%) 0( 0.00%) ( 0.54%) +[NR-eGR] M5 (5) 467( 0.48%) 6( 0.01%) 0( 0.00%) ( 0.49%) +[NR-eGR] M6 (6) 53( 0.05%) 0( 0.00%) 0( 0.00%) ( 0.05%) +[NR-eGR] M7 (7) 35( 0.04%) 0( 0.00%) 0( 0.00%) ( 0.04%) +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] Total 2920( 0.51%) 188( 0.03%) 3( 0.00%) ( 0.54%) +[NR-eGR] +[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.06% H + 0.41% V +[NR-eGR] Overflow after earlyGlobalRoute 0.07% H + 0.49% V +Early Global Route congestion estimation runtime: 0.42 seconds, mem = 1911.8M +Local HotSpot Analysis: normalized max congestion hotspot area = 1.05, normalized total congestion hotspot area = 4.72 (area is in unit of 4 std-cell row bins) + +=== incrementalPlace Internal Loop 1 === +Skipped repairing congestion. +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] M1 (1F) length: 0.000000e+00um, number of vias: 31973 +[NR-eGR] M2 (2H) length: 6.927278e+04um, number of vias: 48050 +[NR-eGR] M3 (3V) length: 8.668531e+04um, number of vias: 10377 +[NR-eGR] M4 (4H) length: 3.519979e+04um, number of vias: 7285 +[NR-eGR] M5 (5V) length: 4.864700e+04um, number of vias: 2704 +[NR-eGR] M6 (6H) length: 2.170008e+04um, number of vias: 1460 +[NR-eGR] M7 (7V) length: 3.211806e+04um, number of vias: 0 +[NR-eGR] Total length: 2.936230e+05um, number of vias: 101849 +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] Total eGR-routed clock nets wire length: 0.000000e+00um +[NR-eGR] -------------------------------------------------------------------------- +Early Global Route wiring runtime: 0.29 seconds, mem = 1904.8M +End of congRepair (cpu=0:00:00.7, real=0:00:01.0) + Congestion Repair done. (took cpu=0:00:00.8 real=0:00:00.7) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Congestion Repair + +CCOpt: Done with congestion repair using flow wrapper. + +Net route status summary: + Clock: 88 (unrouted=0, trialRouted=0, noStatus=0, routed=0, fixed=88, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)]) + Non-clock: 11982 (unrouted=2405, trialRouted=9577, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=2405, (crossesIlmBoundary AND tooFewTerms=0)]) + Leaving CCOpt scope - Routing Tools done. (took cpu=0:00:17.8 real=0:00:15.8) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Leaving CCOpt scope - Routing Tools + Clock implementation routing done. + Leaving CCOpt scope - extractRC... + Updating RC parasitics by calling: "extract_rc -noRouteCheck"... +Extraction called for design 'riscv_top' of instances=12053 and nets=12070 using extraction engine 'pre_route' . +pre_route RC Extraction called for design riscv_top. +RC Extraction called in multi-corner(2) mode. +RCMode: PreRoute + RC Corner Indexes 0 1 +Capacitance Scaling Factor : 1.00000 1.00000 +Resistance Scaling Factor : 1.00000 1.00000 +Clock Cap. Scaling Factor : 1.00000 1.00000 +Clock Res. Scaling Factor : 1.00000 1.00000 +Shrink Factor : 1.00000 +PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets. +Using Quantus QRC technology file ... +Updating RC grid for preRoute extraction ... +Initializing multi-corner resistance tables ... +PreRoute RC Extraction DONE (CPU Time: 0:00:00.2 Real Time: 0:00:00.0 MEM: 1904.793M) + Updating RC parasitics by calling: "extract_rc -noRouteCheck" done. + Leaving CCOpt scope - extractRC done. (took cpu=0:00:00.2 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Leaving CCOpt scope - extractRC + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late... + Rebuilding timing graph... + Rebuilding timing graph done. + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late done. (took cpu=0:00:00.8 real=0:00:00.3) + Clock DAG stats after routing clock trees: + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=145.100um^2, i=0.000um^2, icg=184.291um^2, nicg=0.000um^2, l=0.000um^2, total=329.391um^2 + cell capacitance : b=0.035pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.106pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.468pF, total=0.514pF + wire lengths : top=0.000um, trunk=1891.968um, leaf=17954.328um, total=19846.296um + Clock DAG net violations after routing clock trees: + Remaining Transition : {count=3, worst=[0.8ps, 0.7ps, 0.4ps]} avg=0.6ps sd=0.2ps sum=1.9ps + Clock DAG primary half-corner transition distribution after routing clock trees: + Trunk : target=69.3ps count=41 avg=22.1ps sd=15.7ps min=11.3ps max=64.0ps {34 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.1ps sd=0.1ps min=7.0ps max=7.2ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=55.8ps sd=9.0ps min=24.8ps max=70.1ps {2 <= 41.6ps, 20 <= 55.4ps, 12 <= 62.4ps, 4 <= 65.8ps, 2 <= 69.3ps} {3 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution after routing clock trees {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 30 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 7 ICGx2_ASAP7_75t_SL: 2 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after routing clock trees: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=145.1, sd=8.0], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=134.2 gs=34.7) + Skew group summary after routing clock trees: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=145.1, sd=8.0], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=134.2 gs=34.7) + Clock network insertion delays are now [127.5ps, 160.8ps] average 145.1ps std.dev 8.0ps + CCOpt::Phase::Routing done. (took cpu=0:00:19.0 real=0:00:16.5) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: CCOpt::Phase::Routing + CCOpt::Phase::PostConditioning... + Removing CTS place status from clock tree and sinks. + Switching to inst based legalization. + PostConditioning... + PostConditioning active optimizations: + - DRV fixing with cell sizing and buffering + - Skew fixing with cell sizing + + Currently running CTS, using active skew data + Reset bufferability constraints... + Resetting previous bufferability status on all nets so that PostConditioning will attempt to fix all clock tree violations. + Reset bufferability constraints done. (took cpu=0:00:00.0 real=0:00:00.0) + Upsizing to fix DRVs... + Fixing clock tree DRVs with upsizing: ...20% ...40% ...60% ...80% ...100% + CCOpt-PostConditioning: considered: 88, tested: 88, violation detected: 3, violation ignored (due to small violation): 0, cannot run: 0, attempted: 3, unsuccessful: 0, sized: 1 + + PRO Statistics: Fix DRVs (initial upsizing): + ============================================ + + Cell changes by Net Type: + + ------------------------------------------------------------------------------------------------------------------------------ + Net Type Attempted Upsized Downsized Swapped Same Size Total Changed Not Sized + ------------------------------------------------------------------------------------------------------------------------------ + top 0 0 0 0 0 (0.0%) 0 (0.0%) + trunk 0 0 0 0 0 (0.0%) 0 (0.0%) + leaf 3 (100.0%) 1 (100.0%) 0 0 1 (100.0%) 2 (100.0%) + ------------------------------------------------------------------------------------------------------------------------------ + Total 3 (100%) 1 (100%) - - 1 (100%) 2 (100%) + ------------------------------------------------------------------------------------------------------------------------------ + + Upsized: 1, Downsized: 0, Sized but same area: 0, Unchanged: 2, Area change: 0.233um^2 (0.071%) + Max. move: 0.000um, Min. move: 0.000um, Avg. move: 0.000um + + Clock DAG stats PostConditioning after Upsizing to fix DRVs: + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=145.100um^2, i=0.000um^2, icg=184.524um^2, nicg=0.000um^2, l=0.000um^2, total=329.625um^2 + cell capacitance : b=0.035pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.107pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.468pF, total=0.514pF + wire lengths : top=0.000um, trunk=1891.968um, leaf=17954.328um, total=19846.296um + Clock DAG net violations PostConditioning after Upsizing to fix DRVs: + Remaining Transition : {count=2, worst=[0.7ps, 0.4ps]} avg=0.6ps sd=0.2ps sum=1.1ps + Clock DAG primary half-corner transition distribution PostConditioning after Upsizing to fix DRVs: + Trunk : target=69.3ps count=41 avg=22.1ps sd=15.7ps min=11.3ps max=64.0ps {34 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.1ps sd=0.1ps min=7.0ps max=7.2ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=55.4ps sd=8.8ps min=24.8ps max=70.0ps {2 <= 41.6ps, 21 <= 55.4ps, 12 <= 62.4ps, 4 <= 65.8ps, 2 <= 69.3ps} {2 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution PostConditioning after Upsizing to fix DRVs {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 30 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 8 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group PostConditioning after Upsizing to fix DRVs: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=144.9, sd=7.9], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=132.0 gs=32.5) + Skew group summary PostConditioning after Upsizing to fix DRVs: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=144.9, sd=7.9], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=132.0 gs=32.5) + Clock network insertion delays are now [127.5ps, 160.8ps] average 144.9ps std.dev 7.9ps + Upsizing to fix DRVs done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Upsizing to fix DRVs + Recomputing CTS skew targets... + Resolving skew group constraints... + Solving LP: 1 skew groups; 3 fragments, 3 fraglets and 4 vertices; 25 variables and 66 constraints; tolerance 1 + Resolving skew group constraints done. + Recomputing CTS skew targets done. (took cpu=0:00:00.1 real=0:00:00.1) + Fixing DRVs... + Fixing clock tree DRVs: ...20% ...40% ...60% ...80% ...100% + CCOpt-PostConditioning: considered: 88, tested: 88, violation detected: 2, violation ignored (due to small violation): 0, cannot run: 0, attempted: 2, unsuccessful: 0, sized: 0 + + PRO Statistics: Fix DRVs (cell sizing): + ======================================= + + Cell changes by Net Type: + + ------------------------------------------------------------------------------------------------------------------- + Net Type Attempted Upsized Downsized Swapped Same Size Total Changed Not Sized + ------------------------------------------------------------------------------------------------------------------- + top 0 0 0 0 0 0 (0.0%) + trunk 0 0 0 0 0 0 (0.0%) + leaf 2 (100.0%) 0 0 0 0 2 (100.0%) + ------------------------------------------------------------------------------------------------------------------- + Total 2 (100%) - - - 0 (100%) 2 (100%) + ------------------------------------------------------------------------------------------------------------------- + + Upsized: 0, Downsized: 0, Sized but same area: 0, Unchanged: 2, Area change: 0.000um^2 (0.000%) + Max. move: 0.000um, Min. move: 0.000um, Avg. move: 0.000um + + Clock DAG stats PostConditioning after DRV fixing: + cell counts : b=44, i=0, icg=43, nicg=0, l=0, total=87 + cell areas : b=145.100um^2, i=0.000um^2, icg=184.524um^2, nicg=0.000um^2, l=0.000um^2, total=329.625um^2 + cell capacitance : b=0.035pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.107pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.468pF, total=0.514pF + wire lengths : top=0.000um, trunk=1891.968um, leaf=17954.328um, total=19846.296um + Clock DAG net violations PostConditioning after DRV fixing: + Remaining Transition : {count=2, worst=[0.7ps, 0.4ps]} avg=0.6ps sd=0.2ps sum=1.1ps + Clock DAG primary half-corner transition distribution PostConditioning after DRV fixing: + Trunk : target=69.3ps count=41 avg=22.1ps sd=15.7ps min=11.3ps max=64.0ps {34 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.1ps sd=0.1ps min=7.0ps max=7.2ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=55.4ps sd=8.8ps min=24.8ps max=70.0ps {2 <= 41.6ps, 21 <= 55.4ps, 12 <= 62.4ps, 4 <= 65.8ps, 2 <= 69.3ps} {2 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution PostConditioning after DRV fixing {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 30 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 + ICGs: ICGx3_ASAP7_75t_SL: 8 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group PostConditioning after DRV fixing: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=144.9, sd=7.9], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=132.0 gs=32.5) + Skew group summary PostConditioning after DRV fixing: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=144.9, sd=7.9], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=132.0 gs=32.5) + Clock network insertion delays are now [127.5ps, 160.8ps] average 144.9ps std.dev 7.9ps + Fixing DRVs done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Fixing DRVs + Buffering to fix DRVs... + Rebuffering to fix clock tree DRVs: ...20% ...40% Info: CCOpt is analyzing the delay of a net driven by BUFx2_ASAP7_75t_SRAM/Y using a timing arc from cell HB1xp67_ASAP7_75t_SRAM + ...60% ...80% ...100% + Inserted 1 buffers and inverters. + CCOpt-PostConditioning: nets considered: 88, nets tested: 88, nets violation detected: 2, nets violation ignored (due to small violation): 0, nets cannot run: 0, nets attempted: 2, nets unsuccessful: 1, buffered: 1 + Clock DAG stats PostConditioning after re-buffering DRV fixing: + cell counts : b=45, i=0, icg=43, nicg=0, l=0, total=88 + cell areas : b=146.267um^2, i=0.000um^2, icg=184.524um^2, nicg=0.000um^2, l=0.000um^2, total=330.791um^2 + cell capacitance : b=0.036pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.107pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.468pF, total=0.514pF + wire lengths : top=0.000um, trunk=1892.256um, leaf=17954.040um, total=19846.296um + Clock DAG net violations PostConditioning after re-buffering DRV fixing: + Remaining Transition : {count=1, worst=[0.7ps]} avg=0.7ps sd=0.0ps sum=0.7ps + Clock DAG primary half-corner transition distribution PostConditioning after re-buffering DRV fixing: + Trunk : target=69.3ps count=42 avg=21.8ps sd=15.6ps min=7.9ps max=64.0ps {35 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.1ps sd=0.1ps min=7.0ps max=7.2ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=55.2ps sd=8.6ps min=24.8ps max=70.0ps {2 <= 41.6ps, 21 <= 55.4ps, 12 <= 62.4ps, 5 <= 65.8ps, 2 <= 69.3ps} {1 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution PostConditioning after re-buffering DRV fixing {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 30 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 BUFx2_ASAP7_75t_SRAM: 1 + ICGs: ICGx3_ASAP7_75t_SL: 8 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group PostConditioning after re-buffering DRV fixing: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=145.1, sd=7.9], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=132.0 gs=32.5) + Skew group summary PostConditioning after re-buffering DRV fixing: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=145.1, sd=7.9], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=132.0 gs=32.5) + Clock network insertion delays are now [127.5ps, 160.8ps] average 145.1ps std.dev 7.9ps + Buffering to fix DRVs done. (took cpu=0:00:00.3 real=0:00:00.3) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Buffering to fix DRVs + Fixing Skew by cell sizing... + Resized 0 clock insts to decrease delay. + Resized 0 clock insts to increase delay. + + PRO Statistics: Fix Skew (cell sizing): + ======================================= + + Cell changes by Net Type: + + --------------------------------------------------------------------------------------------------------- + Net Type Attempted Upsized Downsized Swapped Same Size Total Changed Not Sized + --------------------------------------------------------------------------------------------------------- + top 0 0 0 0 0 0 + trunk 0 0 0 0 0 0 + leaf 0 0 0 0 0 0 + --------------------------------------------------------------------------------------------------------- + Total - - - - 0 (100%) 0 (100%) + --------------------------------------------------------------------------------------------------------- + + Upsized: 0, Downsized: 0, Sized but same area: 0, Unchanged: 0, Area change: 0.000um^2 (0.000%) + Max. move: 0.000um, Min. move: 0.000um, Avg. move: N/A + + Clock DAG stats PostConditioning after skew fixing by cell sizing: + cell counts : b=45, i=0, icg=43, nicg=0, l=0, total=88 + cell areas : b=146.267um^2, i=0.000um^2, icg=184.524um^2, nicg=0.000um^2, l=0.000um^2, total=330.791um^2 + cell capacitance : b=0.036pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.107pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.468pF, total=0.514pF + wire lengths : top=0.000um, trunk=1892.256um, leaf=17954.040um, total=19846.296um + Clock DAG net violations PostConditioning after skew fixing by cell sizing: + Remaining Transition : {count=1, worst=[0.7ps]} avg=0.7ps sd=0.0ps sum=0.7ps + Clock DAG primary half-corner transition distribution PostConditioning after skew fixing by cell sizing: + Trunk : target=69.3ps count=42 avg=21.8ps sd=15.6ps min=7.9ps max=64.0ps {35 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.1ps sd=0.1ps min=7.0ps max=7.2ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=55.2ps sd=8.6ps min=24.8ps max=70.0ps {2 <= 41.6ps, 21 <= 55.4ps, 12 <= 62.4ps, 5 <= 65.8ps, 2 <= 69.3ps} {1 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution PostConditioning after skew fixing by cell sizing {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 30 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 BUFx2_ASAP7_75t_SRAM: 1 + ICGs: ICGx3_ASAP7_75t_SL: 8 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group PostConditioning after skew fixing by cell sizing: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=145.1, sd=7.9], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=132.0 gs=32.5) + Skew group summary PostConditioning after skew fixing by cell sizing: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=145.1, sd=7.9], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=132.0 gs=32.5) + Clock network insertion delays are now [127.5ps, 160.8ps] average 145.1ps std.dev 7.9ps + Fixing Skew by cell sizing done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Fixing Skew by cell sizing + Reconnecting optimized routes... + Reset timing graph... +Ignoring AAE DB Resetting ... + Reset timing graph done. + Reconnecting optimized routes done. (took cpu=0:00:00.1 real=0:00:00.1) + ClockRefiner... + Performing Single Pass Refine Place. +*** Starting place_detail (0:08:43 mem=1986.0M) *** +Total net bbox length = 2.540e+05 (1.010e+05 1.531e+05) (ext = 3.759e+04) +Move report: Detail placement moves 0 insts, mean move: 0.00 um, max move: 0.00 um + Runtime: CPU: 0:00:02.3 REAL: 0:00:01.0 MEM: 1986.0MB +Summary Report: +Instances move: 0 (out of 9227 movable) +Instances flipped: 0 +Mean displacement: 0.00 um +Max displacement: 0.00 um +Total net bbox length = 2.540e+05 (1.010e+05 1.531e+05) (ext = 3.759e+04) +Runtime: CPU: 0:00:02.3 REAL: 0:00:01.0 MEM: 1986.0MB +*** Finished place_detail (0:08:45 mem=1986.0M) *** + Moved 0, flipped 0 and cell swapped 0 of 1393 clock instance(s) during refinement. + The largest move was 0 microns for . + ClockRefiner done. (took cpu=0:00:02.7 real=0:00:01.2) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: ClockRefiner + Set dirty flag on 7 insts, 14 nets + PostConditioning done. +Net route status summary: + Clock: 89 (unrouted=0, trialRouted=0, noStatus=0, routed=0, fixed=89, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)]) + Non-clock: 11982 (unrouted=2405, trialRouted=9577, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=2405, (crossesIlmBoundary AND tooFewTerms=0)]) + Update timing and DAG stats after post-conditioning... + Update timing and DAG stats after post-conditioning done. (took cpu=0:00:00.0 real=0:00:00.0) + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late... + Rebuilding timing graph... + Rebuilding timing graph done. + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late done. (took cpu=0:00:00.8 real=0:00:00.3) + Clock DAG stats after post-conditioning: + cell counts : b=45, i=0, icg=43, nicg=0, l=0, total=88 + cell areas : b=146.267um^2, i=0.000um^2, icg=184.524um^2, nicg=0.000um^2, l=0.000um^2, total=330.791um^2 + cell capacitance : b=0.036pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.107pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.468pF, total=0.514pF + wire lengths : top=0.000um, trunk=1893.804um, leaf=17958.008um, total=19851.812um + Clock DAG net violations after post-conditioning: + Remaining Transition : {count=1, worst=[0.7ps]} avg=0.7ps sd=0.0ps sum=0.7ps + Clock DAG primary half-corner transition distribution after post-conditioning: + Trunk : target=69.3ps count=42 avg=21.8ps sd=15.6ps min=7.9ps max=64.0ps {35 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.1ps sd=0.1ps min=7.0ps max=7.2ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=55.2ps sd=8.6ps min=24.8ps max=70.0ps {2 <= 41.6ps, 21 <= 55.4ps, 12 <= 62.4ps, 5 <= 65.8ps, 2 <= 69.3ps} {1 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution after post-conditioning {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 30 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 BUFx2_ASAP7_75t_SRAM: 1 + ICGs: ICGx3_ASAP7_75t_SL: 8 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group after post-conditioning: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=145.1, sd=7.9], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=132.0 gs=32.5) + Skew group summary after post-conditioning: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=145.1, sd=7.9], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=132.0 gs=32.5) + Clock network insertion delays are now [127.5ps, 160.8ps] average 145.1ps std.dev 7.9ps + CCOpt::Phase::PostConditioning done. (took cpu=0:00:04.6 real=0:00:02.6) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: CCOpt::Phase::PostConditioning + Setting CTS place status to fixed for clock tree and sinks. + Post-balance tidy up or trial balance steps... + + Clock DAG stats at end of CTS: + ============================== + + ------------------------------------------------------------- + Cell type Count Area Capacitance + ------------------------------------------------------------- + Buffers 45 146.267 0.036 + Inverters 0 0.000 0.000 + Integrated Clock Gates 43 184.524 0.071 + Non-Integrated Clock Gates 0 0.000 0.000 + Clock Logic 0 0.000 0.000 + All 88 330.791 0.107 + ------------------------------------------------------------- + + + Clock DAG wire lengths at end of CTS: + ===================================== + + -------------------- + Type Wire Length + -------------------- + Top 0.000 + Trunk 1893.804 + Leaf 17958.008 + Total 19851.812 + -------------------- + + + Clock DAG capacitances at end of CTS: + ===================================== + + -------------------------------- + Type Gate Wire Total + -------------------------------- + Top 0.000 0.000 0.000 + Trunk 0.107 0.046 0.153 + Leaf 0.446 0.468 0.914 + Total 0.552 0.514 1.066 + -------------------------------- + + + Clock DAG sink capacitances at end of CTS: + ========================================== + + -------------------------------------------------------- + Count Total Average Std. Dev. Min Max + -------------------------------------------------------- + 1305 0.446 0.000 0.000 0.000 0.004 + -------------------------------------------------------- + + + Clock DAG net violations at end of CTS: + ======================================= + + ------------------------------------------------------------------------------------------ + Type Units Count Average Std. Dev. Sum Top 10 violations + ------------------------------------------------------------------------------------------ + Remaining Transition ps 1 0.7 0.0 0.7 [0.7] + ------------------------------------------------------------------------------------------ + + + Clock DAG primary half-corner transition distribution at end of CTS: + ==================================================================== + + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Net Type Target Count Average Std. Dev. Min Max Distribution Over Target + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Trunk 69.3 42 21.8 15.6 7.9 64.0 {35 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} - + Leaf 8.0 4 7.1 0.1 7.0 7.2 {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} - + Leaf 69.3 43 55.2 8.6 24.8 70.0 {2 <= 41.6ps, 21 <= 55.4ps, 12 <= 62.4ps, 5 <= 65.8ps, 2 <= 69.3ps} {1 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + + + Clock DAG library cell distribution at end of CTS: + ================================================== + + ------------------------------------------------------- + Name Type Inst Inst Area + Count (um^2) + ------------------------------------------------------- + BUFx12f_ASAP7_75t_SRAM buffer 9 37.791 + BUFx10_ASAP7_75t_SRAM buffer 30 97.978 + BUFx6f_ASAP7_75t_SRAM buffer 2 4.666 + BUFx5_ASAP7_75t_SRAM buffer 1 1.866 + BUFx3_ASAP7_75t_SRAM buffer 2 2.799 + BUFx2_ASAP7_75t_SRAM buffer 1 1.166 + ICGx3_ASAP7_75t_SL icg 8 37.325 + ICGx2_ASAP7_75t_SL icg 1 4.432 + ICGx1_ASAP7_75t_SL icg 32 134.369 + ICGx1_ASAP7_75t_SRAM icg 2 8.398 + ------------------------------------------------------- + + + Primary reporting skew group summary at end of CTS: + =================================================== + + -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Half-corner Skew Group Min ID Max ID Skew Skew target Wire skew Worst sink skew Average ID Std.Dev Skew window occupancy + -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + PVT_0P63V_100C.setup_delay:setup.late clk/my_constraint_mode 127.5 160.8 33.3 33.6 40.4 20.0 145.1 7.9 100% {127.5, 160.8} + -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + + + Skew group summary at end of CTS: + ================================= + + -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Half-corner Skew Group Min ID Max ID Skew Skew target Wire skew Worst sink skew Average ID Std.Dev Skew window occupancy + -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + PVT_0P63V_100C.setup_delay:setup.late clk/my_constraint_mode 127.5 160.8 33.3 33.6 40.4 20.0 145.1 7.9 100% {127.5, 160.8} + -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + + Clock network insertion delays are now [127.5ps, 160.8ps] average 145.1ps std.dev 7.9ps + + Found a total of 8 clock tree pins with a slew violation. + + Slew violation summary across all clock trees - Top 8 violating pins: + ===================================================================== + + Target and measured clock slews (in ps): + + --------------------------------------------------------------------------------------------------------------------------------------- + Half corner Violation Slew Slew Dont Ideal Target Pin + amount target achieved touch net? source + net? + --------------------------------------------------------------------------------------------------------------------------------------- + PVT_0P63V_100C.setup_delay:setup.late 0.7 69.3 70.0 N N auto computed cpu/stage1/regfile/mem_reg[20][8]/CLK + PVT_0P63V_100C.setup_delay:setup.late 0.7 69.3 70.0 N N auto computed cpu/stage1/regfile/mem_reg[20][11]/CLK + PVT_0P63V_100C.setup_delay:setup.late 0.7 69.3 70.0 N N auto computed cpu/stage1/regfile/mem_reg[20][14]/CLK + PVT_0P63V_100C.setup_delay:setup.late 0.7 69.3 70.0 N N auto computed cpu/stage1/regfile/mem_reg[20][15]/CLK + PVT_0P63V_100C.setup_delay:setup.late 0.7 69.3 70.0 N N auto computed cpu/stage1/regfile/mem_reg[20][17]/CLK + PVT_0P63V_100C.setup_delay:setup.late 0.7 69.3 70.0 N N auto computed cpu/stage1/regfile/mem_reg[20][26]/CLK + PVT_0P63V_100C.setup_delay:setup.late 0.1 69.3 69.4 N N auto computed cpu/stage1/regfile/mem_reg[20][20]/CLK + PVT_0P63V_100C.setup_delay:setup.late 0.1 69.3 69.4 N N auto computed cpu/stage1/regfile/mem_reg[20][23]/CLK + --------------------------------------------------------------------------------------------------------------------------------------- + + Target sources: + auto extracted - target was extracted from SDC. + auto computed - target was computed when balancing trees. + explicit - target is explicitly set via cts_target_max_transition_time property. + pin explicit - target is explicitly set for this pin via cts_pin_target_max_transition_time property. + liberty explicit - target is explicitly set via max_transition from liberty library. + + Found 0 pins on nets marked dont_touch that have slew violations. + Found 0 pins on nets marked dont_touch that do not have slew violations. + Found 0 pins on nets marked ideal_network that have slew violations. + Found 0 pins on nets marked ideal_network that do not have slew violations. + + + Post-balance tidy up or trial balance steps done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Post-balance tidy up or trial balance steps +Synthesizing clock trees done. +Tidy Up And Update Timing... +Connecting clock gate test enables... +Connecting clock gate test enables done. +External - Set all clocks to propagated mode... +Innovus updating I/O latencies +################################################################################# +# Design Stage: PreRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: No SPEF/RCDB +# Signoff Settings: SI Off +################################################################################# +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=1993.55) +Total number of fetched objects 9946 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +Total number of fetched objects 9946 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +End delay calculation. (MEM=2246.89 CPU=0:00:02.5 REAL=0:00:00.0) +End delay calculation (fullDC). (MEM=2246.89 CPU=0:00:04.1 REAL=0:00:01.0) + Clock: clk, View: PVT_0P63V_100C.setup_view, Ideal Latency: 0, Propagated Latency: 139 + Executing: set_clock_latency -source -early -min -rise -139 [get_pins clk] + Clock: clk, View: PVT_0P63V_100C.setup_view, Ideal Latency: 0, Propagated Latency: 139 + Executing: set_clock_latency -source -late -min -rise -139 [get_pins clk] + Clock: clk, View: PVT_0P63V_100C.setup_view, Ideal Latency: 0, Propagated Latency: 146.627 + Executing: set_clock_latency -source -early -min -fall -146.627 [get_pins clk] + Clock: clk, View: PVT_0P63V_100C.setup_view, Ideal Latency: 0, Propagated Latency: 146.627 + Executing: set_clock_latency -source -late -min -fall -146.627 [get_pins clk] + Clock: clk, View: PVT_0P63V_100C.setup_view, Ideal Latency: 0, Propagated Latency: 139 + Executing: set_clock_latency -source -early -max -rise -139 [get_pins clk] + Clock: clk, View: PVT_0P63V_100C.setup_view, Ideal Latency: 0, Propagated Latency: 139 + Executing: set_clock_latency -source -late -max -rise -139 [get_pins clk] + Clock: clk, View: PVT_0P63V_100C.setup_view, Ideal Latency: 0, Propagated Latency: 146.627 + Executing: set_clock_latency -source -early -max -fall -146.627 [get_pins clk] + Clock: clk, View: PVT_0P63V_100C.setup_view, Ideal Latency: 0, Propagated Latency: 146.627 + Executing: set_clock_latency -source -late -max -fall -146.627 [get_pins clk] + Clock: clk, View: PVT_0P77V_0C.hold_view, Ideal Latency: 0, Propagated Latency: 83.8638 + Executing: set_clock_latency -source -early -min -rise -83.8638 [get_pins clk] + Clock: clk, View: PVT_0P77V_0C.hold_view, Ideal Latency: 0, Propagated Latency: 83.8638 + Executing: set_clock_latency -source -late -min -rise -83.8638 [get_pins clk] + Clock: clk, View: PVT_0P77V_0C.hold_view, Ideal Latency: 0, Propagated Latency: 85.3423 + Executing: set_clock_latency -source -early -min -fall -85.3423 [get_pins clk] + Clock: clk, View: PVT_0P77V_0C.hold_view, Ideal Latency: 0, Propagated Latency: 85.3423 + Executing: set_clock_latency -source -late -min -fall -85.3423 [get_pins clk] + Clock: clk, View: PVT_0P77V_0C.hold_view, Ideal Latency: 0, Propagated Latency: 83.8638 + Executing: set_clock_latency -source -early -max -rise -83.8638 [get_pins clk] + Clock: clk, View: PVT_0P77V_0C.hold_view, Ideal Latency: 0, Propagated Latency: 83.8638 + Executing: set_clock_latency -source -late -max -rise -83.8638 [get_pins clk] + Clock: clk, View: PVT_0P77V_0C.hold_view, Ideal Latency: 0, Propagated Latency: 85.3423 + Executing: set_clock_latency -source -early -max -fall -85.3423 [get_pins clk] + Clock: clk, View: PVT_0P77V_0C.hold_view, Ideal Latency: 0, Propagated Latency: 85.3423 + Executing: set_clock_latency -source -late -max -fall -85.3423 [get_pins clk] +Setting all clocks to propagated mode. +External - Set all clocks to propagated mode done. (took cpu=0:00:06.3 real=0:00:02.3) +Clock DAG stats after update timingGraph: + cell counts : b=45, i=0, icg=43, nicg=0, l=0, total=88 + cell areas : b=146.267um^2, i=0.000um^2, icg=184.524um^2, nicg=0.000um^2, l=0.000um^2, total=330.791um^2 + cell capacitance : b=0.036pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.107pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.046pF, leaf=0.468pF, total=0.514pF + wire lengths : top=0.000um, trunk=1893.804um, leaf=17958.008um, total=19851.812um +Clock DAG net violations after update timingGraph: + Remaining Transition : {count=1, worst=[0.7ps]} avg=0.7ps sd=0.0ps sum=0.7ps +Clock DAG primary half-corner transition distribution after update timingGraph: + Trunk : target=69.3ps count=42 avg=21.8ps sd=15.6ps min=7.9ps max=64.0ps {35 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 1 <= 65.8ps, 0 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=7.1ps sd=0.1ps min=7.0ps max=7.2ps {0 <= 4.8ps, 0 <= 6.4ps, 4 <= 7.2ps, 0 <= 7.6ps, 0 <= 8.0ps} + Leaf : target=69.3ps count=43 avg=55.2ps sd=8.6ps min=24.8ps max=70.0ps {2 <= 41.6ps, 21 <= 55.4ps, 12 <= 62.4ps, 5 <= 65.8ps, 2 <= 69.3ps} {1 <= 72.8ps, 0 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} +Clock DAG library cell distribution after update timingGraph {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 30 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 BUFx2_ASAP7_75t_SRAM: 1 + ICGs: ICGx3_ASAP7_75t_SL: 8 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 +Primary reporting skew group after update timingGraph: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=145.1, sd=7.9], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=132.0 gs=32.5) +Skew group summary after update timingGraph: + skew_group clk/my_constraint_mode: insertion delay [min=127.5, max=160.8, avg=145.1, sd=7.9], skew [33.3 vs 33.6], 100% {127.5, 160.8} (wid=54.2 ws=40.4) (gid=132.0 gs=32.5) +Clock network insertion delays are now [127.5ps, 160.8ps] average 145.1ps std.dev 7.9ps +Logging CTS constraint violations... + Clock tree clk has 1 slew violation. +**WARN: (IMPCCOPT-1007): Did not meet the max transition constraint. Found 8 slew violations below cell cpu/stage1/regfile/CTS_ccl_a_buf_00036 (a lib_cell BUFx10_ASAP7_75t_SRAM) at (170.640,196.560), in power domain AO with half corner PVT_0P63V_100C.setup_delay:setup.late. The worst violation was at the pin cpu/stage1/regfile/mem_reg[20][26]/CLK with a slew time target of 69.3ps. Achieved a slew time of 70.0ps. + +Type 'man IMPCCOPT-1007' for more detail. +Logging CTS constraint violations done. +Tidy Up And Update Timing done. (took cpu=0:00:06.4 real=0:00:02.4) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Tidy Up And Update Timing +Runtime done. (took cpu=0:01:02 real=0:00:44.3) +Runtime Summary +=============== +Clock Runtime: (46%) Core CTS 20.51 (Init 5.35, Construction 4.95, Implementation 5.12, eGRPC 2.73, PostConditioning 1.44, Other 0.93) +Clock Runtime: (44%) CTS services 19.54 (RefinePlace 3.73, EarlyGlobalClock 0.76, NanoRoute 14.53, ExtractRC 0.52) +Clock Runtime: (8%) Other CTS 3.73 (Init 0.73, CongRepair 0.65, TimingUpdate 2.34, Other 0.01) +Clock Runtime: (100%) Total 43.79 + +Synthesizing clock trees with CCOpt done. + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: cts +**WARN: (IMPSP-9025): No scan chain specified/traced. +Type 'man IMPSP-9025' for more detail. +**INFO: set_db design_flow_effort standard -> setting 'set_db opt_all_end_points true' for the duration of this command. +Enable N7 maxLocalDensity: 0.92 +[GPS-MSV] CPF Flow. Number of Power Domains: 1 +[GPS-MSV] Power Domain 'AO' (tag=1) Default +GigaOpt running with 4 threads. +**WARN: (IMPOPT-3564): The following cells are set dont_use temporarily by the tool because there are no rows defined for their technology site, or they are not placeable in any power domain. To avoid this message, review the create_floorplan, msv setting, the library setting or set manualy those cells as dont_use. + Cell DECAPx10_ASAP7_75t_L, site coreSite. + Cell DECAPx10_ASAP7_75t_R, site coreSite. + Cell DECAPx10_ASAP7_75t_SL, site coreSite. + Cell DECAPx10_ASAP7_75t_SRAM, site coreSite. + Cell DECAPx1_ASAP7_75t_L, site coreSite. + Cell DECAPx1_ASAP7_75t_R, site coreSite. + Cell DECAPx1_ASAP7_75t_SL, site coreSite. + Cell DECAPx1_ASAP7_75t_SRAM, site coreSite. + Cell DECAPx2_ASAP7_75t_L, site coreSite. + Cell DECAPx2_ASAP7_75t_R, site coreSite. + Cell DECAPx2_ASAP7_75t_SL, site coreSite. + Cell DECAPx2_ASAP7_75t_SRAM, site coreSite. + Cell DECAPx4_ASAP7_75t_L, site coreSite. + Cell DECAPx4_ASAP7_75t_R, site coreSite. + Cell DECAPx4_ASAP7_75t_SL, site coreSite. + Cell DECAPx4_ASAP7_75t_SRAM, site coreSite. + Cell DECAPx6_ASAP7_75t_L, site coreSite. + Cell DECAPx6_ASAP7_75t_R, site coreSite. + Cell DECAPx6_ASAP7_75t_SL, site coreSite. + Cell DECAPx6_ASAP7_75t_SRAM, site coreSite. + ... + Reporting only the 20 first cells found... +. +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +**opt_design ... cpu = 0:00:00, real = 0:00:00, mem = 1399.5M, totSessionCpu=0:08:56 ** +*** opt_design -post_cts *** +DRC Margin: user margin 0.0; extra margin 0.2 +Hold Target Slack: user slack 0 +Setup Target Slack: user slack 0; extra slack 0.0 +set_db opt_useful_skew_eco_route false +Start to check current routing status for nets... +All nets are already routed correctly. +End to check current routing status for nets (mem=1868.5M) +**WARN: (EMS-27): Message (IMPTS-17) has exceeded the current message display limit of 1. +To increase the message display limit, refer to the product command reference manual. +################################################################################# +# Design Stage: PreRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: No SPEF/RCDB +# Signoff Settings: SI Off +################################################################################# +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=1898.54) +Total number of fetched objects 9946 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +End delay calculation. (MEM=2149.8 CPU=0:00:04.2 REAL=0:00:02.0) +End delay calculation (fullDC). (MEM=2149.8 CPU=0:00:05.1 REAL=0:00:02.0) +*** Done Building Timing Graph (cpu=0:00:06.4 real=0:00:02.0 totSessionCpu=0:09:03 mem=2149.8M) + +------------------------------------------------------------ + Initial Summary +------------------------------------------------------------ + +Setup views included: + PVT_0P63V_100C.setup_view + ++--------------------+---------+---------+---------+---------+ +| Setup mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| -0.042 | -0.042 | -0.033 | 0.172 | +| TNS (ns):| -0.837 | -0.803 | -0.033 | 0.000 | +| Violating Paths:| 47 | 46 | 1 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 7 (7) | -0.909 | 7 (7) | +| max_tran | 8 (9) | -4.905 | 23 (24) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 19.440% +------------------------------------------------------------ +**opt_design ... cpu = 0:00:08, real = 0:00:03, mem = 1431.5M, totSessionCpu=0:09:04 ** +** INFO : this run is activating low effort ccoptDesign flow +#optDebug: fT-E +*** Starting optimizing excluded clock nets MEM= 1912.9M) *** +*info: No excluded clock nets to be optimized. +*** Finished optimizing excluded clock nets (CPU Time= 0:00:00.0 MEM= 1912.9M) *** +*** Starting optimizing excluded clock nets MEM= 1912.9M) *** +*info: No excluded clock nets to be optimized. +*** Finished optimizing excluded clock nets (CPU Time= 0:00:00.0 MEM= 1912.9M) *** +Info: Done creating the CCOpt slew target map. +Begin: GigaOpt DRV Optimization +Info: 89 nets with fixed/cover wires excluded. +Info: 84 clock nets excluded from IPO operation. ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +| max-tran | max-cap | max-fanout | max-length | setup | | | | | | | ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +| nets | terms| wViol | nets | terms| wViol | nets | terms| nets | terms| WNS | TNS | #Buf | #Inv | #Resize|Density| Real | Mem | ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 28| 30| -5.10| 7| 7| -0.93| 0| 0| 0| 0| -0.04| -0.84| 0| 0| 0| 19.44| | | +| 11| 11| -5.04| 7| 7| -0.93| 0| 0| 0| 0| -0.04| -0.84| 16| 22| 18| 19.52| 0:00:00.0| 2259.1M| +| 6| 6| -5.04| 3| 3| -0.93| 0| 0| 0| 0| -0.04| -0.84| 1| 0| 5| 19.54| 0:00:00.0| 2259.1M| +| 6| 6| -5.04| 3| 3| -0.93| 0| 0| 0| 0| -0.04| -0.84| 1| 0| 0| 19.54| 0:00:00.0| 2259.1M| ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +**** Begin NDR-Layer Usage Statistics **** +Layer 3 has 89 constrained nets +Layer 4 has 42 constrained nets +**** End NDR-Layer Usage Statistics **** + + +======================================================================= + Reasons for remaining drv violations +======================================================================= +*info: Total 6 net(s) have violations which can't be fixed by DRV optimization. + +MultiBuffering failure reasons +------------------------------------------------ +*info: 1 net(s): Could not be fixed because the solution degraded timing. +*info: 4 net(s): Could not be fixed because it is def in clock net. +*info: 1 net(s): Could not be fixed because there is no usable buffer or delay cell for buffering. + +*info: Total 1 net(s) were new nets created by previous iteration of DRV buffering. Further DRV fixing might remove some violations. + + +*** Finish DRV Fixing (cpu=0:00:01.1 real=0:00:01.0 mem=2259.1M) *** + +*** Starting place_detail (0:09:11 mem=2259.1M) *** +Total net bbox length = 2.541e+05 (1.010e+05 1.531e+05) (ext = 3.755e+04) +Move report: Detail placement moves 83 insts, mean move: 0.95 um, max move: 2.81 um + Max move on inst (FE_OFC1393_mem_req_data_bits_125): (233.06, 2.16) --> (232.42, 4.32) + Runtime: CPU: 0:00:00.6 REAL: 0:00:00.0 MEM: 2259.1MB +Summary Report: +Instances move: 83 (out of 9179 movable) +Instances flipped: 28 +Mean displacement: 0.95 um +Max displacement: 2.81 um (Instance: FE_OFC1393_mem_req_data_bits_125) (233.064, 2.16) -> (232.416, 4.32) + Length: 30 sites, height: 1 rows, site name: coreSite, cell type: BUFx24_ASAP7_75t_SL +Total net bbox length = 2.542e+05 (1.011e+05 1.531e+05) (ext = 3.755e+04) +Runtime: CPU: 0:00:00.7 REAL: 0:00:00.0 MEM: 2259.1MB +*** Finished place_detail (0:09:12 mem=2259.1M) *** +*** maximum move = 2.81 um *** +*** Finished re-routing un-routed nets (2259.1M) *** + +*** Finish Physical Update (cpu=0:00:01.1 real=0:00:00.0 mem=2259.1M) *** +End: GigaOpt DRV Optimization + +------------------------------------------------------------ + Summary (cpu=0.12min real=0.08min mem=1977.9M) +------------------------------------------------------------ + +Setup views included: + PVT_0P63V_100C.setup_view + ++--------------------+---------+---------+---------+---------+ +| Setup mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| -0.042 | -0.042 | -0.033 | 0.172 | +| TNS (ns):| -0.837 | -0.803 | -0.033 | 0.000 | +| Violating Paths:| 47 | 46 | 1 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 3 (3) | -0.909 | 3 (3) | +| max_tran | 2 (2) | -4.840 | 2 (2) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 19.562% +Routing Overflow: 0.07% H and 0.49% V +------------------------------------------------------------ +**opt_design ... cpu = 0:00:16, real = 0:00:10, mem = 1519.7M, totSessionCpu=0:09:12 ** +*** Timing NOT met, worst failing slack is -0.042 +*** Check timing (0:00:00.0) +Begin: GigaOpt Optimization in TNS mode +Info: 89 nets with fixed/cover wires excluded. +Info: 84 clock nets excluded from IPO operation. +*info: 84 clock nets excluded +*info: 2 special nets excluded. +*info: 1132 no-driver nets excluded. +*info: 89 nets with fixed/cover wires excluded. +** GigaOpt Optimizer WNS Slack -0.042 TNS Slack -0.837 Density 19.56 +CCOptDebug: Start of Optimizer TNS Pass: reg2cgate* WNS -33.2ps TNS -33.2ps; reg2reg* WNS -42.4ps TNS -803.3ps; HEPG WNS -42.4ps TNS -803.3ps; all paths WNS -42.4ps TNS -836.5ps; Real time 0:01:05 +Active Path Group: reg2cgate reg2reg ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| WNS | All WNS | TNS | All TNS | Density | Real | Mem | Worst View |Pathgroup| End Point | ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| -0.042| -0.042| -0.837| -0.837| 19.56%| 0:00:00.0| 2088.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/s1_to_s2_rs2/register_reg[22]/D | +| -0.036| -0.036| -0.577| -0.577| 19.58%| 0:00:15.0| 2307.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.034| -0.034| -0.525| -0.525| 19.59%| 0:00:03.0| 2307.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.034| -0.034| -0.469| -0.469| 19.59%| 0:00:00.0| 2309.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.034| -0.034| -0.464| -0.464| 19.59%| 0:00:01.0| 2309.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.034| -0.034| -0.453| -0.453| 19.60%| 0:00:02.0| 2309.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.034| -0.034| -0.445| -0.445| 19.60%| 0:00:01.0| 2309.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.033| -0.033| -0.442| -0.442| 19.60%| 0:00:00.0| 2309.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.033| -0.033| -0.434| -0.434| 19.60%| 0:00:01.0| 2309.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.032| -0.032| -0.433| -0.433| 19.61%| 0:00:00.0| 2309.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.032| -0.032| -0.427| -0.427| 19.61%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.032| -0.032| -0.420| -0.420| 19.61%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.031| -0.031| -0.405| -0.405| 19.62%| 0:00:01.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.031| -0.031| -0.406| -0.406| 19.62%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.031| -0.031| -0.406| -0.406| 19.62%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.030| -0.030| -0.404| -0.404| 19.62%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.030| -0.030| -0.396| -0.396| 19.62%| 0:00:01.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.029| -0.029| -0.396| -0.396| 19.63%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.029| -0.029| -0.375| -0.375| 19.63%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.029| -0.029| -0.359| -0.359| 19.63%| 0:00:01.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.028| -0.028| -0.354| -0.354| 19.64%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.027| -0.027| -0.338| -0.338| 19.64%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.027| -0.027| -0.337| -0.337| 19.64%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.027| -0.027| -0.329| -0.329| 19.65%| 0:00:01.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.026| -0.026| -0.328| -0.328| 19.66%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.026| -0.026| -0.326| -0.326| 19.66%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.026| -0.026| -0.321| -0.321| 19.66%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.025| -0.025| -0.306| -0.306| 19.66%| 0:00:01.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.025| -0.025| -0.286| -0.286| 19.66%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.024| -0.024| -0.277| -0.277| 19.67%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.024| -0.024| -0.264| -0.264| 19.67%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.023| -0.023| -0.259| -0.259| 19.67%| 0:00:01.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.023| -0.023| -0.248| -0.248| 19.68%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.022| -0.022| -0.247| -0.247| 19.68%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.022| -0.022| -0.244| -0.244| 19.68%| 0:00:00.0| 2293.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.022| -0.022| -0.238| -0.238| 19.68%| 0:00:02.0| 2312.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.021| -0.021| -0.228| -0.228| 19.68%| 0:00:00.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.021| -0.021| -0.222| -0.222| 19.68%| 0:00:00.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.021| -0.021| -0.219| -0.219| 19.69%| 0:00:01.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.021| -0.021| -0.214| -0.214| 19.69%| 0:00:00.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.020| -0.020| -0.202| -0.202| 19.69%| 0:00:02.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.020| -0.020| -0.194| -0.194| 19.70%| 0:00:01.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.020| -0.020| -0.193| -0.193| 19.70%| 0:00:00.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.020| -0.020| -0.177| -0.177| 19.70%| 0:00:00.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[29]/D | +| -0.020| -0.020| -0.169| -0.169| 19.70%| 0:00:00.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[29]/D | +| -0.020| -0.020| -0.167| -0.167| 19.70%| 0:00:00.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[30]/D | +| -0.020| -0.020| -0.167| -0.167| 19.70%| 0:00:00.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[30]/D | +| -0.020| -0.020| -0.148| -0.148| 19.70%| 0:00:00.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[27]/D | +| -0.020| -0.020| -0.082| -0.082| 19.71%| 0:00:01.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[27]/D | +| -0.019| -0.019| -0.066| -0.066| 19.71%| 0:00:00.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[27]/D | +| -0.020| -0.020| -0.058| -0.058| 19.71%| 0:00:00.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[27]/D | +| -0.020| -0.020| -0.056| -0.056| 19.71%| 0:00:01.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[15]/D | +| -0.020| -0.020| -0.054| -0.054| 19.72%| 0:00:00.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[19]/D | +| -0.020| -0.020| -0.052| -0.052| 19.72%| 0:00:00.0| 2314.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[15]/D | +| -0.020| -0.020| -0.052| -0.052| 19.72%| 0:00:01.0| 2334.0M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ + +*** Finish Core Optimize Step (cpu=0:01:24 real=0:00:38.0 mem=2334.0M) *** + +*** Finished Optimize Step Cumulative (cpu=0:01:24 real=0:00:38.0 mem=2334.0M) *** +CCOptDebug: End of Optimizer TNS Pass: reg2cgate* WNS 3.2ps TNS 0.0ps; reg2reg* WNS -19.6ps TNS -52.3ps; HEPG WNS -19.6ps TNS -52.3ps; all paths WNS -19.6ps TNS -52.3ps; Real time 0:01:43 +** GigaOpt Optimizer WNS Slack -0.020 TNS Slack -0.052 Density 19.72 +*** Starting place_detail (0:10:44 mem=2334.0M) *** +Total net bbox length = 2.556e+05 (1.018e+05 1.538e+05) (ext = 3.755e+04) +Density distribution unevenness ratio = 60.968% +Move report: Detail placement moves 183 insts, mean move: 0.53 um, max move: 2.38 um + Max move on inst (cpu/stage1/regfile/FE_OCPC1428_FE_OFN1105_stage1_inst_18): (192.24, 222.48) --> (190.94, 223.56) + Runtime: CPU: 0:00:00.7 REAL: 0:00:00.0 MEM: 2334.0MB +Summary Report: +Instances move: 183 (out of 9237 movable) +Instances flipped: 5 +Mean displacement: 0.53 um +Max displacement: 2.38 um (Instance: cpu/stage1/regfile/FE_OCPC1428_FE_OFN1105_stage1_inst_18) (192.24, 222.48) -> (190.944, 223.56) + Length: 4 sites, height: 1 rows, site name: coreSite, cell type: INVx2_ASAP7_75t_SL +Total net bbox length = 2.556e+05 (1.018e+05 1.538e+05) (ext = 3.755e+04) +Runtime: CPU: 0:00:00.8 REAL: 0:00:01.0 MEM: 2334.0MB +*** Finished place_detail (0:10:45 mem=2334.0M) *** +*** maximum move = 2.38 um *** +*** Finished re-routing un-routed nets (2334.0M) *** + +*** Finish Physical Update (cpu=0:00:01.2 real=0:00:01.0 mem=2334.0M) *** +** GigaOpt Optimizer WNS Slack -0.020 TNS Slack -0.052 Density 19.72 +**** Begin NDR-Layer Usage Statistics **** +Layer 3 has 89 constrained nets +Layer 4 has 117 constrained nets +Layer 6 has 10 constrained nets +**** End NDR-Layer Usage Statistics **** + +*** Finish post-CTS Setup Fixing (cpu=0:01:26 real=0:00:40.0 mem=2334.0M) *** + +End: GigaOpt Optimization in TNS mode +Begin: GigaOpt Optimization in WNS mode +Info: 89 nets with fixed/cover wires excluded. +Info: 84 clock nets excluded from IPO operation. +*info: 84 clock nets excluded +*info: 2 special nets excluded. +*info: 1132 no-driver nets excluded. +*info: 89 nets with fixed/cover wires excluded. +** GigaOpt Optimizer WNS Slack -0.020 TNS Slack -0.052 Density 19.72 +CCOptDebug: Start of Optimizer WNS Pass 0: reg2cgate* WNS 3.2ps TNS 0.0ps; reg2reg* WNS -19.6ps TNS -52.3ps; HEPG WNS -19.6ps TNS -52.3ps; all paths WNS -19.6ps TNS -52.3ps; Real time 0:01:51 +Active Path Group: reg2cgate reg2reg ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| WNS | All WNS | TNS | All TNS | Density | Real | Mem | Worst View |Pathgroup| End Point | ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| -0.020| -0.020| -0.052| -0.052| 19.72%| 0:00:00.0| 2092.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.010| -0.010| -0.089| -0.089| 19.78%| 0:00:07.0| 2297.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.010| -0.010| -0.085| -0.085| 19.79%| 0:00:00.0| 2297.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.009| -0.009| -0.075| -0.075| 19.80%| 0:00:01.0| 2297.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.008| -0.008| -0.062| -0.062| 19.81%| 0:00:01.0| 2316.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.006| -0.006| -0.056| -0.056| 19.82%| 0:00:00.0| 2316.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/s1_to_s2_rs2/register_reg[20]/D | +| -0.005| -0.005| -0.027| -0.027| 19.82%| 0:00:01.0| 2316.9M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.004| -0.004| -0.020| -0.020| 19.82%| 0:00:00.0| 2338.0M|PVT_0P63V_100C.setup_view| reg2reg| cpu/s1_to_s2_rs2/register_reg[5]/D | +| -0.003| -0.003| -0.004| -0.004| 19.83%| 0:00:02.0| 2338.0M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.002| -0.002| -0.003| -0.003| 19.83%| 0:00:00.0| 2376.2M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.002| -0.002| -0.003| -0.003| 19.84%| 0:00:01.0| 2376.2M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.001| -0.001| -0.002| -0.002| 19.85%| 0:00:00.0| 2376.2M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.001| -0.001| -0.001| -0.001| 19.86%| 0:00:01.0| 2376.2M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| 0.001| 0.001| 0.000| 0.000| 19.86%| 0:00:04.0| 2338.0M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| 0.002| 0.002| 0.000| 0.000| 19.86%| 0:00:00.0| 2338.0M| NA| NA| NA | +| 0.002| 0.002| 0.000| 0.000| 19.86%| 0:00:00.0| 2338.0M|PVT_0P63V_100C.setup_view| NA| NA | ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ + +*** Finish Core Optimize Step (cpu=0:00:48.2 real=0:00:18.0 mem=2338.0M) *** + +*** Finished Optimize Step Cumulative (cpu=0:00:48.2 real=0:00:18.0 mem=2338.0M) *** +CCOptDebug: End of Optimizer WNS Pass 0: reg2cgate* WNS 5.9ps TNS 0.0ps; reg2reg* WNS 1.5ps TNS 0.0ps; HEPG WNS 1.5ps TNS 0.0ps; all paths WNS 1.5ps TNS 0.0ps; Real time 0:02:09 +** GigaOpt Optimizer WNS Slack 0.002 TNS Slack 0.000 Density 19.86 +*** Starting place_detail (0:11:41 mem=2338.0M) *** +Total net bbox length = 2.567e+05 (1.023e+05 1.544e+05) (ext = 3.755e+04) +Density distribution unevenness ratio = 60.993% +Move report: Detail placement moves 217 insts, mean move: 0.44 um, max move: 1.73 um + Max move on inst (cpu/stage1/pcadder/FE_RC_19_0_dup): (198.07, 169.56) --> (197.42, 168.48) + Runtime: CPU: 0:00:02.6 REAL: 0:00:01.0 MEM: 2338.0MB +Summary Report: +Instances move: 217 (out of 9292 movable) +Instances flipped: 5 +Mean displacement: 0.44 um +Max displacement: 1.73 um (Instance: cpu/stage1/pcadder/FE_RC_19_0_dup) (198.072, 169.56) -> (197.424, 168.48) + Length: 8 sites, height: 1 rows, site name: coreSite, cell type: OAI21x1_ASAP7_75t_SL +Total net bbox length = 2.567e+05 (1.023e+05 1.544e+05) (ext = 3.755e+04) +Runtime: CPU: 0:00:02.6 REAL: 0:00:01.0 MEM: 2338.0MB +*** Finished place_detail (0:11:44 mem=2338.0M) *** +*** maximum move = 1.73 um *** +*** Finished re-routing un-routed nets (2338.0M) *** + +*** Finish Physical Update (cpu=0:00:03.1 real=0:00:02.0 mem=2338.0M) *** +** GigaOpt Optimizer WNS Slack 0.002 TNS Slack 0.000 Density 19.86 +**** Begin NDR-Layer Usage Statistics **** +Layer 3 has 89 constrained nets +Layer 4 has 148 constrained nets +Layer 6 has 22 constrained nets +**** End NDR-Layer Usage Statistics **** + +*** Finish post-CTS Setup Fixing (cpu=0:00:52.2 real=0:00:20.0 mem=2338.0M) *** + +End: GigaOpt Optimization in WNS mode +Info: 89 nets with fixed/cover wires excluded. +Info: 84 clock nets excluded from IPO operation. +Begin: Area Reclaim Optimization +Usable buffer cells for single buffer setup transform: +HB1xp67_ASAP7_75t_SL HB1xp67_ASAP7_75t_L BUFx2_ASAP7_75t_SL BUFx2_ASAP7_75t_L BUFx3_ASAP7_75t_SL BUFx3_ASAP7_75t_L BUFx4_ASAP7_75t_SL BUFx5_ASAP7_75t_SL BUFx4f_ASAP7_75t_SL BUFx4f_ASAP7_75t_L BUFx6f_ASAP7_75t_SL BUFx6f_ASAP7_75t_L BUFx8_ASAP7_75t_SL BUFx10_ASAP7_75t_SL BUFx12_ASAP7_75t_SL BUFx12f_ASAP7_75t_SL BUFx12f_ASAP7_75t_L BUFx24_ASAP7_75t_SL +Number of usable buffer cells above: 18 +Reclaim Optimization WNS Slack 0.002 TNS Slack 0.000 Density 19.86 ++----------+---------+--------+--------+------------+--------+ +| Density | Commits | WNS | TNS | Real | Mem | ++----------+---------+--------+--------+------------+--------+ +| 19.86%| -| 0.002| 0.000| 0:00:00.0| 2088.1M| +| 19.86%| 0| 0.002| 0.000| 0:00:01.0| 2164.4M| +| 19.86%| 107| 0.002| 0.000| 0:00:01.0| 2259.8M| +| 19.80%| 45| 0.002| 0.000| 0:00:01.0| 2259.8M| +| 19.78%| 6| 0.002| 0.000| 0:00:00.0| 2259.8M| +| 19.61%| 497| 0.000| 0.000| 0:00:03.0| 2278.9M| +| 19.60%| 25| -0.002| -0.002| 0:00:01.0| 2278.9M| +| 19.60%| 0| -0.002| -0.002| 0:00:00.0| 2278.9M| +| 19.60%| 5| -0.002| -0.002| 0:00:00.0| 2278.9M| ++----------+---------+--------+--------+------------+--------+ +Reclaim Optimization End WNS Slack -0.002 TNS Slack -0.002 Density 19.60 +**** Begin NDR-Layer Usage Statistics **** +Layer 3 has 89 constrained nets +Layer 4 has 47 constrained nets +Layer 6 has 16 constrained nets +**** End NDR-Layer Usage Statistics **** +** Finished Core Area Reclaim Optimization (cpu = 0:00:18.2) (real = 0:00:08.0) ** +*** Starting place_detail (0:12:03 mem=2278.9M) *** +Total net bbox length = 2.569e+05 (1.023e+05 1.546e+05) (ext = 3.755e+04) +Move report: Detail placement moves 0 insts, mean move: 0.00 um, max move: 0.00 um + Runtime: CPU: 0:00:02.3 REAL: 0:00:01.0 MEM: 2278.9MB +Summary Report: +Instances move: 0 (out of 9241 movable) +Instances flipped: 0 +Mean displacement: 0.00 um +Max displacement: 0.00 um +Total net bbox length = 2.569e+05 (1.023e+05 1.546e+05) (ext = 3.755e+04) +Runtime: CPU: 0:00:02.3 REAL: 0:00:01.0 MEM: 2278.9MB +*** Finished place_detail (0:12:05 mem=2278.9M) *** +*** maximum move = 0.00 um *** +*** Finished re-routing un-routed nets (2278.9M) *** + +*** Finish Physical Update (cpu=0:00:02.8 real=0:00:01.0 mem=2278.9M) *** +*** Finished Area Reclaim Optimization (cpu=0:00:21, real=0:00:09, mem=1977.89M, totSessionCpu=0:12:05). + +Starting congestion repair ... +[NR-eGR] honorMsvRouteConstraint: false +[NR-eGR] honorClockSpecNDR : 0 +[NR-eGR] minRouteLayer : 2 +[NR-eGR] maxRouteLayer : 7 +[NR-eGR] numTracksPerClockWire : 0 +[NR-eGR] M1 has no routable track +[NR-eGR] M2 has non-uniform track structures +[NR-eGR] M3 has single uniform track structure +[NR-eGR] M4 has single uniform track structure +[NR-eGR] M5 has single uniform track structure +[NR-eGR] M6 has single uniform track structure +[NR-eGR] M7 has single uniform track structure +[NR-eGR] Read 53034 PG shapes in 0.010 seconds + +[NR-eGR] numRoutingBlks=0 numInstBlks=2387 numPGBlocks=53034 numBumpBlks=0 numBoundaryFakeBlks=0 +[NR-eGR] Num Prerouted Nets = 89 Num Prerouted Wires = 9600 +[NR-eGR] Read numTotalNets=9768 numIgnoredNets=89 +[NR-eGR] ============ Routing rule table ============ +[NR-eGR] Rule id: 0 Nets: 9679 +[NR-eGR] Rule id: 1 Nets: 0 +[NR-eGR] ======================================== +[NR-eGR] +[NR-eGR] Layer group 1: route 16 net(s) in layer range [6, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.02% H + 0.03% V. EstWL: 1.944000e+03um +[NR-eGR] +[NR-eGR] Layer group 2: route 46 net(s) in layer range [4, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 2: 0.09% H + 0.08% V. EstWL: 7.050240e+03um +[NR-eGR] +[NR-eGR] Layer group 3: route 9617 net(s) in layer range [2, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 3: 0.10% H + 0.59% V. EstWL: 2.597530e+05um +[NR-eGR] +[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded) +[NR-eGR] OverCon OverCon OverCon +[NR-eGR] #Gcell #Gcell #Gcell %Gcell +[NR-eGR] Layer (1-2) (3-4) (5-5) OverCon +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] M1 (1) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M2 (2) 152( 0.17%) 7( 0.01%) 0( 0.00%) ( 0.18%) +[NR-eGR] M3 (3) 1727( 1.93%) 153( 0.17%) 2( 0.00%) ( 2.10%) +[NR-eGR] M4 (4) 566( 0.54%) 25( 0.02%) 0( 0.00%) ( 0.56%) +[NR-eGR] M5 (5) 484( 0.50%) 5( 0.01%) 0( 0.00%) ( 0.50%) +[NR-eGR] M6 (6) 51( 0.05%) 0( 0.00%) 0( 0.00%) ( 0.05%) +[NR-eGR] M7 (7) 69( 0.07%) 0( 0.00%) 0( 0.00%) ( 0.07%) +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] Total 3049( 0.53%) 190( 0.03%) 2( 0.00%) ( 0.56%) +[NR-eGR] +[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.06% H + 0.42% V +[NR-eGR] Overflow after earlyGlobalRoute 0.07% H + 0.52% V +Early Global Route congestion estimation runtime: 0.48 seconds, mem = 1986.9M +Local HotSpot Analysis: normalized max congestion hotspot area = 2.62, normalized total congestion hotspot area = 6.82 (area is in unit of 4 std-cell row bins) + +=== incrementalPlace Internal Loop 1 === +Skipped repairing congestion. +End of congRepair (cpu=0:00:00.5, real=0:00:01.0) +[NR-eGR] Started earlyGlobalRoute kernel +[NR-eGR] Initial Peak syMemory usage = 1987.6 MB +[NR-eGR] honorMsvRouteConstraint: false +[NR-eGR] honorClockSpecNDR : 0 +[NR-eGR] minRouteLayer : 2 +[NR-eGR] maxRouteLayer : 7 +[NR-eGR] numTracksPerClockWire : 0 +[NR-eGR] M1 has no routable track +[NR-eGR] M2 has non-uniform track structures +[NR-eGR] M3 has single uniform track structure +[NR-eGR] M4 has single uniform track structure +[NR-eGR] M5 has single uniform track structure +[NR-eGR] M6 has single uniform track structure +[NR-eGR] M7 has single uniform track structure +[NR-eGR] Read 53034 PG shapes in 0.010 seconds + +[NR-eGR] numRoutingBlks=0 numInstBlks=2387 numPGBlocks=53034 numBumpBlks=0 numBoundaryFakeBlks=0 +[NR-eGR] Num Prerouted Nets = 89 Num Prerouted Wires = 9600 +[NR-eGR] Read numTotalNets=9768 numIgnoredNets=89 +[NR-eGR] ============ Routing rule table ============ +[NR-eGR] Rule id: 0 Nets: 9679 +[NR-eGR] Rule id: 1 Nets: 0 +[NR-eGR] ======================================== +[NR-eGR] +[NR-eGR] Layer group 1: route 16 net(s) in layer range [6, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.02% H + 0.03% V. EstWL: 1.944000e+03um +[NR-eGR] +[NR-eGR] Layer group 2: route 46 net(s) in layer range [4, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 2: 0.09% H + 0.08% V. EstWL: 7.050240e+03um +[NR-eGR] +[NR-eGR] Layer group 3: route 9617 net(s) in layer range [2, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 3: 0.10% H + 0.59% V. EstWL: 2.597530e+05um +[NR-eGR] +[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded) +[NR-eGR] OverCon OverCon OverCon +[NR-eGR] #Gcell #Gcell #Gcell %Gcell +[NR-eGR] Layer (1-2) (3-4) (5-5) OverCon +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] M1 (1) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M2 (2) 152( 0.17%) 7( 0.01%) 0( 0.00%) ( 0.18%) +[NR-eGR] M3 (3) 1727( 1.93%) 153( 0.17%) 2( 0.00%) ( 2.10%) +[NR-eGR] M4 (4) 566( 0.54%) 25( 0.02%) 0( 0.00%) ( 0.56%) +[NR-eGR] M5 (5) 484( 0.50%) 5( 0.01%) 0( 0.00%) ( 0.50%) +[NR-eGR] M6 (6) 51( 0.05%) 0( 0.00%) 0( 0.00%) ( 0.05%) +[NR-eGR] M7 (7) 69( 0.07%) 0( 0.00%) 0( 0.00%) ( 0.07%) +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] Total 3049( 0.53%) 190( 0.03%) 2( 0.00%) ( 0.56%) +[NR-eGR] +[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.06% H + 0.42% V +[NR-eGR] Overflow after earlyGlobalRoute 0.07% H + 0.52% V +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] M1 (1F) length: 0.000000e+00um, number of vias: 32181 +[NR-eGR] M2 (2H) length: 6.992623e+04um, number of vias: 48450 +[NR-eGR] M3 (3V) length: 8.561196e+04um, number of vias: 10583 +[NR-eGR] M4 (4H) length: 3.586270e+04um, number of vias: 7360 +[NR-eGR] M5 (5V) length: 4.997759e+04um, number of vias: 2835 +[NR-eGR] M6 (6H) length: 2.112487e+04um, number of vias: 1649 +[NR-eGR] M7 (7V) length: 3.322240e+04um, number of vias: 0 +[NR-eGR] Total length: 2.957258e+05um, number of vias: 103058 +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] Total eGR-routed clock nets wire length: 0.000000e+00um +[NR-eGR] -------------------------------------------------------------------------- +[NR-eGR] End Peak syMemory usage = 1943.7 MB +[NR-eGR] Early Global Router Kernel+IO runtime : 0.83 seconds +Extraction called for design 'riscv_top' of instances=12156 and nets=10983 using extraction engine 'pre_route' . +pre_route RC Extraction called for design riscv_top. +RC Extraction called in multi-corner(2) mode. +RCMode: PreRoute + RC Corner Indexes 0 1 +Capacitance Scaling Factor : 1.00000 1.00000 +Resistance Scaling Factor : 1.00000 1.00000 +Clock Cap. Scaling Factor : 1.00000 1.00000 +Clock Res. Scaling Factor : 1.00000 1.00000 +Shrink Factor : 1.00000 +PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets. +Using Quantus QRC technology file ... +Updating RC grid for preRoute extraction ... +Initializing multi-corner resistance tables ... +PreRoute RC Extraction DONE (CPU Time: 0:00:00.2 Real Time: 0:00:00.0 MEM: 1943.719M) +Compute RC Scale Done ... +[hotspot] +------------+---------------+---------------+ +[hotspot] | | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | normalized | 2.62 | 6.82 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis: normalized max congestion hotspot area = 2.62, normalized total congestion hotspot area = 6.82 (area is in unit of 4 std-cell row bins) +[hotspot] top 5 congestion hotspot bounding boxes and scores of normalized hotspot +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | top | hotspot bbox | hotspot score | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 1 | 250.56 103.68 267.84 120.96 | 1.05 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 2 | 250.56 120.96 267.84 138.24 | 1.05 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 3 | 138.24 164.16 155.52 181.44 | 1.05 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 4 | 164.16 146.88 181.44 164.16 | 0.79 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 5 | 164.16 164.16 181.44 181.44 | 0.79 | +[hotspot] +-----+-------------------------------------+---------------+ +################################################################################# +# Design Stage: PreRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: No SPEF/RCDB +# Signoff Settings: SI Off +################################################################################# +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=1975.34) +Total number of fetched objects 10048 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +End delay calculation. (MEM=2209.53 CPU=0:00:03.9 REAL=0:00:01.0) +End delay calculation (fullDC). (MEM=2209.53 CPU=0:00:04.9 REAL=0:00:01.0) +Begin: GigaOpt postEco DRV Optimization +Info: 89 nets with fixed/cover wires excluded. +Info: 84 clock nets excluded from IPO operation. ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +| max-tran | max-cap | max-fanout | max-length | setup | | | | | | | ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +| nets | terms| wViol | nets | terms| wViol | nets | terms| nets | terms| WNS | TNS | #Buf | #Inv | #Resize|Density| Real | Mem | ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 28| 33| -5.04| 3| 3| -0.93| 0| 0| 0| 0| -0.01| -0.02| 0| 0| 0| 19.60| | | +| 8| 8| -5.04| 3| 3| -0.93| 0| 0| 0| 0| -0.01| -0.02| 27| 26| 21| 19.72| 0:00:00.0| 2319.0M| +| 6| 6| -5.04| 3| 3| -0.93| 0| 0| 0| 0| -0.01| -0.02| 2| 0| 3| 19.73| 0:00:00.0| 2319.0M| +| 6| 6| -5.04| 3| 3| -0.93| 0| 0| 0| 0| -0.01| -0.02| 1| 0| 0| 19.73| 0:00:00.0| 2319.0M| ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +**** Begin NDR-Layer Usage Statistics **** +Layer 3 has 89 constrained nets +Layer 4 has 43 constrained nets +Layer 6 has 16 constrained nets +**** End NDR-Layer Usage Statistics **** + + +======================================================================= + Reasons for remaining drv violations +======================================================================= +*info: Total 6 net(s) have violations which can't be fixed by DRV optimization. + +MultiBuffering failure reasons +------------------------------------------------ +*info: 4 net(s): Could not be fixed because it is def in clock net. +*info: 2 net(s): Could not be fixed because there is no usable buffer or delay cell for buffering. + +*info: Total 1 net(s) were new nets created by previous iteration of DRV buffering. Further DRV fixing might remove some violations. + + +*** Finish DRV Fixing (cpu=0:00:01.6 real=0:00:00.0 mem=2319.0M) *** + +*** Starting place_detail (0:12:18 mem=2319.0M) *** +Total net bbox length = 2.571e+05 (1.024e+05 1.548e+05) (ext = 3.755e+04) +Move report: Detail placement moves 11 insts, mean move: 2.40 um, max move: 4.54 um + Max move on inst (mem/dcache/FE_OFC1545_FE_OFN1337_n): (262.44, 19.44) --> (257.90, 19.44) + Runtime: CPU: 0:00:02.4 REAL: 0:00:01.0 MEM: 2319.0MB +Summary Report: +Instances move: 11 (out of 9297 movable) +Instances flipped: 1 +Mean displacement: 2.40 um +Max displacement: 4.54 um (Instance: mem/dcache/FE_OFC1545_FE_OFN1337_n) (262.44, 19.44) -> (257.904, 19.44) + Length: 4 sites, height: 1 rows, site name: coreSite, cell type: INVx2_ASAP7_75t_SL +Total net bbox length = 2.571e+05 (1.024e+05 1.548e+05) (ext = 3.755e+04) +Runtime: CPU: 0:00:02.4 REAL: 0:00:01.0 MEM: 2319.0MB +*** Finished place_detail (0:12:21 mem=2319.0M) *** +*** maximum move = 4.54 um *** +*** Finished re-routing un-routed nets (2319.0M) *** + +*** Finish Physical Update (cpu=0:00:02.9 real=0:00:02.0 mem=2319.0M) *** +End: GigaOpt postEco DRV Optimization +GigaOpt: WNS changes after routing: -0.001 -> -0.010 (bump = 0.009) +GigaOpt: WNS bump threshold: -1.0 +Begin: GigaOpt postEco optimization +Info: 89 nets with fixed/cover wires excluded. +Info: 84 clock nets excluded from IPO operation. +*info: 84 clock nets excluded +*info: 2 special nets excluded. +*info: 1132 no-driver nets excluded. +*info: 89 nets with fixed/cover wires excluded. +** GigaOpt Optimizer WNS Slack -0.010 TNS Slack -0.022 Density 19.74 +CCOptDebug: Start of Optimizer WNS Pass 0: reg2cgate* WNS 3.6ps TNS 0.0ps; reg2reg* WNS -9.8ps TNS -22.0ps; HEPG WNS -9.8ps TNS -22.0ps; all paths WNS -9.8ps TNS -22.0ps; Real time 0:02:34 +Active Path Group: reg2cgate reg2reg ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| WNS | All WNS | TNS | All TNS | Density | Real | Mem | Worst View |Pathgroup| End Point | ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| -0.010| -0.010| -0.022| -0.022| 19.74%| 0:00:00.0| 2318.3M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| 0.000| 0.000| 0.000| 0.000| 19.74%| 0:00:01.0| 2318.3M|PVT_0P63V_100C.setup_view| NA| NA | ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ + +*** Finish Core Optimize Step (cpu=0:00:03.0 real=0:00:01.0 mem=2318.3M) *** + +*** Finished Optimize Step Cumulative (cpu=0:00:03.0 real=0:00:01.0 mem=2318.3M) *** +CCOptDebug: End of Optimizer WNS Pass 0: reg2cgate* WNS 3.6ps TNS 0.0ps; reg2reg* WNS 0.1ps TNS 0.0ps; HEPG WNS 0.1ps TNS 0.0ps; all paths WNS 0.1ps TNS 0.0ps; Real time 0:02:36 +** GigaOpt Optimizer WNS Slack 0.000 TNS Slack 0.000 Density 19.74 +*** Starting place_detail (0:12:31 mem=2318.3M) *** +Total net bbox length = 2.572e+05 (1.024e+05 1.548e+05) (ext = 3.755e+04) +Move report: Detail placement moves 0 insts, mean move: 0.00 um, max move: 0.00 um + Runtime: CPU: 0:00:02.3 REAL: 0:00:01.0 MEM: 2318.3MB +Summary Report: +Instances move: 0 (out of 9299 movable) +Instances flipped: 0 +Mean displacement: 0.00 um +Max displacement: 0.00 um +Total net bbox length = 2.572e+05 (1.024e+05 1.548e+05) (ext = 3.755e+04) +Runtime: CPU: 0:00:02.4 REAL: 0:00:01.0 MEM: 2318.3MB +*** Finished place_detail (0:12:33 mem=2318.3M) *** +*** maximum move = 0.00 um *** +*** Finished re-routing un-routed nets (2318.3M) *** + +*** Finish Physical Update (cpu=0:00:02.8 real=0:00:01.0 mem=2318.3M) *** +** GigaOpt Optimizer WNS Slack 0.000 TNS Slack 0.000 Density 19.74 +**** Begin NDR-Layer Usage Statistics **** +Layer 3 has 89 constrained nets +Layer 4 has 43 constrained nets +Layer 6 has 16 constrained nets +**** End NDR-Layer Usage Statistics **** + +*** Finish post-CTS Setup Fixing (cpu=0:00:06.7 real=0:00:03.0 mem=2318.3M) *** + +End: GigaOpt postEco optimization +*** Steiner Routed Nets: 1.445%; Threshold: 100; Threshold for Hold: 100 +Re-routed 0 nets +#optDebug: fT-D + +Active setup views: + PVT_0P63V_100C.setup_view + Dominating endpoints: 0 + Dominating TNS: -0.000 + +Extraction called for design 'riscv_top' of instances=12214 and nets=11041 using extraction engine 'pre_route' . +pre_route RC Extraction called for design riscv_top. +RC Extraction called in multi-corner(2) mode. +RCMode: PreRoute + RC Corner Indexes 0 1 +Capacitance Scaling Factor : 1.00000 1.00000 +Resistance Scaling Factor : 1.00000 1.00000 +Clock Cap. Scaling Factor : 1.00000 1.00000 +Clock Res. Scaling Factor : 1.00000 1.00000 +Shrink Factor : 1.00000 +PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets. +Using Quantus QRC technology file ... +Initializing multi-corner resistance tables ... +PreRoute RC Extraction DONE (CPU Time: 0:00:00.2 Real Time: 0:00:00.0 MEM: 1899.332M) +[NR-eGR] honorMsvRouteConstraint: false +[NR-eGR] honorClockSpecNDR : 0 +[NR-eGR] minRouteLayer : 2 +[NR-eGR] maxRouteLayer : 7 +[NR-eGR] numTracksPerClockWire : 0 +[NR-eGR] M1 has no routable track +[NR-eGR] M2 has non-uniform track structures +[NR-eGR] M3 has single uniform track structure +[NR-eGR] M4 has single uniform track structure +[NR-eGR] M5 has single uniform track structure +[NR-eGR] M6 has single uniform track structure +[NR-eGR] M7 has single uniform track structure +[NR-eGR] Read 53034 PG shapes in 0.010 seconds + +[NR-eGR] numRoutingBlks=0 numInstBlks=2387 numPGBlocks=53034 numBumpBlks=0 numBoundaryFakeBlks=0 +[NR-eGR] Num Prerouted Nets = 89 Num Prerouted Wires = 9600 +[NR-eGR] Read numTotalNets=9826 numIgnoredNets=89 +[NR-eGR] ============ Routing rule table ============ +[NR-eGR] Rule id: 0 Nets: 9737 +[NR-eGR] Rule id: 1 Nets: 0 +[NR-eGR] ======================================== +[NR-eGR] +[NR-eGR] Layer group 1: route 16 net(s) in layer range [6, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.02% H + 0.03% V. EstWL: 1.944000e+03um +[NR-eGR] +[NR-eGR] Layer group 2: route 42 net(s) in layer range [4, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 2: 0.09% H + 0.08% V. EstWL: 6.958440e+03um +[NR-eGR] +[NR-eGR] Layer group 3: route 9679 net(s) in layer range [2, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 3: 0.10% H + 0.56% V. EstWL: 2.602973e+05um +[NR-eGR] +[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded) +[NR-eGR] OverCon OverCon OverCon +[NR-eGR] #Gcell #Gcell #Gcell %Gcell +[NR-eGR] Layer (1-2) (3-4) (5-5) OverCon +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] M1 (1) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M2 (2) 131( 0.15%) 8( 0.01%) 0( 0.00%) ( 0.16%) +[NR-eGR] M3 (3) 1723( 1.92%) 165( 0.18%) 4( 0.00%) ( 2.11%) +[NR-eGR] M4 (4) 572( 0.55%) 25( 0.02%) 0( 0.00%) ( 0.57%) +[NR-eGR] M5 (5) 486( 0.50%) 4( 0.00%) 0( 0.00%) ( 0.50%) +[NR-eGR] M6 (6) 57( 0.06%) 1( 0.00%) 0( 0.00%) ( 0.06%) +[NR-eGR] M7 (7) 60( 0.06%) 0( 0.00%) 0( 0.00%) ( 0.06%) +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] Total 3029( 0.53%) 203( 0.04%) 4( 0.00%) ( 0.56%) +[NR-eGR] +[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.06% H + 0.40% V +[NR-eGR] Overflow after earlyGlobalRoute 0.08% H + 0.48% V +[NR-eGR] End Peak syMemory usage = 1908.3 MB +[NR-eGR] Early Global Router Kernel+IO runtime : 0.45 seconds +[hotspot] +------------+---------------+---------------+ +[hotspot] | | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | normalized | 1.57 | 5.51 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis: normalized max congestion hotspot area = 1.57, normalized total congestion hotspot area = 5.51 (area is in unit of 4 std-cell row bins) +[hotspot] top 5 congestion hotspot bounding boxes and scores of normalized hotspot +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | top | hotspot bbox | hotspot score | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 1 | 250.56 103.68 267.84 120.96 | 1.05 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 2 | 138.24 164.16 155.52 181.44 | 1.05 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 3 | 250.56 120.96 267.84 138.24 | 0.52 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 4 | 164.16 155.52 181.44 172.80 | 0.52 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 5 | 103.68 164.16 120.96 181.44 | 0.52 | +[hotspot] +-----+-------------------------------------+---------------+ +GigaOpt Hold Optimizer is used +Starting initialization (fixHold) cpu=0:00:00.0 real=0:00:00.0 totSessionCpu=0:12:35 mem=1908.3M *** +**INFO: Starting Non-Blocking QThread +**INFO: Distributing 4 CPU to Master 2 CPU and QThread 2 CPU +Multi-CPU acceleration using 2 CPU(s). +################################################################################# +# Design Stage: PreRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: No SPEF/RCDB +# Signoff Settings: SI Off +################################################################################# +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Start delay calculation (fullDC) (2 T). (MEM=1892.83) +Total number of fetched objects 10106 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +End delay calculation. (MEM=2039.63 CPU=0:00:04.0 REAL=0:00:02.0) +End delay calculation (fullDC). (MEM=2039.63 CPU=0:00:04.8 REAL=0:00:02.0) +*** Done Building Timing Graph (cpu=0:00:05.9 real=0:00:04.0 totSessionCpu=0:12:43 mem=2039.6M) +Done building cte setup timing graph (fixHold) cpu=0:00:08.8 real=0:00:06.0 totSessionCpu=0:12:43 mem=2039.6M *** + ____________________________________________________________________ +__/ message from Non-Blocking QThread +*** QThread HoldInit [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), mem = 0.3M +Multithreaded Timing Analysis is initialized with 2 threads + +################################################################################# +# Design Stage: PreRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: No SPEF/RCDB +# Signoff Settings: SI Off +################################################################################# +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (2 T). (MEM=0) +*** Calculating scaling factor for PVT_0P77V_0C.hold_set libraries using the default operating condition of each library. +Total number of fetched objects 10106 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +End delay calculation. (MEM=0 CPU=0:00:05.9 REAL=0:00:04.0) +End delay calculation (fullDC). (MEM=0 CPU=0:00:06.9 REAL=0:00:04.0) +*** Done Building Timing Graph (cpu=0:00:07.7 real=0:00:05.0 totSessionCpu=0:00:08.6 mem=0.0M) + +Active hold views: + PVT_0P77V_0C.hold_view + Dominating endpoints: 0 + Dominating TNS: -0.000 + +Done building cte hold timing graph (fixHold) cpu=0:00:08.6 real=0:00:05.0 totSessionCpu=0:00:08.6 mem=0.0M *** +Done building hold timer [26202 node(s), 34700 edge(s), 1 view(s)] (fixHold) cpu=0:00:09.6 real=0:00:06.0 totSessionCpu=0:00:09.7 mem=0.0M *** +*** QThread HoldInit [finish] : cpu/real = 0:00:09.7/0:00:06.0 (1.6), mem = 0.0M +_______________________________________________________________________ +Restoring Auto Hold Views: PVT_0P77V_0C.hold_view +Restoring Active Hold Views: PVT_0P77V_0C.hold_view +Restoring Hold Target Slack: 0 + +*Info: minBufDelay = 7.5 ps, libStdDelay = 1.0 ps, minBufSize = 14929920 (4.0) +*Info: worst delay setup view: PVT_0P63V_100C.setup_view + +------------------------------------------------------------ + Initial Summary +------------------------------------------------------------ + +Setup views included: + PVT_0P63V_100C.setup_view +Hold views included: + PVT_0P77V_0C.hold_view + ++--------------------+---------+---------+---------+---------+ +| Setup mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| 0.000 | 0.000 | 0.004 | 0.173 | +| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | +| Violating Paths:| 0 | 0 | 0 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++--------------------+---------+---------+---------+---------+ +| Hold mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| -0.091 | -0.091 | -0.030 | -0.086 | +| TNS (ns):| -57.405 | -56.021 | -0.217 | -4.245 | +| Violating Paths:| 1297 | 1269 | 25 | 111 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 3 (3) | -0.909 | 3 (3) | +| max_tran | 2 (2) | -4.837 | 2 (2) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 19.740% +Routing Overflow: 0.08% H and 0.48% V +------------------------------------------------------------ +**opt_design ... cpu = 0:03:59, real = 0:02:00, mem = 1552.4M, totSessionCpu=0:12:56 ** +*info: Run opt_design holdfix with 4 threads. +Info: 89 nets with fixed/cover wires excluded. +Info: 84 clock nets excluded from IPO operation. +Info: Do not create the CCOpt slew target map as it already exists. + +*** Starting Core Fixing (fixHold) cpu=0:00:21.4 real=0:00:10.0 totSessionCpu=0:12:56 mem=2107.3M density=19.740% *** + +Phase I ...... +Executing transform: ECO Safe Resize ++----+--------+---------+--------+-----------+----------------+----------+------------+---------+ +|Iter| WNS | TNS | #VP | #Buffer | #Resize(F/F) | Density | Real | Mem | ++----+--------+---------+--------+-----------+----------------+----------+------------+---------+ +| 0| -0.091| -57.41| 1297| 0| 0( 0)| 19.74%| 0:00:00.0| 2176.7M| +| 1| -0.091| -57.41| 1297| 0| 0( 0)| 19.74%| 0:00:00.0| 2195.8M| ++----+--------+---------+--------+-----------+----------------+----------+------------+---------+ +Executing transform: AddBuffer + LegalResize ++----+--------+---------+--------+-----------+----------------+----------+------------+---------+ +|Iter| WNS | TNS | #VP | #Buffer | #Resize(F/F) | Density | Real | Mem | ++----+--------+---------+--------+-----------+----------------+----------+------------+---------+ +| 0| -0.091| -57.41| 1297| 0| 0( 0)| 19.74%| 0:00:00.0| 2195.8M| +| 1| -0.081| -25.88| 1202| 1161| 0( 0)| 21.62%| 0:00:16.0| 2308.3M| +| 2| -0.060| -6.19| 366| 729| 0( 0)| 22.65%| 0:00:10.0| 2308.3M| +| 3| -0.054| -1.01| 112| 346| 6( 0)| 23.09%| 0:00:05.0| 2308.3M| +| 4| -0.027| -0.03| 4| 99| 9( 0)| 23.21%| 0:00:02.0| 2308.3M| +| 5| 0.000| 0.00| 0| 5| 1( 0)| 23.22%| 0:00:00.0| 2308.3M| ++----+--------+---------+--------+-----------+----------------+----------+------------+---------+ + +*info: Total 2340 cells added for Phase I +*info: Total 16 instances resized for Phase I + +*** Finished Core Fixing (fixHold) cpu=0:02:15 real=0:00:44.0 totSessionCpu=0:14:49 mem=2356.1M density=23.220% *** + +*info: +*info: Added a total of 2340 cells to fix/reduce hold violation +*info: +*info: Summary: +*info: 37 cells of type 'HB1xp67_ASAP7_75t_SL' used +*info: 22 cells of type 'HB1xp67_ASAP7_75t_L' used +*info: 127 cells of type 'HB1xp67_ASAP7_75t_SRAM' used +*info: 213 cells of type 'BUFx2_ASAP7_75t_SL' used +*info: 5 cells of type 'BUFx2_ASAP7_75t_L' used +*info: 27 cells of type 'HB2xp67_ASAP7_75t_SL' used +*info: 91 cells of type 'HB2xp67_ASAP7_75t_SRAM' used +*info: 2 cells of type 'BUFx3_ASAP7_75t_SL' used +*info: 258 cells of type 'HB3xp67_ASAP7_75t_SL' used +*info: 148 cells of type 'HB3xp67_ASAP7_75t_R' used +*info: 126 cells of type 'HB3xp67_ASAP7_75t_SRAM' used +*info: 5 cells of type 'BUFx4_ASAP7_75t_SRAM' used +*info: 8 cells of type 'HB4xp67_ASAP7_75t_SL' used +*info: 13 cells of type 'HB4xp67_ASAP7_75t_L' used +*info: 1251 cells of type 'HB4xp67_ASAP7_75t_R' used +*info: 1 cell of type 'BUFx4f_ASAP7_75t_SL' used +*info: 1 cell of type 'BUFx6f_ASAP7_75t_L' used +*info: 2 cells of type 'BUFx24_ASAP7_75t_SL' used +*info: 1 cell of type 'BUFx24_ASAP7_75t_R' used +*info: 2 cells of type 'BUFx24_ASAP7_75t_SRAM' used +*info: +*info: Total 16 instances resized +*info: in which 0 FF resizing +*info: + +*** Starting place_detail (0:14:50 mem=2356.1M) *** +Total net bbox length = 2.668e+05 (1.070e+05 1.598e+05) (ext = 3.742e+04) +Move report: Detail placement moves 0 insts, mean move: 0.00 um, max move: 0.00 um + Runtime: CPU: 0:00:03.0 REAL: 0:00:01.0 MEM: 2356.1MB +Summary Report: +Instances move: 0 (out of 11639 movable) +Instances flipped: 309 +Mean displacement: 0.00 um +Max displacement: 0.00 um +Total net bbox length = 2.670e+05 (1.072e+05 1.598e+05) (ext = 3.742e+04) +Runtime: CPU: 0:00:03.0 REAL: 0:00:01.0 MEM: 2356.1MB +*** Finished place_detail (0:14:53 mem=2356.1M) *** +*** maximum move = 0.00 um *** +*** Finished re-routing un-routed nets (2356.1M) *** + +*** Finish Physical Update (cpu=0:00:03.5 real=0:00:02.0 mem=2356.1M) *** +*** Finish Post CTS Hold Fixing (cpu=0:02:19 real=0:00:46.0 totSessionCpu=0:14:53 mem=2356.1M density=23.220%) *** +**INFO: total 3377 insts, 0 nets marked don't touch +**INFO: total 3377 insts, 0 nets marked don't touch DB property +**INFO: total 3377 insts, 0 nets unmarked don't touch + +*** Steiner Routed Nets: 32.024%; Threshold: 100; Threshold for Hold: 100 +Re-routed 0 nets +GigaOpt_HOLD: Recover setup timing after hold fixing +GigaOpt: WNS changes after routing: 0.000 -> -0.000 (bump = 0.0) +GigaOpt: WNS bump threshold: 0.0005 +GigaOpt: Skipping postEco optimization +GigaOpt: WNS changes after postEco optimization: 0.000 -> -0.000 (bump = 0.0) +GigaOpt: Skipping nonLegal postEco optimization +*** Steiner Routed Nets: 32.024%; Threshold: 100; Threshold for Hold: 100 +Re-routed 0 nets +GigaOpt: WNS changes after postEco optimization: 0.000 -> -0.000 (bump = 0.0, threshold = 0.0005) +GigaOpt: Skipping post-eco TNS optimization + +Active setup views: + PVT_0P63V_100C.setup_view + Dominating endpoints: 0 + Dominating TNS: -0.000 + +[NR-eGR] honorMsvRouteConstraint: false +[NR-eGR] honorClockSpecNDR : 0 +[NR-eGR] minRouteLayer : 2 +[NR-eGR] maxRouteLayer : 7 +[NR-eGR] numTracksPerClockWire : 0 +[NR-eGR] M1 has no routable track +[NR-eGR] M2 has non-uniform track structures +[NR-eGR] M3 has single uniform track structure +[NR-eGR] M4 has single uniform track structure +[NR-eGR] M5 has single uniform track structure +[NR-eGR] M6 has single uniform track structure +[NR-eGR] M7 has single uniform track structure +[NR-eGR] Read 53034 PG shapes in 0.010 seconds + +[NR-eGR] numRoutingBlks=0 numInstBlks=2387 numPGBlocks=53034 numBumpBlks=0 numBoundaryFakeBlks=0 +[NR-eGR] Num Prerouted Nets = 89 Num Prerouted Wires = 9600 +[NR-eGR] Read numTotalNets=12166 numIgnoredNets=89 +[NR-eGR] ============ Routing rule table ============ +[NR-eGR] Rule id: 0 Nets: 12077 +[NR-eGR] Rule id: 1 Nets: 0 +[NR-eGR] ======================================== +[NR-eGR] +[NR-eGR] Layer group 1: route 16 net(s) in layer range [6, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.02% H + 0.03% V. EstWL: 1.944000e+03um +[NR-eGR] +[NR-eGR] Layer group 2: route 43 net(s) in layer range [4, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 2: 0.09% H + 0.08% V. EstWL: 6.982200e+03um +[NR-eGR] +[NR-eGR] Layer group 3: route 12018 net(s) in layer range [2, 7] +[NR-eGR] earlyGlobalRoute overflow of layer group 3: 0.12% H + 0.64% V. EstWL: 2.697797e+05um +[NR-eGR] +[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded) +[NR-eGR] OverCon OverCon OverCon +[NR-eGR] #Gcell #Gcell #Gcell %Gcell +[NR-eGR] Layer (1-2) (3-4) (5-5) OverCon +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] M1 (1) 0( 0.00%) 0( 0.00%) 0( 0.00%) ( 0.00%) +[NR-eGR] M2 (2) 229( 0.26%) 19( 0.02%) 0( 0.00%) ( 0.28%) +[NR-eGR] M3 (3) 1943( 2.17%) 183( 0.20%) 6( 0.01%) ( 2.38%) +[NR-eGR] M4 (4) 616( 0.59%) 24( 0.02%) 0( 0.00%) ( 0.61%) +[NR-eGR] M5 (5) 515( 0.53%) 5( 0.01%) 0( 0.00%) ( 0.53%) +[NR-eGR] M6 (6) 73( 0.07%) 0( 0.00%) 0( 0.00%) ( 0.07%) +[NR-eGR] M7 (7) 53( 0.05%) 0( 0.00%) 0( 0.00%) ( 0.05%) +[NR-eGR] -------------------------------------------------------------------------------- +[NR-eGR] Total 3429( 0.59%) 231( 0.04%) 6( 0.00%) ( 0.64%) +[NR-eGR] +[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.09% H + 0.47% V +[NR-eGR] Overflow after earlyGlobalRoute 0.10% H + 0.57% V +[NR-eGR] End Peak syMemory usage = 2013.5 MB +[NR-eGR] Early Global Router Kernel+IO runtime : 0.48 seconds +[hotspot] +------------+---------------+---------------+ +[hotspot] | | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | normalized | 1.57 | 7.08 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis: normalized max congestion hotspot area = 1.57, normalized total congestion hotspot area = 7.08 (area is in unit of 4 std-cell row bins) +[hotspot] top 5 congestion hotspot bounding boxes and scores of normalized hotspot +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | top | hotspot bbox | hotspot score | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 1 | 250.56 103.68 267.84 120.96 | 1.05 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 2 | 164.16 164.16 181.44 181.44 | 1.05 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 3 | 164.16 138.24 181.44 155.52 | 0.79 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 4 | 138.24 164.16 155.52 181.44 | 0.79 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 5 | 164.16 181.44 181.44 198.72 | 0.79 | +[hotspot] +-----+-------------------------------------+---------------+ +Reported timing to dir hammer_cts_debug +**opt_design ... cpu = 0:05:58, real = 0:02:37, mem = 1491.1M, totSessionCpu=0:14:54 ** +**INFO: Starting Non-Blocking QThread +**INFO: Distributing 4 CPU to Master 2 CPU and QThread 2 CPU +Multi-CPU acceleration using 2 CPU(s). +################################################################################# +# Design Stage: PreRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: No SPEF/RCDB +# Signoff Settings: SI Off +################################################################################# +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Start delay calculation (fullDC) (2 T). (MEM=1928.91) +Total number of fetched objects 12446 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +End delay calculation. (MEM=2086.8 CPU=0:00:04.4 REAL=0:00:03.0) +End delay calculation (fullDC). (MEM=2086.8 CPU=0:00:05.4 REAL=0:00:04.0) +*** Done Building Timing Graph (cpu=0:00:07.5 real=0:00:04.0 totSessionCpu=0:15:02 mem=2086.8M) +2020/12/14 21:56:06 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:06 For more info, please run CheckSysConf in +2020/12/14 21:56:06 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:06 For more info, please run CheckSysConf in +2020/12/14 21:56:06 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:06 For more info, please run CheckSysConf in +2020/12/14 21:56:06 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:06 For more info, please run CheckSysConf in +2020/12/14 21:56:06 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:06 For more info, please run CheckSysConf in +2020/12/14 21:56:06 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:06 For more info, please run CheckSysConf in +2020/12/14 21:56:06 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:06 For more info, please run CheckSysConf in +2020/12/14 21:56:06 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:06 For more info, please run CheckSysConf in + ____________________________________________________________________ +__/ message from Non-Blocking QThread +*** QThread HoldRpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), mem = 0.9M +Multithreaded Timing Analysis is initialized with 2 threads + +################################################################################# +# Design Stage: PreRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: No SPEF/RCDB +# Signoff Settings: SI Off +################################################################################# +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (2 T). (MEM=0) +*** Calculating scaling factor for PVT_0P77V_0C.hold_set libraries using the default operating condition of each library. +Total number of fetched objects 12446 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +End delay calculation. (MEM=0 CPU=0:00:06.1 REAL=0:00:03.0) +End delay calculation (fullDC). (MEM=0 CPU=0:00:07.3 REAL=0:00:04.0) +*** Done Building Timing Graph (cpu=0:00:08.2 real=0:00:05.0 totSessionCpu=0:00:18.2 mem=0.0M) +*** QThread HoldRpt [finish] : cpu/real = 0:00:09.6/0:00:05.0 (1.9), mem = 0.0M +_______________________________________________________________________ + +------------------------------------------------------------ + opt_design Final Summary +------------------------------------------------------------ + +Setup views included: + PVT_0P63V_100C.setup_view +Hold views included: + PVT_0P77V_0C.hold_view + ++--------------------+---------+---------+---------+---------+ +| Setup mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| -0.001 | -0.001 | 0.002 | 0.157 | +| TNS (ns):| -0.001 | -0.001 | 0.000 | 0.000 | +| Violating Paths:| 1 | 1 | 0 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++--------------------+---------+---------+---------+---------+ +| Hold mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| 0.000 | 0.000 | 0.013 | 0.009 | +| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | +| Violating Paths:| 0 | 0 | 0 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 3 (3) | -0.909 | 3 (3) | +| max_tran | 2 (2) | -4.837 | 2 (2) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 23.220% +Routing Overflow: 0.10% H and 0.57% V +------------------------------------------------------------ +**opt_design ... cpu = 0:06:16, real = 0:02:44, mem = 1565.6M, totSessionCpu=0:15:12 ** +*** Finished opt_design *** + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: -0.001 ns -0.001 ns final +[hotspot] +------------+---------------+---------------+ +[hotspot] | | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | normalized | 1.57 | 7.08 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis: normalized max congestion hotspot area = 1.57, normalized total congestion hotspot area = 7.08 (area is in unit of 4 std-cell row bins) +[hotspot] top 5 congestion hotspot bounding boxes and scores of normalized hotspot +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | top | hotspot bbox | hotspot score | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 1 | 250.56 103.68 267.84 120.96 | 1.05 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 2 | 164.16 164.16 181.44 181.44 | 1.05 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 3 | 164.16 138.24 181.44 155.52 | 0.79 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 4 | 138.24 164.16 155.52 181.44 | 0.79 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 5 | 164.16 181.44 181.44 198.72 | 0.79 | +[hotspot] +-----+-------------------------------------+---------------+ + + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: opt_design_postcts +Reset maxLocalDensity to default value from N7/N5 setting. +Info: Destroy the CCOpt slew target map. +Removing temporary dont_use automatically set for cells with technology sites with no row. +Set place::cacheFPlanSiteMark to 0 +(ccopt_design): dumping clock statistics to metric +Leaving CCOpt scope - Initializing power interface... +Leaving CCOpt scope - Initializing power interface done. (took cpu=0:00:00.0 real=0:00:00.0) +Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.early... +Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.early done. (took cpu=0:00:00.2 real=0:00:00.2) +Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late... +Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late done. (took cpu=0:00:00.0 real=0:00:00.0) +Clock tree timing engine global stage delay update for PVT_0P77V_0C.hold_delay:hold.early... +Clock tree timing engine global stage delay update for PVT_0P77V_0C.hold_delay:hold.early done. (took cpu=0:00:00.7 real=0:00:00.7) +Clock tree timing engine global stage delay update for PVT_0P77V_0C.hold_delay:hold.late... +Clock tree timing engine global stage delay update for PVT_0P77V_0C.hold_delay:hold.late done. (took cpu=0:00:00.7 real=0:00:00.7) +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +**WARN: (EMS-27): Message (IMPTS-17) has exceeded the current message display limit of 1. +To increase the message display limit, refer to the product command reference manual. +[hotspot] +------------+---------------+---------------+ +[hotspot] | | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | normalized | 1.57 | 7.08 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis: normalized max congestion hotspot area = 1.57, normalized total congestion hotspot area = 7.08 (area is in unit of 4 std-cell row bins) +[hotspot] top 5 congestion hotspot bounding boxes and scores of normalized hotspot +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | top | hotspot bbox | hotspot score | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 1 | 250.56 103.68 267.84 120.96 | 1.05 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 2 | 164.16 164.16 181.44 181.44 | 1.05 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 3 | 164.16 138.24 181.44 155.52 | 0.79 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 4 | 138.24 164.16 155.52 181.44 | 0.79 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 5 | 164.16 181.44 181.44 198.72 | 0.79 | +[hotspot] +-----+-------------------------------------+---------------+ + + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: 442.02 212 -0.001 ns -0.001 ns ccopt_design + +*** Summary of all messages that are not suppressed in this session: +Severity ID Count Summary +ERROR IMPTS-17 1792 Inconsistency detected in the capacitanc... +WARNING IMPSP-9025 1 No scan chain specified/traced. +WARNING IMPOPT-3564 1 The following cells are set dont_use tem... +WARNING IMPCCOPT-2030 1 Found placement violations. Run check_pl... +WARNING IMPCCOPT-1007 1 Did not meet the max transition constrai... +*** Message Summary: 4 warning(s), 1792 error(s) + +#% End ccopt_design (date=12/14 21:56:10, total cpu=0:07:26, real=0:03:35, peak res=1848.9M, current mem=1584.0M) +@file(par.tcl) 107: puts "write_db pre_add_fillers" +write_db pre_add_fillers +@file(par.tcl) 108: write_db pre_add_fillers +#% Begin write_db save design ... (date=12/14 21:56:10, mem=1584.0M) +% Begin Save ccopt configuration ... (date=12/14 21:56:10, mem=1584.0M) +% End Save ccopt configuration ... (date=12/14 21:56:10, total cpu=0:00:00.1, real=0:00:00.0, peak res=1584.5M, current mem=1584.5M) +% Begin Save netlist data ... (date=12/14 21:56:10, mem=1584.5M) +Writing Binary DB to pre_add_fillers/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 21:56:10, total cpu=0:00:00.0, real=0:00:00.0, peak res=1585.2M, current mem=1585.2M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file pre_add_fillers/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 21:56:10, mem=1585.3M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 21:56:10, total cpu=0:00:00.0, real=0:00:00.0, peak res=1585.3M, current mem=1585.3M) +2020/12/14 21:56:10 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:10 For more info, please run CheckSysConf in +2020/12/14 21:56:10 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:10 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 21:56:10, mem=1585.4M) +% End Save clock tree data ... (date=12/14 21:56:10, total cpu=0:00:00.0, real=0:00:00.0, peak res=1585.4M, current mem=1585.4M) +Saving preference file pre_add_fillers/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 21:56:11 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:11 For more info, please run CheckSysConf in +Saving Drc markers ... +... No Drc file written since there is no markers found. +% Begin Save routing data ... (date=12/14 21:56:11, mem=1599.2M) +Saving route file ... +2020/12/14 21:56:11 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:11 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.1 real=0:00:00.0 mem=2047.4M) *** +% End Save routing data ... (date=12/14 21:56:11, total cpu=0:00:00.1, real=0:00:00.0, peak res=1600.2M, current mem=1600.2M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 21:56:11 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:11 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file pre_add_fillers/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=2063.4M) *** +% Begin Save power constraints data ... (date=12/14 21:56:11, mem=1601.2M) +% End Save power constraints data ... (date=12/14 21:56:11, total cpu=0:00:00.0, real=0:00:00.0, peak res=1601.2M, current mem=1601.2M) +Saving rc congestion map pre_add_fillers/riscv_top.congmap.gz ... +2020/12/14 21:56:11 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:11 For more info, please run CheckSysConf in +Saving preRoute extracted patterns in file 'pre_add_fillers/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.00 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design pre_add_fillers +#% End write_db save design ... (date=12/14 21:56:14, total cpu=0:00:02.1, real=0:00:04.0, peak res=1601.2M, current mem=1510.5M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 109: puts "ln -sfn pre_add_fillers latest" +ln -sfn pre_add_fillers latest +@file(par.tcl) 110: ln -sfn pre_add_fillers latest +@file(par.tcl) 111: set_db add_fillers_cells "FILLER_ASAP7_75t_R FILLER_ASAP7_75t_L FILLER_ASAP7_75t_SL FILLER_ASAP7_75t_SRAM FILLERxp5_ASAP7_75t_R FILLERxp5_ASAP7_75t_L FILLERxp5_ASAP7_75t_SL FILLERxp5_ASAP7_75t_SRAM DECAPx1_ASAP7_75t_R DECAPx1_ASAP7_75t_L DECAPx1_ASAP7_75t_SL DECAPx1_ASAP7_75t_SRAM DECAPx2_ASAP7_75t_R DECAPx2_ASAP7_75t_L DECAPx2_ASAP7_75t_SL DECAPx2_ASAP7_75t_SRAM DECAPx4_ASAP7_75t_R DECAPx4_ASAP7_75t_L DECAPx4_ASAP7_75t_SL DECAPx4_ASAP7_75t_SRAM DECAPx6_ASAP7_75t_R DECAPx6_ASAP7_75t_L DECAPx6_ASAP7_75t_SL DECAPx6_ASAP7_75t_SRAM DECAPx10_ASAP7_75t_R DECAPx10_ASAP7_75t_L DECAPx10_ASAP7_75t_SL DECAPx10_ASAP7_75t_SRAM " +@file(par.tcl) 112: add_fillers +*INFO: Adding fillers to module cpu. +*INFO: Added 11841 filler insts (cell DECAPx10_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx10_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx10_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx10_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Added 1067 filler insts (cell DECAPx6_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx6_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx6_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx6_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Added 658 filler insts (cell DECAPx4_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx4_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx4_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx4_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Added 2646 filler insts (cell DECAPx2_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx2_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx2_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx2_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Added 2776 filler insts (cell DECAPx1_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx1_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx1_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx1_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Added 5017 filler insts (cell FILLER_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell FILLER_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell FILLER_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell FILLER_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Added 6007 filler insts (cell FILLERxp5_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell FILLERxp5_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell FILLERxp5_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell FILLERxp5_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Total 30012 filler insts added - prefix FILLER_AO (CPU: 0:00:03.7). +For 30012 new insts, *** Applied 2 GNC rules (cpu = 0:00:00.0) +*INFO: Filler mode add_fillers_with_drc is default true to avoid gaps, which may add fillers with violations. Please check the violations for FILLER_incr* fillers and fix them before routeDesign. Set it to false can avoid the violation but may leave gaps. +*INFO: Second pass addFiller without DRC checking. +*INFO: Adding fillers to module cpu. +*INFO: Added 0 filler inst (cell DECAPx10_ASAP7_75t_L / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx10_ASAP7_75t_R / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx10_ASAP7_75t_SL / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx10_ASAP7_75t_SRAM / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx6_ASAP7_75t_L / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx6_ASAP7_75t_R / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx6_ASAP7_75t_SL / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx6_ASAP7_75t_SRAM / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx4_ASAP7_75t_L / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx4_ASAP7_75t_R / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx4_ASAP7_75t_SL / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx4_ASAP7_75t_SRAM / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx2_ASAP7_75t_L / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx2_ASAP7_75t_R / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx2_ASAP7_75t_SL / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx2_ASAP7_75t_SRAM / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx1_ASAP7_75t_L / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx1_ASAP7_75t_R / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx1_ASAP7_75t_SL / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell DECAPx1_ASAP7_75t_SRAM / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell FILLER_ASAP7_75t_L / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell FILLER_ASAP7_75t_R / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell FILLER_ASAP7_75t_SL / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell FILLER_ASAP7_75t_SRAM / prefix FILLER_incr_AO). +*INFO: Added 250 filler insts (cell FILLERxp5_ASAP7_75t_L / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell FILLERxp5_ASAP7_75t_R / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell FILLERxp5_ASAP7_75t_SL / prefix FILLER_incr_AO). +*INFO: Added 0 filler inst (cell FILLERxp5_ASAP7_75t_SRAM / prefix FILLER_incr_AO). +*INFO: Total 250 filler insts added - prefix FILLER_incr_AO (CPU: 0:00:00.0). +For 250 new insts, *** Applied 2 GNC rules (cpu = 0:00:00.0) +Pre-route DRC Violation: 250 +@file(par.tcl) 113: puts "write_db pre_route_design" +write_db pre_route_design +@file(par.tcl) 114: write_db pre_route_design +#% Begin write_db save design ... (date=12/14 21:56:18, mem=1544.2M) +% Begin Save ccopt configuration ... (date=12/14 21:56:18, mem=1544.2M) +% End Save ccopt configuration ... (date=12/14 21:56:18, total cpu=0:00:00.1, real=0:00:00.0, peak res=1544.3M, current mem=1544.3M) +% Begin Save netlist data ... (date=12/14 21:56:18, mem=1544.3M) +Writing Binary DB to pre_route_design/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 21:56:18, total cpu=0:00:00.1, real=0:00:00.0, peak res=1547.8M, current mem=1547.8M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file pre_route_design/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 21:56:18, mem=1547.9M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 21:56:18, total cpu=0:00:00.0, real=0:00:00.0, peak res=1547.9M, current mem=1547.9M) +2020/12/14 21:56:18 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:18 For more info, please run CheckSysConf in +2020/12/14 21:56:18 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:18 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 21:56:18, mem=1547.9M) +% End Save clock tree data ... (date=12/14 21:56:18, total cpu=0:00:00.0, real=0:00:00.0, peak res=1547.9M, current mem=1547.9M) +Saving preference file pre_route_design/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 21:56:19 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:19 For more info, please run CheckSysConf in +Saving Drc markers ... +2020/12/14 21:56:19 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:19 For more info, please run CheckSysConf in +... 250 markers are saved ... +... 0 geometry drc markers are saved ... +... 0 antenna drc markers are saved ... +% Begin Save routing data ... (date=12/14 21:56:19, mem=1556.1M) +Saving route file ... +2020/12/14 21:56:19 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:19 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.1 real=0:00:00.0 mem=1991.7M) *** +% End Save routing data ... (date=12/14 21:56:19, total cpu=0:00:00.1, real=0:00:00.0, peak res=1557.1M, current mem=1557.1M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 21:56:19 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:19 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file pre_route_design/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=2007.8M) *** +% Begin Save power constraints data ... (date=12/14 21:56:19, mem=1558.5M) +% End Save power constraints data ... (date=12/14 21:56:19, total cpu=0:00:00.0, real=0:00:00.0, peak res=1558.5M, current mem=1558.5M) +Saving rc congestion map pre_route_design/riscv_top.congmap.gz ... +2020/12/14 21:56:19 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:56:19 For more info, please run CheckSysConf in +Saving preRoute extracted patterns in file 'pre_route_design/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.01 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design pre_route_design +#% End write_db save design ... (date=12/14 21:56:22, total cpu=0:00:02.1, real=0:00:04.0, peak res=1558.5M, current mem=1541.8M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 115: puts "ln -sfn pre_route_design latest" +ln -sfn pre_route_design latest +@file(par.tcl) 116: ln -sfn pre_route_design latest +@file(par.tcl) 117: puts "route_design" +route_design +@file(par.tcl) 118: route_design +#% Begin route_design (date=12/14 21:56:22, mem=1541.8M) +#route_design: cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1541.77 (MB), peak = 1848.90 (MB) +#**INFO: setDesignMode -flowEffort standard +#**INFO: multi-cut via swapping will be performed after routing. +#**INFO: All auto set options tuned by route_design will be restored to their original settings on command completion. + +Begin checking placement ... (start mem=1989.8M, init mem=1989.8M) +Overlapping with other instance: 2 +*info: Placed = 44816 (Fixed = 2915) +*info: Unplaced = 0 +Placement Density:100.00%(98816/98816) +Placement Density (including fixed std cells):100.00%(100133/100133) +PowerDomain Density :98.52%(97357/98816) +Finished check_place (total: cpu=0:00:00.3, real=0:00:00.0; vio checks: cpu=0:00:00.2, real=0:00:00.0; mem=1989.8M) +#WARNING (NRIG-77) Found placement violations. Please investigate and correct before routing. Routing with placement violations can cause long runtime and may be irresolvable. +#Use route_design -placement_check to stop on violations. Use route_design -no_placement_check to skip the check. +**WARN: (IMPCK-8086): The command changeUseClockNetStatus is obsolete and will be removed in the next release. This command still works in this release, but by the next release you must transition to the CCOpt-based CTS flow. + +changeUseClockNetStatus Option : -noFixedNetWires +*** Changed status on (89) nets in Clock. +*** End changeUseClockNetStatus (cpu=0:00:00.0, real=0:00:00.0, mem=1989.8M) *** +#ROUTE-DESIGN-CMD: N5-process: 0 [db_process_node=] +#Start route 89 clock nets... + +route_global_detail + +#set_db route_design_detail_end_iteration 5 +#set_db route_design_bottom_routing_layer 2 +#set_db route_design_concurrent_minimize_via_count_effort "high" +#set_db route_design_reserve_space_for_multi_cut true +#set_db route_design_top_routing_layer 7 +#set_db route_design_with_eco true +#set_db route_design_with_si_driven true +#set_db route_design_with_timing_driven true +#Start route_global_detail on Mon Dec 14 21:56:22 2020 +# +Initializing multi-corner resistance tables ... +#WARNING (NRIG-1303) Congestion map does not match the GCELL grid, clearing map. +#WARNING (NRDB-976) The TRACK STEP 0.3840 for preferred direction tracks is smaller than the PITCH 8.1600 for LAYER Pad. This will cause routability problems for NanoRoute. +#NanoRoute Version 18.10-p002_1 NR180522-1057/18_10-UB +#Using multithreading with 4 threads. +#Start routing data preparation on Mon Dec 14 21:56:23 2020 +# +#Minimum voltage of a net in the design = 0.000. +#Maximum voltage of a net in the design = 0.770. +#Voltage range [0.000 - 0.000] has 1 net. +#Voltage range [0.630 - 0.630] has 1 net. +#Voltage range [0.000 - 0.630] has 12249 nets. +#Voltage range [0.000 - 0.770] has 1130 nets. +# M1 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M2 H Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M3 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M4 H Track-Pitch = 0.19200 Line-2-Via Pitch = 0.19200 +# M5 V Track-Pitch = 0.21600 Line-2-Via Pitch = 0.19200 +# M6 H Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M7 V Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M8 H Track-Pitch = 0.38400 Line-2-Via Pitch = 0.32000 +# M9 V Track-Pitch = 0.36000 Line-2-Via Pitch = 0.32000 +# Pad H Track-Pitch = 0.38400 Line-2-Via Pitch = 8.28000 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +#Regenerating Ggrids automatically. +#Auto generating G-grids with size=15 tracks, using layer M3's pitch = 0.14400. +#Using automatically generated G-grids. +#Done routing data preparation. +#cpu time = 00:00:02, elapsed time = 00:00:01, memory = 1575.92 (MB), peak = 1848.90 (MB) +#Merging special wires using 4 threads... +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 171.55600 148.50000 ) on M1 for NET cpu/stage1/regfile/CTS_59. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 141.10000 130.14000 ) on M1 for NET cpu/stage1/regfile/CTS_59. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 179.44000 197.10000 ) on M1 for NET cpu/stage1/regfile/CTS_47. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 147.79600 186.30000 ) on M1 for NET cpu/stage1/regfile/CTS_47. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 159.67600 140.94000 ) on M1 for NET cpu/stage1/regfile/CTS_6. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 140.23600 242.46000 ) on M1 for NET cpu/stage1/regfile/CTS_61. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 145.96000 192.78000 ) on M1 for NET cpu/stage1/regfile/CTS_61. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 151.36000 143.10000 ) on M1 for NET cpu/stage1/regfile/CTS_61. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 179.54800 190.62000 ) on M1 for NET cpu/stage1/regfile/CTS_63. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 142.18000 129.06000 ) on M1 for NET cpu/stage1/regfile/CTS_45. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 138.40000 188.46000 ) on M1 for NET cpu/stage1/regfile/CTS_43. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 116.90800 191.70000 ) on M1 for NET cpu/stage1/regfile/CTS_41. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 136.67200 179.82000 ) on M1 for NET cpu/stage1/regfile/CTS_41. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 182.78800 201.42000 ) on M1 for NET cpu/stage1/regfile/CTS_51. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 149.63200 189.54000 ) on M1 for NET cpu/stage1/regfile/CTS_51. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 154.60000 200.34000 ) on M1 for NET cpu/stage1/regfile/CTS_26. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 160.86400 146.34000 ) on M1 for NET cpu/stage1/regfile/CTS_26. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 114.42400 184.14000 ) on M1 for NET cpu/stage1/regfile/CTS_28. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 185.81200 223.02000 ) on M1 for NET cpu/stage1/regfile/CTS_4. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 137.53600 218.70000 ) on M1 for NET cpu/stage1/regfile/CTS_4. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (EMS-27) Message (NRDB-1005) has exceeded the current message display limit of 20. +#To increase the message display limit, refer to the product command reference manual. +# +#Connectivity extraction summary: +#35 routed nets are extracted. +# 28 (0.21%) extracted nets are partially routed. +#54 routed net(s) are imported. +#13292 nets are fixed|skipped|trivial (not extracted). +#Total number of nets = 13381. +# +#Start instance access analysis using 4 threads... +#Instance access analysis statistics: +#Cpu time = 00:00:01 +#Elapsed time = 00:00:00 +#Increased memory = 208.58 (MB) +#Total memory = 1785.39 (MB) +#Peak memory = 1848.90 (MB) +# +#Finished routing data preparation on Mon Dec 14 21:56:24 2020 +# +#Cpu time = 00:00:03 +#Elapsed time = 00:00:01 +#Increased memory = 237.43 (MB) +#Total memory = 1785.58 (MB) +#Peak memory = 1848.90 (MB) +# +# +#Start global routing on Mon Dec 14 21:56:24 2020 +# +#Number of eco nets is 28 +# +#Start global routing data preparation on Mon Dec 14 21:56:24 2020 +# +#Start routing resource analysis on Mon Dec 14 21:56:24 2020 +# +#Routing resource analysis is done on Mon Dec 14 21:56:24 2020 +# +# Resource Analysis: +# +# Routing #Avail #Track #Total %Gcell +# Layer Direction Track Blocked Gcell Blocked +# -------------------------------------------------------------- +# M1 V 1801 629 30132 95.69% +# M2 H 1904 682 30132 26.36% +# M3 V 1389 1041 30132 24.53% +# M4 H 1541 498 30132 5.63% +# M5 V 1191 429 30132 5.59% +# M6 H 709 221 30132 11.29% +# M7 V 612 200 30132 10.55% +# M8 H 8 1033 30132 98.92% +# M9 V 13 958 30132 98.15% +# -------------------------------------------------------------- +# Total 9169 43.58% 271188 41.86% +# +# 89 nets (0.67%) with 1 preferred extra spacing. +# +# +# +#Global routing data preparation is done on Mon Dec 14 21:56:24 2020 +# +#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1587.45 (MB), peak = 1848.90 (MB) +# +#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1587.45 (MB), peak = 1848.90 (MB) +# +#start global routing iteration 1... +#Initial_route: 0.00880 +#Reroute: 0.00203 +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1592.29 (MB), peak = 1848.90 (MB) +# +#start global routing iteration 2... +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1592.29 (MB), peak = 1848.90 (MB) +# +# +#Total number of trivial nets (e.g. < 2 pins) = 1215 (skipped). +#Total number of nets with skipped attribute = 12077 (skipped). +#Total number of routable nets = 89. +#Total number of nets in the design = 13381. +# +#28 routable nets have only global wires. +#61 routable nets have only detail routed wires. +#12077 skipped nets have only detail routed wires. +#28 global routed or unrouted (routable) nets have been constrained (e.g. have preferred extra spacing, require shielding etc.) +#61 detail routed (routable) nets have been constrained (e.g. have preferred extra spacing, require shielding etc.) +# +#Routed net constraints summary: +#------------------------------------------------ +# Rules Pref Extra Space Unconstrained +#------------------------------------------------ +# Default 28 0 +#------------------------------------------------ +# Total 28 0 +#------------------------------------------------ +# +#Routing constraints summary of the whole design: +#------------------------------------------------------------------------------- +# Rules Pref Extra Space Pref Layer Expansion Ratio Unconstrained +#------------------------------------------------------------------------------- +# Default 89 59 58 12018 +#------------------------------------------------------------------------------- +# Total 89 59 58 12018 +#------------------------------------------------------------------------------- +# +# +# Congestion Analysis: (blocked Gcells are excluded) +# +# OverCon +# #Gcell %Gcell +# Layer (1) OverCon +# -------------------------------- +# M2 0(0.00%) (0.00%) +# M3 0(0.00%) (0.00%) +# M4 0(0.00%) (0.00%) +# M5 0(0.00%) (0.00%) +# M6 0(0.00%) (0.00%) +# M7 0(0.00%) (0.00%) +# -------------------------------- +# Total 0(0.00%) (0.00%) +# +# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 1 +# Overflow after GR: 0.00% H + 0.00% V +# +#Complete Global Routing. +#Total number of nets with non-default rule or having extra spacing = 89 +#Total wire length = 19896 um. +#Total half perimeter of net bounding box = 9440 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 368 um. +#Total wire length on LAYER M3 = 5912 um. +#Total wire length on LAYER M4 = 9148 um. +#Total wire length on LAYER M5 = 3440 um. +#Total wire length on LAYER M6 = 564 um. +#Total wire length on LAYER M7 = 464 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 5573 +#Up-Via Summary (total 5573): +# +#----------------------- +# M1 1433 +# M2 1519 +# M3 1936 +# M4 531 +# M5 120 +# M6 34 +#----------------------- +# 5573 +# +#Total number of involved priority nets 28 +#Maximum src to sink distance for priority net 170.9 +#Average of max src_to_sink distance for priority net 112.9 +#Average of ave src_to_sink distance for priority net 65.4 +#Max overcon = 0 track. +#Total overcon = 0.00%. +#Worst layer Gcell overcon rate = 0.00%. +# +#Global routing statistics: +#Cpu time = 00:00:01 +#Elapsed time = 00:00:00 +#Increased memory = -192.62 (MB) +#Total memory = 1592.96 (MB) +#Peak memory = 1848.90 (MB) +# +#Finished global routing on Mon Dec 14 21:56:24 2020 +# +# +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1583.39 (MB), peak = 1848.90 (MB) +#Start Track Assignment. +#Done with 11 horizontal wires in 2 hboxes and 5 vertical wires in 2 hboxes. +#Done with 0 horizontal wires in 2 hboxes and 0 vertical wires in 2 hboxes. +#Complete Track Assignment. +#Total number of nets with non-default rule or having extra spacing = 89 +#Total wire length = 19926 um. +#Total half perimeter of net bounding box = 9440 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 368 um. +#Total wire length on LAYER M3 = 5917 um. +#Total wire length on LAYER M4 = 9173 um. +#Total wire length on LAYER M5 = 3440 um. +#Total wire length on LAYER M6 = 565 um. +#Total wire length on LAYER M7 = 464 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 5573 +#Up-Via Summary (total 5573): +# +#----------------------- +# M1 1433 +# M2 1519 +# M3 1936 +# M4 531 +# M5 120 +# M6 34 +#----------------------- +# 5573 +# +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1593.09 (MB), peak = 1848.90 (MB) +# +#Routing data preparation, pin analysis, global routing and track assignment statistics: +#Cpu time = 00:00:04 +#Elapsed time = 00:00:02 +#Increased memory = 45.13 (MB) +#Total memory = 1593.29 (MB) +#Peak memory = 1848.90 (MB) +#Using multithreading with 4 threads. +# +#Start Detail Routing.. +#start initial detail routing ... +# ECO: 15.2% of the total area was rechecked for DRC, and 3.8% required routing. +# number of violations = 2 +# +# By Layer and Type : +# EolKO Totals +# M1 0 0 +# M2 0 0 +# M3 0 0 +# M4 2 2 +# Totals 2 2 +#33905 out of 44816 instances (75.7%) need to be verified(marked ipoed), dirty area = 62.7%. +# number of violations = 2 +# +# By Layer and Type : +# EolKO Totals +# M1 0 0 +# M2 0 0 +# M3 0 0 +# M4 2 2 +# Totals 2 2 +#cpu time = 00:00:15, elapsed time = 00:00:15, memory = 1646.08 (MB), peak = 1848.90 (MB) +#start 1st optimization iteration ... +# number of violations = 0 +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1647.79 (MB), peak = 1848.90 (MB) +#Complete Detail Routing. +#Total number of nets with non-default rule or having extra spacing = 89 +#Total wire length = 19906 um. +#Total half perimeter of net bounding box = 9440 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 388 um. +#Total wire length on LAYER M3 = 6023 um. +#Total wire length on LAYER M4 = 9169 um. +#Total wire length on LAYER M5 = 3335 um. +#Total wire length on LAYER M6 = 529 um. +#Total wire length on LAYER M7 = 462 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 5580 +#Up-Via Summary (total 5580): +# +#----------------------- +# M1 1434 +# M2 1520 +# M3 1958 +# M4 521 +# M5 113 +# M6 34 +#----------------------- +# 5580 +# +#Total number of DRC violations = 0 +#Cpu time = 00:00:15 +#Elapsed time = 00:00:15 +#Increased memory = -3.11 (MB) +#Total memory = 1590.17 (MB) +#Peak memory = 1848.90 (MB) +#route_detail Statistics: +#Cpu time = 00:00:15 +#Elapsed time = 00:00:15 +#Increased memory = -3.11 (MB) +#Total memory = 1590.17 (MB) +#Peak memory = 1848.90 (MB) +# +#route_global_detail statistics: +#Cpu time = 00:00:19 +#Elapsed time = 00:00:17 +#Increased memory = 8.06 (MB) +#Total memory = 1550.93 (MB) +#Peak memory = 1848.90 (MB) +#Number of warnings = 26 +#Total number of warnings = 117 +#Number of fails = 0 +#Total number of fails = 0 +#Complete route_global_detail on Mon Dec 14 21:56:39 2020 +# +#**INFO: auto set of droutePostRouteSwapVia to multiCut + +route_global_detail + +#set_db route_design_detail_post_route_swap_via "multiCut" +#set_db route_design_bottom_routing_layer 2 +#set_db route_design_concurrent_minimize_via_count_effort "high" +#set_db route_design_reserve_space_for_multi_cut true +#set_db route_design_top_routing_layer 7 +#set_db route_design_with_si_driven true +#set_db route_design_with_timing_driven true +#Start route_global_detail on Mon Dec 14 21:56:39 2020 +# +#Generating timing data, please wait... +#12248 total nets, 89 already routed, 89 will ignore in trialRoute +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +#Reporting timing... +Total number of fetched objects 12446 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +End delay calculation. (MEM=2258.73 CPU=0:00:04.1 REAL=0:00:01.0) +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 21:56:43 2020 +# Design: riscv_top +# Command: route_design +############################################################### +#Normalized TNS: 1.00 900.00 -26.00 -0.03 -25.68 -0.03 +#Stage 1: cpu time = 00:00:07, elapsed time = 00:00:03, memory = 1708.89 (MB), peak = 1848.90 (MB) +#Library Standard Delay: 1.00ps +#Slack threshold: 2.00ps +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 21:56:43 2020 +# Design: riscv_top +# Command: route_design +############################################################### +#*** Analyzed 42 timing critical paths +#Stage 2: cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1709.61 (MB), peak = 1848.90 (MB) +#Use bna from skp: 0 +#Stage 3: cpu time = 00:00:02, elapsed time = 00:00:02, memory = 1710.41 (MB), peak = 1848.90 (MB) +#Stage 4: cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1710.84 (MB), peak = 1848.90 (MB) +#Current view: PVT_0P63V_100C.setup_view +**WARN: (EMS-27): Message (IMPTS-17) has exceeded the current message display limit of 1. +To increase the message display limit, refer to the product command reference manual. +riscv_top +**WARN: (IMPEXT-3493): The design extraction status has been reset by set_analysis_view/update_rc_corner or set_db command. The parasitic data can be regenerated either by extracting the design using the extract_rc command or by loading the SPEF or RCDB file(s). To prevent resetting of the extraction status, avoid changing extraction modes. +#Generating timing data took: cpu time = 00:00:12, elapsed time = 00:00:06, memory = 1438.08 (MB), peak = 1848.90 (MB) +#Done generating timing data. +#WARNING (NRIG-1303) Congestion map does not match the GCELL grid, clearing map. +#WARNING (NRDB-976) The TRACK STEP 0.3840 for preferred direction tracks is smaller than the PITCH 8.1600 for LAYER Pad. This will cause routability problems for NanoRoute. +#NanoRoute Version 18.10-p002_1 NR180522-1057/18_10-UB +#Start routing data preparation on Mon Dec 14 21:56:47 2020 +# +#Minimum voltage of a net in the design = 0.000. +#Maximum voltage of a net in the design = 0.770. +#Voltage range [0.000 - 0.000] has 1 net. +#Voltage range [0.630 - 0.630] has 1 net. +#Voltage range [0.000 - 0.630] has 12249 nets. +#Voltage range [0.000 - 0.770] has 1130 nets. +# M1 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M2 H Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M3 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M4 H Track-Pitch = 0.19200 Line-2-Via Pitch = 0.19200 +# M5 V Track-Pitch = 0.21600 Line-2-Via Pitch = 0.19200 +# M6 H Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M7 V Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M8 H Track-Pitch = 0.38400 Line-2-Via Pitch = 0.32000 +# M9 V Track-Pitch = 0.36000 Line-2-Via Pitch = 0.32000 +# Pad H Track-Pitch = 0.38400 Line-2-Via Pitch = 8.28000 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +#Regenerating Ggrids automatically. +#Auto generating G-grids with size=15 tracks, using layer M3's pitch = 0.14400. +#Using automatically generated G-grids. +#Done routing data preparation. +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1482.66 (MB), peak = 1848.90 (MB) +#Start instance access analysis using 4 threads... +#Instance access analysis statistics: +#Cpu time = 00:00:01 +#Elapsed time = 00:00:00 +#Increased memory = 211.75 (MB) +#Total memory = 1694.45 (MB) +#Peak memory = 1848.90 (MB) +# +#Summary of active signal nets routing constraints set by OPT: +# preferred routing layers : 59 +# (M4)43 (M6)16 +# preferred routing layer effort: 0 +# preferred extra space : 0 +# preferred multi-cut via : 0 +# avoid detour : 0 +# expansion ratio : 58 +# net priority : 58 +# s2s control : 0 +# avoid chaining : 0 +# inst-based stacking via : 0 +# +#Summary of active signal nets routing constraints set by USER: +# preferred routing layers : 0 +# preferred routing layer effort : 0 +# preferred extra space : 0 +# preferred multi-cut via : 0 +# avoid detour : 0 +# net weight : 0 +# avoid chaining : 0 +# cell-based stacking via (required) : 0 +# cell-based stacking via (optional) : 0 +# +#Start timing driven prevention iteration +#Setup timing driven global route constraints: +#Honor OPT layer assignment for 60 nets. +#Remove OPT layer assignment for 0 nets. +#Honor USER layer assignment for 0 nets. +#Remove USER layer assignment for 0 nets. +#layer M2: M2_RC = 6.23307e-11 +#layer M3: M3_RC = 6.06854e-11 +#layer M4: M4_RC = 3.79089e-11 +#layer M5: M5_RC = 3.848e-11 +#layer M6: M6_RC = 2.3933e-11 +#layer M7: M7_RC = 2.55064e-11 +#Metal stack 1: M2 - M3 +#Metal stack 2: M4 - M5 +#Metal stack 3: M6 - M7 +#Prevention stack gain threshold: Min=0.2 ps, 1-stack=0.2 ps, 2-stack=0.2 ps +#Start building rc corner(s)... +#Number of RC Corner = 2 +#Corner PVT_0P77V_0C.hold_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 (real) +#Corner PVT_0P63V_100C.setup_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 (real) +#LISD -> M1 (1) +#M1 -> M2 (2) +#M2 -> M3 (3) +#M3 -> M4 (4) +#M4 -> M5 (5) +#M5 -> M6 (6) +#M6 -> M7 (7) +#M7 -> M8 (8) +#M8 -> M9 (9) +#M9 -> Pad (10) +#SADV_On +# Corner(s) : +#PVT_0P77V_0C.hold_rc [ 0.00] +#PVT_0P63V_100C.setup_rc [100.00] +# Corner id: 0 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 0.000000 +# Ref. Temp : 25.000000 +# Corner id: 1 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 100.000000 +# Ref. Temp : 25.000000 +#SADV_Off +# +#layer[1] tech width 288 != ict width 400.0 +# +#layer[1] tech spc 288 != ict spc 464.0 +# +#layer[4] tech width 384 != ict width 288.0 +# +#layer[4] tech spc 384 != ict spc 288.0 +# +#layer[6] tech width 512 != ict width 384.0 +# +#layer[6] tech spc 512 != ict spc 384.0 +# +#layer[8] tech width 640 != ict width 512.0 +# +#layer[8] tech spc 640 != ict spc 512.0 +# +#layer[10] tech spc 32000 != ict spc 640.0 +#total pattern=220 [20, 605] +#Generating the tQuantus model file automatically. +#num_tile=19228 avg_aspect_ratio=1.204440 +#Vertical num_row 51 per_row= 372 halo= 49000 +#hor_num_col = 85 final aspect_ratio= 1.292968 +#Build RC corners: cpu time = 00:00:26, elapsed time = 00:00:33, memory = 1652.56 (MB), peak = 1848.90 (MB) +#27 nets (2058.74 um) assigned to layer M6 and 12 nets (1022.76 um) assigned to layer M4 +#0 inserted nodes are removed +#Honor OPT extra spacing for 0 nets. +#Remove OPT extra spacing for 0 nets. +#Honor USER extra spacing for 0 nets. +#Remove USER extra spacing for 0 nets. +#67 critical nets are selected for extra spacing. +#Honor OPT detour control for 0 nets. +#Remove OPT detour control for 0 nets. +#Honor USER detour control for 0 nets. +#Remove USER detour control for 0 nets. +#134 critical nets are selected for detour control. +# +#-------------------------------------------------------- +# Summary of active signal nets routing constraints +# Avoid Detour : 134 +# Max Expansion Ratio : 58 +# Cell-based Stacking Via : 0 +# Inst-based Stacking Via : 0 +# Prefer Extra Space : 67 +# Prefer Multi-cut Via : 0 +# S2s Control : 0 +# Preferred Layer Effort : 98 +# Bottom Preferred Layer +# Layer M4 : 55 +# Layer M6 : 43 +# +#-------------------------------------------------------- +#Done timing-driven prevention +#cpu time = 00:00:29, elapsed time = 00:00:35, memory = 1571.99 (MB), peak = 1848.90 (MB) +#Using multithreading with 4 threads. +# +#Finished routing data preparation on Mon Dec 14 21:57:23 2020 +# +#Cpu time = 00:00:00 +#Elapsed time = 00:00:00 +#Increased memory = 0.00 (MB) +#Total memory = 1571.99 (MB) +#Peak memory = 1848.90 (MB) +# +# +#Start global routing on Mon Dec 14 21:57:23 2020 +# +#Number of eco nets is 0 +# +#Start global routing data preparation on Mon Dec 14 21:57:23 2020 +# +#Start routing resource analysis on Mon Dec 14 21:57:23 2020 +# +#Routing resource analysis is done on Mon Dec 14 21:57:23 2020 +# +# Resource Analysis: +# +# Routing #Avail #Track #Total %Gcell +# Layer Direction Track Blocked Gcell Blocked +# -------------------------------------------------------------- +# M1 V 1801 629 30132 95.69% +# M2 H 1904 682 30132 26.36% +# M3 V 1389 1041 30132 24.53% +# M4 H 1541 498 30132 5.63% +# M5 V 1191 429 30132 5.59% +# M6 H 707 223 30132 11.29% +# M7 V 610 202 30132 10.58% +# M8 H 8 1033 30132 98.92% +# M9 V 13 958 30132 98.15% +# -------------------------------------------------------------- +# Total 9165 43.63% 271188 41.86% +# +# 156 nets (1.17%) with 1 preferred extra spacing. +# +# +# +#Global routing data preparation is done on Mon Dec 14 21:57:23 2020 +# +#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1572.29 (MB), peak = 1848.90 (MB) +# +#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1572.29 (MB), peak = 1848.90 (MB) +# +#Route nets in 1/3 round... +#start global routing iteration 1... +#Initial_route: 0.19683 +#Reroute: 0.11838 +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1577.53 (MB), peak = 1848.90 (MB) +# +#start global routing iteration 2... +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1577.54 (MB), peak = 1848.90 (MB) +# +#Route nets in 2/3 round... +#start global routing iteration 3... +#Initial_route: 0.16802 +#Reroute: 0.06281 +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1577.53 (MB), peak = 1848.90 (MB) +# +#start global routing iteration 4... +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1577.53 (MB), peak = 1848.90 (MB) +# +#Route nets in 3/3 round... +#start global routing iteration 5... +#Initial_route: 4.47486 +#Reroute: 9.59036 +#cpu time = 00:00:14, elapsed time = 00:00:14, memory = 1605.39 (MB), peak = 1848.90 (MB) +# +#start global routing iteration 6... +#cpu time = 00:00:06, elapsed time = 00:00:06, memory = 1608.75 (MB), peak = 1848.90 (MB) +# +# +#Total number of trivial nets (e.g. < 2 pins) = 1215 (skipped). +#Total number of routable nets = 12166. +#Total number of nets in the design = 13381. +# +#12077 routable nets have only global wires. +#89 routable nets have only detail routed wires. +#197 global routed or unrouted (routable) nets have been constrained (e.g. have preferred extra spacing, require shielding etc.) +#89 detail routed (routable) nets have been constrained (e.g. have preferred extra spacing, require shielding etc.) +# +#Routed nets constraints summary: +#---------------------------------------------------------------------------------------------- +# Rules Pref Extra Space Pref Layer Expansion Ratio Avoid Detour Unconstrained +#---------------------------------------------------------------------------------------------- +# Default 67 86 53 67 11880 +#---------------------------------------------------------------------------------------------- +# Total 67 86 53 67 11880 +#---------------------------------------------------------------------------------------------- +# +#Routing constraints summary of the whole design: +#---------------------------------------------------------------------------------------------- +# Rules Pref Extra Space Pref Layer Expansion Ratio Avoid Detour Unconstrained +#---------------------------------------------------------------------------------------------- +# Default 156 86 53 67 11880 +#---------------------------------------------------------------------------------------------- +# Total 156 86 53 67 11880 +#---------------------------------------------------------------------------------------------- +# +# +# Congestion Analysis: (blocked Gcells are excluded) +# +# OverCon OverCon OverCon OverCon +# #Gcell #Gcell #Gcell #Gcell %Gcell +# Layer (1) (2) (3) (4) OverCon +# -------------------------------------------------------------------------- +# M2 3(0.01%) 0(0.00%) 0(0.00%) 0(0.00%) (0.01%) +# M3 0(0.00%) 0(0.00%) 0(0.00%) 0(0.00%) (0.00%) +# M4 8(0.03%) 0(0.00%) 0(0.00%) 0(0.00%) (0.03%) +# M5 11(0.04%) 2(0.01%) 0(0.00%) 0(0.00%) (0.05%) +# M6 137(0.51%) 83(0.31%) 8(0.03%) 1(0.00%) (0.86%) +# M7 46(0.17%) 59(0.22%) 4(0.01%) 0(0.00%) (0.40%) +# -------------------------------------------------------------------------- +# Total 205(0.13%) 144(0.09%) 12(0.01%) 1(0.00%) (0.23%) +# +# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 4 +# Overflow after GR: 0.15% H + 0.08% V +# +[hotspot] +------------+---------------+---------------+ +[hotspot] | | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | normalized | 0.26 | 0.79 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis: normalized max congestion hotspot area = 0.26, normalized total congestion hotspot area = 0.79 (area is in unit of 4 std-cell row bins) +[hotspot] top 3 congestion hotspot bounding boxes and scores of normalized hotspot +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | top | hotspot bbox | hotspot score | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 1 | 250.56 112.32 267.84 129.60 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 2 | 164.16 138.24 181.44 155.52 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 3 | 164.16 181.44 181.44 198.72 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +#Hotspot report including placement blocked areas +[hotspot] +------------+---------------+---------------+ +[hotspot] | layer | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | M1(V) | 5304.33 | 5304.33 | +[hotspot] | M2(H) | 0.00 | 0.00 | +[hotspot] | M3(V) | 0.00 | 0.00 | +[hotspot] | M4(H) | 0.44 | 0.89 | +[hotspot] | M5(V) | 0.44 | 0.44 | +[hotspot] | M6(H) | 14.22 | 32.00 | +[hotspot] | M7(V) | 4.00 | 13.78 | +[hotspot] | M8(H) | 0.00 | 0.00 | +[hotspot] | M9(V) | 0.00 | 0.00 | +[hotspot] +------------+---------------+---------------+ +[hotspot] | worst | (M1) 5304.33 | (M1) 5304.33 | +[hotspot] +------------+---------------+---------------+ +[hotspot] | all layers | 0.00 | 0.00 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis (3d): normalized congestion max/total hotspot area = 0.00/0.00 (area is in unit of 4 std-cell row bins) +#Complete Global Routing. +#Total number of nets with non-default rule or having extra spacing = 156 +#Total wire length = 306200 um. +#Total half perimeter of net bounding box = 281621 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 63087 um. +#Total wire length on LAYER M3 = 93445 um. +#Total wire length on LAYER M4 = 58115 um. +#Total wire length on LAYER M5 = 62630 um. +#Total wire length on LAYER M6 = 11358 um. +#Total wire length on LAYER M7 = 17565 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 77601 +#Up-Via Summary (total 77601): +# +#----------------------- +# M1 36041 +# M2 27409 +# M3 7626 +# M4 4222 +# M5 1445 +# M6 858 +#----------------------- +# 77601 +# +#Total number of involved regular nets 2697 +#Maximum src to sink distance 509.9 +#Average of max src_to_sink distance 66.6 +#Average of ave src_to_sink distance 50.8 +#Total number of involved priority nets 58 +#Maximum src to sink distance for priority net 340.2 +#Average of max src_to_sink distance for priority net 105.5 +#Average of ave src_to_sink distance for priority net 74.2 +#Max overcon = 4 tracks. +#Total overcon = 0.23%. +#Worst layer Gcell overcon rate = 0.86%. +# +#Global routing statistics: +#Cpu time = 00:00:22 +#Elapsed time = 00:00:22 +#Increased memory = 40.68 (MB) +#Total memory = 1612.67 (MB) +#Peak memory = 1848.90 (MB) +# +#Finished global routing on Mon Dec 14 21:57:44 2020 +# +# +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1576.92 (MB), peak = 1848.90 (MB) +#Start Track Assignment. +#Done with 20487 horizontal wires in 2 hboxes and 19140 vertical wires in 2 hboxes. +#Done with 5119 horizontal wires in 2 hboxes and 2753 vertical wires in 2 hboxes. +#Done with 2 horizontal wires in 2 hboxes and 2 vertical wires in 2 hboxes. +# +#Track assignment summary: +# layer (wire length) (overlap) (long ovlp) (with obs/pg/clk) +#------------------------------------------------------------------------ +# M2 62306.29 0.05% 0.00% 0.01% +# M3 86883.24 0.14% 0.00% 0.05% +# M4 49066.86 0.44% 0.02% 0.40% +# M5 59369.98 0.04% 0.00% 0.02% +# M6 10838.43 0.00% 0.00% 0.00% +# M7 17109.14 0.00% 0.00% 0.00% +#------------------------------------------------------------------------ +# All 285573.95 0.14% 0.00% 0.00% +#Complete Track Assignment. +#Total number of nets with non-default rule or having extra spacing = 156 +#Total wire length = 309108 um. +#Total half perimeter of net bounding box = 281621 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 65267 um. +#Total wire length on LAYER M3 = 93392 um. +#Total wire length on LAYER M4 = 58641 um. +#Total wire length on LAYER M5 = 62882 um. +#Total wire length on LAYER M6 = 11351 um. +#Total wire length on LAYER M7 = 17575 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 77601 +#Up-Via Summary (total 77601): +# +#----------------------- +# M1 36041 +# M2 27409 +# M3 7626 +# M4 4222 +# M5 1445 +# M6 858 +#----------------------- +# 77601 +# +#cpu time = 00:00:04, elapsed time = 00:00:03, memory = 1590.74 (MB), peak = 1848.90 (MB) +# +#number of short segments in preferred routing layers +# M4 M5 M6 M7 Total +# 235 176 196 48 655 +# +#Start post global route fixing for timing critical nets ... +# +#* Updating design timing data... +#Extracting RC... +2020/12/14 21:57:55 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:57:55 For more info, please run CheckSysConf in +2020/12/14 21:57:55 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:57:55 For more info, please run CheckSysConf in +2020/12/14 21:57:55 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 21:57:55 For more info, please run CheckSysConf in +Un-suppress "**WARN ..." messages. +#Reporting timing... +Reading RCDB with compressed RC data. +AAE_INFO: 4 threads acquired from CTE. +Total number of fetched objects 12446 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13381, 93.4 percent of the nets selected for SI analysis +End delay calculation. (MEM=2448.6 CPU=0:00:05.9 REAL=0:00:02.0) +Loading CTE timing window is completed (CPU = 0:00:00.1, REAL = 0:00:00.0, MEM = 2448.6M) +Starting SI iteration 2 +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=2246.79) +Glitch Analysis: View PVT_0P63V_100C.setup_view -- Total Number of Nets Skipped = 0. +Glitch Analysis: View PVT_0P63V_100C.setup_view -- Total Number of Nets Analyzed = 12446. +Total number of fetched objects 12446 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13381, 3.9 percent of the nets selected for SI analysis +End delay calculation. (MEM=2367.41 CPU=0:00:00.3 REAL=0:00:01.0) +End delay calculation (fullDC). (MEM=2367.41 CPU=0:00:00.4 REAL=0:00:01.0) +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 21:58:00 2020 +# Design: riscv_top +# Command: route_design +############################################################### +#Normalized TNS: 1.00 900.00 -2670.00 -2.97 -2670.42 -2.97 +#Stage 1: cpu time = 00:00:11, elapsed time = 00:00:04, memory = 1715.74 (MB), peak = 1848.90 (MB) +#Library Standard Delay: 1.00ps +#Slack threshold: 0.00ps +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 21:58:00 2020 +# Design: riscv_top +# Command: route_design +############################################################### +#*** Analyzed 181 timing critical paths +#Stage 2: cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1716.23 (MB), peak = 1848.90 (MB) +#Use bna from skp: 0 +#Stage 3: cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1716.23 (MB), peak = 1848.90 (MB) +Worst slack reported in the design = 444.976318 (late) + +*** writeDesignTiming (0:00:00.8) *** +#Stage 4: cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1716.45 (MB), peak = 1848.90 (MB) +Un-suppress "**WARN ..." messages. +Current (total cpu=0:17:18, real=0:09:30, peak res=1848.9M, current mem=1566.7M) +riscv_top +Ending "Constraint file reading stats" (total cpu=0:00:00.1, real=0:00:00.0, peak res=1575.2M, current mem=1575.2M) +Current (total cpu=0:17:18, real=0:09:30, peak res=1848.9M, current mem=1575.2M) +#Number of victim nets: 0 +#Number of aggressor nets: 0 +#Number of weak nets: 762 +#Number of critical nets: 710 +# level 1 [ -56.1, -3.7]: 660 nets +# level 2 [ -56.1, -49.7]: 25 nets +# level 3 [ -56.1, -55.3]: 25 nets +#Total number of nets: 12166 +AAE DB initialization (MEM=2105.02 CPU=0:00:00.1 REAL=0:00:00.0) +#Total number of significant detoured timing critical nets is 0 +#Total number of selected detoured timing critical nets is 0 +#14 critical nets are selected for extra spacing. +#Postfix stack gain threshold: Min=0.2 ps, 1-stack=1 ps, 2-stack=2 ps +AAE DB initialization (MEM=2108.39 CPU=0:00:00.1 REAL=0:00:00.0) +#Start building rc corner(s)... +#Number of RC Corner = 2 +#Corner PVT_0P77V_0C.hold_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 (real) +#Corner PVT_0P63V_100C.setup_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 (real) +#LISD -> M1 (1) +#M1 -> M2 (2) +#M2 -> M3 (3) +#M3 -> M4 (4) +#M4 -> M5 (5) +#M5 -> M6 (6) +#M6 -> M7 (7) +#M7 -> M8 (8) +#M8 -> M9 (9) +#M9 -> Pad (10) +#SADV_On +# Corner(s) : +#PVT_0P77V_0C.hold_rc [ 0.00] +#PVT_0P63V_100C.setup_rc [100.00] +# Corner id: 0 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 0.000000 +# Ref. Temp : 25.000000 +# Corner id: 1 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 100.000000 +# Ref. Temp : 25.000000 +#SADV_Off +# +#layer[1] tech width 288 != ict width 400.0 +# +#layer[1] tech spc 288 != ict spc 464.0 +# +#layer[4] tech width 384 != ict width 288.0 +# +#layer[4] tech spc 384 != ict spc 288.0 +# +#layer[6] tech width 512 != ict width 384.0 +# +#layer[6] tech spc 512 != ict spc 384.0 +# +#layer[8] tech width 640 != ict width 512.0 +# +#layer[8] tech spc 640 != ict spc 512.0 +# +#layer[10] tech spc 32000 != ict spc 640.0 +#total pattern=220 [20, 605] +#Reading previously stored rc_model file ( rc_model.bin ) ... +#found CAPMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 +#number model r/c [2,1] [20,605] read +#0 rcmodel(s) requires rebuild +#Build RC corners: cpu time = 00:00:01, elapsed time = 00:00:02, memory = 1629.27 (MB), peak = 1848.90 (MB) +#17 nets (1555.73 um) assigned to layer M6 and 5 nets (304.672 um) assigned to layer M4 +#0 inserted nodes are removed +# +# Congestion Analysis: (blocked Gcells are excluded) +# +# OverCon OverCon OverCon OverCon +# #Gcell #Gcell #Gcell #Gcell %Gcell +# Layer (1) (2) (3) (4) OverCon +# -------------------------------------------------------------------------- +# M2 3(0.01%) 0(0.00%) 0(0.00%) 0(0.00%) (0.01%) +# M3 2(0.01%) 0(0.00%) 0(0.00%) 0(0.00%) (0.01%) +# M4 9(0.03%) 0(0.00%) 0(0.00%) 0(0.00%) (0.03%) +# M5 21(0.07%) 2(0.01%) 0(0.00%) 0(0.00%) (0.08%) +# M6 180(0.67%) 97(0.36%) 8(0.03%) 2(0.01%) (1.07%) +# M7 66(0.24%) 63(0.23%) 4(0.01%) 0(0.00%) (0.49%) +# -------------------------------------------------------------------------- +# Total 281(0.18%) 162(0.10%) 12(0.01%) 2(0.00%) (0.29%) +# +# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 4 +# Overflow after GR: 0.19% H + 0.10% V +# +[hotspot] +------------+---------------+---------------+ +[hotspot] | | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | normalized | 0.26 | 0.79 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis: normalized max congestion hotspot area = 0.26, normalized total congestion hotspot area = 0.79 (area is in unit of 4 std-cell row bins) +[hotspot] top 3 congestion hotspot bounding boxes and scores of normalized hotspot +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | top | hotspot bbox | hotspot score | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 1 | 250.56 112.32 267.84 129.60 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 2 | 164.16 138.24 181.44 155.52 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 3 | 164.16 181.44 181.44 198.72 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +#Hotspot report including placement blocked areas +[hotspot] +------------+---------------+---------------+ +[hotspot] | layer | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | M1(V) | 5304.33 | 5304.33 | +[hotspot] | M2(H) | 0.00 | 0.00 | +[hotspot] | M3(V) | 0.00 | 0.00 | +[hotspot] | M4(H) | 0.44 | 0.44 | +[hotspot] | M5(V) | 0.00 | 0.00 | +[hotspot] | M6(H) | 13.56 | 39.78 | +[hotspot] | M7(V) | 4.00 | 16.44 | +[hotspot] | M8(H) | 0.00 | 0.00 | +[hotspot] | M9(V) | 0.00 | 0.00 | +[hotspot] +------------+---------------+---------------+ +[hotspot] | worst | (M1) 5304.33 | (M1) 5304.33 | +[hotspot] +------------+---------------+---------------+ +[hotspot] | all layers | 0.00 | 0.00 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis (3d): normalized congestion max/total hotspot area = 0.00/0.00 (area is in unit of 4 std-cell row bins) +#Max overcon = 4 tracks. +#Total overcon = 0.29%. +#Worst layer Gcell overcon rate = 1.07%. +#Complete Global Routing. +#Total number of nets with non-default rule or having extra spacing = 170 +#Total wire length = 309615 um. +#Total half perimeter of net bounding box = 281621 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 65281 um. +#Total wire length on LAYER M3 = 92606 um. +#Total wire length on LAYER M4 = 57958 um. +#Total wire length on LAYER M5 = 62920 um. +#Total wire length on LAYER M6 = 12316 um. +#Total wire length on LAYER M7 = 18534 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 78079 +#Up-Via Summary (total 78079): +# +#----------------------- +# M1 36039 +# M2 27429 +# M3 7700 +# M4 4329 +# M5 1581 +# M6 1001 +#----------------------- +# 78079 +# +#Total number of involved regular nets 2703 +#Maximum src to sink distance 511.2 +#Average of max src_to_sink distance 67.5 +#Average of ave src_to_sink distance 51.6 +#Total number of involved priority nets 147 +#Maximum src to sink distance for priority net 339.6 +#Average of max src_to_sink distance for priority net 85.1 +#Average of ave src_to_sink distance for priority net 56.3 +#cpu time = 00:00:07, elapsed time = 00:00:06, memory = 1634.15 (MB), peak = 1848.90 (MB) +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1634.15 (MB), peak = 1848.90 (MB) +#* Importing design timing data... +#Number of victim nets: 0 +#Number of aggressor nets: 0 +#Number of weak nets: 762 +#Number of critical nets: 710 +# level 1 [ -56.1, -3.7]: 660 nets +# level 2 [ -56.1, -49.7]: 25 nets +# level 3 [ -56.1, -55.3]: 25 nets +#Total number of nets: 12166 +# +#timing driven effort level: 3 +#Start Track Assignment With Timing Driven. +#Done with 1030 horizontal wires in 2 hboxes and 1028 vertical wires in 2 hboxes. +#Done with 109 horizontal wires in 2 hboxes and 98 vertical wires in 2 hboxes. +#Done with 2 horizontal wires in 2 hboxes and 2 vertical wires in 2 hboxes. +# +#Track assignment summary: +# layer (wire length) (overlap) (long ovlp) (with obs/pg/clk) +#------------------------------------------------------------------------ +# M2 62003.57 0.03% 0.00% 0.00% +# M3 86391.31 0.14% 0.00% 0.06% +# M4 48469.72 0.49% 0.02% 0.42% +# M5 59495.95 0.06% 0.00% 0.02% +# M6 11792.38 0.06% 0.00% 0.00% +# M7 18051.06 0.00% 0.00% 0.00% +#------------------------------------------------------------------------ +# All 286203.99 0.15% 0.00% 0.00% +#Complete Track Assignment With Timing Driven. +#Total number of nets with non-default rule or having extra spacing = 170 +#Total wire length = 309388 um. +#Total half perimeter of net bounding box = 281621 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 65004 um. +#Total wire length on LAYER M3 = 92676 um. +#Total wire length on LAYER M4 = 57950 um. +#Total wire length on LAYER M5 = 62948 um. +#Total wire length on LAYER M6 = 12301 um. +#Total wire length on LAYER M7 = 18509 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 78079 +#Up-Via Summary (total 78079): +# +#----------------------- +# M1 36039 +# M2 27429 +# M3 7700 +# M4 4329 +# M5 1581 +# M6 1001 +#----------------------- +# 78079 +# +#cpu time = 00:00:02, elapsed time = 00:00:02, memory = 1638.43 (MB), peak = 1848.90 (MB) +# +#Routing data preparation, pin analysis, global routing and track assignment statistics: +#Cpu time = 00:01:31 +#Elapsed time = 00:01:24 +#Increased memory = 136.33 (MB) +#Total memory = 1607.32 (MB) +#Peak memory = 1848.90 (MB) +#Using multithreading with 4 threads. +#Start reading timing information from file .timing_file_22257.tif.gz ... +#Read in timing information for 350 ports, 11731 instances from timing file .timing_file_22257.tif.gz. +# +#Start Detail Routing.. +#start initial detail routing ... +# number of violations = 600 +# +# By Layer and Type : +# MetSpc EOLSpc Loop EolKO WidTbl Rect Others Totals +# M1 0 0 0 4 0 0 0 4 +# M2 15 38 0 1 0 0 2 56 +# M3 18 20 0 1 0 0 79 118 +# M4 11 1 63 130 69 134 5 413 +# M5 0 0 0 0 0 0 0 0 +# M6 3 0 0 0 0 0 0 3 +# M7 6 0 0 0 0 0 0 6 +# Totals 53 59 63 136 69 134 86 600 +#cpu time = 00:02:20, elapsed time = 00:02:20, memory = 1755.00 (MB), peak = 1848.90 (MB) +#start 1st optimization iteration ... +# number of violations = 50 +# +# By Layer and Type : +# MetSpc EOLSpc Short CutSpc EolKO Totals +# M1 0 0 0 0 0 0 +# M2 4 6 6 0 5 21 +# M3 4 4 10 1 0 19 +# M4 0 0 0 0 8 8 +# M5 0 0 0 0 0 0 +# M6 2 0 0 0 0 2 +# Totals 10 10 16 1 13 50 +#cpu time = 00:00:34, elapsed time = 00:00:34, memory = 1756.66 (MB), peak = 1848.90 (MB) +#start 2nd optimization iteration ... +# number of violations = 38 +# +# By Layer and Type : +# MetSpc EOLSpc Short EolKO Mar Totals +# M1 0 0 0 0 0 0 +# M2 9 10 1 1 0 21 +# M3 3 3 7 0 1 14 +# M4 0 0 0 3 0 3 +# Totals 12 13 8 4 1 38 +#cpu time = 00:00:06, elapsed time = 00:00:06, memory = 1757.00 (MB), peak = 1848.90 (MB) +#start 3rd optimization iteration ... +# number of violations = 20 +# +# By Layer and Type : +# MetSpc EOLSpc Short EolKO Totals +# M1 0 0 0 0 0 +# M2 2 1 5 2 10 +# M3 3 2 2 1 8 +# M4 0 0 0 1 1 +# M5 0 0 0 0 0 +# M6 0 0 0 0 0 +# M7 1 0 0 0 1 +# Totals 6 3 7 4 20 +#cpu time = 00:00:04, elapsed time = 00:00:04, memory = 1757.42 (MB), peak = 1848.90 (MB) +#start 4th optimization iteration ... +# number of violations = 10 +# +# By Layer and Type : +# MetSpc EOLSpc Short EolKO Totals +# M1 0 0 0 0 0 +# M2 3 3 2 1 9 +# M3 0 0 0 0 0 +# M4 0 0 0 1 1 +# Totals 3 3 2 2 10 +#cpu time = 00:00:02, elapsed time = 00:00:02, memory = 1758.18 (MB), peak = 1848.90 (MB) +#start 5th optimization iteration ... +# number of violations = 9 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 3 7 +# M3 1 1 0 2 +# Totals 3 3 3 9 +#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1793.12 (MB), peak = 1848.90 (MB) +#start 6th optimization iteration ... +# number of violations = 6 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 2 6 +# Totals 2 2 2 6 +#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1792.91 (MB), peak = 1848.90 (MB) +#start 7th optimization iteration ... +# number of violations = 6 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 2 6 +# Totals 2 2 2 6 +#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1792.91 (MB), peak = 1848.90 (MB) +#start 8th optimization iteration ... +# number of violations = 4 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 1 1 2 4 +# Totals 1 1 2 4 +#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1792.91 (MB), peak = 1848.90 (MB) +#start 9th optimization iteration ... +# number of violations = 7 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 0 0 3 3 +# M3 2 2 0 4 +# Totals 2 2 3 7 +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1792.91 (MB), peak = 1848.90 (MB) +#start 10th optimization iteration ... +# number of violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1792.92 (MB), peak = 1848.90 (MB) +#start 11th optimization iteration ... +# number of violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1792.50 (MB), peak = 1848.90 (MB) +#Complete Detail Routing. +#Total number of nets with non-default rule or having extra spacing = 170 +#Total wire length = 313267 um. +#Total half perimeter of net bounding box = 281621 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 68193 um. +#Total wire length on LAYER M3 = 96305 um. +#Total wire length on LAYER M4 = 54950 um. +#Total wire length on LAYER M5 = 60471 um. +#Total wire length on LAYER M6 = 13752 um. +#Total wire length on LAYER M7 = 19595 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 102850 +#Up-Via Summary (total 102850): +# +#----------------------- +# M1 37015 +# M2 47276 +# M3 10361 +# M4 4912 +# M5 2040 +# M6 1246 +#----------------------- +# 102850 +# +#Total number of DRC violations = 5 +#Total number of violations on LAYER M1 = 0 +#Total number of violations on LAYER M2 = 5 +#Total number of violations on LAYER M3 = 0 +#Total number of violations on LAYER M4 = 0 +#Total number of violations on LAYER M5 = 0 +#Total number of violations on LAYER M6 = 0 +#Total number of violations on LAYER M7 = 0 +#Total number of violations on LAYER M8 = 0 +#Total number of violations on LAYER M9 = 0 +#Total number of violations on LAYER Pad = 0 +#Cpu time = 00:03:12 +#Elapsed time = 00:03:10 +#Increased memory = 9.42 (MB) +#Total memory = 1616.74 (MB) +#Peak memory = 1848.90 (MB) +# +#Start Post Routing Optimization. +#start 1st post routing optimization iteration ... +# number of DRC violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:05, elapsed time = 00:00:04, memory = 1616.20 (MB), peak = 1848.90 (MB) +#start 2nd post routing optimization iteration ... +# number of DRC violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:09, elapsed time = 00:00:08, memory = 1612.25 (MB), peak = 1848.90 (MB) +#Complete Post Routing Optimization. +#Cpu time = 00:00:14 +#Elapsed time = 00:00:12 +#Increased memory = -4.49 (MB) +#Total memory = 1612.25 (MB) +#Peak memory = 1848.90 (MB) +#Total number of nets with non-default rule or having extra spacing = 170 +#Total wire length = 313267 um. +#Total half perimeter of net bounding box = 281621 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 68193 um. +#Total wire length on LAYER M3 = 96305 um. +#Total wire length on LAYER M4 = 54950 um. +#Total wire length on LAYER M5 = 60471 um. +#Total wire length on LAYER M6 = 13752 um. +#Total wire length on LAYER M7 = 19595 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 102850 +#Up-Via Summary (total 102850): +# +#----------------------- +# M1 37015 +# M2 47276 +# M3 10361 +# M4 4912 +# M5 2040 +# M6 1246 +#----------------------- +# 102850 +# +#Total number of DRC violations = 5 +#Total number of violations on LAYER M1 = 0 +#Total number of violations on LAYER M2 = 5 +#Total number of violations on LAYER M3 = 0 +#Total number of violations on LAYER M4 = 0 +#Total number of violations on LAYER M5 = 0 +#Total number of violations on LAYER M6 = 0 +#Total number of violations on LAYER M7 = 0 +#Total number of violations on LAYER M8 = 0 +#Total number of violations on LAYER M9 = 0 +#Total number of violations on LAYER Pad = 0 +# +#Start Post Route via swapping... +#55.01% of area are rerouted by ECO routing. +# number of violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:36, elapsed time = 00:00:36, memory = 1634.50 (MB), peak = 1848.90 (MB) +#CELL_VIEW riscv_top,init has 5 DRC violations +#Total number of DRC violations = 5 +#Total number of violations on LAYER M1 = 0 +#Total number of violations on LAYER M2 = 5 +#Total number of violations on LAYER M3 = 0 +#Total number of violations on LAYER M4 = 0 +#Total number of violations on LAYER M5 = 0 +#Total number of violations on LAYER M6 = 0 +#Total number of violations on LAYER M7 = 0 +#Total number of violations on LAYER M8 = 0 +#Total number of violations on LAYER M9 = 0 +#Total number of violations on LAYER Pad = 0 +#No via is swapped. +#Post Route via swapping is done. +#Total number of nets with non-default rule or having extra spacing = 170 +#Total wire length = 313267 um. +#Total half perimeter of net bounding box = 281621 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 68193 um. +#Total wire length on LAYER M3 = 96305 um. +#Total wire length on LAYER M4 = 54950 um. +#Total wire length on LAYER M5 = 60471 um. +#Total wire length on LAYER M6 = 13752 um. +#Total wire length on LAYER M7 = 19595 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 102850 +#Up-Via Summary (total 102850): +# +#----------------------- +# M1 37015 +# M2 47276 +# M3 10361 +# M4 4912 +# M5 2040 +# M6 1246 +#----------------------- +# 102850 +# +# +#Start Post Route wire spreading.. +# +#Start DRC checking.. +# number of violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:54, elapsed time = 00:00:54, memory = 1720.20 (MB), peak = 1848.90 (MB) +#CELL_VIEW riscv_top,init has 5 DRC violations +#Total number of DRC violations = 5 +#Total number of violations on LAYER M1 = 0 +#Total number of violations on LAYER M2 = 5 +#Total number of violations on LAYER M3 = 0 +#Total number of violations on LAYER M4 = 0 +#Total number of violations on LAYER M5 = 0 +#Total number of violations on LAYER M6 = 0 +#Total number of violations on LAYER M7 = 0 +#Total number of violations on LAYER M8 = 0 +#Total number of violations on LAYER M9 = 0 +#Total number of violations on LAYER Pad = 0 +# +#Start data preparation for wire spreading... +# +#Data preparation is done on Mon Dec 14 22:03:03 2020 +# +# +#Start Post Route Wire Spread. +#Done with 0 horizontal wires in 3 hboxes and 0 vertical wires in 3 hboxes. +#Complete Post Route Wire Spread. +# +#Total number of nets with non-default rule or having extra spacing = 170 +#Total wire length = 313267 um. +#Total half perimeter of net bounding box = 281621 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 68193 um. +#Total wire length on LAYER M3 = 96305 um. +#Total wire length on LAYER M4 = 54950 um. +#Total wire length on LAYER M5 = 60471 um. +#Total wire length on LAYER M6 = 13752 um. +#Total wire length on LAYER M7 = 19595 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 102850 +#Up-Via Summary (total 102850): +# +#----------------------- +# M1 37015 +# M2 47276 +# M3 10361 +# M4 4912 +# M5 2040 +# M6 1246 +#----------------------- +# 102850 +# +# +#Start DRC checking.. +# number of violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:55, elapsed time = 00:00:55, memory = 1713.65 (MB), peak = 1848.90 (MB) +#CELL_VIEW riscv_top,init has 5 DRC violations +#Total number of DRC violations = 5 +#Total number of violations on LAYER M1 = 0 +#Total number of violations on LAYER M2 = 5 +#Total number of violations on LAYER M3 = 0 +#Total number of violations on LAYER M4 = 0 +#Total number of violations on LAYER M5 = 0 +#Total number of violations on LAYER M6 = 0 +#Total number of violations on LAYER M7 = 0 +#Total number of violations on LAYER M8 = 0 +#Total number of violations on LAYER M9 = 0 +#Total number of violations on LAYER Pad = 0 +# number of violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:56, elapsed time = 00:00:56, memory = 1614.00 (MB), peak = 1848.90 (MB) +#CELL_VIEW riscv_top,init has 5 DRC violations +#Total number of DRC violations = 5 +#Total number of violations on LAYER M1 = 0 +#Total number of violations on LAYER M2 = 5 +#Total number of violations on LAYER M3 = 0 +#Total number of violations on LAYER M4 = 0 +#Total number of violations on LAYER M5 = 0 +#Total number of violations on LAYER M6 = 0 +#Total number of violations on LAYER M7 = 0 +#Total number of violations on LAYER M8 = 0 +#Total number of violations on LAYER M9 = 0 +#Total number of violations on LAYER Pad = 0 +#Post Route wire spread is done. +#Total number of nets with non-default rule or having extra spacing = 170 +#Total wire length = 313267 um. +#Total half perimeter of net bounding box = 281621 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 68193 um. +#Total wire length on LAYER M3 = 96305 um. +#Total wire length on LAYER M4 = 54950 um. +#Total wire length on LAYER M5 = 60471 um. +#Total wire length on LAYER M6 = 13752 um. +#Total wire length on LAYER M7 = 19595 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 102850 +#Up-Via Summary (total 102850): +# +#----------------------- +# M1 37015 +# M2 47276 +# M3 10361 +# M4 4912 +# M5 2040 +# M6 1246 +#----------------------- +# 102850 +# +#route_detail Statistics: +#Cpu time = 00:05:53 +#Elapsed time = 00:05:48 +#Increased memory = 4.76 (MB) +#Total memory = 1612.08 (MB) +#Peak memory = 1848.90 (MB) +# +#route_global_detail statistics: +#Cpu time = 00:07:37 +#Elapsed time = 00:07:20 +#Increased memory = 61.03 (MB) +#Total memory = 1562.77 (MB) +#Peak memory = 1848.90 (MB) +#Number of warnings = 5 +#Total number of warnings = 124 +#Number of fails = 0 +#Total number of fails = 0 +#Complete route_global_detail on Mon Dec 14 22:03:59 2020 +# + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: final +[hotspot] +------------+---------------+---------------+ +[hotspot] | | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | normalized | 0.26 | 0.79 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis: normalized max congestion hotspot area = 0.26, normalized total congestion hotspot area = 0.79 (area is in unit of 4 std-cell row bins) +[hotspot] top 3 congestion hotspot bounding boxes and scores of normalized hotspot +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | top | hotspot bbox | hotspot score | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 1 | 250.56 112.32 267.84 129.60 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 2 | 164.16 138.24 181.44 155.52 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 3 | 164.16 181.44 181.44 198.72 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ + + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: 486.93 471 route_design +#route_design: cpu time = 00:07:59, elapsed time = 00:07:39, memory = 1558.22 (MB), peak = 1848.90 (MB) +#% End route_design (date=12/14 22:04:01, total cpu=0:07:59, real=0:07:39, peak res=1770.2M, current mem=1558.2M) +@file(par.tcl) 119: puts "write_db pre_opt_design" +write_db pre_opt_design +@file(par.tcl) 120: write_db pre_opt_design +#% Begin write_db save design ... (date=12/14 22:04:01, mem=1558.2M) +% Begin Save ccopt configuration ... (date=12/14 22:04:01, mem=1558.3M) +% End Save ccopt configuration ... (date=12/14 22:04:01, total cpu=0:00:00.1, real=0:00:00.0, peak res=1559.1M, current mem=1559.1M) +% Begin Save netlist data ... (date=12/14 22:04:01, mem=1559.1M) +Writing Binary DB to pre_opt_design/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 22:04:01, total cpu=0:00:00.1, real=0:00:00.0, peak res=1564.5M, current mem=1564.5M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file pre_opt_design/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 22:04:01, mem=1565.1M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 22:04:01, total cpu=0:00:00.0, real=0:00:00.0, peak res=1565.1M, current mem=1565.1M) +2020/12/14 22:04:01 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:04:01 For more info, please run CheckSysConf in +2020/12/14 22:04:01 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:04:01 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 22:04:01, mem=1565.7M) +% End Save clock tree data ... (date=12/14 22:04:01, total cpu=0:00:00.0, real=0:00:00.0, peak res=1565.7M, current mem=1565.7M) +Saving preference file pre_opt_design/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 22:04:02 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:04:02 For more info, please run CheckSysConf in +Saving Drc markers ... +2020/12/14 22:04:02 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:04:02 For more info, please run CheckSysConf in +... 7 markers are saved ... +... 5 geometry drc markers are saved ... +... 0 antenna drc markers are saved ... +% Begin Save routing data ... (date=12/14 22:04:02, mem=1577.1M) +Saving route file ... +2020/12/14 22:04:02 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:04:02 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.1 real=0:00:00.0 mem=2123.1M) *** +% End Save routing data ... (date=12/14 22:04:02, total cpu=0:00:00.1, real=0:00:00.0, peak res=1578.1M, current mem=1578.1M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 22:04:02 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:04:02 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file pre_opt_design/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=2139.1M) *** +#Saving pin access data to file pre_opt_design/riscv_top.apa ... +# +% Begin Save power constraints data ... (date=12/14 22:04:02, mem=1580.2M) +% End Save power constraints data ... (date=12/14 22:04:02, total cpu=0:00:00.0, real=0:00:00.0, peak res=1580.2M, current mem=1580.2M) +Saving preRoute extracted patterns in file 'pre_opt_design/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.01 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design pre_opt_design +#% End write_db save design ... (date=12/14 22:04:05, total cpu=0:00:02.3, real=0:00:04.0, peak res=1580.2M, current mem=1563.2M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 121: puts "ln -sfn pre_opt_design latest" +ln -sfn pre_opt_design latest +@file(par.tcl) 122: ln -sfn pre_opt_design latest +@file(par.tcl) 123: puts "opt_design -post_route -setup -hold" +opt_design -post_route -setup -hold +@file(par.tcl) 124: opt_design -post_route -setup -hold +**INFO: set_db design_flow_effort standard -> setting 'set_db opt_all_end_points true' for the duration of this command. +Enable merging buffers from different footprints for postRoute code for MSV designs +Enable N7 maxLocalDensity: 0.92 +[GPS-MSV] CPF Flow. Number of Power Domains: 1 +[GPS-MSV] Power Domain 'AO' (tag=1) Default +Switching SI Aware to true by default in postroute mode +GigaOpt running with 4 threads. +**WARN: (IMPOPT-3564): The following cells are set dont_use temporarily by the tool because there are no rows defined for their technology site, or they are not placeable in any power domain. To avoid this message, review the create_floorplan, msv setting, the library setting or set manualy those cells as dont_use. + Cell DECAPx10_ASAP7_75t_L, site coreSite. + Cell DECAPx10_ASAP7_75t_R, site coreSite. + Cell DECAPx10_ASAP7_75t_SL, site coreSite. + Cell DECAPx10_ASAP7_75t_SRAM, site coreSite. + Cell DECAPx1_ASAP7_75t_L, site coreSite. + Cell DECAPx1_ASAP7_75t_R, site coreSite. + Cell DECAPx1_ASAP7_75t_SL, site coreSite. + Cell DECAPx1_ASAP7_75t_SRAM, site coreSite. + Cell DECAPx2_ASAP7_75t_L, site coreSite. + Cell DECAPx2_ASAP7_75t_R, site coreSite. + Cell DECAPx2_ASAP7_75t_SL, site coreSite. + Cell DECAPx2_ASAP7_75t_SRAM, site coreSite. + Cell DECAPx4_ASAP7_75t_L, site coreSite. + Cell DECAPx4_ASAP7_75t_R, site coreSite. + Cell DECAPx4_ASAP7_75t_SL, site coreSite. + Cell DECAPx4_ASAP7_75t_SRAM, site coreSite. + Cell DECAPx6_ASAP7_75t_L, site coreSite. + Cell DECAPx6_ASAP7_75t_R, site coreSite. + Cell DECAPx6_ASAP7_75t_SL, site coreSite. + Cell DECAPx6_ASAP7_75t_SRAM, site coreSite. + ... + Reporting only the 20 first cells found... +. +**opt_design ... cpu = 0:00:00, real = 0:00:00, mem = 1594.7M, totSessionCpu=0:23:29 ** +Existing Dirty Nets : 0 +New Signature Flow (optDesignCheckOptions) .... +#Created 820 library cell signatures +#Created 13381 NETS and 0 SPECIALNETS signatures +#Created 44816 instance signatures +#Build design signature : cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1595.33 (MB), peak = 1848.90 (MB) +#Save design signature : cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1595.39 (MB), peak = 1848.90 (MB) + +Begin checking placement ... (start mem=2101.3M, init mem=2101.3M) +Pre-route DRC Violation: 38 +*info: Placed = 44816 (Fixed = 2915) +*info: Unplaced = 0 +Placement Density:100.00%(98816/98816) +Placement Density (including fixed std cells):100.00%(100133/100133) +PowerDomain Density :98.52%(97357/98816) +Finished check_place (total: cpu=0:00:03.2, real=0:00:03.0; vio checks: cpu=0:00:03.1, real=0:00:03.0; mem=2101.3M) +**WARN: (IMPOPT-306): Found placement violations in the postRoute mode. +**INFO: It is recommended to fix the placement violations and reroute the design +**INFO: Command refinePlace may be used to fix the placement violations + Initial DC engine is -> aae + + AAE-Opt:: Current number of nets in RC Memory -> 100 K + + + AAE-Opt:: New number of nets in RC Memory -> 100 K + +Reset EOS DB +Ignoring AAE DB Resetting ... + Set Options for AAE Based Opt flow +*** opt_design -post_route *** +DRC Margin: user margin 0.0; extra margin 0 +Setup Target Slack: user slack 0 +Hold Target Slack: user slack 0 +** INFO : this run is activating 'postRoute' automaton +Set spgFreeCellsHonorFence to 1 +#WARNING (NRDB-976) The TRACK STEP 0.3840 for preferred direction tracks is smaller than the PITCH 8.1600 for LAYER Pad. This will cause routability problems for NanoRoute. +#Start routing data preparation on Mon Dec 14 22:04:13 2020 +# +#Minimum voltage of a net in the design = 0.000. +#Maximum voltage of a net in the design = 0.770. +#Voltage range [0.000 - 0.000] has 1 net. +#Voltage range [0.630 - 0.630] has 1 net. +#Voltage range [0.000 - 0.630] has 12249 nets. +#Voltage range [0.000 - 0.770] has 1130 nets. +# M1 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M2 H Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M3 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M4 H Track-Pitch = 0.19200 Line-2-Via Pitch = 0.19200 +# M5 V Track-Pitch = 0.21600 Line-2-Via Pitch = 0.19200 +# M6 H Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M7 V Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M8 H Track-Pitch = 0.38400 Line-2-Via Pitch = 0.32000 +# M9 V Track-Pitch = 0.36000 Line-2-Via Pitch = 0.32000 +# Pad H Track-Pitch = 0.38400 Line-2-Via Pitch = 8.28000 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +#Regenerating Ggrids automatically. +#Auto generating G-grids with size=15 tracks, using layer M3's pitch = 0.14400. +#Using automatically generated G-grids. +#Done routing data preparation. +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1587.06 (MB), peak = 1848.90 (MB) +#Extract in post route mode +# +#Start tQuantus RC extraction... +#Start building rc corner(s)... +#Number of RC Corner = 2 +#Corner PVT_0P77V_0C.hold_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 (real) +#Corner PVT_0P63V_100C.setup_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 (real) +#LISD -> M1 (1) +#M1 -> M2 (2) +#M2 -> M3 (3) +#M3 -> M4 (4) +#M4 -> M5 (5) +#M5 -> M6 (6) +#M6 -> M7 (7) +#M7 -> M8 (8) +#M8 -> M9 (9) +#M9 -> Pad (10) +#SADV_On +# Corner(s) : +#PVT_0P77V_0C.hold_rc [ 0.00] +#PVT_0P63V_100C.setup_rc [100.00] +# Corner id: 0 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 0.000000 +# Ref. Temp : 25.000000 +# Corner id: 1 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 100.000000 +# Ref. Temp : 25.000000 +#SADV_Off +# +#layer[1] tech width 288 != ict width 400.0 +# +#layer[1] tech spc 288 != ict spc 464.0 +# +#layer[4] tech width 384 != ict width 288.0 +# +#layer[4] tech spc 384 != ict spc 288.0 +# +#layer[6] tech width 512 != ict width 384.0 +# +#layer[6] tech spc 512 != ict spc 384.0 +# +#layer[8] tech width 640 != ict width 512.0 +# +#layer[8] tech spc 640 != ict spc 512.0 +# +#layer[10] tech spc 32000 != ict spc 640.0 +#total pattern=220 [20, 605] +#Reading previously stored rc_model file ( rc_model.bin ) ... +#found CAPMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 +#number model r/c [2,1] [20,605] read +#0 rcmodel(s) requires rebuild +#Build RC corners: cpu time = 00:00:01, elapsed time = 00:00:02, memory = 1626.65 (MB), peak = 1848.90 (MB) +#Start building rc corner(s)... +#Number of RC Corner = 2 +#Corner PVT_0P77V_0C.hold_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 (real) +#Corner PVT_0P63V_100C.setup_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 (real) +#LISD -> M1 (1) +#M1 -> M2 (2) +#M2 -> M3 (3) +#M3 -> M4 (4) +#M4 -> M5 (5) +#M5 -> M6 (6) +#M6 -> M7 (7) +#M7 -> M8 (8) +#M8 -> M9 (9) +#M9 -> Pad (10) +#SADV_On +# Corner(s) : +#PVT_0P77V_0C.hold_rc [ 0.00] +#PVT_0P63V_100C.setup_rc [100.00] +# Corner id: 0 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 0.000000 +# Ref. Temp : 25.000000 +# Corner id: 1 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 100.000000 +# Ref. Temp : 25.000000 +#SADV_Off +# +#layer[1] tech width 288 != ict width 400.0 +# +#layer[1] tech spc 288 != ict spc 464.0 +# +#layer[4] tech width 384 != ict width 288.0 +# +#layer[4] tech spc 384 != ict spc 288.0 +# +#layer[6] tech width 512 != ict width 384.0 +# +#layer[6] tech spc 512 != ict spc 384.0 +# +#layer[8] tech width 640 != ict width 512.0 +# +#layer[8] tech spc 640 != ict spc 512.0 +# +#layer[10] tech spc 32000 != ict spc 640.0 +#total pattern=220 [20, 605] +#Reading previously stored rc_model file ( rc_model.bin ) ... +#found CAPMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 +#number model r/c [2,1] [20,605] read +#0 rcmodel(s) requires rebuild +#Build RC corners: cpu time = 00:00:01, elapsed time = 00:00:02, memory = 1636.02 (MB), peak = 1848.90 (MB) +#Using multithreading with 4 threads. +#Length limit = 200 pitches +#opt mode = 2 +#Start routing data preparation on Mon Dec 14 22:04:21 2020 +# +#Minimum voltage of a net in the design = 0.000. +#Maximum voltage of a net in the design = 0.770. +#Voltage range [0.000 - 0.630] has 12249 nets. +#Voltage range [0.000 - 0.770] has 1130 nets. +#Voltage range [0.630 - 0.630] has 1 net. +#Voltage range [0.000 - 0.000] has 1 net. +#Regenerating Ggrids automatically. +#Auto generating G-grids with size=15 tracks, using layer M3's pitch = 0.14400. +#Using automatically generated G-grids. +#Done routing data preparation. +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1613.21 (MB), peak = 1848.90 (MB) +#Start routing data preparation on Mon Dec 14 22:04:21 2020 +# +#Minimum voltage of a net in the design = 0.000. +#Maximum voltage of a net in the design = 0.770. +#Voltage range [0.000 - 0.630] has 12249 nets. +#Voltage range [0.000 - 0.770] has 1130 nets. +#Voltage range [0.630 - 0.630] has 1 net. +#Voltage range [0.000 - 0.000] has 1 net. +#Regenerating Ggrids automatically. +#Auto generating G-grids with size=15 tracks, using layer M3's pitch = 0.14400. +#Using automatically generated G-grids. +#Done routing data preparation. +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1613.21 (MB), peak = 1848.90 (MB) +#Start generate extraction boxes. +# +#Extract using 30 x 30 Hboxes +#7x8 initial hboxes +#Use area based hbox pruning. +#0/0 hboxes pruned. +#Complete generating extraction boxes. +#Extract 34 hboxes with 4 threads on machine with Core_i5 3.27GHz 3072KB Cache 4CPU... +#Process 0 special clock nets for rc extraction +#0 temporary NDR added +#Total 12166 nets were built. 2439 nodes added to break long wires. 0 net(s) have incomplete routes. +#Run Statistics for Extraction: +# Cpu time = 00:00:14, elapsed time = 00:00:05 . +# Increased memory = 177.18 (MB), total memory = 1790.40 (MB), peak memory = 1848.90 (MB) +#Simplify RC tree: cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1648.83 (MB), peak = 1848.90 (MB) +#RC Statistics: 68095 Res, 42180 Ground Cap, 2534 XCap (Edge to Edge) +#RC V/H edge ratio: 0.59, Avg V/H Edge Length: 8759.71 (45818), Avg L-Edge Length: 15751.34 (17417) +#Start writing rcdb into /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/nr22257_rwNhTT.rcdb.d +2020/12/14 22:04:26 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:04:26 For more info, please run CheckSysConf in +#Finish writing rcdb with 80292 nodes, 68126 edges, and 5540 xcaps +#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1655.97 (MB), peak = 1848.90 (MB) +Restoring parasitic data from file '/tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/nr22257_rwNhTT.rcdb.d' ... +Reading RCDB with compressed RC data. +Reading RCDB with compressed RC data. +Begin read_parasitics... (cpu: 0:00:00.0 real: 0:00:00.0 mem: 2227.332M) +Following multi-corner parasitics specified: + /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/nr22257_rwNhTT.rcdb.d (rcdb) +Reading RCDB with compressed RC data. + Cell riscv_top has rcdb /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/nr22257_rwNhTT.rcdb.d specified +Cell riscv_top, hinst +Reading RCDB with compressed RC data. +2020/12/14 22:04:26 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:04:26 For more info, please run CheckSysConf in +2020/12/14 22:04:27 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:04:27 For more info, please run CheckSysConf in +Done read_parasitics... (cpu: 0:00:00.2 real: 0:00:01.0 mem: 2203.332M) +# +#Restore RCDB. +# +#Complete tQuantus RC extraction. +#Cpu time = 00:00:22 +#Elapsed time = 00:00:13 +#Increased memory = 62.84 (MB) +#Total memory = 1649.90 (MB) +#Peak memory = 1848.90 (MB) +# +#2439 inserted nodes are removed +Reading RCDB with compressed RC data. +Deleted 0 physical inst (cell FILLER_ASAP7_75t_R / prefix -). +Deleted 5017 physical insts (cell FILLER_ASAP7_75t_L / prefix -). +Deleted 0 physical inst (cell FILLER_ASAP7_75t_SL / prefix -). +Deleted 0 physical inst (cell FILLER_ASAP7_75t_SRAM / prefix -). +Deleted 0 physical inst (cell FILLERxp5_ASAP7_75t_R / prefix -). +Deleted 6257 physical insts (cell FILLERxp5_ASAP7_75t_L / prefix -). +Deleted 0 physical inst (cell FILLERxp5_ASAP7_75t_SL / prefix -). +Deleted 0 physical inst (cell FILLERxp5_ASAP7_75t_SRAM / prefix -). +Deleted 0 physical inst (cell DECAPx1_ASAP7_75t_R / prefix -). +Deleted 2776 physical insts (cell DECAPx1_ASAP7_75t_L / prefix -). +Deleted 0 physical inst (cell DECAPx1_ASAP7_75t_SL / prefix -). +Deleted 0 physical inst (cell DECAPx1_ASAP7_75t_SRAM / prefix -). +Deleted 0 physical inst (cell DECAPx2_ASAP7_75t_R / prefix -). +Deleted 2646 physical insts (cell DECAPx2_ASAP7_75t_L / prefix -). +Deleted 0 physical inst (cell DECAPx2_ASAP7_75t_SL / prefix -). +Deleted 0 physical inst (cell DECAPx2_ASAP7_75t_SRAM / prefix -). +Deleted 0 physical inst (cell DECAPx4_ASAP7_75t_R / prefix -). +Deleted 658 physical insts (cell DECAPx4_ASAP7_75t_L / prefix -). +Deleted 0 physical inst (cell DECAPx4_ASAP7_75t_SL / prefix -). +Deleted 0 physical inst (cell DECAPx4_ASAP7_75t_SRAM / prefix -). +Deleted 0 physical inst (cell DECAPx6_ASAP7_75t_R / prefix -). +Deleted 1067 physical insts (cell DECAPx6_ASAP7_75t_L / prefix -). +Deleted 0 physical inst (cell DECAPx6_ASAP7_75t_SL / prefix -). +Deleted 0 physical inst (cell DECAPx6_ASAP7_75t_SRAM / prefix -). +Deleted 0 physical inst (cell DECAPx10_ASAP7_75t_R / prefix -). +Deleted 11841 physical insts (cell DECAPx10_ASAP7_75t_L / prefix -). +Deleted 0 physical inst (cell DECAPx10_ASAP7_75t_SL / prefix -). +Deleted 0 physical inst (cell DECAPx10_ASAP7_75t_SRAM / prefix -). +Total physical insts deleted = 30262. +**INFO: Starting Blocking QThread with 4 CPU + ____________________________________________________________________ +__/ message from Blocking QThread +Multi-CPU acceleration using 4 CPU(s). +*** QThread HoldInit [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), mem = 0.3M +Multithreaded Timing Analysis is initialized with 4 threads + +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +################################################################################# +# Design Stage: PostRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: SPEF/RCDB +# Signoff Settings: SI Off +################################################################################# +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=0) +*** Calculating scaling factor for PVT_0P77V_0C.hold_set libraries using the default operating condition of each library. +Total number of fetched objects 12446 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +Total number of fetched objects 12446 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +End delay calculation. (MEM=0 CPU=0:00:06.0 REAL=0:00:02.0) +End delay calculation (fullDC). (MEM=0 CPU=0:00:06.6 REAL=0:00:02.0) +*** Done Building Timing Graph (cpu=0:00:07.6 real=0:00:02.0 totSessionCpu=0:00:26.7 mem=0.0M) +Done building cte hold timing graph (HoldAware) cpu=0:00:08.7 real=0:00:03.0 totSessionCpu=0:00:26.7 mem=0.0M *** +*** QThread HoldInit [finish] : cpu/real = 0:00:09.2/0:00:04.0 (2.3), mem = 0.0M +_______________________________________________________________________ +*** QThread HoldInit [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), mem = 0.3M +Multithreaded Timing Analysis is initialized with 4 threads + +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +################################################################################# +# Design Stage: PostRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: SPEF/RCDB +# Signoff Settings: SI Off +################################################################################# +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=0) +*** Calculating scaling factor for PVT_0P77V_0C.hold_set libraries using the default operating condition of each library. +Total number of fetched objects 12446 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +Total number of fetched objects 12446 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +End delay calculation. (MEM=0 CPU=0:00:06.0 REAL=0:00:02.0) +End delay calculation (fullDC). (MEM=0 CPU=0:00:06.6 REAL=0:00:02.0) +*** Done Building Timing Graph (cpu=0:00:07.6 real=0:00:02.0 totSessionCpu=0:00:26.7 mem=0.0M) +Done building cte hold timing graph (HoldAware) cpu=0:00:08.7 real=0:00:03.0 totSessionCpu=0:00:26.7 mem=0.0M *** +*** QThread HoldInit [finish] : cpu/real = 0:00:09.2/0:00:04.0 (2.3), mem = 0.0M + +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +Starting SI iteration 1 using Infinite Timing Windows +Begin IPO call back ... +End IPO call back ... +################################################################################# +# Design Stage: PostRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: SPEF/RCDB +# Signoff Settings: SI On +################################################################################# +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=2176.34) +Total number of fetched objects 12446 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13381, 91.8 percent of the nets selected for SI analysis +Total number of fetched objects 12446 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13381, 91.8 percent of the nets selected for SI analysis +End delay calculation. (MEM=2410.48 CPU=0:00:07.3 REAL=0:00:02.0) +End delay calculation (fullDC). (MEM=2354.78 CPU=0:00:08.2 REAL=0:00:03.0) +Loading CTE timing window with TwFlowType 0...(CPU = 0:00:00.0, REAL = 0:00:00.0, MEM = 2354.8M) +Add other clocks and setupCteToAAEClockMapping during iter 1 +Loading CTE timing window is completed (CPU = 0:00:00.1, REAL = 0:00:00.0, MEM = 2354.8M) + +Executing IPO callback for view pruning .. +Starting SI iteration 2 +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=2169.52) +Glitch Analysis: View PVT_0P63V_100C.setup_view -- Total Number of Nets Skipped = 0. +Glitch Analysis: View PVT_0P63V_100C.setup_view -- Total Number of Nets Analyzed = 0. +Total number of fetched objects 12446 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13381, 4.4 percent of the nets selected for SI analysis +End delay calculation. (MEM=2290.14 CPU=0:00:00.7 REAL=0:00:00.0) +End delay calculation (fullDC). (MEM=2290.14 CPU=0:00:00.7 REAL=0:00:00.0) +*** Done Building Timing Graph (cpu=0:00:12.0 real=0:00:05.0 totSessionCpu=0:24:17 mem=2321.1M) + +------------------------------------------------------------ + Initial SI Timing Summary +------------------------------------------------------------ + +Setup views included: + PVT_0P63V_100C.setup_view + ++--------------------+---------+---------+---------+---------+ +| Setup mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| -0.033 | -0.033 | -0.013 | 0.131 | +| TNS (ns):| -0.424 | -0.411 | -0.013 | 0.000 | +| Violating Paths:| 43 | 42 | 1 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 3 (3) | -0.909 | 3 (3) | +| max_tran | 3 (3) | -4.744 | 3 (3) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 23.220% +Total number of glitch violations: 0 +------------------------------------------------------------ +**opt_design ... cpu = 0:00:49, real = 0:00:28, mem = 1570.3M, totSessionCpu=0:24:17 ** +Setting latch borrow mode to budget during optimization. +Info: Done creating the CCOpt slew target map. +Glitch fixing enabled +Running CCOpt-PRO on entire clock network +Net route status summary: + Clock: 89 (unrouted=0, trialRouted=0, noStatus=0, routed=89, fixed=0, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)]) + Non-clock: 13292 (unrouted=1215, trialRouted=0, noStatus=0, routed=12077, fixed=0, [crossesIlmBoundary=0, tooFewTerms=1215, (crossesIlmBoundary AND tooFewTerms=0)]) +Clock tree cells fixed by user: 0 out of 88 (0%) +PRO... +Relaxing cts_adjacent_rows_legal and cts_cell_density for the duration of PRO. To stop this set pro_respect_cell_density_and_adjacent_row_legal to true. +Initializing clock structures... + Creating own balancer + Permitting the movement of (non-FIXED) datapath insts as required for sized/new clock tree insts + Initializing legalizer + Using cell based legalization. + Removing CTS place status from clock tree and sinks. + Reconstructing clock tree datastructures... + Validating CTS configuration... + Checking module port directions... + Leaving CCOpt scope... + Leaving CCOpt scope done. (took cpu=0:00:00.0 real=0:00:00.0) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Leaving CCOpt scope + Checking module port directions done. (took cpu=0:00:00.0 real=0:00:00.0) + Non-default CCOpt properties: + adjacent_rows_legal: 1 (default: false) + allow_non_fterm_identical_swaps: 0 (default: true) + cannot_merge_reason is set for at least one key + cell_density is set for at least one key + clock_nets_detailed_routed: 1 (default: false) + cts_max_thread_override: 1 (default: auto) + force_design_routing_status: 1 (default: auto) + maximum_insertion_delay is set for at least one key + preferred_extra_space is set for at least one key + primary_delay_corner: PVT_0P63V_100C.setup_delay (default: ) + route_clock_tree_nets_in_length_order: 1 (default: false) + route_type is set for at least one key + target_insertion_delay is set for at least one key + target_skew is set for at least one key + target_skew_wire is set for at least one key + Route type trimming info: + No route type modifications were made. + Library trimming buffers in power domain AO and half-corner PVT_0P63V_100C.setup_delay:setup.late removed 1 of 8 cells + Original list had 8 cells: + BUFx12f_ASAP7_75t_SRAM BUFx10_ASAP7_75t_SRAM BUFx6f_ASAP7_75t_SRAM BUFx5_ASAP7_75t_SRAM BUFx4f_ASAP7_75t_SRAM BUFx3_ASAP7_75t_SRAM BUFx2_ASAP7_75t_SRAM HB1xp67_ASAP7_75t_SRAM + New trimmed list has 7 cells: + BUFx12f_ASAP7_75t_SRAM BUFx10_ASAP7_75t_SRAM BUFx6f_ASAP7_75t_SRAM BUFx5_ASAP7_75t_SRAM BUFx3_ASAP7_75t_SRAM BUFx2_ASAP7_75t_SRAM HB1xp67_ASAP7_75t_SRAM + Library trimming inverters in power domain AO and half-corner PVT_0P63V_100C.setup_delay:setup.late removed 1 of 11 cells + Original list had 11 cells: + INVx13_ASAP7_75t_SRAM INVx11_ASAP7_75t_SRAM INVx8_ASAP7_75t_SRAM INVx6_ASAP7_75t_SRAM INVx5_ASAP7_75t_SRAM INVx4_ASAP7_75t_SRAM INVx3_ASAP7_75t_SRAM INVx2_ASAP7_75t_SRAM INVx1_ASAP7_75t_SRAM INVxp67_ASAP7_75t_SRAM INVxp33_ASAP7_75t_SRAM + New trimmed list has 10 cells: + INVx13_ASAP7_75t_SRAM INVx11_ASAP7_75t_SRAM INVx8_ASAP7_75t_SRAM INVx6_ASAP7_75t_SRAM INVx5_ASAP7_75t_SRAM INVx4_ASAP7_75t_SRAM INVx3_ASAP7_75t_SRAM INVx2_ASAP7_75t_SRAM INVx1_ASAP7_75t_SRAM INVxp33_ASAP7_75t_SRAM + Clock tree balancer configuration for clock_tree clk: + Non-default CCOpt properties: + cell_density: 1 (default: 0.75) + route_type (leaf): default_route_type_leaf (default: default) + route_type (trunk): default_route_type_nonleaf (default: default) + route_type (top): default_route_type_nonleaf (default: default) + For power domain AO: + Buffers: {BUFx12f_ASAP7_75t_SRAM BUFx10_ASAP7_75t_SRAM BUFx6f_ASAP7_75t_SRAM BUFx5_ASAP7_75t_SRAM BUFx3_ASAP7_75t_SRAM BUFx2_ASAP7_75t_SRAM HB1xp67_ASAP7_75t_SRAM} + Inverters: {INVx13_ASAP7_75t_SRAM INVx11_ASAP7_75t_SRAM INVx8_ASAP7_75t_SRAM INVx6_ASAP7_75t_SRAM INVx5_ASAP7_75t_SRAM INVx4_ASAP7_75t_SRAM INVx3_ASAP7_75t_SRAM INVx2_ASAP7_75t_SRAM INVx1_ASAP7_75t_SRAM INVxp33_ASAP7_75t_SRAM} + Clock gates: ICGx3_ASAP7_75t_SL ICGx3_ASAP7_75t_L ICGx2_ASAP7_75t_SL ICGx3_ASAP7_75t_R ICGx2_ASAP7_75t_L ICGx3_ASAP7_75t_SRAM ICGx2_ASAP7_75t_R ICGx2_ASAP7_75t_SRAM ICGx1_ASAP7_75t_SL ICGx1_ASAP7_75t_L ICGx1_ASAP7_75t_R ICGx1_ASAP7_75t_SRAM + Unblocked area available for placement of any clock cells in power_domain AO: 99741.197um^2 + Top Routing info: + Route-type name: default_route_type_nonleaf; Top/bottom preferred layer name: M4/M3; + Unshielded; Mask Constraint: 0; Source: cts_route_type. + Trunk Routing info: + Route-type name: default_route_type_nonleaf; Top/bottom preferred layer name: M4/M3; + Unshielded; Preferred extra space: 1; Mask Constraint: 0; Source: cts_route_type. + Leaf Routing info: + Route-type name: default_route_type_leaf; Top/bottom preferred layer name: M4/M3; + Unshielded; Preferred extra space: 1; Mask Constraint: 0; Source: cts_route_type. + For timing_corner PVT_0P63V_100C.setup_delay:setup, late and power domain AO: + Slew time target (leaf): 69.3ps + Slew time target (trunk): 69.3ps + Slew time target (top): 69.3ps (Note: no nets are considered top nets in this clock tree) + Buffer unit delay: 33.6ps + Buffer max distance: 272.774um + Fastest wire driving cells and distances: + Buffer : {lib_cell:BUFx12f_ASAP7_75t_SRAM, fastest_considered_half_corner=PVT_0P63V_100C.setup_delay:setup.late, optimalDrivingDistance=272.774um, saturatedSlew=52.5ps, speed=4906.007um per ns, cellArea=15.394um^2 per 1000um} + Inverter : {lib_cell:INVx6_ASAP7_75t_SRAM, fastest_considered_half_corner=PVT_0P63V_100C.setup_delay:setup.late, optimalDrivingDistance=150.343um, saturatedSlew=35.2ps, speed=5749.254um per ns, cellArea=12.413um^2 per 1000um} + Clock gate: {lib_cell:ICGx3_ASAP7_75t_SL, fastest_considered_half_corner=PVT_0P63V_100C.setup_delay:setup.late, optimalDrivingDistance=222.857um, saturatedSlew=53.9ps, speed=5758.579um per ns, cellArea=20.935um^2 per 1000um} + + + Logic Sizing Table: + + ---------------------------------------------------------- + Cell Instance count Source Eligible library cells + ---------------------------------------------------------- + (empty table) + ---------------------------------------------------------- + + + Clock tree balancer configuration for skew_group clk/my_constraint_mode: + Sources: pin clk + Total number of sinks: 1305 + Delay constrained sinks: 1301 + Non-leaf sinks: 0 + Ignore pins: 0 + Timing corner PVT_0P63V_100C.setup_delay:setup.late: + Skew target: 33.6ps + Primary reporting skew group is skew_group clk/my_constraint_mode with 1305 clock sinks. + + Via Selection for Estimated Routes (rule default): + + -------------------------------------------------------------- + Layer Via Cell Res. Cap. RC Top of Stack + Range (Ohm) (fF) (fs) Only + -------------------------------------------------------------- + M1-M2 VIA12 10.000 0.002 0.018 false + M2-M3 VIA23 10.000 0.002 0.020 false + M3-M4 VIA34 10.000 0.002 0.025 false + M4-M5 VIA45 10.000 0.003 0.033 false + M5-M6 VIA56 10.000 0.004 0.037 false + M6-M7 VIA67 10.000 0.004 0.040 false + M7-M8 VIA78 10.000 0.003 0.034 false + M8-M9 VIA89 10.000 0.003 0.028 false + M9-Pad VIA9Pad 10.000 0.013 0.133 false + -------------------------------------------------------------- + + No ideal or dont_touch nets found in the clock tree + Validating CTS configuration done. (took cpu=0:00:01.9 real=0:00:01.9) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Validating CTS configuration + CCOpt configuration status: all checks passed. + Reconstructing clock tree datastructures done. +Initializing clock structures done. +PRO... + PRO active optimizations: + - DRV fixing with cell sizing + + Detected clock skew data from CTS + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late... + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late done. (took cpu=0:00:00.1 real=0:00:00.1) + Clock DAG stats PRO initial state: + cell counts : b=45, i=0, icg=43, nicg=0, l=0, total=88 + cell areas : b=146.267um^2, i=0.000um^2, icg=184.524um^2, nicg=0.000um^2, l=0.000um^2, total=330.791um^2 +**WARN: (EMS-27): Message (IMPTS-17) has exceeded the current message display limit of 1. +To increase the message display limit, refer to the product command reference manual. + cell capacitance : b=0.036pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.107pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.054pF, leaf=0.560pF, total=0.614pF + wire lengths : top=0.000um, trunk=1893.552um, leaf=18034.440um, total=19927.992um + Clock DAG net violations PRO initial state: + Remaining Transition : {count=11, worst=[9.0ps, 6.3ps, 4.0ps, 1.9ps, 1.7ps, 1.1ps, 1.0ps, 1.0ps, 0.9ps, 0.8ps, ...]} avg=2.6ps sd=2.7ps sum=28.4ps + Clock DAG primary half-corner transition distribution PRO initial state: + Trunk : target=69.3ps count=42 avg=22.9ps sd=15.6ps min=8.0ps max=65.9ps {35 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 0 <= 65.8ps, 1 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=9.0ps sd=0.1ps min=8.8ps max=9.1ps {0 <= 8.4ps, 1 <= 8.8ps, 3 <= 9.6ps, 0 <= 12.0ps, 0 > 12.0ps} + Leaf : target=69.3ps count=43 avg=60.7ps sd=9.9ps min=25.5ps max=78.3ps {2 <= 41.6ps, 2 <= 55.4ps, 24 <= 62.4ps, 3 <= 65.8ps, 5 <= 69.3ps} {4 <= 72.8ps, 2 <= 76.2ps, 1 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution PRO initial state {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 9 BUFx10_ASAP7_75t_SRAM: 30 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 BUFx2_ASAP7_75t_SRAM: 1 + ICGs: ICGx3_ASAP7_75t_SL: 8 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group PRO initial state: + skew_group default.clk/my_constraint_mode: unconstrained + Skew group summary PRO initial state: + skew_group clk/my_constraint_mode: insertion delay [min=130.2, max=168.4, avg=150.9, sd=8.8], skew [38.2 vs 33.6*], 98.2% {131.8, 165.4} (wid=59.6 ws=45.4) (gid=134.2 gs=32.0) + Clock network insertion delays are now [130.2ps, 168.4ps] average 150.9ps std.dev 8.8ps + Recomputing CTS skew targets... + Resolving skew group constraints... + Solving LP: 1 skew groups; 3 fragments, 3 fraglets and 4 vertices; 25 variables and 66 constraints; tolerance 1 + Resolving skew group constraints done. + Recomputing CTS skew targets done. (took cpu=0:00:00.1 real=0:00:00.1) + Fixing DRVs... + Fixing clock tree DRVs: ...20% .. .40% ...60% ...80% ...100% + CCOpt-PRO: considered: 89, tested: 89, violation detected: 11, violation ignored (due to small violation): 0, cannot run: 0, attempted: 11, unsuccessful: 0, sized: 5 + + PRO Statistics: Fix DRVs (cell sizing): + ======================================= + + Cell changes by Net Type: + + ------------------------------------------------------------------------------------------------------------------------------ + Net Type Attempted Upsized Downsized Swapped Same Size Total Changed Not Sized + ------------------------------------------------------------------------------------------------------------------------------ + top 0 0 0 0 0 (0.0%) 0 (0.0%) + trunk 0 0 0 0 0 (0.0%) 0 (0.0%) + leaf 11 (100.0%) 5 (100.0%) 0 0 5 (100.0%) 6 (100.0%) + ------------------------------------------------------------------------------------------------------------------------------ + Total 11 (100%) 5 (100%) - - 5 (100%) 6 (100%) + ------------------------------------------------------------------------------------------------------------------------------ + + Upsized: 5, Downsized: 0, Sized but same area: 0, Unchanged: 6, Area change: 4.666um^2 (1.410%) + Max. move: 0.000um, Min. move: 0.000um, Avg. move: 0.000um + + Clock DAG stats PRO after DRV fixing: + cell counts : b=45, i=0, icg=43, nicg=0, l=0, total=88 + cell areas : b=150.932um^2, i=0.000um^2, icg=184.524um^2, nicg=0.000um^2, l=0.000um^2, total=335.457um^2 + cell capacitance : b=0.039pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.110pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.054pF, leaf=0.560pF, total=0.614pF + wire lengths : top=0.000um, trunk=1893.552um, leaf=18034.440um, total=19927.992um + Clock DAG net violations PRO after DRV fixing: + Remaining Transition : {count=7, worst=[4.8ps, 4.0ps, 1.9ps, 1.1ps, 1.0ps, 0.9ps, 0.8ps]} avg=2.1ps sd=1.6ps sum=14.5ps + Clock DAG primary half-corner transition distribution PRO after DRV fixing: + Trunk : target=69.3ps count=42 avg=23.6ps sd=15.4ps min=8.0ps max=65.9ps {35 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 0 <= 65.8ps, 1 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=9.0ps sd=0.1ps min=8.8ps max=9.1ps {0 <= 8.4ps, 1 <= 8.8ps, 3 <= 9.6ps, 0 <= 12.0ps, 0 > 12.0ps} + Leaf : target=69.3ps count=43 avg=60.0ps sd=9.2ps min=25.5ps max=74.1ps {2 <= 41.6ps, 2 <= 55.4ps, 24 <= 62.4ps, 5 <= 65.8ps, 7 <= 69.3ps} {1 <= 72.8ps, 2 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution PRO after DRV fixing {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 14 BUFx10_ASAP7_75t_SRAM: 25 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 BUFx2_ASAP7_75t_SRAM: 1 + ICGs: ICGx3_ASAP7_75t_SL: 8 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group PRO after DRV fixing: + skew_group default.clk/my_constraint_mode: unconstrained + Skew group summary PRO after DRV fixing: + skew_group clk/my_constraint_mode: insertion delay [min=130.2, max=169.6, avg=150.9, sd=8.8], skew [39.4 vs 33.7*], 98.2% {132.6, 166.3} (wid=55.2 ws=41.0) (gid=134.2 gs=29.8) + Clock network insertion delays are now [130.2ps, 169.6ps] average 150.9ps std.dev 8.8ps + Fixing DRVs done. (took cpu=0:00:00.1 real=0:00:00.1) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: Fixing DRVs + Reconnecting optimized routes... + Reconnecting optimized routes done. (took cpu=0:00:00.0 real=0:00:00.0) + Set dirty flag on 19 insts, 52 nets + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late... + Clock tree timing engine global stage delay update for PVT_0P63V_100C.setup_delay:setup.late done. (took cpu=0:00:00.1 real=0:00:00.1) + Clock DAG stats PRO final: + cell counts : b=45, i=0, icg=43, nicg=0, l=0, total=88 + cell areas : b=150.932um^2, i=0.000um^2, icg=184.524um^2, nicg=0.000um^2, l=0.000um^2, total=335.457um^2 + cell capacitance : b=0.039pF, i=0.000pF, icg=0.071pF, nicg=0.000pF, l=0.000pF, total=0.110pF + sink capacitance : count=1305, total=0.446pF, avg=0.000pF, sd=0.000pF, min=0.000pF, max=0.004pF + wire capacitance : top=0.000pF, trunk=0.054pF, leaf=0.560pF, total=0.614pF + wire lengths : top=0.000um, trunk=1893.552um, leaf=18034.440um, total=19927.992um + Clock DAG net violations PRO final: + Remaining Transition : {count=7, worst=[4.8ps, 4.0ps, 1.9ps, 1.1ps, 1.0ps, 0.9ps, 0.8ps]} avg=2.1ps sd=1.6ps sum=14.5ps + Clock DAG primary half-corner transition distribution PRO final: + Trunk : target=69.3ps count=42 avg=23.6ps sd=15.4ps min=8.0ps max=65.9ps {35 <= 41.6ps, 4 <= 55.4ps, 2 <= 62.4ps, 0 <= 65.8ps, 1 <= 69.3ps} + Leaf : target=8.0ps count=4 avg=9.0ps sd=0.1ps min=8.8ps max=9.1ps {0 <= 8.4ps, 1 <= 8.8ps, 3 <= 9.6ps, 0 <= 12.0ps, 0 > 12.0ps} + Leaf : target=69.3ps count=43 avg=60.0ps sd=9.2ps min=25.5ps max=74.1ps {2 <= 41.6ps, 2 <= 55.4ps, 24 <= 62.4ps, 5 <= 65.8ps, 7 <= 69.3ps} {1 <= 72.8ps, 2 <= 76.2ps, 0 <= 83.2ps, 0 <= 104.0ps, 0 > 104.0ps} + Clock DAG library cell distribution PRO final {count}: + Bufs: BUFx12f_ASAP7_75t_SRAM: 14 BUFx10_ASAP7_75t_SRAM: 25 BUFx6f_ASAP7_75t_SRAM: 2 BUFx5_ASAP7_75t_SRAM: 1 BUFx3_ASAP7_75t_SRAM: 2 BUFx2_ASAP7_75t_SRAM: 1 + ICGs: ICGx3_ASAP7_75t_SL: 8 ICGx2_ASAP7_75t_SL: 1 ICGx1_ASAP7_75t_SL: 32 ICGx1_ASAP7_75t_SRAM: 2 + Primary reporting skew group PRO final: + skew_group default.clk/my_constraint_mode: unconstrained + Skew group summary PRO final: + skew_group clk/my_constraint_mode: insertion delay [min=130.2, max=169.6, avg=150.9, sd=8.8], skew [39.4 vs 33.7*], 98.2% {132.6, 166.3} (wid=55.2 ws=41.0) (gid=134.2 gs=29.8) + Clock network insertion delays are now [130.2ps, 169.6ps] average 150.9ps std.dev 8.8ps +PRO done. +Restoring CTS place status for unmodified clock tree cells and sinks. +Net route status summary: + Clock: 89 (unrouted=0, trialRouted=0, noStatus=0, routed=89, fixed=0, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)]) + Non-clock: 13292 (unrouted=1215, trialRouted=0, noStatus=0, routed=12077, fixed=0, [crossesIlmBoundary=0, tooFewTerms=1215, (crossesIlmBoundary AND tooFewTerms=0)]) +Updating delays... +Updating delays done. +PRO done. (took cpu=0:00:03.0 real=0:00:02.8) + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: PRO +**INFO: Start fixing DRV (Mem = 2227.34M) ... +Begin: GigaOpt DRV Optimization +Glitch fixing enabled +Info: 84 clock nets excluded from IPO operation. +DRV pessimism of 5.00% is used for tran, 5.00% for cap, 5.00% for fanout, on top of margin 0.00% ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| max-tran | max-cap | max-fanout | max-length | glitch | setup | | | | | | | ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| nets | terms| wViol | nets | terms| wViol | nets | terms| nets | terms| nets | terms| WNS | TNS | #Buf | #Inv | #Resize|Density| Real | Mem | ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 7| 7| -4.79| 3| 3| -0.91| 0| 0| 0| 0| 0| 0| -0.03| -0.42| 0| 0| 0| 23.23| | | +| 6| 6| -0.13| 2| 2| -0.30| 0| 0| 0| 0| 0| 0| -0.03| -0.42| 3| 0| 0| 23.24| 0:00:00.0| 2566.8M| +| 4| 4| -0.00| 0| 0| 0.00| 0| 0| 0| 0| 0| 0| -0.03| -0.42| 0| 0| 2| 23.25| 0:00:00.0| 2566.8M| +| 4| 4| -0.00| 0| 0| 0.00| 0| 0| 0| 0| 0| 0| -0.03| -0.42| 0| 0| 0| 23.25| 0:00:00.0| 2566.8M| ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +**** Begin NDR-Layer Usage Statistics **** +Layer 3 has 89 constrained nets +Layer 4 has 58 constrained nets +Layer 6 has 58 constrained nets +**** End NDR-Layer Usage Statistics **** + + +======================================================================= + Reasons for remaining drv violations +======================================================================= +*info: Total 4 net(s) have violations which can't be fixed by DRV optimization. + +MultiBuffering failure reasons +------------------------------------------------ +*info: 4 net(s): Could not be fixed because it is def in clock net. + + +*** Finish DRV Fixing (cpu=0:00:00.9 real=0:00:01.0 mem=2566.8M) *** + +*** Starting place_detail (0:24:28 mem=2455.9M) *** +Move report: Detail placement moves 9 insts, mean move: 1.73 um, max move: 3.89 um + Max move on inst (cpu/stage1/regfile/g81403): (154.22, 150.12) --> (158.11, 150.12) + Runtime: CPU: 0:00:03.0 REAL: 0:00:02.0 MEM: 2463.9MB +Summary Report: +Instances move: 9 (out of 11647 movable) +Instances flipped: 0 +Mean displacement: 1.73 um +Max displacement: 3.89 um (Instance: cpu/stage1/regfile/g81403) (154.224, 150.12) -> (158.112, 150.12) + Length: 4 sites, height: 1 rows, site name: coreSite, cell type: NAND2xp5_ASAP7_75t_SL +Runtime: CPU: 0:00:03.0 REAL: 0:00:02.0 MEM: 2463.9MB +*** Finished place_detail (0:24:31 mem=2463.9M) *** +Density distribution unevenness ratio = 41.840% +End: GigaOpt DRV Optimization +**opt_design ... cpu = 0:01:03, real = 0:00:38, mem = 1721.6M, totSessionCpu=0:24:31 ** +*info: +**INFO: Completed fixing DRV (CPU Time = 0:00:09, Mem = 2292.92M). + +------------------------------------------------------------ + SI Timing Summary (cpu=0.14min real=0.10min mem=2292.9M) +------------------------------------------------------------ + +Setup views included: + PVT_0P63V_100C.setup_view + ++--------------------+---------+---------+---------+---------+ +| Setup mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| -0.032 | -0.032 | -0.013 | 0.131 | +| TNS (ns):| -0.416 | -0.403 | -0.013 | 0.000 | +| Violating Paths:| 41 | 40 | 1 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 0 (0) | 0.000 | 0 (0) | +| max_tran | 0 (0) | 0.000 | 4 (4) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 23.246% +Total number of glitch violations: 0 +------------------------------------------------------------ +**opt_design ... cpu = 0:01:03, real = 0:00:38, mem = 1721.6M, totSessionCpu=0:24:32 ** +*** Timing NOT met, worst failing slack is -0.032 +*** Check timing (0:00:00.0) +Begin: GigaOpt Optimization in WNS mode +Info: 84 clock nets excluded from IPO operation. +*info: 84 clock nets excluded +*info: 2 special nets excluded. +*info: 1132 no-driver nets excluded. +** GigaOpt Optimizer WNS Slack -0.033 TNS Slack -0.416 Density 23.25 +Active Path Group: reg2cgate reg2reg ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| WNS | All WNS | TNS | All TNS | Density | Real | Mem | Worst View |Pathgroup| End Point | ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| -0.033| -0.033| -0.416| -0.416| 23.25%| 0:00:00.0| 2382.3M|PVT_0P63V_100C.setup_view| reg2reg| cpu/s1_to_s2_rs2/register_reg[24]/D | +| -0.009| -0.009| -0.060| -0.060| 23.28%| 0:00:07.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.009| -0.009| -0.049| -0.049| 23.28%| 0:00:00.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.007| -0.007| -0.041| -0.041| 23.29%| 0:00:01.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.006| -0.006| -0.036| -0.036| 23.29%| 0:00:00.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.008| -0.008| -0.036| -0.036| 23.30%| 0:00:01.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.006| -0.006| -0.033| -0.033| 23.30%| 0:00:00.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.005| -0.005| -0.031| -0.031| 23.30%| 0:00:00.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.004| -0.004| -0.023| -0.023| 23.31%| 0:00:01.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[15]/D | +| -0.004| -0.004| -0.015| -0.015| 23.32%| 0:00:02.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.003| -0.003| -0.010| -0.010| 23.32%| 0:00:00.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.003| -0.003| -0.007| -0.007| 23.33%| 0:00:01.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.002| -0.002| -0.007| -0.007| 23.33%| 0:00:00.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.002| -0.002| -0.006| -0.006| 23.34%| 0:00:01.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.002| -0.002| -0.005| -0.005| 23.34%| 0:00:01.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.002| -0.002| -0.004| -0.004| 23.35%| 0:00:01.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.002| -0.002| -0.004| -0.004| 23.35%| 0:00:00.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.002| -0.002| -0.004| -0.004| 23.35%| 0:00:01.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | +| -0.002| -0.002| -0.002| -0.002| 23.37%| 0:00:02.0| 2631.5M|PVT_0P63V_100C.setup_view| reg2reg| cpu/stage1/pcreg/register_reg[31]/D | ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +skewClock sized 0 and inserted 1 insts ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| WNS | All WNS | TNS | All TNS | Density | Real | Mem | Worst View |Pathgroup| End Point | ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ +| 0.000| 0.002| 0.000| 0.000| 23.38%| 0:00:04.0| 2583.5M|PVT_0P63V_100C.setup_view| NA| NA | ++--------+---------+--------+---------+----------+------------+--------+-------------------------+---------+----------------------------------------------------+ + +*** Finish Core Optimize Step (cpu=0:00:56.6 real=0:00:23.0 mem=2583.5M) *** + +*** Finished Optimize Step Cumulative (cpu=0:00:56.6 real=0:00:23.0 mem=2583.5M) *** +** GigaOpt Optimizer WNS Slack 0.000 TNS Slack 0.000 Density 23.38 +Update Timing Windows (Threshold 0.010) ... +Re Calculate Delays on 1 Nets +**** Begin NDR-Layer Usage Statistics **** +Layer 3 has 90 constrained nets +Layer 4 has 67 constrained nets +Layer 6 has 67 constrained nets +**** End NDR-Layer Usage Statistics **** + +*** Finish Post Route Setup Fixing (cpu=0:00:57.4 real=0:00:24.0 mem=2583.5M) *** +*** Starting place_detail (0:25:37 mem=2473.5M) *** +Move report: Detail placement moves 19 insts, mean move: 0.93 um, max move: 4.10 um + Max move on inst (cpu/stage1/regfile/FE_OCPC1530_n_233): (143.64, 204.12) --> (140.62, 203.04) + Runtime: CPU: 0:00:02.9 REAL: 0:00:01.0 MEM: 2505.5MB +Summary Report: +Instances move: 19 (out of 11696 movable) +Instances flipped: 5 +Mean displacement: 0.93 um +Max displacement: 4.10 um (Instance: cpu/stage1/regfile/FE_OCPC1530_n_233) (143.64, 204.12) -> (140.616, 203.04) + Length: 5 sites, height: 1 rows, site name: coreSite, cell type: BUFx2_ASAP7_75t_SL +Runtime: CPU: 0:00:02.9 REAL: 0:00:01.0 MEM: 2505.5MB +*** Finished place_detail (0:25:40 mem=2505.5M) *** +Density distribution unevenness ratio = 41.858% +End: GigaOpt Optimization in WNS mode +GigaOpt: target slack met, skip TNS optimization +GigaOpt Hold Optimizer is used +Starting initialization (fixHold) cpu=0:00:00.0 real=0:00:00.0 totSessionCpu=0:25:42 mem=2264.4M *** +**INFO: Starting Blocking QThread with 4 CPU + ____________________________________________________________________ +__/ message from Blocking QThread +Multi-CPU acceleration using 4 CPU(s). +*** QThread HoldInit [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), mem = 0.4M +Multithreaded Timing Analysis is initialized with 4 threads + +Latch borrow mode reset to max_borrow +Starting SI iteration 1 using Infinite Timing Windows +Begin IPO call back ... +End IPO call back ... +################################################################################# +# Design Stage: PostRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: SPEF/RCDB +# Signoff Settings: SI On +################################################################################# +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=0) +*** Calculating scaling factor for PVT_0P77V_0C.hold_set libraries using the default operating condition of each library. +Total number of fetched objects 12498 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13433, 91.9 percent of the nets selected for SI analysis +Total number of fetched objects 12498 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13433, 91.9 percent of the nets selected for SI analysis +End delay calculation. (MEM=0 CPU=0:00:09.3 REAL=0:00:03.0) +End delay calculation (fullDC). (MEM=0 CPU=0:00:09.9 REAL=0:00:03.0) +Loading CTE timing window with TwFlowType 0...(CPU = 0:00:00.0, REAL = 0:00:00.0, MEM = 0.0M) +Add other clocks and setupCteToAAEClockMapping during iter 1 +Loading CTE timing window is completed (CPU = 0:00:00.1, REAL = 0:00:00.0, MEM = 0.0M) + +Executing IPO callback for view pruning .. + +Active hold views: + PVT_0P77V_0C.hold_view + Dominating endpoints: 0 + Dominating TNS: -0.000 + +Starting SI iteration 2 +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=0) +Glitch Analysis: View PVT_0P77V_0C.hold_view -- Total Number of Nets Skipped = 0. +Glitch Analysis: View PVT_0P77V_0C.hold_view -- Total Number of Nets Analyzed = 0. +Total number of fetched objects 12498 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13433, 6.5 percent of the nets selected for SI analysis +End delay calculation. (MEM=0 CPU=0:00:00.9 REAL=0:00:00.0) +End delay calculation (fullDC). (MEM=0 CPU=0:00:00.9 REAL=0:00:00.0) +*** Done Building Timing Graph (cpu=0:00:13.4 real=0:00:05.0 totSessionCpu=0:00:40.5 mem=0.0M) +Done building cte hold timing graph (fixHold) cpu=0:00:14.5 real=0:00:05.0 totSessionCpu=0:00:40.5 mem=0.0M *** +Timing Data dump into file /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/coe_eosdata_WIt9bI/PVT_0P77V_0C.hold_view.twf, for view: PVT_0P77V_0C.hold_view + Dumping view 1 PVT_0P77V_0C.hold_view +Done building hold timer [30820 node(s), 39140 edge(s), 1 view(s)] (fixHold) cpu=0:00:16.0 real=0:00:06.0 totSessionCpu=0:00:42.0 mem=0.0M *** +*** QThread HoldInit [finish] : cpu/real = 0:00:16.0/0:00:06.0 (2.7), mem = 0.0M +_______________________________________________________________________ +*** QThread HoldInit [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), mem = 0.4M +Multithreaded Timing Analysis is initialized with 4 threads + +Latch borrow mode reset to max_borrow +Starting SI iteration 1 using Infinite Timing Windows +Begin IPO call back ... +End IPO call back ... +################################################################################# +# Design Stage: PostRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: SPEF/RCDB +# Signoff Settings: SI On +################################################################################# +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=0) +*** Calculating scaling factor for PVT_0P77V_0C.hold_set libraries using the default operating condition of each library. +Total number of fetched objects 12498 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13433, 91.9 percent of the nets selected for SI analysis +Total number of fetched objects 12498 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13433, 91.9 percent of the nets selected for SI analysis +End delay calculation. (MEM=0 CPU=0:00:09.3 REAL=0:00:03.0) +End delay calculation (fullDC). (MEM=0 CPU=0:00:09.9 REAL=0:00:03.0) +Loading CTE timing window with TwFlowType 0...(CPU = 0:00:00.0, REAL = 0:00:00.0, MEM = 0.0M) +Add other clocks and setupCteToAAEClockMapping during iter 1 +Loading CTE timing window is completed (CPU = 0:00:00.1, REAL = 0:00:00.0, MEM = 0.0M) + +Executing IPO callback for view pruning .. + +Active hold views: + PVT_0P77V_0C.hold_view + Dominating endpoints: 0 + Dominating TNS: -0.000 + +Starting SI iteration 2 +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=0) +Glitch Analysis: View PVT_0P77V_0C.hold_view -- Total Number of Nets Skipped = 0. +Glitch Analysis: View PVT_0P77V_0C.hold_view -- Total Number of Nets Analyzed = 0. +Total number of fetched objects 12498 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13433, 6.5 percent of the nets selected for SI analysis +End delay calculation. (MEM=0 CPU=0:00:00.9 REAL=0:00:00.0) +End delay calculation (fullDC). (MEM=0 CPU=0:00:00.9 REAL=0:00:00.0) +*** Done Building Timing Graph (cpu=0:00:13.4 real=0:00:05.0 totSessionCpu=0:00:40.5 mem=0.0M) +Done building cte hold timing graph (fixHold) cpu=0:00:14.5 real=0:00:05.0 totSessionCpu=0:00:40.5 mem=0.0M *** +Timing Data dump into file /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/coe_eosdata_WIt9bI/PVT_0P77V_0C.hold_view.twf, for view: PVT_0P77V_0C.hold_view + Dumping view 1 PVT_0P77V_0C.hold_view +Done building hold timer [30820 node(s), 39140 edge(s), 1 view(s)] (fixHold) cpu=0:00:16.0 real=0:00:06.0 totSessionCpu=0:00:42.0 mem=0.0M *** +*** QThread HoldInit [finish] : cpu/real = 0:00:16.0/0:00:06.0 (2.7), mem = 0.0M + +Done building cte setup timing graph (fixHold) cpu=0:00:16.7 real=0:00:08.0 totSessionCpu=0:25:58 mem=2264.4M *** +Restoring Auto Hold Views: PVT_0P77V_0C.hold_view +Restoring Active Hold Views: PVT_0P77V_0C.hold_view +Restoring Hold Target Slack: 0 +Loading timing data from /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/coe_eosdata_WIt9bI/PVT_0P77V_0C.hold_view.twf + Loading view 1 PVT_0P77V_0C.hold_view + +*Info: minBufDelay = 7.5 ps, libStdDelay = 1.0 ps, minBufSize = 14929920 (4.0) +*Info: worst delay setup view: PVT_0P63V_100C.setup_view + +------------------------------------------------------------ + Initial Summary +------------------------------------------------------------ + +Setup views included: + PVT_0P63V_100C.setup_view +Hold views included: + PVT_0P77V_0C.hold_view + ++--------------------+---------+---------+---------+---------+ +| Setup mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| 0.002 | 0.002 | 0.004 | 0.129 | +| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | +| Violating Paths:| 0 | 0 | 0 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++--------------------+---------+---------+---------+---------+ +| Hold mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| -0.019 | -0.019 | 0.013 | 0.012 | +| TNS (ns):| -0.258 | -0.258 | 0.000 | 0.000 | +| Violating Paths:| 58 | 58 | 0 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 0 (0) | 0.000 | 0 (0) | +| max_tran | 0 (0) | 0.000 | 4 (4) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 23.383% +Total number of glitch violations: 0 +------------------------------------------------------------ +**opt_design ... cpu = 0:02:32, real = 0:01:23, mem = 1751.2M, totSessionCpu=0:26:01 ** +*info: Run opt_design holdfix with 4 threads. +Info: 85 clock nets excluded from IPO operation. +Info: Do not create the CCOpt slew target map as it already exists. + +*** Starting Core Fixing (fixHold) cpu=0:00:19.7 real=0:00:11.0 totSessionCpu=0:26:01 mem=2372.6M density=23.383% *** + +Phase I ...... +Executing transform: ECO Safe Resize ++----+--------+---------+--------+-----------+----------------+----------+------------+---------+ +|Iter| WNS | TNS | #VP | #Buffer | #Resize(F/F) | Density | Real | Mem | ++----+--------+---------+--------+-----------+----------------+----------+------------+---------+ +| 0| -0.019| -0.26| 58| 0| 0( 0)| 23.38%| 0:00:00.0| 2444.0M| +| 1| -0.019| -0.23| 41| 0| 44( 44)| 23.38%| 0:00:01.0| 2558.5M| +| 2| -0.019| -0.23| 41| 0| 0( 0)| 23.38%| 0:00:00.0| 2558.5M| ++----+--------+---------+--------+-----------+----------------+----------+------------+---------+ +Executing transform: AddBuffer + LegalResize ++----+--------+---------+--------+-----------+----------------+----------+------------+---------+ +|Iter| WNS | TNS | #VP | #Buffer | #Resize(F/F) | Density | Real | Mem | ++----+--------+---------+--------+-----------+----------------+----------+------------+---------+ +| 0| -0.019| -0.23| 41| 0| 0( 0)| 23.38%| 0:00:00.0| 2558.5M| +| 1| -0.010| -0.05| 9| 24| 1( 1)| 23.41%| 0:00:01.0| 2596.6M| +| 2| -0.006| -0.01| 3| 7| 2( 0)| 23.42%| 0:00:00.0| 2596.6M| +| 3| 0.000| 0.00| 0| 3| 0( 0)| 23.43%| 0:00:00.0| 2596.6M| ++----+--------+---------+--------+-----------+----------------+----------+------------+---------+ + +*info: Total 34 cells added for Phase I +*info: Total 47 instances resized for Phase I + +*** Finished Core Fixing (fixHold) cpu=0:00:26.4 real=0:00:14.0 totSessionCpu=0:26:08 mem=2627.2M density=23.427% *** + +*info: +*info: Added a total of 34 cells to fix/reduce hold violation +*info: +*info: Summary: +*info: 10 cells of type 'HB1xp67_ASAP7_75t_SL' used +*info: 3 cells of type 'HB1xp67_ASAP7_75t_L' used +*info: 4 cells of type 'HB1xp67_ASAP7_75t_SRAM' used +*info: 11 cells of type 'BUFx2_ASAP7_75t_SL' used +*info: 1 cell of type 'HB2xp67_ASAP7_75t_SL' used +*info: 1 cell of type 'HB2xp67_ASAP7_75t_SRAM' used +*info: 2 cells of type 'HB3xp67_ASAP7_75t_SL' used +*info: 1 cell of type 'BUFx4f_ASAP7_75t_SL' used +*info: 1 cell of type 'BUFx24_ASAP7_75t_SRAM' used +*info: +*info: Total 47 instances resized +*info: in which 45 FF resizing +*info: + +*** Finish Post Route Hold Fixing (cpu=0:00:26.4 real=0:00:14.0 totSessionCpu=0:26:08 mem=2627.2M density=23.427%) *** +**INFO: total 823 insts, 0 nets marked don't touch +**INFO: total 823 insts, 0 nets marked don't touch DB property +**INFO: total 823 insts, 0 nets unmarked don't touch + +*** Starting place_detail (0:26:08 mem=2516.2M) *** +Move report: Detail placement moves 0 insts, mean move: 0.00 um, max move: 0.00 um + Runtime: CPU: 0:00:02.9 REAL: 0:00:01.0 MEM: 2524.2MB +Summary Report: +Instances move: 0 (out of 11730 movable) +Instances flipped: 3 +Mean displacement: 0.00 um +Max displacement: 0.00 um +Runtime: CPU: 0:00:02.9 REAL: 0:00:01.0 MEM: 2524.2MB +*** Finished place_detail (0:26:11 mem=2524.2M) *** +Density distribution unevenness ratio = 41.862% +[hotspot] +------------+---------------+---------------+ +[hotspot] | | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | normalized | 0.26 | 0.79 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis: normalized max congestion hotspot area = 0.26, normalized total congestion hotspot area = 0.79 (area is in unit of 4 std-cell row bins) +[hotspot] top 3 congestion hotspot bounding boxes and scores of normalized hotspot +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | top | hotspot bbox | hotspot score | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 1 | 250.56 112.32 267.84 129.60 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 2 | 164.16 138.24 181.44 155.52 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 3 | 164.16 181.44 181.44 198.72 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ + + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: 0.000 ps 1.887 ps postroute.hold +Running postRoute recovery in preEcoRoute mode +**opt_design ... cpu = 0:02:44, real = 0:01:28, mem = 1744.5M, totSessionCpu=0:26:12 ** +Checking DRV degradation... +**INFO: Skipping DRV recovery as drv did not degrade beyond margin +*** Finish postRoute recovery in preEcoRoute mode (cpu=0:00:01, real=0:00:01, mem=2262.35M, totSessionCpu=0:26:14). +**opt_design ... cpu = 0:02:45, real = 0:01:29, mem = 1748.7M, totSessionCpu=0:26:14 ** + +Default Rule : "" +Non Default Rules : +Worst Slack : 0.002 ns +Total 0 nets layer assigned (0.2). +GigaOpt: setting up router preferences +GigaOpt: 127 nets assigned router directives + +Start Assign Priority Nets ... +TargetSlk(0.200ns) MaxAssign(3%) minLen(50um) +Existing Priority Nets 0 (0.0%) +Total Assign Priority Nets 401 (3.0%) +Default Rule : "" +Non Default Rules : +Worst Slack : 0.002 ns +Total 0 nets layer assigned (0.3). +GigaOpt: setting up router preferences +GigaOpt: 0 nets assigned router directives + +Start Assign Priority Nets ... +TargetSlk(0.200ns) MaxAssign(3%) minLen(50um) +Existing Priority Nets 0 (0.0%) +Total Assign Priority Nets 401 (3.0%) + +------------------------------------------------------------ + Pre-ecoRoute Summary +------------------------------------------------------------ + +Setup views included: + PVT_0P63V_100C.setup_view + ++--------------------+---------+---------+---------+---------+ +| Setup mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| 0.002 | 0.002 | 0.005 | 0.129 | +| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | +| Violating Paths:| 0 | 0 | 0 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 0 (0) | 0.000 | 0 (0) | +| max_tran | 0 (0) | 0.000 | 4 (4) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 23.427% +Total number of glitch violations: 0 +------------------------------------------------------------ +**opt_design ... cpu = 0:02:46, real = 0:01:31, mem = 1689.7M, totSessionCpu=0:26:15 ** +For 29680 new insts, *** Applied 2 GNC rules (cpu = 0:00:00.0) +*INFO: Adding fillers to module cpu. +*INFO: Added 0 filler inst (cell DECAPx10_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 11829 filler insts (cell DECAPx10_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx10_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx10_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Added 6 filler insts (cell DECAPx6_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 1048 filler insts (cell DECAPx6_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx6_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx6_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Added 8 filler insts (cell DECAPx4_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 638 filler insts (cell DECAPx4_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx4_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx4_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Added 19 filler insts (cell DECAPx2_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 2596 filler insts (cell DECAPx2_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx2_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx2_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Added 35 filler insts (cell DECAPx1_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 2687 filler insts (cell DECAPx1_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx1_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell DECAPx1_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Added 106 filler insts (cell FILLER_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 4946 filler insts (cell FILLER_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell FILLER_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell FILLER_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Added 96 filler insts (cell FILLERxp5_ASAP7_75t_R / prefix FILLER_AO). +*INFO: Added 5936 filler insts (cell FILLERxp5_ASAP7_75t_L / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell FILLERxp5_ASAP7_75t_SL / prefix FILLER_AO). +*INFO: Added 0 filler inst (cell FILLERxp5_ASAP7_75t_SRAM / prefix FILLER_AO). +*INFO: Total 29950 filler insts added - prefix FILLER_AO (CPU: 0:00:03.8). +For 270 new insts, *** Applied 2 GNC rules (cpu = 0:00:00.0) +*INFO: Filler mode add_fillers_with_drc is default true to avoid gaps, which may add fillers with violations. Please check the violations for FILLER_incr* fillers and fix them before routeDesign. Set it to false can avoid the violation but may leave gaps. +*INFO: Second pass addFiller without DRC checking. +*INFO: Adding fillers to module cpu. +*INFO: Added 0 filler inst of any cell-type. +-routeWithEco false # bool, default=false +-routeWithEco true # bool, default=false, user setting +-routeSelectedNetOnly false # bool, default=false +-routeWithTimingDriven false # bool, default=false +-routeWithSiDriven false # bool, default=false +Existing Dirty Nets : 194 +New Signature Flow (saveAndSetNanoRouteOptions) .... +Reset Dirty Nets : 194 + +route_global_detail + +#set_db route_design_bottom_routing_layer 2 +#set_db route_design_top_routing_layer 7 +#set_db route_design_with_eco true +#Start route_global_detail on Mon Dec 14 22:05:44 2020 +# +#WARNING (NRDB-976) The TRACK STEP 0.3840 for preferred direction tracks is smaller than the PITCH 8.1600 for LAYER Pad. This will cause routability problems for NanoRoute. +#NanoRoute Version 18.10-p002_1 NR180522-1057/18_10-UB +#Loading the last recorded routing design signature +#Created 1078 NETS and 0 SPECIALNETS new signatures +#Summary of the placement changes since last routing: +# Number of instances added (including moved) = 270 +# Number of instances deleted (including moved) = 496 +# Number of instances resized = 279 +# Number of instances with same cell size swap = 58 +# Number of instances with different orientation = 4 +# Number of instances with pin swaps = 2 +# Total number of placement changes (moved instances are counted twice) = 1049 +#Using multithreading with 4 threads. +#Start routing data preparation on Mon Dec 14 22:05:44 2020 +# +#Minimum voltage of a net in the design = 0.000. +#Maximum voltage of a net in the design = 0.770. +#Voltage range [0.000 - 0.000] has 1 net. +#Voltage range [0.630 - 0.630] has 1 net. +#Voltage range [0.000 - 0.630] has 12335 nets. +#Voltage range [0.000 - 0.770] has 1130 nets. +# M1 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M2 H Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M3 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M4 H Track-Pitch = 0.19200 Line-2-Via Pitch = 0.19200 +# M5 V Track-Pitch = 0.21600 Line-2-Via Pitch = 0.19200 +# M6 H Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M7 V Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M8 H Track-Pitch = 0.38400 Line-2-Via Pitch = 0.32000 +# M9 V Track-Pitch = 0.36000 Line-2-Via Pitch = 0.32000 +# Pad H Track-Pitch = 0.38400 Line-2-Via Pitch = 8.28000 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +#Regenerating Ggrids automatically. +#Auto generating G-grids with size=15 tracks, using layer M3's pitch = 0.14400. +#Using automatically generated G-grids. +#Done routing data preparation. +#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1678.32 (MB), peak = 2053.06 (MB) +#Merging special wires using 4 threads... +#WARNING (NRDB-1005) Cannot establish connection to PIN A1 at ( 198.70800 145.31600 ) on M1 for NET cpu/stage1/data1sel_s1/n_10. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN A at ( 210.57600 172.26000 ) on M1 for NET FE_OFN0_reset. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN A at ( 159.16800 150.66000 ) on M1 for NET cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN A1 at ( 174.85200 197.17200 ) on M1 for NET cpu/stage1/regfile/n_266. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN Y at ( 140.22800 196.02000 ) on M1 for NET cpu/stage1/regfile/n_266. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN Y at ( 153.94400 190.62000 ) on M1 for NET cpu/stage1/regfile/CTS_59. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN Y at ( 148.76000 180.90000 ) on M1 for NET cpu/stage1/regfile/CTS_61. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN Y at ( 154.16000 149.58000 ) on M1 for NET cpu/stage1/regfile/CTS_41. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 252.12400 232.74000 ) on M1 for NET mem/dcache/n_635. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN CLK at ( 254.50000 228.42000 ) on M1 for NET mem/dcache/n_635. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN Y at ( 208.58000 130.14000 ) on M1 for NET cpu/stage1/pcreg/CTS_2. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN A1 at ( 207.56400 192.83600 ) on M1 for NET cpu/stage1/pcadder/n_1. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN A1 at ( 206.48400 170.04000 ) on M1 for NET cpu/stage1/pcadder/n_1. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN A1 at ( 203.24400 110.75600 ) on M1 for NET cpu/stage1/pcadder/n_1. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN A1 at ( 198.06000 107.40000 ) on M1 for NET cpu/stage1/pcadder/n_1. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN Y at ( 198.65600 183.06000 ) on M1 for NET cpu/stage1/pcadder/n_1. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN A at ( 204.76800 177.74400 ) on M1 for NET cpu/stage1/pcadder/n_17. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN Y at ( 234.29600 150.66000 ) on M1 for NET cpu/stage2/alu/FE_DBTN43_stage2_alu_in2_1. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN A2 at ( 234.68400 211.06800 ) on M1 for NET cpu/stage3/wbselmux/FE_OCPN1451_n_3. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (NRDB-1005) Cannot establish connection to PIN A2 at ( 230.14800 189.46800 ) on M1 for NET cpu/stage3/wbselmux/FE_OCPN1451_n_3. The NET is considered partially routed. Visually verify wiring at the specified location as the wire/via origin may not touch the PIN. This NET will be rerouted with same or different wiring. +#WARNING (EMS-27) Message (NRDB-1005) has exceeded the current message display limit of 20. +#To increase the message display limit, refer to the product command reference manual. +# +#Connectivity extraction summary: +#1581 routed nets are extracted. +# 468 (3.48%) extracted nets are partially routed. +#10645 routed net(s) are imported. +#26 (0.19%) nets are without wires. +#1215 nets are fixed|skipped|trivial (not extracted). +#Total number of nets = 13467. +# +#Start instance access analysis using 4 threads... +#Instance access analysis statistics: +#Cpu time = 00:00:01 +#Elapsed time = 00:00:00 +#Increased memory = 202.64 (MB) +#Total memory = 1881.47 (MB) +#Peak memory = 2053.06 (MB) +#Found 0 nets for post-route si or timing fixing. +# +#Finished routing data preparation on Mon Dec 14 22:05:45 2020 +# +#Cpu time = 00:00:02 +#Elapsed time = 00:00:01 +#Increased memory = 208.25 (MB) +#Total memory = 1881.47 (MB) +#Peak memory = 2053.06 (MB) +# +# +#Start global routing on Mon Dec 14 22:05:45 2020 +# +#Number of eco nets is 468 +# +#Start global routing data preparation on Mon Dec 14 22:05:45 2020 +# +#Start routing resource analysis on Mon Dec 14 22:05:45 2020 +# +#Routing resource analysis is done on Mon Dec 14 22:05:46 2020 +# +# Resource Analysis: +# +# Routing #Avail #Track #Total %Gcell +# Layer Direction Track Blocked Gcell Blocked +# -------------------------------------------------------------- +# M1 V 1801 629 30132 95.70% +# M2 H 1904 682 30132 26.36% +# M3 V 1389 1041 30132 24.53% +# M4 H 1541 498 30132 5.63% +# M5 V 1191 429 30132 5.59% +# M6 H 641 289 30132 13.79% +# M7 V 526 286 30132 13.90% +# M8 H 8 1033 30132 98.92% +# M9 V 13 958 30132 98.15% +# -------------------------------------------------------------- +# Total 9015 45.57% 271188 42.51% +# +# 302 nets (2.24%) with 1 preferred extra spacing. +# +# +# +#Global routing data preparation is done on Mon Dec 14 22:05:46 2020 +# +#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1687.80 (MB), peak = 2053.06 (MB) +# +#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1687.80 (MB), peak = 2053.06 (MB) +# +#start global routing iteration 1... +#Initial_route: 0.01405 +#Reroute: 0.00283 +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1696.30 (MB), peak = 2053.06 (MB) +# +#start global routing iteration 2... +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1696.55 (MB), peak = 2053.06 (MB) +# +# +#Total number of trivial nets (e.g. < 2 pins) = 1215 (skipped). +#Total number of routable nets = 12252. +#Total number of nets in the design = 13467. +# +#494 routable nets have only global wires. +#11758 routable nets have only detail routed wires. +#114 global routed or unrouted (routable) nets have been constrained (e.g. have preferred extra spacing, require shielding etc.) +#355 detail routed (routable) nets have been constrained (e.g. have preferred extra spacing, require shielding etc.) +# +#Routed nets constraints summary: +#---------------------------------------------------------------------------------------------- +# Rules Pref Extra Space Pref Layer Expansion Ratio Avoid Detour Unconstrained +#---------------------------------------------------------------------------------------------- +# Default 57 49 33 19 380 +#---------------------------------------------------------------------------------------------- +# Total 57 49 33 19 380 +#---------------------------------------------------------------------------------------------- +# +#Routing constraints summary of the whole design: +#---------------------------------------------------------------------------------------------- +# Rules Pref Extra Space Pref Layer Expansion Ratio Avoid Detour Unconstrained +#---------------------------------------------------------------------------------------------- +# Default 302 121 68 70 11783 +#---------------------------------------------------------------------------------------------- +# Total 302 121 68 70 11783 +#---------------------------------------------------------------------------------------------- +# +# +# Congestion Analysis: (blocked Gcells are excluded) +# +# OverCon OverCon +# #Gcell #Gcell %Gcell +# Layer (1) (2) OverCon +# ---------------------------------------------- +# M2 2(0.01%) 1(0.00%) (0.01%) +# M3 0(0.00%) 1(0.00%) (0.00%) +# M4 0(0.00%) 0(0.00%) (0.00%) +# M5 0(0.00%) 0(0.00%) (0.00%) +# M6 7(0.03%) 1(0.00%) (0.03%) +# M7 3(0.01%) 0(0.00%) (0.01%) +# ---------------------------------------------- +# Total 12(0.01%) 3(0.00%) (0.01%) +# +# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 2 +# Overflow after GR: 0.01% H + 0.00% V +# +#Complete Global Routing. +#Total number of nets with non-default rule or having extra spacing = 302 +#Total wire length = 313630 um. +#Total half perimeter of net bounding box = 282334 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 68378 um. +#Total wire length on LAYER M3 = 96396 um. +#Total wire length on LAYER M4 = 54958 um. +#Total wire length on LAYER M5 = 60485 um. +#Total wire length on LAYER M6 = 13782 um. +#Total wire length on LAYER M7 = 19631 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 103121 +#Up-Via Summary (total 103121): +# +#----------------------- +# M1 37119 +# M2 47313 +# M3 10414 +# M4 4949 +# M5 2061 +# M6 1265 +#----------------------- +# 103121 +# +#Total number of involved priority nets 7 +#Maximum src to sink distance for priority net 165.6 +#Average of max src_to_sink distance for priority net 85.6 +#Average of ave src_to_sink distance for priority net 52.8 +#Max overcon = 2 tracks. +#Total overcon = 0.01%. +#Worst layer Gcell overcon rate = 0.03%. +# +#Global routing statistics: +#Cpu time = 00:00:02 +#Elapsed time = 00:00:01 +#Increased memory = -183.45 (MB) +#Total memory = 1698.02 (MB) +#Peak memory = 2053.06 (MB) +# +#Finished global routing on Mon Dec 14 22:05:46 2020 +# +# +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1687.00 (MB), peak = 2053.06 (MB) +#Start Track Assignment. +#Done with 158 horizontal wires in 2 hboxes and 74 vertical wires in 2 hboxes. +#Done with 16 horizontal wires in 2 hboxes and 3 vertical wires in 2 hboxes. +#Complete Track Assignment. +#Total number of nets with non-default rule or having extra spacing = 302 +#Total wire length = 313955 um. +#Total half perimeter of net bounding box = 282334 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 68602 um. +#Total wire length on LAYER M3 = 96443 um. +#Total wire length on LAYER M4 = 54992 um. +#Total wire length on LAYER M5 = 60495 um. +#Total wire length on LAYER M6 = 13791 um. +#Total wire length on LAYER M7 = 19633 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 103121 +#Up-Via Summary (total 103121): +# +#----------------------- +# M1 37119 +# M2 47313 +# M3 10414 +# M4 4949 +# M5 2061 +# M6 1265 +#----------------------- +# 103121 +# +#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1730.75 (MB), peak = 2053.06 (MB) +# +#number of short segments in preferred routing layers +# M4 M5 M6 M7 Total +# 1 4 12 6 23 +# +#Routing data preparation, pin analysis, global routing and track assignment statistics: +#Cpu time = 00:00:04 +#Elapsed time = 00:00:03 +#Increased memory = 57.99 (MB) +#Total memory = 1731.21 (MB) +#Peak memory = 2053.06 (MB) +#Using multithreading with 4 threads. +# +#Start Detail Routing.. +#start initial detail routing ... +# ECO: 2.7% of the total area was rechecked for DRC, and 12.9% required routing. +# number of violations = 31 +# +# By Layer and Type : +# MetSpc EOLSpc Short EolKO Mar Totals +# M1 0 0 0 0 0 0 +# M2 3 5 7 0 1 16 +# M3 1 1 2 0 0 4 +# M4 0 0 0 11 0 11 +# Totals 4 6 9 11 1 31 +#553 out of 44590 instances (1.2%) need to be verified(marked ipoed), dirty area = 0.5%. +#2.0% of the total area is being checked for drcs +#2.0% of the total area was checked +# number of violations = 31 +# +# By Layer and Type : +# MetSpc EOLSpc Short EolKO Mar Totals +# M1 0 0 0 0 0 0 +# M2 3 5 7 0 1 16 +# M3 1 1 2 0 0 4 +# M4 0 0 0 11 0 11 +# Totals 4 6 9 11 1 31 +#cpu time = 00:00:36, elapsed time = 00:00:35, memory = 1823.87 (MB), peak = 2053.06 (MB) +#start 1st optimization iteration ... +# number of violations = 9 +# +# By Layer and Type : +# MetSpc EOLSpc Short EolKO Totals +# M1 0 0 0 0 0 +# M2 1 1 4 0 6 +# M3 0 0 1 0 1 +# M4 0 0 0 2 2 +# Totals 1 1 5 2 9 +#cpu time = 00:00:04, elapsed time = 00:00:04, memory = 1827.79 (MB), peak = 2053.06 (MB) +#start 2nd optimization iteration ... +# number of violations = 7 +# +# By Layer and Type : +# MetSpc EOLSpc Short EolKO Totals +# M1 0 0 0 0 0 +# M2 2 2 2 0 6 +# M3 0 0 0 0 0 +# M4 0 0 0 1 1 +# Totals 2 2 2 1 7 +#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1828.22 (MB), peak = 2053.06 (MB) +#start 3rd optimization iteration ... +# number of violations = 13 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 3 4 1 8 +# M3 2 2 1 5 +# Totals 5 6 2 13 +#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1827.81 (MB), peak = 2053.06 (MB) +#start 4th optimization iteration ... +# number of violations = 5 +# +# By Layer and Type : +# Short EolKO Totals +# M1 0 0 0 +# M2 4 1 5 +# Totals 4 1 5 +#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1860.62 (MB), peak = 2053.06 (MB) +#start 5th optimization iteration ... +# number of violations = 8 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# M3 1 1 1 3 +# Totals 3 3 2 8 +#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1860.53 (MB), peak = 2053.06 (MB) +#start 6th optimization iteration ... +# number of violations = 7 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 1 1 2 4 +# M3 1 1 1 3 +# Totals 2 2 3 7 +#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1860.39 (MB), peak = 2053.06 (MB) +#start 7th optimization iteration ... +# number of violations = 6 +# +# By Layer and Type : +# MetSpc EOLSpc Totals +# M1 0 0 0 +# M2 3 3 6 +# Totals 3 3 6 +#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1861.15 (MB), peak = 2053.06 (MB) +#start 8th optimization iteration ... +# number of violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1860.55 (MB), peak = 2053.06 (MB) +#start 9th optimization iteration ... +# number of violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1861.07 (MB), peak = 2053.06 (MB) +#Complete Detail Routing. +#Total number of nets with non-default rule or having extra spacing = 302 +#Total wire length = 313658 um. +#Total half perimeter of net bounding box = 282334 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 68406 um. +#Total wire length on LAYER M3 = 96441 um. +#Total wire length on LAYER M4 = 54962 um. +#Total wire length on LAYER M5 = 60462 um. +#Total wire length on LAYER M6 = 13779 um. +#Total wire length on LAYER M7 = 19609 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 103628 +#Up-Via Summary (total 103628): +# +#----------------------- +# M1 37188 +# M2 47690 +# M3 10466 +# M4 4962 +# M5 2053 +# M6 1269 +#----------------------- +# 103628 +# +#Total number of DRC violations = 5 +#Total number of violations on LAYER M1 = 0 +#Total number of violations on LAYER M2 = 5 +#Total number of violations on LAYER M3 = 0 +#Total number of violations on LAYER M4 = 0 +#Total number of violations on LAYER M5 = 0 +#Total number of violations on LAYER M6 = 0 +#Total number of violations on LAYER M7 = 0 +#Total number of violations on LAYER M8 = 0 +#Total number of violations on LAYER M9 = 0 +#Total number of violations on LAYER Pad = 0 +#Cpu time = 00:00:46 +#Elapsed time = 00:00:45 +#Increased memory = -27.90 (MB) +#Total memory = 1703.38 (MB) +#Peak memory = 2053.06 (MB) +# +#Start Post Routing Optimization. +#start 1st post routing optimization iteration ... +# number of DRC violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:06, elapsed time = 00:00:05, memory = 1704.54 (MB), peak = 2053.06 (MB) +#start 2nd post routing optimization iteration ... +# number of DRC violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:04, elapsed time = 00:00:03, memory = 1699.27 (MB), peak = 2053.06 (MB) +#start 3rd post routing optimization iteration ... +# number of DRC violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:04, elapsed time = 00:00:04, memory = 1699.91 (MB), peak = 2053.06 (MB) +#Complete Post Routing Optimization. +#Cpu time = 00:00:13 +#Elapsed time = 00:00:12 +#Increased memory = -3.46 (MB) +#Total memory = 1699.91 (MB) +#Peak memory = 2053.06 (MB) +#Total number of nets with non-default rule or having extra spacing = 302 +#Total wire length = 313658 um. +#Total half perimeter of net bounding box = 282334 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 68406 um. +#Total wire length on LAYER M3 = 96441 um. +#Total wire length on LAYER M4 = 54962 um. +#Total wire length on LAYER M5 = 60462 um. +#Total wire length on LAYER M6 = 13779 um. +#Total wire length on LAYER M7 = 19609 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 103628 +#Up-Via Summary (total 103628): +# +#----------------------- +# M1 37188 +# M2 47690 +# M3 10466 +# M4 4962 +# M5 2053 +# M6 1269 +#----------------------- +# 103628 +# +#Total number of DRC violations = 5 +#Total number of violations on LAYER M1 = 0 +#Total number of violations on LAYER M2 = 5 +#Total number of violations on LAYER M3 = 0 +#Total number of violations on LAYER M4 = 0 +#Total number of violations on LAYER M5 = 0 +#Total number of violations on LAYER M6 = 0 +#Total number of violations on LAYER M7 = 0 +#Total number of violations on LAYER M8 = 0 +#Total number of violations on LAYER M9 = 0 +#Total number of violations on LAYER Pad = 0 +# +#Start Post Route wire spreading.. +# +#Start data preparation for wire spreading... +# +#Data preparation is done on Mon Dec 14 22:06:45 2020 +# +# +#Start Post Route Wire Spread. +#Done with 0 horizontal wires in 3 hboxes and 0 vertical wires in 3 hboxes. +#Complete Post Route Wire Spread. +# +#Total number of nets with non-default rule or having extra spacing = 302 +#Total wire length = 313658 um. +#Total half perimeter of net bounding box = 282334 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 68406 um. +#Total wire length on LAYER M3 = 96441 um. +#Total wire length on LAYER M4 = 54962 um. +#Total wire length on LAYER M5 = 60462 um. +#Total wire length on LAYER M6 = 13779 um. +#Total wire length on LAYER M7 = 19609 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 103628 +#Up-Via Summary (total 103628): +# +#----------------------- +# M1 37188 +# M2 47690 +# M3 10466 +# M4 4962 +# M5 2053 +# M6 1269 +#----------------------- +# 103628 +# +# number of violations = 5 +# +# By Layer and Type : +# MetSpc EOLSpc Short Totals +# M1 0 0 0 0 +# M2 2 2 1 5 +# Totals 2 2 1 5 +#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1721.67 (MB), peak = 2053.06 (MB) +#CELL_VIEW riscv_top,init has 5 DRC violations +#Total number of DRC violations = 5 +#Total number of violations on LAYER M1 = 0 +#Total number of violations on LAYER M2 = 5 +#Total number of violations on LAYER M3 = 0 +#Total number of violations on LAYER M4 = 0 +#Total number of violations on LAYER M5 = 0 +#Total number of violations on LAYER M6 = 0 +#Total number of violations on LAYER M7 = 0 +#Total number of violations on LAYER M8 = 0 +#Total number of violations on LAYER M9 = 0 +#Total number of violations on LAYER Pad = 0 +#Post Route wire spread is done. +#Total number of nets with non-default rule or having extra spacing = 302 +#Total wire length = 313658 um. +#Total half perimeter of net bounding box = 282334 um. +#Total wire length on LAYER M1 = 0 um. +#Total wire length on LAYER M2 = 68406 um. +#Total wire length on LAYER M3 = 96441 um. +#Total wire length on LAYER M4 = 54962 um. +#Total wire length on LAYER M5 = 60462 um. +#Total wire length on LAYER M6 = 13779 um. +#Total wire length on LAYER M7 = 19609 um. +#Total wire length on LAYER M8 = 0 um. +#Total wire length on LAYER M9 = 0 um. +#Total wire length on LAYER Pad = 0 um. +#Total number of vias = 103628 +#Up-Via Summary (total 103628): +# +#----------------------- +# M1 37188 +# M2 47690 +# M3 10466 +# M4 4962 +# M5 2053 +# M6 1269 +#----------------------- +# 103628 +# +#route_detail Statistics: +#Cpu time = 00:01:01 +#Elapsed time = 00:00:58 +#Increased memory = -35.71 (MB) +#Total memory = 1695.56 (MB) +#Peak memory = 2053.06 (MB) +#Updating routing design signature +#Created 820 library cell signatures +#Created 13467 NETS and 0 SPECIALNETS signatures +#Created 44590 instance signatures +#Build design signature : cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1696.44 (MB), peak = 2053.06 (MB) +#Save design signature : cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1696.65 (MB), peak = 2053.06 (MB) +# +#route_global_detail statistics: +#Cpu time = 00:01:07 +#Elapsed time = 00:01:02 +#Increased memory = -49.37 (MB) +#Total memory = 1660.14 (MB) +#Peak memory = 2053.06 (MB) +#Number of warnings = 25 +#Total number of warnings = 155 +#Number of fails = 0 +#Total number of fails = 0 +#Complete route_global_detail on Mon Dec 14 22:06:46 2020 +# +**opt_design ... cpu = 0:03:58, real = 0:02:37, mem = 1619.9M, totSessionCpu=0:27:26 ** +-routeWithEco false # bool, default=false +-routeSelectedNetOnly false # bool, default=false +-routeWithTimingDriven false # bool, default=false +-routeWithSiDriven false # bool, default=false +New Signature Flow (restoreNanoRouteOptions) .... +#WARNING (NRDB-976) The TRACK STEP 0.3840 for preferred direction tracks is smaller than the PITCH 8.1600 for LAYER Pad. This will cause routability problems for NanoRoute. +#Start routing data preparation on Mon Dec 14 22:06:46 2020 +# +#Minimum voltage of a net in the design = 0.000. +#Maximum voltage of a net in the design = 0.770. +#Voltage range [0.000 - 0.000] has 1 net. +#Voltage range [0.630 - 0.630] has 1 net. +#Voltage range [0.000 - 0.630] has 12335 nets. +#Voltage range [0.000 - 0.770] has 1130 nets. +# M1 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M2 H Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M3 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M4 H Track-Pitch = 0.19200 Line-2-Via Pitch = 0.19200 +# M5 V Track-Pitch = 0.21600 Line-2-Via Pitch = 0.19200 +# M6 H Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M7 V Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M8 H Track-Pitch = 0.38400 Line-2-Via Pitch = 0.32000 +# M9 V Track-Pitch = 0.36000 Line-2-Via Pitch = 0.32000 +# Pad H Track-Pitch = 0.38400 Line-2-Via Pitch = 8.28000 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +#Regenerating Ggrids automatically. +#Auto generating G-grids with size=15 tracks, using layer M3's pitch = 0.14400. +#Using automatically generated G-grids. +#Done routing data preparation. +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1623.51 (MB), peak = 2053.06 (MB) +#Extract in post route mode +# +#Start tQuantus RC extraction... +#Start building rc corner(s)... +#Number of RC Corner = 2 +#Corner PVT_0P77V_0C.hold_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 (real) +#Corner PVT_0P63V_100C.setup_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 (real) +#LISD -> M1 (1) +#M1 -> M2 (2) +#M2 -> M3 (3) +#M3 -> M4 (4) +#M4 -> M5 (5) +#M5 -> M6 (6) +#M6 -> M7 (7) +#M7 -> M8 (8) +#M8 -> M9 (9) +#M9 -> Pad (10) +#SADV_On +# Corner(s) : +#PVT_0P77V_0C.hold_rc [ 0.00] +#PVT_0P63V_100C.setup_rc [100.00] +# Corner id: 0 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 0.000000 +# Ref. Temp : 25.000000 +# Corner id: 1 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 100.000000 +# Ref. Temp : 25.000000 +#SADV_Off +# +#layer[1] tech width 288 != ict width 400.0 +# +#layer[1] tech spc 288 != ict spc 464.0 +# +#layer[4] tech width 384 != ict width 288.0 +# +#layer[4] tech spc 384 != ict spc 288.0 +# +#layer[6] tech width 512 != ict width 384.0 +# +#layer[6] tech spc 512 != ict spc 384.0 +# +#layer[8] tech width 640 != ict width 512.0 +# +#layer[8] tech spc 640 != ict spc 512.0 +# +#layer[10] tech spc 32000 != ict spc 640.0 +#total pattern=220 [20, 605] +#Reading previously stored rc_model file ( rc_model.bin ) ... +#found CAPMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 +#number model r/c [2,1] [20,605] read +#0 rcmodel(s) requires rebuild +#Build RC corners: cpu time = 00:00:01, elapsed time = 00:00:02, memory = 1657.16 (MB), peak = 2053.06 (MB) +#Start building rc corner(s)... +#Number of RC Corner = 2 +#Corner PVT_0P77V_0C.hold_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 (real) +#Corner PVT_0P63V_100C.setup_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 (real) +#LISD -> M1 (1) +#M1 -> M2 (2) +#M2 -> M3 (3) +#M3 -> M4 (4) +#M4 -> M5 (5) +#M5 -> M6 (6) +#M6 -> M7 (7) +#M7 -> M8 (8) +#M8 -> M9 (9) +#M9 -> Pad (10) +#SADV_On +# Corner(s) : +#PVT_0P77V_0C.hold_rc [ 0.00] +#PVT_0P63V_100C.setup_rc [100.00] +# Corner id: 0 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 0.000000 +# Ref. Temp : 25.000000 +# Corner id: 1 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 100.000000 +# Ref. Temp : 25.000000 +#SADV_Off +# +#layer[1] tech width 288 != ict width 400.0 +# +#layer[1] tech spc 288 != ict spc 464.0 +# +#layer[4] tech width 384 != ict width 288.0 +# +#layer[4] tech spc 384 != ict spc 288.0 +# +#layer[6] tech width 512 != ict width 384.0 +# +#layer[6] tech spc 512 != ict spc 384.0 +# +#layer[8] tech width 640 != ict width 512.0 +# +#layer[8] tech spc 640 != ict spc 512.0 +# +#layer[10] tech spc 32000 != ict spc 640.0 +#total pattern=220 [20, 605] +#Reading previously stored rc_model file ( rc_model.bin ) ... +#found CAPMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 +#number model r/c [2,1] [20,605] read +#0 rcmodel(s) requires rebuild +#Build RC corners: cpu time = 00:00:01, elapsed time = 00:00:02, memory = 1671.36 (MB), peak = 2053.06 (MB) +#Using multithreading with 4 threads. +#Length limit = 200 pitches +#opt mode = 2 +#Start routing data preparation on Mon Dec 14 22:06:54 2020 +# +#Minimum voltage of a net in the design = 0.000. +#Maximum voltage of a net in the design = 0.770. +#Voltage range [0.000 - 0.630] has 12335 nets. +#Voltage range [0.000 - 0.770] has 1130 nets. +#Voltage range [0.630 - 0.630] has 1 net. +#Voltage range [0.000 - 0.000] has 1 net. +#Regenerating Ggrids automatically. +#Auto generating G-grids with size=15 tracks, using layer M3's pitch = 0.14400. +#Using automatically generated G-grids. +#Done routing data preparation. +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1649.09 (MB), peak = 2053.06 (MB) +#Start routing data preparation on Mon Dec 14 22:06:54 2020 +# +#Minimum voltage of a net in the design = 0.000. +#Maximum voltage of a net in the design = 0.770. +#Voltage range [0.000 - 0.630] has 12335 nets. +#Voltage range [0.000 - 0.770] has 1130 nets. +#Voltage range [0.630 - 0.630] has 1 net. +#Voltage range [0.000 - 0.000] has 1 net. +#Regenerating Ggrids automatically. +#Auto generating G-grids with size=15 tracks, using layer M3's pitch = 0.14400. +#Using automatically generated G-grids. +#Done routing data preparation. +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1649.09 (MB), peak = 2053.06 (MB) +#Start generate extraction boxes. +# +#Extract using 30 x 30 Hboxes +#7x8 initial hboxes +#Use area based hbox pruning. +#0/0 hboxes pruned. +#Complete generating extraction boxes. +#Extract 34 hboxes with 4 threads on machine with Core_i5 2.90GHz 3072KB Cache 4CPU... +#Process 0 special clock nets for rc extraction +#0 temporary NDR added +#Total 12252 nets were built. 2439 nodes added to break long wires. 0 net(s) have incomplete routes. +#Run Statistics for Extraction: +# Cpu time = 00:00:14, elapsed time = 00:00:04 . +# Increased memory = 195.46 (MB), total memory = 1844.55 (MB), peak memory = 2053.06 (MB) +#Simplify RC tree: cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1684.45 (MB), peak = 2053.06 (MB) +#RC Statistics: 68196 Res, 42195 Ground Cap, 2500 XCap (Edge to Edge) +#RC V/H edge ratio: 0.59, Avg V/H Edge Length: 8760.02 (45733), Avg L-Edge Length: 15755.16 (17600) +#Start writing rcdb into /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/nr22257_rKMqFl.rcdb.d +2020/12/14 22:06:59 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:06:59 For more info, please run CheckSysConf in +#Finish writing rcdb with 80479 nodes, 68227 edges, and 5472 xcaps +#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1690.83 (MB), peak = 2053.06 (MB) +Restoring parasitic data from file '/tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/nr22257_rKMqFl.rcdb.d' ... +Reading RCDB with compressed RC data. +Reading RCDB with compressed RC data. +Begin read_parasitics... (cpu: 0:00:00.0 real: 0:00:00.0 mem: 2272.391M) +Following multi-corner parasitics specified: + /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/nr22257_rKMqFl.rcdb.d (rcdb) +Reading RCDB with compressed RC data. + Cell riscv_top has rcdb /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/nr22257_rKMqFl.rcdb.d specified +Cell riscv_top, hinst +Reading RCDB with compressed RC data. +2020/12/14 22:06:59 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:06:59 For more info, please run CheckSysConf in +2020/12/14 22:06:59 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:06:59 For more info, please run CheckSysConf in +Done read_parasitics... (cpu: 0:00:00.2 real: 0:00:00.0 mem: 2248.391M) +# +#Restore RCDB. +# +#Complete tQuantus RC extraction. +#Cpu time = 00:00:22 +#Elapsed time = 00:00:13 +#Increased memory = 61.66 (MB) +#Total memory = 1685.16 (MB) +#Peak memory = 2053.06 (MB) +# +#2439 inserted nodes are removed +**opt_design ... cpu = 0:04:21, real = 0:02:51, mem = 1638.7M, totSessionCpu=0:27:50 ** +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +Starting SI iteration 1 using Infinite Timing Windows +Begin IPO call back ... +End IPO call back ... +################################################################################# +# Design Stage: PostRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: SPEF/RCDB +# Signoff Settings: SI On +################################################################################# +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=2235.96) +Initializing multi-corner resistance tables ... +Reading RCDB with compressed RC data. +AAE_INFO: 4 threads acquired from CTE. +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 91.9 percent of the nets selected for SI analysis +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 91.9 percent of the nets selected for SI analysis +End delay calculation. (MEM=2475.91 CPU=0:00:07.4 REAL=0:00:03.0) +End delay calculation (fullDC). (MEM=2475.91 CPU=0:00:08.0 REAL=0:00:03.0) +Loading CTE timing window with TwFlowType 0...(CPU = 0:00:00.0, REAL = 0:00:00.0, MEM = 2475.9M) +Add other clocks and setupCteToAAEClockMapping during iter 1 +Loading CTE timing window is completed (CPU = 0:00:00.1, REAL = 0:00:00.0, MEM = 2475.9M) +Starting SI iteration 2 +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=2264.56) +Glitch Analysis: View PVT_0P63V_100C.setup_view -- Total Number of Nets Skipped = 0. +Glitch Analysis: View PVT_0P63V_100C.setup_view -- Total Number of Nets Analyzed = 0. +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 4.3 percent of the nets selected for SI analysis +End delay calculation. (MEM=2385.18 CPU=0:00:00.6 REAL=0:00:01.0) +End delay calculation (fullDC). (MEM=2385.18 CPU=0:00:00.7 REAL=0:00:01.0) +*** Done Building Timing Graph (cpu=0:00:13.1 real=0:00:05.0 totSessionCpu=0:28:03 mem=2416.2M) + +------------------------------------------------------------ + Post-ecoRoute Summary +------------------------------------------------------------ + +Setup views included: + PVT_0P63V_100C.setup_view + ++--------------------+---------+---------+---------+---------+ +| Setup mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| 0.002 | 0.002 | 0.004 | 0.129 | +| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | +| Violating Paths:| 0 | 0 | 0 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 0 (0) | 0.000 | 0 (0) | +| max_tran | 0 (0) | 0.000 | 0 (0) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 23.427% + (99.999% with Fillers) +Total number of glitch violations: 0 +------------------------------------------------------------ +**opt_design ... cpu = 0:04:35, real = 0:02:57, mem = 1710.0M, totSessionCpu=0:28:04 ** +**opt_design ... cpu = 0:04:35, real = 0:02:57, mem = 1710.0M, totSessionCpu=0:28:04 ** +Executing marking Critical Nets1 +*** Timing Is met +*** Check timing (0:00:00.0) +Running postRoute recovery in postEcoRoute mode +**opt_design ... cpu = 0:04:35, real = 0:02:57, mem = 1710.0M, totSessionCpu=0:28:04 ** +Checking setup slack degradation ... +Checking DRV degradation... +**INFO: Skipping DRV recovery as drv did not degrade beyond margin +*** Finish postRoute recovery in postEcoRoute mode (cpu=0:00:00, real=0:00:00, mem=2256.57M, totSessionCpu=0:28:04). +**opt_design ... cpu = 0:04:35, real = 0:02:57, mem = 1710.0M, totSessionCpu=0:28:04 ** + +[hotspot] +------------+---------------+---------------+ +[hotspot] | | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | normalized | 0.26 | 0.79 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis: normalized max congestion hotspot area = 0.26, normalized total congestion hotspot area = 0.79 (area is in unit of 4 std-cell row bins) +[hotspot] top 3 congestion hotspot bounding boxes and scores of normalized hotspot +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | top | hotspot bbox | hotspot score | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 1 | 250.56 112.32 267.84 129.60 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 2 | 164.16 138.24 181.44 155.52 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 3 | 164.16 181.44 181.44 198.72 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ + + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: postroute.recovery +Latch borrow mode reset to max_borrow +Set spgFreeCellsHonorFence to 1 +Reported timing to dir ./timingReports +**opt_design ... cpu = 0:04:38, real = 0:02:59, mem = 1710.9M, totSessionCpu=0:28:07 ** +2020/12/14 22:07:08 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:08 For more info, please run CheckSysConf in +**INFO: Starting Blocking QThread with 4 CPU + ____________________________________________________________________ +__/ message from Blocking QThread +Multi-CPU acceleration using 4 CPU(s). +*** QThread HoldRpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), mem = 0.6M +Multithreaded Timing Analysis is initialized with 4 threads + +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +Starting SI iteration 1 using Infinite Timing Windows +Begin IPO call back ... +End IPO call back ... +################################################################################# +# Design Stage: PostRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: SPEF/RCDB +# Signoff Settings: SI On +################################################################################# +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=0) +*** Calculating scaling factor for PVT_0P77V_0C.hold_set libraries using the default operating condition of each library. +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 91.9 percent of the nets selected for SI analysis +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 91.9 percent of the nets selected for SI analysis +End delay calculation. (MEM=0 CPU=0:00:09.3 REAL=0:00:03.0) +End delay calculation (fullDC). (MEM=0 CPU=0:00:09.9 REAL=0:00:04.0) +Loading CTE timing window with TwFlowType 0...(CPU = 0:00:00.0, REAL = 0:00:00.0, MEM = 0.0M) +Add other clocks and setupCteToAAEClockMapping during iter 1 +Loading CTE timing window is completed (CPU = 0:00:00.1, REAL = 0:00:00.0, MEM = 0.0M) +Starting SI iteration 2 +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=0) +Glitch Analysis: View PVT_0P77V_0C.hold_view -- Total Number of Nets Skipped = 0. +Glitch Analysis: View PVT_0P77V_0C.hold_view -- Total Number of Nets Analyzed = 0. +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 6.5 percent of the nets selected for SI analysis +End delay calculation. (MEM=0 CPU=0:00:00.9 REAL=0:00:01.0) +End delay calculation (fullDC). (MEM=0 CPU=0:00:00.9 REAL=0:00:01.0) +*** Done Building Timing Graph (cpu=0:00:13.9 real=0:00:05.0 totSessionCpu=0:00:56.0 mem=0.0M) +*** QThread HoldRpt [finish] : cpu/real = 0:00:15.5/0:00:06.0 (2.6), mem = 0.0M +_______________________________________________________________________ +*** QThread HoldRpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), mem = 0.6M +Multithreaded Timing Analysis is initialized with 4 threads + +**ERROR: (IMPTS-17): Inconsistency detected in the capacitance units specified among the timing libraries being used. Default system capacitance unit of 1pF will be used. Use the 'setLibraryUnit' command to set a specific capacitance unit. +Type 'man IMPTS-17' for more detail. +Starting SI iteration 1 using Infinite Timing Windows +Begin IPO call back ... +End IPO call back ... +################################################################################# +# Design Stage: PostRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: SPEF/RCDB +# Signoff Settings: SI On +################################################################################# +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=0) +*** Calculating scaling factor for PVT_0P77V_0C.hold_set libraries using the default operating condition of each library. +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 91.9 percent of the nets selected for SI analysis +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 91.9 percent of the nets selected for SI analysis +End delay calculation. (MEM=0 CPU=0:00:09.3 REAL=0:00:03.0) +End delay calculation (fullDC). (MEM=0 CPU=0:00:09.9 REAL=0:00:04.0) +Loading CTE timing window with TwFlowType 0...(CPU = 0:00:00.0, REAL = 0:00:00.0, MEM = 0.0M) +Add other clocks and setupCteToAAEClockMapping during iter 1 +Loading CTE timing window is completed (CPU = 0:00:00.1, REAL = 0:00:00.0, MEM = 0.0M) +Starting SI iteration 2 +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=0) +Glitch Analysis: View PVT_0P77V_0C.hold_view -- Total Number of Nets Skipped = 0. +Glitch Analysis: View PVT_0P77V_0C.hold_view -- Total Number of Nets Analyzed = 0. +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 6.5 percent of the nets selected for SI analysis +End delay calculation. (MEM=0 CPU=0:00:00.9 REAL=0:00:01.0) +End delay calculation (fullDC). (MEM=0 CPU=0:00:00.9 REAL=0:00:01.0) +*** Done Building Timing Graph (cpu=0:00:13.9 real=0:00:05.0 totSessionCpu=0:00:56.0 mem=0.0M) +*** QThread HoldRpt [finish] : cpu/real = 0:00:15.5/0:00:06.0 (2.6), mem = 0.0M + +2020/12/14 22:07:15 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:15 For more info, please run CheckSysConf in +2020/12/14 22:07:15 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:15 For more info, please run CheckSysConf in +2020/12/14 22:07:15 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:15 For more info, please run CheckSysConf in +2020/12/14 22:07:15 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:15 For more info, please run CheckSysConf in +2020/12/14 22:07:15 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:15 For more info, please run CheckSysConf in +2020/12/14 22:07:15 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:15 For more info, please run CheckSysConf in +2020/12/14 22:07:15 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:15 For more info, please run CheckSysConf in +2020/12/14 22:07:15 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:15 For more info, please run CheckSysConf in + +------------------------------------------------------------ + opt_design Final SI Timing Summary +------------------------------------------------------------ + +Setup views included: + PVT_0P63V_100C.setup_view +Hold views included: + PVT_0P77V_0C.hold_view + ++--------------------+---------+---------+---------+---------+ +| Setup mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| 0.002 | 0.002 | 0.004 | 0.129 | +| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | +| Violating Paths:| 0 | 0 | 0 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++--------------------+---------+---------+---------+---------+ +| Hold mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| -0.000 | -0.000 | 0.013 | 0.012 | +| TNS (ns):| -0.000 | -0.000 | 0.000 | 0.000 | +| Violating Paths:| 2 | 2 | 0 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 0 (0) | 0.000 | 0 (0) | +| max_tran | 0 (0) | 0.000 | 0 (0) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 23.427% + (99.999% with Fillers) +Total number of glitch violations: 0 +------------------------------------------------------------ +**opt_design ... cpu = 0:04:55, real = 0:03:07, mem = 1711.1M, totSessionCpu=0:28:23 ** + ReSet Options after AAE Based Opt flow +*** Finished opt_design *** + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: 0.000 ns 0.002 ns final +[hotspot] +------------+---------------+---------------+ +[hotspot] | | max hotspot | total hotspot | +[hotspot] +------------+---------------+---------------+ +[hotspot] | normalized | 0.26 | 0.79 | +[hotspot] +------------+---------------+---------------+ +Local HotSpot Analysis: normalized max congestion hotspot area = 0.26, normalized total congestion hotspot area = 0.79 (area is in unit of 4 std-cell row bins) +[hotspot] top 3 congestion hotspot bounding boxes and scores of normalized hotspot +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | top | hotspot bbox | hotspot score | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 1 | 250.56 112.32 267.84 129.60 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 2 | 164.16 138.24 181.44 155.52 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ +[hotspot] | 3 | 164.16 181.44 181.44 198.72 | 0.26 | +[hotspot] +-----+-------------------------------------+---------------+ + + flow.cputime flow.realtime timing.setup.tns timing.setup.wns snapshot +UM: 302.52 196 0.000 ns 0.002 ns opt_design_postroute +Reset maxLocalDensity to default value from N7/N5 setting. +Info: Destroy the CCOpt slew target map. +Removing temporary dont_use automatically set for cells with technology sites with no row. +@file(par.tcl) 125: puts "write_db pre_write_regs" +write_db pre_write_regs +@file(par.tcl) 126: write_db pre_write_regs +#% Begin write_db save design ... (date=12/14 22:07:18, mem=1721.1M) +The in-memory database contained RC information but was not saved. To save +the RC information, use write_db's -rc_extract option. Note: Saving RC information can be quite large, +so it should only be saved when it is really desired. +% Begin Save ccopt configuration ... (date=12/14 22:07:18, mem=1721.1M) +% End Save ccopt configuration ... (date=12/14 22:07:18, total cpu=0:00:00.1, real=0:00:00.0, peak res=1721.6M, current mem=1721.6M) +% Begin Save netlist data ... (date=12/14 22:07:18, mem=1721.6M) +Writing Binary DB to pre_write_regs/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 22:07:18, total cpu=0:00:00.1, real=0:00:00.0, peak res=1727.9M, current mem=1727.9M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file pre_write_regs/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 22:07:18, mem=1728.4M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 22:07:18, total cpu=0:00:00.0, real=0:00:00.0, peak res=1728.4M, current mem=1728.4M) +2020/12/14 22:07:18 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:18 For more info, please run CheckSysConf in +2020/12/14 22:07:18 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:18 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 22:07:18, mem=1750.7M) +% End Save clock tree data ... (date=12/14 22:07:18, total cpu=0:00:00.0, real=0:00:00.0, peak res=1750.7M, current mem=1750.7M) +Saving preference file pre_write_regs/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 22:07:19 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:19 For more info, please run CheckSysConf in +Saving Drc markers ... +2020/12/14 22:07:19 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:19 For more info, please run CheckSysConf in +... 5 markers are saved ... +... 5 geometry drc markers are saved ... +... 0 antenna drc markers are saved ... +% Begin Save routing data ... (date=12/14 22:07:19, mem=1759.1M) +Saving route file ... +2020/12/14 22:07:19 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:19 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.1 real=0:00:00.0 mem=2274.6M) *** +% End Save routing data ... (date=12/14 22:07:19, total cpu=0:00:00.1, real=0:00:00.0, peak res=1760.1M, current mem=1760.1M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 22:07:19 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:19 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file pre_write_regs/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=2290.6M) *** +#Saving pin access data to file pre_write_regs/riscv_top.apa ... +# +% Begin Save power constraints data ... (date=12/14 22:07:19, mem=1763.5M) +% End Save power constraints data ... (date=12/14 22:07:19, total cpu=0:00:00.0, real=0:00:00.0, peak res=1763.5M, current mem=1763.5M) +Saving preRoute extracted patterns in file 'pre_write_regs/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.01 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design pre_write_regs +#% End write_db save design ... (date=12/14 22:07:22, total cpu=0:00:02.4, real=0:00:04.0, peak res=1763.5M, current mem=1737.5M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 127: puts "ln -sfn pre_write_regs latest" +ln -sfn pre_write_regs latest +@file(par.tcl) 128: ln -sfn pre_write_regs latest +@file(par.tcl) 130: set write_cells_ir "./find_regs_cells.json" +@file(par.tcl) 131: set write_cells_ir [open $write_cells_ir "w"] +@file(par.tcl) 132: puts $write_cells_ir "\[" +@file(par.tcl) 134: set refs [get_db [get_db lib_cells -if .is_flop==true] .base_name] +@file(par.tcl) 136: set len [llength $refs] +@file(par.tcl) 138: for {set i 0} {$i < [llength $refs]} {incr i} { + if {$i == $len - 1} { + puts $write_cells_ir " \"[lindex $refs $i]\"" + } else { + puts $write_cells_ir " \"[lindex $refs $i]\"," + } + } +@file(par.tcl) 146: puts $write_cells_ir "\]" +@file(par.tcl) 147: close $write_cells_ir +@file(par.tcl) 148: set write_regs_ir "./find_regs_paths.json" +@file(par.tcl) 149: set write_regs_ir [open $write_regs_ir "w"] +@file(par.tcl) 150: puts $write_regs_ir "\[" +@file(par.tcl) 152: set regs [get_db [get_db [all_registers -edge_triggered -output_pins] -if .direction==out] .name] +@file(par.tcl) 154: set len [llength $regs] +@file(par.tcl) 156: for {set i 0} {$i < [llength $regs]} {incr i} { + #regsub -all {/} [lindex $regs $i] . myreg + set myreg [lindex $regs $i] + if {$i == $len - 1} { + puts $write_regs_ir " \"$myreg\"" + } else { + puts $write_regs_ir " \"$myreg\"," + } + } +@file(par.tcl) 166: puts $write_regs_ir "\]" +@file(par.tcl) 168: close $write_regs_ir +@file(par.tcl) 170: puts "write_db pre_write_design" +write_db pre_write_design +@file(par.tcl) 171: write_db pre_write_design +#% Begin write_db save design ... (date=12/14 22:07:22, mem=1737.6M) +The in-memory database contained RC information but was not saved. To save +the RC information, use write_db's -rc_extract option. Note: Saving RC information can be quite large, +so it should only be saved when it is really desired. +% Begin Save ccopt configuration ... (date=12/14 22:07:22, mem=1737.6M) +% End Save ccopt configuration ... (date=12/14 22:07:22, total cpu=0:00:00.1, real=0:00:00.0, peak res=1737.7M, current mem=1737.7M) +% Begin Save netlist data ... (date=12/14 22:07:22, mem=1737.7M) +Writing Binary DB to pre_write_design/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 22:07:22, total cpu=0:00:00.1, real=0:00:00.0, peak res=1744.1M, current mem=1744.1M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file pre_write_design/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 22:07:22, mem=1744.1M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 22:07:22, total cpu=0:00:00.0, real=0:00:00.0, peak res=1744.1M, current mem=1744.1M) +2020/12/14 22:07:22 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:22 For more info, please run CheckSysConf in +2020/12/14 22:07:22 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:22 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 22:07:23, mem=1744.1M) +% End Save clock tree data ... (date=12/14 22:07:23, total cpu=0:00:00.0, real=0:00:00.0, peak res=1744.1M, current mem=1744.1M) +Saving preference file pre_write_design/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 22:07:23 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:23 For more info, please run CheckSysConf in +Saving Drc markers ... +2020/12/14 22:07:23 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:23 For more info, please run CheckSysConf in +... 5 markers are saved ... +... 5 geometry drc markers are saved ... +... 0 antenna drc markers are saved ... +% Begin Save routing data ... (date=12/14 22:07:23, mem=1751.9M) +Saving route file ... +2020/12/14 22:07:23 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:23 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.1 real=0:00:00.0 mem=2302.8M) *** +% End Save routing data ... (date=12/14 22:07:23, total cpu=0:00:00.1, real=0:00:00.0, peak res=1752.9M, current mem=1752.9M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 22:07:24 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:24 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 1 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 1 : CPU = 0 : MEM = 0. +Saving property file pre_write_design/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=2318.8M) *** +#Saving pin access data to file pre_write_design/riscv_top.apa ... +# +% Begin Save power constraints data ... (date=12/14 22:07:24, mem=1754.3M) +% End Save power constraints data ... (date=12/14 22:07:24, total cpu=0:00:00.0, real=0:00:00.0, peak res=1754.3M, current mem=1754.3M) +Saving preRoute extracted patterns in file 'pre_write_design/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.01 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design pre_write_design +#% End write_db save design ... (date=12/14 22:07:26, total cpu=0:00:02.3, real=0:00:04.0, peak res=1754.3M, current mem=1739.7M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 172: puts "ln -sfn pre_write_design latest" +ln -sfn pre_write_design latest +@file(par.tcl) 173: ln -sfn pre_write_design latest +@file(par.tcl) 174: puts "write_db riscv_top_FINAL -def -verilog" +write_db riscv_top_FINAL -def -verilog +@file(par.tcl) 175: write_db riscv_top_FINAL -def -verilog +#% Begin write_db save design ... (date=12/14 22:07:26, mem=1739.7M) +The in-memory database contained RC information but was not saved. To save +the RC information, use write_db's -rc_extract option. Note: Saving RC information can be quite large, +so it should only be saved when it is really desired. +% Begin Save ccopt configuration ... (date=12/14 22:07:26, mem=1739.7M) +% End Save ccopt configuration ... (date=12/14 22:07:26, total cpu=0:00:00.1, real=0:00:00.0, peak res=1739.7M, current mem=1739.7M) +% Begin Save netlist data ... (date=12/14 22:07:26, mem=1739.7M) +Writing Binary DB to riscv_top_FINAL/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 22:07:26, total cpu=0:00:00.1, real=0:00:00.0, peak res=1744.6M, current mem=1744.6M) +Writing Netlist "riscv_top_FINAL/riscv_top.v.gz" ... +2020/12/14 22:07:27 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:27 For more info, please run CheckSysConf in +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file riscv_top_FINAL/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 22:07:27, mem=1744.7M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 22:07:27, total cpu=0:00:00.0, real=0:00:00.0, peak res=1744.7M, current mem=1744.7M) +2020/12/14 22:07:27 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:27 For more info, please run CheckSysConf in +2020/12/14 22:07:27 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:27 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 22:07:27, mem=1744.7M) +% End Save clock tree data ... (date=12/14 22:07:27, total cpu=0:00:00.0, real=0:00:00.0, peak res=1744.7M, current mem=1744.7M) +Saving preference file riscv_top_FINAL/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 22:07:27 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:27 For more info, please run CheckSysConf in +Saving Drc markers ... +2020/12/14 22:07:28 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:28 For more info, please run CheckSysConf in +... 5 markers are saved ... +... 5 geometry drc markers are saved ... +... 0 antenna drc markers are saved ... +% Begin Save routing data ... (date=12/14 22:07:28, mem=1751.9M) +Saving route file ... +2020/12/14 22:07:28 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:28 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.1 real=0:00:00.0 mem=2319.8M) *** +% End Save routing data ... (date=12/14 22:07:28, total cpu=0:00:00.1, real=0:00:00.0, peak res=1752.9M, current mem=1752.9M) +Saving Def ... +Writing DEF file 'riscv_top_FINAL/riscv_top.def.gz', current time is Mon Dec 14 22:07:28 2020 ... +unitPerMicron=4000, dbgMicronPerDBU=0.000250, unitPerDBU=1.000000 +2020/12/14 22:07:28 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:28 For more info, please run CheckSysConf in +DEF file 'riscv_top_FINAL/riscv_top.def.gz' is written, current time is Mon Dec 14 22:07:28 2020 ... +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 22:07:28 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:28 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file riscv_top_FINAL/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=2335.8M) *** +#Saving pin access data to file riscv_top_FINAL/riscv_top.apa ... +# +% Begin Save power constraints data ... (date=12/14 22:07:28, mem=1757.4M) +% End Save power constraints data ... (date=12/14 22:07:29, total cpu=0:00:00.0, real=0:00:00.0, peak res=1757.4M, current mem=1757.4M) +Saving preRoute extracted patterns in file 'riscv_top_FINAL/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.01 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design riscv_top_FINAL +#% End write_db save design ... (date=12/14 22:07:31, total cpu=0:00:02.7, real=0:00:05.0, peak res=1757.4M, current mem=1742.3M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 176: puts "set_db write_stream_virtual_connection false" +set_db write_stream_virtual_connection false +@file(par.tcl) 177: set_db write_stream_virtual_connection false +@file(par.tcl) 178: puts "write_netlist /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.lvs.v -top_module_first -top_module riscv_top -exclude_leaf_cells -phys -flat -exclude_insts_of_cells { TAPCELL_ASAP7_75t_R TAPCELL_ASAP7_75t_L TAPCELL_ASAP7_75t_SL TAPCELL_ASAP7_75t_SRAM TAPCELL_WITH_FILLER_ASAP7_75t_R TAPCELL_WITH_FILLER_ASAP7_75t_L TAPCELL_WITH_FILLER_ASAP7_75t_SL TAPCELL_WITH_FILLER_ASAP7_75t_SRAM FILLER_ASAP7_75t_R FILLER_ASAP7_75t_L FILLER_ASAP7_75t_SL FILLER_ASAP7_75t_SRAM FILLERxp5_ASAP7_75t_R FILLERxp5_ASAP7_75t_L FILLERxp5_ASAP7_75t_SL FILLERxp5_ASAP7_75t_SRAM DECAPx1_ASAP7_75t_R DECAPx1_ASAP7_75t_L DECAPx1_ASAP7_75t_SL DECAPx1_ASAP7_75t_SRAM DECAPx2_ASAP7_75t_R DECAPx2_ASAP7_75t_L DECAPx2_ASAP7_75t_SL DECAPx2_ASAP7_75t_SRAM DECAPx4_ASAP7_75t_R DECAPx4_ASAP7_75t_L DECAPx4_ASAP7_75t_SL DECAPx4_ASAP7_75t_SRAM DECAPx6_ASAP7_75t_R DECAPx6_ASAP7_75t_L DECAPx6_ASAP7_75t_SL DECAPx6_ASAP7_75t_SRAM DECAPx10_ASAP7_75t_R DECAPx10_ASAP7_75t_L DECAPx10_ASAP7_75t_SL DECAPx10_ASAP7_75t_SRAM } " +write_netlist /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.lvs.v -top_module_first -top_module riscv_top -exclude_leaf_cells -phys -flat -exclude_insts_of_cells { TAPCELL_ASAP7_75t_R TAPCELL_ASAP7_75t_L TAPCELL_ASAP7_75t_SL TAPCELL_ASAP7_75t_SRAM TAPCELL_WITH_FILLER_ASAP7_75t_R TAPCELL_WITH_FILLER_ASAP7_75t_L TAPCELL_WITH_FILLER_ASAP7_75t_SL TAPCELL_WITH_FILLER_ASAP7_75t_SRAM FILLER_ASAP7_75t_R FILLER_ASAP7_75t_L FILLER_ASAP7_75t_SL FILLER_ASAP7_75t_SRAM FILLERxp5_ASAP7_75t_R FILLERxp5_ASAP7_75t_L FILLERxp5_ASAP7_75t_SL FILLERxp5_ASAP7_75t_SRAM DECAPx1_ASAP7_75t_R DECAPx1_ASAP7_75t_L DECAPx1_ASAP7_75t_SL DECAPx1_ASAP7_75t_SRAM DECAPx2_ASAP7_75t_R DECAPx2_ASAP7_75t_L DECAPx2_ASAP7_75t_SL DECAPx2_ASAP7_75t_SRAM DECAPx4_ASAP7_75t_R DECAPx4_ASAP7_75t_L DECAPx4_ASAP7_75t_SL DECAPx4_ASAP7_75t_SRAM DECAPx6_ASAP7_75t_R DECAPx6_ASAP7_75t_L DECAPx6_ASAP7_75t_SL DECAPx6_ASAP7_75t_SRAM DECAPx10_ASAP7_75t_R DECAPx10_ASAP7_75t_L DECAPx10_ASAP7_75t_SL DECAPx10_ASAP7_75t_SRAM } +@file(par.tcl) 179: write_netlist /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.lvs.v -top_module_first -top_module riscv_top -exclude_leaf_cells -phys -flat -exclude_insts_of_cells { TAPCELL_ASAP7_75t_R TAPCELL_ASAP7_75t_L TAPCELL_ASAP7_75t_SL TAPCELL_ASAP7_75t_SRAM TAPCELL_WITH_FILLER_ASAP7_75t_R TAPCELL_WITH_FILLER_ASAP7_75t_L TAPCELL_WITH_FILLER_ASAP7_75t_SL TAPCELL_WITH_FILLER_ASAP7_75t_SRAM FILLER_ASAP7_75t_R FILLER_ASAP7_75t_L FILLER_ASAP7_75t_SL FILLER_ASAP7_75t_SRAM FILLERxp5_ASAP7_75t_R FILLERxp5_ASAP7_75t_L FILLERxp5_ASAP7_75t_SL FILLERxp5_ASAP7_75t_SRAM DECAPx1_ASAP7_75t_R DECAPx1_ASAP7_75t_L DECAPx1_ASAP7_75t_SL DECAPx1_ASAP7_75t_SRAM DECAPx2_ASAP7_75t_R DECAPx2_ASAP7_75t_L DECAPx2_ASAP7_75t_SL DECAPx2_ASAP7_75t_SRAM DECAPx4_ASAP7_75t_R DECAPx4_ASAP7_75t_L DECAPx4_ASAP7_75t_SL DECAPx4_ASAP7_75t_SRAM DECAPx6_ASAP7_75t_R DECAPx6_ASAP7_75t_L DECAPx6_ASAP7_75t_SL DECAPx6_ASAP7_75t_SRAM DECAPx10_ASAP7_75t_R DECAPx10_ASAP7_75t_L DECAPx10_ASAP7_75t_SL DECAPx10_ASAP7_75t_SRAM } +Writing Netlist "/home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.lvs.v" ... +**WARN: (IMPVL-535): -topModuleFirst is not supported for saving physical netlist. The option will be ignored. +Pwr name (VDD). +Gnd name (VSS). +1 Pwr names and 1 Gnd names. +@file(par.tcl) 180: puts "write_netlist /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.sim.v -top_module_first -top_module riscv_top -exclude_leaf_cells -exclude_insts_of_cells { TAPCELL_ASAP7_75t_R TAPCELL_ASAP7_75t_L TAPCELL_ASAP7_75t_SL TAPCELL_ASAP7_75t_SRAM TAPCELL_WITH_FILLER_ASAP7_75t_R TAPCELL_WITH_FILLER_ASAP7_75t_L TAPCELL_WITH_FILLER_ASAP7_75t_SL TAPCELL_WITH_FILLER_ASAP7_75t_SRAM FILLER_ASAP7_75t_R FILLER_ASAP7_75t_L FILLER_ASAP7_75t_SL FILLER_ASAP7_75t_SRAM FILLERxp5_ASAP7_75t_R FILLERxp5_ASAP7_75t_L FILLERxp5_ASAP7_75t_SL FILLERxp5_ASAP7_75t_SRAM DECAPx1_ASAP7_75t_R DECAPx1_ASAP7_75t_L DECAPx1_ASAP7_75t_SL DECAPx1_ASAP7_75t_SRAM DECAPx2_ASAP7_75t_R DECAPx2_ASAP7_75t_L DECAPx2_ASAP7_75t_SL DECAPx2_ASAP7_75t_SRAM DECAPx4_ASAP7_75t_R DECAPx4_ASAP7_75t_L DECAPx4_ASAP7_75t_SL DECAPx4_ASAP7_75t_SRAM DECAPx6_ASAP7_75t_R DECAPx6_ASAP7_75t_L DECAPx6_ASAP7_75t_SL DECAPx6_ASAP7_75t_SRAM DECAPx10_ASAP7_75t_R DECAPx10_ASAP7_75t_L DECAPx10_ASAP7_75t_SL DECAPx10_ASAP7_75t_SRAM } " +write_netlist /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.sim.v -top_module_first -top_module riscv_top -exclude_leaf_cells -exclude_insts_of_cells { TAPCELL_ASAP7_75t_R TAPCELL_ASAP7_75t_L TAPCELL_ASAP7_75t_SL TAPCELL_ASAP7_75t_SRAM TAPCELL_WITH_FILLER_ASAP7_75t_R TAPCELL_WITH_FILLER_ASAP7_75t_L TAPCELL_WITH_FILLER_ASAP7_75t_SL TAPCELL_WITH_FILLER_ASAP7_75t_SRAM FILLER_ASAP7_75t_R FILLER_ASAP7_75t_L FILLER_ASAP7_75t_SL FILLER_ASAP7_75t_SRAM FILLERxp5_ASAP7_75t_R FILLERxp5_ASAP7_75t_L FILLERxp5_ASAP7_75t_SL FILLERxp5_ASAP7_75t_SRAM DECAPx1_ASAP7_75t_R DECAPx1_ASAP7_75t_L DECAPx1_ASAP7_75t_SL DECAPx1_ASAP7_75t_SRAM DECAPx2_ASAP7_75t_R DECAPx2_ASAP7_75t_L DECAPx2_ASAP7_75t_SL DECAPx2_ASAP7_75t_SRAM DECAPx4_ASAP7_75t_R DECAPx4_ASAP7_75t_L DECAPx4_ASAP7_75t_SL DECAPx4_ASAP7_75t_SRAM DECAPx6_ASAP7_75t_R DECAPx6_ASAP7_75t_L DECAPx6_ASAP7_75t_SL DECAPx6_ASAP7_75t_SRAM DECAPx10_ASAP7_75t_R DECAPx10_ASAP7_75t_L DECAPx10_ASAP7_75t_SL DECAPx10_ASAP7_75t_SRAM } +@file(par.tcl) 181: write_netlist /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.sim.v -top_module_first -top_module riscv_top -exclude_leaf_cells -exclude_insts_of_cells { TAPCELL_ASAP7_75t_R TAPCELL_ASAP7_75t_L TAPCELL_ASAP7_75t_SL TAPCELL_ASAP7_75t_SRAM TAPCELL_WITH_FILLER_ASAP7_75t_R TAPCELL_WITH_FILLER_ASAP7_75t_L TAPCELL_WITH_FILLER_ASAP7_75t_SL TAPCELL_WITH_FILLER_ASAP7_75t_SRAM FILLER_ASAP7_75t_R FILLER_ASAP7_75t_L FILLER_ASAP7_75t_SL FILLER_ASAP7_75t_SRAM FILLERxp5_ASAP7_75t_R FILLERxp5_ASAP7_75t_L FILLERxp5_ASAP7_75t_SL FILLERxp5_ASAP7_75t_SRAM DECAPx1_ASAP7_75t_R DECAPx1_ASAP7_75t_L DECAPx1_ASAP7_75t_SL DECAPx1_ASAP7_75t_SRAM DECAPx2_ASAP7_75t_R DECAPx2_ASAP7_75t_L DECAPx2_ASAP7_75t_SL DECAPx2_ASAP7_75t_SRAM DECAPx4_ASAP7_75t_R DECAPx4_ASAP7_75t_L DECAPx4_ASAP7_75t_SL DECAPx4_ASAP7_75t_SRAM DECAPx6_ASAP7_75t_R DECAPx6_ASAP7_75t_L DECAPx6_ASAP7_75t_SL DECAPx6_ASAP7_75t_SRAM DECAPx10_ASAP7_75t_R DECAPx10_ASAP7_75t_L DECAPx10_ASAP7_75t_SL DECAPx10_ASAP7_75t_SRAM } +Writing Netlist "/home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.sim.v" ... +@file(par.tcl) 182: puts "write_stream -mode ALL -map_file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7PDK_r1p5.tar.bz2/asap7PDK_r1p5/cdslib/asap7_TechLib/asap7_fromAPR.layermap -uniquify_cell_names -merge { /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_R.gds /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_L.gds /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_SL.gds /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_SRAM.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW1024x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x46_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x48_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x128_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x46_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x48_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW32x50_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x128_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x128_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x34_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x16_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x4_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x16_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x4_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x16_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x22_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x39_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x4_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x16_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x4_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x8_x4.gds } /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.gds" +write_stream -mode ALL -map_file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7PDK_r1p5.tar.bz2/asap7PDK_r1p5/cdslib/asap7_TechLib/asap7_fromAPR.layermap -uniquify_cell_names -merge { /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_R.gds /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_L.gds /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_SL.gds /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_SRAM.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW1024x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x46_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x48_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x128_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x46_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x48_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW32x50_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x128_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x128_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x34_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x16_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x4_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x16_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x4_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x16_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x22_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x39_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x4_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x16_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x4_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x8_x4.gds } /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.gds +@file(par.tcl) 183: write_stream -mode ALL -map_file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7PDK_r1p5.tar.bz2/asap7PDK_r1p5/cdslib/asap7_TechLib/asap7_fromAPR.layermap -uniquify_cell_names -merge { /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_R.gds /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_L.gds /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_SL.gds /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_SRAM.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW1024x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x46_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x48_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x128_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x46_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x48_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW32x50_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x128_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x128_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x34_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x16_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x4_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x16_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x4_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x16_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x22_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x39_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x4_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x8_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x16_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x32_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x4_x4.gds /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x8_x4.gds } /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.gds +Finding the highest version number among the merge files +Merge file: /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_R.gds has version number: 600 +Merge file: /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_L.gds has version number: 600 +Merge file: /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_SL.gds has version number: 600 +Merge file: /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_SRAM.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW1024x8_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x46_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x48_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x8_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x128_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x32_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x46_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x48_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x8_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW32x50_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x128_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x32_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x8_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x128_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x32_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x34_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x8_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x16_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x32_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x4_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x8_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x16_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x32_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x4_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x8_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x16_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x22_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x32_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x39_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x4_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x8_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x16_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x32_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x4_x4.gds has version number: 600 +Merge file: /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x8_x4.gds has version number: 600 + +Parse map file... +Writing GDSII file ... + ****** db unit per micron = 4000 ****** + ****** output gds2 file unit per micron = 4000 ****** + ****** unit scaling factor = 1 ****** +Output for instance +Output for bump +Output for physical terminals +Output for logical terminals +Output for regular nets +Output for special nets and metal fills +Output for via structure generation +Statistics for GDS generated (version 600) +---------------------------------------- +Stream Out Layer Mapping Information: +GDS Layer Number GDS Layer Name +---------------------------------------- + 101 COMP + 235 DIEAREA + 18 V0 + 19 M1 + 21 V1 + 20 M2 + 25 V2 + 30 M3 + 35 V3 + 40 M4 + 45 V4 + 50 M5 + 55 V5 + 60 M6 + 65 V6 + 70 M7 + 75 V7 + 80 M8 + 85 V8 + 90 M9 + 95 V9 + 19 M1 + 20 M2 + 30 M3 + 40 M4 + 50 M5 + 60 M6 + 70 M7 + 80 M8 + 90 M9 + 95 Pad + + +Stream Out Information Processed for GDS version 600: +Units: 4000 DBU + +Object Count +---------------------------------------- +Instances 44590 + +Ports/Pins 1161 + metal layer M1 503 + metal layer M5 200 + metal layer M7 150 + metal layer M9 308 + +Nets 96905 + metal layer M2 48529 + metal layer M3 33122 + metal layer M4 8481 + metal layer M5 4197 + metal layer M6 1825 + metal layer M7 751 + + Via Instances 103628 + +Special Nets 1653 + metal layer M1 858 + metal layer M3 121 + metal layer M4 171 + metal layer M5 66 + metal layer M6 56 + metal layer M7 50 + metal layer M8 177 + metal layer M9 154 + + Via Instances 47464 + +Metal Fills 0 + + Via Instances 0 + +Metal FillOPCs 0 + + Via Instances 0 + +Metal FillDRCs 0 + + Via Instances 0 + +Text 1163 + metal layer M1 505 + metal layer M5 200 + metal layer M7 150 + metal layer M9 308 + + +Blockages 0 + + +Custom Text 0 + + +Custom Box 0 + +Trim Metal 0 + +Merging with GDS libraries +Scanning GDS file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_R.gds to register cell name ...... +Scanning GDS file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_L.gds to register cell name ...... +Scanning GDS file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_SL.gds to register cell name ...... +Scanning GDS file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_SRAM.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW1024x8_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x46_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x48_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW128x8_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x128_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x32_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x46_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x48_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW256x8_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW32x50_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x128_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x32_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW512x8_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x128_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x32_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x34_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM1RW64x8_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x16_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x32_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x4_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW128x8_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x16_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x32_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x4_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW16x8_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x16_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x22_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x32_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x39_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x4_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW32x8_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x16_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x32_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x4_x4.gds to register cell name ...... +Scanning GDS file /home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x8_x4.gds to register cell name ...... +Merging GDS file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/asap7sc7p5t_24_R.gds ...... + ****** Merge file: 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/home/ff/eecs151/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/gds/SRAM2RW64x8_x4.gds has units: 1000 per micron. + ****** unit scaling factor = 4 ****** +######Streamout is finished! +@file(par.tcl) 184: puts "write_sdf /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.par.sdf" +write_sdf /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.par.sdf +@file(par.tcl) 185: write_sdf /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.par.sdf +**WARN: (SDF-808): The software is currently operating in a high performance mode which optimizes the handling of multiple timing arcs between input and output pin pairs. With the current settings, the SDF file generated will contain the same delay information for all of these arcs. To have the SDF recalculated with explicit pin pair data, you should use the option '-recompute_delay_calc'. This setting is recommended for generating SDF for functional simulation applications. +Starting SI iteration 1 using Infinite Timing Windows +Begin IPO call back ... +End IPO call back ... +################################################################################# +# Design Stage: PostRoute +# Design Name: riscv_top +# Design Mode: 7nm +# Analysis Mode: MMMC OCV +# Parasitics Mode: SPEF/RCDB +# Signoff Settings: SI On +################################################################################# +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=2297.95) +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 91.9 percent of the nets selected for SI analysis +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 91.9 percent of the nets selected for SI analysis +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 91.9 percent of the nets selected for SI analysis +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 91.9 percent of the nets selected for SI analysis +End delay calculation. (MEM=2524.14 CPU=0:00:16.7 REAL=0:00:05.0) +End delay calculation (fullDC). (MEM=2524.14 CPU=0:00:17.6 REAL=0:00:06.0) +Loading CTE timing window with TwFlowType 0...(CPU = 0:00:00.0, REAL = 0:00:00.0, MEM = 2524.1M) +Add other clocks and setupCteToAAEClockMapping during iter 1 +Loading CTE timing window is completed (CPU = 0:00:00.2, REAL = 0:00:01.0, MEM = 2524.1M) +Starting SI iteration 2 +Calculate early delays in OCV mode... +Calculate late delays in OCV mode... +Calculate late delays in OCV mode... +Calculate early delays in OCV mode... +Start delay calculation (fullDC) (4 T). (MEM=2327.86) +Glitch Analysis: View PVT_0P63V_100C.setup_view -- Total Number of Nets Skipped = 0. +Glitch Analysis: View PVT_0P63V_100C.setup_view -- Total Number of Nets Analyzed = 0. +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 4.3 percent of the nets selected for SI analysis +Glitch Analysis: View PVT_0P77V_0C.hold_view -- Total Number of Nets Skipped = 0. +Glitch Analysis: View PVT_0P77V_0C.hold_view -- Total Number of Nets Analyzed = 0. +Total number of fetched objects 12532 +AAE_INFO: Total number of nets for which stage creation was skipped for all views 0 +AAE_INFO-618: Total number of nets in the design is 13467, 6.9 percent of the nets selected for SI analysis +End delay calculation. (MEM=2524.79 CPU=0:00:02.8 REAL=0:00:01.0) +End delay calculation (fullDC). (MEM=2524.79 CPU=0:00:02.9 REAL=0:00:01.0) +@file(par.tcl) 186: puts "set_db extract_rc_coupled true" +set_db extract_rc_coupled true +@file(par.tcl) 187: set_db extract_rc_coupled true +**WARN: (IMPEXT-3493): The design extraction status has been reset by set_analysis_view/update_rc_corner or set_db command. The parasitic data can be regenerated either by extracting the design using the extract_rc command or by loading the SPEF or RCDB file(s). To prevent resetting of the extraction status, avoid changing extraction modes. +Type 'man IMPEXT-3493' for more detail. +@file(par.tcl) 188: puts "extract_rc" +extract_rc +@file(par.tcl) 189: extract_rc +#WARNING (NRDB-976) The TRACK STEP 0.3840 for preferred direction tracks is smaller than the PITCH 8.1600 for LAYER Pad. This will cause routability problems for NanoRoute. +#Start routing data preparation on Mon Dec 14 22:07:42 2020 +# +#Minimum voltage of a net in the design = 0.000. +#Maximum voltage of a net in the design = 0.770. +#Voltage range [0.000 - 0.000] has 1 net. +#Voltage range [0.630 - 0.630] has 1 net. +#Voltage range [0.000 - 0.630] has 12335 nets. +#Voltage range [0.000 - 0.770] has 1130 nets. +# M1 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M2 H Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M3 V Track-Pitch = 0.14400 Line-2-Via Pitch = 0.14400 +# M4 H Track-Pitch = 0.19200 Line-2-Via Pitch = 0.19200 +# M5 V Track-Pitch = 0.21600 Line-2-Via Pitch = 0.19200 +# M6 H Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M7 V Track-Pitch = 0.28800 Line-2-Via Pitch = 0.41600 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +# M8 H Track-Pitch = 0.38400 Line-2-Via Pitch = 0.32000 +# M9 V Track-Pitch = 0.36000 Line-2-Via Pitch = 0.32000 +# Pad H Track-Pitch = 0.38400 Line-2-Via Pitch = 8.28000 +#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch. +#Regenerating Ggrids automatically. +#Auto generating G-grids with size=15 tracks, using layer M3's pitch = 0.14400. +#Using automatically generated G-grids. +#Done routing data preparation. +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1620.39 (MB), peak = 2053.06 (MB) +#Extract in post route mode +# +#Start tQuantus RC extraction... +#Start building rc corner(s)... +#Number of RC Corner = 2 +#Corner PVT_0P77V_0C.hold_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 (real) +#Corner PVT_0P63V_100C.setup_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 (real) +#LISD -> M1 (1) +#M1 -> M2 (2) +#M2 -> M3 (3) +#M3 -> M4 (4) +#M4 -> M5 (5) +#M5 -> M6 (6) +#M6 -> M7 (7) +#M7 -> M8 (8) +#M8 -> M9 (9) +#M9 -> Pad (10) +#SADV_On +# Corner(s) : +#PVT_0P77V_0C.hold_rc [ 0.00] +#PVT_0P63V_100C.setup_rc [100.00] +# Corner id: 0 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 0.000000 +# Ref. Temp : 25.000000 +# Corner id: 1 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 100.000000 +# Ref. Temp : 25.000000 +#SADV_Off +# +#layer[1] tech width 288 != ict width 400.0 +# +#layer[1] tech spc 288 != ict spc 464.0 +# +#layer[4] tech width 384 != ict width 288.0 +# +#layer[4] tech spc 384 != ict spc 288.0 +# +#layer[6] tech width 512 != ict width 384.0 +# +#layer[6] tech spc 512 != ict spc 384.0 +# +#layer[8] tech width 640 != ict width 512.0 +# +#layer[8] tech spc 640 != ict spc 512.0 +# +#layer[10] tech spc 32000 != ict spc 640.0 +#total pattern=220 [20, 605] +#Reading previously stored rc_model file ( rc_model.bin ) ... +#found CAPMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 +#number model r/c [2,1] [20,605] read +#0 rcmodel(s) requires rebuild +#Build RC corners: cpu time = 00:00:01, elapsed time = 00:00:02, memory = 1651.88 (MB), peak = 2053.06 (MB) +#Start building rc corner(s)... +#Number of RC Corner = 2 +#Corner PVT_0P77V_0C.hold_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 (real) +#Corner PVT_0P63V_100C.setup_rc /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 (real) +#LISD -> M1 (1) +#M1 -> M2 (2) +#M2 -> M3 (3) +#M3 -> M4 (4) +#M4 -> M5 (5) +#M5 -> M6 (6) +#M6 -> M7 (7) +#M7 -> M8 (8) +#M8 -> M9 (9) +#M9 -> Pad (10) +#SADV_On +# Corner(s) : +#PVT_0P77V_0C.hold_rc [ 0.00] +#PVT_0P63V_100C.setup_rc [100.00] +# Corner id: 0 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 0.000000 +# Ref. Temp : 25.000000 +# Corner id: 1 +# Layout Scale: 1.000000 +# Has Metal Fill model: yes +# Temperature was set +# Temperature : 100.000000 +# Ref. Temp : 25.000000 +#SADV_Off +# +#layer[1] tech width 288 != ict width 400.0 +# +#layer[1] tech spc 288 != ict spc 464.0 +# +#layer[4] tech width 384 != ict width 288.0 +# +#layer[4] tech spc 384 != ict spc 288.0 +# +#layer[6] tech width 512 != ict width 384.0 +# +#layer[6] tech spc 512 != ict spc 384.0 +# +#layer[8] tech width 640 != ict width 512.0 +# +#layer[8] tech spc 640 != ict spc 512.0 +# +#layer[10] tech spc 32000 != ict spc 640.0 +#total pattern=220 [20, 605] +#Reading previously stored rc_model file ( rc_model.bin ) ... +#found CAPMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 0.000000 +#found RESMODEL /home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/qrc/qrcTechFile_typ03_scaled4xV06 100.000000 +#number model r/c [2,1] [20,605] read +#0 rcmodel(s) requires rebuild +#Build RC corners: cpu time = 00:00:01, elapsed time = 00:00:02, memory = 1661.71 (MB), peak = 2053.06 (MB) +#Using multithreading with 4 threads. +#Length limit = 200 pitches +#opt mode = 2 +#Start routing data preparation on Mon Dec 14 22:07:49 2020 +# +#Minimum voltage of a net in the design = 0.000. +#Maximum voltage of a net in the design = 0.770. +#Voltage range [0.000 - 0.630] has 12335 nets. +#Voltage range [0.000 - 0.770] has 1130 nets. +#Voltage range [0.630 - 0.630] has 1 net. +#Voltage range [0.000 - 0.000] has 1 net. +#Regenerating Ggrids automatically. +#Auto generating G-grids with size=15 tracks, using layer M3's pitch = 0.14400. +#Using automatically generated G-grids. +#Done routing data preparation. +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1644.66 (MB), peak = 2053.06 (MB) +#Start routing data preparation on Mon Dec 14 22:07:49 2020 +# +#Minimum voltage of a net in the design = 0.000. +#Maximum voltage of a net in the design = 0.770. +#Voltage range [0.000 - 0.630] has 12335 nets. +#Voltage range [0.000 - 0.770] has 1130 nets. +#Voltage range [0.630 - 0.630] has 1 net. +#Voltage range [0.000 - 0.000] has 1 net. +#Regenerating Ggrids automatically. +#Auto generating G-grids with size=15 tracks, using layer M3's pitch = 0.14400. +#Using automatically generated G-grids. +#Done routing data preparation. +#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1644.66 (MB), peak = 2053.06 (MB) +#Start generate extraction boxes. +# +#Extract using 30 x 30 Hboxes +#7x8 initial hboxes +#Use area based hbox pruning. +#0/0 hboxes pruned. +#Complete generating extraction boxes. +#Extract 34 hboxes with 4 threads on machine with Core_i5 3.30GHz 3072KB Cache 4CPU... +#Process 0 special clock nets for rc extraction +#0 temporary NDR added +#Total 12252 nets were built. 2439 nodes added to break long wires. 0 net(s) have incomplete routes. +#Run Statistics for Extraction: +# Cpu time = 00:00:14, elapsed time = 00:00:05 . +# Increased memory = 186.02 (MB), total memory = 1830.68 (MB), peak memory = 2053.06 (MB) +#Simplify RC tree: cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1672.02 (MB), peak = 2053.06 (MB) +#RC Statistics: 68196 Res, 42195 Ground Cap, 2500 XCap (Edge to Edge) +#RC V/H edge ratio: 0.59, Avg V/H Edge Length: 8760.02 (45733), Avg L-Edge Length: 15755.16 (17600) +#Start writing rcdb into /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/nr22257_r2A16u.rcdb.d +2020/12/14 22:07:55 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:55 For more info, please run CheckSysConf in +#Finish writing rcdb with 80479 nodes, 68227 edges, and 5472 xcaps +#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1677.87 (MB), peak = 2053.06 (MB) +Restoring parasitic data from file '/tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/nr22257_r2A16u.rcdb.d' ... +Reading RCDB with compressed RC data. +Reading RCDB with compressed RC data. +Begin read_parasitics... (cpu: 0:00:00.0 real: 0:00:00.0 mem: 2354.582M) +Following multi-corner parasitics specified: + /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/nr22257_r2A16u.rcdb.d (rcdb) +Reading RCDB with compressed RC data. + Cell riscv_top has rcdb /tmp/innovus_temp_22257_c125m-16.EECS.Berkeley.EDU_eecs151-abr_rCI35A/nr22257_r2A16u.rcdb.d specified +Cell riscv_top, hinst +Reading RCDB with compressed RC data. +2020/12/14 22:07:55 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:55 For more info, please run CheckSysConf in +2020/12/14 22:07:56 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:56 For more info, please run CheckSysConf in +Done read_parasitics... (cpu: 0:00:00.2 real: 0:00:01.0 mem: 2330.582M) +# +#Restore RCDB. +# +#Complete tQuantus RC extraction. +#Cpu time = 00:00:22 +#Elapsed time = 00:00:14 +#Increased memory = 51.92 (MB) +#Total memory = 1672.31 (MB) +#Peak memory = 2053.06 (MB) +# +#2439 inserted nodes are removed +@file(par.tcl) 190: puts "write_parasitics -spef_file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.setup.par.spef -rc_corner PVT_0P63V_100C.setup_rc" +write_parasitics -spef_file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.setup.par.spef -rc_corner PVT_0P63V_100C.setup_rc +@file(par.tcl) 191: write_parasitics -spef_file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.setup.par.spef -rc_corner PVT_0P63V_100C.setup_rc +Reading RCDB with compressed RC data. +RC Out has the following PVT Info: + RC:PVT_0P63V_100C.setup_rc +Dumping Spef file..... +Printing D_NET... + rcOut completed:: 9 % rcOut completed:: 19 % rcOut completed:: 29 % rcOut completed:: 39 % rcOut completed:: 49 % rcOut completed:: 59 % rcOut completed:: 69 % rcOut completed:: 79 % rcOut completed:: 89 % rcOut completed:: 100 % +RC Out from RCDB Completed (CPU Time= 0:00:00.3 MEM= 2298.6M) +@file(par.tcl) 192: puts "write_parasitics -spef_file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.hold.par.spef -rc_corner PVT_0P77V_0C.hold_rc" +write_parasitics -spef_file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.hold.par.spef -rc_corner PVT_0P77V_0C.hold_rc +@file(par.tcl) 193: write_parasitics -spef_file /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.hold.par.spef -rc_corner PVT_0P77V_0C.hold_rc +Reading RCDB with compressed RC data. +RC Out has the following PVT Info: + RC:PVT_0P77V_0C.hold_rc +Dumping Spef file..... +Printing D_NET... + rcOut completed:: 9 % rcOut completed:: 19 % rcOut completed:: 29 % rcOut completed:: 39 % rcOut completed:: 49 % rcOut completed:: 59 % rcOut completed:: 69 % rcOut completed:: 79 % rcOut completed:: 89 % rcOut completed:: 100 % +RC Out from RCDB Completed (CPU Time= 0:00:00.3 MEM= 2298.6M) +@file(par.tcl) 194: puts "write_db pre_scale_final_gds" +write_db pre_scale_final_gds +@file(par.tcl) 195: write_db pre_scale_final_gds +#% Begin write_db save design ... (date=12/14 22:07:57, mem=1626.2M) +The in-memory database contained RC information but was not saved. To save +the RC information, use write_db's -rc_extract option. Note: Saving RC information can be quite large, +so it should only be saved when it is really desired. +% Begin Save ccopt configuration ... (date=12/14 22:07:57, mem=1626.2M) +% End Save ccopt configuration ... (date=12/14 22:07:57, total cpu=0:00:00.0, real=0:00:00.0, peak res=1626.5M, current mem=1626.5M) +% Begin Save netlist data ... (date=12/14 22:07:57, mem=1626.5M) +Writing Binary DB to pre_scale_final_gds/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 22:07:57, total cpu=0:00:00.0, real=0:00:00.0, peak res=1631.3M, current mem=1631.3M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file pre_scale_final_gds/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 22:07:57, mem=1631.6M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 22:07:57, total cpu=0:00:00.0, real=0:00:00.0, peak res=1631.6M, current mem=1631.6M) +2020/12/14 22:07:57 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:57 For more info, please run CheckSysConf in +2020/12/14 22:07:57 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:57 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 22:07:57, mem=1673.1M) +% End Save clock tree data ... (date=12/14 22:07:57, total cpu=0:00:00.0, real=0:00:00.0, peak res=1673.1M, current mem=1673.1M) +Saving preference file pre_scale_final_gds/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 22:07:58 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:58 For more info, please run CheckSysConf in +Saving Drc markers ... +2020/12/14 22:07:58 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:58 For more info, please run CheckSysConf in +... 5 markers are saved ... +... 5 geometry drc markers are saved ... +... 0 antenna drc markers are saved ... +% Begin Save routing data ... (date=12/14 22:07:58, mem=1681.0M) +Saving route file ... +2020/12/14 22:07:58 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:58 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.1 real=0:00:00.0 mem=2310.6M) *** +% End Save routing data ... (date=12/14 22:07:58, total cpu=0:00:00.1, real=0:00:00.0, peak res=1682.0M, current mem=1682.0M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 22:07:58 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:07:58 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file pre_scale_final_gds/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=2326.6M) *** +#Saving pin access data to file pre_scale_final_gds/riscv_top.apa ... +# +% Begin Save power constraints data ... (date=12/14 22:07:58, mem=1683.3M) +% End Save power constraints data ... (date=12/14 22:07:58, total cpu=0:00:00.0, real=0:00:00.0, peak res=1683.3M, current mem=1683.3M) +Saving preRoute extracted patterns in file 'pre_scale_final_gds/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.00 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design pre_scale_final_gds +#% End write_db save design ... (date=12/14 22:08:01, total cpu=0:00:02.4, real=0:00:04.0, peak res=1683.3M, current mem=1670.3M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 196: puts "ln -sfn pre_scale_final_gds latest" +ln -sfn pre_scale_final_gds latest +@file(par.tcl) 197: ln -sfn pre_scale_final_gds latest +@file(par.tcl) 200: set fp [open "/home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/gds_scale.py" "w"] +@file(par.tcl) 201: puts -nonewline $fp "#!/usr/bin/python3 + +# Scale the final GDS by a factor of 4 +# This is a tech hook that should be inserted post write_design + +import sys + +try: + import gdspy + print('Scaling down place & routed GDS') +except ImportError: + print('Check your gdspy installation!') + sys.exit() + +# load the standard cell list from the gds folder and lop off '_SL' from end +cell_list = \[line.strip()\[:-3\] for line in open('/home/cc/eecs151/fa20/class/eecs151-abr/project/build/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/cell_list.txt', 'r')\] + +# Need to remove blk layer from any macros, else LVS rule deck interprets it as a polygon +blockage_datatype = 4 + +# load original_gds +gds_lib = gdspy.GdsLibrary().read_gds(infile='/home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.gds', units='import') +# Iterate through cells that aren't part of standard cell library and scale +for k,v in gds_lib.cell_dict.items(): + if not any(cell in k for cell in cell_list): + print('Scaling down ' + k) + + # Need to remove 'blk' layer from any macros, else LVS rule deck interprets it as a polygon + # This has a layer datatype of 4 + # Then scale down the polygon + v.polygons = \[poly.scale(0.25) for poly in v.polygons if not 4 in poly.datatypes\] + + # Scale paths + for path in v.paths: + path.scale(0.25) + # gdspy bug: we also need to scale custom path extensions + # Will be fixed by gdspy/pull#101 in next release + for i, end in enumerate(path.ends): + if isinstance(end, tuple): + path.ends\[i\] = tuple(\[e*0.25 for e in end\]) + + # Scale and move labels + for label in v.labels: + # Bug fix for some EDA tools that didn't set MAG field in gds file + # Maybe this is expected behavior in ASAP7 PDK + # In gdspy/__init__.py: `kwargs\['magnification'\] = record\[1\]\[0\]` + label.magnification = 0.25 + label.translate(-label.position\[0\]*0.75, -label.position\[1\]*0.75) + + # Scale and move references + for ref in v.references: + ref.magnification = 0.25 + ref.translate(-ref.origin\[0\]*0.75, -ref.origin\[1\]*0.75) + ref.magnification = 1 + +# Overwrite original GDS file +gds_lib.write_gds('/home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.gds') + " +@file(par.tcl) 259: close $fp +@file(par.tcl) 262: set env(LD_LIBRARY_PATH) [join [lsearch -not -all -inline [split $env(LD_LIBRARY_PATH) ":"] "*INNOVUS*"] ":"] +@file(par.tcl) 263: python3 /home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/gds_scale.py +/home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/gds_scale.py:22: UserWarning: [GDSPY] Record type BOX (2D) is not supported. + gds_lib = gdspy.GdsLibrary().read_gds(infile='/home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.gds', units='import') +/home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/gds_scale.py:22: UserWarning: [GDSPY] Record type BOXTYPE (2E) is not supported. + gds_lib = gdspy.GdsLibrary().read_gds(infile='/home/cc/eecs151/fa20/class/eecs151-abr/project/build/par-rundir/riscv_top.gds', units='import') +Scaling down place & routed GDS +Scaling down riscv_top +Scaling down VIA23 +Scaling down VIA12 +Scaling down VIA34 +Scaling down VIA45 +Scaling down VIA56 +Scaling down VIA67 +Scaling down riscv_top_VIA0 +Scaling down riscv_top_VIA1 +Scaling down riscv_top_VIA2 +Scaling down riscv_top_VIA3 +Scaling down riscv_top_VIA4 +Scaling down riscv_top_VIA5 +Scaling down riscv_top_VIA6 +Scaling down riscv_top_VIA7 +Scaling down riscv_top_VIA8 +Scaling down riscv_top_VIA9 +Scaling down riscv_top_VIA10 +Scaling down riscv_top_VIA11 +Scaling down riscv_top_VIA12 +Scaling down SRAM1RW64x128 +Scaling down SRAM2RW16x32 +@file(par.tcl) 265: puts "write_db post_scale_final_gds" +write_db post_scale_final_gds +@file(par.tcl) 266: write_db post_scale_final_gds +#% Begin write_db save design ... (date=12/14 22:08:37, mem=1670.3M) +The in-memory database contained RC information but was not saved. To save +the RC information, use write_db's -rc_extract option. Note: Saving RC information can be quite large, +so it should only be saved when it is really desired. +% Begin Save ccopt configuration ... (date=12/14 22:08:37, mem=1670.3M) +% End Save ccopt configuration ... (date=12/14 22:08:37, total cpu=0:00:00.1, real=0:00:00.0, peak res=1670.4M, current mem=1670.4M) +% Begin Save netlist data ... (date=12/14 22:08:37, mem=1670.4M) +Writing Binary DB to post_scale_final_gds/riscv_top.v.bin in multi-threaded mode... +% End Save netlist data ... (date=12/14 22:08:37, total cpu=0:00:00.1, real=0:00:00.0, peak res=1675.2M, current mem=1675.2M) +Saving symbol-table file in separate thread ... +Saving congestion map file in separate thread ... +Saving congestion map file post_scale_final_gds/riscv_top.route.congmap.gz ... +% Begin Save AAE data ... (date=12/14 22:08:37, mem=1675.2M) +Saving AAE Data ... +% End Save AAE data ... (date=12/14 22:08:37, total cpu=0:00:00.0, real=0:00:00.0, peak res=1675.2M, current mem=1675.2M) +2020/12/14 22:08:37 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:08:37 For more info, please run CheckSysConf in +2020/12/14 22:08:37 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:08:37 For more info, please run CheckSysConf in +% Begin Save clock tree data ... (date=12/14 22:08:37, mem=1675.2M) +% End Save clock tree data ... (date=12/14 22:08:37, total cpu=0:00:00.0, real=0:00:00.0, peak res=1675.2M, current mem=1675.2M) +Saving preference file post_scale_final_gds/gui.pref.tcl ... +Saving mode setting ... +Saving root attributes to be loaded post write_db ... +Saving global file ... +Saving root attributes to be loaded previous write_db ... +2020/12/14 22:08:38 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:08:38 For more info, please run CheckSysConf in +Saving Drc markers ... +2020/12/14 22:08:38 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:08:38 For more info, please run CheckSysConf in +... 5 markers are saved ... +... 5 geometry drc markers are saved ... +... 0 antenna drc markers are saved ... +% Begin Save routing data ... (date=12/14 22:08:38, mem=1682.2M) +Saving route file ... +2020/12/14 22:08:38 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:08:38 For more info, please run CheckSysConf in +*** Completed saveRoute (cpu=0:00:00.1 real=0:00:00.0 mem=2329.6M) *** +% End Save routing data ... (date=12/14 22:08:38, total cpu=0:00:00.2, real=0:00:00.0, peak res=1683.2M, current mem=1683.2M) +Saving floorplan file in separate thread ... +Saving PG Conn file in separate thread ... +Saving placement file in separate thread ... +** Saving stdCellPlacement_binary (version# 2) ... +2020/12/14 22:08:38 WARNING This OS does not appear to be a Cadence supported Linux configuration. +2020/12/14 22:08:38 For more info, please run CheckSysConf in +TAT_INFO: ::saveFPlan REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0. +TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0. +Saving property file post_scale_final_gds/riscv_top.prop +*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=2345.6M) *** +#Saving pin access data to file post_scale_final_gds/riscv_top.apa ... +# +% Begin Save power constraints data ... (date=12/14 22:08:38, mem=1685.2M) +% End Save power constraints data ... (date=12/14 22:08:38, total cpu=0:00:00.0, real=0:00:00.0, peak res=1685.2M, current mem=1685.2M) +Saving preRoute extracted patterns in file 'post_scale_final_gds/riscv_top.techData.gz' ... +Saving preRoute extraction data in directory 'extraction' ... +Saving CPF database ... +*** End saving CPF database: cpu=0:00:00.00 real=0:00:00.00 *** +PVT_0P77V_0C.hold_rc PVT_0P63V_100C.setup_rc +Generated self-contained design post_scale_final_gds +#% End write_db save design ... (date=12/14 22:08:41, total cpu=0:00:02.3, real=0:00:04.0, peak res=1685.2M, current mem=1671.5M) +*** Message Summary: 0 warning(s), 0 error(s) + +@file(par.tcl) 267: puts "ln -sfn post_scale_final_gds latest" +ln -sfn post_scale_final_gds latest +@file(par.tcl) 268: ln -sfn post_scale_final_gds latest +@file(par.tcl) 269: puts "exit" +exit +@file(par.tcl) 270: exit + +-------------------------------------------------------------------------------- +Exiting Innovus on Mon Dec 14 22:08:41 2020 + Total CPU time: 0:30:43 + Total real time: 0:20:10 + Peak memory (main): 2045.38MB + + +*** Memory Usage v#1 (Current mem = 2327.629M, initial mem = 267.492M) *** +*** Message Summary: 6550 warning(s), 1967 error(s) + +--- Ending "Innovus" (totcpu=0:29:28, real=0:20:09, mem=2327.6M) --- diff --git a/build/par-rundir/timingReports/riscv_top_postRoute.SI_Glitches.rpt b/build/par-rundir/timingReports/riscv_top_postRoute.SI_Glitches.rpt new file mode 100644 index 0000000..47ce40a --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute.SI_Glitches.rpt @@ -0,0 +1,4 @@ +NetName vlPeak vlView vhPeak vhView +# + +Total number of glitch violations: 0 diff --git a/build/par-rundir/timingReports/riscv_top_postRoute.cap b/build/par-rundir/timingReports/riscv_top_postRoute.cap new file mode 100644 index 0000000..e6e8f13 --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute.cap @@ -0,0 +1,11 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:15 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### +# Net / InstPin MaxCap Cap CapSlack CellPort Remark +# + +*info: there is 0 max_cap violation in the design. diff --git a/build/par-rundir/timingReports/riscv_top_postRoute.fanout b/build/par-rundir/timingReports/riscv_top_postRoute.fanout new file mode 100644 index 0000000..7f547f7 --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute.fanout @@ -0,0 +1,11 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:15 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### +# Net / InstPin MaxFanLoad FanLoad FanLoadSlk CellPort Remark +# + +*info: there is 0 max fanout load violation in the design. diff --git a/build/par-rundir/timingReports/riscv_top_postRoute.length b/build/par-rundir/timingReports/riscv_top_postRoute.length new file mode 100644 index 0000000..5de8a0d --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute.length @@ -0,0 +1,7 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:15 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### diff --git a/build/par-rundir/timingReports/riscv_top_postRoute.summary b/build/par-rundir/timingReports/riscv_top_postRoute.summary new file mode 100644 index 0000000..6c8a03e --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute.summary @@ -0,0 +1,36 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:08 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### + +------------------------------------------------------------ + opt_design Final SI Timing Summary +------------------------------------------------------------ + ++--------------------+---------+---------+---------+---------+ +| Setup mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| 0.002 | 0.002 | 0.004 | 0.129 | +| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | +| Violating Paths:| 0 | 0 | 0 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 0 (0) | 0.000 | 0 (0) | +| max_tran | 0 (0) | 0.000 | 0 (0) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 23.427% + (99.999% with Fillers) +Total number of glitch violations: 0 +------------------------------------------------------------ diff --git a/build/par-rundir/timingReports/riscv_top_postRoute.tran b/build/par-rundir/timingReports/riscv_top_postRoute.tran new file mode 100644 index 0000000..72a8ee5 --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute.tran @@ -0,0 +1,11 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:15 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### +# Net / InstPin MaxTranTime TranTime TranSlack CellPort Remark +# + +*info: there is 0 max_tran violation in the design. diff --git a/build/par-rundir/timingReports/riscv_top_postRoute_all.tarpt b/build/par-rundir/timingReports/riscv_top_postRoute_all.tarpt new file mode 100644 index 0000000..3bc9015 --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute_all.tarpt @@ -0,0 +1,7254 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:15 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### +Path 1: MET (1.791 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 126.000 (P) 160.200 (P) + Arrival:= 887.000 21.200 + + Setup:- 3.310 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 783.690 + Launch Clock:= 21.200 + Data Path:+ 760.700 + Slack:= 1.791 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.800 | 17.200 | 705.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1504/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 1 | 12.300 | 15.900 | 721.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_238 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1503/Y | | B->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 10.300 | 12.500 | 733.900 | + | cpu/stage2/alu/n_322 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5521/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 4 | 17.000 | 23.100 | 757.000 | + | dcache_addr[31] | | | F | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g420__5477/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 22.700 | 7.700 | 764.700 | + | cpu/s2_to_s3_alu/n_31 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC3942_n_31/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 47.500 | 17.200 | 781.900 | + | cpu/s2_to_s3_alu/FE_PHN3942_n_31 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[31]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 13.200 | 0.100 | 781.900 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 40.200 | 887.000 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 62.800 | 9.300 | 887.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 2: MET (3.298 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/register_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 126.300 (P) 160.200 (P) + Arrival:= 887.300 21.200 + + Setup:- 3.302 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 783.998 + Launch Clock:= 21.200 + Data Path:+ 759.500 + Slack:= 3.298 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.800 | 17.200 | 705.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1505/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 12.300 | 14.100 | 719.600 | + | cpu/stage2/alu/n_321 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5504/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 1 | 18.500 | 20.100 | 739.700 | + | cpu/FE_RN_3 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2795_dcache_addr_30/Y | | A->Y | F | BUFx24_ASAP7_75t_SL | 4 | 20.600 | 18.900 | 758.600 | + | dcache_addr[30] | | | F | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g434__7098/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 7.600 | 5.600 | 764.200 | + | cpu/s2_to_s3_alu/n_17 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2849_n_17/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 48.000 | 16.500 | 780.700 | + | cpu/s2_to_s3_alu/FE_PHN2849_n_17 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[30]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 12.000 | 0.000 | 780.700 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 40.500 | 887.300 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[30]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 62.800 | 9.600 | 887.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 3: MET (3.967 ps) Clock Gating Setup Check with Pin mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 106.800 (P) 160.200 (P) + Arrival:= 867.800 21.200 + + Clock Gating Setup:- 65.333 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 702.467 + Launch Clock:= 21.200 + Data Path:+ 677.300 + Slack:= 3.967 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.300 | 179.500 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2349/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.500 | 192.000 | + | cpu/stage3/ldselmux/n_97 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2313/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 23.800 | 17.900 | 209.900 | + | cpu/stage3/wb_dmem[5] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1109/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 51.100 | 17.800 | 227.700 | + | cpu/wb_data[5] | | | R | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g550/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 5 | 19.800 | 23.100 | 250.800 | + | cpu/stage2/stage2_rs1_data[5] | | | R | (net) | 5 | | | | + | cpu/stage2/aselmux/g549/Y | | A1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 30.400 | 17.400 | 268.200 | + | cpu/stage2/stage2_alu_in1[5] | | | R | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC821_stage2_alu_in1_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 14.800 | 9.100 | 277.300 | + | cpu/stage2/alu/FE_DBTN72_stage2_alu_in1_5 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC823_stage2_alu_in1_5/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 9 | 13.500 | 34.700 | 312.000 | + | cpu/stage2/alu/FE_OFN957_stage2_alu_in1_5 | | | R | (net) | 9 | | | | + | cpu/stage2/alu/FE_OFC825_stage2_alu_in1_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 5 | 71.900 | 19.400 | 331.400 | + | cpu/stage2/alu/FE_OFN959_stage2_alu_in1_5 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/lt_30_22_g1493/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 4 | 35.800 | 20.700 | 352.100 | + | cpu/stage2/alu/lt_30_22_n_37 | | | F | (net) | 4 | | | | + | cpu/stage2/alu/lt_29_31_g1466/Y | | A1->Y | R | OAI32xp33_ASAP7_75t_SL | 1 | 12.400 | 14.200 | 366.300 | + | cpu/stage2/alu/lt_29_31_n_63 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1465/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 55.100 | 6.700 | 373.000 | + | cpu/stage2/alu/lt_29_31_n_64 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1451/Y | | C1->Y | R | OAI322xp33_ASAP7_75t_SL | 1 | 18.400 | 16.000 | 389.000 | + | cpu/stage2/alu/lt_29_31_n_78 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1444/Y | | B->Y | F | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 46.900 | 17.300 | 406.300 | + | cpu/stage2/alu/lt_29_31_n_85 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1443/Y | | A1->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 35.500 | 32.200 | 438.500 | + | cpu/stage2/alu/lt_29_31_n_86 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1442/Y | | A1->Y | F | AOI321xp33_ASAP7_75t_SL | 1 | 67.200 | 36.700 | 475.200 | + | cpu/stage2/alu/n_324 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5667/Y | | B1->Y | R | AOI33xp33_ASAP7_75t_SL | 1 | 68.000 | 30.300 | 505.500 | + | cpu/stage2/alu/n_54 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5520/Y | | A2->Y | F | OAI211xp5_ASAP7_75t_SL | 1 | 53.400 | 19.300 | 524.800 | + | cpu/stage2/alu/n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5502/Y | | C->Y | F | AO221x2_ASAP7_75t_SL | 9 | 43.500 | 52.300 | 577.100 | + | cpu/stage2_alu_out[0] | | | F | (net) | 9 | | | | + | cpu/stage3/memrw/g432/Y | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 56.900 | 16.900 | 594.000 | + | cpu/stage3/memrw/n_6 | | | R | (net) | 2 | | | | + | cpu/stage3/memrw/g425/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 3 | 31.900 | 19.900 | 613.900 | + | dcache_we[1] | | | F | (net) | 3 | | | | + | mem/dcache/g13997/Y | | B->Y | R | NOR4xp25_ASAP7_75t_SL | 1 | 42.400 | 28.500 | 642.400 | + | mem/dcache/n_119 | | | R | (net) | 1 | | | | + | mem/dcache/FE_OFC480_n_119/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 54.100 | 21.200 | 663.600 | + | mem/dcache/n_321 | | | F | (net) | 3 | | | | + | mem/dcache/FE_OFC481_n_119/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 37.600 | 9.300 | 672.900 | + | mem/dcache/FE_OFN727_n_119 | | | R | (net) | 1 | | | | + | mem/dcache/g13731/Y | | A1->Y | F | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 15.500 | 12.000 | 684.900 | + | mem/dcache/n_195 | | | F | (net) | 1 | | | | + | mem/dcache/g13600/Y | | A1->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 30.900 | 13.600 | 698.500 | + | mem/dcache/n_323 | | | R | (net) | 1 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | ENA | R | ICGx1_ASAP7_75t_SRAM | 1 | 27.100 | 0.100 | 698.500 | + | ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 42.100 | 867.800 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 39.600 | 2.600 | 867.800 | + | CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 4: MET (4.910 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[28]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 124.100 (P) 160.200 (P) + Arrival:= 885.100 21.200 + + Setup:- 6.091 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.009 + Launch Clock:= 21.200 + Data Path:+ 752.900 + Slack:= 4.910 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g400__2398/Y | | B->Y | R | AND2x4_ASAP7_75t_L | 11 | 7.800 | 30.000 | 450.900 | + | cpu/stage1_inst[21] | | | R | (net) | 11 | | | | + | cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 40.400 | 15.500 | 466.400 | + | cpu/stage1/regfile/n_194 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/g80394/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 25.500 | 15.900 | 482.300 | + | cpu/stage1/regfile/n_250 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g79869/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 28.300 | 12.700 | 495.000 | + | cpu/stage1/regfile/n_249 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g79864/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 29 | 20.000 | 72.400 | 567.400 | + | cpu/stage1/regfile/n_271 | | | F | (net) | 29 | | | | + | cpu/stage1/regfile/g79350/Y | | A->Y | R | INVxp67_ASAP7_75t_SL | 1 | 142.300 | 19.900 | 587.300 | + | cpu/stage1/regfile/n_270 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g78482/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 4 | 40.700 | 59.300 | 646.600 | + | cpu/stage1/regfile/n_689 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77761/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 108.600 | 27.400 | 674.000 | + | cpu/stage1/regfile/n_1379 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77278/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 14.400 | 21.300 | 695.300 | + | cpu/stage1/regfile/n_1851 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76888__4733/Y | | C->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 46.200 | 23.900 | 719.200 | + | cpu/stage1/rs2_mux_data[28] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3939_rs2_mux_data_28/ | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 49.600 | 19.100 | 738.300 | + | Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_PHN3939_rs2_mux_data_28 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g546__2346/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 8.100 | 16.500 | 754.800 | + | cpu/stage1_rs2[28] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC2788_stage1_rs2_28/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 12.800 | 12.400 | 767.200 | + | cpu/s1_to_s2_rs2/FE_PHN2788_stage1_rs2_28 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g447__9945/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.800 | 6.900 | 774.100 | + | cpu/s1_to_s2_rs2/n_4 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[28]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 58.900 | 0.100 | 774.100 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 36.400 | 885.100 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[28]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 4.500 | 885.100 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 5: MET (6.967 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[12]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[12]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 125.000 (P) 160.200 (P) + Arrival:= 886.000 21.200 + + Setup:- 5.933 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.067 + Launch Clock:= 21.200 + Data Path:+ 751.900 + Slack:= 6.967 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 30.100 | 502.700 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79855/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 26 | 50.100 | 69.500 | 572.200 | + | cpu/stage1/regfile/n_285 | | | F | (net) | 26 | | | | + | cpu/stage1/regfile/g78523/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 9 | 116.500 | 52.200 | 624.400 | + | cpu/stage1/regfile/n_633 | | | F | (net) | 9 | | | | + | cpu/stage1/regfile/g77606/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 49.900 | 16.700 | 641.100 | + | cpu/stage1/regfile/n_1530 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77064/Y | | A->Y | F | NAND4xp25_ASAP7_75t_SL | 1 | 28.200 | 12.900 | 654.000 | + | cpu/stage1/regfile/n_2045 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77002/Y | | B->Y | R | AOI211xp5_ASAP7_75t_SL | 1 | 32.000 | 19.300 | 673.300 | + | cpu/stage1/regfile/n_2107 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3935_n_2107/Y | | A->Y | R | BUFx4f_ASAP7_75t_SL | 1 | 38.600 | 14.500 | 687.800 | + | cpu/stage1/regfile/FE_PHN3935_n_2107 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76890__9315/Y | | B->Y | F | OAI211xp5_ASAP7_75t_SL | 1 | 7.400 | 39.400 | 727.200 | + | cpu/stage1/rs2_mux_data[12] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g566__1881/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 90.400 | 26.500 | 753.700 | + | cpu/stage1_rs2[12] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3586_stage1_rs2_12/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 14.000 | 12.700 | 766.400 | + | cpu/s1_to_s2_rs2/FE_PHN3586_stage1_rs2_12 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g433__3680/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.800 | 6.700 | 773.100 | + | cpu/s1_to_s2_rs2/n_18 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[12]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 57.400 | 0.000 | 773.100 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.300 | 886.000 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[12]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.600 | 5.400 | 886.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 6: MET (9.117 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[29]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/register_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 126.300 (P) 160.200 (P) + Arrival:= 887.300 21.200 + + Setup:- 1.983 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 785.317 + Launch Clock:= 21.200 + Data Path:+ 755.000 + Slack:= 9.117 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1508/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 11.800 | 14.100 | 702.400 | + | cpu/stage2/alu/n_320 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5506/Y | | A2->Y | F | AO21x1_ASAP7_75t_L | 1 | 18.800 | 24.800 | 727.200 | + | cpu/FE_RN_1 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2794_dcache_addr_29/Y | | A->Y | F | BUFx24_ASAP7_75t_SL | 4 | 23.300 | 19.000 | 746.200 | + | dcache_addr[29] | | | F | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g421__2398/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 6.800 | 6.100 | 752.300 | + | cpu/s2_to_s3_alu/n_30 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2840_n_30/Y | | A->Y | R | HB2xp67_ASAP7_75t_SL | 1 | 50.300 | 23.900 | 776.200 | + | cpu/s2_to_s3_alu/FE_PHN2840_n_30 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[29]/D | | D | R | DFFHQNx1_ASAP7_75t_L | 1 | 13.200 | 0.000 | 776.200 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 40.500 | 887.300 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[29]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 62.800 | 9.600 | 887.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 7: MET (9.139 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 149.000 (P) 160.200 (P) + Arrival:= 910.000 21.200 + + Setup:- 4.761 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 805.239 + Launch Clock:= 21.200 + Data Path:+ 774.900 + Slack:= 9.139 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.800 | 17.200 | 705.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1505/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 12.300 | 14.100 | 719.600 | + | cpu/stage2/alu/n_321 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5504/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 1 | 18.500 | 20.100 | 739.700 | + | cpu/FE_RN_3 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2795_dcache_addr_30/Y | | A->Y | F | BUFx24_ASAP7_75t_SL | 4 | 20.600 | 18.900 | 758.600 | + | dcache_addr[30] | | | F | (net) | 4 | | | | + | cpu/FE_PHC4128_dcache_addr_30/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 7.600 | 13.700 | 772.300 | + | cpu/FE_PHN4128_dcache_addr_30 | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g962__3680/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 10.600 | 15.200 | 787.500 | + | cpu/stage1/stage1_pc_mux_to_pc[30] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g349__8428/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 15.500 | 8.600 | 796.100 | + | cpu/stage1/pcreg/n_31 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[30]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 46.000 | 0.000 | 796.100 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 34.000 | 910.000 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[30]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.200 | 6.900 | 910.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 8: MET (9.350 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[4]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[4]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 123.400 (P) 160.200 (P) + Arrival:= 884.400 21.200 + + Setup:- 3.150 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 781.250 + Launch Clock:= 21.200 + Data Path:+ 750.700 + Slack:= 9.350 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 6 | 7.800 | 24.500 | 445.400 | + | cpu/stage1_inst[20] | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 4 | 31.800 | 30.600 | 476.000 | + | cpu/stage1/regfile/n_237 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 13 | 56.400 | 35.900 | 511.900 | + | cpu/stage1/regfile/n_236 | | | R | (net) | 13 | | | | + | cpu/stage1/regfile/FE_OFC643_n_237/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 59.300 | 5.400 | 517.300 | + | cpu/stage1/regfile/FE_OFN834_n_237 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g79821/Y | | B->Y | R | NOR2xp33_ASAP7_75t_L | 6 | 18.100 | 91.000 | 608.300 | + | cpu/stage1/regfile/n_332 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g77521/Y | | A1->Y | R | AO222x2_ASAP7_75t_SL | 1 | 196.500 | 58.200 | 666.500 | + | cpu/stage1/regfile/n_1615 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77282/Y | | C->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 19.100 | 10.800 | 677.300 | + | cpu/stage1/regfile/n_1847 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3566_n_1847/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 65.300 | 21.300 | 698.600 | + | cpu/stage1/regfile/FE_PHN3566_n_1847 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77107/Y | | A2->Y | F | OA211x2_ASAP7_75t_SL | 1 | 9.000 | 20.800 | 719.400 | + | cpu/stage1/regfile/n_2002 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76955__5107/Y | | B->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 15.300 | 18.400 | 737.800 | + | cpu/stage1/rs2_mux_data[4] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g550__5477/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 46.500 | 20.200 | 758.000 | + | cpu/stage1_rs2[4] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g435__2802/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 11.700 | 13.900 | 771.900 | + | cpu/s1_to_s2_rs2/n_16 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[4]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 83.700 | 0.300 | 771.900 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 35.700 | 884.400 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[4]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.500 | 3.800 | 884.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 9: MET (9.598 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/register_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 120.500 (P) 160.200 (P) + Arrival:= 881.500 21.200 + + Setup:- 3.402 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 778.098 + Launch Clock:= 21.200 + Data Path:+ 747.300 + Slack:= 9.598 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1549/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 1 | 33.200 | 20.100 | 550.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_206 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1547/Y | | B->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 11.000 | 12.600 | 562.700 | + | cpu/stage2/alu/n_306 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5665/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 12.600 | 8.100 | 570.800 | + | cpu/stage2/alu/n_56 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5522/Y | | A->Y | F | NAND3xp33_ASAP7_75t_SL | 2 | 33.300 | 42.000 | 612.800 | + | dcache_addr[15] | | | F | (net) | 2 | | | | + | cpu/FE_PHC2730_dcache_addr_15/Y | | A->Y | F | HB3xp67_ASAP7_75t_SL | 3 | 94.800 | 72.600 | 685.400 | + | cpu/FE_PHN2730_dcache_addr_15 | | | F | (net) | 3 | | | | + | cpu/s2_to_s3_alu/g450__5107/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 63.100 | 18.500 | 703.900 | + | cpu/s2_to_s3_alu/n_1 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2797_n_1/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 57.800 | 64.600 | 768.500 | + | cpu/s2_to_s3_alu/FE_PHN2797_n_1 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[15]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 22.900 | 0.000 | 768.500 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 34.700 | 881.500 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[15]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 60.300 | 3.800 | 881.500 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 10: MET (10.150 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.500 (P) 160.200 (P) + Arrival:= 900.500 21.200 + + Setup:- 3.050 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 797.450 + Launch Clock:= 21.200 + Data Path:+ 766.100 + Slack:= 10.150 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.800 | 17.200 | 705.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1504/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 1 | 12.300 | 15.900 | 721.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_238 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1503/Y | | B->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 10.300 | 12.500 | 733.900 | + | cpu/stage2/alu/n_322 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5521/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 4 | 17.000 | 23.400 | 757.300 | + | dcache_addr[31] | | | F | (net) | 4 | | | | + | cpu/stage3/csr/g178/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 22.700 | 13.200 | 770.500 | + | cpu/stage3/csr/n_17 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2848_n_17/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 53.500 | 16.800 | 787.300 | + | cpu/stage3/csr/FE_PHN2848_n_17 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[31]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 12.000 | 0.000 | 787.300 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 31.100 | 900.500 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.100 | 1.800 | 900.500 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 11: MET (10.609 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[28]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 124.700 (P) 160.800 (P) + Arrival:= 885.700 21.800 + + Setup:- -5.009 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.709 + Launch Clock:= 21.800 + Data Path:+ 758.300 + Slack:= 10.609 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.800 | 21.800 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[3]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 50.100 | 71.900 | + | cpu/stage3_inst[3] | | | R | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OCPC1470_stage3_inst_3/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 2 | 10.500 | 4.600 | 76.500 | + | cpu/stage3/ldsel/FE_OCPN1434_stage3_inst_3 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_RC_26_0/Y | | B->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 6.000 | 5.300 | 81.800 | + | cpu/stage3/ldsel/FE_RN_10_0 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/FE_RC_27_0/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 16.200 | 6.500 | 88.300 | + | cpu/stage3/ldsel/n_10 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g208/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 1 | 9.800 | 7.100 | 95.400 | + | cpu/stage3/ldsel/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g205/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 4 | 16.800 | 17.600 | 113.000 | + | cpu/stage3/LdSelect[0] | | | R | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y | | A->Y | F | INVx3_ASAP7_75t_SL | 1 | 16.000 | 6.300 | 119.300 | + | cpu/stage3/ldselmux/n_14 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 9.300 | 7.400 | 126.700 | + | cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 | | | R | (net) | 5 | | | | + | cpu/stage3/ldselmux/g2426/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 10.600 | 12.600 | 139.300 | + | cpu/stage3/ldselmux/n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/FE_OCPC1515_n_30/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 2 | 8.400 | 11.600 | 150.900 | + | cpu/stage3/ldselmux/FE_OCPN1476_n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/g2399/Y | | A2->Y | F | AOI21x1_ASAP7_75t_SL | 7 | 7.800 | 15.700 | 166.600 | + | cpu/stage3/ldselmux/n_62 | | | F | (net) | 7 | | | | + | cpu/stage3/ldselmux/g2354/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 31.000 | 15.700 | 182.300 | + | cpu/stage3/ldselmux/n_92 | | | R | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | F | OAI221xp5_ASAP7_75t_SL | 1 | 25.100 | 15.700 | 198.000 | + | cpu/stage3/wb_dmem[0] | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | F | AO21x1_ASAP7_75t_SL | 3 | 28.200 | 22.300 | 220.300 | + | cpu/wb_data[0] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 4 | 15.500 | 23.200 | 243.500 | + | cpu/stage2/stage2_rs2_data[0] | | | F | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 18.500 | 10.300 | 253.800 | + | cpu/stage2/bselmux/n_6 | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 2 | 25.000 | 23.800 | 277.600 | + | cpu/stage2/stage2_alu_in2[0] | | | R | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 24 | 28.000 | 16.300 | 293.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | F | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 5 | 29.700 | 29.900 | 323.800 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | F | XNOR2xp5_ASAP7_75t_SL | 2 | 33.500 | 25.800 | 349.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | R | MAJIxp5_ASAP7_75t_SL | 2 | 33.200 | 23.900 | 373.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 44.100 | 19.200 | 392.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 15.700 | 408.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 3 | 13.100 | 16.700 | 425.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | F | OAI311xp33_ASAP7_75t_SL | 1 | 14.900 | 9.900 | 435.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 27.900 | 13.600 | 448.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 20.800 | 16.700 | 465.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 11.900 | 14.500 | 479.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 11.000 | 8.800 | 488.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 16.000 | 20.900 | 509.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | R | AOI31xp67_ASAP7_75t_SL | 3 | 15.700 | 15.200 | 524.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 30.500 | 10.200 | 534.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 32.200 | 26.200 | 561.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 20.400 | 17.700 | 578.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | R | NAND2x1_ASAP7_75t_SL | 2 | 13.200 | 10.700 | 589.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 20.400 | 9.300 | 598.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | R | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 36.500 | 16.100 | 614.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 27.700 | 12.200 | 627.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 19.200 | 19.500 | 646.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 16.700 | 10.700 | 657.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 19.400 | 16.500 | 673.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1511/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 12.600 | 16.900 | 690.700 | + | cpu/stage2/alu/n_319 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5508/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 22.700 | 29.800 | 720.500 | + | dcache_addr[28] | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g447__6417/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 48.000 | 8.000 | 728.500 | + | cpu/s2_to_s3_alu/n_4 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2784_n_4/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 60.400 | 30.400 | 758.900 | + | cpu/s2_to_s3_alu/FE_PHN2784_n_4 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC3581_n_4/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 13.300 | 21.200 | 780.100 | + | cpu/s2_to_s3_alu/FE_PHN3581_n_4 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[28]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 11.600 | 0.100 | 780.100 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 38.900 | 885.700 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[28]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 62.700 | 8.000 | 885.700 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 12: MET (10.978 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[7]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[7]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 123.000 (P) 160.200 (P) + Arrival:= 884.000 21.200 + + Setup:- 6.822 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 777.178 + Launch Clock:= 21.200 + Data Path:+ 745.000 + Slack:= 10.978 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g400__2398/Y | | B->Y | R | AND2x4_ASAP7_75t_L | 11 | 7.800 | 30.000 | 450.900 | + | cpu/stage1_inst[21] | | | R | (net) | 11 | | | | + | cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 40.400 | 15.500 | 466.400 | + | cpu/stage1/regfile/n_194 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/g80394/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 25.500 | 15.900 | 482.300 | + | cpu/stage1/regfile/n_250 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g79869/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 28.300 | 12.700 | 495.000 | + | cpu/stage1/regfile/n_249 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g79864/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 29 | 20.000 | 72.400 | 567.400 | + | cpu/stage1/regfile/n_271 | | | F | (net) | 29 | | | | + | cpu/stage1/regfile/g79350/Y | | A->Y | R | INVxp67_ASAP7_75t_SL | 1 | 142.300 | 19.900 | 587.300 | + | cpu/stage1/regfile/n_270 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g78482/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 4 | 40.700 | 58.700 | 646.000 | + | cpu/stage1/regfile/n_689 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77646/Y | | A2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 108.600 | 19.200 | 665.200 | + | cpu/stage1/regfile/n_1494 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77151/Y | | B->Y | F | NAND3xp33_ASAP7_75t_SL | 1 | 45.800 | 14.100 | 679.300 | + | cpu/stage1/regfile/n_1958 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76907__2802/Y | | B->Y | R | AOI21xp5_ASAP7_75t_SL | 1 | 29.200 | 19.400 | 698.700 | + | cpu/stage1/regfile/n_2169 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76894__1666/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 35.800 | 24.200 | 722.900 | + | cpu/stage1/rs2_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g575__1666/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 53.700 | 21.300 | 744.200 | + | cpu/stage1_rs2[7] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC2790_stage1_rs2_7/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 10.600 | 11.900 | 756.100 | + | cpu/s1_to_s2_rs2/FE_PHN2790_stage1_rs2_7 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g427__5107/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.800 | 10.100 | 766.200 | + | cpu/s1_to_s2_rs2/n_24 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[7]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 65.700 | 0.400 | 766.200 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 35.300 | 884.000 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[7]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.500 | 3.400 | 884.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 13: MET (12.150 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.400 (P) 160.200 (P) + Arrival:= 900.400 21.200 + + Setup:- 3.050 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 797.350 + Launch Clock:= 21.200 + Data Path:+ 764.000 + Slack:= 12.150 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.800 | 17.200 | 705.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1505/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 12.300 | 14.100 | 719.600 | + | cpu/stage2/alu/n_321 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5504/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 1 | 18.500 | 20.100 | 739.700 | + | cpu/FE_RN_3 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2795_dcache_addr_30/Y | | A->Y | F | BUFx24_ASAP7_75t_SL | 4 | 20.600 | 19.100 | 758.800 | + | dcache_addr[30] | | | F | (net) | 4 | | | | + | cpu/stage3/csr/g191/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 7.700 | 9.600 | 768.400 | + | cpu/stage3/csr/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2839_n_4/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 53.000 | 16.800 | 785.200 | + | cpu/stage3/csr/FE_PHN2839_n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[30]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 12.000 | 0.000 | 785.200 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 31.000 | 900.400 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[30]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.100 | 1.700 | 900.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 14: MET (12.262 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[20]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[20]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 124.700 (P) 160.200 (P) + Arrival:= 885.700 21.200 + + Setup:- 6.038 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.662 + Launch Clock:= 21.200 + Data Path:+ 746.200 + Slack:= 12.262 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g400__2398/Y | | B->Y | R | AND2x4_ASAP7_75t_L | 11 | 7.800 | 30.000 | 450.900 | + | cpu/stage1_inst[21] | | | R | (net) | 11 | | | | + | cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 40.400 | 15.500 | 466.400 | + | cpu/stage1/regfile/n_194 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/g80394/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 25.500 | 15.900 | 482.300 | + | cpu/stage1/regfile/n_250 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g79869/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 28.300 | 12.600 | 494.900 | + | cpu/stage1/regfile/n_249 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g79860/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 27 | 20.000 | 77.400 | 572.300 | + | cpu/stage1/regfile/n_277 | | | F | (net) | 27 | | | | + | cpu/stage1/regfile/g79348/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 138.200 | 33.000 | 605.300 | + | cpu/stage1/regfile/n_276 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g78341/Y | | B2->Y | F | OAI22xp5_ASAP7_75t_SL | 1 | 57.200 | 9.000 | 614.300 | + | cpu/stage1/regfile/n_802 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77497/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 23.600 | 17.800 | 632.100 | + | cpu/stage1/regfile/n_1639 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76958__8428/Y | | B->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 60.200 | 20.200 | 652.300 | + | cpu/stage1/regfile/n_2147 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76903__5526/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 46.000 | 13.000 | 665.300 | + | cpu/stage1/regfile/n_2170 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76895__7410/Y | | B->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 24.000 | 54.000 | 719.300 | + | cpu/stage1/rs2_mux_data[20] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g571__9315/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 119.900 | 27.200 | 746.500 | + | cpu/stage1_rs2[20] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3596_stage1_rs2_20/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 13.600 | 13.600 | 760.100 | + | cpu/s1_to_s2_rs2/FE_PHN3596_stage1_rs2_20 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g441__1881/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 8.500 | 7.300 | 767.400 | + | cpu/s1_to_s2_rs2/n_10 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[20]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 58.400 | 0.000 | 767.400 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.000 | 885.700 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[20]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 5.100 | 885.700 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 15: MET (12.957 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[21]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 123.300 (P) 160.200 (P) + Arrival:= 884.300 21.200 + + Setup:- 6.343 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 777.957 + Launch Clock:= 21.200 + Data Path:+ 743.800 + Slack:= 12.957 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 30.100 | 502.700 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/FE_OFC643_n_237/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 50.100 | 9.500 | 512.200 | + | cpu/stage1/regfile/FE_OFN834_n_237 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g79821/Y | | B->Y | F | NOR2xp33_ASAP7_75t_L | 6 | 17.300 | 75.300 | 587.500 | + | cpu/stage1/regfile/n_332 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g78338/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 145.600 | 28.500 | 616.000 | + | cpu/stage1/regfile/n_805 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77346/Y | | B->Y | F | NAND3xp33_ASAP7_75t_SL | 1 | 53.600 | 11.000 | 627.000 | + | cpu/stage1/regfile/n_1783 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77062/Y | | A2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 26.600 | 15.200 | 642.200 | + | cpu/stage1/regfile/n_2047 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3561_n_2047/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 1 | 70.200 | 35.000 | 677.200 | + | cpu/stage1/regfile/FE_PHN3561_n_2047 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76916__4733/Y | | C->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 16.700 | 42.000 | 719.200 | + | cpu/stage1/rs2_mux_data[21] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g569__4733/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 93.900 | 25.500 | 744.700 | + | cpu/stage1_rs2[21] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3591_stage1_rs2_21/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 12.700 | 12.400 | 757.100 | + | cpu/s1_to_s2_rs2/FE_PHN3591_stage1_rs2_21 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g442__5115/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.800 | 7.900 | 765.000 | + | cpu/s1_to_s2_rs2/n_9 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[21]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 61.300 | 0.100 | 765.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 35.600 | 884.300 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[21]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.600 | 3.700 | 884.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 16: MET (13.588 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[25]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[25]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 120.700 (P) 160.200 (P) + Arrival:= 881.700 21.200 + + Setup:- 1.712 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.988 + Launch Clock:= 21.200 + Data Path:+ 745.200 + Slack:= 13.588 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 6 | 7.800 | 24.500 | 445.400 | + | cpu/stage1_inst[20] | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 4 | 31.800 | 30.600 | 476.000 | + | cpu/stage1/regfile/n_237 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 13 | 56.400 | 35.900 | 511.900 | + | cpu/stage1/regfile/n_236 | | | R | (net) | 13 | | | | + | cpu/stage1/regfile/FE_OFC643_n_237/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 59.300 | 5.400 | 517.300 | + | cpu/stage1/regfile/FE_OFN834_n_237 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g79821/Y | | B->Y | R | NOR2xp33_ASAP7_75t_L | 6 | 18.100 | 92.500 | 609.800 | + | cpu/stage1/regfile/n_332 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g77534/Y | | A1->Y | R | AO222x2_ASAP7_75t_SL | 1 | 196.500 | 57.300 | 667.100 | + | cpu/stage1/regfile/n_1602 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77284/Y | | C->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 18.200 | 10.400 | 677.500 | + | cpu/stage1/regfile/n_1845 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77061/Y | | A2->Y | F | OA211x2_ASAP7_75t_SL | 1 | 47.900 | 27.600 | 705.100 | + | cpu/stage1/regfile/n_2048 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76935__2802/Y | | B->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 14.000 | 28.700 | 733.800 | + | cpu/stage1/rs2_mux_data[25] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g547__1666/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 66.800 | 22.600 | 756.400 | + | cpu/stage1_rs2[25] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g430__8428/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 13.700 | 10.000 | 766.400 | + | cpu/s1_to_s2_rs2/n_21 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[25]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 66.700 | 0.400 | 766.400 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 33.000 | 881.700 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[25]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 52.800 | 1.100 | 881.700 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 17: MET (14.437 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[29]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.500 (P) 160.200 (P) + Arrival:= 900.500 21.200 + + Setup:- 3.063 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 797.437 + Launch Clock:= 21.200 + Data Path:+ 761.800 + Slack:= 14.437 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1508/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 11.800 | 14.100 | 702.400 | + | cpu/stage2/alu/n_320 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5506/Y | | A2->Y | F | AO21x1_ASAP7_75t_L | 1 | 18.800 | 24.800 | 727.200 | + | cpu/FE_RN_1 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2794_dcache_addr_29/Y | | A->Y | F | BUFx24_ASAP7_75t_SL | 4 | 23.300 | 19.000 | 746.200 | + | dcache_addr[29] | | | F | (net) | 4 | | | | + | cpu/stage3/csr/g164/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 6.800 | 11.800 | 758.000 | + | cpu/stage3/csr/n_31 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2835_n_31/Y | | A->Y | R | HB2xp67_ASAP7_75t_SL | 1 | 57.700 | 25.000 | 783.000 | + | cpu/stage3/csr/FE_PHN2835_n_31 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[29]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 14.100 | 0.000 | 783.000 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 31.100 | 900.500 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[29]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.100 | 1.800 | 900.500 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 18: MET (14.484 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[9]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 124.900 (P) 160.200 (P) + Arrival:= 885.900 21.200 + + Setup:- 6.416 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.484 + Launch Clock:= 21.200 + Data Path:+ 743.800 + Slack:= 14.484 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g400__2398/Y | | B->Y | R | AND2x4_ASAP7_75t_L | 11 | 7.800 | 30.000 | 450.900 | + | cpu/stage1_inst[21] | | | R | (net) | 11 | | | | + | cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 40.400 | 15.500 | 466.400 | + | cpu/stage1/regfile/n_194 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/g80394/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 25.500 | 15.900 | 482.300 | + | cpu/stage1/regfile/n_250 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g79869/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 28.300 | 12.700 | 495.000 | + | cpu/stage1/regfile/n_249 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g79864/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 29 | 20.000 | 72.400 | 567.400 | + | cpu/stage1/regfile/n_271 | | | F | (net) | 29 | | | | + | cpu/stage1/regfile/g79350/Y | | A->Y | R | INVxp67_ASAP7_75t_SL | 1 | 142.300 | 19.900 | 587.300 | + | cpu/stage1/regfile/n_270 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g78482/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 4 | 40.700 | 59.800 | 647.100 | + | cpu/stage1/regfile/n_689 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77725/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 108.600 | 26.600 | 673.700 | + | cpu/stage1/regfile/n_1415 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77264/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 13.600 | 15.100 | 688.800 | + | cpu/stage1/regfile/n_1865 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76891__9945/Y | | C->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 35.000 | 29.700 | 718.500 | + | cpu/stage1/rs2_mux_data[9] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g572__9945/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 67.600 | 24.800 | 743.300 | + | cpu/stage1_rs2[9] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3585_stage1_rs2_9/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 13.300 | 12.900 | 756.200 | + | cpu/s1_to_s2_rs2/FE_PHN3585_stage1_rs2_9 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g429__4319/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 6.300 | 8.800 | 765.000 | + | cpu/s1_to_s2_rs2/n_22 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[9]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 62.000 | 0.200 | 765.000 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.200 | 885.900 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[9]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.600 | 5.300 | 885.900 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 19: MET (14.899 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[16]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[16]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 122.000 (P) 160.200 (P) + Arrival:= 883.000 21.200 + + Setup:- 6.701 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 776.299 + Launch Clock:= 21.200 + Data Path:+ 740.200 + Slack:= 14.899 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 28.700 | 501.300 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79856/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 27 | 49.900 | 70.000 | 571.300 | + | cpu/stage1/regfile/n_284 | | | F | (net) | 27 | | | | + | cpu/stage1/regfile/g78499/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 111.700 | 45.400 | 616.700 | + | cpu/stage1/regfile/n_667 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g77579/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 42.100 | 20.200 | 636.900 | + | cpu/stage1/regfile/n_1557 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77069/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 54.800 | 21.100 | 658.000 | + | cpu/stage1/regfile/n_2040 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77003/Y | | B->Y | R | AOI211xp5_ASAP7_75t_SL | 1 | 43.200 | 21.600 | 679.600 | + | cpu/stage1/regfile/n_2106 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76905__3680/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 37.700 | 45.100 | 724.700 | + | cpu/stage1/rs2_mux_data[16] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g555__8428/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 96.100 | 25.700 | 750.400 | + | cpu/stage1_rs2[16] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g436__1705/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 12.800 | 11.000 | 761.400 | + | cpu/s1_to_s2_rs2/n_15 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[16]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 64.600 | 0.300 | 761.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 34.300 | 883.000 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[16]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.300 | 2.400 | 883.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 20: MET (16.083 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 125.100 (P) 160.200 (P) + Arrival:= 886.100 21.200 + + Setup:- 6.017 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.083 + Launch Clock:= 21.200 + Data Path:+ 742.800 + Slack:= 16.083 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g393__9945/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 7 | 7.800 | 29.800 | 450.700 | + | cpu/stage1_inst[23] | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g80399/Y | | B->Y | F | NOR2x1_ASAP7_75t_SL | 9 | 43.300 | 44.600 | 495.300 | + | cpu/stage1/regfile/n_242 | | | F | (net) | 9 | | | | + | cpu/stage1/regfile/g79852/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 23 | 78.800 | 72.000 | 567.300 | + | cpu/stage1/regfile/n_289 | | | F | (net) | 23 | | | | + | cpu/stage1/regfile/g78533/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 14 | 107.700 | 60.600 | 627.900 | + | cpu/stage1/regfile/n_619 | | | F | (net) | 14 | | | | + | cpu/stage1/regfile/g77861/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 67.200 | 17.000 | 644.900 | + | cpu/stage1/regfile/n_1278 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77155/Y | | A->Y | F | NAND3xp33_ASAP7_75t_SL | 1 | 28.400 | 10.800 | 655.700 | + | cpu/stage1/regfile/n_1954 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77082/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 25.600 | 19.500 | 675.200 | + | cpu/stage1/regfile/n_2027 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76997__1881/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 46.800 | 21.300 | 696.500 | + | cpu/stage1/regfile/n_2112 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76939__7098/Y | | B->Y | F | AO21x1_ASAP7_75t_SL | 1 | 43.300 | 20.300 | 716.800 | + | cpu/stage1/rs2_mux_data[31] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3943_rs2_mux_data_31/ | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 11.000 | 11.800 | 728.600 | + | Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_PHN3943_rs2_mux_data_31 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g560__2802/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 5.500 | 16.500 | 745.100 | + | cpu/stage1_rs2[31] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC2793_stage1_rs2_31/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 13.000 | 12.400 | 757.500 | + | cpu/s1_to_s2_rs2/FE_PHN2793_stage1_rs2_31 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g420__2883/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.700 | 6.500 | 764.000 | + | cpu/s1_to_s2_rs2/n_31 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[31]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 58.200 | 0.000 | 764.000 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.400 | 886.100 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 5.500 | 886.100 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 21: MET (16.141 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 124.400 (P) 160.200 (P) + Arrival:= 885.400 21.200 + + Setup:- 6.259 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.141 + Launch Clock:= 21.200 + Data Path:+ 741.800 + Slack:= 16.141 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g393__9945/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 7 | 5.800 | 26.700 | 443.200 | + | cpu/stage1_inst[23] | | | F | (net) | 7 | | | | + | cpu/stage1/regfile/g80396/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 33.600 | 41.200 | 484.400 | + | cpu/stage1/regfile/n_247 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79870/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 80.200 | 16.300 | 500.700 | + | cpu/stage1/regfile/n_246 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g79865/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 30 | 34.300 | 92.800 | 593.500 | + | cpu/stage1/regfile/n_269 | | | F | (net) | 30 | | | | + | cpu/stage1/regfile/g78030/Y | | A2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 149.400 | 21.900 | 615.400 | + | cpu/stage1/regfile/n_1109 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77369/Y | | A->Y | R | AND4x1_ASAP7_75t_SL | 1 | 55.000 | 24.400 | 639.800 | + | cpu/stage1/regfile/n_1771 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77051/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 12.900 | 13.000 | 652.800 | + | cpu/stage1/regfile/n_2058 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76973__6161/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 37.900 | 15.800 | 668.600 | + | cpu/stage1/regfile/n_2136 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76953__5477/Y | | B->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 27.700 | 33.000 | 701.600 | + | cpu/stage1/rs2_mux_data[8] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC4119_rs2_mux_data_8/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 74.600 | 22.300 | 723.900 | + | cpu/stage1/data2sel_s1/FE_PHN4119_rs2_mux_data_8 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g573__2883/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 11.100 | 17.800 | 741.700 | + | cpu/stage1_rs2[8] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3595_stage1_rs2_8/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 13.900 | 13.300 | 755.000 | + | cpu/s1_to_s2_rs2/FE_PHN3595_stage1_rs2_8 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g428__6260/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 8.100 | 8.000 | 763.000 | + | cpu/s1_to_s2_rs2/n_23 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[8]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 60.500 | 0.100 | 763.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 36.700 | 885.400 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[8]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.600 | 4.800 | 885.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 22: MET (16.902 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 148.400 (P) 160.200 (P) + Arrival:= 909.400 21.200 + + Setup:- 2.198 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 807.202 + Launch Clock:= 21.200 + Data Path:+ 769.100 + Slack:= 16.902 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.700 | 401.000 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 4 | 17.300 | 20.200 | 421.200 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1209_stage1_inst_15/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 6 | 37.700 | 11.200 | 432.400 | + | cpu/stage1/regfile/FE_OFN1007_stage1_inst_15 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/FE_RC_2_0/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 20.200 | 14.700 | 447.100 | + | cpu/stage1/regfile/FE_RN_0_0 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_RC_3_0/Y | | A->Y | F | INVx6_ASAP7_75t_SL | 5 | 22.500 | 12.500 | 459.600 | + | cpu/stage1/regfile/n_211 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC991_n_211/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 1 | 19.600 | 8.200 | 467.800 | + | cpu/stage1/regfile/FE_OFN1087_n_211 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1195_n_211/Y | | A->Y | F | INVx8_ASAP7_75t_SL | 13 | 12.200 | 10.500 | 478.300 | + | cpu/stage1/regfile/FE_OFN1090_n_211 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79826/Y | | B->Y | F | AND2x6_ASAP7_75t_SL | 7 | 13.200 | 22.500 | 500.800 | + | cpu/stage1/regfile/n_326 | | | F | (net) | 7 | | | | + | cpu/stage1/regfile/g78423/Y | | B->Y | R | NAND2x2_ASAP7_75t_SL | 4 | 19.600 | 15.400 | 516.200 | + | cpu/stage1/regfile/n_788 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77789/Y | | A2->Y | F | OAI22x1_ASAP7_75t_SL | 1 | 28.200 | 12.500 | 528.700 | + | cpu/stage1/regfile/n_1351 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77281/Y | | A->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 19.700 | 8.600 | 537.300 | + | cpu/stage1/regfile/n_1848 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76866__1666/Y | | B->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 15.800 | 19.300 | 556.600 | + | cpu/stage1/rs1_mux_data[13] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g563__7098/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 38.200 | 25.700 | 582.300 | + | cpu/stage1_rs1[13] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1258__4319/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 15.900 | 19.900 | 602.200 | + | cpu/stage1/pcadder/n_44 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 3 | 18.300 | 11.000 | 613.200 | + | 33_g1450__7098/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_77 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 2 | 18.700 | 8.200 | 621.400 | + | 33_g1353__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_158 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 14.200 | 17.500 | 638.900 | + | 33_g1318__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_186 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OA21x2_ASAP7_75t_SL | 2 | 33.100 | 19.900 | 658.800 | + | 33_g1305__9945/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_196 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0_dup/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 14.800 | 15.500 | 674.300 | + | cpu/stage1/pcadder/FE_RN_1 | | | F | (net) | 1 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 27.400 | 11.400 | 685.700 | + | 33_g1283__1617/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_19 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 20.300 | 9.000 | 694.700 | + | 33_g1275__4319/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_20 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 2 | 12.500 | 21.400 | 716.100 | + | 33_g1263__2883/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_226 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 43.100 | 14.100 | 730.200 | + | 33_g1249__5122/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_238 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 26.500 | 16.900 | 747.100 | + | 33_g1240__4319/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[27] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g999__5115/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 14.700 | 8.600 | 755.700 | + | cpu/stage1/pcselmux/n_5 | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g932__5526/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 44.000 | 10.400 | 766.100 | + | cpu/stage1/stage1_pc_mux_to_pc[27] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g352__3680/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 23.400 | 8.900 | 775.000 | + | cpu/stage1/pcreg/FE_PHN4121_n_28 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC4121_n_28/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 43.800 | 15.300 | 790.300 | + | cpu/stage1/pcreg/n_28 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[27]/D | | D | R | DFFHQNx1_ASAP7_75t_L | 1 | 7.700 | 0.000 | 790.300 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 33.400 | 909.400 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[27]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 51.200 | 6.300 | 909.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 23: MET (17.679 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[25]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[25]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 125.500 (P) 160.800 (P) + Arrival:= 886.500 21.800 + + Setup:- -7.579 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 794.079 + Launch Clock:= 21.800 + Data Path:+ 754.600 + Slack:= 17.679 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.800 | 21.800 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[3]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 50.100 | 71.900 | + | cpu/stage3_inst[3] | | | R | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OCPC1470_stage3_inst_3/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 2 | 10.500 | 4.600 | 76.500 | + | cpu/stage3/ldsel/FE_OCPN1434_stage3_inst_3 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_RC_26_0/Y | | B->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 6.000 | 5.300 | 81.800 | + | cpu/stage3/ldsel/FE_RN_10_0 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/FE_RC_27_0/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 16.200 | 6.500 | 88.300 | + | cpu/stage3/ldsel/n_10 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g208/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 1 | 9.800 | 7.100 | 95.400 | + | cpu/stage3/ldsel/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g205/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 4 | 16.800 | 17.600 | 113.000 | + | cpu/stage3/LdSelect[0] | | | R | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y | | A->Y | F | INVx3_ASAP7_75t_SL | 1 | 16.000 | 6.300 | 119.300 | + | cpu/stage3/ldselmux/n_14 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 9.300 | 7.400 | 126.700 | + | cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 | | | R | (net) | 5 | | | | + | cpu/stage3/ldselmux/g2426/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 10.600 | 12.600 | 139.300 | + | cpu/stage3/ldselmux/n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/FE_OCPC1515_n_30/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 2 | 8.400 | 11.600 | 150.900 | + | cpu/stage3/ldselmux/FE_OCPN1476_n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/g2399/Y | | A2->Y | F | AOI21x1_ASAP7_75t_SL | 7 | 7.800 | 15.700 | 166.600 | + | cpu/stage3/ldselmux/n_62 | | | F | (net) | 7 | | | | + | cpu/stage3/ldselmux/g2354/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 31.000 | 15.700 | 182.300 | + | cpu/stage3/ldselmux/n_92 | | | R | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | F | OAI221xp5_ASAP7_75t_SL | 1 | 25.100 | 15.700 | 198.000 | + | cpu/stage3/wb_dmem[0] | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | F | AO21x1_ASAP7_75t_SL | 3 | 28.200 | 22.300 | 220.300 | + | cpu/wb_data[0] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 4 | 15.500 | 23.200 | 243.500 | + | cpu/stage2/stage2_rs2_data[0] | | | F | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 18.500 | 10.300 | 253.800 | + | cpu/stage2/bselmux/n_6 | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 2 | 25.000 | 23.800 | 277.600 | + | cpu/stage2/stage2_alu_in2[0] | | | R | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 24 | 28.000 | 16.300 | 293.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | F | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 5 | 29.700 | 29.900 | 323.800 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | F | XNOR2xp5_ASAP7_75t_SL | 2 | 33.500 | 25.800 | 349.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | R | MAJIxp5_ASAP7_75t_SL | 2 | 33.200 | 23.900 | 373.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 44.100 | 19.200 | 392.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 15.700 | 408.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 3 | 13.100 | 16.700 | 425.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | F | OAI311xp33_ASAP7_75t_SL | 1 | 14.900 | 9.900 | 435.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 27.900 | 13.600 | 448.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 20.800 | 16.700 | 465.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 11.900 | 14.500 | 479.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 11.000 | 8.800 | 488.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 16.000 | 20.900 | 509.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | R | AOI31xp67_ASAP7_75t_SL | 3 | 15.700 | 15.200 | 524.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 30.500 | 10.200 | 534.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 32.200 | 26.200 | 561.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 20.400 | 17.700 | 578.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | R | NAND2x1_ASAP7_75t_SL | 2 | 13.200 | 10.700 | 589.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 20.400 | 9.300 | 598.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | R | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 36.500 | 16.100 | 614.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 27.700 | 12.200 | 627.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1519/Y | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 1 | 19.200 | 12.900 | 640.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_232 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1518/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 23.500 | 16.600 | 656.600 | + | cpu/stage2/alu/n_316 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5509/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 20.600 | 31.600 | 688.200 | + | dcache_addr[25] | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g430__2802/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 52.600 | 13.600 | 701.800 | + | cpu/s2_to_s3_alu/n_21 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC3580_n_21/Y | | A->Y | F | BUFx6f_ASAP7_75t_L | 1 | 66.300 | 24.800 | 726.600 | + | cpu/s2_to_s3_alu/FE_PHN3580_n_21 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2777_n_21/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 7.800 | 49.800 | 776.400 | + | cpu/s2_to_s3_alu/FE_PHN2777_n_21 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[25]/D | | D | F | DFFHQNx1_ASAP7_75t_L | 1 | 19.300 | 0.100 | 776.400 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 39.700 | 886.500 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[25]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 62.800 | 8.800 | 886.500 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 24: MET (17.815 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[25]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage3/csr/csr_reg[25]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.300 (P) 160.800 (P) + Arrival:= 900.300 21.800 + + Setup:- -4.515 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 804.815 + Launch Clock:= 21.800 + Data Path:+ 765.200 + Slack:= 17.815 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.800 | 21.800 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[3]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 50.100 | 71.900 | + | cpu/stage3_inst[3] | | | R | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OCPC1470_stage3_inst_3/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 2 | 10.500 | 4.600 | 76.500 | + | cpu/stage3/ldsel/FE_OCPN1434_stage3_inst_3 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_RC_26_0/Y | | B->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 6.000 | 5.300 | 81.800 | + | cpu/stage3/ldsel/FE_RN_10_0 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/FE_RC_27_0/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 16.200 | 6.500 | 88.300 | + | cpu/stage3/ldsel/n_10 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g208/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 1 | 9.800 | 7.100 | 95.400 | + | cpu/stage3/ldsel/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g205/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 4 | 16.800 | 17.600 | 113.000 | + | cpu/stage3/LdSelect[0] | | | R | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y | | A->Y | F | INVx3_ASAP7_75t_SL | 1 | 16.000 | 6.300 | 119.300 | + | cpu/stage3/ldselmux/n_14 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 9.300 | 7.400 | 126.700 | + | cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 | | | R | (net) | 5 | | | | + | cpu/stage3/ldselmux/g2426/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 10.600 | 12.600 | 139.300 | + | cpu/stage3/ldselmux/n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/FE_OCPC1515_n_30/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 2 | 8.400 | 11.600 | 150.900 | + | cpu/stage3/ldselmux/FE_OCPN1476_n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/g2399/Y | | A2->Y | F | AOI21x1_ASAP7_75t_SL | 7 | 7.800 | 15.700 | 166.600 | + | cpu/stage3/ldselmux/n_62 | | | F | (net) | 7 | | | | + | cpu/stage3/ldselmux/g2354/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 31.000 | 15.700 | 182.300 | + | cpu/stage3/ldselmux/n_92 | | | R | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | F | OAI221xp5_ASAP7_75t_SL | 1 | 25.100 | 15.700 | 198.000 | + | cpu/stage3/wb_dmem[0] | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | F | AO21x1_ASAP7_75t_SL | 3 | 28.200 | 22.300 | 220.300 | + | cpu/wb_data[0] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 4 | 15.500 | 23.200 | 243.500 | + | cpu/stage2/stage2_rs2_data[0] | | | F | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 18.500 | 10.300 | 253.800 | + | cpu/stage2/bselmux/n_6 | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 2 | 25.000 | 23.800 | 277.600 | + | cpu/stage2/stage2_alu_in2[0] | | | R | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 24 | 28.000 | 16.300 | 293.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | F | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 5 | 29.700 | 29.900 | 323.800 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | F | XNOR2xp5_ASAP7_75t_SL | 2 | 33.500 | 25.800 | 349.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | R | MAJIxp5_ASAP7_75t_SL | 2 | 33.200 | 23.900 | 373.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 44.100 | 19.200 | 392.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 15.700 | 408.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 3 | 13.100 | 16.700 | 425.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | F | OAI311xp33_ASAP7_75t_SL | 1 | 14.900 | 9.900 | 435.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 27.900 | 13.600 | 448.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 20.800 | 16.700 | 465.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 11.900 | 14.500 | 479.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 11.000 | 8.800 | 488.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 16.000 | 20.900 | 509.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | R | AOI31xp67_ASAP7_75t_SL | 3 | 15.700 | 15.200 | 524.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 30.500 | 10.200 | 534.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 32.200 | 26.200 | 561.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 20.400 | 17.700 | 578.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | R | NAND2x1_ASAP7_75t_SL | 2 | 13.200 | 10.700 | 589.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 20.400 | 9.300 | 598.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | R | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 36.500 | 16.100 | 614.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 27.700 | 12.200 | 627.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1519/Y | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 1 | 19.200 | 12.900 | 640.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_232 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1518/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 23.500 | 16.600 | 656.600 | + | cpu/stage2/alu/n_316 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5509/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 20.600 | 32.100 | 688.700 | + | dcache_addr[25] | | | R | (net) | 4 | | | | + | cpu/stage3/csr/g167/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 52.600 | 15.700 | 704.400 | + | cpu/stage3/csr/n_28 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2773_n_28/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 63.400 | 60.700 | 765.100 | + | cpu/stage3/csr/FE_PHN2773_n_28 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC3576_n_28/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 17.700 | 21.900 | 787.000 | + | cpu/stage3/csr/FE_PHN3576_n_28 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[25]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 11.300 | 0.000 | 787.000 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 30.900 | 900.300 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[25]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.100 | 1.600 | 900.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 25: MET (19.415 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[11]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[11]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 125.000 (P) 160.200 (P) + Arrival:= 886.000 21.200 + + Setup:- 6.185 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.815 + Launch Clock:= 21.200 + Data Path:+ 739.200 + Slack:= 19.415 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g393__9945/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 7 | 5.800 | 26.700 | 443.200 | + | cpu/stage1_inst[23] | | | F | (net) | 7 | | | | + | cpu/stage1/regfile/g80396/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 33.600 | 41.200 | 484.400 | + | cpu/stage1/regfile/n_247 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79870/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 80.200 | 16.300 | 500.700 | + | cpu/stage1/regfile/n_246 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g79865/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 30 | 34.300 | 93.600 | 594.300 | + | cpu/stage1/regfile/n_269 | | | F | (net) | 30 | | | | + | cpu/stage1/regfile/g78003/Y | | A2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 149.400 | 22.700 | 617.000 | + | cpu/stage1/regfile/n_1136 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77367/Y | | A->Y | R | AND4x1_ASAP7_75t_SL | 1 | 56.000 | 24.500 | 641.500 | + | cpu/stage1/regfile/n_1773 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77050/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 12.900 | 13.800 | 655.300 | + | cpu/stage1/regfile/n_2059 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76972__4733/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 39.800 | 15.700 | 671.000 | + | cpu/stage1/regfile/n_2137 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76948__2883/Y | | B->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 27.100 | 50.800 | 721.800 | + | cpu/stage1/rs2_mux_data[11] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g567__5115/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 111.800 | 29.100 | 750.900 | + | cpu/stage1_rs2[11] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g432__6783/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 15.900 | 9.500 | 760.400 | + | cpu/s1_to_s2_rs2/n_19 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[11]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 59.800 | 0.100 | 760.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.300 | 886.000 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[11]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 5.400 | 886.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 26: MET (19.487 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 148.900 (P) 160.200 (P) + Arrival:= 909.900 21.200 + + Setup:- 4.813 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 805.087 + Launch Clock:= 21.200 + Data Path:+ 764.400 + Slack:= 19.487 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.700 | 401.000 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 4 | 17.300 | 20.200 | 421.200 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1209_stage1_inst_15/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 6 | 37.700 | 11.200 | 432.400 | + | cpu/stage1/regfile/FE_OFN1007_stage1_inst_15 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/FE_RC_2_0/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 20.200 | 14.700 | 447.100 | + | cpu/stage1/regfile/FE_RN_0_0 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_RC_3_0/Y | | A->Y | F | INVx6_ASAP7_75t_SL | 5 | 22.500 | 12.500 | 459.600 | + | cpu/stage1/regfile/n_211 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC991_n_211/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 1 | 19.600 | 8.200 | 467.800 | + | cpu/stage1/regfile/FE_OFN1087_n_211 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1195_n_211/Y | | A->Y | F | INVx8_ASAP7_75t_SL | 13 | 12.200 | 10.500 | 478.300 | + | cpu/stage1/regfile/FE_OFN1090_n_211 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79826/Y | | B->Y | F | AND2x6_ASAP7_75t_SL | 7 | 13.200 | 22.500 | 500.800 | + | cpu/stage1/regfile/n_326 | | | F | (net) | 7 | | | | + | cpu/stage1/regfile/g78423/Y | | B->Y | R | NAND2x2_ASAP7_75t_SL | 4 | 19.600 | 15.400 | 516.200 | + | cpu/stage1/regfile/n_788 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77789/Y | | A2->Y | F | OAI22x1_ASAP7_75t_SL | 1 | 28.200 | 12.500 | 528.700 | + | cpu/stage1/regfile/n_1351 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77281/Y | | A->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 19.700 | 8.600 | 537.300 | + | cpu/stage1/regfile/n_1848 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76866__1666/Y | | B->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 15.800 | 19.300 | 556.600 | + | cpu/stage1/rs1_mux_data[13] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g563__7098/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 38.200 | 25.700 | 582.300 | + | cpu/stage1_rs1[13] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1258__4319/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 15.900 | 19.900 | 602.200 | + | cpu/stage1/pcadder/n_44 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 3 | 18.300 | 11.000 | 613.200 | + | 33_g1450__7098/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_77 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 2 | 18.700 | 8.200 | 621.400 | + | 33_g1353__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_158 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 14.200 | 17.500 | 638.900 | + | 33_g1318__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_186 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OA21x2_ASAP7_75t_SL | 2 | 33.100 | 19.900 | 658.800 | + | 33_g1305__9945/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_196 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0_dup/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 14.800 | 15.500 | 674.300 | + | cpu/stage1/pcadder/FE_RN_1 | | | F | (net) | 1 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 27.400 | 11.400 | 685.700 | + | 33_g1283__1617/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_19 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 20.300 | 9.000 | 694.700 | + | 33_g1275__4319/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_20 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 12.500 | 18.100 | 712.800 | + | 33_g1257__7482/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_231 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 12.000 | 11.100 | 723.900 | + | 33_g1244__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_243 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 24.600 | 6.600 | 730.500 | + | 33_g1236__5477/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_251 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 15.800 | 14.100 | 744.600 | + | 33_g1235__6417/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[31] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g988__5526/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 1 | 16.100 | 14.900 | 759.500 | + | cpu/stage1/pcselmux/n_16 | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g961__6783/Y | | B->Y | F | AO21x1_ASAP7_75t_SL | 2 | 14.200 | 17.300 | 776.800 | + | cpu/stage1/stage1_pc_mux_to_pc[31] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g362__7482/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 15.200 | 8.800 | 785.600 | + | cpu/stage1/pcreg/n_18 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[31]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 46.500 | 0.100 | 785.600 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 33.900 | 909.900 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.200 | 6.800 | 909.900 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 27: MET (20.493 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[22]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 120.300 (P) 160.200 (P) + Arrival:= 881.300 21.200 + + Setup:- 6.907 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 774.393 + Launch Clock:= 21.200 + Data Path:+ 732.700 + Slack:= 20.493 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 28.700 | 501.300 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79856/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 27 | 49.900 | 70.000 | 571.300 | + | cpu/stage1/regfile/n_284 | | | F | (net) | 27 | | | | + | cpu/stage1/regfile/g78499/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 111.700 | 45.300 | 616.600 | + | cpu/stage1/regfile/n_667 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g77806/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 42.100 | 19.600 | 636.200 | + | cpu/stage1/regfile/n_1334 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77085/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 53.900 | 24.300 | 660.500 | + | cpu/stage1/regfile/n_2024 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77004/Y | | B->Y | R | AOI211xp5_ASAP7_75t_SL | 1 | 48.700 | 25.500 | 686.000 | + | cpu/stage1/regfile/n_2105 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76906__1617/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 45.300 | 15.500 | 701.500 | + | cpu/stage1/rs2_mux_data[22] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_OCPC1477_rs2_mux_data_22 | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 33.400 | 23.500 | 725.000 | + | /Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_OCPN1438_rs2_mux_data_22 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g562__5122/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 17.700 | 17.300 | 742.300 | + | cpu/stage1_rs2[22] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g443__7482/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 12.400 | 11.600 | 753.900 | + | cpu/s1_to_s2_rs2/n_8 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[22]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 66.500 | 0.300 | 753.900 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 32.600 | 881.300 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[22]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 52.700 | 0.700 | 881.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 28: MET (20.999 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[24]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[24]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 121.300 (P) 160.200 (P) + Arrival:= 882.300 21.200 + + Setup:- 1.701 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.599 + Launch Clock:= 21.200 + Data Path:+ 738.400 + Slack:= 20.999 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.800 | 409.200 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_RC_13_0/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 13.000 | 6.300 | 415.500 | + | cpu/stage1/nopselmux/FE_RN_3_0 | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_RC_10_0/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 1 | 9.300 | 18.500 | 434.000 | + | cpu/stage1/nopselmux/FE_RN_5_0 | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_RC_11_0/Y | | A->Y | R | INVx6_ASAP7_75t_SL | 44 | 10.600 | 41.000 | 475.000 | + | cpu/stage1_inst[22] | | | R | (net) | 44 | | | | + | cpu/stage1/regfile/g80975/Y | | A->Y | F | INVx6_ASAP7_75t_SL | 19 | 59.400 | 17.000 | 492.000 | + | cpu/stage1/regfile/n_179 | | | F | (net) | 19 | | | | + | cpu/stage1/regfile/g79812/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 3 | 43.100 | 25.200 | 517.200 | + | cpu/stage1/regfile/n_342 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g79319/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 48.900 | 7.600 | 524.800 | + | cpu/stage1/regfile/n_341 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78502/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 7 | 18.200 | 87.600 | 612.400 | + | cpu/stage1/regfile/n_663 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g77792/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 198.700 | 19.900 | 632.300 | + | cpu/stage1/regfile/n_1348 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77156/Y | | C->Y | R | OAI211xp5_ASAP7_75t_SL | 1 | 70.600 | 22.500 | 654.800 | + | cpu/stage1/regfile/n_1953 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77066/Y | | C->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 41.200 | 16.500 | 671.300 | + | cpu/stage1/regfile/n_2043 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76942__5115/Y | | B->Y | R | OAI211xp5_ASAP7_75t_SL | 1 | 50.700 | 23.400 | 694.700 | + | cpu/stage1/rs2_mux_data[24] | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PSC4052_rs2_mux_data_24/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 1 | 48.400 | 27.000 | 721.700 | + | cpu/stage1/FE_PSN4052_rs2_mux_data_24 | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g552__5107/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 28.800 | 18.100 | 739.800 | + | cpu/stage1_rs2[24] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3587_stage1_rs2_24/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 13.700 | 11.400 | 751.200 | + | cpu/s1_to_s2_rs2/FE_PHN3587_stage1_rs2_24 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g445__6161/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.600 | 8.400 | 759.600 | + | cpu/s1_to_s2_rs2/n_6 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[24]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 66.700 | 0.300 | 759.600 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 33.600 | 882.300 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[24]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.100 | 1.700 | 882.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 29: MET (22.098 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 148.500 (P) 160.200 (P) + Arrival:= 909.500 21.200 + + Setup:- 4.802 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 804.698 + Launch Clock:= 21.200 + Data Path:+ 761.400 + Slack:= 22.098 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 18.400 | 398.500 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 4 | 17.400 | 18.100 | 416.600 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y | | A->Y | R | INVx4_ASAP7_75t_SL | 1 | 31.400 | 9.200 | 425.800 | + | cpu/stage1/regfile/FE_OFN1120_n | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 14.500 | 7.500 | 433.300 | + | cpu/stage1/regfile/FE_OFN1214_n | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/g80989/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 5 | 11.100 | 20.300 | 453.600 | + | cpu/stage1/regfile/n_171 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1093_n_171/Y | | A->Y | F | BUFx6f_ASAP7_75t_SL | 8 | 20.000 | 18.900 | 472.500 | + | cpu/stage1/regfile/FE_OFN1071_n_171 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/g79839/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 3 | 18.300 | 18.900 | 491.400 | + | cpu/stage1/regfile/n_311 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC797_n_311/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 3 | 11.900 | 9.500 | 500.900 | + | cpu/stage1/regfile/n_310 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g78360/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.000 | 11.000 | 511.900 | + | cpu/stage1/regfile/n_770 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77522/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 16.100 | 528.000 | + | cpu/stage1/regfile/n_1614 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77116/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 32.500 | 13.400 | 541.400 | + | cpu/stage1/regfile/n_1993 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76985__4319/Y | | A1->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 23.500 | 15.500 | 556.900 | + | cpu/stage1/regfile/n_2124 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76911__7098/Y | | A->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 26.200 | 12.400 | 569.300 | + | cpu/stage1/rs1_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g575__7410/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 25.100 | 20.800 | 590.100 | + | cpu/stage1_rs1[7] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1267__8246/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 16.800 | 606.900 | + | cpu/stage1/pcadder/n_38 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_L | 3 | 16.500 | 12.700 | 619.600 | + | 33_g1502__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_33 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 19.900 | 16.200 | 635.800 | + | 33_g1361__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_148 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 12.200 | 7.300 | 643.100 | + | 33_g1328__2802/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_176 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.700 | 13.400 | 656.500 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | R | BUFx2_ASAP7_75t_SL | 4 | 23.700 | 17.900 | 674.400 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | R | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0/Y | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 2 | 15.300 | 14.300 | 688.700 | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_18 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 25.000 | 14.000 | 702.700 | + | 33_g1295/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_203 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 21.800 | 9.400 | 712.100 | + | 33_g1288__1705/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_209 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 17.400 | 15.300 | 727.400 | + | 33_g1272__5107/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_218 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_18_0/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 30.600 | 12.500 | 739.900 | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_235 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 21.300 | 18.300 | 758.200 | + | 33_g1246__1617/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[19] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g947__9315/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.700 | 15.700 | 773.900 | + | cpu/stage1/stage1_pc_mux_to_pc[19] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g360__1881/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 15.000 | 8.700 | 782.600 | + | cpu/stage1/pcreg/n_20 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[19]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 46.400 | 0.100 | 782.600 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 33.500 | 909.500 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.200 | 6.400 | 909.500 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 30: MET (22.401 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[29]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 149.000 (P) 160.200 (P) + Arrival:= 910.000 21.200 + + Setup:- 4.699 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 805.301 + Launch Clock:= 21.200 + Data Path:+ 761.700 + Slack:= 22.401 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.700 | 401.000 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 4 | 17.300 | 20.200 | 421.200 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1209_stage1_inst_15/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 6 | 37.700 | 11.200 | 432.400 | + | cpu/stage1/regfile/FE_OFN1007_stage1_inst_15 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/FE_RC_2_0/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 20.200 | 14.700 | 447.100 | + | cpu/stage1/regfile/FE_RN_0_0 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_RC_3_0/Y | | A->Y | F | INVx6_ASAP7_75t_SL | 5 | 22.500 | 12.500 | 459.600 | + | cpu/stage1/regfile/n_211 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC991_n_211/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 1 | 19.600 | 8.200 | 467.800 | + | cpu/stage1/regfile/FE_OFN1087_n_211 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1195_n_211/Y | | A->Y | F | INVx8_ASAP7_75t_SL | 13 | 12.200 | 10.500 | 478.300 | + | cpu/stage1/regfile/FE_OFN1090_n_211 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79826/Y | | B->Y | F | AND2x6_ASAP7_75t_SL | 7 | 13.200 | 22.500 | 500.800 | + | cpu/stage1/regfile/n_326 | | | F | (net) | 7 | | | | + | cpu/stage1/regfile/g78423/Y | | B->Y | R | NAND2x2_ASAP7_75t_SL | 4 | 19.600 | 15.400 | 516.200 | + | cpu/stage1/regfile/n_788 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77789/Y | | A2->Y | F | OAI22x1_ASAP7_75t_SL | 1 | 28.200 | 12.500 | 528.700 | + | cpu/stage1/regfile/n_1351 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77281/Y | | A->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 19.700 | 8.600 | 537.300 | + | cpu/stage1/regfile/n_1848 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76866__1666/Y | | B->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 15.800 | 19.300 | 556.600 | + | cpu/stage1/rs1_mux_data[13] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g563__7098/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 38.200 | 25.700 | 582.300 | + | cpu/stage1_rs1[13] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1258__4319/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 15.900 | 19.900 | 602.200 | + | cpu/stage1/pcadder/n_44 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 3 | 18.300 | 11.000 | 613.200 | + | 33_g1450__7098/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_77 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 2 | 18.700 | 8.200 | 621.400 | + | 33_g1353__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_158 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 14.200 | 17.500 | 638.900 | + | 33_g1318__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_186 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OA21x2_ASAP7_75t_SL | 2 | 33.100 | 19.900 | 658.800 | + | 33_g1305__9945/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_196 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0_dup/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 14.800 | 15.500 | 674.300 | + | cpu/stage1/pcadder/FE_RN_1 | | | F | (net) | 1 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 27.400 | 11.400 | 685.700 | + | 33_g1283__1617/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_19 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 20.300 | 9.000 | 694.700 | + | 33_g1275__4319/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_20 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 12.500 | 18.100 | 712.800 | + | 33_g1257__7482/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_231 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 12.000 | 9.300 | 722.100 | + | 33_g1256/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_232 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 14.900 | 9.500 | 731.600 | + | 33_g1241__8428/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_246 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.800 | 14.000 | 745.600 | + | 33_g1238__5107/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[29] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g989__6783/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 1 | 18.400 | 14.100 | 759.700 | + | cpu/stage1/pcselmux/n_15 | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/FE_OCPC1474_n_15/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 12.600 | 7.900 | 767.600 | + | cpu/stage1/pcselmux/FE_RN_7_0 | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/FE_RC_15_0/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 11.900 | 6.700 | 774.300 | + | cpu/stage1/stage1_pc_mux_to_pc[29] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g350__5526/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 16.900 | 8.600 | 782.900 | + | cpu/stage1/pcreg/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[29]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 45.400 | 0.000 | 782.900 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 34.000 | 910.000 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[29]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.200 | 6.900 | 910.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 31: MET (22.659 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[23]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 148.300 (P) 160.200 (P) + Arrival:= 909.300 21.200 + + Setup:- 4.741 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 804.559 + Launch Clock:= 21.200 + Data Path:+ 760.700 + Slack:= 22.659 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 18.400 | 398.500 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 4 | 17.400 | 18.100 | 416.600 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y | | A->Y | R | INVx4_ASAP7_75t_SL | 1 | 31.400 | 9.200 | 425.800 | + | cpu/stage1/regfile/FE_OFN1120_n | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 14.500 | 7.500 | 433.300 | + | cpu/stage1/regfile/FE_OFN1214_n | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/g80989/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 5 | 11.100 | 20.300 | 453.600 | + | cpu/stage1/regfile/n_171 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1093_n_171/Y | | A->Y | F | BUFx6f_ASAP7_75t_SL | 8 | 20.000 | 18.900 | 472.500 | + | cpu/stage1/regfile/FE_OFN1071_n_171 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/g79839/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 3 | 18.300 | 18.900 | 491.400 | + | cpu/stage1/regfile/n_311 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC797_n_311/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 3 | 11.900 | 9.500 | 500.900 | + | cpu/stage1/regfile/n_310 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g78360/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.000 | 11.000 | 511.900 | + | cpu/stage1/regfile/n_770 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77522/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 16.100 | 528.000 | + | cpu/stage1/regfile/n_1614 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77116/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 32.500 | 13.400 | 541.400 | + | cpu/stage1/regfile/n_1993 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76985__4319/Y | | A1->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 23.500 | 15.500 | 556.900 | + | cpu/stage1/regfile/n_2124 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76911__7098/Y | | A->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 26.200 | 12.400 | 569.300 | + | cpu/stage1/rs1_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g575__7410/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 25.100 | 20.800 | 590.100 | + | cpu/stage1_rs1[7] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1267__8246/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 16.800 | 606.900 | + | cpu/stage1/pcadder/n_38 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_L | 3 | 16.500 | 12.700 | 619.600 | + | 33_g1502__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_33 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 19.900 | 16.200 | 635.800 | + | 33_g1361__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_148 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 12.200 | 7.300 | 643.100 | + | 33_g1328__2802/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_176 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.700 | 13.400 | 656.500 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | R | BUFx2_ASAP7_75t_SL | 4 | 23.700 | 17.900 | 674.400 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | R | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0/Y | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 2 | 15.300 | 14.300 | 688.700 | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_18 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 25.000 | 19.400 | 708.100 | + | 33_g1280__3680/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_213 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 36.000 | 13.000 | 721.100 | + | 33_g1270__5477/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_220 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 13.600 | 734.700 | + | 33_g1255__5115/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_233 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 28.000 | 7.200 | 741.900 | + | 33_g1242__5526/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_245 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 14.100 | 15.900 | 757.800 | + | 33_g1239__6260/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[23] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g933__6783/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 18.300 | 15.700 | 773.500 | + | cpu/stage1/stage1_pc_mux_to_pc[23] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g364__6161/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 14.900 | 8.400 | 781.900 | + | cpu/stage1/pcreg/n_16 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[23]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 45.900 | 0.000 | 781.900 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 33.300 | 909.300 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[23]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.100 | 6.200 | 909.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 32: MET (22.723 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 140.200 (P) 160.200 (P) + Arrival:= 901.200 21.200 + + Setup:- 3.776 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 797.424 + Launch Clock:= 21.200 + Data Path:+ 753.500 + Slack:= 22.723 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1549/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 1 | 33.200 | 20.100 | 550.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_206 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1547/Y | | B->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 11.000 | 12.600 | 562.700 | + | cpu/stage2/alu/n_306 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5665/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 12.600 | 8.100 | 570.800 | + | cpu/stage2/alu/n_56 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5522/Y | | A->Y | F | NAND3xp33_ASAP7_75t_SL | 2 | 33.300 | 42.000 | 612.800 | + | dcache_addr[15] | | | F | (net) | 2 | | | | + | cpu/FE_PHC2730_dcache_addr_15/Y | | A->Y | F | HB3xp67_ASAP7_75t_SL | 3 | 94.800 | 76.000 | 688.800 | + | cpu/FE_PHN2730_dcache_addr_15 | | | F | (net) | 3 | | | | + | cpu/stage3/csr/g180/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 63.400 | 17.200 | 706.000 | + | cpu/stage3/csr/FE_PHN2799_n_15 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2799_n_15/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 50.000 | 68.700 | 774.700 | + | cpu/stage3/csr/n_15 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[15]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.200 | 0.400 | 774.700 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 31.800 | 901.200 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[15]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.300 | 2.500 | 901.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 33: MET (23.236 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 125.000 (P) 160.200 (P) + Arrival:= 886.000 21.200 + + Setup:- 6.164 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.836 + Launch Clock:= 21.200 + Data Path:+ 735.400 + Slack:= 23.236 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 28.700 | 501.300 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79863/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 28 | 49.900 | 90.200 | 591.500 | + | cpu/stage1/regfile/n_272 | | | F | (net) | 28 | | | | + | cpu/stage1/regfile/g77956/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 133.000 | 28.300 | 619.800 | + | cpu/stage1/regfile/n_1183 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77455/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 14.500 | 15.500 | 635.300 | + | cpu/stage1/regfile/n_1681 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77174/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 59.600 | 20.100 | 655.400 | + | cpu/stage1/regfile/n_1941 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77019/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 41.900 | 15.100 | 670.500 | + | cpu/stage1/regfile/n_2090 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76938__8246/Y | | C->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 26.000 | 18.800 | 689.300 | + | cpu/stage1/rs2_mux_data[15] | | | F | (net) | 1 | | | | + | cpu/stage1/FE_PHC4116_rs2_mux_data_15/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 41.700 | 28.300 | 717.600 | + | cpu/stage1/FE_PHN4116_rs2_mux_data_15 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g545__2883/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 13.600 | 17.600 | 735.200 | + | cpu/stage1_rs2[15] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3597_stage1_rs2_15/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 13.400 | 13.600 | 748.800 | + | cpu/s1_to_s2_rs2/FE_PHN3597_stage1_rs2_15 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g450__1666/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 8.600 | 7.800 | 756.600 | + | cpu/s1_to_s2_rs2/n_1 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[15]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 59.700 | 0.100 | 756.600 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.300 | 886.000 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[15]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 5.400 | 886.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 34: MET (24.331 ps) Setup Check with Pin mem/dcache/STATE_reg[1]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) mem/dcache/STATE_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 140.800 (P) 160.200 (P) + Arrival:= 901.800 21.200 + + Setup:- 8.169 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 793.631 + Launch Clock:= 21.200 + Data Path:+ 748.100 + Slack:= 24.331 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.300 | 179.500 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2349/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.500 | 192.000 | + | cpu/stage3/ldselmux/n_97 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2313/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 23.800 | 17.900 | 209.900 | + | cpu/stage3/wb_dmem[5] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1109/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 51.100 | 17.800 | 227.700 | + | cpu/wb_data[5] | | | R | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g550/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 5 | 19.800 | 23.100 | 250.800 | + | cpu/stage2/stage2_rs1_data[5] | | | R | (net) | 5 | | | | + | cpu/stage2/aselmux/g549/Y | | A1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 30.400 | 17.400 | 268.200 | + | cpu/stage2/stage2_alu_in1[5] | | | R | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC821_stage2_alu_in1_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 14.800 | 9.100 | 277.300 | + | cpu/stage2/alu/FE_DBTN72_stage2_alu_in1_5 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC823_stage2_alu_in1_5/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 9 | 13.500 | 34.700 | 312.000 | + | cpu/stage2/alu/FE_OFN957_stage2_alu_in1_5 | | | R | (net) | 9 | | | | + | cpu/stage2/alu/FE_OFC825_stage2_alu_in1_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 5 | 71.900 | 19.400 | 331.400 | + | cpu/stage2/alu/FE_OFN959_stage2_alu_in1_5 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/lt_30_22_g1493/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 4 | 35.800 | 20.700 | 352.100 | + | cpu/stage2/alu/lt_30_22_n_37 | | | F | (net) | 4 | | | | + | cpu/stage2/alu/lt_29_31_g1466/Y | | A1->Y | R | OAI32xp33_ASAP7_75t_SL | 1 | 12.400 | 14.200 | 366.300 | + | cpu/stage2/alu/lt_29_31_n_63 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1465/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 55.100 | 6.700 | 373.000 | + | cpu/stage2/alu/lt_29_31_n_64 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1451/Y | | C1->Y | R | OAI322xp33_ASAP7_75t_SL | 1 | 18.400 | 16.000 | 389.000 | + | cpu/stage2/alu/lt_29_31_n_78 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1444/Y | | B->Y | F | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 46.900 | 17.300 | 406.300 | + | cpu/stage2/alu/lt_29_31_n_85 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1443/Y | | A1->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 35.500 | 32.200 | 438.500 | + | cpu/stage2/alu/lt_29_31_n_86 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1442/Y | | A1->Y | F | AOI321xp33_ASAP7_75t_SL | 1 | 67.200 | 36.700 | 475.200 | + | cpu/stage2/alu/n_324 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5667/Y | | B1->Y | R | AOI33xp33_ASAP7_75t_SL | 1 | 68.000 | 30.300 | 505.500 | + | cpu/stage2/alu/n_54 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5520/Y | | A2->Y | F | OAI211xp5_ASAP7_75t_SL | 1 | 53.400 | 19.300 | 524.800 | + | cpu/stage2/alu/n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5502/Y | | C->Y | F | AO221x2_ASAP7_75t_SL | 9 | 43.500 | 52.300 | 577.100 | + | cpu/stage2_alu_out[0] | | | F | (net) | 9 | | | | + | cpu/stage3/memrw/g432/Y | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 56.900 | 16.900 | 594.000 | + | cpu/stage3/memrw/n_6 | | | R | (net) | 2 | | | | + | cpu/stage3/memrw/g425/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 3 | 31.900 | 19.800 | 613.800 | + | dcache_we[1] | | | F | (net) | 3 | | | | + | mem/g31/Y | | B->Y | F | OR5x1_ASAP7_75t_SL | 3 | 42.400 | 50.300 | 664.100 | + | mem/n_317 | | | F | (net) | 3 | | | | + | mem/dcache/g14019/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 5 | 46.900 | 29.700 | 693.800 | + | mem/dcache/n_316 | | | R | (net) | 5 | | | | + | mem/dcache/g14016/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 47.800 | 17.400 | 711.200 | + | mem/dcache/n_99 | | | F | (net) | 2 | | | | + | mem/dcache/g13751/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 4 | 29.800 | 28.400 | 739.600 | + | mem/dc_mem_req_rw | | | R | (net) | 4 | | | | + | mem/dcache/g13730/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 52.700 | 14.500 | 754.100 | + | mem/dcache/n_314 | | | F | (net) | 2 | | | | + | mem/dcache/g11166/Y | | B->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 28.700 | 15.200 | 769.300 | + | mem/dcache/n_81 | | | R | (net) | 1 | | | | + | mem/dcache/STATE_reg[1]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 41.900 | 0.100 | 769.300 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 42.100 | 867.800 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 39.600 | 34.000 | 901.800 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[1]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 3 | 24.000 | 0.200 | 901.800 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 35: MET (24.409 ps) Setup Check with Pin mem/dcache/STATE_reg[2]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) mem/dcache/STATE_reg[2]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 140.800 (P) 160.200 (P) + Arrival:= 901.800 21.200 + + Setup:- 4.391 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 797.409 + Launch Clock:= 21.200 + Data Path:+ 751.800 + Slack:= 24.409 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.300 | 179.500 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2349/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.500 | 192.000 | + | cpu/stage3/ldselmux/n_97 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2313/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 23.800 | 17.900 | 209.900 | + | cpu/stage3/wb_dmem[5] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1109/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 51.100 | 17.800 | 227.700 | + | cpu/wb_data[5] | | | R | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g550/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 5 | 19.800 | 23.100 | 250.800 | + | cpu/stage2/stage2_rs1_data[5] | | | R | (net) | 5 | | | | + | cpu/stage2/aselmux/g549/Y | | A1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 30.400 | 17.400 | 268.200 | + | cpu/stage2/stage2_alu_in1[5] | | | R | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC821_stage2_alu_in1_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 14.800 | 9.100 | 277.300 | + | cpu/stage2/alu/FE_DBTN72_stage2_alu_in1_5 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC823_stage2_alu_in1_5/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 9 | 13.500 | 34.700 | 312.000 | + | cpu/stage2/alu/FE_OFN957_stage2_alu_in1_5 | | | R | (net) | 9 | | | | + | cpu/stage2/alu/FE_OFC825_stage2_alu_in1_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 5 | 71.900 | 19.400 | 331.400 | + | cpu/stage2/alu/FE_OFN959_stage2_alu_in1_5 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/lt_30_22_g1493/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 4 | 35.800 | 20.700 | 352.100 | + | cpu/stage2/alu/lt_30_22_n_37 | | | F | (net) | 4 | | | | + | cpu/stage2/alu/lt_29_31_g1466/Y | | A1->Y | R | OAI32xp33_ASAP7_75t_SL | 1 | 12.400 | 14.200 | 366.300 | + | cpu/stage2/alu/lt_29_31_n_63 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1465/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 55.100 | 6.700 | 373.000 | + | cpu/stage2/alu/lt_29_31_n_64 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1451/Y | | C1->Y | R | OAI322xp33_ASAP7_75t_SL | 1 | 18.400 | 16.000 | 389.000 | + | cpu/stage2/alu/lt_29_31_n_78 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1444/Y | | B->Y | F | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 46.900 | 17.300 | 406.300 | + | cpu/stage2/alu/lt_29_31_n_85 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1443/Y | | A1->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 35.500 | 32.200 | 438.500 | + | cpu/stage2/alu/lt_29_31_n_86 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1442/Y | | A1->Y | F | AOI321xp33_ASAP7_75t_SL | 1 | 67.200 | 36.700 | 475.200 | + | cpu/stage2/alu/n_324 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5667/Y | | B1->Y | R | AOI33xp33_ASAP7_75t_SL | 1 | 68.000 | 30.300 | 505.500 | + | cpu/stage2/alu/n_54 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5520/Y | | A2->Y | F | OAI211xp5_ASAP7_75t_SL | 1 | 53.400 | 19.300 | 524.800 | + | cpu/stage2/alu/n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5502/Y | | C->Y | F | AO221x2_ASAP7_75t_SL | 9 | 43.500 | 52.300 | 577.100 | + | cpu/stage2_alu_out[0] | | | F | (net) | 9 | | | | + | cpu/stage3/memrw/g432/Y | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 56.900 | 16.900 | 594.000 | + | cpu/stage3/memrw/n_6 | | | R | (net) | 2 | | | | + | cpu/stage3/memrw/g425/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 3 | 31.900 | 19.800 | 613.800 | + | dcache_we[1] | | | F | (net) | 3 | | | | + | mem/g31/Y | | B->Y | F | OR5x1_ASAP7_75t_SL | 3 | 42.400 | 50.300 | 664.100 | + | mem/n_317 | | | F | (net) | 3 | | | | + | mem/dcache/g14019/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 5 | 46.900 | 29.700 | 693.800 | + | mem/dcache/n_316 | | | R | (net) | 5 | | | | + | mem/dcache/g14016/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 47.800 | 17.400 | 711.200 | + | mem/dcache/n_99 | | | F | (net) | 2 | | | | + | mem/dcache/g13751/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 4 | 29.800 | 28.800 | 740.000 | + | mem/dc_mem_req_rw | | | R | (net) | 4 | | | | + | mem/dcache/FE_OFC439_dc_mem_req_rw/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 52.700 | 6.400 | 746.400 | + | mem/dcache/n_2 | | | F | (net) | 1 | | | | + | mem/dcache/g11190/Y | | B->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 17.800 | 10.700 | 757.100 | + | mem/dcache/n_57 | | | R | (net) | 1 | | | | + | mem/dcache/FE_PHC3589_n_57/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 37.900 | 15.900 | 773.000 | + | mem/dcache/FE_PHN3589_n_57 | | | R | (net) | 1 | | | | + | mem/dcache/STATE_reg[2]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 11.700 | 0.000 | 773.000 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 42.100 | 867.800 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 39.600 | 34.000 | 901.800 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[2]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 3 | 24.000 | 0.200 | 901.800 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 36: MET (24.464 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 146.700 (P) 160.200 (P) + Arrival:= 907.700 21.200 + + Setup:- 4.736 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 802.964 + Launch Clock:= 21.200 + Data Path:+ 757.300 + Slack:= 24.464 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 18.400 | 398.500 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 4 | 17.400 | 18.100 | 416.600 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y | | A->Y | R | INVx4_ASAP7_75t_SL | 1 | 31.400 | 9.200 | 425.800 | + | cpu/stage1/regfile/FE_OFN1120_n | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 14.500 | 7.500 | 433.300 | + | cpu/stage1/regfile/FE_OFN1214_n | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/g80989/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 5 | 11.100 | 20.300 | 453.600 | + | cpu/stage1/regfile/n_171 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1093_n_171/Y | | A->Y | F | BUFx6f_ASAP7_75t_SL | 8 | 20.000 | 18.900 | 472.500 | + | cpu/stage1/regfile/FE_OFN1071_n_171 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/g79839/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 3 | 18.300 | 18.900 | 491.400 | + | cpu/stage1/regfile/n_311 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC797_n_311/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 3 | 11.900 | 9.500 | 500.900 | + | cpu/stage1/regfile/n_310 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g78360/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.000 | 11.000 | 511.900 | + | cpu/stage1/regfile/n_770 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77522/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 16.100 | 528.000 | + | cpu/stage1/regfile/n_1614 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77116/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 32.500 | 13.400 | 541.400 | + | cpu/stage1/regfile/n_1993 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76985__4319/Y | | A1->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 23.500 | 15.500 | 556.900 | + | cpu/stage1/regfile/n_2124 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76911__7098/Y | | A->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 26.200 | 12.400 | 569.300 | + | cpu/stage1/rs1_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g575__7410/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 25.100 | 20.800 | 590.100 | + | cpu/stage1_rs1[7] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1267__8246/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 16.800 | 606.900 | + | cpu/stage1/pcadder/n_38 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_L | 3 | 16.500 | 12.700 | 619.600 | + | 33_g1502__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_33 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 19.900 | 16.200 | 635.800 | + | 33_g1361__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_148 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 12.200 | 7.300 | 643.100 | + | 33_g1328__2802/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_176 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.700 | 13.400 | 656.500 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | R | BUFx2_ASAP7_75t_SL | 4 | 23.700 | 18.000 | 674.500 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | R | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 15.300 | 8.100 | 682.600 | + | 33_g1310/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_193 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.800 | 12.200 | 694.800 | + | 33_g1299__5115/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_202 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 23.000 | 9.900 | 704.700 | + | 33_g1290__5122/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_207 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 14.300 | 17.600 | 722.300 | + | 33_g1273__6260/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_217 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 34.800 | 13.600 | 735.900 | + | 33_g1254__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_234 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 24.100 | 17.400 | 753.300 | + | 33_g1247__2802/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[15] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g934__3680/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 18.800 | 16.300 | 769.600 | + | cpu/stage1/stage1_pc_mux_to_pc[15] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g355__1705/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 15.500 | 8.900 | 778.500 | + | cpu/stage1/pcreg/n_25 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[15]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 45.800 | 0.100 | 778.500 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 31.700 | 907.700 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[15]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.600 | 4.600 | 907.700 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 37: MET (24.517 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[28]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage3/csr/csr_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.500 (P) 160.800 (P) + Arrival:= 900.500 21.800 + + Setup:- -3.916 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 804.416 + Launch Clock:= 21.800 + Data Path:+ 758.100 + Slack:= 24.517 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.800 | 21.800 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[3]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 50.100 | 71.900 | + | cpu/stage3_inst[3] | | | R | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OCPC1470_stage3_inst_3/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 2 | 10.500 | 4.600 | 76.500 | + | cpu/stage3/ldsel/FE_OCPN1434_stage3_inst_3 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_RC_26_0/Y | | B->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 6.000 | 5.300 | 81.800 | + | cpu/stage3/ldsel/FE_RN_10_0 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/FE_RC_27_0/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 16.200 | 6.500 | 88.300 | + | cpu/stage3/ldsel/n_10 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g208/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 1 | 9.800 | 7.100 | 95.400 | + | cpu/stage3/ldsel/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g205/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 4 | 16.800 | 17.600 | 113.000 | + | cpu/stage3/LdSelect[0] | | | R | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y | | A->Y | F | INVx3_ASAP7_75t_SL | 1 | 16.000 | 6.300 | 119.300 | + | cpu/stage3/ldselmux/n_14 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 9.300 | 7.400 | 126.700 | + | cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 | | | R | (net) | 5 | | | | + | cpu/stage3/ldselmux/g2426/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 10.600 | 12.600 | 139.300 | + | cpu/stage3/ldselmux/n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/FE_OCPC1515_n_30/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 2 | 8.400 | 11.600 | 150.900 | + | cpu/stage3/ldselmux/FE_OCPN1476_n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/g2399/Y | | A2->Y | F | AOI21x1_ASAP7_75t_SL | 7 | 7.800 | 15.700 | 166.600 | + | cpu/stage3/ldselmux/n_62 | | | F | (net) | 7 | | | | + | cpu/stage3/ldselmux/g2354/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 31.000 | 15.700 | 182.300 | + | cpu/stage3/ldselmux/n_92 | | | R | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | F | OAI221xp5_ASAP7_75t_SL | 1 | 25.100 | 15.700 | 198.000 | + | cpu/stage3/wb_dmem[0] | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | F | AO21x1_ASAP7_75t_SL | 3 | 28.200 | 22.300 | 220.300 | + | cpu/wb_data[0] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 4 | 15.500 | 23.200 | 243.500 | + | cpu/stage2/stage2_rs2_data[0] | | | F | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 18.500 | 10.300 | 253.800 | + | cpu/stage2/bselmux/n_6 | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 2 | 25.000 | 23.800 | 277.600 | + | cpu/stage2/stage2_alu_in2[0] | | | R | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 24 | 28.000 | 16.300 | 293.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | F | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 5 | 29.700 | 29.900 | 323.800 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | F | XNOR2xp5_ASAP7_75t_SL | 2 | 33.500 | 25.800 | 349.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | R | MAJIxp5_ASAP7_75t_SL | 2 | 33.200 | 23.900 | 373.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 44.100 | 19.200 | 392.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 15.700 | 408.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 3 | 13.100 | 16.700 | 425.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | F | OAI311xp33_ASAP7_75t_SL | 1 | 14.900 | 9.900 | 435.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 27.900 | 13.600 | 448.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 20.800 | 16.700 | 465.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 11.900 | 14.500 | 479.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 11.000 | 8.800 | 488.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 16.000 | 20.900 | 509.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | R | AOI31xp67_ASAP7_75t_SL | 3 | 15.700 | 15.200 | 524.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 30.500 | 10.200 | 534.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 32.200 | 26.200 | 561.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 20.400 | 17.700 | 578.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | R | NAND2x1_ASAP7_75t_SL | 2 | 13.200 | 10.700 | 589.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 20.400 | 9.300 | 598.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | R | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 36.500 | 16.100 | 614.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 27.700 | 12.200 | 627.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 19.200 | 19.500 | 646.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 16.700 | 10.700 | 657.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 19.400 | 16.500 | 673.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1511/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 12.600 | 16.900 | 690.700 | + | cpu/stage2/alu/n_319 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5508/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 22.700 | 30.200 | 720.900 | + | dcache_addr[28] | | | R | (net) | 4 | | | | + | cpu/stage3/csr/g190/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 47.900 | 17.700 | 738.600 | + | cpu/stage3/csr/n_5 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2779_n_5/Y | | A->Y | F | HB3xp67_ASAP7_75t_SL | 1 | 66.900 | 41.300 | 779.900 | + | cpu/stage3/csr/FE_PHN2779_n_5 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[28]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 16.200 | 0.000 | 779.900 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 31.100 | 900.500 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[28]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.100 | 1.800 | 900.500 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 38: MET (24.870 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage3/csr/csr_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.200 (P) 160.200 (P) + Arrival:= 900.200 21.200 + + Setup:- -2.370 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 802.570 + Launch Clock:= 21.200 + Data Path:+ 756.500 + Slack:= 24.870 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1545/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 2 | 23.000 | 15.000 | 580.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_210 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1540/Y | | A1->Y | F | AOI21xp5_ASAP7_75t_SL | 2 | 9.100 | 12.100 | 592.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_215 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1533/Y | | A2->Y | R | OAI21xp5_ASAP7_75t_SL | 1 | 22.800 | 14.500 | 607.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_222 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1528/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 31.300 | 17.000 | 624.200 | + | cpu/stage2/alu/n_310 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5523/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 19.300 | 31.600 | 655.800 | + | dcache_addr[19] | | | R | (net) | 4 | | | | + | cpu/stage3/csr/g183/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 51.300 | 9.800 | 665.600 | + | cpu/stage3/csr/FE_PHN2759_n_12 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC3573_n_12/Y | | A->Y | F | HB3xp67_ASAP7_75t_SL | 1 | 55.700 | 40.800 | 706.400 | + | cpu/stage3/csr/FE_PHN3573_n_12 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2759_n_12/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 17.600 | 71.300 | 777.700 | + | cpu/stage3/csr/n_12 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[19]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 26.700 | 0.300 | 777.700 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 30.800 | 900.200 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.200 | 1.500 | 900.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 39: MET (25.620 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[18]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[18]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 123.600 (P) 160.200 (P) + Arrival:= 884.600 21.200 + + Setup:- 6.080 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 778.520 + Launch Clock:= 21.200 + Data Path:+ 731.700 + Slack:= 25.620 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 30.100 | 502.700 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/FE_OFC643_n_237/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 50.100 | 9.500 | 512.200 | + | cpu/stage1/regfile/FE_OFN834_n_237 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g79821/Y | | B->Y | F | NOR2xp33_ASAP7_75t_L | 6 | 17.300 | 75.000 | 587.200 | + | cpu/stage1/regfile/n_332 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g77926/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 145.700 | 33.300 | 620.500 | + | cpu/stage1/regfile/n_1213 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77310/Y | | B->Y | F | NAND3xp33_ASAP7_75t_SL | 1 | 59.400 | 10.200 | 630.700 | + | cpu/stage1/regfile/n_1819 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77010/Y | | A2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 27.000 | 12.500 | 643.200 | + | cpu/stage1/regfile/n_2099 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC4041_n_2099/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 65.500 | 17.100 | 660.300 | + | cpu/stage1/regfile/FE_PHN4041_n_2099 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76915__7482/Y | | C->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 9.000 | 33.100 | 693.400 | + | cpu/stage1/rs2_mux_data[18] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3941_rs2_mux_data_18/ | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 73.100 | 22.200 | 715.600 | + | Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_PHN3941_rs2_mux_data_18 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g548__7410/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 9.200 | 17.700 | 733.300 | + | cpu/stage1_rs2[18] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3584_stage1_rs2_18/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 14.200 | 12.700 | 746.000 | + | cpu/s1_to_s2_rs2/FE_PHN3584_stage1_rs2_18 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g439__7098/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.400 | 6.900 | 752.900 | + | cpu/s1_to_s2_rs2/n_12 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[18]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 58.800 | 0.100 | 752.900 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 35.900 | 884.600 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[18]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.600 | 4.000 | 884.600 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 40: MET (25.828 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[21]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 148.200 (P) 160.200 (P) + Arrival:= 909.200 21.200 + + Setup:- 4.772 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 804.428 + Launch Clock:= 21.200 + Data Path:+ 757.400 + Slack:= 25.828 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 18.400 | 398.500 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 4 | 17.400 | 18.100 | 416.600 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y | | A->Y | R | INVx4_ASAP7_75t_SL | 1 | 31.400 | 9.200 | 425.800 | + | cpu/stage1/regfile/FE_OFN1120_n | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 14.500 | 7.500 | 433.300 | + | cpu/stage1/regfile/FE_OFN1214_n | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/g80989/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 5 | 11.100 | 20.300 | 453.600 | + | cpu/stage1/regfile/n_171 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1093_n_171/Y | | A->Y | F | BUFx6f_ASAP7_75t_SL | 8 | 20.000 | 18.900 | 472.500 | + | cpu/stage1/regfile/FE_OFN1071_n_171 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/g79839/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 3 | 18.300 | 18.900 | 491.400 | + | cpu/stage1/regfile/n_311 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC797_n_311/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 3 | 11.900 | 9.500 | 500.900 | + | cpu/stage1/regfile/n_310 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g78360/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.000 | 11.000 | 511.900 | + | cpu/stage1/regfile/n_770 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77522/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 16.100 | 528.000 | + | cpu/stage1/regfile/n_1614 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77116/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 32.500 | 13.400 | 541.400 | + | cpu/stage1/regfile/n_1993 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76985__4319/Y | | A1->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 23.500 | 15.500 | 556.900 | + | cpu/stage1/regfile/n_2124 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76911__7098/Y | | A->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 26.200 | 12.400 | 569.300 | + | cpu/stage1/rs1_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g575__7410/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 25.100 | 20.800 | 590.100 | + | cpu/stage1_rs1[7] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1267__8246/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 16.800 | 606.900 | + | cpu/stage1/pcadder/n_38 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_L | 3 | 16.500 | 12.700 | 619.600 | + | 33_g1502__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_33 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 19.900 | 16.200 | 635.800 | + | 33_g1361__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_148 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 12.200 | 7.300 | 643.100 | + | 33_g1328__2802/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_176 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.700 | 13.400 | 656.500 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | R | BUFx2_ASAP7_75t_SL | 4 | 23.700 | 17.900 | 674.400 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | R | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0/Y | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 2 | 15.300 | 14.300 | 688.700 | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_18 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 25.000 | 19.400 | 708.100 | + | 33_g1280__3680/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_213 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 36.000 | 13.000 | 721.100 | + | 33_g1270__5477/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_220 | | | | | | | | | + | cpu/stage1/pcadder/FE_OFC530_add_18_35_Y_add_17_34 | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 19.700 | 6.900 | 728.000 | + | _Y_add_16_33_n_220/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_221 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NAND2xp5_ASAP7_75t_L | 1 | 10.100 | 10.100 | 738.100 | + | 33_g1261__9945/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_227 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 19.200 | 16.800 | 754.900 | + | 33_g1250__8246/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[21] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g940__7098/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 15.600 | 15.200 | 770.100 | + | cpu/stage1/stage1_pc_mux_to_pc[21] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g347__6260/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 14.900 | 8.500 | 778.600 | + | cpu/stage1/pcreg/n_33 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[21]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 46.100 | 0.000 | 778.600 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 33.200 | 909.200 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[21]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.100 | 6.100 | 909.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 41: MET (26.565 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage3/csr/csr_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.300 (P) 160.800 (P) + Arrival:= 900.300 21.800 + + Setup:- -3.665 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 803.965 + Launch Clock:= 21.800 + Data Path:+ 755.600 + Slack:= 26.565 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.800 | 21.800 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[3]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 50.100 | 71.900 | + | cpu/stage3_inst[3] | | | R | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OCPC1470_stage3_inst_3/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 2 | 10.500 | 4.600 | 76.500 | + | cpu/stage3/ldsel/FE_OCPN1434_stage3_inst_3 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_RC_26_0/Y | | B->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 6.000 | 5.300 | 81.800 | + | cpu/stage3/ldsel/FE_RN_10_0 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/FE_RC_27_0/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 16.200 | 6.500 | 88.300 | + | cpu/stage3/ldsel/n_10 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g208/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 1 | 9.800 | 7.100 | 95.400 | + | cpu/stage3/ldsel/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g205/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 4 | 16.800 | 17.600 | 113.000 | + | cpu/stage3/LdSelect[0] | | | R | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y | | A->Y | F | INVx3_ASAP7_75t_SL | 1 | 16.000 | 6.300 | 119.300 | + | cpu/stage3/ldselmux/n_14 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 9.300 | 7.400 | 126.700 | + | cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 | | | R | (net) | 5 | | | | + | cpu/stage3/ldselmux/g2426/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 10.600 | 12.600 | 139.300 | + | cpu/stage3/ldselmux/n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/FE_OCPC1515_n_30/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 2 | 8.400 | 11.600 | 150.900 | + | cpu/stage3/ldselmux/FE_OCPN1476_n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/g2399/Y | | A2->Y | F | AOI21x1_ASAP7_75t_SL | 7 | 7.800 | 15.700 | 166.600 | + | cpu/stage3/ldselmux/n_62 | | | F | (net) | 7 | | | | + | cpu/stage3/ldselmux/g2354/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 31.000 | 15.700 | 182.300 | + | cpu/stage3/ldselmux/n_92 | | | R | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | F | OAI221xp5_ASAP7_75t_SL | 1 | 25.100 | 15.700 | 198.000 | + | cpu/stage3/wb_dmem[0] | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | F | AO21x1_ASAP7_75t_SL | 3 | 28.200 | 22.300 | 220.300 | + | cpu/wb_data[0] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 4 | 15.500 | 23.200 | 243.500 | + | cpu/stage2/stage2_rs2_data[0] | | | F | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 18.500 | 10.300 | 253.800 | + | cpu/stage2/bselmux/n_6 | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 2 | 25.000 | 23.800 | 277.600 | + | cpu/stage2/stage2_alu_in2[0] | | | R | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 24 | 28.000 | 16.300 | 293.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | F | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 5 | 29.700 | 29.900 | 323.800 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | F | XNOR2xp5_ASAP7_75t_SL | 2 | 33.500 | 25.800 | 349.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | R | MAJIxp5_ASAP7_75t_SL | 2 | 33.200 | 23.900 | 373.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 44.100 | 19.200 | 392.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 15.700 | 408.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 3 | 13.100 | 16.700 | 425.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | F | OAI311xp33_ASAP7_75t_SL | 1 | 14.900 | 9.900 | 435.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 27.900 | 13.600 | 448.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 20.800 | 16.700 | 465.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 11.900 | 14.500 | 479.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 11.000 | 8.800 | 488.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 16.000 | 20.900 | 509.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | R | AOI31xp67_ASAP7_75t_SL | 3 | 15.700 | 15.200 | 524.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 30.500 | 10.200 | 534.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 32.200 | 26.200 | 561.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 20.400 | 17.700 | 578.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | R | NAND2x1_ASAP7_75t_SL | 2 | 13.200 | 10.700 | 589.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 20.400 | 9.300 | 598.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | R | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 36.500 | 16.100 | 614.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 27.700 | 12.200 | 627.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 19.200 | 19.500 | 646.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 16.700 | 10.700 | 657.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1514/Y | | B->Y | R | XNOR2xp5_ASAP7_75t_SL | 1 | 19.400 | 13.200 | 670.500 | + | cpu/stage2/alu/n_318 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5512/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 24.700 | 28.600 | 699.100 | + | dcache_addr[27] | | | R | (net) | 4 | | | | + | cpu/stage3/csr/g168/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 43.500 | 16.500 | 715.600 | + | cpu/stage3/csr/n_27 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2781_n_27/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 65.900 | 61.800 | 777.400 | + | cpu/stage3/csr/FE_PHN2781_n_27 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[27]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 18.300 | 0.000 | 777.400 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 30.900 | 900.300 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[27]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.100 | 1.600 | 900.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 42: MET (26.995 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 151.200 (P) 160.200 (P) + Arrival:= 912.200 21.200 + + Setup:- -3.795 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 815.995 + Launch Clock:= 21.200 + Data Path:+ 767.800 + Slack:= 26.995 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 18.400 | 398.500 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 4 | 17.400 | 18.100 | 416.600 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y | | A->Y | R | INVx4_ASAP7_75t_SL | 1 | 31.400 | 9.200 | 425.800 | + | cpu/stage1/regfile/FE_OFN1120_n | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 14.500 | 7.500 | 433.300 | + | cpu/stage1/regfile/FE_OFN1214_n | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/g80989/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 5 | 11.100 | 20.300 | 453.600 | + | cpu/stage1/regfile/n_171 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1093_n_171/Y | | A->Y | F | BUFx6f_ASAP7_75t_SL | 8 | 20.000 | 18.900 | 472.500 | + | cpu/stage1/regfile/FE_OFN1071_n_171 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/g79839/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 3 | 18.300 | 18.900 | 491.400 | + | cpu/stage1/regfile/n_311 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC797_n_311/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 3 | 11.900 | 9.500 | 500.900 | + | cpu/stage1/regfile/n_310 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g78360/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.000 | 11.000 | 511.900 | + | cpu/stage1/regfile/n_770 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77522/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 16.100 | 528.000 | + | cpu/stage1/regfile/n_1614 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77116/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 32.500 | 13.400 | 541.400 | + | cpu/stage1/regfile/n_1993 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76985__4319/Y | | A1->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 23.500 | 15.500 | 556.900 | + | cpu/stage1/regfile/n_2124 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76911__7098/Y | | A->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 26.200 | 12.400 | 569.300 | + | cpu/stage1/rs1_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g575__7410/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 25.100 | 20.800 | 590.100 | + | cpu/stage1_rs1[7] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1267__8246/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 16.800 | 606.900 | + | cpu/stage1/pcadder/n_38 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_L | 3 | 16.500 | 12.700 | 619.600 | + | 33_g1502__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_33 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 19.900 | 16.200 | 635.800 | + | 33_g1361__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_148 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 12.200 | 7.300 | 643.100 | + | 33_g1328__2802/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_176 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.700 | 13.400 | 656.500 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | R | BUFx2_ASAP7_75t_SL | 4 | 23.700 | 18.000 | 674.500 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | R | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_PSC4087_FE_OCPN1494_add_18_3 | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 15.300 | 16.300 | 690.800 | + | 5_Y_add_17_34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_PSN4087_FE_OCPN1494_add_18_3 | | | R | (net) | 1 | | | | + | 5_Y_add_17_34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 16.400 | 14.800 | 705.600 | + | 33_g1300__7482/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[8] | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g952__7410/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 14.000 | 719.600 | + | cpu/stage1/stage1_pc_mux_to_pc[8] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g374__5107/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.100 | 14.400 | 734.000 | + | cpu/stage1/pcreg/n_6 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2856_n_6/Y | | A->Y | F | HB4xp67_ASAP7_75t_SL | 1 | 82.800 | 55.000 | 789.000 | + | cpu/stage1/pcreg/FE_PHN2856_n_6 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[8]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 19.500 | 0.000 | 789.000 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 36.200 | 912.200 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[8]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.000 | 9.100 | 912.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 43: MET (27.008 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[22]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 149.000 (P) 160.200 (P) + Arrival:= 910.000 21.200 + + Setup:- 4.792 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 805.208 + Launch Clock:= 21.200 + Data Path:+ 757.000 + Slack:= 27.008 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 9.000 | 409.400 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/g409__1617/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 3 | 13.000 | 17.200 | 426.600 | + | cpu/stage1/FE_OFN1186_stage1_inst_19 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC1169_stage1_inst_19/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 16.400 | 7.700 | 434.300 | + | cpu/stage1/regfile/n_192 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1171_stage1_inst_19/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 2 | 11.600 | 5.500 | 439.800 | + | cpu/stage1/regfile/FE_OFN1188_stage1_inst_19 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g80405/Y | | A->Y | R | AND2x6_ASAP7_75t_SL | 7 | 7.200 | 18.900 | 458.700 | + | cpu/stage1/regfile/n_231 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g79846/Y | | B->Y | R | AND2x6_ASAP7_75t_SL | 9 | 22.600 | 24.700 | 483.400 | + | cpu/stage1/regfile/n_300 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/FE_OFC1204_n_300/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 6 | 28.500 | 13.900 | 497.300 | + | cpu/stage1/regfile/n_299 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g77334/Y | | B->Y | R | AOI21xp5_ASAP7_75t_SL | 1 | 26.300 | 18.800 | 516.100 | + | cpu/stage1/regfile/n_1795 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77024/Y | | B->Y | F | NOR3x1_ASAP7_75t_SL | 1 | 32.100 | 16.200 | 532.300 | + | cpu/stage1/regfile/n_2085 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76910__8246/Y | | C->Y | R | NAND4xp75_ASAP7_75t_SL | 1 | 24.200 | 16.400 | 548.700 | + | cpu/stage1/rs1_mux_data[1] | | | R | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g556__6783/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 2 | 26.900 | 22.400 | 571.100 | + | cpu/stage1_rs1[1] | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/g1276__9945/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 2 | 20.900 | 18.300 | 589.400 | + | cpu/stage1/pcadder/n_32 | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 17.900 | 10.000 | 599.400 | + | 33_g1433__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_98 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | R | OAI21x1_ASAP7_75t_SL | 2 | 17.200 | 12.600 | 612.000 | + | 33_g1356__4319/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_153 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | F | NAND2x1p5_ASAP7_75t_SL | 1 | 21.700 | 5.400 | 617.400 | + | 33_g1335__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_169 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 3 | 11.000 | 10.000 | 627.400 | + | 33_g1332__8246/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_172 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AND2x2_ASAP7_75t_SL | 2 | 17.100 | 16.100 | 643.500 | + | 33_g1324__5526/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_180 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 11.900 | 10.400 | 653.900 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | F | BUFx2_ASAP7_75t_SL | 4 | 17.400 | 17.800 | 671.700 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | F | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0/Y | | A2->Y | R | OAI21x1_ASAP7_75t_SL | 2 | 12.700 | 19.000 | 690.700 | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_18 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | AOI21xp5_ASAP7_75t_SL | 2 | 36.900 | 17.600 | 708.300 | + | 33_g1280__3680/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_213 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_SL | 2 | 30.500 | 12.800 | 721.100 | + | 33_g1270__5477/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_220 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 22.800 | 12.500 | 733.600 | + | 33_g1255__5115/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_233 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 20.500 | 19.000 | 752.600 | + | 33_g1245__3680/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[22] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g936__2802/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 22.000 | 16.800 | 769.400 | + | cpu/stage1/stage1_pc_mux_to_pc[22] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g378__5526/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 15.500 | 8.800 | 778.200 | + | cpu/stage1/pcreg/n_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[22]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 46.400 | 0.100 | 778.200 | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 34.000 | 910.000 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[22]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.200 | 6.900 | 910.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 44: MET (27.746 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[11]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[11]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 149.100 (P) 160.200 (P) + Arrival:= 910.100 21.200 + + Setup:- 3.154 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 806.946 + Launch Clock:= 21.200 + Data Path:+ 758.000 + Slack:= 27.746 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 18.400 | 398.500 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 4 | 17.400 | 18.100 | 416.600 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y | | A->Y | R | INVx4_ASAP7_75t_SL | 1 | 31.400 | 9.200 | 425.800 | + | cpu/stage1/regfile/FE_OFN1120_n | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 14.500 | 7.500 | 433.300 | + | cpu/stage1/regfile/FE_OFN1214_n | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/g80989/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 5 | 11.100 | 20.300 | 453.600 | + | cpu/stage1/regfile/n_171 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1093_n_171/Y | | A->Y | F | BUFx6f_ASAP7_75t_SL | 8 | 20.000 | 18.900 | 472.500 | + | cpu/stage1/regfile/FE_OFN1071_n_171 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/g79839/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 3 | 18.300 | 18.900 | 491.400 | + | cpu/stage1/regfile/n_311 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC797_n_311/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 3 | 11.900 | 9.500 | 500.900 | + | cpu/stage1/regfile/n_310 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g78360/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.000 | 11.000 | 511.900 | + | cpu/stage1/regfile/n_770 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77522/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 16.100 | 528.000 | + | cpu/stage1/regfile/n_1614 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77116/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 32.500 | 13.400 | 541.400 | + | cpu/stage1/regfile/n_1993 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76985__4319/Y | | A1->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 23.500 | 15.500 | 556.900 | + | cpu/stage1/regfile/n_2124 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76911__7098/Y | | A->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 26.200 | 12.400 | 569.300 | + | cpu/stage1/rs1_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g575__7410/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 25.100 | 20.800 | 590.100 | + | cpu/stage1_rs1[7] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1267__8246/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 16.800 | 606.900 | + | cpu/stage1/pcadder/n_38 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_L | 3 | 16.500 | 12.700 | 619.600 | + | 33_g1502__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_33 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 19.900 | 16.200 | 635.800 | + | 33_g1361__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_148 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 12.200 | 7.300 | 643.100 | + | 33_g1328__2802/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_176 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.700 | 13.400 | 656.500 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | R | BUFx2_ASAP7_75t_SL | 4 | 23.700 | 17.600 | 674.100 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | R | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 2 | 15.300 | 16.000 | 690.100 | + | 33_g1302__4733/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_199 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 28.000 | 18.200 | 708.300 | + | 33_g1291__8246/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_206 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 32.900 | 12.500 | 720.800 | + | 33_g1271__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_219 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 21.700 | 17.300 | 738.100 | + | 33_g1260__9315/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[11] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g941__6131/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 15.800 | 15.200 | 753.300 | + | cpu/stage1/stage1_pc_mux_to_pc[11] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g377__8428/Y | | B->Y | R | NOR2xp33_ASAP7_75t_L | 1 | 14.700 | 9.500 | 762.800 | + | cpu/stage1/pcreg/n_3 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2868_n_3/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 44.100 | 16.400 | 779.200 | + | cpu/stage1/pcreg/FE_PHN2868_n_3 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[11]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 12.100 | 0.000 | 779.200 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 34.100 | 910.100 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[11]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 52.700 | 7.000 | 910.100 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 45: MET (28.315 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[23]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 125.100 (P) 160.200 (P) + Arrival:= 886.100 21.200 + + Setup:- 1.185 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 784.915 + Launch Clock:= 21.200 + Data Path:+ 735.400 + Slack:= 28.315 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 6 | 7.800 | 24.500 | 445.400 | + | cpu/stage1_inst[20] | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 4 | 31.800 | 30.600 | 476.000 | + | cpu/stage1/regfile/n_237 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 13 | 56.400 | 35.900 | 511.900 | + | cpu/stage1/regfile/n_236 | | | R | (net) | 13 | | | | + | cpu/stage1/regfile/FE_OFC643_n_237/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 59.300 | 5.400 | 517.300 | + | cpu/stage1/regfile/FE_OFN834_n_237 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g79821/Y | | B->Y | R | NOR2xp33_ASAP7_75t_L | 6 | 18.100 | 93.000 | 610.300 | + | cpu/stage1/regfile/n_332 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g77539/Y | | B1->Y | F | AOI222xp33_ASAP7_75t_SL | 1 | 196.500 | 33.700 | 644.000 | + | cpu/stage1/regfile/n_1597 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77131/Y | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 1 | 80.700 | 16.500 | 660.500 | + | cpu/stage1/regfile/n_1978 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77084/Y | | C->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 37.400 | 12.200 | 672.700 | + | cpu/stage1/regfile/n_2025 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76998__5115/Y | | A->Y | F | AND5x1_ASAP7_75t_SL | 1 | 66.500 | 19.100 | 691.800 | + | cpu/stage1/regfile/n_2111 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76936__1705/Y | | C->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 12.400 | 14.900 | 706.700 | + | cpu/stage1/rs2_mux_data[23] | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3936_rs2_mux_data_23/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 48.600 | 25.200 | 731.900 | + | cpu/stage1/FE_PHN3936_rs2_mux_data_23 | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g559__1617/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 28.700 | 18.100 | 750.000 | + | cpu/stage1_rs2[23] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g444__4733/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 13.700 | 6.600 | 756.600 | + | cpu/s1_to_s2_rs2/n_7 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[23]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 61.200 | 0.000 | 756.600 | + +-------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.400 | 886.100 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[23]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 5.500 | 886.100 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 46: MET (28.343 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 126.400 (P) 160.200 (P) + Arrival:= 887.400 21.200 + + Setup:- -3.643 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.043 + Launch Clock:= 21.200 + Data Path:+ 741.500 + Slack:= 28.343 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1545/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 2 | 23.000 | 15.000 | 580.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_210 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1540/Y | | A1->Y | F | AOI21xp5_ASAP7_75t_SL | 2 | 9.100 | 12.100 | 592.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_215 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1533/Y | | A2->Y | R | OAI21xp5_ASAP7_75t_SL | 1 | 22.800 | 14.500 | 607.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_222 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1528/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 31.300 | 17.000 | 624.200 | + | cpu/stage2/alu/n_310 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5523/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 19.300 | 31.100 | 655.300 | + | dcache_addr[19] | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g440__6161/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 51.300 | 8.200 | 663.500 | + | cpu/s2_to_s3_alu/n_11 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC3575_n_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 60.000 | 32.100 | 695.600 | + | cpu/s2_to_s3_alu/FE_PHN3575_n_11 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2757_n_11/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 15.400 | 67.100 | 762.700 | + | cpu/s2_to_s3_alu/FE_PHN2757_n_11 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[19]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 22.600 | 0.100 | 762.700 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 40.600 | 887.400 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 62.800 | 9.700 | 887.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 47: MET (29.089 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 124.900 (P) 160.200 (P) + Arrival:= 885.900 21.200 + + Setup:- 6.111 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.789 + Launch Clock:= 21.200 + Data Path:+ 729.500 + Slack:= 29.089 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 28.700 | 501.300 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79863/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 28 | 49.900 | 84.300 | 585.600 | + | cpu/stage1/regfile/n_272 | | | F | (net) | 28 | | | | + | cpu/stage1/regfile/g78269/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 132.400 | 29.500 | 615.100 | + | cpu/stage1/regfile/n_874 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77490/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 15.800 | 15.400 | 630.500 | + | cpu/stage1/regfile/n_1646 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77181/Y | | A->Y | R | AND5x1_ASAP7_75t_SL | 1 | 59.300 | 25.400 | 655.900 | + | cpu/stage1/regfile/n_1937 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77009/Y | | A2->Y | R | OA211x2_ASAP7_75t_SL | 1 | 14.300 | 16.300 | 672.200 | + | cpu/stage1/regfile/n_2100 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76931__5526/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 11.300 | 24.900 | 697.100 | + | cpu/stage1/rs2_mux_data[27] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g558__3680/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 63.300 | 22.400 | 719.500 | + | cpu/stage1/data2sel_s1/FE_PHN3592_stage1_rs2_27 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3592_stage1_rs2_27/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 12.100 | 12.700 | 732.200 | + | cpu/stage1_rs2[27] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3938_stage1_rs2_27/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 6.300 | 11.400 | 743.600 | + | cpu/s1_to_s2_rs2/FE_PHN3938_stage1_rs2_27 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g425__5477/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 6.200 | 7.100 | 750.700 | + | cpu/s1_to_s2_rs2/n_26 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[27]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 59.100 | 0.100 | 750.700 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.200 | 885.900 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[27]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 5.300 | 885.900 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 48: MET (29.840 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[24]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[24]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 126.300 (P) 160.200 (P) + Arrival:= 887.300 21.200 + + Setup:- -3.740 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.040 + Launch Clock:= 21.200 + Data Path:+ 740.000 + Slack:= 29.840 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.700 | 624.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1522/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 22.200 | 16.200 | 640.600 | + | cpu/stage2/alu/n_315 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5503/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 17.700 | 29.300 | 669.900 | + | dcache_addr[24] | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g445__1666/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 47.700 | 11.900 | 681.800 | + | cpu/s2_to_s3_alu/n_6 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2770_n_6/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 64.300 | 79.400 | 761.200 | + | cpu/s2_to_s3_alu/FE_PHN2770_n_6 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[24]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 22.000 | 0.000 | 761.200 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 40.500 | 887.300 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[24]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 62.800 | 9.600 | 887.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 49: MET (30.163 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[23]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 126.400 (P) 160.200 (P) + Arrival:= 887.400 21.200 + + Setup:- -3.463 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.863 + Launch Clock:= 21.200 + Data Path:+ 739.500 + Slack:= 30.163 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1542/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 15.400 | 7.900 | 590.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_213 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1536/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 2 | 11.900 | 22.500 | 612.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_219 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1530/Y | | A1->Y | F | AOI21xp5_ASAP7_75t_SL | 1 | 59.100 | 14.300 | 626.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_225 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1527/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 30.000 | 11.400 | 638.200 | + | cpu/stage2/alu/n_314 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5526/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 19.600 | 29.300 | 667.500 | + | dcache_addr[23] | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g444__2346/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 48.300 | 11.800 | 679.300 | + | cpu/s2_to_s3_alu/n_7 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2762_n_7/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 64.600 | 81.400 | 760.700 | + | cpu/s2_to_s3_alu/FE_PHN2762_n_7 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[23]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 24.000 | 0.100 | 760.700 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 40.600 | 887.400 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[23]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 62.800 | 9.700 | 887.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 50: MET (30.203 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage3/csr/csr_reg[14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 140.200 (P) 160.800 (P) + Arrival:= 901.200 21.800 + + Setup:- -1.203 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 802.403 + Launch Clock:= 21.800 + Data Path:+ 750.400 + Slack:= 30.203 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.800 | 21.800 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[3]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 50.100 | 71.900 | + | cpu/stage3_inst[3] | | | R | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OCPC1470_stage3_inst_3/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 2 | 10.500 | 4.600 | 76.500 | + | cpu/stage3/ldsel/FE_OCPN1434_stage3_inst_3 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_RC_26_0/Y | | B->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 6.000 | 5.300 | 81.800 | + | cpu/stage3/ldsel/FE_RN_10_0 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/FE_RC_27_0/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 16.200 | 6.500 | 88.300 | + | cpu/stage3/ldsel/n_10 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g208/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 1 | 9.800 | 7.100 | 95.400 | + | cpu/stage3/ldsel/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g205/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 4 | 16.800 | 17.600 | 113.000 | + | cpu/stage3/LdSelect[0] | | | R | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y | | A->Y | F | INVx3_ASAP7_75t_SL | 1 | 16.000 | 6.300 | 119.300 | + | cpu/stage3/ldselmux/n_14 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 9.300 | 7.400 | 126.700 | + | cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 | | | R | (net) | 5 | | | | + | cpu/stage3/ldselmux/g2426/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 10.600 | 12.600 | 139.300 | + | cpu/stage3/ldselmux/n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/FE_OCPC1515_n_30/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 2 | 8.400 | 11.600 | 150.900 | + | cpu/stage3/ldselmux/FE_OCPN1476_n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/g2399/Y | | A2->Y | F | AOI21x1_ASAP7_75t_SL | 7 | 7.800 | 15.700 | 166.600 | + | cpu/stage3/ldselmux/n_62 | | | F | (net) | 7 | | | | + | cpu/stage3/ldselmux/g2354/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 31.000 | 15.700 | 182.300 | + | cpu/stage3/ldselmux/n_92 | | | R | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | F | OAI221xp5_ASAP7_75t_SL | 1 | 25.100 | 15.700 | 198.000 | + | cpu/stage3/wb_dmem[0] | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | F | AO21x1_ASAP7_75t_SL | 3 | 28.200 | 22.300 | 220.300 | + | cpu/wb_data[0] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 4 | 15.500 | 23.200 | 243.500 | + | cpu/stage2/stage2_rs2_data[0] | | | F | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 18.500 | 10.300 | 253.800 | + | cpu/stage2/bselmux/n_6 | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 2 | 25.000 | 23.800 | 277.600 | + | cpu/stage2/stage2_alu_in2[0] | | | R | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 24 | 28.000 | 17.600 | 295.200 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | F | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC696_n_30/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 14 | 29.900 | 38.500 | 333.700 | + | cpu/stage2/alu/FE_OFN871_n_30 | | | R | (net) | 14 | | | | + | cpu/stage2/alu/FE_OFC700_n_30/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 71.900 | 6.300 | 340.000 | + | cpu/stage2/alu/FE_OFN875_n_30 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC702_n_30/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 16 | 22.000 | 44.500 | 384.500 | + | cpu/stage2/alu/FE_OFN877_n_30 | | | R | (net) | 16 | | | | + | cpu/stage2/alu/FE_OFC704_n_30/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 16 | 86.900 | 36.600 | 421.100 | + | cpu/stage2/alu/FE_OFN879_n_30 | | | R | (net) | 16 | | | | + | cpu/stage2/alu/srl_33_21_g1794/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 46.600 | 9.400 | 430.500 | + | cpu/stage2/alu/srl_33_21_n_34 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/srl_33_21_g1788/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 3 | 41.800 | 30.600 | 461.100 | + | cpu/stage2/alu/srl_33_21_n_55 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/srl_33_21_g1769/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 73.700 | 11.900 | 473.000 | + | cpu/stage2/alu/srl_33_21_n_67 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/srl_33_21_g1765/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 2 | 43.800 | 23.500 | 496.500 | + | cpu/stage2/alu/srl_33_21_n_79 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/srl_33_21_g1731/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 2 | 67.100 | 21.200 | 517.700 | + | cpu/stage2/alu/srl_33_21_n_112 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/srl_33_21_g1706/Y | | A2->Y | R | OAI22xp5_ASAP7_75t_SL | 1 | 40.400 | 19.100 | 536.800 | + | cpu/stage2/alu/n_210 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5562/Y | | A1->Y | F | AOI222xp33_ASAP7_75t_SL | 1 | 37.000 | 14.600 | 551.400 | + | cpu/stage2/alu/n_159 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5515/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 1 | 84.200 | 22.900 | 574.300 | + | cpu/stage2/alu/FE_PHN4114_dcache_addr_14 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/FE_PHC4114_dcache_addr_14/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 2 | 40.900 | 50.200 | 624.500 | + | dcache_addr[14] | | | R | (net) | 2 | | | | + | cpu/FE_PHC2732_dcache_addr_14/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 3 | 55.700 | 48.900 | 673.400 | + | cpu/FE_PHN2732_dcache_addr_14 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/g179/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 78.500 | 11.400 | 684.800 | + | cpu/stage3/csr/FE_PHN2800_n_16 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2800_n_16/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 56.900 | 87.400 | 772.200 | + | cpu/stage3/csr/n_16 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[14]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 33.800 | 0.600 | 772.200 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 31.800 | 901.200 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[14]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.300 | 2.500 | 901.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + diff --git a/build/par-rundir/timingReports/riscv_top_postRoute_all_hold.tarpt b/build/par-rundir/timingReports/riscv_top_postRoute_all_hold.tarpt new file mode 100644 index 0000000..6c0d76f --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute_all_hold.tarpt @@ -0,0 +1,3683 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:14 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### +Path 1: VIOLATED (-0.176 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[20][17]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[17]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[20][17]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 111.400 (P) 76.500 (P) + Arrival:= 27.536 -7.364 + + Hold:+ 11.576 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 139.112 + Launch Clock:= -7.364 + Data Path:+ 146.300 + Slack:= -0.176 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 25.200 | -7.364 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[17]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 41.500 | 23.000 | 15.636 | + | cpu/stage3_alu[17] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1148/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 9.800 | 10.100 | 25.736 | + | cpu/stage3/wbselmux/n_13 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1112/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 8.000 | 8.900 | 34.636 | + | cpu/wb_data[17] | | | R | (net) | 3 | | | | + | cpu/stage1/FE_PHC2718_wb_data_17/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 7.100 | 27.200 | 61.836 | + | cpu/stage1/FE_PHN2718_wb_data_17 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3030_wb_data_17/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 11.700 | 26.600 | 88.436 | + | cpu/stage1/FE_PHN3030_wb_data_17 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OCPC1492_wb_data_17/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 3 | 9.400 | 14.000 | 102.436 | + | cpu/stage1/FE_OCPN1453_wb_data_17 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC899_wb_data_17/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 17.700 | 3.700 | 106.136 | + | cpu/stage1/regfile/FE_OFN1030_wb_data_17 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC900_wb_data_17/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 5 | 7.500 | 10.000 | 116.136 | + | cpu/stage1/regfile/FE_OFN1031_wb_data_17 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/g81398/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 8 | 17.900 | 22.800 | 138.936 | + | cpu/stage1/regfile/n_101 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/mem_reg[20][17]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 8 | 45.700 | 1.000 | 138.936 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 30.300 | -19.164 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.600 | 12.600 | -6.564 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_56 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00036/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 16.900 | 34.100 | 27.536 | + | cpu/stage1/regfile/CTS_57 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[20][17]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 48.500 | 19.800 | 27.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 2: VIOLATED (-0.060 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[13]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[26][13]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[13]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.800 (P) 84.300 (P) + Arrival:= -3.064 0.436 + + Hold:+ 7.560 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.496 + Launch Clock:= 0.436 + Data Path:+ 104.000 + Slack:= -0.060 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 23.800 | -28.464 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 23.200 | 7.300 | -21.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_5 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00018/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.800 | 21.600 | 0.436 | + | cpu/stage1/regfile/CTS_4 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[26][13]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_L | 1 | 15.800 | 22.400 | 22.836 | + | cpu/stage1/regfile/mem[26][13] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC1730_mem_26_13/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 2 | 7.200 | 28.700 | 51.536 | + | cpu/stage1/regfile/FE_PHN1730_mem_26_13 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77975/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 17.400 | 4.900 | 56.436 | + | cpu/stage1/regfile/n_1164 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77163/Y | | E->Y | F | AND5x1_ASAP7_75t_SL | 1 | 8.800 | 10.200 | 66.636 | + | cpu/stage1/regfile/n_1950 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76940__6131/Y | | A2->Y | R | OAI211xp5_ASAP7_75t_SL | 1 | 5.000 | 20.700 | 87.336 | + | cpu/stage1/rs2_mux_data[13] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g563__8246/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 24.400 | 11.800 | 99.136 | + | cpu/stage1_rs2[13] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g419__9945/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 6.400 | 5.300 | 104.436 | + | cpu/s1_to_s2_rs2/n_32 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[13]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.400 | 0.100 | 104.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.500 | -3.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[13]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.700 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 3: MET (0.155 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[16]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[30][16]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[16]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 77.800 (P) 86.100 (P) + Arrival:= -6.064 2.236 + + Hold:+ 7.545 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 101.481 + Launch Clock:= 2.236 + Data Path:+ 99.400 + Slack:= 0.155 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 22.300 | -51.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 19.400 | 25.300 | -26.564 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 20.300 | 7.600 | -18.964 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_48 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00006/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 7.300 | 21.200 | 2.236 | + | cpu/stage1/regfile/CTS_49 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[30][16]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 18.600 | 20.800 | 23.036 | + | cpu/stage1/regfile/mem[30][16] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2195_mem_30_16/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.900 | 33.000 | 56.036 | + | cpu/stage1/regfile/FE_PHN2195_mem_30_16 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77581/Y | | B1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 19.900 | 4.900 | 60.936 | + | cpu/stage1/regfile/n_1555 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77069/Y | | E->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 9.000 | 6.900 | 67.836 | + | cpu/stage1/regfile/n_2040 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77003/Y | | B->Y | F | AOI211xp5_ASAP7_75t_SL | 1 | 7.000 | 5.100 | 72.936 | + | cpu/stage1/regfile/n_2106 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76905__3680/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 7.500 | 12.900 | 85.836 | + | cpu/stage1/rs2_mux_data[16] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g555__8428/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 22.400 | 10.700 | 96.536 | + | cpu/stage1_rs2[16] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g436__1705/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.000 | 5.100 | 101.636 | + | cpu/s1_to_s2_rs2/n_15 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[16]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.100 | 0.100 | 101.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 21.500 | -6.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[16]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 36.700 | 2.700 | -6.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 4: MET (0.188 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[5]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[10][5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[5]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.800 (P) 82.700 (P) + Arrival:= -3.064 -1.164 + + Hold:+ 7.812 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.748 + Launch Clock:= -1.164 + Data Path:+ 106.100 + Slack:= 0.188 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 23.600 | -30.464 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.800 | 7.000 | -23.464 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_37 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00066/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.100 | 22.300 | -1.164 | + | cpu/stage1/regfile/CTS_36 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[10][5]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 20.000 | 21.200 | 20.036 | + | cpu/stage1/regfile/mem[10][5] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC1961_mem_10_5/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 9.300 | 30.700 | 50.736 | + | cpu/stage1/regfile/FE_PHN1961_mem_10_5 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC2891_mem_10_5/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 1 | 16.300 | 26.900 | 77.636 | + | cpu/stage1/regfile/FE_PHN2891_mem_10_5 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77660/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 10.200 | 4.900 | 82.536 | + | cpu/stage1/regfile/n_1480 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76954__2398/Y | | D->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 7.600 | 8.300 | 90.836 | + | cpu/stage1/rs2_mux_data[5] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g549__6417/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 10.000 | 9.900 | 100.736 | + | cpu/stage1_rs2[5] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g424__6417/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.500 | 4.200 | 104.936 | + | cpu/s1_to_s2_rs2/n_27 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[5]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 7.300 | 0.000 | 104.936 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.500 | -3.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[5]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.700 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 5: MET (0.296 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[9]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[11][9]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.900 (P) 83.200 (P) + Arrival:= -2.964 -0.664 + + Hold:+ 7.704 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.740 + Launch Clock:= -0.664 + Data Path:+ 105.700 + Slack:= 0.296 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 22.400 | -29.864 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 22.000 | 7.200 | -22.664 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_19 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00063/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.500 | 22.000 | -0.664 | + | cpu/stage1/regfile/CTS_20 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[11][9]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 17.700 | 19.200 | 18.536 | + | cpu/stage1/regfile/mem[11][9] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3888_mem_11_9/Y | | A->Y | R | HB1xp67_ASAP7_75t_SRAM | 1 | 6.500 | 11.900 | 30.436 | + | cpu/stage1/regfile/FE_PHN3888_mem_11_9 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC1843_mem_11_9/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.300 | 31.800 | 62.236 | + | cpu/stage1/regfile/FE_PHN1843_mem_11_9 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77635/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 18.400 | 4.500 | 66.736 | + | cpu/stage1/regfile/n_1505 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77092/Y | | A->Y | F | AND5x1_ASAP7_75t_SL | 1 | 6.000 | 7.600 | 74.336 | + | cpu/stage1/regfile/n_2017 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76891__9945/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 5.000 | 8.400 | 82.736 | + | cpu/stage1/rs2_mux_data[9] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g572__9945/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 13.400 | 10.800 | 93.536 | + | cpu/stage1_rs2[9] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3585_stage1_rs2_9/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 6.500 | 6.800 | 100.336 | + | cpu/s1_to_s2_rs2/FE_PHN3585_stage1_rs2_9 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g429__4319/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 4.700 | 105.036 | + | cpu/s1_to_s2_rs2/n_22 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[9]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 8.200 | 0.100 | 105.036 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.600 | -2.964 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[9]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.800 | -2.964 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 6: MET (0.304 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[17]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[25][17]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[17]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 81.200 (P) 81.500 (P) + Arrival:= -2.664 -2.364 + + Hold:+ 7.796 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 105.132 + Launch Clock:= -2.364 + Data Path:+ 107.800 + Slack:= 0.304 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 22.100 | -30.164 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 21.900 | 7.000 | -23.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00021/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.100 | 20.800 | -2.364 | + | cpu/stage1/regfile/CTS_8 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[25][17]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 15.800 | 20.800 | 18.436 | + | cpu/stage1/regfile/mem[25][17] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2335_mem_25_17/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 9.200 | 31.500 | 49.936 | + | cpu/stage1/regfile/FE_PHN2335_mem_25_17 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC2899_mem_25_17/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 1 | 17.600 | 18.200 | 68.136 | + | cpu/stage1/regfile/FE_PHN2899_mem_25_17 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77571/Y | | B1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 9.600 | 5.200 | 73.336 | + | cpu/stage1/regfile/n_1565 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77185/Y | | C->Y | F | AND4x1_ASAP7_75t_SL | 1 | 9.200 | 6.700 | 80.036 | + | cpu/stage1/regfile/n_1933 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76946__9315/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 4.000 | 10.500 | 90.536 | + | cpu/stage1/rs2_mux_data[17] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g553__6260/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 18.000 | 10.500 | 101.036 | + | cpu/stage1_rs2[17] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g438__8246/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.900 | 4.400 | 105.436 | + | cpu/s1_to_s2_rs2/n_13 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[17]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 7.500 | 0.100 | 105.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.900 | -2.664 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[17]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.600 | 6.100 | -2.664 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 7: MET (0.461 ps) Hold Check with Pin cpu/s2_to_s3_pc/register_reg[23]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_pc/register_reg[23]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 83.800 (P) 73.600 (P) + Arrival:= -0.064 -10.264 + + Hold:+ 8.039 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 107.975 + Launch Clock:= -10.264 + Data Path:+ 118.700 + Slack:= 0.461 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.100 | -32.164 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.200 | 21.900 | -10.264 | + | NST/GCLK | | | | | | | | | + | cpu/s1_to_s2_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_pc/register_reg[23]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.700 | 21.700 | 11.436 | + | cpu/stage2_pc[23] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2618_stage2_pc_23/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.700 | 32.200 | 43.636 | + | cpu/FE_PHN2618_stage2_pc_23 | | | R | (net) | 2 | | | | + | cpu/s2_to_s3_pc/FE_PHC3328_stage2_pc_23/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 18.900 | 31.900 | 75.536 | + | cpu/s2_to_s3_pc/FE_PHN3328_stage2_pc_23 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3599_stage2_pc_23/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 14.400 | 28.000 | 103.536 | + | cpu/s2_to_s3_pc/FE_PHN3599_stage2_pc_23 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/g444__5115/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 10.300 | 4.900 | 108.436 | + | cpu/s2_to_s3_pc/n_7 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_pc/register_reg[23]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 8.700 | 0.100 | 108.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.000 | -26.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 25.100 | 26.500 | -0.064 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[23]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 42.800 | 8.500 | -0.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 8: MET (0.476 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[10]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[27][10]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[10]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.900 (P) 85.700 (P) + Arrival:= -2.964 1.836 + + Hold:+ 7.824 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.860 + Launch Clock:= 1.836 + Data Path:+ 103.500 + Slack:= 0.476 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 24.400 | -27.864 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 23.300 | 8.000 | -19.864 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00015/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 7.800 | 21.700 | 1.836 | + | cpu/stage1/regfile/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[27][10]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 15.800 | 20.100 | 21.936 | + | cpu/stage1/regfile/mem[27][10] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2338_mem_27_10/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.300 | 30.200 | 52.136 | + | cpu/stage1/regfile/FE_PHN2338_mem_27_10 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC2970_mem_27_10/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 1 | 15.900 | 16.400 | 68.536 | + | cpu/stage1/regfile/FE_PHN2970_mem_27_10 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77418/Y | | C2->Y | F | AOI222xp33_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 76.436 | + | cpu/stage1/regfile/n_1722 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76933__3680/Y | | C->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 10.000 | 13.400 | 89.836 | + | cpu/stage1/rs2_mux_data[10] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g570__6161/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 20.100 | 11.400 | 101.236 | + | cpu/stage1_rs2[10] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g431__5526/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 6.300 | 4.100 | 105.336 | + | cpu/s1_to_s2_rs2/n_20 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[10]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 7.100 | 0.000 | 105.336 | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.600 | -2.964 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[10]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.800 | -2.964 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 9: MET (0.585 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[4][26]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[26]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[4][26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 102.300 (P) 76.600 (P) + Arrival:= 18.436 -7.264 + + Hold:+ 7.315 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 125.751 + Launch Clock:= -7.264 + Data Path:+ 133.600 + Slack:= 0.585 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 25.300 | -7.264 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[26]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 41.500 | 22.000 | 14.736 | + | cpu/stage3_alu[26] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1154/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 1 | 8.300 | 8.100 | 22.836 | + | cpu/stage3/wbselmux/n_7 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1138/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 1 | 4.600 | 6.900 | 29.736 | + | cpu/stage3/wbselmux/n_23 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1095/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 6.200 | 7.900 | 37.636 | + | cpu/wb_data[26] | | | R | (net) | 3 | | | | + | cpu/FE_PHC3919_wb_data_26/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 6.200 | 6.900 | 44.536 | + | cpu/FE_PHN3919_wb_data_26 | | | R | (net) | 1 | | | | + | cpu/FE_PHC3514_wb_data_26/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 1 | 4.000 | 29.500 | 74.036 | + | cpu/FE_PHN3514_wb_data_26 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC2715_wb_data_26/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 19.800 | 27.900 | 101.936 | + | cpu/stage1/FE_PHN2715_wb_data_26 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC908_wb_data_26/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 7 | 8.400 | 19.300 | 121.236 | + | cpu/stage1/FE_OFN1039_wb_data_26 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g51144/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 29.700 | 5.100 | 126.336 | + | cpu/stage1/regfile/n_18 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/mem_reg[4][26]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 12.800 | 0.000 | 126.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 29.100 | -20.364 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.600 | 10.500 | -9.864 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_62 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00084/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 12.300 | 28.300 | 18.436 | + | cpu/stage1/regfile/CTS_63 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[4][26]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 25.300 | 10.200 | 18.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 10: MET (0.588 ps) Hold Check with Pin cpu/s2_to_s3_pc/register_reg[22]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_pc/register_reg[22]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 83.700 (P) 73.600 (P) + Arrival:= -0.164 -10.264 + + Hold:+ 8.012 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 107.848 + Launch Clock:= -10.264 + Data Path:+ 118.700 + Slack:= 0.588 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.100 | -32.164 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.200 | 21.900 | -10.264 | + | NST/GCLK | | | | | | | | | + | cpu/s1_to_s2_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_pc/register_reg[22]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.700 | 21.800 | 11.536 | + | cpu/stage2_pc[22] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2615_stage2_pc_22/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.800 | 31.900 | 43.436 | + | cpu/FE_PHN2615_stage2_pc_22 | | | R | (net) | 2 | | | | + | cpu/s2_to_s3_pc/FE_PHC3329_stage2_pc_22/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 18.400 | 31.500 | 74.936 | + | cpu/s2_to_s3_pc/FE_PHN3329_stage2_pc_22 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3692_stage2_pc_22/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 14.000 | 28.500 | 103.436 | + | cpu/s2_to_s3_pc/FE_PHN3692_stage2_pc_22 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/g443__1881/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 11.100 | 5.000 | 108.436 | + | cpu/s2_to_s3_pc/n_8 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_pc/register_reg[22]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.000 | 0.000 | 108.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.000 | -26.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 25.100 | 26.400 | -0.164 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[22]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 42.800 | 8.400 | -0.164 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 11: MET (0.614 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[4]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[8][4]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[4]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 79.300 (P) 80.700 (P) + Arrival:= -4.564 -3.164 + + Hold:+ 8.786 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.222 + Launch Clock:= -3.164 + Data Path:+ 108.000 + Slack:= 0.614 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 21.100 | -31.164 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 21.700 | 7.000 | -24.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_23 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00072/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.100 | 21.000 | -3.164 | + | cpu/stage1/regfile/CTS_24 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[8][4]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 17.700 | 20.700 | 17.536 | + | cpu/stage1/regfile/mem[8][4] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2125_mem_8_4/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.900 | 30.800 | 48.336 | + | cpu/stage1/regfile/FE_PHN2125_mem_8_4 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC2892_mem_8_4/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 1 | 16.600 | 23.000 | 71.336 | + | cpu/stage1/regfile/FE_PHN2892_mem_8_4 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77668/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 10.000 | 5.100 | 76.436 | + | cpu/stage1/regfile/n_1472 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76955__5107/Y | | D->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 8.000 | 10.800 | 87.236 | + | cpu/stage1/rs2_mux_data[4] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g550__5477/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 14.400 | 9.700 | 96.936 | + | cpu/stage1_rs2[4] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g435__2802/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 4.500 | 7.900 | 104.836 | + | cpu/s1_to_s2_rs2/n_16 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[4]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 13.100 | 0.100 | 104.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 23.000 | -4.564 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[4]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.200 | 4.200 | -4.564 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 12: MET (0.736 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[31]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_rs1/register_reg[30]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 95.000 (P) 71.400 (P) + Arrival:= 11.136 -12.464 + + Hold:+ 7.764 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 118.901 + Launch Clock:= -12.464 + Data Path:+ 132.100 + Slack:= 0.736 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.300 | -31.964 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.300 | 19.500 | -12.464 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs1/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs1/register_reg[30]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_L | 1 | 30.900 | 25.000 | 12.536 | + | cpu/stage2_rs1[30] | | | R | (net) | 1 | | | | + | cpu/stage2/rs1DataSel/FE_PHC2632_stage2_rs1_30/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 1 | 8.700 | 15.100 | 27.636 | + | cpu/stage2/rs1DataSel/FE_PHN2632_stage2_rs1_30 | | | R | (net) | 1 | | | | + | cpu/stage2/rs1DataSel/g596/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 1 | 7.400 | 7.600 | 35.236 | + | cpu/stage2/rs1DataSel/n_17 | | | R | (net) | 1 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 6 | 4.000 | 11.500 | 46.736 | + | cpu/stage2/stage2_rs1_data[30] | | | R | (net) | 6 | | | | + | cpu/stage2/aselmux/g564/Y | | A1->Y | R | AO22x1_ASAP7_75t_SL | 15 | 13.200 | 31.100 | 77.836 | + | cpu/stage2/stage2_alu_in1[30] | | | R | (net) | 15 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1661/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 51.500 | 5.500 | 83.336 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_106 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1504/Y | | B->Y | F | OA21x2_ASAP7_75t_SL | 1 | 11.100 | 7.800 | 91.136 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_238 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1503/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 4.000 | 4.400 | 95.536 | + | cpu/stage2/alu/n_322 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5521/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 4 | 6.500 | 11.900 | 107.436 | + | dcache_addr[31] | | | R | (net) | 4 | | | | + | cpu/stage1/pcselmux/g961__6783/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 9.800 | 8.300 | 115.736 | + | cpu/stage1/stage1_pc_mux_to_pc[31] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g362__7482/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.700 | 3.900 | 119.636 | + | cpu/stage1/pcreg/n_18 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[31]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.800 | 0.000 | 119.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 23.100 | 11.136 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 36.400 | 7.200 | 11.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 13: MET (0.839 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[2]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[15][2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[2]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 78.800 (P) 82.500 (P) + Arrival:= -5.064 -1.364 + + Hold:+ 7.461 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 102.397 + Launch Clock:= -1.364 + Data Path:+ 104.600 + Slack:= 0.839 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 22.300 | -51.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 19.400 | 25.800 | -26.064 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 20.300 | 8.800 | -17.264 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_58 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00051/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 9.700 | 15.900 | -1.364 | + | cpu/stage1/regfile/CTS_59 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[15][2]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 23.400 | 20.900 | 19.536 | + | cpu/stage1/regfile/mem[15][2] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3461_mem_15_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.400 | 31.000 | 50.536 | + | cpu/stage1/regfile/FE_PHN3461_mem_15_2 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g78093/Y | | B1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 17.000 | 4.500 | 55.036 | + | cpu/stage1/regfile/n_1047 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77373/Y | | D->Y | F | AND4x1_ASAP7_75t_SL | 1 | 9.500 | 7.000 | 62.036 | + | cpu/stage1/regfile/n_1767 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77054/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 4.000 | 4.200 | 66.236 | + | cpu/stage1/regfile/n_2055 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76977__2346/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.800 | 4.000 | 70.236 | + | cpu/stage1/regfile/n_2132 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76949__2346/Y | | B->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 6.900 | 5.900 | 76.136 | + | cpu/stage1/rs2_mux_data[2] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g554__4319/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.100 | 8.800 | 84.936 | + | cpu/stage1_rs2[2] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC2787_stage1_rs2_2/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 4.600 | 6.300 | 91.236 | + | cpu/s1_to_s2_rs2/FE_PHN2787_stage1_rs2_2 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3594_stage1_rs2_2/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 4.000 | 6.300 | 97.536 | + | cpu/s1_to_s2_rs2/FE_PHN3594_stage1_rs2_2 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g422__1666/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.200 | 5.700 | 103.236 | + | cpu/s1_to_s2_rs2/n_29 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[2]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.900 | 0.300 | 103.236 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 22.500 | -5.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[2]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.000 | 3.700 | -5.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 14: MET (0.846 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[9]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_imm/register_reg[9]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 97.700 (P) 73.300 (P) + Arrival:= 13.836 -10.564 + + Hold:+ 8.054 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 121.891 + Launch Clock:= -10.564 + Data Path:+ 133.300 + Slack:= 0.846 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.700 | -31.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.300 | 21.000 | -10.564 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_imm/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_imm/register_reg[9]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.700 | 21.600 | 11.036 | + | cpu/stage2_imm[9] | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g574/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 8.300 | 9.300 | 20.336 | + | cpu/stage2/stage2_alu_in2[9] | | | R | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC638_stage2_alu_in2_9/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 5 | 7.200 | 6.200 | 26.536 | + | cpu/stage2/alu/FE_DBTN48_stage2_alu_in2_9 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/FE_OFC639_stage2_alu_in2_9/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 9.700 | 8.300 | 34.836 | + | cpu/stage2/alu/FE_OFN831_stage2_alu_in2_9 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/g5552/Y | | B2->Y | F | AOI222xp33_ASAP7_75t_SL | 1 | 13.500 | 7.000 | 41.836 | + | cpu/stage2/alu/n_169 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5513/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 10.500 | 26.500 | 68.336 | + | dcache_addr[9] | | | R | (net) | 4 | | | | + | cpu/stage1/pcselmux/g975__9315/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 58.900 | 14.700 | 83.036 | + | cpu/stage1/pcselmux/n_29 | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/FE_PHC3546_n_29/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 1 | 6.100 | 16.000 | 99.036 | + | cpu/stage1/pcselmux/FE_PHN3546_n_29 | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g931__8428/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 2 | 9.300 | 6.300 | 105.336 | + | cpu/stage1/stage1_pc_mux_to_pc[9] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g375__6260/Y | | B->Y | F | NOR2xp33_ASAP7_75t_L | 1 | 4.600 | 5.400 | 110.736 | + | cpu/stage1/pcreg/n_5 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2860_n_5/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 7.500 | 12.000 | 122.736 | + | cpu/stage1/pcreg/FE_PHN2860_n_5 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[9]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.000 | 122.736 | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 25.800 | 13.836 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[9]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 39.100 | 9.900 | 13.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 15: MET (0.851 ps) Hold Check with Pin cpu/s2_to_s3_pc/register_reg[29]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_pc/register_reg[29]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/register_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 83.500 (P) 73.200 (P) + Arrival:= -0.364 -10.664 + + Hold:+ 10.049 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.685 + Launch Clock:= -10.664 + Data Path:+ 121.200 + Slack:= 0.851 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.100 | -32.164 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.200 | 21.500 | -10.664 | + | NST/GCLK | | | | | | | | | + | cpu/s1_to_s2_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_pc/register_reg[29]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.700 | 21.500 | 10.836 | + | cpu/stage2_pc[29] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2620_stage2_pc_29/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.300 | 29.400 | 40.236 | + | cpu/FE_PHN2620_stage2_pc_29 | | | R | (net) | 2 | | | | + | cpu/s2_to_s3_pc/FE_PHC3355_stage2_pc_29/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 14.500 | 30.200 | 70.436 | + | cpu/s2_to_s3_pc/FE_PHN3355_stage2_pc_29 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3764_stage2_pc_29/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 13.400 | 28.700 | 99.136 | + | cpu/s2_to_s3_pc/FE_PHN3764_stage2_pc_29 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3988_stage2_pc_29/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 11.600 | 7.500 | 106.636 | + | cpu/s2_to_s3_pc/FE_PHN3988_stage2_pc_29 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/g421__9945/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.900 | 110.536 | + | cpu/s2_to_s3_pc/n_30 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_pc/register_reg[29]/D | | D | F | DFFHQNx1_ASAP7_75t_L | 1 | 6.700 | 0.000 | 110.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.000 | -26.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 25.100 | 26.200 | -0.364 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[29]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 42.800 | 8.200 | -0.364 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 16: MET (0.990 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[22]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[15][22]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 75.900 (P) 84.700 (P) + Arrival:= -7.964 0.836 + + Hold:+ 7.410 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 99.446 + Launch Clock:= 0.836 + Data Path:+ 99.600 + Slack:= 0.990 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 22.300 | -51.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 19.400 | 25.800 | -26.064 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 20.300 | 8.800 | -17.264 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_58 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00051/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 9.700 | 18.100 | 0.836 | + | cpu/stage1/regfile/CTS_59 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[15][22]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 26.700 | 21.400 | 22.236 | + | cpu/stage1/regfile/mem[15][22] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC1739_mem_15_22/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.900 | 30.300 | 52.536 | + | cpu/stage1/regfile/FE_PHN1739_mem_15_22 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77807/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 15.800 | 5.100 | 57.636 | + | cpu/stage1/regfile/n_1333 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77085/Y | | B->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 6.400 | 6.200 | 63.836 | + | cpu/stage1/regfile/n_2024 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77004/Y | | B->Y | F | AOI211xp5_ASAP7_75t_SL | 1 | 8.300 | 6.200 | 70.036 | + | cpu/stage1/regfile/n_2105 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76906__1617/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 9.200 | 4.600 | 74.636 | + | cpu/stage1/rs2_mux_data[22] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_OCPC1477_rs2_mux_data_22 | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 6.000 | 11.100 | 85.736 | + | /Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_OCPN1438_rs2_mux_data_22 | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g562__5122/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 10.800 | 9.200 | 94.936 | + | cpu/stage1_rs2[22] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g443__7482/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.300 | 5.500 | 100.436 | + | cpu/s1_to_s2_rs2/n_8 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[22]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.700 | 0.200 | 100.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 19.600 | -7.964 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[22]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.500 | 0.800 | -7.964 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 17: MET (1.007 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[27]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[14][27]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.900 (P) 77.300 (P) + Arrival:= -2.964 -6.564 + + Hold:+ 7.893 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.929 + Launch Clock:= -6.564 + Data Path:+ 112.500 + Slack:= 1.007 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 25.500 | -33.064 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 33.400 | 10.400 | -22.664 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_42 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00054/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 12.100 | 16.100 | -6.564 | + | cpu/stage1/regfile/CTS_43 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[14][27]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 23.500 | 20.900 | 14.336 | + | cpu/stage1/regfile/mem[14][27] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2407_mem_14_27/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.500 | 31.300 | 45.636 | + | cpu/stage1/regfile/FE_PHN2407_mem_14_27 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g78270/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 17.500 | 5.300 | 50.936 | + | cpu/stage1/regfile/n_873 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77181/Y | | E->Y | F | AND5x1_ASAP7_75t_SL | 1 | 9.700 | 9.400 | 60.336 | + | cpu/stage1/regfile/n_1937 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77009/Y | | A2->Y | F | OA211x2_ASAP7_75t_SL | 1 | 4.000 | 11.000 | 71.336 | + | cpu/stage1/regfile/n_2100 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76931__5526/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 5.300 | 7.800 | 79.136 | + | cpu/stage1/rs2_mux_data[27] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g558__3680/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 12.700 | 9.700 | 88.836 | + | cpu/stage1/data2sel_s1/FE_PHN3592_stage1_rs2_27 | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3592_stage1_rs2_27/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 4.800 | 6.700 | 95.536 | + | cpu/stage1_rs2[27] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3938_stage1_rs2_27/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 4.000 | 6.500 | 102.036 | + | cpu/s1_to_s2_rs2/FE_PHN3938_stage1_rs2_27 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g425__5477/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.900 | 105.936 | + | cpu/s1_to_s2_rs2/n_26 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[27]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.600 | 0.000 | 105.936 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.600 | -2.964 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[27]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.600 | 5.800 | -2.964 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 18: MET (1.034 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[6][3]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[6][3]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 98.000 (P) 74.300 (P) + Arrival:= 14.136 -9.564 + + Hold:+ 8.766 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 122.902 + Launch Clock:= -9.564 + Data Path:+ 133.500 + Slack:= 1.034 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 23.000 | -9.564 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[3]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 38.500 | 21.100 | 11.536 | + | cpu/stage3_alu[3] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1145/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.300 | 8.500 | 20.036 | + | cpu/stage3/wbselmux/n_16 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1113/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 5.800 | 8.900 | 28.936 | + | cpu/wb_data[3] | | | R | (net) | 3 | | | | + | cpu/FE_PHC3916_wb_data_3/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 1 | 8.000 | 19.900 | 48.836 | + | cpu/FE_PHN3916_wb_data_3 | | | R | (net) | 1 | | | | + | cpu/FE_PHC3521_wb_data_3/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 8.700 | 19.600 | 68.436 | + | cpu/FE_PHN3521_wb_data_3 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC2716_wb_data_3/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 1 | 11.500 | 24.400 | 92.836 | + | cpu/stage1/FE_PHN2716_wb_data_3 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OCPC1516_wb_data_3/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 7 | 8.900 | 20.400 | 113.236 | + | cpu/stage1/FE_OCPN1477_wb_data_3 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g51163/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 32.300 | 10.700 | 123.936 | + | cpu/stage1/regfile/n_1 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/mem_reg[6][3]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 2 | 20.800 | 0.200 | 123.936 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 25.500 | -24.364 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 30.300 | 9.600 | -14.764 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_27 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00078/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 10.400 | 28.900 | 14.136 | + | cpu/stage1/regfile/CTS_28 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[6][3]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 25.500 | 11.000 | 14.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 19: MET (1.080 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[6]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[26][6]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[6]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.800 (P) 83.500 (P) + Arrival:= -3.064 -0.364 + + Hold:+ 7.620 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.556 + Launch Clock:= -0.364 + Data Path:+ 106.000 + Slack:= 1.080 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 23.800 | -28.464 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 23.200 | 7.300 | -21.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_5 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00018/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.800 | 20.800 | -0.364 | + | cpu/stage1/regfile/CTS_4 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[26][6]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 15.600 | 20.600 | 20.236 | + | cpu/stage1/regfile/mem[26][6] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2293_mem_26_6/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 9.000 | 30.100 | 50.336 | + | cpu/stage1/regfile/FE_PHN2293_mem_26_6 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g78050/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 15.400 | 5.400 | 55.736 | + | cpu/stage1/regfile/n_1089 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77165/Y | | E->Y | F | AND5x1_ASAP7_75t_SL | 1 | 9.900 | 10.100 | 65.836 | + | cpu/stage1/regfile/n_1948 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76941__1881/Y | | A2->Y | R | OAI211xp5_ASAP7_75t_SL | 1 | 4.600 | 16.500 | 82.336 | + | cpu/stage1/rs2_mux_data[6] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g561__1705/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 19.000 | 11.500 | 93.836 | + | cpu/stage1_rs2[6] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3588_stage1_rs2_6/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 6.600 | 6.800 | 100.636 | + | cpu/s1_to_s2_rs2/FE_PHN3588_stage1_rs2_6 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g426__2398/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 5.000 | 105.636 | + | cpu/s1_to_s2_rs2/n_25 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[6]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 8.900 | 0.100 | 105.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.500 | -3.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[6]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.700 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 20: MET (1.135 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[23][2]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[23][2]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 95.200 (P) 74.200 (P) + Arrival:= 11.336 -9.664 + + Hold:+ 11.365 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 122.701 + Launch Clock:= -9.664 + Data Path:+ 133.500 + Slack:= 1.135 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 22.900 | -9.664 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[2]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 38.500 | 21.100 | 11.436 | + | cpu/stage3_alu[2] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1147/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.400 | 8.000 | 19.436 | + | cpu/stage3/wbselmux/n_14 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1114/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 5.100 | 7.900 | 27.336 | + | cpu/wb_data[2] | | | R | (net) | 3 | | | | + | cpu/FE_PHC3923_wb_data_2/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 6.500 | 8.000 | 35.336 | + | cpu/FE_PHN3923_wb_data_2 | | | R | (net) | 1 | | | | + | cpu/FE_PHC3517_wb_data_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 6.900 | 28.800 | 64.136 | + | cpu/FE_PHN3517_wb_data_2 | | | R | (net) | 1 | | | | + | cpu/FE_PHC2707_wb_data_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 13.900 | 31.200 | 95.336 | + | cpu/FE_PHN2707_wb_data_2 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OCPC1438_wb_data_2/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 7 | 14.900 | 19.500 | 114.836 | + | cpu/stage1/FE_OCPN1403_wb_data_2 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g51162/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 29.100 | 9.000 | 123.836 | + | cpu/stage1/regfile/n_2 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/mem_reg[23][2]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 2 | 17.900 | 0.000 | 123.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 30.400 | -26.464 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 42.700 | 10.800 | -15.664 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_40 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00027/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 12.900 | 27.000 | 11.336 | + | cpu/stage1/regfile/CTS_41 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[23][2]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 40.800 | 13.200 | 11.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 21: MET (1.138 ps) Hold Check with Pin cpu/s1_to_s2_inst/register_reg[7]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/register_reg[7]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 85.100 (P) 77.900 (P) + Arrival:= 1.236 -5.964 + + Hold:+ 7.762 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 108.998 + Launch Clock:= -5.964 + Data Path:+ 116.100 + Slack:= 1.138 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 22.200 | -5.964 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.100 | 21.300 | 15.336 | + | cpu/stage2_inst[8] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2647_stage2_inst_8/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 3 | 8.100 | 29.900 | 45.236 | + | cpu/FE_PHN2647_stage2_inst_8 | | | R | (net) | 3 | | | | + | cpu/stage1/nopsel/g472__3680/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 25.600 | 3.900 | 49.136 | + | cpu/stage1/nopsel/n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g465__2398/Y | | C->Y | F | AND5x1_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 57.036 | + | cpu/stage1/nopsel/FE_PHN4110_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC4110_n_14/Y | | A->Y | F | HB1xp67_ASAP7_75t_L | 1 | 4.000 | 8.600 | 65.636 | + | cpu/stage1/nopsel/n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC2690_n_14/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 6.300 | 7.200 | 72.836 | + | cpu/stage1/nopsel/FE_PHN2690_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 4 | 3.800 | 11.200 | 84.036 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1417_NOPSignal/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 9.100 | 9.400 | 93.436 | + | cpu/stage1/nopselmux/FE_OFN971_FE_DBTN75_NOPSignal | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_OFC843_FE_DBTN75_NOPSignal | | A->Y | R | INVx3_ASAP7_75t_SL | 14 | 5.800 | 4.800 | 98.236 | + | /Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OFN974_FE_DBTN75_NOPSignal | | | R | (net) | 14 | | | | + | cpu/stage1/nopselmux/g408__3680/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 9.900 | 8.100 | 106.336 | + | cpu/stage1_inst[7] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_inst/g380__1881/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.800 | 110.136 | + | cpu/s1_to_s2_inst/n_23 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_inst/register_reg[7]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.000 | 110.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 29.700 | -22.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 33.200 | 23.600 | 1.236 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[7]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.900 | 5.900 | 1.236 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 22: MET (1.160 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[23][4]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[4]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[23][4]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 94.700 (P) 73.900 (P) + Arrival:= 10.836 -9.964 + + Hold:+ 11.640 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 122.476 + Launch Clock:= -9.964 + Data Path:+ 133.600 + Slack:= 1.160 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 22.600 | -9.964 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[4]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_L | 1 | 38.500 | 24.900 | 14.936 | + | cpu/stage3_alu[4] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1143/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.700 | 7.900 | 22.836 | + | cpu/stage3/wbselmux/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1110/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 5.000 | 8.500 | 31.336 | + | cpu/wb_data[4] | | | R | (net) | 3 | | | | + | cpu/FE_PHC2703_wb_data_4/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 7.100 | 33.000 | 64.336 | + | cpu/FE_PHN2703_wb_data_4 | | | R | (net) | 2 | | | | + | cpu/stage1/FE_PHC2869_wb_data_4/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 20.300 | 30.200 | 94.536 | + | cpu/stage1/FE_PHN2869_wb_data_4 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC1192_wb_data_4/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 6 | 11.300 | 19.900 | 114.436 | + | cpu/stage1/FE_OFN1208_wb_data_4 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g51164/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 30.200 | 9.200 | 123.636 | + | cpu/stage1/regfile/n_0 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/mem_reg[23][4]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 2 | 18.500 | 0.000 | 123.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 30.400 | -26.464 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 42.700 | 10.800 | -15.664 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_40 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00027/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 12.900 | 26.500 | 10.836 | + | cpu/stage1/regfile/CTS_41 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[23][4]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 40.800 | 12.700 | 10.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 23: MET (1.202 ps) Hold Check with Pin cpu/s2_to_s3_pc/register_reg[9]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_pc/register_reg[9]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.800 (P) 73.100 (P) + Arrival:= -3.064 -10.764 + + Hold:+ 7.998 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.934 + Launch Clock:= -10.764 + Data Path:+ 116.900 + Slack:= 1.202 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.100 | -32.164 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.200 | 21.400 | -10.764 | + | NST/GCLK | | | | | | | | | + | cpu/s1_to_s2_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_pc/register_reg[9]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.400 | 21.600 | 10.836 | + | cpu/stage2_pc[9] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2631_stage2_pc_9/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.500 | 31.400 | 42.236 | + | cpu/FE_PHN2631_stage2_pc_9 | | | R | (net) | 2 | | | | + | cpu/s2_to_s3_pc/FE_PHC3351_stage2_pc_9/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 17.600 | 31.400 | 73.636 | + | cpu/s2_to_s3_pc/FE_PHN3351_stage2_pc_9 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3598_stage2_pc_9/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 14.000 | 28.300 | 101.936 | + | cpu/s2_to_s3_pc/FE_PHN3598_stage2_pc_9 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/g429__5107/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 10.800 | 4.200 | 106.136 | + | cpu/s2_to_s3_pc/n_22 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_pc/register_reg[9]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 7.900 | 0.000 | 106.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.000 | -26.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 25.100 | 23.500 | -3.064 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[9]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 41.000 | 5.500 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 24: MET (1.222 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[14]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[28][14]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 93.300 (P) 78.300 (P) + Arrival:= 9.436 -5.564 + + Hold:+ 7.878 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 117.314 + Launch Clock:= -5.564 + Data Path:+ 124.100 + Slack:= 1.222 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 26.000 | -32.564 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 33.400 | 7.400 | -25.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_38 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00012/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.600 | 19.600 | -5.564 | + | cpu/stage1/regfile/CTS_39 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[28][14]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 13.600 | 20.100 | 14.536 | + | cpu/stage1/regfile/mem[28][14] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC1850_mem_28_14/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.500 | 33.100 | 47.636 | + | cpu/stage1/regfile/FE_PHN1850_mem_28_14 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g78277/Y | | B1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 20.200 | 6.000 | 53.636 | + | cpu/stage1/regfile/n_866 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76930__8428/Y | | A3->Y | F | AO31x2_ASAP7_75t_SL | 1 | 10.800 | 9.900 | 63.536 | + | cpu/stage1/regfile/n_2153 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76886__5115/Y | | C->Y | R | NAND4xp75_ASAP7_75t_SL | 1 | 4.700 | 5.900 | 69.436 | + | cpu/stage1/rs1_mux_data[14] | | | R | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g576__6417/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 2 | 6.000 | 10.600 | 80.036 | + | cpu/stage1_rs1[14] | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/g1256__5107/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 2 | 7.100 | 9.200 | 89.236 | + | cpu/stage1/pcadder/n_45 | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1p5_ASAP7_75t_SL | 2 | 4.700 | 3.900 | 93.136 | + | 33_g1507__9315/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_24 | | | | | | | | | + | cpu/stage1/pcadder/FE_OFC1223_add_18_35_Y_add_17_3 | | A->Y | R | INVx2_ASAP7_75t_SL | 3 | 5.300 | 3.300 | 96.436 | + | 4_Y_add_16_33_n_24/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_23 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.900 | 4.900 | 101.336 | + | 33_g1371__5115/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_134 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 9.000 | 5.600 | 106.936 | + | 33_g1259__6161/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[14] | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g935__1617/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 7.300 | 7.800 | 114.736 | + | cpu/stage1/stage1_pc_mux_to_pc[14] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g357__8246/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.300 | 3.800 | 118.536 | + | cpu/stage1/pcreg/n_23 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[14]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.000 | 118.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 21.400 | 9.436 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[14]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.300 | 5.500 | 9.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 25: MET (1.222 ps) Hold Check with Pin cpu/s2_to_s3_pc/register_reg[13]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_pc/register_reg[13]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/register_reg[13]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 79.100 (P) 72.200 (P) + Arrival:= -4.764 -11.664 + + Hold:+ 7.978 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 103.214 + Launch Clock:= -11.664 + Data Path:+ 116.100 + Slack:= 1.222 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.100 | -32.164 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.200 | 20.500 | -11.664 | + | NST/GCLK | | | | | | | | | + | cpu/s1_to_s2_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_pc/register_reg[13]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.300 | 21.600 | 9.936 | + | cpu/stage2_pc[13] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2600_stage2_pc_13/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.600 | 30.800 | 40.736 | + | cpu/FE_PHN2600_stage2_pc_13 | | | R | (net) | 2 | | | | + | cpu/s2_to_s3_pc/FE_PHC3338_stage2_pc_13/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 16.600 | 31.700 | 72.436 | + | cpu/s2_to_s3_pc/FE_PHN3338_stage2_pc_13 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3708_stage2_pc_13/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 14.900 | 27.800 | 100.236 | + | cpu/s2_to_s3_pc/FE_PHN3708_stage2_pc_13 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/g419__6161/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 10.000 | 4.200 | 104.436 | + | cpu/s2_to_s3_pc/n_32 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_pc/register_reg[13]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 7.800 | 0.000 | 104.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.000 | -26.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 25.100 | 21.800 | -4.764 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[13]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 40.400 | 3.800 | -4.764 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 26: MET (1.282 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[7]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[2][7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[7]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 78.800 (P) 82.200 (P) + Arrival:= -5.064 -1.664 + + Hold:+ 7.518 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 102.454 + Launch Clock:= -1.664 + Data Path:+ 105.400 + Slack:= 1.282 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 24.400 | -27.864 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 23.300 | 7.900 | -19.964 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_31 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00090/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 7.600 | 18.300 | -1.664 | + | cpu/stage1/regfile/CTS_32 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[2][7]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 13.300 | 20.100 | 18.436 | + | cpu/stage1/regfile/mem[2][7] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2172_mem_2_7/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.500 | 26.900 | 45.336 | + | cpu/stage1/regfile/FE_PHN2172_mem_2_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3504_mem_2_7/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 2 | 10.900 | 23.500 | 68.836 | + | cpu/stage1/regfile/FE_PHN3504_mem_2_7 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77647/Y | | B1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 13.200 | 4.900 | 73.736 | + | cpu/stage1/regfile/n_1493 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76894__1666/Y | | E->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 9.100 | 8.900 | 82.636 | + | cpu/stage1/rs2_mux_data[7] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g575__1666/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 10.500 | 9.300 | 91.936 | + | cpu/stage1_rs2[7] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC2790_stage1_rs2_7/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 4.500 | 6.400 | 98.336 | + | cpu/s1_to_s2_rs2/FE_PHN2790_stage1_rs2_7 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g427__5107/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 5.400 | 103.736 | + | cpu/s1_to_s2_rs2/n_24 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[7]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.500 | 0.200 | 103.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 22.500 | -5.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[7]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.000 | 3.700 | -5.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 27: MET (1.288 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[3]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[17][3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[3]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.800 (P) 82.800 (P) + Arrival:= -3.064 -1.064 + + Hold:+ 7.812 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.748 + Launch Clock:= -1.064 + Data Path:+ 107.100 + Slack:= 1.288 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 21.200 | -31.064 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 22.100 | 7.100 | -23.964 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_15 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00045/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.400 | 22.900 | -1.064 | + | cpu/stage1/regfile/CTS_16 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[17][3]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 19.000 | 21.200 | 20.136 | + | cpu/stage1/regfile/mem[17][3] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC1925_mem_17_3/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 9.300 | 27.800 | 47.936 | + | cpu/stage1/regfile/FE_PHN1925_mem_17_3 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3491_mem_17_3/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 2 | 11.900 | 29.600 | 77.536 | + | cpu/stage1/regfile/FE_PHN3491_mem_17_3 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77099/Y | | A2->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 7.900 | 85.436 | + | cpu/stage1/regfile/n_2010 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76913__1881/Y | | C->Y | R | NAND4xp25_ASAP7_75t_SL | 1 | 6.800 | 6.600 | 92.036 | + | cpu/stage1/rs2_mux_data[3] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g551__2398/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 8.900 | 9.800 | 101.836 | + | cpu/stage1_rs2[3] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g423__7410/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.600 | 4.200 | 106.036 | + | cpu/s1_to_s2_rs2/n_28 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[3]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 7.300 | 0.000 | 106.036 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.500 | -3.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[3]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.700 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 28: MET (1.299 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[8]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_imm/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 97.200 (P) 73.000 (P) + Arrival:= 13.336 -10.864 + + Hold:+ 7.601 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 120.938 + Launch Clock:= -10.864 + Data Path:+ 133.100 + Slack:= 1.299 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.700 | -31.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.300 | 20.700 | -10.864 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_imm/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_imm/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_L | 1 | 33.700 | 25.700 | 14.836 | + | cpu/stage2_imm[8] | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g575/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 9.300 | 8.300 | 23.136 | + | cpu/stage2/stage2_alu_in2[8] | | | R | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC661_stage2_alu_in2_8/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 5 | 5.500 | 7.000 | 30.136 | + | cpu/stage2/alu/FE_DBTN47_stage2_alu_in2_8 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/FE_OFC662_stage2_alu_in2_8/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 11.800 | 7.900 | 38.036 | + | cpu/stage2/alu/FE_OFN848_stage2_alu_in2_8 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/g5553/Y | | B2->Y | F | AOI222xp33_ASAP7_75t_SL | 1 | 12.700 | 7.100 | 45.136 | + | cpu/stage2/alu/n_168 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5514/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 10.700 | 26.500 | 71.636 | + | dcache_addr[8] | | | R | (net) | 4 | | | | + | cpu/stage1/pcselmux/g977__2883/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 57.900 | 14.200 | 85.836 | + | cpu/stage1/pcselmux/n_27 | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g952__7410/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 2 | 5.100 | 6.100 | 91.936 | + | cpu/stage1/stage1_pc_mux_to_pc[8] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g374__5107/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 4.800 | 6.800 | 98.736 | + | cpu/stage1/pcreg/n_6 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2856_n_6/Y | | A->Y | F | HB4xp67_ASAP7_75t_SL | 1 | 11.000 | 23.500 | 122.236 | + | cpu/stage1/pcreg/FE_PHN2856_n_6 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[8]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.700 | 0.000 | 122.236 | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 25.300 | 13.336 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[8]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 39.100 | 9.400 | 13.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 29: MET (1.350 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[13]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[17][13]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[13]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 94.600 (P) 83.000 (P) + Arrival:= 10.736 -0.864 + + Hold:+ 7.950 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 118.687 + Launch Clock:= -0.864 + Data Path:+ 120.900 + Slack:= 1.350 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 21.200 | -31.064 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 22.100 | 7.100 | -23.964 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_15 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00045/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.400 | 23.100 | -0.864 | + | cpu/stage1/regfile/CTS_16 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[17][13]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 19.100 | 20.600 | 19.736 | + | cpu/stage1/regfile/mem[17][13] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2166_mem_17_13/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.600 | 30.400 | 50.136 | + | cpu/stage1/regfile/FE_PHN2166_mem_17_13 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g79288/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 3.800 | 53.936 | + | cpu/stage1/regfile/n_384 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77783/Y | | B1->Y | R | OAI22xp5_ASAP7_75t_SL | 1 | 7.400 | 6.000 | 59.936 | + | cpu/stage1/regfile/n_1357 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77433/Y | | B->Y | F | NOR2x1_ASAP7_75t_SL | 1 | 8.000 | 4.300 | 64.236 | + | cpu/stage1/regfile/n_1707 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76866__1666/Y | | A->Y | R | NAND4xp75_ASAP7_75t_SL | 1 | 6.000 | 7.300 | 71.536 | + | cpu/stage1/rs1_mux_data[13] | | | R | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g563__7098/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 2 | 11.000 | 11.800 | 83.336 | + | cpu/stage1_rs1[13] | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/g1258__4319/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 2 | 7.600 | 9.700 | 93.036 | + | cpu/stage1/pcadder/n_44 | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NAND2x1p5_ASAP7_75t_SL | 2 | 5.600 | 3.300 | 96.336 | + | 33_g1478__6161/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_67 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.600 | 5.800 | 102.136 | + | 33_g1372__7482/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_133 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 1 | 8.400 | 6.800 | 108.936 | + | 33_g1267__7410/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[13] | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g937__1705/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 5.000 | 7.300 | 116.236 | + | cpu/stage1/stage1_pc_mux_to_pc[13] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g354__2802/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.000 | 3.800 | 120.036 | + | cpu/stage1/pcreg/n_26 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[13]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.600 | 0.000 | 120.036 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 22.700 | 10.736 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[13]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 38.100 | 6.800 | 10.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 30: MET (1.354 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[20][15]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[15]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[20][15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 110.300 (P) 71.000 (P) + Arrival:= 26.436 -12.864 + + Hold:+ 11.646 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 138.082 + Launch Clock:= -12.864 + Data Path:+ 152.300 + Slack:= 1.354 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 19.700 | -12.864 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[15]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 37.800 | 21.400 | 8.536 | + | cpu/stage3_alu[15] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1121/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.800 | 8.000 | 16.536 | + | cpu/stage3/wbselmux/n_40 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1090/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 5.000 | 9.300 | 25.836 | + | cpu/wb_data[15] | | | R | (net) | 3 | | | | + | cpu/FE_PHC4040_wb_data_15/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 8.300 | 23.100 | 48.936 | + | cpu/FE_PHN4040_wb_data_15 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3529_wb_data_15/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 17.700 | 21.900 | 70.836 | + | cpu/stage1/FE_PHN3529_wb_data_15 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3904_wb_data_15/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 10.600 | 26.800 | 97.636 | + | cpu/stage1/FE_PHN3904_wb_data_15 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC858_wb_data_15/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 6 | 10.100 | 17.800 | 115.436 | + | cpu/stage1/FE_OFN989_wb_data_15 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g81275/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 8 | 26.000 | 24.000 | 139.436 | + | cpu/stage1/regfile/n_123 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/mem_reg[20][15]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 8 | 47.200 | 1.100 | 139.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 30.300 | -19.164 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.600 | 12.600 | -6.564 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_56 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00036/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 16.900 | 33.000 | 26.436 | + | cpu/stage1/regfile/CTS_57 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[20][15]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 48.500 | 18.700 | 26.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 31: MET (1.356 ps) Hold Check with Pin cpu/s2_to_s3_pc/register_reg[20]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_pc/register_reg[20]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/register_reg[20]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 83.600 (P) 73.600 (P) + Arrival:= -0.264 -10.264 + + Hold:+ 8.144 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 107.880 + Launch Clock:= -10.264 + Data Path:+ 119.500 + Slack:= 1.356 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.100 | -32.164 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.200 | 21.900 | -10.264 | + | NST/GCLK | | | | | | | | | + | cpu/s1_to_s2_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_pc/register_reg[20]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.700 | 21.800 | 11.536 | + | cpu/s1_to_s2_pc/FE_RN_4 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_pc/FE_PHC2616_stage2_pc_20/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.900 | 33.100 | 44.636 | + | cpu/stage2_pc[20] | | | R | (net) | 2 | | | | + | cpu/s2_to_s3_pc/FE_PHC3334_stage2_pc_20/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 20.100 | 32.400 | 77.036 | + | cpu/s2_to_s3_pc/FE_PHN3334_stage2_pc_20 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3600_stage2_pc_20/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 14.600 | 27.800 | 104.836 | + | cpu/s2_to_s3_pc/FE_PHN3600_stage2_pc_20 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/g441__7098/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 10.100 | 4.400 | 109.236 | + | cpu/s2_to_s3_pc/n_10 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_pc/register_reg[20]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 8.000 | 0.000 | 109.236 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.000 | -26.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 25.100 | 26.300 | -0.264 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[20]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 42.800 | 8.300 | -0.264 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 32: MET (1.403 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[19]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[14][19]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 94.500 (P) 77.700 (P) + Arrival:= 10.636 -6.164 + + Hold:+ 7.797 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 118.433 + Launch Clock:= -6.164 + Data Path:+ 126.000 + Slack:= 1.403 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 25.500 | -33.064 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 33.400 | 10.400 | -22.664 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_42 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00054/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 12.100 | 16.500 | -6.164 | + | cpu/stage1/regfile/CTS_43 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[14][19]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 23.600 | 21.100 | 14.936 | + | cpu/stage1/regfile/mem[14][19] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2364_mem_14_19/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.800 | 30.700 | 45.636 | + | cpu/stage1/regfile/FE_PHN2364_mem_14_19 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77903/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 16.400 | 8.100 | 53.736 | + | cpu/stage1/regfile/n_1236 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76986__8428/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 4.700 | 4.700 | 58.436 | + | cpu/stage1/regfile/n_2123 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76881__5122/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 1 | 7.600 | 5.900 | 64.336 | + | cpu/stage1/rs1_mux_data[19] | | | R | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g574__1666/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 6.000 | 9.000 | 73.336 | + | cpu/stage1_rs1[19] | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/g1265__1705/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 7.700 | 7.800 | 81.136 | + | cpu/stage1/pcadder/n_50 | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NAND2xp5_ASAP7_75t_L | 2 | 5.300 | 6.100 | 87.236 | + | 33_g1428__6161/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_104 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 10.300 | 5.300 | 92.536 | + | 33_g1376__9945/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_130 | | | | | | | | | + | cpu/stage1/pcadder/FE_PHC4112_add_18_35_Y_add_17_3 | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 5.100 | 8.700 | 101.236 | + | 4_Y_add_16_33_n_130/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_PHN4112_add_18_35_Y_add_17_3 | | | R | (net) | 1 | | | | + | 4_Y_add_16_33_n_130 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 1 | 8.600 | 7.400 | 108.636 | + | 33_g1246__1617/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[19] | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g947__9315/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 6.000 | 7.400 | 116.036 | + | cpu/stage1/stage1_pc_mux_to_pc[19] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g360__1881/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.100 | 3.800 | 119.836 | + | cpu/stage1/pcreg/n_20 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[19]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.600 | 0.000 | 119.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 22.600 | 10.636 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 36.400 | 6.700 | 10.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 33: MET (1.407 ps) Hold Check with Pin cpu/s1_to_s2_inst/register_reg[11]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/register_reg[11]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 85.000 (P) 77.900 (P) + Arrival:= 1.136 -5.964 + + Hold:+ 7.793 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 108.929 + Launch Clock:= -5.964 + Data Path:+ 116.300 + Slack:= 1.407 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 22.200 | -5.964 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.100 | 21.300 | 15.336 | + | cpu/stage2_inst[8] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2647_stage2_inst_8/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 3 | 8.100 | 29.900 | 45.236 | + | cpu/FE_PHN2647_stage2_inst_8 | | | R | (net) | 3 | | | | + | cpu/stage1/nopsel/g472__3680/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 25.600 | 3.900 | 49.136 | + | cpu/stage1/nopsel/n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g465__2398/Y | | C->Y | F | AND5x1_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 57.036 | + | cpu/stage1/nopsel/FE_PHN4110_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC4110_n_14/Y | | A->Y | F | HB1xp67_ASAP7_75t_L | 1 | 4.000 | 8.600 | 65.636 | + | cpu/stage1/nopsel/n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC2690_n_14/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 6.300 | 7.200 | 72.836 | + | cpu/stage1/nopsel/FE_PHN2690_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 4 | 3.800 | 11.200 | 84.036 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1417_NOPSignal/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 9.100 | 9.400 | 93.436 | + | cpu/stage1/nopselmux/FE_OFN971_FE_DBTN75_NOPSignal | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_OFC843_FE_DBTN75_NOPSignal | | A->Y | R | INVx3_ASAP7_75t_SL | 14 | 5.800 | 5.300 | 98.736 | + | /Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OFN974_FE_DBTN75_NOPSignal | | | R | (net) | 14 | | | | + | cpu/stage1/nopselmux/g399__5477/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 10.200 | 8.000 | 106.736 | + | cpu/stage1_inst[11] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_inst/g385__9315/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.600 | 110.336 | + | cpu/s1_to_s2_inst/n_18 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_inst/register_reg[11]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.100 | 0.000 | 110.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 29.700 | -22.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 33.200 | 23.500 | 1.136 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[11]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.900 | 5.800 | 1.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 34: MET (1.428 ps) Hold Check with Pin cpu/s1_to_s2_inst/register_reg[31]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 86.000 (P) 77.900 (P) + Arrival:= 2.136 -5.964 + + Hold:+ 7.772 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.909 + Launch Clock:= -5.964 + Data Path:+ 117.300 + Slack:= 1.428 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 22.200 | -5.964 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.100 | 21.300 | 15.336 | + | cpu/stage2_inst[8] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2647_stage2_inst_8/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 3 | 8.100 | 29.900 | 45.236 | + | cpu/FE_PHN2647_stage2_inst_8 | | | R | (net) | 3 | | | | + | cpu/stage1/nopsel/g472__3680/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 25.600 | 3.900 | 49.136 | + | cpu/stage1/nopsel/n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g465__2398/Y | | C->Y | F | AND5x1_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 57.036 | + | cpu/stage1/nopsel/FE_PHN4110_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC4110_n_14/Y | | A->Y | F | HB1xp67_ASAP7_75t_L | 1 | 4.000 | 8.600 | 65.636 | + | cpu/stage1/nopsel/n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC2690_n_14/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 6.300 | 7.200 | 72.836 | + | cpu/stage1/nopsel/FE_PHN2690_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 4 | 3.800 | 11.200 | 84.036 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1417_NOPSignal/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 9.100 | 9.400 | 93.436 | + | cpu/stage1/nopselmux/FE_OFN971_FE_DBTN75_NOPSignal | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_OFC843_FE_DBTN75_NOPSignal | | A->Y | R | INVx3_ASAP7_75t_SL | 14 | 5.800 | 6.200 | 99.636 | + | /Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OFN974_FE_DBTN75_NOPSignal | | | R | (net) | 14 | | | | + | cpu/stage1/nopselmux/g401__5107/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 10.400 | 8.000 | 107.636 | + | cpu/stage1_inst[31] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_inst/g255__5526/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.700 | 111.336 | + | cpu/s1_to_s2_inst/n_33 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_inst/register_reg[31]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.400 | 0.000 | 111.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 29.700 | -22.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 33.200 | 24.500 | 2.136 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.900 | 6.800 | 2.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 35: MET (1.492 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[1]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_imm/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.900 (P) 73.400 (P) + Arrival:= -2.964 -10.464 + + Hold:+ 9.408 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 106.445 + Launch Clock:= -10.464 + Data Path:+ 118.400 + Slack:= 1.492 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.700 | -31.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.300 | 21.100 | -10.464 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_imm/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_imm/register_reg[3]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 1 | 33.700 | 21.600 | 11.136 | + | cpu/stage2_imm[3] | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g588/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 1 | 9.700 | 9.500 | 20.636 | + | cpu/stage2/bselmux/n_1 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g553/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 6 | 4.800 | 11.700 | 32.336 | + | cpu/stage2/stage2_alu_in2[3] | | | F | (net) | 6 | | | | + | cpu/stage2/alu/FE_PHC4127_stage2_alu_in2_3/Y | | A->Y | F | BUFx4f_ASAP7_75t_SL | 9 | 11.800 | 10.700 | 43.036 | + | cpu/stage2/alu/FE_PHN4127_stage2_alu_in2_3 | | | F | (net) | 9 | | | | + | cpu/stage2/alu/srl_33_21_g1726/Y | | A2->Y | R | AOI222xp33_ASAP7_75t_SL | 2 | 9.500 | 8.700 | 51.736 | + | cpu/stage2/alu/srl_33_21_n_125 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/srl_33_21_g1693/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 16.000 | 5.200 | 56.936 | + | cpu/stage2/alu/n_197 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5501/Y | | A1->Y | F | AO221x2_ASAP7_75t_SL | 6 | 7.300 | 16.000 | 72.936 | + | cpu/stage2_alu_out[1] | | | F | (net) | 6 | | | | + | cpu/FE_PHC2782_stage2_alu_out_1/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 3 | 13.800 | 24.600 | 97.536 | + | cpu/FE_PHN2782_stage2_alu_out_1 | | | F | (net) | 3 | | | | + | cpu/s2_to_s3_alu/g448__5477/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 1 | 16.200 | 10.400 | 107.936 | + | cpu/s2_to_s3_alu/n_3 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[1]/D | | D | F | DFFHQx4_ASAP7_75t_SL | 1 | 4.800 | 0.000 | 107.936 | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 24.900 | -2.964 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[1]/CLK | | CLK | R | DFFHQx4_ASAP7_75t_SL | 32 | 42.700 | 7.900 | -2.964 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 36: MET (1.492 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[20][28]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[28]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[20][28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 105.000 (P) 74.900 (P) + Arrival:= 21.136 -8.964 + + Hold:+ 11.808 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 132.944 + Launch Clock:= -8.964 + Data Path:+ 143.400 + Slack:= 1.492 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 23.600 | -8.964 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[28]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 41.300 | 23.100 | 14.136 | + | cpu/stage3_alu[28] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1126/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 10.000 | 10.900 | 25.036 | + | cpu/stage3/wbselmux/n_35 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1111/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 9.600 | 8.700 | 33.736 | + | cpu/wb_data[28] | | | R | (net) | 3 | | | | + | cpu/FE_PHC3921_wb_data_28/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 7.000 | 7.400 | 41.136 | + | cpu/FE_PHN3921_wb_data_28 | | | R | (net) | 1 | | | | + | cpu/FE_PHC3513_wb_data_28/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 1 | 5.500 | 27.600 | 68.736 | + | cpu/FE_PHN3513_wb_data_28 | | | R | (net) | 1 | | | | + | cpu/FE_PHC2710_wb_data_28/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 16.200 | 35.700 | 104.436 | + | cpu/FE_PHN2710_wb_data_28 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC890_wb_data_28/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 21.500 | 15.100 | 119.536 | + | cpu/stage1/regfile/FE_OFN1021_wb_data_28 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/g81631/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 5 | 18.300 | 14.900 | 134.436 | + | cpu/stage1/regfile/n_68 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/mem_reg[20][28]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 5 | 28.000 | 0.500 | 134.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 30.300 | -19.164 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.600 | 12.600 | -6.564 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_56 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00036/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 16.900 | 27.700 | 21.136 | + | cpu/stage1/regfile/CTS_57 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[20][28]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.200 | 13.400 | 21.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 37: MET (1.492 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[17]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[8][17]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[17]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 94.600 (P) 81.400 (P) + Arrival:= 10.736 -2.464 + + Hold:+ 7.808 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 118.544 + Launch Clock:= -2.464 + Data Path:+ 122.500 + Slack:= 1.492 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 21.100 | -31.164 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 21.700 | 7.000 | -24.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_23 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00072/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.100 | 21.700 | -2.464 | + | cpu/stage1/regfile/CTS_24 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[8][17]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_L | 1 | 16.900 | 23.200 | 20.736 | + | cpu/stage1/regfile/mem[8][17] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2194_mem_8_17/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.200 | 29.700 | 50.436 | + | cpu/stage1/regfile/FE_PHN2194_mem_8_17 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g79217/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 15.000 | 3.100 | 53.536 | + | cpu/stage1/regfile/n_451 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77213/Y | | A1->Y | R | OAI21xp5_ASAP7_75t_SL | 1 | 6.400 | 4.900 | 58.436 | + | cpu/stage1/regfile/n_1911 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77080/Y | | B->Y | F | NOR2x1_ASAP7_75t_SL | 1 | 6.200 | 5.200 | 63.636 | + | cpu/stage1/regfile/n_2029 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76962__1617/Y | | C->Y | R | NAND4xp75_ASAP7_75t_SL | 1 | 7.300 | 7.100 | 70.736 | + | cpu/stage1/rs1_mux_data[17] | | | R | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g553__4319/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 8.700 | 8.600 | 79.336 | + | cpu/stage1_rs1[17] | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/g1252__7410/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 6.700 | 7.900 | 87.236 | + | cpu/stage1/pcadder/n_48 | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 5.700 | 6.500 | 93.736 | + | 33_g1484__7410/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_58 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 12.300 | 7.500 | 101.236 | + | 33_g1367__8246/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_138 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 1 | 9.900 | 7.000 | 108.236 | + | 33_g1266__1666/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[17] | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g954__5477/Y | | A2->Y | R | AO21x1_ASAP7_75t_L | 2 | 5.200 | 8.000 | 116.236 | + | cpu/stage1/stage1_pc_mux_to_pc[17] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g358__7098/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.100 | 3.800 | 120.036 | + | cpu/stage1/pcreg/n_22 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[17]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.000 | 120.036 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 22.700 | 10.736 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[17]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 36.400 | 6.800 | 10.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 38: MET (1.546 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[19]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[27][19]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 81.100 (P) 87.600 (P) + Arrival:= -2.764 3.736 + + Hold:+ 7.954 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 105.190 + Launch Clock:= 3.736 + Data Path:+ 103.000 + Slack:= 1.546 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 24.400 | -27.864 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 23.300 | 8.000 | -19.864 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00015/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 7.800 | 23.600 | 3.736 | + | cpu/stage1/regfile/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[27][19]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 20.100 | 20.600 | 24.336 | + | cpu/stage1/regfile/mem[27][19] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2392_mem_27_19/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.300 | 28.700 | 53.036 | + | cpu/stage1/regfile/FE_PHN2392_mem_27_19 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC3982_mem_27_19/Y | | A->Y | R | HB1xp67_ASAP7_75t_L | 1 | 13.400 | 9.200 | 62.236 | + | cpu/stage1/regfile/FE_PHN3982_mem_27_19 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77145/Y | | A2->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 5.600 | 7.800 | 70.036 | + | cpu/stage1/regfile/n_1964 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76922__1666/Y | | B->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 7.000 | 5.500 | 75.536 | + | cpu/stage1/regfile/n_2161 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76882__8246/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 1 | 6.700 | 6.100 | 81.636 | + | cpu/stage1/rs2_mux_data[19] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3934_rs2_mux_data_19/ | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 4.500 | 6.500 | 88.136 | + | Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_PHN3934_rs2_mux_data_19 | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g574__2346/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 4.000 | 8.500 | 96.636 | + | cpu/stage1_rs2[19] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3583_stage1_rs2_19/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 4.800 | 6.400 | 103.036 | + | cpu/s1_to_s2_rs2/FE_PHN3583_stage1_rs2_19 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g440__6131/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.700 | 106.736 | + | cpu/s1_to_s2_rs2/n_11 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[19]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.200 | 0.000 | 106.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.800 | -2.764 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.600 | 6.000 | -2.764 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 39: MET (1.652 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[0]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[11][0]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[0]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.800 (P) 83.800 (P) + Arrival:= -3.064 -0.064 + + Hold:+ 7.548 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.484 + Launch Clock:= -0.064 + Data Path:+ 106.200 + Slack:= 1.652 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 22.400 | -29.864 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 22.000 | 7.200 | -22.664 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_19 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00063/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.500 | 22.600 | -0.064 | + | cpu/stage1/regfile/CTS_20 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[11][0]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 17.700 | 20.800 | 20.736 | + | cpu/stage1/regfile/mem[11][0] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2046_mem_11_0/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 9.000 | 30.300 | 51.036 | + | cpu/stage1/regfile/FE_PHN2046_mem_11_0 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC2933_mem_11_0/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 15.800 | 20.900 | 71.936 | + | cpu/stage1/regfile/FE_PHN2933_mem_11_0 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77707/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 10.000 | 4.300 | 76.236 | + | cpu/stage1/regfile/n_1433 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77094/Y | | A->Y | F | AND5x1_ASAP7_75t_SL | 1 | 6.700 | 7.600 | 83.836 | + | cpu/stage1/regfile/n_2015 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76887__7482/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 4.800 | 5.900 | 89.736 | + | cpu/stage1/rs2_mux_data[0] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g557__6783/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 8.900 | 10.200 | 99.936 | + | cpu/stage1_rs2[0] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g449__2346/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 6.300 | 6.200 | 106.136 | + | cpu/s1_to_s2_rs2/n_2 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[0]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.400 | 0.000 | 106.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.500 | -3.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[0]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.700 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 40: MET (1.671 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[6][12]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[12]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[6][12]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 96.100 (P) 72.200 (P) + Arrival:= 12.236 -11.664 + + Hold:+ 7.529 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 119.765 + Launch Clock:= -11.664 + Data Path:+ 133.100 + Slack:= 1.671 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 20.900 | -11.664 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[12]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_L | 1 | 38.200 | 24.800 | 13.136 | + | cpu/stage3_alu[12] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1127/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.400 | 11.300 | 24.436 | + | cpu/stage3/wbselmux/n_34 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1094/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 10.500 | 9.100 | 33.536 | + | cpu/wb_data[12] | | | R | (net) | 3 | | | | + | cpu/FE_PHC2704_wb_data_12/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 2 | 6.800 | 32.000 | 65.536 | + | cpu/FE_PHN2704_wb_data_12 | | | R | (net) | 2 | | | | + | cpu/stage1/FE_PHC2870_wb_data_12/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 23.300 | 28.600 | 94.136 | + | cpu/stage1/FE_PHN2870_wb_data_12 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC868_wb_data_12/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 6 | 8.100 | 22.100 | 116.236 | + | cpu/stage1/FE_OFN999_wb_data_12 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g51152/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 35.700 | 5.200 | 121.436 | + | cpu/stage1/regfile/n_12 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/mem_reg[6][12]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 14.100 | 0.000 | 121.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 25.500 | -24.364 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 30.300 | 9.600 | -14.764 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_27 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00078/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 10.400 | 27.000 | 12.236 | + | cpu/stage1/regfile/CTS_28 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[6][12]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 25.100 | 9.100 | 12.236 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 41: MET (1.728 ps) Hold Check with Pin cpu/s1_to_s2_inst/register_reg[9]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 85.900 (P) 77.900 (P) + Arrival:= 2.036 -5.964 + + Hold:+ 7.772 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.809 + Launch Clock:= -5.964 + Data Path:+ 117.500 + Slack:= 1.728 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 22.200 | -5.964 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.100 | 21.300 | 15.336 | + | cpu/stage2_inst[8] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2647_stage2_inst_8/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 3 | 8.100 | 29.900 | 45.236 | + | cpu/FE_PHN2647_stage2_inst_8 | | | R | (net) | 3 | | | | + | cpu/stage1/nopsel/g472__3680/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 25.600 | 3.900 | 49.136 | + | cpu/stage1/nopsel/n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g465__2398/Y | | C->Y | F | AND5x1_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 57.036 | + | cpu/stage1/nopsel/FE_PHN4110_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC4110_n_14/Y | | A->Y | F | HB1xp67_ASAP7_75t_L | 1 | 4.000 | 8.600 | 65.636 | + | cpu/stage1/nopsel/n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC2690_n_14/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 6.300 | 7.200 | 72.836 | + | cpu/stage1/nopsel/FE_PHN2690_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 4 | 3.800 | 11.200 | 84.036 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1417_NOPSignal/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 9.100 | 9.400 | 93.436 | + | cpu/stage1/nopselmux/FE_OFN971_FE_DBTN75_NOPSignal | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_OFC843_FE_DBTN75_NOPSignal | | A->Y | R | INVx3_ASAP7_75t_SL | 14 | 5.800 | 6.300 | 99.736 | + | /Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OFN974_FE_DBTN75_NOPSignal | | | R | (net) | 14 | | | | + | cpu/stage1/nopselmux/g418__5115/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 10.400 | 8.100 | 107.836 | + | cpu/stage1_inst[9] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_inst/g382__7482/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.700 | 111.536 | + | cpu/s1_to_s2_inst/n_21 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_inst/register_reg[9]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.300 | 0.000 | 111.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 29.700 | -22.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 33.200 | 24.400 | 2.036 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[9]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.900 | 6.700 | 2.036 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 42: MET (1.786 ps) Hold Check with Pin cpu/s1_to_s2_inst/register_reg[8]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/register_reg[8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 85.700 (P) 77.900 (P) + Arrival:= 1.836 -5.964 + + Hold:+ 7.814 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.650 + Launch Clock:= -5.964 + Data Path:+ 117.400 + Slack:= 1.786 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 22.200 | -5.964 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.100 | 21.300 | 15.336 | + | cpu/stage2_inst[8] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2647_stage2_inst_8/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 3 | 8.100 | 29.900 | 45.236 | + | cpu/FE_PHN2647_stage2_inst_8 | | | R | (net) | 3 | | | | + | cpu/stage1/nopsel/g472__3680/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 25.600 | 3.900 | 49.136 | + | cpu/stage1/nopsel/n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g465__2398/Y | | C->Y | F | AND5x1_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 57.036 | + | cpu/stage1/nopsel/FE_PHN4110_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC4110_n_14/Y | | A->Y | F | HB1xp67_ASAP7_75t_L | 1 | 4.000 | 8.600 | 65.636 | + | cpu/stage1/nopsel/n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC2690_n_14/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 6.300 | 7.200 | 72.836 | + | cpu/stage1/nopsel/FE_PHN2690_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 4 | 3.800 | 11.200 | 84.036 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1417_NOPSignal/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 9.100 | 9.400 | 93.436 | + | cpu/stage1/nopselmux/FE_OFN971_FE_DBTN75_NOPSignal | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_OFC843_FE_DBTN75_NOPSignal | | A->Y | R | INVx3_ASAP7_75t_SL | 14 | 5.800 | 6.300 | 99.736 | + | /Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OFN974_FE_DBTN75_NOPSignal | | | R | (net) | 14 | | | | + | cpu/stage1/nopselmux/g407__6783/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 10.400 | 8.100 | 107.836 | + | cpu/stage1_inst[8] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_inst/g381__5115/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.600 | 111.436 | + | cpu/s1_to_s2_inst/n_22 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.000 | 0.000 | 111.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 29.700 | -22.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 33.200 | 24.200 | 1.836 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.900 | 6.500 | 1.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 43: MET (1.828 ps) Hold Check with Pin cpu/s1_to_s2_inst/register_reg[10]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/register_reg[10]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 85.800 (P) 77.900 (P) + Arrival:= 1.936 -5.964 + + Hold:+ 7.772 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.709 + Launch Clock:= -5.964 + Data Path:+ 117.500 + Slack:= 1.828 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 22.200 | -5.964 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.100 | 21.300 | 15.336 | + | cpu/stage2_inst[8] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2647_stage2_inst_8/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 3 | 8.100 | 29.900 | 45.236 | + | cpu/FE_PHN2647_stage2_inst_8 | | | R | (net) | 3 | | | | + | cpu/stage1/nopsel/g472__3680/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 25.600 | 3.900 | 49.136 | + | cpu/stage1/nopsel/n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g465__2398/Y | | C->Y | F | AND5x1_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 57.036 | + | cpu/stage1/nopsel/FE_PHN4110_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC4110_n_14/Y | | A->Y | F | HB1xp67_ASAP7_75t_L | 1 | 4.000 | 8.600 | 65.636 | + | cpu/stage1/nopsel/n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC2690_n_14/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 6.300 | 7.200 | 72.836 | + | cpu/stage1/nopsel/FE_PHN2690_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 4 | 3.800 | 11.200 | 84.036 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1417_NOPSignal/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 9.100 | 9.400 | 93.436 | + | cpu/stage1/nopselmux/FE_OFN971_FE_DBTN75_NOPSignal | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_OFC843_FE_DBTN75_NOPSignal | | A->Y | R | INVx3_ASAP7_75t_SL | 14 | 5.800 | 6.300 | 99.736 | + | /Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OFN974_FE_DBTN75_NOPSignal | | | R | (net) | 14 | | | | + | cpu/stage1/nopselmux/g386__6131/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 10.400 | 8.100 | 107.836 | + | cpu/stage1_inst[10] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_inst/g384__6161/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.700 | 111.536 | + | cpu/s1_to_s2_inst/n_19 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_inst/register_reg[10]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.400 | 0.000 | 111.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 29.700 | -22.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 33.200 | 24.300 | 1.936 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[10]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.900 | 6.600 | 1.936 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 44: MET (1.874 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[6][24]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[24]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[6][24]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 92.400 (P) 76.500 (P) + Arrival:= 8.536 -7.364 + + Hold:+ 7.226 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 115.762 + Launch Clock:= -7.364 + Data Path:+ 125.000 + Slack:= 1.874 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 25.200 | -7.364 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[24]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 41.500 | 23.300 | 15.936 | + | cpu/stage3_alu[24] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1122/Y | | B1->Y | R | AO22x2_ASAP7_75t_SL | 1 | 10.200 | 11.400 | 27.336 | + | cpu/stage3/wbselmux/n_39 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1115/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 9.200 | 9.100 | 36.436 | + | cpu/wb_data[24] | | | R | (net) | 3 | | | | + | cpu/FE_PHC2702_wb_data_24/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 2 | 7.000 | 32.100 | 68.536 | + | cpu/FE_PHN2702_wb_data_24 | | | R | (net) | 2 | | | | + | cpu/stage1/FE_PHC2873_wb_data_24/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 23.200 | 21.000 | 89.536 | + | cpu/stage1/FE_PHN2873_wb_data_24 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC872_wb_data_24/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 6 | 6.300 | 22.700 | 112.236 | + | cpu/stage1/FE_OFN1003_wb_data_24 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g51159/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 37.800 | 5.400 | 117.636 | + | cpu/stage1/regfile/n_5 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/mem_reg[6][24]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 14.700 | 0.000 | 117.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 25.500 | -24.364 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 30.300 | 9.600 | -14.764 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_27 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00078/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 10.400 | 23.300 | 8.536 | + | cpu/stage1/regfile/CTS_28 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[6][24]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 22.400 | 5.400 | 8.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 45: MET (1.894 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[1]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[24][1]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.500 (P) 82.600 (P) + Arrival:= -3.364 -1.264 + + Hold:+ 8.006 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.642 + Launch Clock:= -1.264 + Data Path:+ 107.800 + Slack:= 1.894 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 21.800 | -30.464 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 21.900 | 7.000 | -23.464 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_9 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00024/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.000 | 22.200 | -1.264 | + | cpu/stage1/regfile/CTS_10 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[24][1]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 18.600 | 20.700 | 19.436 | + | cpu/stage1/regfile/mem[24][1] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2099_mem_24_1/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.700 | 29.400 | 48.836 | + | cpu/stage1/regfile/FE_PHN2099_mem_24_1 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC3812_mem_24_1/Y | | A->Y | R | BUFx2_ASAP7_75t_L | 1 | 14.400 | 9.000 | 57.836 | + | cpu/stage1/regfile/FE_PHN3812_mem_24_1 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g78102/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 4.000 | 5.200 | 63.036 | + | cpu/stage1/regfile/n_1038 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77060/Y | | C->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 7.700 | 6.100 | 69.136 | + | cpu/stage1/regfile/n_2049 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76932__6783/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 1 | 6.400 | 13.700 | 82.836 | + | cpu/stage1/rs2_mux_data[1] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g556__5526/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 16.400 | 10.800 | 93.636 | + | cpu/stage1_rs2[1] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g448__2883/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 6.000 | 4.900 | 98.536 | + | cpu/s1_to_s2_rs2/n_3 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3582_n_3/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 7.100 | 8.000 | 106.536 | + | cpu/s1_to_s2_rs2/FE_PHN3582_n_3 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[1]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 5.600 | 0.000 | 106.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.200 | -3.364 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[1]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.400 | 5.400 | -3.364 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 46: MET (1.923 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[16]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/pcreg/register_reg[16]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[16]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 94.200 (P) 87.800 (P) + Arrival:= 10.336 3.936 + + Hold:+ 7.777 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 118.113 + Launch Clock:= 3.936 + Data Path:+ 116.100 + Slack:= 1.923 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 22.600 | -33.664 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 18.500 | 6.900 | -26.764 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 6.000 | 9.500 | -17.264 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 21.200 | 3.936 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[16]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 2 | 33.200 | 23.100 | 27.036 | + | cpu/stage1/FE_RN_14 | | | R | (net) | 2 | | | | + | cpu/stage1/FE_PHC3368_FE_RN_14/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 10.800 | 28.300 | 55.336 | + | cpu/stage1/FE_PHN3368_FE_RN_14 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC2555_stage1_pc_16/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 12.100 | 35.700 | 91.036 | + | cpu/stage1_pc[16] | | | R | (net) | 3 | | | | + | cpu/stage1/pcselmux/g963__1617/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 23.900 | 8.600 | 99.636 | + | cpu/stage1/pcselmux/n_41 | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g957__6260/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 2 | 5.400 | 6.500 | 106.136 | + | cpu/stage1/stage1_pc_mux_to_pc[16] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/FE_PHC2859_stage1_pc_mux_to_pc_16 | | A->Y | R | HB2xp67_ASAP7_75t_SL | 1 | 5.700 | 10.000 | 116.136 | + | /Y | | | | | | | | | + | cpu/stage1/pcreg/FE_PHN2859_stage1_pc_mux_to_pc_16 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/g356__5122/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.300 | 3.900 | 120.036 | + | cpu/stage1/pcreg/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[16]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.700 | 0.000 | 120.036 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 22.300 | 10.336 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[16]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 36.300 | 6.400 | 10.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 47: MET (1.968 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[5][15]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[15]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[5][15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 107.500 (P) 71.000 (P) + Arrival:= 23.636 -12.864 + + Hold:+ 11.232 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 134.868 + Launch Clock:= -12.864 + Data Path:+ 149.700 + Slack:= 1.968 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 19.700 | -12.864 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[15]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 37.800 | 21.400 | 8.536 | + | cpu/stage3_alu[15] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1121/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.800 | 8.000 | 16.536 | + | cpu/stage3/wbselmux/n_40 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1090/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 5.000 | 9.300 | 25.836 | + | cpu/wb_data[15] | | | R | (net) | 3 | | | | + | cpu/FE_PHC4040_wb_data_15/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 8.300 | 23.100 | 48.936 | + | cpu/FE_PHN4040_wb_data_15 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3529_wb_data_15/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 17.700 | 21.900 | 70.836 | + | cpu/stage1/FE_PHN3529_wb_data_15 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3904_wb_data_15/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 10.600 | 26.800 | 97.636 | + | cpu/stage1/FE_PHN3904_wb_data_15 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC858_wb_data_15/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 6 | 10.100 | 17.800 | 115.436 | + | cpu/stage1/FE_OFN989_wb_data_15 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g81088/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 7 | 26.000 | 21.400 | 136.836 | + | cpu/stage1/regfile/n_148 | | | F | (net) | 7 | | | | + | cpu/stage1/regfile/mem_reg[5][15]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 7 | 41.300 | 0.700 | 136.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 29.900 | -19.564 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.600 | 10.300 | -9.264 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_60 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00081/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 12.100 | 32.900 | 23.636 | + | cpu/stage1/regfile/CTS_61 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[5][15]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.200 | 18.700 | 23.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 48: MET (2.056 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[22][11]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_pc/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[22][11]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 106.400 (P) 73.100 (P) + Arrival:= 22.536 -10.764 + + Hold:+ 11.544 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 134.080 + Launch Clock:= -10.764 + Data Path:+ 146.900 + Slack:= 2.056 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.600 | -31.664 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.300 | 20.900 | -10.764 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 2 | 36.800 | 22.800 | 12.036 | + | cpu/stage3_pc[11] | | | F | (net) | 2 | | | | + | cpu/stage3/pcfour/add_9_31_g752/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 1 | 11.400 | 7.000 | 19.036 | + | cpu/stage3/stage3_pc4[11] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_PHC2680_stage3_pc4_11/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 1 | 5.800 | 14.700 | 33.736 | + | cpu/stage3/wbselmux/FE_PHN2680_stage3_pc4_11 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1129/Y | | A1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.400 | 8.900 | 42.636 | + | cpu/stage3/wbselmux/n_32 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1097/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 4.900 | 9.400 | 52.036 | + | cpu/wb_data[11] | | | R | (net) | 3 | | | | + | cpu/stage1/FE_PHC3522_wb_data_11/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 1 | 8.900 | 24.100 | 76.136 | + | cpu/stage1/FE_PHN3522_wb_data_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3910_wb_data_11/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 9.600 | 7.200 | 83.336 | + | cpu/stage1/FE_PHN3910_wb_data_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OCPC1453_wb_data_11/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 7 | 4.000 | 30.400 | 113.736 | + | cpu/stage1/FE_OCPN1418_wb_data_11 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g81797/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 6 | 56.400 | 22.400 | 136.136 | + | cpu/stage1/regfile/n_40 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/mem_reg[22][11]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 6 | 43.000 | 1.400 | 136.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 28.000 | -21.464 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CG | | CLK->GCLK | R | ICGx2_ASAP7_75t_SL | 1 | 26.300 | 10.900 | -10.564 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_52 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00030/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 10.600 | 33.100 | 22.536 | + | cpu/stage1/regfile/CTS_53 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[22][11]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 49.800 | 19.500 | 22.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 49: MET (2.101 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[21]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[8][20]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 94.300 (P) 80.600 (P) + Arrival:= 10.436 -3.264 + + Hold:+ 7.799 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 118.235 + Launch Clock:= -3.264 + Data Path:+ 123.600 + Slack:= 2.101 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 21.100 | -31.164 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 21.700 | 7.000 | -24.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_23 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00072/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.100 | 20.900 | -3.264 | + | cpu/stage1/regfile/CTS_24 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[8][20]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 16.600 | 20.500 | 17.236 | + | cpu/stage1/regfile/mem[8][20] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2282_mem_8_20/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.800 | 31.400 | 48.636 | + | cpu/stage1/regfile/FE_PHN2282_mem_8_20 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77613/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 17.500 | 8.500 | 57.136 | + | cpu/stage1/regfile/n_1523 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76865__2346/Y | | D->Y | R | NAND4xp75_ASAP7_75t_SL | 1 | 14.200 | 9.200 | 66.336 | + | cpu/stage1/rs1_mux_data[20] | | | R | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g571__9945/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 2 | 8.300 | 10.400 | 76.736 | + | cpu/stage1_rs1[20] | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/g1280__7410/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 6.200 | 8.000 | 84.736 | + | cpu/stage1/pcadder/n_51 | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 3 | 6.000 | 8.900 | 93.636 | + | 33_g1439__6260/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 3 | | | | + | 33_n_12 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | NAND2xp5_ASAP7_75t_L | 1 | 17.000 | 8.500 | 102.136 | + | 33_g1261__9945/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_227 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | XNOR2xp5_ASAP7_75t_SL | 1 | 7.500 | 7.200 | 109.336 | + | 33_g1250__8246/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[21] | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g940__7098/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 5.300 | 7.200 | 116.536 | + | cpu/stage1/stage1_pc_mux_to_pc[21] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g347__6260/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.000 | 3.800 | 120.336 | + | cpu/stage1/pcreg/n_33 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[21]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.000 | 120.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 22.400 | 10.436 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[21]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 36.300 | 6.500 | 10.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 50: MET (2.158 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[31]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[3][31]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 81.200 (P) 85.900 (P) + Arrival:= -2.664 2.036 + + Hold:+ 7.942 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 105.278 + Launch Clock:= 2.036 + Data Path:+ 105.400 + Slack:= 2.158 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 23.900 | -28.364 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 23.200 | 7.500 | -20.864 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_29 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00087/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 7.100 | 22.900 | 2.036 | + | cpu/stage1/regfile/CTS_30 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[3][31]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 18.600 | 20.400 | 22.436 | + | cpu/stage1/regfile/mem[3][31] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3107_mem_3_31/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.400 | 31.500 | 53.936 | + | cpu/stage1/regfile/FE_PHN3107_mem_3_31 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77734/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 17.900 | 5.300 | 59.236 | + | cpu/stage1/regfile/n_1406 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77155/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 1 | 9.700 | 6.000 | 65.236 | + | cpu/stage1/regfile/n_1954 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77082/Y | | C->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 6.300 | 4.700 | 69.936 | + | cpu/stage1/regfile/n_2027 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76997__1881/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 7.100 | 5.700 | 75.636 | + | cpu/stage1/regfile/n_2112 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76939__7098/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 1 | 8.100 | 6.600 | 82.236 | + | cpu/stage1/rs2_mux_data[31] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3943_rs2_mux_data_31/ | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 5.100 | 6.400 | 88.636 | + | Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_PHN3943_rs2_mux_data_31 | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g560__2802/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 4.000 | 8.700 | 97.336 | + | cpu/stage1_rs2[31] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC2793_stage1_rs2_31/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 5.200 | 6.400 | 103.736 | + | cpu/s1_to_s2_rs2/FE_PHN2793_stage1_rs2_31 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g420__2883/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.700 | 107.436 | + | cpu/s1_to_s2_rs2/n_31 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[31]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.300 | 0.000 | 107.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.900 | -2.664 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.600 | 6.100 | -2.664 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + diff --git a/build/par-rundir/timingReports/riscv_top_postRoute_default.tarpt b/build/par-rundir/timingReports/riscv_top_postRoute_default.tarpt new file mode 100644 index 0000000..f0d7845 --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute_default.tarpt @@ -0,0 +1,3115 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:16 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### +Path 1: MET (129.199 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 78.800 (P) 0.000 (I) + Arrival:= 839.800 0.000 + + Clock Gating Setup:- 36.701 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 703.099 + Launch Clock:= 0.000 + Data Path:+ 573.900 + Slack:= 129.199 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 71.500 | 544.500 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77348/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 120.700 | 29.400 | 573.900 | + | cpu/stage1/regfile/n_2203 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 80.300 | 0.300 | 573.900 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 42.300 | 839.800 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 48.000 | 14.600 | 839.800 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 2: MET (131.283 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 79.600 (P) 0.000 (I) + Arrival:= 840.600 0.000 + + Clock Gating Setup:- 36.117 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 704.483 + Launch Clock:= 0.000 + Data Path:+ 573.200 + Slack:= 131.283 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 73.200 | 546.200 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77356/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 121.000 | 27.000 | 573.200 | + | cpu/stage1/regfile/n_2204 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 77.400 | 0.200 | 573.200 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 43.100 | 840.600 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 48.000 | 15.400 | 840.600 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 3: MET (132.516 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 84.300 (P) 0.000 (I) + Arrival:= 845.300 0.000 + + Clock Gating Setup:- 36.784 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 708.516 + Launch Clock:= 0.000 + Data Path:+ 576.000 + Slack:= 132.516 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 71.600 | 544.600 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77259/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 120.700 | 31.400 | 576.000 | + | cpu/stage1/regfile/n_2209 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 82.900 | 0.400 | 576.000 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 39.900 | 845.300 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 39.900 | 2.700 | 845.300 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 4: MET (133.909 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 79.600 (P) 0.000 (I) + Arrival:= 840.600 0.000 + + Clock Gating Setup:- 35.990 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 704.610 + Launch Clock:= 0.000 + Data Path:+ 570.700 + Slack:= 133.909 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 71.300 | 544.300 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77355/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 120.600 | 26.400 | 570.700 | + | cpu/stage1/regfile/n_2205 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 76.800 | 0.200 | 570.700 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 43.100 | 840.600 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 48.000 | 15.400 | 840.600 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 5: MET (134.634 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 79.000 (P) 0.000 (I) + Arrival:= 840.000 0.000 + + Clock Gating Setup:- 35.266 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 704.734 + Launch Clock:= 0.000 + Data Path:+ 570.100 + Slack:= 134.634 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 72.700 | 545.700 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77358/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 121.000 | 24.400 | 570.100 | + | cpu/stage1/regfile/n_2213 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 74.700 | 0.100 | 570.100 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.200 | 840.000 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.600 | 4.000 | 840.000 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 6: MET (138.253 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 80.100 (P) 0.000 (I) + Arrival:= 841.100 0.000 + + Clock Gating Setup:- 36.447 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 704.653 + Launch Clock:= 0.000 + Data Path:+ 566.400 + Slack:= 138.253 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 64.000 | 537.000 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77361/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 118.200 | 29.400 | 566.400 | + | cpu/stage1/regfile/n_2202 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 80.600 | 0.300 | 566.400 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 35.300 | 841.100 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.700 | 5.100 | 841.100 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 7: MET (139.303 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 82.900 (P) 0.000 (I) + Arrival:= 843.900 0.000 + + Clock Gating Setup:- 36.697 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 707.203 + Launch Clock:= 0.000 + Data Path:+ 567.900 + Slack:= 139.303 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 64.000 | 537.000 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77360/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 118.200 | 30.900 | 567.900 | + | cpu/stage1/regfile/n_2210 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 82.500 | 0.400 | 567.900 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 38.500 | 843.900 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 39.400 | 1.300 | 843.900 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 8: MET (141.977 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 79.600 (P) 0.000 (I) + Arrival:= 840.600 0.000 + + Clock Gating Setup:- 35.623 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 704.977 + Launch Clock:= 0.000 + Data Path:+ 563.000 + Slack:= 141.977 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 64.100 | 537.100 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77354/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 118.200 | 25.900 | 563.000 | + | cpu/stage1/regfile/n_2212 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 76.400 | 0.200 | 563.000 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.800 | 840.600 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.600 | 4.600 | 840.600 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 9: MET (144.181 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 85.700 (P) 0.000 (I) + Arrival:= 846.700 0.000 + + Clock Gating Setup:- 36.419 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 710.281 + Launch Clock:= 0.000 + Data Path:+ 566.100 + Slack:= 144.181 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 64.100 | 537.100 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77362/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 118.200 | 29.000 | 566.100 | + | cpu/stage1/regfile/n_2206 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 80.000 | 0.400 | 566.100 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 41.300 | 846.700 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.100 | 4.100 | 846.700 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 10: MET (145.585 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 85.000 (P) 0.000 (I) + Arrival:= 846.000 0.000 + + Clock Gating Setup:- 34.715 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 711.285 + Launch Clock:= 0.000 + Data Path:+ 565.700 + Slack:= 145.585 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 71.600 | 544.600 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77353/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 120.700 | 21.100 | 565.700 | + | cpu/stage1/regfile/n_2211 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 71.700 | 0.000 | 565.700 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 40.600 | 846.000 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.400 | 3.400 | 846.000 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 11: MET (145.957 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 87.800 (P) 0.000 (I) + Arrival:= 848.800 0.000 + + Clock Gating Setup:- 36.543 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 712.257 + Launch Clock:= 0.000 + Data Path:+ 566.300 + Slack:= 145.957 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 64.000 | 537.000 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77357/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 118.200 | 29.300 | 566.300 | + | cpu/stage1/regfile/n_2215 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 80.500 | 0.300 | 566.300 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 43.400 | 848.800 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.900 | 6.200 | 848.800 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 12: MET (149.350 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 79.600 (P) 0.000 (I) + Arrival:= 840.600 0.000 + + Clock Gating Setup:- 29.550 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 711.050 + Launch Clock:= 0.000 + Data Path:+ 561.700 + Slack:= 149.350 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 71.400 | 544.400 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77199/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 120.700 | 17.300 | 561.700 | + | cpu/stage1/regfile/n_2188 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 47.100 | 0.400 | 561.700 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.800 | 840.600 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.600 | 4.600 | 840.600 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 13: MET (149.733 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 89.600 (P) 0.000 (I) + Arrival:= 850.600 0.000 + + Clock Gating Setup:- 36.567 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 714.033 + Launch Clock:= 0.000 + Data Path:+ 564.300 + Slack:= 149.733 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 64.000 | 537.000 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77254/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 118.200 | 27.300 | 564.300 | + | cpu/stage1/regfile/n_2207 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 78.000 | 0.300 | 564.300 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 47.100 | 850.600 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 4 | 53.300 | 2.700 | 850.600 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 14: MET (150.092 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 79.300 (P) 0.000 (I) + Arrival:= 840.300 0.000 + + Clock Gating Setup:- 29.308 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 710.992 + Launch Clock:= 0.000 + Data Path:+ 560.900 + Slack:= 150.092 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 72.300 | 545.300 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77162/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 120.900 | 15.600 | 560.900 | + | cpu/stage1/regfile/n_2189 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 45.200 | 0.300 | 560.900 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 42.800 | 840.300 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 48.000 | 15.100 | 840.300 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 15: MET (151.220 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 79.600 (P) 0.000 (I) + Arrival:= 840.600 0.000 + + Clock Gating Setup:- 29.280 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 711.320 + Launch Clock:= 0.000 + Data Path:+ 560.100 + Slack:= 151.220 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 70.900 | 543.900 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77172/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 120.600 | 16.200 | 560.100 | + | cpu/stage1/regfile/n_2186 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 45.800 | 0.300 | 560.100 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.800 | 840.600 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.600 | 4.600 | 840.600 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 16: MET (151.450 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 83.800 (P) 0.000 (I) + Arrival:= 844.800 0.000 + + Clock Gating Setup:- 34.950 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 709.850 + Launch Clock:= 0.000 + Data Path:+ 558.400 + Slack:= 151.450 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 71.600 | 544.600 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77249/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 120.700 | 13.800 | 558.400 | + | cpu/stage1/regfile/n_2208 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 73.000 | 0.200 | 558.400 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 39.400 | 844.800 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 39.900 | 2.200 | 844.800 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 17: MET (155.212 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 80.000 (P) 0.000 (I) + Arrival:= 841.000 0.000 + + Clock Gating Setup:- 29.488 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 711.512 + Launch Clock:= 0.000 + Data Path:+ 556.300 + Slack:= 155.212 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 66.100 | 539.100 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77203/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 119.500 | 17.200 | 556.300 | + | cpu/stage1/regfile/n_2197 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 46.800 | 0.300 | 556.300 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 35.200 | 841.000 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.700 | 5.000 | 841.000 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 18: MET (155.460 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[9][19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[9][19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 133.700 (P) 0.000 (I) + Arrival:= 894.700 0.000 + + Setup:- 12.141 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 782.560 + Launch Clock:= 0.000 + Data Path:+ 627.100 + Slack:= 155.460 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 105.600 | 525.800 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81126/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 14 | 193.300 | 101.300 | 627.100 | + | cpu/stage1/regfile/n_144 | | | R | (net) | 14 | | | | + | cpu/stage1/regfile/mem_reg[9][19]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 14 | 163.600 | 1.100 | 627.100 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 39.400 | 844.800 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 39.900 | 11.200 | 856.000 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_21 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00069/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 9.500 | 38.700 | 894.700 | + | cpu/stage1/regfile/CTS_22 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[9][19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 48.700 | 6.000 | 894.700 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 19: MET (155.638 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 87.200 (P) 0.000 (I) + Arrival:= 848.200 0.000 + + Clock Gating Setup:- 34.762 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 713.438 + Launch Clock:= 0.000 + Data Path:+ 557.800 + Slack:= 155.638 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 63.800 | 536.800 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77359/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 118.200 | 21.000 | 557.800 | + | cpu/stage1/regfile/n_2214 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 71.800 | 0.000 | 557.800 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 42.800 | 848.200 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.800 | 5.600 | 848.200 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 20: MET (155.946 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 78.100 (P) 0.000 (I) + Arrival:= 839.100 0.000 + + Clock Gating Setup:- 27.854 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 711.246 + Launch Clock:= 0.000 + Data Path:+ 555.300 + Slack:= 155.946 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 70.900 | 543.900 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77202/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 120.600 | 11.400 | 555.300 | + | cpu/stage1/regfile/n_2195 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CG | | ENA | F | ICGx2_ASAP7_75t_SL | 1 | 40.700 | 0.100 | 555.300 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 33.300 | 839.100 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CG | | CLK | R | ICGx2_ASAP7_75t_SL | 9 | 38.300 | 3.100 | 839.100 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 21: MET (156.023 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[23][19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[23][19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 134.200 (P) 0.000 (I) + Arrival:= 895.200 0.000 + + Setup:- 12.177 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 783.023 + Launch Clock:= 0.000 + Data Path:+ 627.000 + Slack:= 156.023 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 105.600 | 525.800 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81126/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 14 | 193.300 | 101.200 | 627.000 | + | cpu/stage1/regfile/n_144 | | | R | (net) | 14 | | | | + | cpu/stage1/regfile/mem_reg[23][19]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 14 | 163.600 | 1.000 | 627.000 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 43.300 | 840.800 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 48.000 | 15.900 | 856.700 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_40 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00027/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 18.200 | 38.500 | 895.200 | + | cpu/stage1/regfile/CTS_41 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[23][19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.200 | 6.700 | 895.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 22: MET (157.405 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 85.500 (P) 0.000 (I) + Arrival:= 846.500 0.000 + + Clock Gating Setup:- 35.795 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 710.705 + Launch Clock:= 0.000 + Data Path:+ 553.300 + Slack:= 157.405 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 64.100 | 537.100 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77250/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 118.200 | 16.200 | 553.300 | + | cpu/stage1/regfile/n_2216 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGI | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 77.000 | 0.300 | 553.300 | + | C_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 41.100 | 846.500 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGI | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.100 | 3.900 | 846.500 | + | C_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 23: MET (157.574 ps) Clock Gating Setup Check with Pin mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) mem_resp_tag[1] + Clock: (R) clk + Endpoint: (F) mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 106.800 (P) 0.000 (I) + Arrival:= 867.800 0.000 + + Clock Gating Setup:- 41.926 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 725.874 + Launch Clock:= 0.000 + Input Delay:+ 180.000 + Data Path:+ 388.300 + Slack:= 157.574 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------------+------+--------------------------+--------+---------+---------+---------| + | mem_resp_tag[1] | | mem_resp_tag[1] | F | (arrival) | 1 | 4.000 | 0.100 | 180.100 | + | mem_resp_tag[1] | | | F | (net) | 1 | | | | + | mem/arbiter/g295/Y | | D->Y | R | NOR4xp25_ASAP7_75t_SL | 2 | 4.000 | 28.800 | 208.900 | + | mem/arbiter/n_2 | | | R | (net) | 2 | | | | + | mem/arbiter/g293/Y | | A->Y | R | AND3x1_ASAP7_75t_SL | 8 | 57.500 | 45.600 | 254.500 | + | mem/ic_mem_resp_valid | | | R | (net) | 8 | | | | + | mem/icache/g8840/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 31 | 61.900 | 110.500 | 365.000 | + | mem/ic_mem_req_valid | | | R | (net) | 31 | | | | + | mem/FE_DBTC0_ic_mem_req_valid/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 12 | 240.900 | 57.800 | 422.800 | + | FE_OFN1444_mem_req_tag_0 | | | F | (net) | 12 | | | | + | mem/arbiter/FE_OFC98_mem_req_tag_0/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 19 | 114.200 | 85.800 | 508.600 | + | mem/arbiter/FE_OFN98_mem_req_tag_0 | | | F | (net) | 19 | | | | + | mem/arbiter/g539/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 3 | 125.800 | 38.900 | 547.500 | + | mem/dc_mem_req_ready | | | F | (net) | 3 | | | | + | mem/dcache/g13992/Y | | B->Y | R | OAI21xp5_ASAP7_75t_SL | 1 | 18.800 | 9.200 | 556.700 | + | mem/dcache/n_101 | | | R | (net) | 1 | | | | + | mem/dcache/g13600/Y | | A2->Y | F | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 26.300 | 11.600 | 568.300 | + | mem/dcache/n_323 | | | F | (net) | 1 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | ENA | F | ICGx1_ASAP7_75t_SRAM | 1 | 24.500 | 0.100 | 568.300 | + | ENA | | | | | | | | | + +-------------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 42.100 | 867.800 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 39.600 | 2.600 | 867.800 | + | CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 24: MET (158.721 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 79.500 (P) 0.000 (I) + Arrival:= 840.500 0.000 + + Clock Gating Setup:- 28.179 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 712.321 + Launch Clock:= 0.000 + Data Path:+ 553.600 + Slack:= 158.721 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 69.300 | 542.300 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77158/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 120.300 | 11.300 | 553.600 | + | cpu/stage1/regfile/n_2187 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 40.500 | 0.100 | 553.600 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.700 | 840.500 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.600 | 4.500 | 840.500 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 25: MET (158.797 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 85.000 (P) 0.000 (I) + Arrival:= 846.000 0.000 + + Clock Gating Setup:- 28.703 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 717.297 + Launch Clock:= 0.000 + Data Path:+ 558.500 + Slack:= 158.797 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 72.000 | 545.000 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77201/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 120.900 | 13.500 | 558.500 | + | cpu/stage1/regfile/n_2201 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 42.900 | 0.200 | 558.500 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 40.600 | 846.000 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.100 | 3.400 | 846.000 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 26: MET (158.925 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 84.400 (P) 0.000 (I) + Arrival:= 845.400 0.000 + + Clock Gating Setup:- 28.375 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 717.025 + Launch Clock:= 0.000 + Data Path:+ 558.100 + Slack:= 158.925 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 73.200 | 546.200 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77179/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 121.000 | 11.900 | 558.100 | + | cpu/stage1/regfile/n_2200 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 41.300 | 0.100 | 558.100 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 40.000 | 845.400 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.200 | 2.800 | 845.400 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 27: MET (159.117 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 79.400 (P) 0.000 (I) + Arrival:= 840.400 0.000 + + Clock Gating Setup:- 28.283 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 712.117 + Launch Clock:= 0.000 + Data Path:+ 553.000 + Slack:= 159.117 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 68.100 | 541.100 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77180/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 120.100 | 11.900 | 553.000 | + | cpu/stage1/regfile/n_2196 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 41.000 | 0.100 | 553.000 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.600 | 840.400 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.600 | 4.400 | 840.400 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 28: MET (159.159 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 85.100 (P) 0.000 (I) + Arrival:= 846.100 0.000 + + Clock Gating Setup:- 28.641 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 717.459 + Launch Clock:= 0.000 + Data Path:+ 558.300 + Slack:= 159.159 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 72.100 | 545.100 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77161/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 120.900 | 13.200 | 558.300 | + | cpu/stage1/regfile/n_2193 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 42.600 | 0.200 | 558.300 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 40.700 | 846.100 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.100 | 3.500 | 846.100 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 29: MET (159.191 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[10][19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[10][19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 137.700 (P) 0.000 (I) + Arrival:= 898.700 0.000 + + Setup:- 12.109 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 786.591 + Launch Clock:= 0.000 + Data Path:+ 627.400 + Slack:= 159.191 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 105.600 | 525.800 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81126/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 14 | 193.300 | 101.600 | 627.400 | + | cpu/stage1/regfile/n_144 | | | R | (net) | 14 | | | | + | cpu/stage1/regfile/mem_reg[10][19]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 14 | 163.600 | 1.400 | 627.400 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 47.100 | 850.600 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 53.300 | 12.000 | 862.600 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_37 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00066/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 10.900 | 36.100 | 898.700 | + | cpu/stage1/regfile/CTS_36 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[10][19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.900 | 7.200 | 898.700 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 30: MET (159.502 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 86.500 (P) 0.000 (I) + Arrival:= 847.500 0.000 + + Clock Gating Setup:- 28.998 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 718.502 + Launch Clock:= 0.000 + Data Path:+ 559.000 + Slack:= 159.502 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 71.200 | 544.200 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77200/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 120.600 | 14.800 | 559.000 | + | cpu/stage1/regfile/n_2199 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 44.200 | 0.300 | 559.000 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 42.100 | 847.500 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.700 | 4.900 | 847.500 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 31: MET (159.751 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 85.400 (P) 0.000 (I) + Arrival:= 846.400 0.000 + + Clock Gating Setup:- 28.349 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 718.051 + Launch Clock:= 0.000 + Data Path:+ 558.300 + Slack:= 159.751 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 73.500 | 546.500 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77198/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 121.100 | 11.800 | 558.300 | + | cpu/stage1/regfile/n_2192 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 41.200 | 0.100 | 558.300 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 41.000 | 846.400 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.100 | 3.800 | 846.400 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 32: MET (160.203 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 79.800 (P) 0.000 (I) + Arrival:= 840.800 0.000 + + Clock Gating Setup:- 28.697 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 712.103 + Launch Clock:= 0.000 + Data Path:+ 551.900 + Slack:= 160.203 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 65.600 | 538.600 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77178/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 119.300 | 13.300 | 551.900 | + | cpu/stage1/regfile/n_2194 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 42.300 | 0.200 | 551.900 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 43.300 | 840.800 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 48.000 | 15.600 | 840.800 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 33: MET (160.351 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[15][19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[15][19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 138.600 (P) 0.000 (I) + Arrival:= 899.600 0.000 + + Setup:- 12.249 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 787.351 + Launch Clock:= 0.000 + Data Path:+ 627.000 + Slack:= 160.351 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 105.600 | 525.800 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81126/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 14 | 193.300 | 101.200 | 627.000 | + | cpu/stage1/regfile/n_144 | | | R | (net) | 14 | | | | + | cpu/stage1/regfile/mem_reg[15][19]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 14 | 163.600 | 1.000 | 627.000 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 35.300 | 841.100 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.700 | 14.600 | 855.700 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_58 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00051/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 16.300 | 43.900 | 899.600 | + | cpu/stage1/regfile/CTS_59 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[15][19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 59.100 | 13.000 | 899.600 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 34: MET (160.814 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 87.700 (P) 0.000 (I) + Arrival:= 848.700 0.000 + + Clock Gating Setup:- 29.086 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 719.614 + Launch Clock:= 0.000 + Data Path:+ 558.800 + Slack:= 160.814 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 70.700 | 543.700 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77171/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 120.600 | 15.100 | 558.800 | + | cpu/stage1/regfile/n_2190 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 44.600 | 0.300 | 558.800 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 43.300 | 848.700 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.900 | 6.100 | 848.700 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 35: MET (161.104 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 87.100 (P) 0.000 (I) + Arrival:= 848.100 0.000 + + Clock Gating Setup:- 28.896 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 719.204 + Launch Clock:= 0.000 + Data Path:+ 558.100 + Slack:= 161.104 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 70.900 | 543.900 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77157/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 120.600 | 14.200 | 558.100 | + | cpu/stage1/regfile/n_2191 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 43.700 | 0.200 | 558.100 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 42.700 | 848.100 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.800 | 5.500 | 848.100 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 36: MET (161.540 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[17][19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[17][19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 139.300 (P) 0.000 (I) + Arrival:= 900.300 0.000 + + Setup:- 12.160 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 788.140 + Launch Clock:= 0.000 + Data Path:+ 626.600 + Slack:= 161.540 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 105.600 | 525.800 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81126/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 14 | 193.300 | 100.800 | 626.600 | + | cpu/stage1/regfile/n_144 | | | R | (net) | 14 | | | | + | cpu/stage1/regfile/mem_reg[17][19]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 14 | 163.600 | 0.600 | 626.600 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 40.000 | 845.400 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 40.200 | 12.100 | 857.500 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_15 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00045/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 11.200 | 42.800 | 900.300 | + | cpu/stage1/regfile/CTS_16 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[17][19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.600 | 3.900 | 900.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 37: MET (161.964 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 87.800 (P) 0.000 (I) + Arrival:= 848.800 0.000 + + Clock Gating Setup:- 28.836 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 719.964 + Launch Clock:= 0.000 + Data Path:+ 558.000 + Slack:= 161.964 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 68.500 | 68.700 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 26.500 | 76.300 | 145.000 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 54.000 | 60.200 | 205.200 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 30.500 | 86.900 | 292.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | R | INVx2_ASAP7_75t_L | 46 | 182.900 | 91.100 | 383.200 | + | cpu/stage1/FE_DBTN77_reset | | | R | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 180.800 | 89.800 | 473.000 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | R | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC93_FE_DBTN77_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 41 | 212.600 | 71.000 | 544.000 | + | cpu/stage1/regfile/FE_OFN93_FE_DBTN77_reset | | | R | (net) | 41 | | | | + | cpu/stage1/regfile/g77246/Y | | B->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 120.600 | 14.000 | 558.000 | + | cpu/stage1/regfile/n_2198 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 43.400 | 0.200 | 558.000 | + | IC_INST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 43.400 | 848.800 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.900 | 6.200 | 848.800 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 38: MET (162.175 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[8][26]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[8][26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 138.300 (P) 0.000 (I) + Arrival:= 899.300 0.000 + + Setup:- 18.725 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.575 + Launch Clock:= 0.000 + Data Path:+ 618.400 + Slack:= 162.175 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 110.800 | 531.000 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81625/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 10 | 193.600 | 87.400 | 618.400 | + | cpu/stage1/regfile/n_70 | | | R | (net) | 10 | | | | + | cpu/stage1/regfile/mem_reg[8][26]/D | | D | R | DFFHQNx1_ASAP7_75t_R | 10 | 139.800 | 0.300 | 618.400 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 39.900 | 845.300 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 39.900 | 11.800 | 857.100 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_23 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00072/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 10.600 | 42.200 | 899.300 | + | cpu/stage1/regfile/CTS_24 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[8][26]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_R | 32 | 50.800 | 5.300 | 899.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 39: MET (164.284 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[1][19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[1][19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 142.200 (P) 0.000 (I) + Arrival:= 903.200 0.000 + + Setup:- 12.216 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.984 + Launch Clock:= 0.000 + Data Path:+ 626.700 + Slack:= 164.284 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 105.600 | 525.800 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81126/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 14 | 193.300 | 100.900 | 626.700 | + | cpu/stage1/regfile/n_144 | | | R | (net) | 14 | | | | + | cpu/stage1/regfile/mem_reg[1][19]/D | | D | R | DFFHQNx1_ASAP7_75t_L | 14 | 163.600 | 0.700 | 626.700 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 41.100 | 846.500 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGI | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 40.100 | 13.000 | 859.500 | + | C_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_34 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00093/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 13.100 | 43.700 | 903.200 | + | cpu/stage1/regfile/CTS_33 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[1][19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 50.500 | 8.100 | 903.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 40: MET (164.453 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[29][19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[29][19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 142.700 (P) 0.000 (I) + Arrival:= 903.700 0.000 + + Setup:- 12.247 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.453 + Launch Clock:= 0.000 + Data Path:+ 627.000 + Slack:= 164.453 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 105.600 | 525.800 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81126/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 14 | 193.300 | 101.200 | 627.000 | + | cpu/stage1/regfile/n_144 | | | R | (net) | 14 | | | | + | cpu/stage1/regfile/mem_reg[29][19]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 14 | 163.600 | 1.000 | 627.000 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.800 | 840.600 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.600 | 15.000 | 855.600 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_50 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00009/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 16.600 | 48.100 | 903.700 | + | cpu/stage1/regfile/CTS_51 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[29][19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 58.300 | 10.600 | 903.700 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 41: MET (164.518 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[16][19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[16][19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 142.300 (P) 0.000 (I) + Arrival:= 903.300 0.000 + + Setup:- 12.082 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.218 + Launch Clock:= 0.000 + Data Path:+ 626.700 + Slack:= 164.518 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 105.600 | 525.800 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81126/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 14 | 193.300 | 100.900 | 626.700 | + | cpu/stage1/regfile/n_144 | | | R | (net) | 14 | | | | + | cpu/stage1/regfile/mem_reg[16][19]/D | | D | R | DFFHQNx1_ASAP7_75t_L | 14 | 163.600 | 0.700 | 626.700 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 40.600 | 846.000 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 40.100 | 12.100 | 858.100 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_17 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00048/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 11.100 | 45.200 | 903.300 | + | cpu/stage1/regfile/CTS_18 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[16][19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 54.900 | 7.900 | 903.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 42: MET (165.069 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[5][19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[5][19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 143.400 (P) 0.000 (I) + Arrival:= 904.400 0.000 + + Setup:- 12.331 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.069 + Launch Clock:= 0.000 + Data Path:+ 627.000 + Slack:= 165.069 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 105.600 | 525.800 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81126/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 14 | 193.300 | 101.200 | 627.000 | + | cpu/stage1/regfile/n_144 | | | R | (net) | 14 | | | | + | cpu/stage1/regfile/mem_reg[5][19]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 14 | 163.600 | 1.000 | 627.000 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.800 | 840.600 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.600 | 15.000 | 855.600 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_60 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00081/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 16.900 | 48.800 | 904.400 | + | cpu/stage1/regfile/CTS_61 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[5][19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 66.400 | 16.200 | 904.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 43: MET (165.124 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[9][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[9][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 135.800 (P) 0.000 (I) + Arrival:= 896.800 0.000 + + Setup:- 10.976 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 785.824 + Launch Clock:= 0.000 + Data Path:+ 620.700 + Slack:= 165.124 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 111.900 | 532.100 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81268/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 10 | 194.200 | 88.600 | 620.700 | + | cpu/stage1/regfile/n_124 | | | R | (net) | 10 | | | | + | cpu/stage1/regfile/mem_reg[9][14]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 10 | 139.500 | 1.300 | 620.700 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 39.400 | 844.800 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 39.900 | 11.200 | 856.000 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_21 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00069/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 9.500 | 40.800 | 896.800 | + | cpu/stage1/regfile/CTS_22 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[9][14]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 49.500 | 8.100 | 896.800 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 44: MET (166.303 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[14][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[14][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 135.200 (P) 0.000 (I) + Arrival:= 896.200 0.000 + + Setup:- 10.797 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 785.403 + Launch Clock:= 0.000 + Data Path:+ 619.100 + Slack:= 166.303 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 111.900 | 532.100 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81512/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 10 | 194.200 | 87.000 | 619.100 | + | cpu/stage1/regfile/n_85 | | | R | (net) | 10 | | | | + | cpu/stage1/regfile/mem_reg[14][14]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 10 | 136.000 | 1.400 | 619.100 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 42.300 | 839.800 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 48.000 | 17.000 | 856.800 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_42 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00054/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 20.600 | 39.400 | 896.200 | + | cpu/stage1/regfile/CTS_43 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[14][14]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 49.000 | 7.000 | 896.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 45: MET (166.413 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[11][19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[11][19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 144.800 (P) 0.000 (I) + Arrival:= 905.800 0.000 + + Setup:- 12.187 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 793.613 + Launch Clock:= 0.000 + Data Path:+ 627.200 + Slack:= 166.413 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 105.600 | 525.800 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81126/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 14 | 193.300 | 101.400 | 627.200 | + | cpu/stage1/regfile/n_144 | | | R | (net) | 14 | | | | + | cpu/stage1/regfile/mem_reg[11][19]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 14 | 163.600 | 1.200 | 627.200 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 41.300 | 846.700 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 40.100 | 12.200 | 858.900 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_19 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00063/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 11.500 | 46.900 | 905.800 | + | cpu/stage1/regfile/CTS_20 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[11][19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.600 | 8.300 | 905.800 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 46: MET (166.561 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[13][19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[13][19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 144.600 (P) 0.000 (I) + Arrival:= 905.600 0.000 + + Setup:- 12.139 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 793.461 + Launch Clock:= 0.000 + Data Path:+ 626.900 + Slack:= 166.561 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 105.600 | 525.800 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81126/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 14 | 193.300 | 101.100 | 626.900 | + | cpu/stage1/regfile/n_144 | | | R | (net) | 14 | | | | + | cpu/stage1/regfile/mem_reg[13][19]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 14 | 163.600 | 0.900 | 626.900 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 43.100 | 840.600 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 48.000 | 20.200 | 860.800 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_44 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00057/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 26.800 | 44.800 | 905.600 | + | cpu/stage1/regfile/CTS_45 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[13][19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 50.000 | 5.400 | 905.600 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 47: MET (166.981 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[23][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[23][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 138.000 (P) 0.000 (I) + Arrival:= 899.000 0.000 + + Setup:- 11.019 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 787.981 + Launch Clock:= 0.000 + Data Path:+ 621.000 + Slack:= 166.981 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 111.900 | 532.100 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81268/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 10 | 194.200 | 88.900 | 621.000 | + | cpu/stage1/regfile/n_124 | | | R | (net) | 10 | | | | + | cpu/stage1/regfile/mem_reg[23][14]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 10 | 139.500 | 1.600 | 621.000 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 43.300 | 840.800 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 48.000 | 15.900 | 856.700 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_40 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00027/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 18.200 | 42.300 | 899.000 | + | cpu/stage1/regfile/CTS_41 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[23][14]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 54.200 | 10.500 | 899.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 48: MET (167.226 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[30][28]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[30][28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 132.800 (P) 0.000 (I) + Arrival:= 893.800 0.000 + + Setup:- 11.674 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 782.126 + Launch Clock:= 0.000 + Data Path:+ 614.900 + Slack:= 167.226 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 98.500 | 518.700 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81566/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 12 | 191.400 | 96.200 | 614.900 | + | cpu/stage1/regfile/n_78 | | | R | (net) | 12 | | | | + | cpu/stage1/regfile/mem_reg[30][28]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 12 | 153.800 | 1.500 | 614.900 | + +------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.700 | 840.500 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.600 | 13.100 | 853.600 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_48 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00006/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 13.200 | 40.200 | 893.800 | + | cpu/stage1/regfile/CTS_49 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[30][28]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 54.900 | 10.200 | 893.800 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 49: MET (167.402 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[3][19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[3][19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 145.900 (P) 0.000 (I) + Arrival:= 906.900 0.000 + + Setup:- 12.198 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 794.702 + Launch Clock:= 0.000 + Data Path:+ 627.300 + Slack:= 167.402 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 105.600 | 525.800 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81126/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 14 | 193.300 | 101.500 | 627.300 | + | cpu/stage1/regfile/n_144 | | | R | (net) | 14 | | | | + | cpu/stage1/regfile/mem_reg[3][19]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 14 | 163.600 | 1.300 | 627.300 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 42.800 | 848.200 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 40.800 | 12.800 | 861.000 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_29 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00087/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 12.600 | 45.900 | 906.900 | + | cpu/stage1/regfile/CTS_30 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[3][19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 54.700 | 7.000 | 906.900 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 50: MET (167.664 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[10][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[10][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 0.000 + Net Latency:+ 138.800 (P) 0.000 (I) + Arrival:= 899.800 0.000 + + Setup:- 10.936 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 788.864 + Launch Clock:= 0.000 + Data Path:+ 621.200 + Slack:= 167.664 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-----------------------------------------------+-------+-------+------+-----------------------+--------+---------+---------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.200 | 0.200 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 52.100 | 52.300 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 27.900 | 69.500 | 121.800 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 66.800 | 62.500 | 184.300 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 34.200 | 99.300 | 283.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/FE_DBTC77_reset/Y | | A->Y | F | INVx2_ASAP7_75t_L | 46 | 221.200 | 78.700 | 362.300 | + | cpu/stage1/FE_DBTN77_reset | | | F | (net) | 46 | | | | + | cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 156.900 | 57.900 | 420.200 | + | cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset | | | F | (net) | 48 | | | | + | cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 58 | 144.800 | 111.900 | 532.100 | + | cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset | | | F | (net) | 58 | | | | + | cpu/stage1/regfile/g81268/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 10 | 194.200 | 89.100 | 621.200 | + | cpu/stage1/regfile/n_124 | | | R | (net) | 10 | | | | + | cpu/stage1/regfile/mem_reg[10][14]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 10 | 139.500 | 1.800 | 621.200 | + +-------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 47.100 | 850.600 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 53.300 | 12.000 | 862.600 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_37 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00066/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 10.900 | 37.200 | 899.800 | + | cpu/stage1/regfile/CTS_36 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[10][14]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 47.000 | 8.300 | 899.800 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + diff --git a/build/par-rundir/timingReports/riscv_top_postRoute_default_hold.tarpt b/build/par-rundir/timingReports/riscv_top_postRoute_default_hold.tarpt new file mode 100644 index 0000000..edbba29 --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute_default_hold.tarpt @@ -0,0 +1,2983 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:14 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### +Path 1: MET (11.876 ps) Hold Check with Pin mem/dcache/STATE_reg[2]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) mem/dcache/STATE_reg[2]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 80.100 (P) 0.000 (I) + Arrival:= -3.764 0.000 + + Hold:+ 0.887 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 97.124 + Launch Clock:= 0.000 + Data Path:+ 109.000 + Slack:= 11.876 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------+-------+-------+------+--------------------------+--------+--------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.600 | 92.500 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | mem/dcache/FE_DBTC5_reset/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 16.200 | 5.100 | 97.600 | + | mem/dcache/FE_DBTN5_reset | | | F | (net) | 3 | | | | + | mem/dcache/g11190/Y | | C->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 9.300 | 4.000 | 101.600 | + | mem/dcache/n_57 | | | R | (net) | 1 | | | | + | mem/dcache/FE_PHC3589_n_57/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 5.300 | 7.400 | 109.000 | + | mem/dcache/FE_PHN3589_n_57 | | | R | (net) | 1 | | | | + | mem/dcache/STATE_reg[2]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 5.900 | 0.000 | 109.000 | + +---------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 20.500 | -20.364 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 23.000 | 16.600 | -3.764 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[2]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 3 | 12.400 | 0.200 | -3.764 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 2: MET (12.523 ps) Hold Check with Pin mem/dcache/STATE_reg[1]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) mem/dcache/STATE_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 80.100 (P) 0.000 (I) + Arrival:= -3.764 0.000 + + Hold:+ 0.841 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 97.077 + Launch Clock:= 0.000 + Data Path:+ 109.600 + Slack:= 12.523 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------+-------+-------+------+--------------------------+--------+--------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.600 | 92.500 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | mem/dcache/FE_DBTC5_reset/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 16.200 | 5.100 | 97.600 | + | mem/dcache/FE_DBTN5_reset | | | F | (net) | 3 | | | | + | mem/dcache/FE_PHC4015_FE_DBTN5_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 9.300 | 7.500 | 105.100 | + | mem/dcache/FE_PHN4015_FE_DBTN5_reset | | | F | (net) | 1 | | | | + | mem/dcache/g11166/Y | | C->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 4.000 | 4.500 | 109.600 | + | mem/dcache/n_81 | | | R | (net) | 1 | | | | + | mem/dcache/STATE_reg[1]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.100 | 109.600 | + +-------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 20.500 | -20.364 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 23.000 | 16.600 | -3.764 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[1]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 3 | 12.400 | 0.200 | -3.764 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 3: MET (19.190 ps) Hold Check with Pin mem/dcache/STATE_reg[0]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (F) mem/dcache/STATE_reg[0]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 80.000 (P) 0.000 (I) + Arrival:= -3.864 0.000 + + Hold:+ 6.774 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 102.910 + Launch Clock:= 0.000 + Data Path:+ 122.100 + Slack:= 19.190 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------+-------+-------+------+--------------------------+--------+--------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.700 | 92.600 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | mem/dcache/g11141/Y | | C->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 16.200 | 6.100 | 98.700 | + | mem/dcache/n_82 | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC3578_n_82/Y | | A->Y | F | HB4xp67_ASAP7_75t_SL | 1 | 9.200 | 23.400 | 122.100 | + | mem/dcache/FE_PHN3578_n_82 | | | F | (net) | 1 | | | | + | mem/dcache/STATE_reg[0]/D | | D | F | DFFHQx4_ASAP7_75t_SL | 1 | 9.900 | 0.000 | 122.100 | + +---------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 20.500 | -20.364 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 23.000 | 16.500 | -3.864 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[0]/CLK | | CLK | R | DFFHQx4_ASAP7_75t_SL | 3 | 12.400 | 0.100 | -3.864 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 4: MET (36.806 ps) Clock Gating Hold Check with Pin mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 63.500 (P) 0.000 (I) + Arrival:= -20.364 0.000 + + Clock Gating Hold:+ -13.842 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 65.794 + Launch Clock:= 0.000 + Data Path:+ 102.600 + Slack:= 36.806 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+--------------------------+--------+--------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.600 | 92.500 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | mem/dcache/FE_DBTC5_reset/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 16.200 | 5.100 | 97.600 | + | mem/dcache/FE_DBTN5_reset | | | F | (net) | 3 | | | | + | mem/dcache/g13600/Y | | C->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 9.300 | 5.000 | 102.600 | + | mem/dcache/n_323 | | | R | (net) | 1 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | ENA | R | ICGx1_ASAP7_75t_SRAM | 1 | 6.800 | 0.100 | 102.600 | + | ENA | | | | | | | | | + +-------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 20.500 | -20.364 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 23.000 | 2.900 | -20.364 | + | CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 5: MET (37.149 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[30]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 83.400 (P) 0.000 (I) + Arrival:= -0.464 0.000 + + Hold:+ 8.714 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 108.251 + Launch Clock:= 0.000 + Data Path:+ 145.400 + Slack:= 37.149 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 39.800 | 140.200 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g434__7098/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 107.600 | -2.100 | 138.100 | + | cpu/s2_to_s3_alu/n_17 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2849_n_17/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 4.600 | 7.300 | 145.400 | + | cpu/s2_to_s3_alu/FE_PHN2849_n_17 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[30]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 5.200 | 0.000 | 145.400 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 27.400 | -0.464 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[30]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.000 | 10.400 | -0.464 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 6: MET (41.807 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[31]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 83.000 (P) 0.000 (I) + Arrival:= -0.864 0.000 + + Hold:+ 8.657 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 107.793 + Launch Clock:= 0.000 + Data Path:+ 149.600 + Slack:= 41.807 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 44.000 | 144.400 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g420__5477/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 110.300 | -2.700 | 141.700 | + | cpu/s2_to_s3_alu/n_31 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC3942_n_31/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 6.000 | 7.900 | 149.600 | + | cpu/s2_to_s3_alu/FE_PHN3942_n_31 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[31]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 5.800 | 0.000 | 149.600 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 27.000 | -0.864 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.000 | 10.000 | -0.864 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 7: MET (42.841 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[11]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (F) cpu/stage1/pcreg/register_reg[11]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 95.100 (P) 0.000 (I) + Arrival:= 11.236 0.000 + + Hold:+ 8.123 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 119.359 + Launch Clock:= 0.000 + Data Path:+ 162.200 + Slack:= 42.841 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 47.200 | 140.000 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/pcreg/g377__8428/Y | | A->Y | F | NOR2xp33_ASAP7_75t_L | 1 | 135.000 | 14.800 | 154.800 | + | cpu/stage1/pcreg/n_3 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2868_n_3/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 5.000 | 7.400 | 162.200 | + | cpu/stage1/pcreg/FE_PHN2868_n_3 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[11]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 5.400 | 0.000 | 162.200 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 23.200 | 11.236 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[11]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 38.300 | 7.300 | 11.236 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 8: MET (42.962 ps) Hold Check with Pin cpu/stage3/csr/csr_reg[30]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage3/csr/csr_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 85.700 (P) 0.000 (I) + Arrival:= 1.836 0.000 + + Hold:+ 7.302 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.138 + Launch Clock:= 0.000 + Data Path:+ 152.100 + Slack:= 42.962 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |---------------------------------+-------+-------+------+-----------------------+--------+--------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 26.600 | 98.700 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/stage3/csr/g196/Y | | A->Y | R | INVx1_ASAP7_75t_L | 32 | 15.100 | 42.600 | 141.300 | + | cpu/stage3/csr/n_0 | | | R | (net) | 32 | | | | + | cpu/stage3/csr/g191/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 95.200 | 2.800 | 144.100 | + | cpu/stage3/csr/n_4 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2839_n_4/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 8.300 | 8.000 | 152.100 | + | cpu/stage3/csr/FE_PHN2839_n_4 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[30]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 5.300 | 0.000 | 152.100 | + +---------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 23.700 | 20.400 | 1.836 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[30]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 30.300 | 2.000 | 1.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 9: MET (43.165 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[29]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 83.400 (P) 0.000 (I) + Arrival:= -0.464 0.000 + + Hold:+ 9.999 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.535 + Launch Clock:= 0.000 + Data Path:+ 152.700 + Slack:= 43.165 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 42.500 | 142.900 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g421__2398/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 109.400 | -1.500 | 141.400 | + | cpu/s2_to_s3_alu/n_30 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2840_n_30/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 5.100 | 11.300 | 152.700 | + | cpu/s2_to_s3_alu/FE_PHN2840_n_30 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[29]/D | | D | F | DFFHQNx1_ASAP7_75t_L | 1 | 6.300 | 0.000 | 152.700 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 27.400 | -0.464 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[29]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 46.000 | 10.400 | -0.464 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 10: MET (43.362 ps) Hold Check with Pin cpu/stage3/csr/csr_reg[31]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage3/csr/csr_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 85.700 (P) 0.000 (I) + Arrival:= 1.836 0.000 + + Hold:+ 7.302 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.138 + Launch Clock:= 0.000 + Data Path:+ 152.500 + Slack:= 43.362 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------+-------+-------+------+-----------------------+--------+--------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 26.600 | 98.700 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/stage3/csr/g196/Y | | A->Y | R | INVx1_ASAP7_75t_L | 32 | 15.100 | 42.600 | 141.300 | + | cpu/stage3/csr/n_0 | | | R | (net) | 32 | | | | + | cpu/stage3/csr/g178/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 95.200 | 3.000 | 144.300 | + | cpu/stage3/csr/n_17 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2848_n_17/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 9.800 | 8.200 | 152.500 | + | cpu/stage3/csr/FE_PHN2848_n_17 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[31]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 5.300 | 0.000 | 152.500 | + +----------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 23.700 | 20.400 | 1.836 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 30.300 | 2.000 | 1.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 11: MET (47.613 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[10]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (F) cpu/stage1/pcreg/register_reg[10]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 96.100 (P) 0.000 (I) + Arrival:= 12.236 0.000 + + Hold:+ 8.350 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 120.587 + Launch Clock:= 0.000 + Data Path:+ 168.200 + Slack:= 47.613 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 50.700 | 143.500 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/pcreg/g376__4319/Y | | A->Y | F | NOR2xp33_ASAP7_75t_L | 1 | 137.100 | 17.400 | 160.900 | + | cpu/stage1/pcreg/n_4 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2862_n_4/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 7.100 | 7.300 | 168.200 | + | cpu/stage1/pcreg/FE_PHN2862_n_4 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[10]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 4.000 | 0.000 | 168.200 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 24.200 | 12.236 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[10]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 38.700 | 8.300 | 12.236 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 12: MET (48.548 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[2]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[2]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 80.800 (P) 0.000 (I) + Arrival:= -3.064 0.000 + + Hold:+ 12.116 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.052 + Launch Clock:= 0.000 + Data Path:+ 157.600 + Slack:= 48.548 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------------+-------+-------+------+------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 58.200 | 158.600 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g422__5107/Y | | A->Y | F | NAND2xp33_ASAP7_75t_SL | 1 | 114.600 | -1.000 | 157.600 | + | cpu/s2_to_s3_alu/n_29 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[2]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 22.200 | 0.000 | 157.600 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 24.800 | -3.064 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[2]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 42.700 | 7.800 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 13: MET (49.118 ps) Hold Check with Pin cpu/stage3/csr/csr_reg[29]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage3/csr/csr_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 85.800 (P) 0.000 (I) + Arrival:= 1.936 0.000 + + Hold:+ 7.246 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.182 + Launch Clock:= 0.000 + Data Path:+ 158.300 + Slack:= 49.118 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------+-------+-------+------+-----------------------+--------+--------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 26.600 | 98.700 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/stage3/csr/g196/Y | | A->Y | R | INVx1_ASAP7_75t_L | 32 | 15.100 | 42.600 | 141.300 | + | cpu/stage3/csr/n_0 | | | R | (net) | 32 | | | | + | cpu/stage3/csr/g164/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 95.200 | 4.500 | 145.800 | + | cpu/stage3/csr/n_31 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2835_n_31/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 10.200 | 12.500 | 158.300 | + | cpu/stage3/csr/FE_PHN2835_n_31 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[29]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.000 | 158.300 | + +----------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 23.700 | 20.500 | 1.936 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[29]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 30.300 | 2.100 | 1.936 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 14: MET (52.612 ps) Hold Check with Pin mem/icache/STATE_reg[0]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) mem/icache/STATE_reg[0]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 76.800 (P) 0.000 (I) + Arrival:= -7.064 0.000 + + Hold:+ 0.451 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 93.388 + Launch Clock:= 0.000 + Data Path:+ 146.000 + Slack:= 52.612 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 22.000 | 114.800 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | mem/icache/g7254/Y | | D->Y | R | OR4x1_ASAP7_75t_SL | 1 | 109.100 | 4.300 | 119.100 | + | mem/icache/FE_PHN2697_n_78 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC2697_n_78/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.300 | 26.900 | 146.000 | + | mem/icache/n_78 | | | R | (net) | 1 | | | | + | mem/icache/STATE_reg[0]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 11.800 | 0.100 | 146.000 | + +-------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 17.900 | -22.964 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 21.400 | 15.900 | -7.064 | + | GCLK | | | | | | | | | + | mem/icache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/icache/STATE_reg[0]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 3 | 11.800 | 0.100 | -7.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 15: MET (54.340 ps) Hold Check with Pin mem/icache/STATE_reg[1]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) mem/icache/STATE_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 76.800 (P) 0.000 (I) + Arrival:= -7.064 0.000 + + Hold:+ 0.524 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 93.460 + Launch Clock:= 0.000 + Data Path:+ 147.800 + Slack:= 54.340 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 22.000 | 114.800 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | mem/icache/g7279/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 1 | 109.100 | 6.800 | 121.600 | + | mem/icache/n_77 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC3543_n_77/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 5.000 | 26.200 | 147.800 | + | mem/icache/FE_PHN3543_n_77 | | | R | (net) | 1 | | | | + | mem/icache/STATE_reg[1]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 10.800 | 0.000 | 147.800 | + +-------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 17.900 | -22.964 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 21.400 | 15.900 | -7.064 | + | GCLK | | | | | | | | | + | mem/icache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/icache/STATE_reg[1]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 3 | 11.800 | 0.100 | -7.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 16: MET (54.576 ps) Hold Check with Pin mem/icache/STATE_reg[2]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) mem/icache/STATE_reg[2]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 76.800 (P) 0.000 (I) + Arrival:= -7.064 0.000 + + Hold:+ 0.488 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 93.424 + Launch Clock:= 0.000 + Data Path:+ 148.000 + Slack:= 54.576 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 22.000 | 114.800 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | mem/icache/g7336/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 1 | 109.100 | 6.700 | 121.500 | + | mem/icache/n_51 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC3544_n_51/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.900 | 26.500 | 148.000 | + | mem/icache/FE_PHN3544_n_51 | | | R | (net) | 1 | | | | + | mem/icache/STATE_reg[2]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 11.300 | 0.000 | 148.000 | + +-------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 17.900 | -22.964 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 21.400 | 15.900 | -7.064 | + | GCLK | | | | | | | | | + | mem/icache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/icache/STATE_reg[2]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 3 | 11.800 | 0.100 | -7.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 17: MET (55.209 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[9]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (F) cpu/stage1/pcreg/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 97.700 (P) 0.000 (I) + Arrival:= 13.836 0.000 + + Hold:+ 8.054 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 121.891 + Launch Clock:= 0.000 + Data Path:+ 177.100 + Slack:= 55.209 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 54.100 | 146.900 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/pcreg/g375__6260/Y | | A->Y | F | NOR2xp33_ASAP7_75t_L | 1 | 138.300 | 18.200 | 165.100 | + | cpu/stage1/pcreg/n_5 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2860_n_5/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 7.500 | 12.000 | 177.100 | + | cpu/stage1/pcreg/FE_PHN2860_n_5 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[9]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.000 | 177.100 | + +-------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 25.800 | 13.836 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[9]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 39.100 | 9.900 | 13.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 18: MET (56.282 ps) Hold Check with Pin cpu/stage3/csr/csr_reg[28]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage3/csr/csr_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 85.800 (P) 0.000 (I) + Arrival:= 1.936 0.000 + + Hold:+ 7.182 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.118 + Launch Clock:= 0.000 + Data Path:+ 165.400 + Slack:= 56.282 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |---------------------------------+-------+-------+------+-----------------------+--------+--------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 26.600 | 98.700 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/stage3/csr/g196/Y | | A->Y | R | INVx1_ASAP7_75t_L | 32 | 15.100 | 42.000 | 140.700 | + | cpu/stage3/csr/n_0 | | | R | (net) | 32 | | | | + | cpu/stage3/csr/g190/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 95.100 | 6.000 | 146.700 | + | cpu/stage3/csr/n_5 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2779_n_5/Y | | A->Y | F | HB3xp67_ASAP7_75t_SL | 1 | 16.200 | 18.700 | 165.400 | + | cpu/stage3/csr/FE_PHN2779_n_5 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[28]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 8.100 | 0.000 | 165.400 | + +---------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 23.700 | 20.500 | 1.936 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[28]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 30.300 | 2.100 | 1.936 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 19: MET (60.631 ps) Clock Gating Hold Check with Pin mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 60.900 (P) 0.000 (I) + Arrival:= -22.964 0.000 + + Clock Gating Hold:+ -13.567 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 63.469 + Launch Clock:= 0.000 + Data Path:+ 124.100 + Slack:= 60.631 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 21.800 | 114.600 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | mem/icache/g6623/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 109.100 | 1.700 | 116.300 | + | mem/icache/n_206 | | | F | (net) | 1 | | | | + | mem/icache/g6621/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 25.900 | 7.800 | 124.100 | + | mem/icache/n_214 | | | R | (net) | 1 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | ENA | R | ICGx1_ASAP7_75t_SRAM | 1 | 7.200 | 0.000 | 124.100 | + | ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 17.900 | -22.964 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 21.400 | 0.300 | -22.964 | + | CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 20: MET (60.789 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[27]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 83.200 (P) 0.000 (I) + Arrival:= -0.664 0.000 + + Hold:+ 8.175 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 107.511 + Launch Clock:= 0.000 + Data Path:+ 168.300 + Slack:= 60.789 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 43.800 | 144.200 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g425__8428/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 110.200 | 0.500 | 144.700 | + | cpu/s2_to_s3_alu/n_26 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2780_n_26/Y | | A->Y | F | HB4xp67_ASAP7_75t_SL | 1 | 10.900 | 23.600 | 168.300 | + | cpu/s2_to_s3_alu/FE_PHN2780_n_26 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[27]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.900 | 0.000 | 168.300 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 27.200 | -0.664 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[27]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.000 | 10.200 | -0.664 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 21: MET (61.871 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[12]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (F) cpu/stage1/pcreg/register_reg[12]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 96.600 (P) 0.000 (I) + Arrival:= 12.736 0.000 + + Hold:+ 7.793 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 120.529 + Launch Clock:= 0.000 + Data Path:+ 182.400 + Slack:= 61.871 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 51.600 | 144.400 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/pcreg/g363__4733/Y | | A->Y | F | NOR2xp33_ASAP7_75t_L | 1 | 137.500 | 20.500 | 164.900 | + | cpu/stage1/pcreg/n_17 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2858_n_17/Y | | A->Y | F | HB3xp67_ASAP7_75t_SL | 1 | 9.600 | 17.500 | 182.400 | + | cpu/stage1/pcreg/FE_PHN2858_n_17 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[12]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 8.300 | 0.000 | 182.400 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 24.700 | 12.736 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[12]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 38.900 | 8.800 | 12.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 22: MET (63.639 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[22]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 83.500 (P) 0.000 (I) + Arrival:= -0.364 0.000 + + Hold:+ 11.924 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 111.561 + Launch Clock:= 0.000 + Data Path:+ 175.200 + Slack:= 63.639 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 41.800 | 142.200 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g443__2883/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 108.800 | 0.500 | 142.700 | + | cpu/s2_to_s3_alu/n_8 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2758_n_8/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 11.300 | 32.500 | 175.200 | + | cpu/s2_to_s3_alu/FE_PHN2758_n_8 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[22]/D | | D | F | DFFHQNx1_ASAP7_75t_L | 1 | 10.400 | 0.000 | 175.200 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 27.500 | -0.364 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[22]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 46.000 | 10.500 | -0.364 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 23: MET (64.237 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[28]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 81.600 (P) 0.000 (I) + Arrival:= -2.264 0.000 + + Hold:+ 8.527 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 106.263 + Launch Clock:= 0.000 + Data Path:+ 170.500 + Slack:= 64.237 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 47.900 | 148.300 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g447__6417/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 112.200 | -1.600 | 146.700 | + | cpu/s2_to_s3_alu/n_4 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2784_n_4/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 9.400 | 11.900 | 158.600 | + | cpu/s2_to_s3_alu/FE_PHN2784_n_4 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC3581_n_4/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 5.900 | 11.900 | 170.500 | + | cpu/s2_to_s3_alu/FE_PHN3581_n_4 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[28]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.800 | 0.000 | 170.500 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 25.600 | -2.264 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[28]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 45.800 | 8.600 | -2.264 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 24: MET (65.151 ps) Hold Check with Pin cpu/stage3/csr/csr_reg[27]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage3/csr/csr_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 85.600 (P) 0.000 (I) + Arrival:= 1.736 0.000 + + Hold:+ 7.113 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 108.849 + Launch Clock:= 0.000 + Data Path:+ 174.000 + Slack:= 65.151 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------+-------+-------+------+-----------------------+--------+--------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 26.600 | 98.700 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/stage3/csr/g196/Y | | A->Y | R | INVx1_ASAP7_75t_L | 32 | 15.100 | 42.500 | 141.200 | + | cpu/stage3/csr/n_0 | | | R | (net) | 32 | | | | + | cpu/stage3/csr/g168/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 95.200 | 5.200 | 146.400 | + | cpu/stage3/csr/n_27 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2781_n_27/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 14.900 | 27.600 | 174.000 | + | cpu/stage3/csr/FE_PHN2781_n_27 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[27]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.600 | 0.000 | 174.000 | + +----------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 23.700 | 20.300 | 1.736 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[27]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 30.300 | 1.900 | 1.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 25: MET (65.589 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[26]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 83.500 (P) 0.000 (I) + Arrival:= -0.364 0.000 + + Hold:+ 8.175 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 107.811 + Launch Clock:= 0.000 + Data Path:+ 173.400 + Slack:= 65.589 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 45.700 | 146.100 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g446__7410/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 111.200 | 0.100 | 146.200 | + | cpu/s2_to_s3_alu/n_5 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2778_n_5/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.200 | 27.200 | 173.400 | + | cpu/s2_to_s3_alu/FE_PHN2778_n_5 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[26]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.900 | 0.000 | 173.400 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 27.500 | -0.364 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[26]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.000 | 10.500 | -0.364 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 26: MET (65.986 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[17]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[17]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 83.400 (P) 0.000 (I) + Arrival:= -0.464 0.000 + + Hold:+ 8.378 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 107.914 + Launch Clock:= 0.000 + Data Path:+ 173.900 + Slack:= 65.986 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 40.500 | 140.900 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g438__7482/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 108.100 | 0.500 | 141.400 | + | cpu/s2_to_s3_alu/n_13 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2755_n_13/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 11.000 | 32.500 | 173.900 | + | cpu/s2_to_s3_alu/FE_PHN2755_n_13 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[17]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 10.500 | 0.000 | 173.900 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 27.400 | -0.464 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[17]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.000 | 10.400 | -0.464 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 27: MET (66.194 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[7]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (F) cpu/stage1/pcreg/register_reg[7]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 98.200 (P) 0.000 (I) + Arrival:= 14.336 0.000 + + Hold:+ 7.170 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 121.506 + Launch Clock:= 0.000 + Data Path:+ 187.700 + Slack:= 66.194 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------------+-------+-------+------+---------------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 55.600 | 148.400 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/pcreg/g373__2398/Y | | A->Y | F | NOR2xp33_ASAP7_75t_L | 1 | 138.600 | 21.800 | 170.200 | + | cpu/stage1/pcreg/n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2857_n_7/Y | | A->Y | F | HB3xp67_ASAP7_75t_SL | 1 | 10.800 | 17.500 | 187.700 | + | cpu/stage1/pcreg/FE_PHN2857_n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[7]/D | | D | F | ASYNC_DFFHx1_ASAP7_75t_SL | 1 | 7.900 | 0.000 | 187.700 | + +-----------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+---------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 26.300 | 14.336 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[7]/CLK | | CLK | R | ASYNC_DFFHx1_ASAP7_75t_SL | 32 | 39.100 | 10.400 | 14.336 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ +Path 28: MET (66.447 ps) Hold Check with Pin cpu/stage3/csr/csr_reg[26]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage3/csr/csr_reg[26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 85.500 (P) 0.000 (I) + Arrival:= 1.636 0.000 + + Hold:+ 7.117 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 108.753 + Launch Clock:= 0.000 + Data Path:+ 175.200 + Slack:= 66.447 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |---------------------------------+-------+-------+------+-----------------------+--------+--------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 26.600 | 98.700 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/stage3/csr/g196/Y | | A->Y | R | INVx1_ASAP7_75t_L | 32 | 15.100 | 42.800 | 141.500 | + | cpu/stage3/csr/n_0 | | | R | (net) | 32 | | | | + | cpu/stage3/csr/g189/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 95.400 | 5.800 | 147.300 | + | cpu/stage3/csr/n_6 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2769_n_6/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 16.100 | 27.900 | 175.200 | + | cpu/stage3/csr/FE_PHN2769_n_6 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[26]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.600 | 0.000 | 175.200 | + +---------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 23.700 | 20.200 | 1.636 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[26]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 30.300 | 1.800 | 1.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 29: MET (66.686 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[18]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[18]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 83.500 (P) 0.000 (I) + Arrival:= -0.364 0.000 + + Hold:+ 8.378 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 108.014 + Launch Clock:= 0.000 + Data Path:+ 174.700 + Slack:= 66.686 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 41.600 | 142.000 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g439__4733/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 108.800 | 0.300 | 142.300 | + | cpu/s2_to_s3_alu/n_12 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2761_n_12/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 10.800 | 32.400 | 174.700 | + | cpu/s2_to_s3_alu/FE_PHN2761_n_12 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[18]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 10.400 | 0.000 | 174.700 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 27.500 | -0.364 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[18]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.000 | 10.500 | -0.364 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 30: MET (66.916 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[0]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[0]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 80.800 (P) 0.000 (I) + Arrival:= -3.064 0.000 + + Hold:+ 7.548 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.484 + Launch Clock:= 0.000 + Data Path:+ 171.400 + Slack:= 66.916 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 59.900 | 152.700 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/s1_to_s2_rs2/g449__2346/Y | | A->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 139.200 | 18.700 | 171.400 | + | cpu/s1_to_s2_rs2/n_2 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[0]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.400 | 0.000 | 171.400 | + +-------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.500 | -3.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[0]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.700 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 31: MET (67.605 ps) Clock Gating Hold Check with Pin cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 65.300 (P) 0.000 (I) + Arrival:= -18.564 0.000 + + Clock Gating Hold:+ -7.641 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 73.795 + Launch Clock:= 0.000 + Data Path:+ 141.400 + Slack:= 67.605 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-------+------+------------------------+--------+--------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | cpu/stage3/csr/g195/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 16.200 | 10.500 | 103.300 | + | cpu/stage3/csr/n_33 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC3551_n_33/Y | | A->Y | R | HB1xp67_ASAP7_75t_SRAM | 1 | 6.100 | 12.000 | 115.300 | + | cpu/stage3/csr/FE_PHN3551_n_33 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/FE_PHC268 | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.800 | 26.100 | 141.400 | + | 9_n_33/Y | | | | | | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/FE_PHN268 | | | R | (net) | 1 | | | | + | 9_n_33 | | | | | | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | ENA | R | ICGx3_ASAP7_75t_SL | 1 | 9.600 | 0.000 | 141.400 | + | NST/ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK | R | ICGx3_ASAP7_75t_SL | 3 | 23.700 | 4.700 | -18.564 | + | NST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 32: MET (67.667 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[20]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[20]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 83.500 (P) 0.000 (I) + Arrival:= -0.364 0.000 + + Hold:+ 8.297 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 107.933 + Launch Clock:= 0.000 + Data Path:+ 175.600 + Slack:= 67.667 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 41.700 | 142.100 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g441__9315/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 108.800 | 1.000 | 143.100 | + | cpu/s2_to_s3_alu/n_10 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2750_n_10/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 12.000 | 32.500 | 175.600 | + | cpu/s2_to_s3_alu/FE_PHN2750_n_10 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[20]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 10.200 | 0.000 | 175.600 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 27.500 | -0.364 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[20]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.000 | 10.500 | -0.364 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 33: MET (67.786 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[24]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[24]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 83.400 (P) 0.000 (I) + Arrival:= -0.464 0.000 + + Hold:+ 8.378 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 107.914 + Launch Clock:= 0.000 + Data Path:+ 175.700 + Slack:= 67.786 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 41.900 | 142.300 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g445__1666/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 109.000 | 0.800 | 143.100 | + | cpu/s2_to_s3_alu/n_6 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2770_n_6/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 11.700 | 32.600 | 175.700 | + | cpu/s2_to_s3_alu/FE_PHN2770_n_6 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[24]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 10.400 | 0.000 | 175.700 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 27.400 | -0.464 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[24]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.000 | 10.400 | -0.464 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 34: MET (68.155 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[1]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 80.900 (P) 0.000 (I) + Arrival:= -2.964 0.000 + + Hold:+ 9.408 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 106.445 + Launch Clock:= 0.000 + Data Path:+ 174.600 + Slack:= 68.155 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------------+-------+-------+------+----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.500 | 100.600 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 15.700 | 56.500 | 157.100 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/s2_to_s3_alu/g448__5477/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 1 | 129.700 | 17.500 | 174.600 | + | cpu/s2_to_s3_alu/n_3 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[1]/D | | D | F | DFFHQx4_ASAP7_75t_SL | 1 | 4.800 | 0.000 | 174.600 | + +------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 24.900 | -2.964 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[1]/CLK | | CLK | R | DFFHQx4_ASAP7_75t_SL | 32 | 42.700 | 7.900 | -2.964 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 35: MET (68.271 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[6]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (R) cpu/stage1/pcreg/register_reg[6]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 97.900 (P) 0.000 (I) + Arrival:= 14.036 0.000 + + Hold:+ 3.893 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 117.929 + Launch Clock:= 0.000 + Data Path:+ 186.200 + Slack:= 68.271 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------------+-------+-------+------+---------------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.500 | 100.600 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 15.700 | 52.700 | 153.300 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/pcreg/g372__5477/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 129.400 | 11.800 | 165.100 | + | cpu/stage1/pcreg/n_8 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2855_n_8/Y | | A->Y | R | HB4xp67_ASAP7_75t_SL | 1 | 12.700 | 21.100 | 186.200 | + | cpu/stage1/pcreg/FE_PHN2855_n_8 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[6]/D | | D | R | ASYNC_DFFHx1_ASAP7_75t_SL | 1 | 9.500 | 0.000 | 186.200 | + +-----------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+---------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 26.000 | 14.036 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[6]/CLK | | CLK | R | ASYNC_DFFHx1_ASAP7_75t_SL | 32 | 39.100 | 10.100 | 14.036 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ +Path 36: MET (68.862 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[8]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (F) cpu/stage1/pcreg/register_reg[8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 97.200 (P) 0.000 (I) + Arrival:= 13.336 0.000 + + Hold:+ 7.601 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 120.938 + Launch Clock:= 0.000 + Data Path:+ 189.800 + Slack:= 68.862 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 53.300 | 146.100 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/pcreg/g374__5107/Y | | A->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 138.100 | 20.200 | 166.300 | + | cpu/stage1/pcreg/n_6 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2856_n_6/Y | | A->Y | F | HB4xp67_ASAP7_75t_SL | 1 | 11.000 | 23.500 | 189.800 | + | cpu/stage1/pcreg/FE_PHN2856_n_6 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[8]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.700 | 0.000 | 189.800 | + +-------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 25.300 | 13.336 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[8]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 39.100 | 9.400 | 13.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 37: MET (69.491 ps) Hold Check with Pin cpu/stage3/csr/csr_reg[23]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage3/csr/csr_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 85.200 (P) 0.000 (I) + Arrival:= 1.336 0.000 + + Hold:+ 7.973 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.309 + Launch Clock:= 0.000 + Data Path:+ 178.800 + Slack:= 69.491 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------+-------+-------+------+-----------------------+--------+--------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 26.600 | 98.700 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/stage3/csr/g196/Y | | A->Y | R | INVx1_ASAP7_75t_L | 32 | 15.100 | 44.300 | 143.000 | + | cpu/stage3/csr/n_0 | | | R | (net) | 32 | | | | + | cpu/stage3/csr/g176/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 95.400 | 0.800 | 143.800 | + | cpu/stage3/csr/n_19 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2764_n_19/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 11.100 | 35.000 | 178.800 | + | cpu/stage3/csr/FE_PHN2764_n_19 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[23]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 13.300 | 0.200 | 178.800 | + +----------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 23.700 | 19.900 | 1.336 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[23]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 30.300 | 1.500 | 1.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 38: MET (69.513 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[13]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/pcreg/register_reg[13]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 94.600 (P) 0.000 (I) + Arrival:= 10.736 0.000 + + Hold:+ 7.950 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 118.687 + Launch Clock:= 0.000 + Data Path:+ 188.200 + Slack:= 69.513 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.500 | 100.600 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 15.700 | 50.200 | 150.800 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/pcreg/FE_DBTC78_reset/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 22 | 128.500 | 35.800 | 186.600 | + | cpu/stage1/pcreg/FE_DBTN78_reset | | | R | (net) | 22 | | | | + | cpu/stage1/pcreg/g354__2802/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 79.300 | 1.600 | 188.200 | + | cpu/stage1/pcreg/n_26 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[13]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.600 | 0.000 | 188.200 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 22.700 | 10.736 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[13]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 38.100 | 6.800 | 10.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 39: MET (70.019 ps) Hold Check with Pin cpu/stage3/csr/csr_reg[21]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage3/csr/csr_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 84.600 (P) 0.000 (I) + Arrival:= 0.736 0.000 + + Hold:+ 7.744 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 108.481 + Launch Clock:= 0.000 + Data Path:+ 178.500 + Slack:= 70.019 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------+-------+-------+------+-----------------------+--------+--------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 26.600 | 98.700 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/stage3/csr/g196/Y | | A->Y | R | INVx1_ASAP7_75t_L | 32 | 15.100 | 44.900 | 143.600 | + | cpu/stage3/csr/n_0 | | | R | (net) | 32 | | | | + | cpu/stage3/csr/g175/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 95.500 | 0.700 | 144.300 | + | cpu/stage3/csr/n_20 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2760_n_20/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 11.600 | 34.200 | 178.500 | + | cpu/stage3/csr/FE_PHN2760_n_20 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[21]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 12.300 | 0.100 | 178.500 | + +----------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 23.700 | 19.300 | 0.736 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[21]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 30.200 | 0.900 | 0.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 40: MET (70.078 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[4]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[4]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 79.300 (P) 0.000 (I) + Arrival:= -4.564 0.000 + + Hold:+ 8.786 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.222 + Launch Clock:= 0.000 + Data Path:+ 174.300 + Slack:= 70.078 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 59.300 | 152.100 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/s1_to_s2_rs2/g435__2802/Y | | A->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 139.100 | 22.200 | 174.300 | + | cpu/s1_to_s2_rs2/n_16 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[4]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 13.100 | 0.100 | 174.300 | + +-------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 23.000 | -4.564 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[4]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.200 | 4.200 | -4.564 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 41: MET (70.678 ps) Hold Check with Pin cpu/stage3/csr/csr_reg[7]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage3/csr/csr_reg[7]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 87.000 (P) 0.000 (I) + Arrival:= 3.136 0.000 + + Hold:+ 8.286 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 111.422 + Launch Clock:= 0.000 + Data Path:+ 182.100 + Slack:= 70.678 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------+-------+-------+------+-----------------------+--------+--------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 26.600 | 98.700 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/stage3/csr/g196/Y | | A->Y | R | INVx1_ASAP7_75t_L | 32 | 15.100 | 45.900 | 144.600 | + | cpu/stage3/csr/n_0 | | | R | (net) | 32 | | | | + | cpu/stage3/csr/g172/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 95.500 | 1.100 | 145.700 | + | cpu/stage3/csr/n_23 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2746_n_23/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 14.000 | 36.400 | 182.100 | + | cpu/stage3/csr/FE_PHN2746_n_23 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[7]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 14.300 | 0.300 | 182.100 | + +----------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 23.700 | 21.700 | 3.136 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[7]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 30.800 | 3.300 | 3.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 42: MET (70.907 ps) Hold Check with Pin cpu/stage3/csr/csr_reg[15]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage3/csr/csr_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 86.600 (P) 0.000 (I) + Arrival:= 2.736 0.000 + + Hold:+ 8.357 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 111.093 + Launch Clock:= 0.000 + Data Path:+ 182.000 + Slack:= 70.907 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------+-------+-------+------+-----------------------+--------+--------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 26.600 | 98.700 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/stage3/csr/g196/Y | | A->Y | R | INVx1_ASAP7_75t_L | 32 | 15.100 | 45.800 | 144.500 | + | cpu/stage3/csr/n_0 | | | R | (net) | 32 | | | | + | cpu/stage3/csr/g180/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 95.500 | 0.700 | 145.200 | + | cpu/stage3/csr/FE_PHN2799_n_15 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2799_n_15/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 15.100 | 36.800 | 182.000 | + | cpu/stage3/csr/n_15 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[15]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 14.600 | 0.300 | 182.000 | + +----------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 23.700 | 21.300 | 2.736 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[15]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 30.700 | 2.900 | 2.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 43: MET (71.082 ps) Hold Check with Pin cpu/stage3/csr/csr_reg[24]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage3/csr/csr_reg[24]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 85.200 (P) 0.000 (I) + Arrival:= 1.336 0.000 + + Hold:+ 8.982 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 110.318 + Launch Clock:= 0.000 + Data Path:+ 181.400 + Slack:= 71.082 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |---------------------------------+-------+-------+------+-----------------------+--------+--------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 26.600 | 98.700 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/stage3/csr/g196/Y | | A->Y | R | INVx1_ASAP7_75t_L | 32 | 15.100 | 44.200 | 142.900 | + | cpu/stage3/csr/n_0 | | | R | (net) | 32 | | | | + | cpu/stage3/csr/g186/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 95.700 | 0.700 | 143.600 | + | cpu/stage3/csr/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2768_n_9/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 10.800 | 37.800 | 181.400 | + | cpu/stage3/csr/FE_PHN2768_n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[24]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 17.000 | 0.600 | 181.400 | + +---------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 23.700 | 19.900 | 1.336 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[24]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 30.300 | 1.500 | 1.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 44: MET (71.686 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[14]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage1/pcreg/register_reg[14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 93.300 (P) 0.000 (I) + Arrival:= 9.436 0.000 + + Hold:+ 7.878 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 117.314 + Launch Clock:= 0.000 + Data Path:+ 189.000 + Slack:= 71.686 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.500 | 100.600 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 48 | 15.700 | 50.200 | 150.800 | + | FE_OFN0_reset | | | F | (net) | 48 | | | | + | cpu/stage1/pcreg/FE_DBTC78_reset/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 22 | 128.500 | 36.800 | 187.600 | + | cpu/stage1/pcreg/FE_DBTN78_reset | | | R | (net) | 22 | | | | + | cpu/stage1/pcreg/g357__8246/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 80.200 | 1.400 | 189.000 | + | cpu/stage1/pcreg/n_23 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[14]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.000 | 189.000 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 21.400 | 9.436 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[14]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.300 | 5.500 | 9.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 45: MET (71.851 ps) Hold Check with Pin cpu/stage3/csr/csr_reg[6]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage3/csr/csr_reg[6]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 86.600 (P) 0.000 (I) + Arrival:= 2.736 0.000 + + Hold:+ 8.413 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 111.149 + Launch Clock:= 0.000 + Data Path:+ 183.000 + Slack:= 71.851 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------+-------+-------+------+-----------------------+--------+--------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 26.600 | 98.700 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/stage3/csr/g196/Y | | A->Y | R | INVx1_ASAP7_75t_L | 32 | 15.100 | 45.700 | 144.400 | + | cpu/stage3/csr/n_0 | | | R | (net) | 32 | | | | + | cpu/stage3/csr/g171/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 95.500 | 1.300 | 145.700 | + | cpu/stage3/csr/n_24 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2747_n_24/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 16.200 | 37.300 | 183.000 | + | cpu/stage3/csr/FE_PHN2747_n_24 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[6]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 14.700 | 0.400 | 183.000 | + +----------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 23.700 | 21.300 | 2.736 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[6]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 30.700 | 2.900 | 2.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 46: MET (71.958 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[1]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 80.500 (P) 0.000 (I) + Arrival:= -3.364 0.000 + + Hold:+ 8.006 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.642 + Launch Clock:= 0.000 + Data Path:+ 176.600 + Slack:= 71.958 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 59.500 | 152.300 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/s1_to_s2_rs2/g448__2883/Y | | A->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 139.200 | 16.300 | 168.600 | + | cpu/s1_to_s2_rs2/n_3 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3582_n_3/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 7.100 | 8.000 | 176.600 | + | cpu/s1_to_s2_rs2/FE_PHN3582_n_3 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[1]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 5.600 | 0.000 | 176.600 | + +-------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.200 | -3.364 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[1]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.400 | 5.400 | -3.364 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 47: MET (72.317 ps) Hold Check with Pin cpu/stage3/csr/csr_reg[22]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/stage3/csr/csr_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 84.800 (P) 0.000 (I) + Arrival:= 0.936 0.000 + + Hold:+ 8.746 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.683 + Launch Clock:= 0.000 + Data Path:+ 182.000 + Slack:= 72.317 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------+-------+-------+------+-----------------------+--------+--------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 26.600 | 98.700 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/stage3/csr/g196/Y | | A->Y | R | INVx1_ASAP7_75t_L | 32 | 15.100 | 45.200 | 143.900 | + | cpu/stage3/csr/n_0 | | | R | (net) | 32 | | | | + | cpu/stage3/csr/g185/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 95.800 | 0.800 | 144.700 | + | cpu/stage3/csr/n_10 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2767_n_10/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 10.800 | 37.300 | 182.000 | + | cpu/stage3/csr/FE_PHN2767_n_10 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[22]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 16.300 | 0.500 | 182.000 | + +----------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 23.700 | 19.500 | 0.936 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[22]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 30.200 | 1.100 | 0.936 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 48: MET (72.330 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[4]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (F) cpu/stage1/pcreg/register_reg[4]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 98.400 (P) 0.000 (I) + Arrival:= 14.536 0.000 + + Hold:+ 11.834 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 126.370 + Launch Clock:= 0.000 + Data Path:+ 198.700 + Slack:= 72.330 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | R | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | R | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 26.900 | 27.000 | + | FE_PHN3891_reset | | | R | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | R | HB4xp67_ASAP7_75t_L | 1 | 12.000 | 36.900 | 63.900 | + | FE_PHN3428_reset | | | R | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | R | BUFx4_ASAP7_75t_SRAM | 6 | 33.100 | 28.900 | 92.800 | + | FE_PHN2673_reset | | | R | (net) | 6 | | | | + | FE_OFC0_reset/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 48 | 16.200 | 55.600 | 148.400 | + | FE_OFN0_reset | | | R | (net) | 48 | | | | + | cpu/stage1/pcreg/g370__7410/Y | | A->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 138.600 | 18.500 | 166.900 | + | cpu/stage1/pcreg/n_10 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2853_n_10/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 9.200 | 31.800 | 198.700 | + | cpu/stage1/pcreg/FE_PHN2853_n_10 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[4]/D | | D | F | DFFHQNx1_ASAP7_75t_L | 1 | 10.100 | 0.000 | 198.700 | + +-------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 26.500 | 14.536 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[4]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 39.100 | 10.600 | 14.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 49: MET (72.386 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[21]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 83.500 (P) 0.000 (I) + Arrival:= -0.364 0.000 + + Hold:+ 8.378 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 108.014 + Launch Clock:= 0.000 + Data Path:+ 180.400 + Slack:= 72.386 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 46.800 | 147.200 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g442__9945/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 111.700 | 0.500 | 147.700 | + | cpu/s2_to_s3_alu/n_9 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2754_n_9/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 12.400 | 32.700 | 180.400 | + | cpu/s2_to_s3_alu/FE_PHN2754_n_9 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[21]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 10.400 | 0.000 | 180.400 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 27.500 | -0.364 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[21]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.000 | 10.500 | -0.364 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 50: MET (72.528 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[25]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: default + Startpoint: (F) reset + Clock: + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[25]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 0.000 + Net Latency:+ 82.500 (P) 0.000 (I) + Arrival:= -1.364 0.000 + + Hold:+ 12.036 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 110.672 + Launch Clock:= 0.000 + Data Path:+ 183.200 + Slack:= 72.528 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |-------------------------------------+-------+-------+------+-----------------------+--------+---------+--------+---------| + | reset | | reset | F | (arrival) | 1 | 4.000 | 0.100 | 0.100 | + | reset | | | F | (net) | 1 | | | | + | FE_PHC3891_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 4.000 | 32.200 | 32.300 | + | FE_PHN3891_reset | | | F | (net) | 1 | | | | + | FE_PHC3428_reset/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 11.600 | 39.800 | 72.100 | + | FE_PHN3428_reset | | | F | (net) | 1 | | | | + | FE_PHC2673_reset/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 6 | 29.300 | 28.300 | 100.400 | + | FE_PHN2673_reset | | | F | (net) | 6 | | | | + | cpu/s2_to_s3_alu/FE_DBTC8_reset/Y | | A->Y | R | INVx1_ASAP7_75t_L | 30 | 15.700 | 44.500 | 144.900 | + | cpu/s2_to_s3_alu/FE_DBTN8_reset | | | R | (net) | 30 | | | | + | cpu/s2_to_s3_alu/g430__2802/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 110.600 | 2.600 | 147.500 | + | cpu/s2_to_s3_alu/n_21 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC3580_n_21/Y | | A->Y | F | BUFx6f_ASAP7_75t_L | 1 | 14.000 | 9.300 | 156.800 | + | cpu/s2_to_s3_alu/FE_PHN3580_n_21 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2777_n_21/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 4.000 | 26.400 | 183.200 | + | cpu/s2_to_s3_alu/FE_PHN2777_n_21 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[25]/D | | D | F | DFFHQNx1_ASAP7_75t_L | 1 | 10.000 | 0.000 | 183.200 | + +--------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 26.500 | -1.364 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[25]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 46.000 | 9.500 | -1.364 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + diff --git a/build/par-rundir/timingReports/riscv_top_postRoute_hold.summary b/build/par-rundir/timingReports/riscv_top_postRoute_hold.summary new file mode 100644 index 0000000..c5a3c89 --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute_hold.summary @@ -0,0 +1,36 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:08 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### + +------------------------------------------------------------ + opt_design Final SI Timing Summary +------------------------------------------------------------ + ++--------------------+---------+---------+---------+---------+ +| Hold mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| -0.000 | -0.000 | 0.013 | 0.012 | +| TNS (ns):| -0.000 | -0.000 | 0.000 | 0.000 | +| Violating Paths:| 2 | 2 | 0 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 0 (0) | 0.000 | 0 (0) | +| max_tran | 0 (0) | 0.000 | 0 (0) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 23.427% + (99.999% with Fillers) +Total number of glitch violations: 0 +------------------------------------------------------------ diff --git a/build/par-rundir/timingReports/riscv_top_postRoute_reg2cgate.tarpt b/build/par-rundir/timingReports/riscv_top_postRoute_reg2cgate.tarpt new file mode 100644 index 0000000..8e00114 --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute_reg2cgate.tarpt @@ -0,0 +1,3230 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:15 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### +Path 1: MET (3.967 ps) Clock Gating Setup Check with Pin mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 106.800 (P) 160.200 (P) + Arrival:= 867.800 21.200 + + Clock Gating Setup:- 65.333 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 702.467 + Launch Clock:= 21.200 + Data Path:+ 677.300 + Slack:= 3.967 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.300 | 179.500 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2349/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.500 | 192.000 | + | cpu/stage3/ldselmux/n_97 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2313/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 23.800 | 17.900 | 209.900 | + | cpu/stage3/wb_dmem[5] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1109/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 51.100 | 17.800 | 227.700 | + | cpu/wb_data[5] | | | R | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g550/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 5 | 19.800 | 23.100 | 250.800 | + | cpu/stage2/stage2_rs1_data[5] | | | R | (net) | 5 | | | | + | cpu/stage2/aselmux/g549/Y | | A1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 30.400 | 17.400 | 268.200 | + | cpu/stage2/stage2_alu_in1[5] | | | R | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC821_stage2_alu_in1_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 14.800 | 9.100 | 277.300 | + | cpu/stage2/alu/FE_DBTN72_stage2_alu_in1_5 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC823_stage2_alu_in1_5/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 9 | 13.500 | 34.700 | 312.000 | + | cpu/stage2/alu/FE_OFN957_stage2_alu_in1_5 | | | R | (net) | 9 | | | | + | cpu/stage2/alu/FE_OFC825_stage2_alu_in1_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 5 | 71.900 | 19.400 | 331.400 | + | cpu/stage2/alu/FE_OFN959_stage2_alu_in1_5 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/lt_30_22_g1493/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 4 | 35.800 | 20.700 | 352.100 | + | cpu/stage2/alu/lt_30_22_n_37 | | | F | (net) | 4 | | | | + | cpu/stage2/alu/lt_29_31_g1466/Y | | A1->Y | R | OAI32xp33_ASAP7_75t_SL | 1 | 12.400 | 14.200 | 366.300 | + | cpu/stage2/alu/lt_29_31_n_63 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1465/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 55.100 | 6.700 | 373.000 | + | cpu/stage2/alu/lt_29_31_n_64 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1451/Y | | C1->Y | R | OAI322xp33_ASAP7_75t_SL | 1 | 18.400 | 16.000 | 389.000 | + | cpu/stage2/alu/lt_29_31_n_78 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1444/Y | | B->Y | F | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 46.900 | 17.300 | 406.300 | + | cpu/stage2/alu/lt_29_31_n_85 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1443/Y | | A1->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 35.500 | 32.200 | 438.500 | + | cpu/stage2/alu/lt_29_31_n_86 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1442/Y | | A1->Y | F | AOI321xp33_ASAP7_75t_SL | 1 | 67.200 | 36.700 | 475.200 | + | cpu/stage2/alu/n_324 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5667/Y | | B1->Y | R | AOI33xp33_ASAP7_75t_SL | 1 | 68.000 | 30.300 | 505.500 | + | cpu/stage2/alu/n_54 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5520/Y | | A2->Y | F | OAI211xp5_ASAP7_75t_SL | 1 | 53.400 | 19.300 | 524.800 | + | cpu/stage2/alu/n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5502/Y | | C->Y | F | AO221x2_ASAP7_75t_SL | 9 | 43.500 | 52.300 | 577.100 | + | cpu/stage2_alu_out[0] | | | F | (net) | 9 | | | | + | cpu/stage3/memrw/g432/Y | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 56.900 | 16.900 | 594.000 | + | cpu/stage3/memrw/n_6 | | | R | (net) | 2 | | | | + | cpu/stage3/memrw/g425/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 3 | 31.900 | 19.900 | 613.900 | + | dcache_we[1] | | | F | (net) | 3 | | | | + | mem/dcache/g13997/Y | | B->Y | R | NOR4xp25_ASAP7_75t_SL | 1 | 42.400 | 28.500 | 642.400 | + | mem/dcache/n_119 | | | R | (net) | 1 | | | | + | mem/dcache/FE_OFC480_n_119/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 54.100 | 21.200 | 663.600 | + | mem/dcache/n_321 | | | F | (net) | 3 | | | | + | mem/dcache/FE_OFC481_n_119/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 37.600 | 9.300 | 672.900 | + | mem/dcache/FE_OFN727_n_119 | | | R | (net) | 1 | | | | + | mem/dcache/g13731/Y | | A1->Y | F | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 15.500 | 12.000 | 684.900 | + | mem/dcache/n_195 | | | F | (net) | 1 | | | | + | mem/dcache/g13600/Y | | A1->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 30.900 | 13.600 | 698.500 | + | mem/dcache/n_323 | | | R | (net) | 1 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | ENA | R | ICGx1_ASAP7_75t_SRAM | 1 | 27.100 | 0.100 | 698.500 | + | ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 42.100 | 867.800 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 39.600 | 2.600 | 867.800 | + | CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 2: MET (241.350 ps) Clock Gating Setup Check with Pin mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 104.400 (P) 151.100 (P) + Arrival:= 865.400 12.100 + + Clock Gating Setup:- 40.349 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 725.051 + Launch Clock:= 12.100 + Data Path:+ 471.600 + Slack:= 241.350 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 26.700 | -100.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 17.700 | 27.500 | -72.500 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 29.700 | 46.800 | -25.700 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 47.900 | 37.800 | 12.100 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[2]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 1 | 27.000 | 33.800 | 45.900 | + | mem/dcache/STATE[2] | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC3288_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 15.800 | 69.700 | 115.600 | + | mem/dcache/FE_PHN3288_STATE_2 | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC2590_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 3 | 25.500 | 80.600 | 196.200 | + | mem/dcache/FE_PHN2590_STATE_2 | | | F | (net) | 3 | | | | + | mem/dcache/g11633/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 36.500 | 11.700 | 207.900 | + | mem/dcache/n_204 | | | R | (net) | 2 | | | | + | mem/dcache/g11616/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 6 | 18.500 | 19.800 | 227.700 | + | mem/dcache/n_325 | | | F | (net) | 6 | | | | + | mem/dcache/g14031/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 40.100 | 21.600 | 249.300 | + | mem/dcache/n_92 | | | R | (net) | 3 | | | | + | mem/dcache/g14018/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 33.100 | 29.600 | 278.900 | + | mem/d_stall_n | | | F | (net) | 1 | | | | + | mem/g20/Y | | A->Y | R | NAND2x1_ASAP7_75t_SL | 41 | 55.700 | 103.900 | 382.800 | + | stall | | | R | (net) | 41 | | | | + | mem/g22/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 263.000 | 8.800 | 391.600 | + | mem/n_1 | | | F | (net) | 2 | | | | + | mem/icache/g6622/Y | | A2->Y | R | OAI21xp5_ASAP7_75t_SL | 1 | 67.900 | 19.800 | 411.400 | + | mem/icache/n_216 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC2687_n_216/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 34.000 | 64.000 | 475.400 | + | mem/icache/FE_PHN2687_n_216 | | | R | (net) | 2 | | | | + | mem/icache/g6621/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 33.300 | 8.300 | 483.700 | + | mem/icache/n_214 | | | F | (net) | 1 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | ENA | F | ICGx1_ASAP7_75t_SRAM | 1 | 17.200 | 0.100 | 483.700 | + | ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 39.700 | 865.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 38.900 | 0.200 | 865.400 | + | CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 3: MET (282.556 ps) Clock Gating Setup Check with Pin cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 86.200 (P) 151.100 (P) + Arrival:= 847.200 12.100 + + Clock Gating Setup:- 34.644 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 712.556 + Launch Clock:= 12.100 + Data Path:+ 417.900 + Slack:= 282.556 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 26.700 | -100.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 17.700 | 27.500 | -72.500 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 29.700 | 46.800 | -25.700 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 47.900 | 37.800 | 12.100 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[2]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 1 | 27.000 | 33.800 | 45.900 | + | mem/dcache/STATE[2] | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC3288_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 15.800 | 69.700 | 115.600 | + | mem/dcache/FE_PHN3288_STATE_2 | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC2590_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 3 | 25.500 | 80.600 | 196.200 | + | mem/dcache/FE_PHN2590_STATE_2 | | | F | (net) | 3 | | | | + | mem/dcache/g11633/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 36.500 | 11.700 | 207.900 | + | mem/dcache/n_204 | | | R | (net) | 2 | | | | + | mem/dcache/g11616/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 6 | 18.500 | 19.800 | 227.700 | + | mem/dcache/n_325 | | | F | (net) | 6 | | | | + | mem/dcache/g14031/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 40.100 | 21.600 | 249.300 | + | mem/dcache/n_92 | | | R | (net) | 3 | | | | + | mem/dcache/g14018/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 33.100 | 29.600 | 278.900 | + | mem/d_stall_n | | | F | (net) | 1 | | | | + | mem/g20/Y | | A->Y | R | NAND2x1_ASAP7_75t_SL | 41 | 55.700 | 136.000 | 414.900 | + | stall | | | R | (net) | 41 | | | | + | cpu/s1_to_s2_pc/g213__1705/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 275.200 | 15.100 | 430.000 | + | cpu/s1_to_s2_pc/n_34 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | ENA | F | ICGx3_ASAP7_75t_SL | 1 | 83.000 | 0.400 | 430.000 | + | NST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 46.200 | 847.200 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK | R | ICGx3_ASAP7_75t_SL | 6 | 38.800 | 2.400 | 847.200 | + | NST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 4: MET (283.791 ps) Clock Gating Setup Check with Pin cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 92.500 (P) 151.100 (P) + Arrival:= 853.500 12.100 + + Clock Gating Setup:- 37.209 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 716.291 + Launch Clock:= 12.100 + Data Path:+ 420.400 + Slack:= 283.791 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 26.700 | -100.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 17.700 | 27.500 | -72.500 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 29.700 | 46.800 | -25.700 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 47.900 | 37.800 | 12.100 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[2]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 1 | 27.000 | 33.800 | 45.900 | + | mem/dcache/STATE[2] | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC3288_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 15.800 | 69.700 | 115.600 | + | mem/dcache/FE_PHN3288_STATE_2 | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC2590_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 3 | 25.500 | 80.600 | 196.200 | + | mem/dcache/FE_PHN2590_STATE_2 | | | F | (net) | 3 | | | | + | mem/dcache/g11633/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 36.500 | 11.700 | 207.900 | + | mem/dcache/n_204 | | | R | (net) | 2 | | | | + | mem/dcache/g11616/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 6 | 18.500 | 19.800 | 227.700 | + | mem/dcache/n_325 | | | F | (net) | 6 | | | | + | mem/dcache/g14031/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 40.100 | 21.600 | 249.300 | + | mem/dcache/n_92 | | | R | (net) | 3 | | | | + | mem/dcache/g14018/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 33.100 | 29.600 | 278.900 | + | mem/d_stall_n | | | F | (net) | 1 | | | | + | mem/g20/Y | | A->Y | R | NAND2x1_ASAP7_75t_SL | 41 | 55.700 | 140.200 | 419.100 | + | stall | | | R | (net) | 41 | | | | + | cpu/s2_to_s3_inst/g128__6260/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 275.200 | 13.400 | 432.500 | + | cpu/s2_to_s3_inst/n_19 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 81.200 | 0.400 | 432.500 | + | _INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 50.000 | 853.500 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK | R | ICGx1_ASAP7_75t_SL | 4 | 53.900 | 5.600 | 853.500 | + | _INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 5: MET (286.507 ps) Clock Gating Setup Check with Pin cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 86.400 (P) 151.100 (P) + Arrival:= 847.400 12.100 + + Clock Gating Setup:- 34.193 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 713.208 + Launch Clock:= 12.100 + Data Path:+ 414.600 + Slack:= 286.507 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 26.700 | -100.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 17.700 | 27.500 | -72.500 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 29.700 | 46.800 | -25.700 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 47.900 | 37.800 | 12.100 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[2]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 1 | 27.000 | 33.800 | 45.900 | + | mem/dcache/STATE[2] | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC3288_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 15.800 | 69.700 | 115.600 | + | mem/dcache/FE_PHN3288_STATE_2 | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC2590_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 3 | 25.500 | 80.600 | 196.200 | + | mem/dcache/FE_PHN2590_STATE_2 | | | F | (net) | 3 | | | | + | mem/dcache/g11633/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 36.500 | 11.700 | 207.900 | + | mem/dcache/n_204 | | | R | (net) | 2 | | | | + | mem/dcache/g11616/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 6 | 18.500 | 19.800 | 227.700 | + | mem/dcache/n_325 | | | F | (net) | 6 | | | | + | mem/dcache/g14031/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 40.100 | 21.600 | 249.300 | + | mem/dcache/n_92 | | | R | (net) | 3 | | | | + | mem/dcache/g14018/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 33.100 | 29.600 | 278.900 | + | mem/d_stall_n | | | F | (net) | 1 | | | | + | mem/g20/Y | | A->Y | R | NAND2x1_ASAP7_75t_SL | 41 | 55.700 | 135.900 | 414.800 | + | stall | | | R | (net) | 41 | | | | + | cpu/s1_to_s2_rs1/g213__1881/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 275.200 | 11.900 | 426.700 | + | cpu/s1_to_s2_rs1/n_34 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_ | | ENA | F | ICGx3_ASAP7_75t_SL | 1 | 80.100 | 0.200 | 426.700 | + | INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 46.400 | 847.400 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_ | | CLK | R | ICGx3_ASAP7_75t_SL | 6 | 38.800 | 2.600 | 847.400 | + | INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 6: MET (286.607 ps) Clock Gating Setup Check with Pin cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 86.700 (P) 151.100 (P) + Arrival:= 847.700 12.100 + + Clock Gating Setup:- 34.193 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 713.508 + Launch Clock:= 12.100 + Data Path:+ 414.800 + Slack:= 286.607 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 26.700 | -100.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 17.700 | 27.500 | -72.500 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 29.700 | 46.800 | -25.700 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 47.900 | 37.800 | 12.100 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[2]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 1 | 27.000 | 33.800 | 45.900 | + | mem/dcache/STATE[2] | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC3288_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 15.800 | 69.700 | 115.600 | + | mem/dcache/FE_PHN3288_STATE_2 | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC2590_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 3 | 25.500 | 80.600 | 196.200 | + | mem/dcache/FE_PHN2590_STATE_2 | | | F | (net) | 3 | | | | + | mem/dcache/g11633/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 36.500 | 11.700 | 207.900 | + | mem/dcache/n_204 | | | R | (net) | 2 | | | | + | mem/dcache/g11616/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 6 | 18.500 | 19.800 | 227.700 | + | mem/dcache/n_325 | | | F | (net) | 6 | | | | + | mem/dcache/g14031/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 40.100 | 21.600 | 249.300 | + | mem/dcache/n_92 | | | R | (net) | 3 | | | | + | mem/dcache/g14018/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 33.100 | 29.600 | 278.900 | + | mem/d_stall_n | | | F | (net) | 1 | | | | + | mem/g20/Y | | A->Y | R | NAND2x1_ASAP7_75t_SL | 41 | 55.700 | 136.000 | 414.900 | + | stall | | | R | (net) | 41 | | | | + | cpu/s2_to_s3_pc/g213__4733/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 275.200 | 12.000 | 426.900 | + | cpu/s2_to_s3_pc/n_34 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | ENA | F | ICGx3_ASAP7_75t_SL | 1 | 80.100 | 0.200 | 426.900 | + | NST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 46.700 | 847.700 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK | R | ICGx3_ASAP7_75t_SL | 6 | 38.700 | 2.900 | 847.700 | + | NST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 7: MET (286.837 ps) Clock Gating Setup Check with Pin cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 84.600 (P) 151.100 (P) + Arrival:= 845.600 12.100 + + Clock Gating Setup:- 36.663 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 708.937 + Launch Clock:= 12.100 + Data Path:+ 410.000 + Slack:= 286.837 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 26.700 | -100.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 17.700 | 27.500 | -72.500 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 29.700 | 46.800 | -25.700 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 47.900 | 37.800 | 12.100 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[2]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 1 | 27.000 | 33.800 | 45.900 | + | mem/dcache/STATE[2] | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC3288_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 15.800 | 69.700 | 115.600 | + | mem/dcache/FE_PHN3288_STATE_2 | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC2590_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 3 | 25.500 | 80.600 | 196.200 | + | mem/dcache/FE_PHN2590_STATE_2 | | | F | (net) | 3 | | | | + | mem/dcache/g11633/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 36.500 | 11.700 | 207.900 | + | mem/dcache/n_204 | | | R | (net) | 2 | | | | + | mem/dcache/g11616/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 6 | 18.500 | 19.800 | 227.700 | + | mem/dcache/n_325 | | | F | (net) | 6 | | | | + | mem/dcache/g14031/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 40.100 | 21.600 | 249.300 | + | mem/dcache/n_92 | | | R | (net) | 3 | | | | + | mem/dcache/g14018/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 33.100 | 29.600 | 278.900 | + | mem/d_stall_n | | | F | (net) | 1 | | | | + | mem/g20/Y | | A->Y | R | NAND2x1_ASAP7_75t_SL | 41 | 55.700 | 127.400 | 406.300 | + | stall | | | R | (net) | 41 | | | | + | cpu/stage1/pcreg/g189__5107/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 274.300 | 15.800 | 422.100 | + | cpu/stage1/pcreg/n_35 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 83.500 | 0.300 | 422.100 | + | INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 38.400 | 0.800 | 845.600 | + | INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 8: MET (290.483 ps) Clock Gating Setup Check with Pin cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 86.800 (P) 151.100 (P) + Arrival:= 847.800 12.100 + + Clock Gating Setup:- 33.716 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 714.084 + Launch Clock:= 12.100 + Data Path:+ 411.500 + Slack:= 290.483 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 26.700 | -100.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 17.700 | 27.500 | -72.500 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 29.700 | 46.800 | -25.700 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 47.900 | 37.800 | 12.100 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[2]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 1 | 27.000 | 33.800 | 45.900 | + | mem/dcache/STATE[2] | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC3288_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 15.800 | 69.700 | 115.600 | + | mem/dcache/FE_PHN3288_STATE_2 | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC2590_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 3 | 25.500 | 80.600 | 196.200 | + | mem/dcache/FE_PHN2590_STATE_2 | | | F | (net) | 3 | | | | + | mem/dcache/g11633/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 36.500 | 11.700 | 207.900 | + | mem/dcache/n_204 | | | R | (net) | 2 | | | | + | mem/dcache/g11616/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 6 | 18.500 | 19.800 | 227.700 | + | mem/dcache/n_325 | | | F | (net) | 6 | | | | + | mem/dcache/g14031/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 40.100 | 21.600 | 249.300 | + | mem/dcache/n_92 | | | R | (net) | 3 | | | | + | mem/dcache/g14018/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 33.100 | 29.600 | 278.900 | + | mem/d_stall_n | | | F | (net) | 1 | | | | + | mem/g20/Y | | A->Y | R | NAND2x1_ASAP7_75t_SL | 41 | 55.700 | 136.000 | 414.900 | + | stall | | | R | (net) | 41 | | | | + | cpu/s1_to_s2_imm/g213__2398/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 275.200 | 8.700 | 423.600 | + | cpu/s1_to_s2_imm/n_34 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_ | | ENA | F | ICGx3_ASAP7_75t_SL | 1 | 77.100 | 0.100 | 423.600 | + | INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 46.800 | 847.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_ | | CLK | R | ICGx3_ASAP7_75t_SL | 6 | 38.700 | 3.000 | 847.800 | + | INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 9: MET (291.225 ps) Clock Gating Setup Check with Pin cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 87.700 (P) 151.100 (P) + Arrival:= 848.700 12.100 + + Clock Gating Setup:- 34.075 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 714.625 + Launch Clock:= 12.100 + Data Path:+ 411.300 + Slack:= 291.225 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 26.700 | -100.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 17.700 | 27.500 | -72.500 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 29.700 | 46.800 | -25.700 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 47.900 | 37.800 | 12.100 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[2]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 1 | 27.000 | 33.800 | 45.900 | + | mem/dcache/STATE[2] | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC3288_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 15.800 | 69.700 | 115.600 | + | mem/dcache/FE_PHN3288_STATE_2 | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC2590_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 3 | 25.500 | 80.600 | 196.200 | + | mem/dcache/FE_PHN2590_STATE_2 | | | F | (net) | 3 | | | | + | mem/dcache/g11633/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 36.500 | 11.700 | 207.900 | + | mem/dcache/n_204 | | | R | (net) | 2 | | | | + | mem/dcache/g11616/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 6 | 18.500 | 19.800 | 227.700 | + | mem/dcache/n_325 | | | F | (net) | 6 | | | | + | mem/dcache/g14031/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 40.100 | 21.600 | 249.300 | + | mem/dcache/n_92 | | | R | (net) | 3 | | | | + | mem/dcache/g14018/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 33.100 | 29.600 | 278.900 | + | mem/d_stall_n | | | F | (net) | 1 | | | | + | mem/g20/Y | | A->Y | R | NAND2x1_ASAP7_75t_SL | 41 | 55.700 | 136.100 | 415.000 | + | stall | | | R | (net) | 41 | | | | + | cpu/s1_to_s2_rs2/g213__9315/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 275.200 | 8.400 | 423.400 | + | cpu/s1_to_s2_rs2/n_34 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | ENA | F | ICGx3_ASAP7_75t_SL | 1 | 76.800 | 0.100 | 423.400 | + | INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK | R | ICGx3_ASAP7_75t_SL | 4 | 53.000 | 0.800 | 848.700 | + | INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 10: MET (294.596 ps) Clock Gating Setup Check with Pin cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 92.200 (P) 151.100 (P) + Arrival:= 853.200 12.100 + + Clock Gating Setup:- 33.704 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 719.496 + Launch Clock:= 12.100 + Data Path:+ 412.800 + Slack:= 294.596 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 26.700 | -100.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 17.700 | 27.500 | -72.500 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 29.700 | 46.800 | -25.700 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 47.900 | 37.800 | 12.100 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[2]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 1 | 27.000 | 33.800 | 45.900 | + | mem/dcache/STATE[2] | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC3288_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 15.800 | 69.700 | 115.600 | + | mem/dcache/FE_PHN3288_STATE_2 | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC2590_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 3 | 25.500 | 80.600 | 196.200 | + | mem/dcache/FE_PHN2590_STATE_2 | | | F | (net) | 3 | | | | + | mem/dcache/g11633/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 36.500 | 11.700 | 207.900 | + | mem/dcache/n_204 | | | R | (net) | 2 | | | | + | mem/dcache/g11616/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 6 | 18.500 | 19.800 | 227.700 | + | mem/dcache/n_325 | | | F | (net) | 6 | | | | + | mem/dcache/g14031/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 40.100 | 21.600 | 249.300 | + | mem/dcache/n_92 | | | R | (net) | 3 | | | | + | mem/dcache/g14018/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 33.100 | 29.600 | 278.900 | + | mem/d_stall_n | | | F | (net) | 1 | | | | + | mem/g20/Y | | A->Y | R | NAND2x1_ASAP7_75t_SL | 41 | 55.700 | 140.100 | 419.000 | + | stall | | | R | (net) | 41 | | | | + | cpu/s1_to_s2_inst/g261__5122/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 275.200 | 5.900 | 424.900 | + | cpu/s1_to_s2_inst/n_34 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | ENA | F | ICGx3_ASAP7_75t_SL | 1 | 74.400 | 0.100 | 424.900 | + | _INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 49.700 | 853.200 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK | R | ICGx3_ASAP7_75t_SL | 4 | 53.900 | 5.300 | 853.200 | + | _INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 11: MET (294.916 ps) Clock Gating Setup Check with Pin cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 85.800 (P) 151.100 (P) + Arrival:= 846.800 12.100 + + Clock Gating Setup:- 33.584 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 713.216 + Launch Clock:= 12.100 + Data Path:+ 406.200 + Slack:= 294.916 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 26.700 | -100.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 17.700 | 27.500 | -72.500 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 29.700 | 46.800 | -25.700 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 47.900 | 37.800 | 12.100 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[2]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 1 | 27.000 | 33.800 | 45.900 | + | mem/dcache/STATE[2] | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC3288_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 15.800 | 69.700 | 115.600 | + | mem/dcache/FE_PHN3288_STATE_2 | | | F | (net) | 1 | | | | + | mem/dcache/FE_PHC2590_STATE_2/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 3 | 25.500 | 80.600 | 196.200 | + | mem/dcache/FE_PHN2590_STATE_2 | | | F | (net) | 3 | | | | + | mem/dcache/g11633/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 36.500 | 11.700 | 207.900 | + | mem/dcache/n_204 | | | R | (net) | 2 | | | | + | mem/dcache/g11616/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 6 | 18.500 | 19.800 | 227.700 | + | mem/dcache/n_325 | | | F | (net) | 6 | | | | + | mem/dcache/g14031/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 40.100 | 21.600 | 249.300 | + | mem/dcache/n_92 | | | R | (net) | 3 | | | | + | mem/dcache/g14018/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 33.100 | 29.600 | 278.900 | + | mem/d_stall_n | | | F | (net) | 1 | | | | + | mem/g20/Y | | A->Y | R | NAND2x1_ASAP7_75t_SL | 41 | 55.700 | 131.400 | 410.300 | + | stall | | | R | (net) | 41 | | | | + | cpu/s2_to_s3_alu/g213__7410/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 274.900 | 8.000 | 418.300 | + | cpu/s2_to_s3_alu/n_34 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | ENA | F | ICGx3_ASAP7_75t_SL | 1 | 76.300 | 0.100 | 418.300 | + | INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK | R | ICGx3_ASAP7_75t_SL | 6 | 38.700 | 2.000 | 846.800 | + | INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 12: MET (312.050 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 79.600 (P) 160.100 (P) + Arrival:= 840.600 21.100 + + Clock Gating Setup:- 29.550 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 711.050 + Launch Clock:= 21.100 + Data Path:+ 377.900 + Slack:= 312.050 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77627/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.800 | 382.600 | + | cpu/stage1/regfile/n_1702 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77199/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 55.800 | 16.400 | 399.000 | + | cpu/stage1/regfile/n_2188 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 47.100 | 0.400 | 399.000 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.800 | 840.600 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.600 | 4.600 | 840.600 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 13: MET (312.512 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 80.000 (P) 160.100 (P) + Arrival:= 841.000 21.100 + + Clock Gating Setup:- 29.488 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 711.512 + Launch Clock:= 21.100 + Data Path:+ 377.900 + Slack:= 312.512 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77625/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.800 | 382.600 | + | cpu/stage1/regfile/n_1704 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77203/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 55.800 | 16.400 | 399.000 | + | cpu/stage1/regfile/n_2197 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 46.800 | 0.300 | 399.000 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 35.200 | 841.000 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.700 | 5.000 | 841.000 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 14: MET (313.620 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 79.600 (P) 160.100 (P) + Arrival:= 840.600 21.100 + + Clock Gating Setup:- 29.280 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 711.320 + Launch Clock:= 21.100 + Data Path:+ 376.600 + Slack:= 313.620 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77627/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.600 | 382.400 | + | cpu/stage1/regfile/n_1702 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77172/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 55.800 | 15.300 | 397.700 | + | cpu/stage1/regfile/n_2186 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 45.800 | 0.300 | 397.700 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.800 | 840.600 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.600 | 4.600 | 840.600 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 15: MET (313.892 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 79.300 (P) 160.100 (P) + Arrival:= 840.300 21.100 + + Clock Gating Setup:- 29.308 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 710.992 + Launch Clock:= 21.100 + Data Path:+ 376.000 + Slack:= 313.892 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77625/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.500 | 382.300 | + | cpu/stage1/regfile/n_1704 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77162/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 55.800 | 14.800 | 397.100 | + | cpu/stage1/regfile/n_2189 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 45.200 | 0.300 | 397.100 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 42.800 | 840.300 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 48.000 | 15.100 | 840.300 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 16: MET (317.103 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 79.800 (P) 160.100 (P) + Arrival:= 840.800 21.100 + + Clock Gating Setup:- 28.697 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 712.103 + Launch Clock:= 21.100 + Data Path:+ 373.900 + Slack:= 317.103 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77627/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.700 | 382.500 | + | cpu/stage1/regfile/n_1702 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77178/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 55.800 | 12.500 | 395.000 | + | cpu/stage1/regfile/n_2194 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 42.300 | 0.200 | 395.000 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 43.300 | 840.800 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 48.000 | 15.600 | 840.800 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 17: MET (318.246 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 78.100 (P) 160.100 (P) + Arrival:= 839.100 21.100 + + Clock Gating Setup:- 27.854 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 711.246 + Launch Clock:= 21.100 + Data Path:+ 371.900 + Slack:= 318.246 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77625/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.600 | 382.400 | + | cpu/stage1/regfile/n_1704 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77202/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 55.800 | 10.600 | 393.000 | + | cpu/stage1/regfile/n_2195 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CG | | ENA | F | ICGx2_ASAP7_75t_SL | 1 | 40.700 | 0.100 | 393.000 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 33.300 | 839.100 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CG | | CLK | R | ICGx2_ASAP7_75t_SL | 9 | 38.300 | 3.100 | 839.100 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 18: MET (318.517 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 79.400 (P) 160.100 (P) + Arrival:= 840.400 21.100 + + Clock Gating Setup:- 28.283 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 712.117 + Launch Clock:= 21.100 + Data Path:+ 372.500 + Slack:= 318.517 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77627/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.700 | 382.500 | + | cpu/stage1/regfile/n_1702 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77180/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 55.800 | 11.100 | 393.600 | + | cpu/stage1/regfile/n_2196 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 41.000 | 0.100 | 393.600 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.600 | 840.400 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.600 | 4.400 | 840.400 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 19: MET (319.321 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 79.500 (P) 160.100 (P) + Arrival:= 840.500 21.100 + + Clock Gating Setup:- 28.179 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 712.321 + Launch Clock:= 21.100 + Data Path:+ 371.900 + Slack:= 319.321 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77625/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.700 | 382.500 | + | cpu/stage1/regfile/n_1704 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77158/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 55.800 | 10.500 | 393.000 | + | cpu/stage1/regfile/n_2187 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 40.500 | 0.100 | 393.000 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.700 | 840.500 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.600 | 4.500 | 840.500 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 20: MET (322.697 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 85.000 (P) 160.100 (P) + Arrival:= 846.000 21.100 + + Clock Gating Setup:- 28.703 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 717.297 + Launch Clock:= 21.100 + Data Path:+ 373.500 + Slack:= 322.697 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77628/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.200 | 382.000 | + | cpu/stage1/regfile/n_1701 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77201/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 53.900 | 12.600 | 394.600 | + | cpu/stage1/regfile/n_2201 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 42.900 | 0.200 | 394.600 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 40.600 | 846.000 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.100 | 3.400 | 846.000 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 21: MET (322.702 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 86.500 (P) 160.100 (P) + Arrival:= 847.500 21.100 + + Clock Gating Setup:- 28.998 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 718.502 + Launch Clock:= 21.100 + Data Path:+ 374.700 + Slack:= 322.702 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77628/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.100 | 381.900 | + | cpu/stage1/regfile/n_1701 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77200/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 53.900 | 13.900 | 395.800 | + | cpu/stage1/regfile/n_2199 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 44.200 | 0.300 | 395.800 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 42.100 | 847.500 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.700 | 4.900 | 847.500 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 22: MET (323.014 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 87.700 (P) 160.100 (P) + Arrival:= 848.700 21.100 + + Clock Gating Setup:- 29.086 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 719.614 + Launch Clock:= 21.100 + Data Path:+ 375.500 + Slack:= 323.014 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77626/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.500 | 382.300 | + | cpu/stage1/regfile/n_1703 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77171/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 54.300 | 14.300 | 396.600 | + | cpu/stage1/regfile/n_2190 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 44.600 | 0.300 | 396.600 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 43.300 | 848.700 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.900 | 6.100 | 848.700 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 23: MET (323.159 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 85.100 (P) 160.100 (P) + Arrival:= 846.100 21.100 + + Clock Gating Setup:- 28.641 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 717.459 + Launch Clock:= 21.100 + Data Path:+ 373.200 + Slack:= 323.159 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77628/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.200 | 382.000 | + | cpu/stage1/regfile/n_1701 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77161/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 53.900 | 12.300 | 394.300 | + | cpu/stage1/regfile/n_2193 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 42.600 | 0.200 | 394.300 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 40.700 | 846.100 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.100 | 3.500 | 846.100 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 24: MET (324.004 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 87.100 (P) 160.100 (P) + Arrival:= 848.100 21.100 + + Clock Gating Setup:- 28.896 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 719.204 + Launch Clock:= 21.100 + Data Path:+ 374.100 + Slack:= 324.004 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77628/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.100 | 381.900 | + | cpu/stage1/regfile/n_1701 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77157/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 53.900 | 13.300 | 395.200 | + | cpu/stage1/regfile/n_2191 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 43.700 | 0.200 | 395.200 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 42.700 | 848.100 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.800 | 5.500 | 848.100 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 25: MET (324.125 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 84.400 (P) 160.100 (P) + Arrival:= 845.400 21.100 + + Clock Gating Setup:- 28.375 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 717.025 + Launch Clock:= 21.100 + Data Path:+ 371.800 + Slack:= 324.125 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77626/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.100 | 381.900 | + | cpu/stage1/regfile/n_1703 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77179/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 54.300 | 11.000 | 392.900 | + | cpu/stage1/regfile/n_2200 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 41.300 | 0.100 | 392.900 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 40.000 | 845.400 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.200 | 2.800 | 845.400 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 26: MET (324.564 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 87.800 (P) 160.100 (P) + Arrival:= 848.800 21.100 + + Clock Gating Setup:- 28.836 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 719.964 + Launch Clock:= 21.100 + Data Path:+ 374.300 + Slack:= 324.564 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77626/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.500 | 382.300 | + | cpu/stage1/regfile/n_1703 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77246/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 54.300 | 13.100 | 395.400 | + | cpu/stage1/regfile/n_2198 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 43.400 | 0.200 | 395.400 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 43.400 | 848.800 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.900 | 6.200 | 848.800 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 27: MET (324.951 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 85.400 (P) 160.100 (P) + Arrival:= 846.400 21.100 + + Clock Gating Setup:- 28.349 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 718.051 + Launch Clock:= 21.100 + Data Path:+ 372.000 + Slack:= 324.951 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.800 | 329.200 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77822/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 230.700 | 18.600 | 347.800 | + | cpu/stage1/regfile/n_1317 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77626/Y | | A->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 70.300 | 34.300 | 382.100 | + | cpu/stage1/regfile/n_1703 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77198/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 54.300 | 11.000 | 393.100 | + | cpu/stage1/regfile/n_2192 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 41.200 | 0.100 | 393.100 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 41.000 | 846.400 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.100 | 3.800 | 846.400 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 28: MET (357.799 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 78.800 (P) 160.100 (P) + Arrival:= 839.800 21.100 + + Clock Gating Setup:- 36.701 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 703.099 + Launch Clock:= 21.100 + Data Path:+ 324.200 + Slack:= 357.799 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 102.000 | 329.400 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77348/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 230.700 | 15.900 | 345.300 | + | cpu/stage1/regfile/n_2203 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 80.300 | 0.300 | 345.300 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 42.300 | 839.800 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 48.000 | 14.600 | 839.800 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 29: MET (359.553 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 80.100 (P) 160.100 (P) + Arrival:= 841.100 21.100 + + Clock Gating Setup:- 36.447 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 704.653 + Launch Clock:= 21.100 + Data Path:+ 324.000 + Slack:= 359.553 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.400 | 328.800 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77361/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 230.700 | 16.300 | 345.100 | + | cpu/stage1/regfile/n_2202 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 80.600 | 0.300 | 345.100 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 35.300 | 841.100 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.700 | 5.100 | 841.100 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 30: MET (360.416 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 84.300 (P) 160.100 (P) + Arrival:= 845.300 21.100 + + Clock Gating Setup:- 36.784 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 708.516 + Launch Clock:= 21.100 + Data Path:+ 327.000 + Slack:= 360.416 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 102.100 | 329.500 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77259/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 230.700 | 18.600 | 348.100 | + | cpu/stage1/regfile/n_2209 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 82.900 | 0.400 | 348.100 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 39.900 | 845.300 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 39.900 | 2.700 | 845.300 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 31: MET (360.703 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 82.900 (P) 160.100 (P) + Arrival:= 843.900 21.100 + + Clock Gating Setup:- 36.697 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 707.203 + Launch Clock:= 21.100 + Data Path:+ 325.400 + Slack:= 360.703 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 100.900 | 328.300 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77360/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 230.700 | 18.200 | 346.500 | + | cpu/stage1/regfile/n_2210 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 82.500 | 0.400 | 346.500 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 38.500 | 843.900 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 39.400 | 1.300 | 843.900 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 32: MET (362.183 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 79.600 (P) 160.100 (P) + Arrival:= 840.600 21.100 + + Clock Gating Setup:- 36.117 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 704.483 + Launch Clock:= 21.100 + Data Path:+ 321.200 + Slack:= 362.183 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 102.200 | 329.600 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77356/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 230.800 | 12.700 | 342.300 | + | cpu/stage1/regfile/n_2204 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 77.400 | 0.200 | 342.300 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 43.100 | 840.600 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 48.000 | 15.400 | 840.600 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 33: MET (363.110 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 79.600 (P) 160.100 (P) + Arrival:= 840.600 21.100 + + Clock Gating Setup:- 35.990 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 704.610 + Launch Clock:= 21.100 + Data Path:+ 320.400 + Slack:= 363.110 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 102.100 | 329.500 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77355/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 230.700 | 12.000 | 341.500 | + | cpu/stage1/regfile/n_2205 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 76.800 | 0.200 | 341.500 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 43.100 | 840.600 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 48.000 | 15.400 | 840.600 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 34: MET (363.305 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 85.500 (P) 160.100 (P) + Arrival:= 846.500 21.100 + + Clock Gating Setup:- 35.795 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 710.705 + Launch Clock:= 21.100 + Data Path:+ 326.300 + Slack:= 363.305 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.400 | 328.800 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77250/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 230.700 | 18.600 | 347.400 | + | cpu/stage1/regfile/n_2216 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGI | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 77.000 | 0.300 | 347.400 | + | C_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 41.100 | 846.500 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGI | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.100 | 3.900 | 846.500 | + | C_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 35: MET (364.477 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 79.600 (P) 160.100 (P) + Arrival:= 840.600 21.100 + + Clock Gating Setup:- 35.623 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 704.977 + Launch Clock:= 21.100 + Data Path:+ 319.400 + Slack:= 364.477 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.600 | 329.000 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77354/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 230.700 | 11.500 | 340.500 | + | cpu/stage1/regfile/n_2212 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 76.400 | 0.200 | 340.500 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.800 | 840.600 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.600 | 4.600 | 840.600 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 36: MET (365.781 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 85.700 (P) 160.100 (P) + Arrival:= 846.700 21.100 + + Clock Gating Setup:- 36.419 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 710.281 + Launch Clock:= 21.100 + Data Path:+ 323.400 + Slack:= 365.781 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.400 | 328.800 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77362/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 230.700 | 15.700 | 344.500 | + | cpu/stage1/regfile/n_2206 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 80.000 | 0.400 | 344.500 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 41.300 | 846.700 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.100 | 4.100 | 846.700 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 37: MET (365.834 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 79.000 (P) 160.100 (P) + Arrival:= 840.000 21.100 + + Clock Gating Setup:- 35.266 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 704.734 + Launch Clock:= 21.100 + Data Path:+ 317.800 + Slack:= 365.834 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 102.200 | 329.600 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77358/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 230.800 | 9.300 | 338.900 | + | cpu/stage1/regfile/n_2213 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 74.700 | 0.100 | 338.900 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.600 | 805.800 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 26.500 | 34.200 | 840.000 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 38.600 | 4.000 | 840.000 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 38: MET (365.950 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 83.800 (P) 160.100 (P) + Arrival:= 844.800 21.100 + + Clock Gating Setup:- 34.950 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 709.850 + Launch Clock:= 21.100 + Data Path:+ 322.800 + Slack:= 365.950 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 102.100 | 329.500 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77249/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 230.700 | 14.400 | 343.900 | + | cpu/stage1/regfile/n_2208 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 73.000 | 0.200 | 343.900 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 39.400 | 844.800 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 39.900 | 2.200 | 844.800 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 39: MET (368.057 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 87.800 (P) 160.100 (P) + Arrival:= 848.800 21.100 + + Clock Gating Setup:- 36.543 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 712.257 + Launch Clock:= 21.100 + Data Path:+ 323.100 + Slack:= 368.057 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 100.600 | 328.000 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77357/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 230.600 | 16.200 | 344.200 | + | cpu/stage1/regfile/n_2215 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 80.500 | 0.300 | 344.200 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 43.400 | 848.800 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.900 | 6.200 | 848.800 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 40: MET (372.533 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 89.600 (P) 160.100 (P) + Arrival:= 850.600 21.100 + + Clock Gating Setup:- 36.567 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 714.033 + Launch Clock:= 21.100 + Data Path:+ 320.400 + Slack:= 372.533 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 100.600 | 328.000 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77254/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 230.600 | 13.500 | 341.500 | + | cpu/stage1/regfile/n_2207 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 78.000 | 0.300 | 341.500 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 47.100 | 850.600 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 4 | 53.300 | 2.700 | 850.600 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 41: MET (376.785 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 85.000 (P) 160.100 (P) + Arrival:= 846.000 21.100 + + Clock Gating Setup:- 34.715 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 711.285 + Launch Clock:= 21.100 + Data Path:+ 313.400 + Slack:= 376.785 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 102.100 | 329.500 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77353/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 230.700 | 5.000 | 334.500 | + | cpu/stage1/regfile/n_2211 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 71.700 | 0.000 | 334.500 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 40.600 | 846.000 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.400 | 3.400 | 846.000 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 42: MET (379.438 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 87.200 (P) 160.100 (P) + Arrival:= 848.200 21.100 + + Clock Gating Setup:- 34.762 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 713.438 + Launch Clock:= 21.100 + Data Path:+ 312.900 + Slack:= 379.438 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+---------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.100 | 21.100 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[7]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 5 | 64.300 | 50.200 | 71.300 | + | cpu/stage3_inst[7] | | | F | (net) | 5 | | | | + | cpu/FE_PHC3512_stage3_inst_7/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 1 | 11.200 | 40.500 | 111.800 | + | cpu/FE_PHN3512_stage3_inst_7 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2599_stage3_inst_7/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 5 | 15.700 | 43.400 | 155.200 | + | cpu/FE_PHN2599_stage3_inst_7 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC911_stage3_inst_7/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 22.300 | 20.300 | 175.500 | + | cpu/stage1/regfile/FE_OFN1042_stage3_inst_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC912_stage3_inst_7/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 34.600 | 12.500 | 188.000 | + | cpu/stage1/regfile/FE_OFN1043_stage3_inst_7 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g80393/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 4 | 20.600 | 30.300 | 218.300 | + | cpu/stage1/regfile/n_252 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79868/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 63.700 | 9.100 | 227.400 | + | cpu/stage1/regfile/n_251 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78085/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 23.000 | 101.400 | 328.800 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77359/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 230.700 | 5.200 | 334.000 | + | cpu/stage1/regfile/n_2214 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 71.800 | 0.000 | 334.000 | + | IC_INST/ENA | | | | | | | | | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 33.200 | 805.400 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 26.500 | 42.800 | 848.200 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 40.800 | 5.600 | 848.200 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 43: MET (389.228 ps) Clock Gating Setup Check with Pin cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 108.400 (P) 142.000 (P) + Arrival:= 869.400 3.000 + + Clock Gating Setup:- 33.272 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 736.128 + Launch Clock:= 3.000 + Data Path:+ 343.900 + Slack:= 389.228 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 56.700 | -36.800 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 66.000 | 39.800 | 3.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[2]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 1 | 56.800 | 35.200 | 38.200 | + | cpu/stage2_inst[2] | | | F | (net) | 1 | | | | + | cpu/FE_OFC948_stage2_inst_2/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 13.800 | 8.000 | 46.200 | + | cpu/FE_OFN851_stage2_inst_2 | | | R | (net) | 2 | | | | + | cpu/FE_OFC952_stage2_inst_2/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 10 | 12.000 | 20.000 | 66.200 | + | cpu/FE_OFN850_stage2_inst_2 | | | F | (net) | 10 | | | | + | cpu/FE_PHC2681_FE_OFN850_stage2_inst_2/Y | | A->Y | F | HB3xp67_ASAP7_75t_SRAM | 4 | 36.900 | 98.300 | 164.500 | + | cpu/FE_PHN2681_FE_OFN850_stage2_inst_2 | | | F | (net) | 4 | | | | + | cpu/stage3/csrsel/g212/Y | | C->Y | R | NOR5xp2_ASAP7_75t_SL | 1 | 64.000 | 33.600 | 198.100 | + | cpu/stage3/csrsel/n_7 | | | R | (net) | 1 | | | | + | cpu/stage3/csrsel/g211/Y | | A->Y | R | AND5x1_ASAP7_75t_SL | 1 | 63.300 | 49.200 | 247.300 | + | cpu/stage3/CSRSelect | | | R | (net) | 1 | | | | + | cpu/stage3/csr/g195/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 1 | 56.300 | 19.700 | 267.000 | + | cpu/stage3/csr/n_33 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC3551_n_33/Y | | A->Y | R | HB1xp67_ASAP7_75t_SRAM | 1 | 12.400 | 28.100 | 295.100 | + | cpu/stage3/csr/FE_PHN3551_n_33 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/FE_PHC268 | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 23.600 | 51.800 | 346.900 | + | 9_n_33/Y | | | | | | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/FE_PHN268 | | | R | (net) | 1 | | | | + | 9_n_33 | | | | | | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | ENA | R | ICGx3_ASAP7_75t_SL | 1 | 20.000 | 0.000 | 346.900 | + | NST/ENA | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK | R | ICGx3_ASAP7_75t_SL | 3 | 39.800 | 4.200 | 869.400 | + | NST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ + diff --git a/build/par-rundir/timingReports/riscv_top_postRoute_reg2cgate_hold.tarpt b/build/par-rundir/timingReports/riscv_top_postRoute_reg2cgate_hold.tarpt new file mode 100644 index 0000000..60f105d --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute_reg2cgate_hold.tarpt @@ -0,0 +1,2892 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:14 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### +Path 1: MET (13.069 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 64.200 (P) 82.600 (P) + Arrival:= -19.664 -1.264 + + Clock Gating Hold:+ -4.769 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 75.567 + Launch Clock:= -1.264 + Data Path:+ 89.900 + Slack:= 13.069 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77625/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 15.300 | 83.536 | + | cpu/stage1/regfile/n_1704 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77158/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 21.000 | 5.100 | 88.636 | + | cpu/stage1/regfile/n_2187 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 10.500 | 0.000 | 88.636 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 29.800 | -19.664 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 26.600 | 5.300 | -19.664 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 2: MET (13.070 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 64.100 (P) 82.600 (P) + Arrival:= -19.764 -1.264 + + Clock Gating Hold:+ -4.570 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 75.666 + Launch Clock:= -1.264 + Data Path:+ 90.000 + Slack:= 13.070 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77627/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 15.200 | 83.436 | + | cpu/stage1/regfile/n_1702 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77180/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 19.500 | 5.300 | 88.736 | + | cpu/stage1/regfile/n_2196 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 9.400 | 0.000 | 88.736 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 29.700 | -19.764 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 26.600 | 5.200 | -19.764 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 3: MET (13.255 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 60.000 (P) 82.900 (P) + Arrival:= -23.864 -0.964 + + Clock Gating Hold:+ -5.155 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 70.981 + Launch Clock:= -0.964 + Data Path:+ 85.200 + Slack:= 13.255 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 21.200 | -0.964 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[8]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 5 | 26.800 | 28.600 | 27.636 | + | cpu/stage3_inst[8] | | | R | (net) | 5 | | | | + | cpu/FE_PHC3511_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SRAM | 2 | 6.800 | 15.000 | 42.636 | + | cpu/FE_PHN3511_stage3_inst_8 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 8 | 13.700 | 29.900 | 72.536 | + | cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 | | | R | (net) | 8 | | | | + | cpu/stage1/regfile/g79356/Y | | B->Y | R | OR3x1_ASAP7_75t_SL | 1 | 54.300 | 5.700 | 78.236 | + | cpu/stage1/regfile/n_261 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77250/Y | | A1->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 4.100 | 6.000 | 84.236 | + | cpu/stage1/regfile/n_2216 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGI | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 10.700 | 0.200 | 84.236 | + | C_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 26.000 | -23.864 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGI | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 29.400 | 5.300 | -23.864 | + | C_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 4: MET (13.841 ps) Clock Gating Hold Check with Pin cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[21]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 65.300 (P) 73.300 (P) + Arrival:= -18.564 -10.564 + + Clock Gating Hold:+ -7.641 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 73.795 + Launch Clock:= -10.564 + Data Path:+ 98.200 + Slack:= 13.841 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 17.600 | -10.564 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[21]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 2 | 30.000 | 23.800 | 13.236 | + | cpu/stage2_inst[21] | | | R | (net) | 2 | | | | + | cpu/stage3/csrsel/g211/Y | | E->Y | R | AND5x1_ASAP7_75t_SL | 1 | 12.200 | 25.200 | 38.436 | + | cpu/stage3/CSRSelect | | | R | (net) | 1 | | | | + | cpu/stage3/csr/g195/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 1 | 28.100 | 11.100 | 49.536 | + | cpu/stage3/csr/n_33 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC3551_n_33/Y | | A->Y | R | HB1xp67_ASAP7_75t_SRAM | 1 | 6.100 | 12.000 | 61.536 | + | cpu/stage3/csr/FE_PHN3551_n_33 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/FE_PHC268 | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.800 | 26.100 | 87.636 | + | 9_n_33/Y | | | | | | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/FE_PHN268 | | | R | (net) | 1 | | | | + | 9_n_33 | | | | | | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | ENA | R | ICGx3_ASAP7_75t_SL | 1 | 9.600 | 0.000 | 87.636 | + | NST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 22.300 | -18.564 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK | R | ICGx3_ASAP7_75t_SL | 3 | 23.700 | 4.700 | -18.564 | + | NST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 5: MET (14.313 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 62.400 (P) 82.600 (P) + Arrival:= -21.464 -1.264 + + Clock Gating Hold:+ -4.313 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 74.223 + Launch Clock:= -1.264 + Data Path:+ 89.800 + Slack:= 14.313 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77625/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 15.200 | 83.436 | + | cpu/stage1/regfile/n_1704 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77202/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 21.000 | 5.100 | 88.536 | + | cpu/stage1/regfile/n_2195 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CG | | ENA | F | ICGx2_ASAP7_75t_SL | 1 | 8.200 | 0.000 | 88.536 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 28.000 | -21.464 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CG | | CLK | R | ICGx2_ASAP7_75t_SL | 9 | 26.300 | 3.500 | -21.464 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 6: MET (14.516 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 64.900 (P) 82.900 (P) + Arrival:= -18.964 -0.964 + + Clock Gating Hold:+ -8.416 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 72.620 + Launch Clock:= -0.964 + Data Path:+ 88.100 + Slack:= 14.516 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 21.200 | -0.964 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[8]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 5 | 26.800 | 28.600 | 27.636 | + | cpu/stage3_inst[8] | | | R | (net) | 5 | | | | + | cpu/FE_PHC3511_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SRAM | 2 | 6.800 | 15.000 | 42.636 | + | cpu/FE_PHN3511_stage3_inst_8 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 8 | 13.700 | 29.900 | 72.536 | + | cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 | | | R | (net) | 8 | | | | + | cpu/stage1/regfile/g79798/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 54.300 | 4.300 | 76.836 | + | cpu/stage1/regfile/n_351 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g77361/Y | | A2->Y | R | OAI31xp33_ASAP7_75t_SL | 1 | 8.700 | 10.300 | 87.136 | + | cpu/stage1/regfile/n_2202 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CG | | ENA | R | ICGx1_ASAP7_75t_SL | 1 | 19.300 | 0.200 | 87.136 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 30.500 | -18.964 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 26.600 | 6.000 | -18.964 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 7: MET (14.645 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 62.300 (P) 82.900 (P) + Arrival:= -21.564 -0.964 + + Clock Gating Hold:+ -8.345 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 70.091 + Launch Clock:= -0.964 + Data Path:+ 85.700 + Slack:= 14.645 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 21.200 | -0.964 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[8]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 5 | 26.800 | 28.600 | 27.636 | + | cpu/stage3_inst[8] | | | R | (net) | 5 | | | | + | cpu/FE_PHC3511_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SRAM | 2 | 6.800 | 15.000 | 42.636 | + | cpu/FE_PHN3511_stage3_inst_8 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 8 | 13.700 | 29.900 | 72.536 | + | cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 | | | R | (net) | 8 | | | | + | cpu/stage1/regfile/g79796/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 54.300 | 5.000 | 77.536 | + | cpu/stage1/regfile/n_353 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g77359/Y | | A2->Y | R | OAI31xp33_ASAP7_75t_SL | 1 | 9.600 | 7.200 | 84.736 | + | cpu/stage1/regfile/n_2214 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CG | | ENA | R | ICGx1_ASAP7_75t_SL | 1 | 12.400 | 0.000 | 84.736 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 28.300 | -21.564 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 31.300 | 7.600 | -21.564 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 8: MET (14.753 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 64.300 (P) 82.600 (P) + Arrival:= -19.564 -1.264 + + Clock Gating Hold:+ -5.053 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 75.383 + Launch Clock:= -1.264 + Data Path:+ 91.400 + Slack:= 14.753 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 25.900 | 24.636 | + | cpu/stage3_inst[11] | | | R | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 2 | 16.300 | 24.000 | 48.636 | + | cpu/FE_PHN2611_stage3_inst_11 | | | R | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 15.300 | 4.100 | 52.736 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | F | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 10 | 7.700 | 15.300 | 68.036 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | R | (net) | 10 | | | | + | cpu/stage1/regfile/g80395/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 7 | 28.000 | 14.100 | 82.136 | + | cpu/stage1/regfile/n_248 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g77354/Y | | A3->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 12.100 | 8.000 | 90.136 | + | cpu/stage1/regfile/n_2212 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 12.100 | 0.100 | 90.136 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 29.900 | -19.564 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 26.600 | 5.400 | -19.564 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 9: MET (14.829 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 63.500 (P) 82.600 (P) + Arrival:= -20.364 -1.264 + + Clock Gating Hold:+ -4.929 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 74.707 + Launch Clock:= -1.264 + Data Path:+ 90.800 + Slack:= 14.829 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 25.900 | 24.636 | + | cpu/stage3_inst[11] | | | R | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 2 | 16.300 | 24.000 | 48.636 | + | cpu/FE_PHN2611_stage3_inst_11 | | | R | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 15.300 | 4.100 | 52.736 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | F | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 10 | 7.700 | 15.300 | 68.036 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | R | (net) | 10 | | | | + | cpu/stage1/regfile/g80395/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 7 | 28.000 | 14.100 | 82.136 | + | cpu/stage1/regfile/n_248 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g77358/Y | | A3->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 12.100 | 7.400 | 89.536 | + | cpu/stage1/regfile/n_2213 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 11.400 | 0.100 | 89.536 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 29.100 | -20.364 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 26.600 | 4.600 | -20.364 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 10: MET (15.466 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 64.300 (P) 82.600 (P) + Arrival:= -19.564 -1.264 + + Clock Gating Hold:+ -5.266 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 75.170 + Launch Clock:= -1.264 + Data Path:+ 91.900 + Slack:= 15.466 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77627/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 15.100 | 83.336 | + | cpu/stage1/regfile/n_1702 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77172/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 19.500 | 7.300 | 90.636 | + | cpu/stage1/regfile/n_2186 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 13.300 | 0.200 | 90.636 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 29.900 | -19.564 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 26.600 | 5.400 | -19.564 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 11: MET (15.556 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 63.100 (P) 82.600 (P) + Arrival:= -20.764 -1.264 + + Clock Gating Hold:+ -5.256 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 73.980 + Launch Clock:= -1.264 + Data Path:+ 90.800 + Slack:= 15.556 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77626/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 15.100 | 83.336 | + | cpu/stage1/regfile/n_1703 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77246/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 19.000 | 6.200 | 89.536 | + | cpu/stage1/regfile/n_2198 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 9.700 | 0.100 | 89.536 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 29.100 | -20.764 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 31.400 | 8.400 | -20.764 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 12: MET (15.877 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 64.700 (P) 82.600 (P) + Arrival:= -19.164 -1.264 + + Clock Gating Hold:+ -5.177 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 75.659 + Launch Clock:= -1.264 + Data Path:+ 92.800 + Slack:= 15.877 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77625/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 15.300 | 83.536 | + | cpu/stage1/regfile/n_1704 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77203/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 21.000 | 8.000 | 91.536 | + | cpu/stage1/regfile/n_2197 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 12.800 | 0.300 | 91.536 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 30.300 | -19.164 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 26.600 | 5.800 | -19.164 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 13: MET (16.290 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 64.300 (P) 82.600 (P) + Arrival:= -19.564 -1.264 + + Clock Gating Hold:+ -5.390 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 75.046 + Launch Clock:= -1.264 + Data Path:+ 92.600 + Slack:= 16.290 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77627/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 15.200 | 83.436 | + | cpu/stage1/regfile/n_1702 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77199/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 19.500 | 7.900 | 91.336 | + | cpu/stage1/regfile/n_2188 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 13.900 | 0.300 | 91.336 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 29.900 | -19.564 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 9 | 26.600 | 5.400 | -19.564 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 14: MET (16.643 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 63.000 (P) 82.600 (P) + Arrival:= -20.864 -1.264 + + Clock Gating Hold:+ -5.743 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 73.393 + Launch Clock:= -1.264 + Data Path:+ 91.300 + Slack:= 16.643 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77626/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 15.100 | 83.336 | + | cpu/stage1/regfile/n_1703 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77171/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 19.000 | 6.700 | 90.036 | + | cpu/stage1/regfile/n_2190 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 12.500 | 0.100 | 90.036 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 29.000 | -20.864 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 31.400 | 8.300 | -20.864 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 15: MET (16.755 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 59.500 (P) 82.900 (P) + Arrival:= -24.364 -0.964 + + Clock Gating Hold:+ -8.255 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 67.382 + Launch Clock:= -0.964 + Data Path:+ 85.100 + Slack:= 16.755 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 21.200 | -0.964 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[8]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 5 | 26.800 | 28.600 | 27.636 | + | cpu/stage3_inst[8] | | | R | (net) | 5 | | | | + | cpu/FE_PHC3511_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SRAM | 2 | 6.800 | 15.000 | 42.636 | + | cpu/FE_PHN3511_stage3_inst_8 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 8 | 13.700 | 30.000 | 72.636 | + | cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 | | | R | (net) | 8 | | | | + | cpu/stage1/regfile/g79802/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 54.300 | 4.100 | 76.736 | + | cpu/stage1/regfile/n_350 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g77353/Y | | A2->Y | R | OAI31xp33_ASAP7_75t_SL | 1 | 12.300 | 7.400 | 84.136 | + | cpu/stage1/regfile/n_2211 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CG | | ENA | R | ICGx1_ASAP7_75t_SL | 1 | 12.300 | 0.000 | 84.136 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 25.500 | -24.364 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 30.300 | 4.800 | -24.364 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 16: MET (16.805 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 62.300 (P) 82.600 (P) + Arrival:= -21.564 -1.264 + + Clock Gating Hold:+ -5.705 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 72.732 + Launch Clock:= -1.264 + Data Path:+ 90.800 + Slack:= 16.805 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77628/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 14.900 | 83.136 | + | cpu/stage1/regfile/n_1701 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77157/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 20.400 | 6.400 | 89.536 | + | cpu/stage1/regfile/n_2191 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 12.300 | 0.100 | 89.536 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 28.300 | -21.564 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 31.300 | 7.600 | -21.564 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 17: MET (17.487 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 63.100 (P) 82.600 (P) + Arrival:= -20.764 -1.264 + + Clock Gating Hold:+ -6.187 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 73.049 + Launch Clock:= -1.264 + Data Path:+ 91.800 + Slack:= 17.487 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 25.900 | 24.636 | + | cpu/stage3_inst[11] | | | R | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 2 | 16.300 | 24.000 | 48.636 | + | cpu/FE_PHN2611_stage3_inst_11 | | | R | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 15.300 | 4.100 | 52.736 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | F | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 10 | 7.700 | 15.300 | 68.036 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | R | (net) | 10 | | | | + | cpu/stage1/regfile/g80395/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 7 | 28.000 | 13.900 | 81.936 | + | cpu/stage1/regfile/n_248 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g77357/Y | | A2->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 12.100 | 8.600 | 90.536 | + | cpu/stage1/regfile/n_2215 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 15.000 | 0.200 | 90.536 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 29.100 | -20.764 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 31.400 | 8.400 | -20.764 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 18: MET (17.593 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 61.400 (P) 82.600 (P) + Arrival:= -22.464 -1.264 + + Clock Gating Hold:+ -5.293 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 72.243 + Launch Clock:= -1.264 + Data Path:+ 91.100 + Slack:= 17.593 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77628/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 14.900 | 83.136 | + | cpu/stage1/regfile/n_1701 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77200/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 20.400 | 6.700 | 89.836 | + | cpu/stage1/regfile/n_2199 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 10.200 | 0.100 | 89.836 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 27.400 | -22.464 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 31.200 | 6.700 | -22.464 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 19: MET (17.681 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 59.800 (P) 82.600 (P) + Arrival:= -24.064 -1.264 + + Clock Gating Hold:+ -5.081 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 70.855 + Launch Clock:= -1.264 + Data Path:+ 89.800 + Slack:= 17.681 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77626/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 15.000 | 83.236 | + | cpu/stage1/regfile/n_1703 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77198/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 19.000 | 5.300 | 88.536 | + | cpu/stage1/regfile/n_2192 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 10.400 | 0.100 | 88.536 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 25.800 | -24.064 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 29.400 | 5.100 | -24.064 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 20: MET (18.265 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 58.500 (P) 82.900 (P) + Arrival:= -25.364 -0.964 + + Clock Gating Hold:+ -8.865 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 65.771 + Launch Clock:= -0.964 + Data Path:+ 85.000 + Slack:= 18.265 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 21.200 | -0.964 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[8]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 5 | 26.800 | 28.600 | 27.636 | + | cpu/stage3_inst[8] | | | R | (net) | 5 | | | | + | cpu/FE_PHC3511_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SRAM | 2 | 6.800 | 15.000 | 42.636 | + | cpu/FE_PHN3511_stage3_inst_8 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 8 | 13.700 | 29.900 | 72.536 | + | cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 | | | R | (net) | 8 | | | | + | cpu/stage1/regfile/g79352/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 54.300 | 1.800 | 74.336 | + | cpu/stage1/regfile/n_265 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77254/Y | | A2->Y | R | OAI31xp33_ASAP7_75t_SL | 1 | 11.100 | 9.700 | 84.036 | + | cpu/stage1/regfile/n_2207 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CG | | ENA | R | ICGx1_ASAP7_75t_SL | 1 | 17.700 | 0.100 | 84.036 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 26.700 | -25.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 4 | 31.200 | 3.200 | -25.364 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 21: MET (18.530 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 58.700 (P) 82.600 (P) + Arrival:= -25.164 -1.264 + + Clock Gating Hold:+ -4.930 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 69.906 + Launch Clock:= -1.264 + Data Path:+ 89.700 + Slack:= 18.530 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77626/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 14.800 | 83.036 | + | cpu/stage1/regfile/n_1703 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77179/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 19.000 | 5.400 | 88.436 | + | cpu/stage1/regfile/n_2200 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 9.400 | 0.100 | 88.436 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 24.700 | -25.164 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 29.700 | 4.000 | -25.164 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 22: MET (18.864 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 59.400 (P) 82.600 (P) + Arrival:= -24.464 -1.264 + + Clock Gating Hold:+ -5.064 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 70.473 + Launch Clock:= -1.264 + Data Path:+ 90.600 + Slack:= 18.864 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77628/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 15.000 | 83.236 | + | cpu/stage1/regfile/n_1701 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77201/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 20.400 | 6.100 | 89.336 | + | cpu/stage1/regfile/n_2201 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 10.300 | 0.100 | 89.336 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 25.400 | -24.464 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 29.400 | 4.700 | -24.464 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 23: MET (18.912 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 59.500 (P) 82.600 (P) + Arrival:= -24.364 -1.264 + + Clock Gating Hold:+ -5.312 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 70.324 + Launch Clock:= -1.264 + Data Path:+ 90.500 + Slack:= 18.912 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77628/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 15.000 | 83.236 | + | cpu/stage1/regfile/n_1701 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77161/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 20.400 | 6.000 | 89.236 | + | cpu/stage1/regfile/n_2193 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 11.600 | 0.100 | 89.236 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 25.500 | -24.364 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 29.400 | 4.800 | -24.364 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 24: MET (19.998 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 60.200 (P) 82.900 (P) + Arrival:= -23.664 -0.964 + + Clock Gating Hold:+ -8.598 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 67.738 + Launch Clock:= -0.964 + Data Path:+ 88.700 + Slack:= 19.998 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 21.200 | -0.964 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[8]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 5 | 26.800 | 28.600 | 27.636 | + | cpu/stage3_inst[8] | | | R | (net) | 5 | | | | + | cpu/FE_PHC3511_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SRAM | 2 | 6.800 | 15.000 | 42.636 | + | cpu/FE_PHN3511_stage3_inst_8 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 8 | 13.700 | 29.900 | 72.536 | + | cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 | | | R | (net) | 8 | | | | + | cpu/stage1/regfile/g79796/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 54.300 | 5.000 | 77.536 | + | cpu/stage1/regfile/n_353 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g77362/Y | | A2->Y | R | OAI31xp33_ASAP7_75t_SL | 1 | 9.600 | 10.200 | 87.736 | + | cpu/stage1/regfile/n_2206 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CG | | ENA | R | ICGx1_ASAP7_75t_SL | 1 | 19.000 | 0.200 | 87.736 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 26.200 | -23.664 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 29.500 | 5.500 | -23.664 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 25: MET (20.697 ps) Clock Gating Hold Check with Pin mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 63.500 (P) 78.300 (P) + Arrival:= -20.364 -5.564 + + Clock Gating Hold:+ -9.797 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 69.839 + Launch Clock:= -5.564 + Data Path:+ 96.100 + Slack:= 20.697 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 22.600 | -5.564 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[5]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 5 | 32.100 | 28.600 | 23.036 | + | cpu/stage2_inst[5] | | | R | (net) | 5 | | | | + | cpu/FE_OFC847_stage2_inst_5/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 12 | 20.100 | 16.300 | 39.336 | + | cpu/FE_OFN978_stage2_inst_5 | | | R | (net) | 12 | | | | + | cpu/stage3/g62/Y | | D->Y | F | NOR4xp25_ASAP7_75t_SL | 1 | 18.400 | 8.800 | 48.136 | + | dcache_re | | | F | (net) | 1 | | | | + | mem/g31/Y | | E->Y | F | OR5x1_ASAP7_75t_SL | 3 | 9.000 | 27.300 | 75.436 | + | mem/n_317 | | | F | (net) | 3 | | | | + | mem/dcache/g13992/Y | | A2->Y | R | OAI21xp5_ASAP7_75t_SL | 1 | 26.200 | 8.400 | 83.836 | + | mem/dcache/n_101 | | | R | (net) | 1 | | | | + | mem/dcache/g13600/Y | | A2->Y | F | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 6.400 | 6.700 | 90.536 | + | mem/dcache/n_323 | | | F | (net) | 1 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | ENA | F | ICGx1_ASAP7_75t_SRAM | 1 | 7.500 | 0.100 | 90.536 | + | ENA | | | | | | | | | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 20.500 | -20.364 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 23.000 | 2.900 | -20.364 | + | CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 26: MET (21.273 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[4]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 57.900 (P) 82.700 (P) + Arrival:= -25.964 -1.164 + + Clock Gating Hold:+ -8.073 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 65.963 + Launch Clock:= -1.164 + Data Path:+ 88.400 + Slack:= 21.273 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 21.000 | -1.164 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[4]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 6 | 26.900 | 30.000 | 28.836 | + | cpu/stage3_inst[4] | | | R | (net) | 6 | | | | + | cpu/stage1/regwen/g90/Y | | D->Y | R | OR5x1_ASAP7_75t_SL | 1 | 8.200 | 16.500 | 45.336 | + | cpu/stage1/RegWEnSelect | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g78085/Y | | B->Y | F | OAI31xp33_ASAP7_75t_SL | 16 | 19.500 | 28.800 | 74.136 | + | cpu/stage1/regfile/n_1318 | | | F | (net) | 16 | | | | + | cpu/stage1/regfile/g77249/Y | | A2->Y | R | OAI21xp5_ASAP7_75t_SL | 1 | 55.600 | 13.100 | 87.236 | + | cpu/stage1/regfile/n_2208 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CG | | ENA | R | ICGx1_ASAP7_75t_SL | 1 | 10.800 | 0.100 | 87.236 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 23.900 | -25.964 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 29.000 | 3.200 | -25.964 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 27: MET (23.060 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 57.400 (P) 82.600 (P) + Arrival:= -26.464 -1.264 + + Clock Gating Hold:+ -7.160 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 66.377 + Launch Clock:= -1.264 + Data Path:+ 90.700 + Slack:= 23.060 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77627/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 15.200 | 83.436 | + | cpu/stage1/regfile/n_1702 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77178/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 19.500 | 6.000 | 89.436 | + | cpu/stage1/regfile/n_2194 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 9.300 | 0.100 | 89.436 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 30.400 | -26.464 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 42.700 | 14.800 | -26.464 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 28: MET (23.658 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 56.600 (P) 82.900 (P) + Arrival:= -27.264 -0.964 + + Clock Gating Hold:+ -8.558 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 64.179 + Launch Clock:= -0.964 + Data Path:+ 88.800 + Slack:= 23.658 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 21.200 | -0.964 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[8]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 5 | 26.800 | 28.600 | 27.636 | + | cpu/stage3_inst[8] | | | R | (net) | 5 | | | | + | cpu/FE_PHC3511_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SRAM | 2 | 6.800 | 15.000 | 42.636 | + | cpu/FE_PHN3511_stage3_inst_8 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 8 | 13.700 | 29.900 | 72.536 | + | cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 | | | R | (net) | 8 | | | | + | cpu/stage1/regfile/g79798/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 54.300 | 4.300 | 76.836 | + | cpu/stage1/regfile/n_351 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g77360/Y | | A2->Y | R | OAI31xp33_ASAP7_75t_SL | 1 | 8.700 | 11.000 | 87.836 | + | cpu/stage1/regfile/n_2210 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CG | | ENA | R | ICGx1_ASAP7_75t_SL | 1 | 20.700 | 0.300 | 87.836 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 22.600 | -27.264 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 27.900 | 1.900 | -27.264 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 29: MET (25.122 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 56.100 (P) 82.900 (P) + Arrival:= -27.764 -0.964 + + Clock Gating Hold:+ -10.022 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 62.215 + Launch Clock:= -0.964 + Data Path:+ 88.300 + Slack:= 25.122 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 21.200 | -0.964 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[8]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 5 | 26.800 | 28.600 | 27.636 | + | cpu/stage3_inst[8] | | | R | (net) | 5 | | | | + | cpu/FE_PHC3511_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SRAM | 2 | 6.800 | 15.000 | 42.636 | + | cpu/FE_PHN3511_stage3_inst_8 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 8 | 13.700 | 30.000 | 72.636 | + | cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 | | | R | (net) | 8 | | | | + | cpu/stage1/regfile/g79802/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 54.300 | 4.100 | 76.736 | + | cpu/stage1/regfile/n_350 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g77348/Y | | A2->Y | R | OAI31xp33_ASAP7_75t_SL | 1 | 12.300 | 10.600 | 87.336 | + | cpu/stage1/regfile/n_2203 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CG | | ENA | R | ICGx1_ASAP7_75t_SL | 1 | 19.600 | 0.200 | 87.336 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 29.100 | -27.764 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 42.600 | 13.500 | -27.764 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 30: MET (25.668 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 56.800 (P) 82.600 (P) + Arrival:= -27.064 -1.264 + + Clock Gating Hold:+ -7.968 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 64.968 + Launch Clock:= -1.264 + Data Path:+ 91.900 + Slack:= 25.668 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 20.900 | -1.264 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 4 | 26.800 | 24.800 | 23.536 | + | cpu/stage3_inst[11] | | | F | (net) | 4 | | | | + | cpu/FE_PHC2611_stage3_inst_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SRAM | 2 | 15.200 | 25.300 | 48.836 | + | cpu/FE_PHN2611_stage3_inst_11 | | | F | (net) | 2 | | | | + | cpu/stage1/FE_OFC866_stage3_inst_11/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 14.100 | 5.100 | 53.936 | + | cpu/stage1/FE_OFN997_stage3_inst_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC867_stage3_inst_11/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 10 | 8.000 | 14.300 | 68.236 | + | cpu/stage1/FE_OFN998_stage3_inst_11 | | | F | (net) | 10 | | | | + | cpu/stage1/regfile/g77625/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 26.200 | 15.200 | 83.436 | + | cpu/stage1/regfile/n_1704 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77162/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 21.000 | 7.200 | 90.636 | + | cpu/stage1/regfile/n_2189 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 13.300 | 0.200 | 90.636 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 29.800 | -27.064 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 42.700 | 14.200 | -27.064 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 31: MET (26.705 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[4]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 58.400 (P) 82.700 (P) + Arrival:= -25.464 -1.164 + + Clock Gating Hold:+ -6.105 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 68.431 + Launch Clock:= -1.164 + Data Path:+ 96.300 + Slack:= 26.705 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 21.000 | -1.164 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[4]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 6 | 26.900 | 30.500 | 29.336 | + | cpu/stage3_inst[4] | | | F | (net) | 6 | | | | + | cpu/stage1/regwen/g90/Y | | D->Y | F | OR5x1_ASAP7_75t_SL | 1 | 7.700 | 24.000 | 53.336 | + | cpu/stage1/RegWEnSelect | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g78085/Y | | B->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 20.100 | 32.500 | 85.836 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77259/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 63.300 | 9.300 | 95.136 | + | cpu/stage1/regfile/n_2209 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 16.300 | 0.300 | 95.136 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 24.400 | -25.464 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 16 | 29.200 | 3.700 | -25.464 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 32: MET (27.062 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[4]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 57.000 (P) 82.700 (P) + Arrival:= -26.864 -1.164 + + Clock Gating Hold:+ -7.862 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 65.274 + Launch Clock:= -1.164 + Data Path:+ 93.500 + Slack:= 27.062 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 21.000 | -1.164 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[4]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 6 | 26.900 | 30.500 | 29.336 | + | cpu/stage3_inst[4] | | | F | (net) | 6 | | | | + | cpu/stage1/regwen/g90/Y | | D->Y | F | OR5x1_ASAP7_75t_SL | 1 | 7.700 | 24.000 | 53.336 | + | cpu/stage1/RegWEnSelect | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g78085/Y | | B->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 20.100 | 32.400 | 85.736 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77355/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 63.300 | 6.600 | 92.336 | + | cpu/stage1/regfile/n_2205 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 12.700 | 0.100 | 92.336 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 30.000 | -26.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 42.700 | 14.400 | -26.864 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 33: MET (27.362 ps) Clock Gating Hold Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[4]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 57.100 (P) 82.700 (P) + Arrival:= -26.764 -1.164 + + Clock Gating Hold:+ -7.862 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 65.374 + Launch Clock:= -1.164 + Data Path:+ 93.900 + Slack:= 27.362 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 26.200 | -27.864 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.200 | 5.700 | -22.164 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 4.000 | 21.000 | -1.164 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[4]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 6 | 26.900 | 30.500 | 29.336 | + | cpu/stage3_inst[4] | | | F | (net) | 6 | | | | + | cpu/stage1/regwen/g90/Y | | D->Y | F | OR5x1_ASAP7_75t_SL | 1 | 7.700 | 24.000 | 53.336 | + | cpu/stage1/RegWEnSelect | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g78085/Y | | B->Y | R | OAI31xp33_ASAP7_75t_SL | 16 | 20.100 | 32.500 | 85.836 | + | cpu/stage1/regfile/n_1318 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/g77356/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 1 | 63.300 | 6.900 | 92.736 | + | cpu/stage1/regfile/n_2204 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CG | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 12.700 | 0.100 | 92.736 | + | IC_INST/ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 30.100 | -26.764 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CG | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 42.700 | 14.500 | -26.764 | + | IC_INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 34: MET (61.742 ps) Clock Gating Hold Check with Pin mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) mem/icache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 60.900 (P) 71.200 (P) + Arrival:= -22.964 -12.664 + + Clock Gating Hold:+ -10.242 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 66.794 + Launch Clock:= -12.664 + Data Path:+ 141.200 + Slack:= 61.742 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 15.200 | -43.364 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 9.100 | 16.300 | -27.064 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 17.400 | 14.400 | -12.664 | + | GCLK | | | | | | | | | + | mem/icache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/icache/STATE_reg[2]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 10.700 | 19.700 | 7.036 | + | mem/icache/STATE[2] | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC3415_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.500 | 28.000 | 35.036 | + | mem/icache/FE_PHN3415_STATE_2 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC2593_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 12.400 | 32.200 | 67.236 | + | mem/icache/FE_PHN2593_STATE_2 | | | R | (net) | 3 | | | | + | mem/icache/g9080/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 3 | 17.600 | 6.100 | 73.336 | + | mem/icache/n_103 | | | F | (net) | 3 | | | | + | mem/icache/g8876/Y | | A3->Y | R | AOI31xp33_ASAP7_75t_SL | 1 | 11.600 | 9.100 | 82.436 | + | mem/icache/n_172 | | | R | (net) | 1 | | | | + | mem/icache/g8874/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 11.400 | 3.000 | 85.436 | + | mem/icache/n_173 | | | F | (net) | 1 | | | | + | mem/icache/g8837/Y | | B->Y | F | OA21x2_ASAP7_75t_SL | 1 | 5.500 | 6.700 | 92.136 | + | mem/icache/n_5234_BAR | | | F | (net) | 1 | | | | + | mem/icache/g6622/Y | | B->Y | R | OAI21xp5_ASAP7_75t_SL | 1 | 4.000 | 3.600 | 95.736 | + | mem/icache/n_216 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC2687_n_216/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 5.600 | 28.700 | 124.436 | + | mem/icache/FE_PHN2687_n_216 | | | R | (net) | 2 | | | | + | mem/icache/g6621/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 14.300 | 4.100 | 128.536 | + | mem/icache/n_214 | | | F | (net) | 1 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | ENA | F | ICGx1_ASAP7_75t_SRAM | 1 | 8.300 | 0.000 | 128.536 | + | ENA | | | | | | | | | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 16.000 | -40.864 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 10.200 | 17.900 | -22.964 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 21.400 | 0.300 | -22.964 | + | CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 35: MET (87.698 ps) Clock Gating Hold Check with Pin cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) mem/icache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 56.000 (P) 71.200 (P) + Arrival:= -27.864 -12.664 + + Clock Gating Hold:+ -8.798 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 63.338 + Launch Clock:= -12.664 + Data Path:+ 163.700 + Slack:= 87.698 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 15.200 | -43.364 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 9.100 | 16.300 | -27.064 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 17.400 | 14.400 | -12.664 | + | GCLK | | | | | | | | | + | mem/icache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/icache/STATE_reg[2]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 10.700 | 19.700 | 7.036 | + | mem/icache/STATE[2] | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC3415_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.500 | 28.000 | 35.036 | + | mem/icache/FE_PHN3415_STATE_2 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC2593_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 12.400 | 32.200 | 67.236 | + | mem/icache/FE_PHN2593_STATE_2 | | | R | (net) | 3 | | | | + | mem/icache/g9105/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 17.600 | 3.600 | 70.836 | + | mem/icache/n_82 | | | F | (net) | 2 | | | | + | mem/icache/g9081/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 2 | 7.500 | 6.000 | 76.836 | + | mem/icache/n_101 | | | R | (net) | 2 | | | | + | mem/icache/g9061/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 9.300 | 4.800 | 81.636 | + | mem/icache/n_127 | | | F | (net) | 2 | | | | + | mem/icache/g9051/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 9.300 | 4.100 | 85.736 | + | mem/icache/n_128 | | | R | (net) | 2 | | | | + | mem/icache/g9032/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 6.200 | 8.000 | 93.736 | + | mem/i_stall_n | | | R | (net) | 1 | | | | + | mem/g20/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 41 | 4.300 | 43.200 | 136.936 | + | stall | | | F | (net) | 41 | | | | + | cpu/s2_to_s3_alu/g213__7410/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 105.900 | 14.100 | 151.036 | + | cpu/s2_to_s3_alu/n_34 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | ENA | R | ICGx3_ASAP7_75t_SL | 1 | 30.500 | 0.100 | 151.036 | + | INST/ENA | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK | R | ICGx3_ASAP7_75t_SL | 6 | 24.800 | 2.600 | -27.864 | + | INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 36: MET (87.864 ps) Clock Gating Hold Check with Pin cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) mem/icache/STATE_reg[1]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 54.500 (P) 71.200 (P) + Arrival:= -29.364 -12.664 + + Clock Gating Hold:+ -7.664 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 62.973 + Launch Clock:= -12.664 + Data Path:+ 163.500 + Slack:= 87.864 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 15.200 | -43.364 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 9.100 | 16.300 | -27.064 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 17.400 | 14.400 | -12.664 | + | GCLK | | | | | | | | | + | mem/icache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/icache/STATE_reg[1]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 10.700 | 19.600 | 6.936 | + | mem/icache/STATE[1] | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC3419_STATE_1/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.300 | 27.200 | 34.136 | + | mem/icache/FE_PHN3419_STATE_1 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC2592_STATE_1/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 11.300 | 32.800 | 66.936 | + | mem/icache/FE_PHN2592_STATE_1 | | | R | (net) | 3 | | | | + | mem/icache/g9081/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 18.900 | 5.500 | 72.436 | + | mem/icache/n_101 | | | F | (net) | 2 | | | | + | mem/icache/g9061/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 2 | 10.100 | 6.600 | 79.036 | + | mem/icache/n_127 | | | R | (net) | 2 | | | | + | mem/icache/g9051/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 9.300 | 3.400 | 82.436 | + | mem/icache/n_128 | | | F | (net) | 2 | | | | + | mem/icache/g9032/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 5.700 | 7.600 | 90.036 | + | mem/i_stall_n | | | F | (net) | 1 | | | | + | mem/g20/Y | | B->Y | R | NAND2x1_ASAP7_75t_SL | 41 | 4.000 | 52.300 | 142.336 | + | stall | | | R | (net) | 41 | | | | + | cpu/stage1/pcreg/g189__5107/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 129.100 | 8.500 | 150.836 | + | cpu/stage1/pcreg/n_35 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 27.400 | 0.200 | 150.836 | + | INST/ENA | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK | R | ICGx1_ASAP7_75t_SL | 6 | 24.000 | 1.100 | -29.364 | + | INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 37: MET (88.083 ps) Clock Gating Hold Check with Pin cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) mem/icache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 61.500 (P) 71.200 (P) + Arrival:= -22.364 -12.664 + + Clock Gating Hold:+ -9.483 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 68.153 + Launch Clock:= -12.664 + Data Path:+ 168.900 + Slack:= 88.083 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 15.200 | -43.364 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 9.100 | 16.300 | -27.064 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 17.400 | 14.400 | -12.664 | + | GCLK | | | | | | | | | + | mem/icache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/icache/STATE_reg[2]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 10.700 | 19.700 | 7.036 | + | mem/icache/STATE[2] | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC3415_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.500 | 28.000 | 35.036 | + | mem/icache/FE_PHN3415_STATE_2 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC2593_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 12.400 | 32.200 | 67.236 | + | mem/icache/FE_PHN2593_STATE_2 | | | R | (net) | 3 | | | | + | mem/icache/g9105/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 17.600 | 3.600 | 70.836 | + | mem/icache/n_82 | | | F | (net) | 2 | | | | + | mem/icache/g9081/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 2 | 7.500 | 6.000 | 76.836 | + | mem/icache/n_101 | | | R | (net) | 2 | | | | + | mem/icache/g9061/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 9.300 | 4.800 | 81.636 | + | mem/icache/n_127 | | | F | (net) | 2 | | | | + | mem/icache/g9051/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 9.300 | 4.100 | 85.736 | + | mem/icache/n_128 | | | R | (net) | 2 | | | | + | mem/icache/g9032/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 6.200 | 8.000 | 93.736 | + | mem/i_stall_n | | | R | (net) | 1 | | | | + | mem/g20/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 41 | 4.300 | 49.300 | 143.036 | + | stall | | | F | (net) | 41 | | | | + | cpu/s1_to_s2_inst/g261__5122/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 106.900 | 13.200 | 156.236 | + | cpu/s1_to_s2_inst/n_34 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | ENA | R | ICGx3_ASAP7_75t_SL | 1 | 29.800 | 0.000 | 156.236 | + | _INST/ENA | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 29.700 | -22.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK | R | ICGx3_ASAP7_75t_SL | 4 | 33.200 | 6.200 | -22.364 | + | _INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 38: MET (88.531 ps) Clock Gating Hold Check with Pin cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) mem/icache/STATE_reg[1]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 61.900 (P) 71.200 (P) + Arrival:= -21.964 -12.664 + + Clock Gating Hold:+ -8.031 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 70.006 + Launch Clock:= -12.664 + Data Path:+ 171.200 + Slack:= 88.531 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 15.200 | -43.364 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 9.100 | 16.300 | -27.064 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 17.400 | 14.400 | -12.664 | + | GCLK | | | | | | | | | + | mem/icache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/icache/STATE_reg[1]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 10.700 | 19.600 | 6.936 | + | mem/icache/STATE[1] | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC3419_STATE_1/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.300 | 27.200 | 34.136 | + | mem/icache/FE_PHN3419_STATE_1 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC2592_STATE_1/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 11.300 | 32.800 | 66.936 | + | mem/icache/FE_PHN2592_STATE_1 | | | R | (net) | 3 | | | | + | mem/icache/g9081/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 18.900 | 5.500 | 72.436 | + | mem/icache/n_101 | | | F | (net) | 2 | | | | + | mem/icache/g9061/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 2 | 10.100 | 6.600 | 79.036 | + | mem/icache/n_127 | | | R | (net) | 2 | | | | + | mem/icache/g9051/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 9.300 | 3.400 | 82.436 | + | mem/icache/n_128 | | | F | (net) | 2 | | | | + | mem/icache/g9032/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 5.700 | 7.600 | 90.036 | + | mem/i_stall_n | | | F | (net) | 1 | | | | + | mem/g20/Y | | B->Y | R | NAND2x1_ASAP7_75t_SL | 41 | 4.000 | 61.300 | 151.336 | + | stall | | | R | (net) | 41 | | | | + | cpu/s2_to_s3_inst/g128__6260/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 130.500 | 7.200 | 158.536 | + | cpu/s2_to_s3_inst/n_19 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | ENA | F | ICGx1_ASAP7_75t_SL | 1 | 22.300 | 0.100 | 158.536 | + | _INST/ENA | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 30.100 | -21.964 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK | R | ICGx1_ASAP7_75t_SL | 4 | 33.200 | 6.600 | -21.964 | + | _INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 39: MET (89.847 ps) Clock Gating Hold Check with Pin cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) mem/icache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 57.400 (P) 71.200 (P) + Arrival:= -26.464 -12.664 + + Clock Gating Hold:+ -8.847 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 64.689 + Launch Clock:= -12.664 + Data Path:+ 167.200 + Slack:= 89.847 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 15.200 | -43.364 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 9.100 | 16.300 | -27.064 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 17.400 | 14.400 | -12.664 | + | GCLK | | | | | | | | | + | mem/icache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/icache/STATE_reg[2]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 10.700 | 19.700 | 7.036 | + | mem/icache/STATE[2] | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC3415_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.500 | 28.000 | 35.036 | + | mem/icache/FE_PHN3415_STATE_2 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC2593_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 12.400 | 32.200 | 67.236 | + | mem/icache/FE_PHN2593_STATE_2 | | | R | (net) | 3 | | | | + | mem/icache/g9105/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 17.600 | 3.600 | 70.836 | + | mem/icache/n_82 | | | F | (net) | 2 | | | | + | mem/icache/g9081/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 2 | 7.500 | 6.000 | 76.836 | + | mem/icache/n_101 | | | R | (net) | 2 | | | | + | mem/icache/g9061/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 9.300 | 4.800 | 81.636 | + | mem/icache/n_127 | | | F | (net) | 2 | | | | + | mem/icache/g9051/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 9.300 | 4.100 | 85.736 | + | mem/icache/n_128 | | | R | (net) | 2 | | | | + | mem/icache/g9032/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 6.200 | 8.000 | 93.736 | + | mem/i_stall_n | | | R | (net) | 1 | | | | + | mem/g20/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 41 | 4.300 | 46.400 | 140.136 | + | stall | | | F | (net) | 41 | | | | + | cpu/s1_to_s2_imm/g213__2398/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 106.400 | 14.400 | 154.536 | + | cpu/s1_to_s2_imm/n_34 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_ | | ENA | R | ICGx3_ASAP7_75t_SL | 1 | 30.900 | 0.100 | 154.536 | + | INST/ENA | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.100 | -26.464 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_ | | CLK | R | ICGx3_ASAP7_75t_SL | 6 | 25.100 | 4.000 | -26.464 | + | INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 40: MET (91.320 ps) Clock Gating Hold Check with Pin cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) mem/icache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 57.300 (P) 71.200 (P) + Arrival:= -26.564 -12.664 + + Clock Gating Hold:+ -8.920 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 64.516 + Launch Clock:= -12.664 + Data Path:+ 168.500 + Slack:= 91.320 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 15.200 | -43.364 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 9.100 | 16.300 | -27.064 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 17.400 | 14.400 | -12.664 | + | GCLK | | | | | | | | | + | mem/icache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/icache/STATE_reg[2]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 10.700 | 19.700 | 7.036 | + | mem/icache/STATE[2] | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC3415_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.500 | 28.000 | 35.036 | + | mem/icache/FE_PHN3415_STATE_2 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC2593_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 12.400 | 32.200 | 67.236 | + | mem/icache/FE_PHN2593_STATE_2 | | | R | (net) | 3 | | | | + | mem/icache/g9105/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 17.600 | 3.600 | 70.836 | + | mem/icache/n_82 | | | F | (net) | 2 | | | | + | mem/icache/g9081/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 2 | 7.500 | 6.000 | 76.836 | + | mem/icache/n_101 | | | R | (net) | 2 | | | | + | mem/icache/g9061/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 9.300 | 4.800 | 81.636 | + | mem/icache/n_127 | | | F | (net) | 2 | | | | + | mem/icache/g9051/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 9.300 | 4.100 | 85.736 | + | mem/icache/n_128 | | | R | (net) | 2 | | | | + | mem/icache/g9032/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 6.200 | 8.000 | 93.736 | + | mem/i_stall_n | | | R | (net) | 1 | | | | + | mem/g20/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 41 | 4.300 | 46.400 | 140.136 | + | stall | | | F | (net) | 41 | | | | + | cpu/s2_to_s3_pc/g213__4733/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 106.400 | 15.700 | 155.836 | + | cpu/s2_to_s3_pc/n_34 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | ENA | R | ICGx3_ASAP7_75t_SL | 1 | 32.400 | 0.100 | 155.836 | + | NST/ENA | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.000 | -26.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK | R | ICGx3_ASAP7_75t_SL | 6 | 25.100 | 3.900 | -26.564 | + | NST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 41: MET (91.440 ps) Clock Gating Hold Check with Pin cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) mem/icache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 56.300 (P) 71.200 (P) + Arrival:= -27.564 -12.664 + + Clock Gating Hold:+ -9.340 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 63.096 + Launch Clock:= -12.664 + Data Path:+ 167.200 + Slack:= 91.440 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 15.200 | -43.364 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 9.100 | 16.300 | -27.064 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 17.400 | 14.400 | -12.664 | + | GCLK | | | | | | | | | + | mem/icache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/icache/STATE_reg[2]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 10.700 | 19.700 | 7.036 | + | mem/icache/STATE[2] | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC3415_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.500 | 28.000 | 35.036 | + | mem/icache/FE_PHN3415_STATE_2 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC2593_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 12.400 | 32.200 | 67.236 | + | mem/icache/FE_PHN2593_STATE_2 | | | R | (net) | 3 | | | | + | mem/icache/g9105/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 17.600 | 3.600 | 70.836 | + | mem/icache/n_82 | | | F | (net) | 2 | | | | + | mem/icache/g9081/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 2 | 7.500 | 6.000 | 76.836 | + | mem/icache/n_101 | | | R | (net) | 2 | | | | + | mem/icache/g9061/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 9.300 | 4.800 | 81.636 | + | mem/icache/n_127 | | | F | (net) | 2 | | | | + | mem/icache/g9051/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 9.300 | 4.100 | 85.736 | + | mem/icache/n_128 | | | R | (net) | 2 | | | | + | mem/icache/g9032/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 6.200 | 8.000 | 93.736 | + | mem/i_stall_n | | | R | (net) | 1 | | | | + | mem/g20/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 41 | 4.300 | 46.500 | 140.236 | + | stall | | | F | (net) | 41 | | | | + | cpu/s1_to_s2_rs2/g213__9315/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 106.500 | 14.300 | 154.536 | + | cpu/s1_to_s2_rs2/n_34 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | ENA | R | ICGx3_ASAP7_75t_SL | 1 | 30.800 | 0.100 | 154.536 | + | INST/ENA | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK | R | ICGx3_ASAP7_75t_SL | 4 | 30.500 | 1.000 | -27.564 | + | INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 42: MET (91.715 ps) Clock Gating Hold Check with Pin cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) mem/icache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 56.800 (P) 71.200 (P) + Arrival:= -27.064 -12.664 + + Clock Gating Hold:+ -8.915 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 64.021 + Launch Clock:= -12.664 + Data Path:+ 168.400 + Slack:= 91.715 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 15.200 | -43.364 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 9.100 | 16.300 | -27.064 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 17.400 | 14.400 | -12.664 | + | GCLK | | | | | | | | | + | mem/icache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/icache/STATE_reg[2]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 10.700 | 19.700 | 7.036 | + | mem/icache/STATE[2] | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC3415_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.500 | 28.000 | 35.036 | + | mem/icache/FE_PHN3415_STATE_2 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC2593_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 12.400 | 32.200 | 67.236 | + | mem/icache/FE_PHN2593_STATE_2 | | | R | (net) | 3 | | | | + | mem/icache/g9105/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 17.600 | 3.600 | 70.836 | + | mem/icache/n_82 | | | F | (net) | 2 | | | | + | mem/icache/g9081/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 2 | 7.500 | 6.000 | 76.836 | + | mem/icache/n_101 | | | R | (net) | 2 | | | | + | mem/icache/g9061/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 9.300 | 4.800 | 81.636 | + | mem/icache/n_127 | | | F | (net) | 2 | | | | + | mem/icache/g9051/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 9.300 | 4.100 | 85.736 | + | mem/icache/n_128 | | | R | (net) | 2 | | | | + | mem/icache/g9032/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 6.200 | 8.000 | 93.736 | + | mem/i_stall_n | | | R | (net) | 1 | | | | + | mem/g20/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 41 | 4.300 | 46.300 | 140.036 | + | stall | | | F | (net) | 41 | | | | + | cpu/s1_to_s2_rs1/g213__1881/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 106.400 | 15.700 | 155.736 | + | cpu/s1_to_s2_rs1/n_34 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_ | | ENA | R | ICGx3_ASAP7_75t_SL | 1 | 32.300 | 0.100 | 155.736 | + | INST/ENA | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 27.500 | -27.064 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_ | | CLK | R | ICGx3_ASAP7_75t_SL | 6 | 25.100 | 3.400 | -27.064 | + | INST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ +Path 43: MET (93.374 ps) Clock Gating Hold Check with Pin cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_INST/CLK->ENA + View: PVT_0P77V_0C.hold_view + Group: reg2cgate + Startpoint: (R) mem/icache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 56.500 (P) 71.200 (P) + Arrival:= -27.364 -12.664 + + Clock Gating Hold:+ -8.974 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 63.662 + Launch Clock:= -12.664 + Data Path:+ 169.700 + Slack:= 93.374 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 15.200 | -43.364 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 9.100 | 16.300 | -27.064 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 17.400 | 14.400 | -12.664 | + | GCLK | | | | | | | | | + | mem/icache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/icache/STATE_reg[2]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 10.700 | 19.700 | 7.036 | + | mem/icache/STATE[2] | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC3415_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.500 | 28.000 | 35.036 | + | mem/icache/FE_PHN3415_STATE_2 | | | R | (net) | 1 | | | | + | mem/icache/FE_PHC2593_STATE_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 12.400 | 32.200 | 67.236 | + | mem/icache/FE_PHN2593_STATE_2 | | | R | (net) | 3 | | | | + | mem/icache/g9105/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 17.600 | 3.600 | 70.836 | + | mem/icache/n_82 | | | F | (net) | 2 | | | | + | mem/icache/g9081/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 2 | 7.500 | 6.000 | 76.836 | + | mem/icache/n_101 | | | R | (net) | 2 | | | | + | mem/icache/g9061/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 9.300 | 4.800 | 81.636 | + | mem/icache/n_127 | | | F | (net) | 2 | | | | + | mem/icache/g9051/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 9.300 | 4.100 | 85.736 | + | mem/icache/n_128 | | | R | (net) | 2 | | | | + | mem/icache/g9032/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 6.200 | 8.000 | 93.736 | + | mem/i_stall_n | | | R | (net) | 1 | | | | + | mem/g20/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 41 | 4.300 | 46.400 | 140.136 | + | stall | | | F | (net) | 41 | | | | + | cpu/s1_to_s2_pc/g213__1705/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 106.400 | 16.900 | 157.036 | + | cpu/s1_to_s2_pc/n_34 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | ENA | R | ICGx3_ASAP7_75t_SL | 1 | 33.800 | 0.100 | 157.036 | + | NST/ENA | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +----------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 27.200 | -27.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK | R | ICGx3_ASAP7_75t_SL | 6 | 25.000 | 3.100 | -27.364 | + | NST/CLK | | | | | | | | | + +----------------------------------------------------------------------------------------------------------------------------------------+ + diff --git a/build/par-rundir/timingReports/riscv_top_postRoute_reg2reg.tarpt b/build/par-rundir/timingReports/riscv_top_postRoute_reg2reg.tarpt new file mode 100644 index 0000000..f575d00 --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute_reg2reg.tarpt @@ -0,0 +1,7273 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:15 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### +Path 1: MET (1.791 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 126.000 (P) 160.200 (P) + Arrival:= 887.000 21.200 + + Setup:- 3.310 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 783.690 + Launch Clock:= 21.200 + Data Path:+ 760.700 + Slack:= 1.791 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.800 | 17.200 | 705.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1504/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 1 | 12.300 | 15.900 | 721.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_238 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1503/Y | | B->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 10.300 | 12.500 | 733.900 | + | cpu/stage2/alu/n_322 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5521/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 4 | 17.000 | 23.100 | 757.000 | + | dcache_addr[31] | | | F | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g420__5477/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 22.700 | 7.700 | 764.700 | + | cpu/s2_to_s3_alu/n_31 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC3942_n_31/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 47.500 | 17.200 | 781.900 | + | cpu/s2_to_s3_alu/FE_PHN3942_n_31 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[31]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 13.200 | 0.100 | 781.900 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 40.200 | 887.000 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 62.800 | 9.300 | 887.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 2: MET (3.298 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/register_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 126.300 (P) 160.200 (P) + Arrival:= 887.300 21.200 + + Setup:- 3.302 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 783.998 + Launch Clock:= 21.200 + Data Path:+ 759.500 + Slack:= 3.298 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.800 | 17.200 | 705.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1505/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 12.300 | 14.100 | 719.600 | + | cpu/stage2/alu/n_321 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5504/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 1 | 18.500 | 20.100 | 739.700 | + | cpu/FE_RN_3 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2795_dcache_addr_30/Y | | A->Y | F | BUFx24_ASAP7_75t_SL | 4 | 20.600 | 18.900 | 758.600 | + | dcache_addr[30] | | | F | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g434__7098/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 7.600 | 5.600 | 764.200 | + | cpu/s2_to_s3_alu/n_17 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2849_n_17/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 48.000 | 16.500 | 780.700 | + | cpu/s2_to_s3_alu/FE_PHN2849_n_17 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[30]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 12.000 | 0.000 | 780.700 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 40.500 | 887.300 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[30]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 62.800 | 9.600 | 887.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 3: MET (4.910 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[28]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 124.100 (P) 160.200 (P) + Arrival:= 885.100 21.200 + + Setup:- 6.091 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.009 + Launch Clock:= 21.200 + Data Path:+ 752.900 + Slack:= 4.910 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g400__2398/Y | | B->Y | R | AND2x4_ASAP7_75t_L | 11 | 7.800 | 30.000 | 450.900 | + | cpu/stage1_inst[21] | | | R | (net) | 11 | | | | + | cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 40.400 | 15.500 | 466.400 | + | cpu/stage1/regfile/n_194 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/g80394/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 25.500 | 15.900 | 482.300 | + | cpu/stage1/regfile/n_250 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g79869/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 28.300 | 12.700 | 495.000 | + | cpu/stage1/regfile/n_249 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g79864/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 29 | 20.000 | 72.400 | 567.400 | + | cpu/stage1/regfile/n_271 | | | F | (net) | 29 | | | | + | cpu/stage1/regfile/g79350/Y | | A->Y | R | INVxp67_ASAP7_75t_SL | 1 | 142.300 | 19.900 | 587.300 | + | cpu/stage1/regfile/n_270 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g78482/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 4 | 40.700 | 59.300 | 646.600 | + | cpu/stage1/regfile/n_689 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77761/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 108.600 | 27.400 | 674.000 | + | cpu/stage1/regfile/n_1379 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77278/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 14.400 | 21.300 | 695.300 | + | cpu/stage1/regfile/n_1851 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76888__4733/Y | | C->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 46.200 | 23.900 | 719.200 | + | cpu/stage1/rs2_mux_data[28] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3939_rs2_mux_data_28/ | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 49.600 | 19.100 | 738.300 | + | Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_PHN3939_rs2_mux_data_28 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g546__2346/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 8.100 | 16.500 | 754.800 | + | cpu/stage1_rs2[28] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC2788_stage1_rs2_28/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 12.800 | 12.400 | 767.200 | + | cpu/s1_to_s2_rs2/FE_PHN2788_stage1_rs2_28 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g447__9945/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.800 | 6.900 | 774.100 | + | cpu/s1_to_s2_rs2/n_4 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[28]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 58.900 | 0.100 | 774.100 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 36.400 | 885.100 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[28]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 4.500 | 885.100 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 4: MET (6.967 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[12]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[12]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 125.000 (P) 160.200 (P) + Arrival:= 886.000 21.200 + + Setup:- 5.933 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.067 + Launch Clock:= 21.200 + Data Path:+ 751.900 + Slack:= 6.967 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 30.100 | 502.700 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79855/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 26 | 50.100 | 69.500 | 572.200 | + | cpu/stage1/regfile/n_285 | | | F | (net) | 26 | | | | + | cpu/stage1/regfile/g78523/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 9 | 116.500 | 52.200 | 624.400 | + | cpu/stage1/regfile/n_633 | | | F | (net) | 9 | | | | + | cpu/stage1/regfile/g77606/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 49.900 | 16.700 | 641.100 | + | cpu/stage1/regfile/n_1530 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77064/Y | | A->Y | F | NAND4xp25_ASAP7_75t_SL | 1 | 28.200 | 12.900 | 654.000 | + | cpu/stage1/regfile/n_2045 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77002/Y | | B->Y | R | AOI211xp5_ASAP7_75t_SL | 1 | 32.000 | 19.300 | 673.300 | + | cpu/stage1/regfile/n_2107 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3935_n_2107/Y | | A->Y | R | BUFx4f_ASAP7_75t_SL | 1 | 38.600 | 14.500 | 687.800 | + | cpu/stage1/regfile/FE_PHN3935_n_2107 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76890__9315/Y | | B->Y | F | OAI211xp5_ASAP7_75t_SL | 1 | 7.400 | 39.400 | 727.200 | + | cpu/stage1/rs2_mux_data[12] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g566__1881/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 90.400 | 26.500 | 753.700 | + | cpu/stage1_rs2[12] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3586_stage1_rs2_12/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 14.000 | 12.700 | 766.400 | + | cpu/s1_to_s2_rs2/FE_PHN3586_stage1_rs2_12 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g433__3680/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.800 | 6.700 | 773.100 | + | cpu/s1_to_s2_rs2/n_18 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[12]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 57.400 | 0.000 | 773.100 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.300 | 886.000 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[12]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.600 | 5.400 | 886.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 5: MET (9.117 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[29]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/register_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 126.300 (P) 160.200 (P) + Arrival:= 887.300 21.200 + + Setup:- 1.983 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 785.317 + Launch Clock:= 21.200 + Data Path:+ 755.000 + Slack:= 9.117 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1508/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 11.800 | 14.100 | 702.400 | + | cpu/stage2/alu/n_320 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5506/Y | | A2->Y | F | AO21x1_ASAP7_75t_L | 1 | 18.800 | 24.800 | 727.200 | + | cpu/FE_RN_1 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2794_dcache_addr_29/Y | | A->Y | F | BUFx24_ASAP7_75t_SL | 4 | 23.300 | 19.000 | 746.200 | + | dcache_addr[29] | | | F | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g421__2398/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 6.800 | 6.100 | 752.300 | + | cpu/s2_to_s3_alu/n_30 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2840_n_30/Y | | A->Y | R | HB2xp67_ASAP7_75t_SL | 1 | 50.300 | 23.900 | 776.200 | + | cpu/s2_to_s3_alu/FE_PHN2840_n_30 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[29]/D | | D | R | DFFHQNx1_ASAP7_75t_L | 1 | 13.200 | 0.000 | 776.200 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 40.500 | 887.300 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[29]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 62.800 | 9.600 | 887.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 6: MET (9.139 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 149.000 (P) 160.200 (P) + Arrival:= 910.000 21.200 + + Setup:- 4.761 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 805.239 + Launch Clock:= 21.200 + Data Path:+ 774.900 + Slack:= 9.139 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.800 | 17.200 | 705.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1505/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 12.300 | 14.100 | 719.600 | + | cpu/stage2/alu/n_321 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5504/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 1 | 18.500 | 20.100 | 739.700 | + | cpu/FE_RN_3 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2795_dcache_addr_30/Y | | A->Y | F | BUFx24_ASAP7_75t_SL | 4 | 20.600 | 18.900 | 758.600 | + | dcache_addr[30] | | | F | (net) | 4 | | | | + | cpu/FE_PHC4128_dcache_addr_30/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 7.600 | 13.700 | 772.300 | + | cpu/FE_PHN4128_dcache_addr_30 | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g962__3680/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 10.600 | 15.200 | 787.500 | + | cpu/stage1/stage1_pc_mux_to_pc[30] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g349__8428/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 15.500 | 8.600 | 796.100 | + | cpu/stage1/pcreg/n_31 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[30]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 46.000 | 0.000 | 796.100 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 34.000 | 910.000 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[30]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.200 | 6.900 | 910.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 7: MET (9.350 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[4]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[4]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 123.400 (P) 160.200 (P) + Arrival:= 884.400 21.200 + + Setup:- 3.150 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 781.250 + Launch Clock:= 21.200 + Data Path:+ 750.700 + Slack:= 9.350 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 6 | 7.800 | 24.500 | 445.400 | + | cpu/stage1_inst[20] | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 4 | 31.800 | 30.600 | 476.000 | + | cpu/stage1/regfile/n_237 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 13 | 56.400 | 35.900 | 511.900 | + | cpu/stage1/regfile/n_236 | | | R | (net) | 13 | | | | + | cpu/stage1/regfile/FE_OFC643_n_237/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 59.300 | 5.400 | 517.300 | + | cpu/stage1/regfile/FE_OFN834_n_237 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g79821/Y | | B->Y | R | NOR2xp33_ASAP7_75t_L | 6 | 18.100 | 91.000 | 608.300 | + | cpu/stage1/regfile/n_332 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g77521/Y | | A1->Y | R | AO222x2_ASAP7_75t_SL | 1 | 196.500 | 58.200 | 666.500 | + | cpu/stage1/regfile/n_1615 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77282/Y | | C->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 19.100 | 10.800 | 677.300 | + | cpu/stage1/regfile/n_1847 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3566_n_1847/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 65.300 | 21.300 | 698.600 | + | cpu/stage1/regfile/FE_PHN3566_n_1847 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77107/Y | | A2->Y | F | OA211x2_ASAP7_75t_SL | 1 | 9.000 | 20.800 | 719.400 | + | cpu/stage1/regfile/n_2002 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76955__5107/Y | | B->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 15.300 | 18.400 | 737.800 | + | cpu/stage1/rs2_mux_data[4] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g550__5477/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 46.500 | 20.200 | 758.000 | + | cpu/stage1_rs2[4] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g435__2802/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 11.700 | 13.900 | 771.900 | + | cpu/s1_to_s2_rs2/n_16 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[4]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 83.700 | 0.300 | 771.900 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 35.700 | 884.400 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[4]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.500 | 3.800 | 884.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 8: MET (9.598 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/register_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 120.500 (P) 160.200 (P) + Arrival:= 881.500 21.200 + + Setup:- 3.402 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 778.098 + Launch Clock:= 21.200 + Data Path:+ 747.300 + Slack:= 9.598 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1549/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 1 | 33.200 | 20.100 | 550.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_206 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1547/Y | | B->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 11.000 | 12.600 | 562.700 | + | cpu/stage2/alu/n_306 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5665/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 12.600 | 8.100 | 570.800 | + | cpu/stage2/alu/n_56 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5522/Y | | A->Y | F | NAND3xp33_ASAP7_75t_SL | 2 | 33.300 | 42.000 | 612.800 | + | dcache_addr[15] | | | F | (net) | 2 | | | | + | cpu/FE_PHC2730_dcache_addr_15/Y | | A->Y | F | HB3xp67_ASAP7_75t_SL | 3 | 94.800 | 72.600 | 685.400 | + | cpu/FE_PHN2730_dcache_addr_15 | | | F | (net) | 3 | | | | + | cpu/s2_to_s3_alu/g450__5107/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 63.100 | 18.500 | 703.900 | + | cpu/s2_to_s3_alu/n_1 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2797_n_1/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 57.800 | 64.600 | 768.500 | + | cpu/s2_to_s3_alu/FE_PHN2797_n_1 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[15]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 22.900 | 0.000 | 768.500 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 34.700 | 881.500 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[15]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 60.300 | 3.800 | 881.500 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 9: MET (10.150 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.500 (P) 160.200 (P) + Arrival:= 900.500 21.200 + + Setup:- 3.050 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 797.450 + Launch Clock:= 21.200 + Data Path:+ 766.100 + Slack:= 10.150 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.800 | 17.200 | 705.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1504/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 1 | 12.300 | 15.900 | 721.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_238 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1503/Y | | B->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 10.300 | 12.500 | 733.900 | + | cpu/stage2/alu/n_322 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5521/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 4 | 17.000 | 23.400 | 757.300 | + | dcache_addr[31] | | | F | (net) | 4 | | | | + | cpu/stage3/csr/g178/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 22.700 | 13.200 | 770.500 | + | cpu/stage3/csr/n_17 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2848_n_17/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 53.500 | 16.800 | 787.300 | + | cpu/stage3/csr/FE_PHN2848_n_17 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[31]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 12.000 | 0.000 | 787.300 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 31.100 | 900.500 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.100 | 1.800 | 900.500 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 10: MET (10.609 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[28]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 124.700 (P) 160.800 (P) + Arrival:= 885.700 21.800 + + Setup:- -5.009 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.709 + Launch Clock:= 21.800 + Data Path:+ 758.300 + Slack:= 10.609 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.800 | 21.800 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[3]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 50.100 | 71.900 | + | cpu/stage3_inst[3] | | | R | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OCPC1470_stage3_inst_3/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 2 | 10.500 | 4.600 | 76.500 | + | cpu/stage3/ldsel/FE_OCPN1434_stage3_inst_3 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_RC_26_0/Y | | B->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 6.000 | 5.300 | 81.800 | + | cpu/stage3/ldsel/FE_RN_10_0 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/FE_RC_27_0/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 16.200 | 6.500 | 88.300 | + | cpu/stage3/ldsel/n_10 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g208/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 1 | 9.800 | 7.100 | 95.400 | + | cpu/stage3/ldsel/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g205/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 4 | 16.800 | 17.600 | 113.000 | + | cpu/stage3/LdSelect[0] | | | R | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y | | A->Y | F | INVx3_ASAP7_75t_SL | 1 | 16.000 | 6.300 | 119.300 | + | cpu/stage3/ldselmux/n_14 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 9.300 | 7.400 | 126.700 | + | cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 | | | R | (net) | 5 | | | | + | cpu/stage3/ldselmux/g2426/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 10.600 | 12.600 | 139.300 | + | cpu/stage3/ldselmux/n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/FE_OCPC1515_n_30/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 2 | 8.400 | 11.600 | 150.900 | + | cpu/stage3/ldselmux/FE_OCPN1476_n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/g2399/Y | | A2->Y | F | AOI21x1_ASAP7_75t_SL | 7 | 7.800 | 15.700 | 166.600 | + | cpu/stage3/ldselmux/n_62 | | | F | (net) | 7 | | | | + | cpu/stage3/ldselmux/g2354/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 31.000 | 15.700 | 182.300 | + | cpu/stage3/ldselmux/n_92 | | | R | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | F | OAI221xp5_ASAP7_75t_SL | 1 | 25.100 | 15.700 | 198.000 | + | cpu/stage3/wb_dmem[0] | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | F | AO21x1_ASAP7_75t_SL | 3 | 28.200 | 22.300 | 220.300 | + | cpu/wb_data[0] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 4 | 15.500 | 23.200 | 243.500 | + | cpu/stage2/stage2_rs2_data[0] | | | F | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 18.500 | 10.300 | 253.800 | + | cpu/stage2/bselmux/n_6 | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 2 | 25.000 | 23.800 | 277.600 | + | cpu/stage2/stage2_alu_in2[0] | | | R | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 24 | 28.000 | 16.300 | 293.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | F | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 5 | 29.700 | 29.900 | 323.800 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | F | XNOR2xp5_ASAP7_75t_SL | 2 | 33.500 | 25.800 | 349.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | R | MAJIxp5_ASAP7_75t_SL | 2 | 33.200 | 23.900 | 373.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 44.100 | 19.200 | 392.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 15.700 | 408.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 3 | 13.100 | 16.700 | 425.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | F | OAI311xp33_ASAP7_75t_SL | 1 | 14.900 | 9.900 | 435.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 27.900 | 13.600 | 448.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 20.800 | 16.700 | 465.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 11.900 | 14.500 | 479.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 11.000 | 8.800 | 488.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 16.000 | 20.900 | 509.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | R | AOI31xp67_ASAP7_75t_SL | 3 | 15.700 | 15.200 | 524.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 30.500 | 10.200 | 534.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 32.200 | 26.200 | 561.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 20.400 | 17.700 | 578.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | R | NAND2x1_ASAP7_75t_SL | 2 | 13.200 | 10.700 | 589.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 20.400 | 9.300 | 598.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | R | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 36.500 | 16.100 | 614.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 27.700 | 12.200 | 627.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 19.200 | 19.500 | 646.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 16.700 | 10.700 | 657.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 19.400 | 16.500 | 673.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1511/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 12.600 | 16.900 | 690.700 | + | cpu/stage2/alu/n_319 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5508/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 22.700 | 29.800 | 720.500 | + | dcache_addr[28] | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g447__6417/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 48.000 | 8.000 | 728.500 | + | cpu/s2_to_s3_alu/n_4 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2784_n_4/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 60.400 | 30.400 | 758.900 | + | cpu/s2_to_s3_alu/FE_PHN2784_n_4 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC3581_n_4/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 13.300 | 21.200 | 780.100 | + | cpu/s2_to_s3_alu/FE_PHN3581_n_4 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[28]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 11.600 | 0.100 | 780.100 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 38.900 | 885.700 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[28]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 62.700 | 8.000 | 885.700 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 11: MET (10.978 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[7]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[7]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 123.000 (P) 160.200 (P) + Arrival:= 884.000 21.200 + + Setup:- 6.822 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 777.178 + Launch Clock:= 21.200 + Data Path:+ 745.000 + Slack:= 10.978 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g400__2398/Y | | B->Y | R | AND2x4_ASAP7_75t_L | 11 | 7.800 | 30.000 | 450.900 | + | cpu/stage1_inst[21] | | | R | (net) | 11 | | | | + | cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 40.400 | 15.500 | 466.400 | + | cpu/stage1/regfile/n_194 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/g80394/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 25.500 | 15.900 | 482.300 | + | cpu/stage1/regfile/n_250 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g79869/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 28.300 | 12.700 | 495.000 | + | cpu/stage1/regfile/n_249 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g79864/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 29 | 20.000 | 72.400 | 567.400 | + | cpu/stage1/regfile/n_271 | | | F | (net) | 29 | | | | + | cpu/stage1/regfile/g79350/Y | | A->Y | R | INVxp67_ASAP7_75t_SL | 1 | 142.300 | 19.900 | 587.300 | + | cpu/stage1/regfile/n_270 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g78482/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 4 | 40.700 | 58.700 | 646.000 | + | cpu/stage1/regfile/n_689 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77646/Y | | A2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 108.600 | 19.200 | 665.200 | + | cpu/stage1/regfile/n_1494 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77151/Y | | B->Y | F | NAND3xp33_ASAP7_75t_SL | 1 | 45.800 | 14.100 | 679.300 | + | cpu/stage1/regfile/n_1958 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76907__2802/Y | | B->Y | R | AOI21xp5_ASAP7_75t_SL | 1 | 29.200 | 19.400 | 698.700 | + | cpu/stage1/regfile/n_2169 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76894__1666/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 35.800 | 24.200 | 722.900 | + | cpu/stage1/rs2_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g575__1666/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 53.700 | 21.300 | 744.200 | + | cpu/stage1_rs2[7] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC2790_stage1_rs2_7/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 10.600 | 11.900 | 756.100 | + | cpu/s1_to_s2_rs2/FE_PHN2790_stage1_rs2_7 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g427__5107/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.800 | 10.100 | 766.200 | + | cpu/s1_to_s2_rs2/n_24 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[7]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 65.700 | 0.400 | 766.200 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 35.300 | 884.000 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[7]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.500 | 3.400 | 884.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 12: MET (12.150 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.400 (P) 160.200 (P) + Arrival:= 900.400 21.200 + + Setup:- 3.050 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 797.350 + Launch Clock:= 21.200 + Data Path:+ 764.000 + Slack:= 12.150 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.800 | 17.200 | 705.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1505/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 12.300 | 14.100 | 719.600 | + | cpu/stage2/alu/n_321 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5504/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 1 | 18.500 | 20.100 | 739.700 | + | cpu/FE_RN_3 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2795_dcache_addr_30/Y | | A->Y | F | BUFx24_ASAP7_75t_SL | 4 | 20.600 | 19.100 | 758.800 | + | dcache_addr[30] | | | F | (net) | 4 | | | | + | cpu/stage3/csr/g191/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 7.700 | 9.600 | 768.400 | + | cpu/stage3/csr/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2839_n_4/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 53.000 | 16.800 | 785.200 | + | cpu/stage3/csr/FE_PHN2839_n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[30]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 12.000 | 0.000 | 785.200 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 31.000 | 900.400 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[30]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.100 | 1.700 | 900.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 13: MET (12.262 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[20]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[20]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 124.700 (P) 160.200 (P) + Arrival:= 885.700 21.200 + + Setup:- 6.038 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.662 + Launch Clock:= 21.200 + Data Path:+ 746.200 + Slack:= 12.262 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g400__2398/Y | | B->Y | R | AND2x4_ASAP7_75t_L | 11 | 7.800 | 30.000 | 450.900 | + | cpu/stage1_inst[21] | | | R | (net) | 11 | | | | + | cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 40.400 | 15.500 | 466.400 | + | cpu/stage1/regfile/n_194 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/g80394/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 25.500 | 15.900 | 482.300 | + | cpu/stage1/regfile/n_250 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g79869/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 28.300 | 12.600 | 494.900 | + | cpu/stage1/regfile/n_249 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g79860/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 27 | 20.000 | 77.400 | 572.300 | + | cpu/stage1/regfile/n_277 | | | F | (net) | 27 | | | | + | cpu/stage1/regfile/g79348/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 138.200 | 33.000 | 605.300 | + | cpu/stage1/regfile/n_276 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g78341/Y | | B2->Y | F | OAI22xp5_ASAP7_75t_SL | 1 | 57.200 | 9.000 | 614.300 | + | cpu/stage1/regfile/n_802 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77497/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 23.600 | 17.800 | 632.100 | + | cpu/stage1/regfile/n_1639 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76958__8428/Y | | B->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 60.200 | 20.200 | 652.300 | + | cpu/stage1/regfile/n_2147 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76903__5526/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 46.000 | 13.000 | 665.300 | + | cpu/stage1/regfile/n_2170 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76895__7410/Y | | B->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 24.000 | 54.000 | 719.300 | + | cpu/stage1/rs2_mux_data[20] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g571__9315/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 119.900 | 27.200 | 746.500 | + | cpu/stage1_rs2[20] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3596_stage1_rs2_20/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 13.600 | 13.600 | 760.100 | + | cpu/s1_to_s2_rs2/FE_PHN3596_stage1_rs2_20 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g441__1881/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 8.500 | 7.300 | 767.400 | + | cpu/s1_to_s2_rs2/n_10 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[20]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 58.400 | 0.000 | 767.400 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.000 | 885.700 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[20]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 5.100 | 885.700 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 14: MET (12.957 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[21]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 123.300 (P) 160.200 (P) + Arrival:= 884.300 21.200 + + Setup:- 6.343 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 777.957 + Launch Clock:= 21.200 + Data Path:+ 743.800 + Slack:= 12.957 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 30.100 | 502.700 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/FE_OFC643_n_237/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 50.100 | 9.500 | 512.200 | + | cpu/stage1/regfile/FE_OFN834_n_237 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g79821/Y | | B->Y | F | NOR2xp33_ASAP7_75t_L | 6 | 17.300 | 75.300 | 587.500 | + | cpu/stage1/regfile/n_332 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g78338/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 145.600 | 28.500 | 616.000 | + | cpu/stage1/regfile/n_805 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77346/Y | | B->Y | F | NAND3xp33_ASAP7_75t_SL | 1 | 53.600 | 11.000 | 627.000 | + | cpu/stage1/regfile/n_1783 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77062/Y | | A2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 26.600 | 15.200 | 642.200 | + | cpu/stage1/regfile/n_2047 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3561_n_2047/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 1 | 70.200 | 35.000 | 677.200 | + | cpu/stage1/regfile/FE_PHN3561_n_2047 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76916__4733/Y | | C->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 16.700 | 42.000 | 719.200 | + | cpu/stage1/rs2_mux_data[21] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g569__4733/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 93.900 | 25.500 | 744.700 | + | cpu/stage1_rs2[21] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3591_stage1_rs2_21/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 12.700 | 12.400 | 757.100 | + | cpu/s1_to_s2_rs2/FE_PHN3591_stage1_rs2_21 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g442__5115/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.800 | 7.900 | 765.000 | + | cpu/s1_to_s2_rs2/n_9 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[21]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 61.300 | 0.100 | 765.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 35.600 | 884.300 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[21]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.600 | 3.700 | 884.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 15: MET (13.588 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[25]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[25]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 120.700 (P) 160.200 (P) + Arrival:= 881.700 21.200 + + Setup:- 1.712 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.988 + Launch Clock:= 21.200 + Data Path:+ 745.200 + Slack:= 13.588 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 6 | 7.800 | 24.500 | 445.400 | + | cpu/stage1_inst[20] | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 4 | 31.800 | 30.600 | 476.000 | + | cpu/stage1/regfile/n_237 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 13 | 56.400 | 35.900 | 511.900 | + | cpu/stage1/regfile/n_236 | | | R | (net) | 13 | | | | + | cpu/stage1/regfile/FE_OFC643_n_237/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 59.300 | 5.400 | 517.300 | + | cpu/stage1/regfile/FE_OFN834_n_237 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g79821/Y | | B->Y | R | NOR2xp33_ASAP7_75t_L | 6 | 18.100 | 92.500 | 609.800 | + | cpu/stage1/regfile/n_332 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g77534/Y | | A1->Y | R | AO222x2_ASAP7_75t_SL | 1 | 196.500 | 57.300 | 667.100 | + | cpu/stage1/regfile/n_1602 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77284/Y | | C->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 18.200 | 10.400 | 677.500 | + | cpu/stage1/regfile/n_1845 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77061/Y | | A2->Y | F | OA211x2_ASAP7_75t_SL | 1 | 47.900 | 27.600 | 705.100 | + | cpu/stage1/regfile/n_2048 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76935__2802/Y | | B->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 14.000 | 28.700 | 733.800 | + | cpu/stage1/rs2_mux_data[25] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g547__1666/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 66.800 | 22.600 | 756.400 | + | cpu/stage1_rs2[25] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g430__8428/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 13.700 | 10.000 | 766.400 | + | cpu/s1_to_s2_rs2/n_21 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[25]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 66.700 | 0.400 | 766.400 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 33.000 | 881.700 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[25]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 52.800 | 1.100 | 881.700 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 16: MET (14.437 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[29]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.500 (P) 160.200 (P) + Arrival:= 900.500 21.200 + + Setup:- 3.063 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 797.437 + Launch Clock:= 21.200 + Data Path:+ 761.800 + Slack:= 14.437 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.800 | 624.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 22.200 | 18.400 | 642.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 10.100 | 653.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 16.600 | 17.900 | 670.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 11.700 | 17.400 | 688.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1508/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 11.800 | 14.100 | 702.400 | + | cpu/stage2/alu/n_320 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5506/Y | | A2->Y | F | AO21x1_ASAP7_75t_L | 1 | 18.800 | 24.800 | 727.200 | + | cpu/FE_RN_1 | | | F | (net) | 1 | | | | + | cpu/FE_PHC2794_dcache_addr_29/Y | | A->Y | F | BUFx24_ASAP7_75t_SL | 4 | 23.300 | 19.000 | 746.200 | + | dcache_addr[29] | | | F | (net) | 4 | | | | + | cpu/stage3/csr/g164/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 6.800 | 11.800 | 758.000 | + | cpu/stage3/csr/n_31 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2835_n_31/Y | | A->Y | R | HB2xp67_ASAP7_75t_SL | 1 | 57.700 | 25.000 | 783.000 | + | cpu/stage3/csr/FE_PHN2835_n_31 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[29]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 14.100 | 0.000 | 783.000 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 31.100 | 900.500 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[29]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.100 | 1.800 | 900.500 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 17: MET (14.484 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[9]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 124.900 (P) 160.200 (P) + Arrival:= 885.900 21.200 + + Setup:- 6.416 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.484 + Launch Clock:= 21.200 + Data Path:+ 743.800 + Slack:= 14.484 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g400__2398/Y | | B->Y | R | AND2x4_ASAP7_75t_L | 11 | 7.800 | 30.000 | 450.900 | + | cpu/stage1_inst[21] | | | R | (net) | 11 | | | | + | cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 40.400 | 15.500 | 466.400 | + | cpu/stage1/regfile/n_194 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/g80394/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 3 | 25.500 | 15.900 | 482.300 | + | cpu/stage1/regfile/n_250 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g79869/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 28.300 | 12.700 | 495.000 | + | cpu/stage1/regfile/n_249 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g79864/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 29 | 20.000 | 72.400 | 567.400 | + | cpu/stage1/regfile/n_271 | | | F | (net) | 29 | | | | + | cpu/stage1/regfile/g79350/Y | | A->Y | R | INVxp67_ASAP7_75t_SL | 1 | 142.300 | 19.900 | 587.300 | + | cpu/stage1/regfile/n_270 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g78482/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 4 | 40.700 | 59.800 | 647.100 | + | cpu/stage1/regfile/n_689 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g77725/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 108.600 | 26.600 | 673.700 | + | cpu/stage1/regfile/n_1415 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77264/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 13.600 | 15.100 | 688.800 | + | cpu/stage1/regfile/n_1865 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76891__9945/Y | | C->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 35.000 | 29.700 | 718.500 | + | cpu/stage1/rs2_mux_data[9] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g572__9945/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 67.600 | 24.800 | 743.300 | + | cpu/stage1_rs2[9] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3585_stage1_rs2_9/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 13.300 | 12.900 | 756.200 | + | cpu/s1_to_s2_rs2/FE_PHN3585_stage1_rs2_9 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g429__4319/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 6.300 | 8.800 | 765.000 | + | cpu/s1_to_s2_rs2/n_22 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[9]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 62.000 | 0.200 | 765.000 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.200 | 885.900 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[9]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.600 | 5.300 | 885.900 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 18: MET (14.899 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[16]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[16]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 122.000 (P) 160.200 (P) + Arrival:= 883.000 21.200 + + Setup:- 6.701 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 776.299 + Launch Clock:= 21.200 + Data Path:+ 740.200 + Slack:= 14.899 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 28.700 | 501.300 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79856/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 27 | 49.900 | 70.000 | 571.300 | + | cpu/stage1/regfile/n_284 | | | F | (net) | 27 | | | | + | cpu/stage1/regfile/g78499/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 111.700 | 45.400 | 616.700 | + | cpu/stage1/regfile/n_667 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g77579/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 42.100 | 20.200 | 636.900 | + | cpu/stage1/regfile/n_1557 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77069/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 54.800 | 21.100 | 658.000 | + | cpu/stage1/regfile/n_2040 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77003/Y | | B->Y | R | AOI211xp5_ASAP7_75t_SL | 1 | 43.200 | 21.600 | 679.600 | + | cpu/stage1/regfile/n_2106 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76905__3680/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 37.700 | 45.100 | 724.700 | + | cpu/stage1/rs2_mux_data[16] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g555__8428/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 96.100 | 25.700 | 750.400 | + | cpu/stage1_rs2[16] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g436__1705/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 12.800 | 11.000 | 761.400 | + | cpu/s1_to_s2_rs2/n_15 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[16]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 64.600 | 0.300 | 761.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 34.300 | 883.000 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[16]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.300 | 2.400 | 883.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 19: MET (16.083 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 125.100 (P) 160.200 (P) + Arrival:= 886.100 21.200 + + Setup:- 6.017 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.083 + Launch Clock:= 21.200 + Data Path:+ 742.800 + Slack:= 16.083 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g393__9945/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 7 | 7.800 | 29.800 | 450.700 | + | cpu/stage1_inst[23] | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g80399/Y | | B->Y | F | NOR2x1_ASAP7_75t_SL | 9 | 43.300 | 44.600 | 495.300 | + | cpu/stage1/regfile/n_242 | | | F | (net) | 9 | | | | + | cpu/stage1/regfile/g79852/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 23 | 78.800 | 72.000 | 567.300 | + | cpu/stage1/regfile/n_289 | | | F | (net) | 23 | | | | + | cpu/stage1/regfile/g78533/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 14 | 107.700 | 60.600 | 627.900 | + | cpu/stage1/regfile/n_619 | | | F | (net) | 14 | | | | + | cpu/stage1/regfile/g77861/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 67.200 | 17.000 | 644.900 | + | cpu/stage1/regfile/n_1278 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77155/Y | | A->Y | F | NAND3xp33_ASAP7_75t_SL | 1 | 28.400 | 10.800 | 655.700 | + | cpu/stage1/regfile/n_1954 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77082/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 25.600 | 19.500 | 675.200 | + | cpu/stage1/regfile/n_2027 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76997__1881/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 46.800 | 21.300 | 696.500 | + | cpu/stage1/regfile/n_2112 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76939__7098/Y | | B->Y | F | AO21x1_ASAP7_75t_SL | 1 | 43.300 | 20.300 | 716.800 | + | cpu/stage1/rs2_mux_data[31] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3943_rs2_mux_data_31/ | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 11.000 | 11.800 | 728.600 | + | Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_PHN3943_rs2_mux_data_31 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g560__2802/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 5.500 | 16.500 | 745.100 | + | cpu/stage1_rs2[31] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC2793_stage1_rs2_31/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 13.000 | 12.400 | 757.500 | + | cpu/s1_to_s2_rs2/FE_PHN2793_stage1_rs2_31 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g420__2883/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.700 | 6.500 | 764.000 | + | cpu/s1_to_s2_rs2/n_31 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[31]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 58.200 | 0.000 | 764.000 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.400 | 886.100 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 5.500 | 886.100 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 20: MET (16.141 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 124.400 (P) 160.200 (P) + Arrival:= 885.400 21.200 + + Setup:- 6.259 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.141 + Launch Clock:= 21.200 + Data Path:+ 741.800 + Slack:= 16.141 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g393__9945/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 7 | 5.800 | 26.700 | 443.200 | + | cpu/stage1_inst[23] | | | F | (net) | 7 | | | | + | cpu/stage1/regfile/g80396/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 33.600 | 41.200 | 484.400 | + | cpu/stage1/regfile/n_247 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79870/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 80.200 | 16.300 | 500.700 | + | cpu/stage1/regfile/n_246 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g79865/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 30 | 34.300 | 92.800 | 593.500 | + | cpu/stage1/regfile/n_269 | | | F | (net) | 30 | | | | + | cpu/stage1/regfile/g78030/Y | | A2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 149.400 | 21.900 | 615.400 | + | cpu/stage1/regfile/n_1109 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77369/Y | | A->Y | R | AND4x1_ASAP7_75t_SL | 1 | 55.000 | 24.400 | 639.800 | + | cpu/stage1/regfile/n_1771 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77051/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 12.900 | 13.000 | 652.800 | + | cpu/stage1/regfile/n_2058 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76973__6161/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 37.900 | 15.800 | 668.600 | + | cpu/stage1/regfile/n_2136 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76953__5477/Y | | B->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 27.700 | 33.000 | 701.600 | + | cpu/stage1/rs2_mux_data[8] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC4119_rs2_mux_data_8/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 74.600 | 22.300 | 723.900 | + | cpu/stage1/data2sel_s1/FE_PHN4119_rs2_mux_data_8 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g573__2883/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 11.100 | 17.800 | 741.700 | + | cpu/stage1_rs2[8] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3595_stage1_rs2_8/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 13.900 | 13.300 | 755.000 | + | cpu/s1_to_s2_rs2/FE_PHN3595_stage1_rs2_8 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g428__6260/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 8.100 | 8.000 | 763.000 | + | cpu/s1_to_s2_rs2/n_23 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[8]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 60.500 | 0.100 | 763.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 36.700 | 885.400 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[8]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.600 | 4.800 | 885.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 21: MET (16.902 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 148.400 (P) 160.200 (P) + Arrival:= 909.400 21.200 + + Setup:- 2.198 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 807.202 + Launch Clock:= 21.200 + Data Path:+ 769.100 + Slack:= 16.902 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.700 | 401.000 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 4 | 17.300 | 20.200 | 421.200 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1209_stage1_inst_15/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 6 | 37.700 | 11.200 | 432.400 | + | cpu/stage1/regfile/FE_OFN1007_stage1_inst_15 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/FE_RC_2_0/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 20.200 | 14.700 | 447.100 | + | cpu/stage1/regfile/FE_RN_0_0 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_RC_3_0/Y | | A->Y | F | INVx6_ASAP7_75t_SL | 5 | 22.500 | 12.500 | 459.600 | + | cpu/stage1/regfile/n_211 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC991_n_211/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 1 | 19.600 | 8.200 | 467.800 | + | cpu/stage1/regfile/FE_OFN1087_n_211 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1195_n_211/Y | | A->Y | F | INVx8_ASAP7_75t_SL | 13 | 12.200 | 10.500 | 478.300 | + | cpu/stage1/regfile/FE_OFN1090_n_211 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79826/Y | | B->Y | F | AND2x6_ASAP7_75t_SL | 7 | 13.200 | 22.500 | 500.800 | + | cpu/stage1/regfile/n_326 | | | F | (net) | 7 | | | | + | cpu/stage1/regfile/g78423/Y | | B->Y | R | NAND2x2_ASAP7_75t_SL | 4 | 19.600 | 15.400 | 516.200 | + | cpu/stage1/regfile/n_788 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77789/Y | | A2->Y | F | OAI22x1_ASAP7_75t_SL | 1 | 28.200 | 12.500 | 528.700 | + | cpu/stage1/regfile/n_1351 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77281/Y | | A->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 19.700 | 8.600 | 537.300 | + | cpu/stage1/regfile/n_1848 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76866__1666/Y | | B->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 15.800 | 19.300 | 556.600 | + | cpu/stage1/rs1_mux_data[13] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g563__7098/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 38.200 | 25.700 | 582.300 | + | cpu/stage1_rs1[13] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1258__4319/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 15.900 | 19.900 | 602.200 | + | cpu/stage1/pcadder/n_44 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 3 | 18.300 | 11.000 | 613.200 | + | 33_g1450__7098/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_77 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 2 | 18.700 | 8.200 | 621.400 | + | 33_g1353__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_158 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 14.200 | 17.500 | 638.900 | + | 33_g1318__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_186 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OA21x2_ASAP7_75t_SL | 2 | 33.100 | 19.900 | 658.800 | + | 33_g1305__9945/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_196 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0_dup/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 14.800 | 15.500 | 674.300 | + | cpu/stage1/pcadder/FE_RN_1 | | | F | (net) | 1 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 27.400 | 11.400 | 685.700 | + | 33_g1283__1617/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_19 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 20.300 | 9.000 | 694.700 | + | 33_g1275__4319/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_20 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 2 | 12.500 | 21.400 | 716.100 | + | 33_g1263__2883/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_226 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 43.100 | 14.100 | 730.200 | + | 33_g1249__5122/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_238 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 26.500 | 16.900 | 747.100 | + | 33_g1240__4319/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[27] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g999__5115/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 14.700 | 8.600 | 755.700 | + | cpu/stage1/pcselmux/n_5 | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g932__5526/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 44.000 | 10.400 | 766.100 | + | cpu/stage1/stage1_pc_mux_to_pc[27] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g352__3680/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 23.400 | 8.900 | 775.000 | + | cpu/stage1/pcreg/FE_PHN4121_n_28 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC4121_n_28/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 43.800 | 15.300 | 790.300 | + | cpu/stage1/pcreg/n_28 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[27]/D | | D | R | DFFHQNx1_ASAP7_75t_L | 1 | 7.700 | 0.000 | 790.300 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 33.400 | 909.400 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[27]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 51.200 | 6.300 | 909.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 22: MET (17.679 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[25]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[25]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 125.500 (P) 160.800 (P) + Arrival:= 886.500 21.800 + + Setup:- -7.579 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 794.079 + Launch Clock:= 21.800 + Data Path:+ 754.600 + Slack:= 17.679 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.800 | 21.800 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[3]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 50.100 | 71.900 | + | cpu/stage3_inst[3] | | | R | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OCPC1470_stage3_inst_3/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 2 | 10.500 | 4.600 | 76.500 | + | cpu/stage3/ldsel/FE_OCPN1434_stage3_inst_3 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_RC_26_0/Y | | B->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 6.000 | 5.300 | 81.800 | + | cpu/stage3/ldsel/FE_RN_10_0 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/FE_RC_27_0/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 16.200 | 6.500 | 88.300 | + | cpu/stage3/ldsel/n_10 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g208/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 1 | 9.800 | 7.100 | 95.400 | + | cpu/stage3/ldsel/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g205/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 4 | 16.800 | 17.600 | 113.000 | + | cpu/stage3/LdSelect[0] | | | R | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y | | A->Y | F | INVx3_ASAP7_75t_SL | 1 | 16.000 | 6.300 | 119.300 | + | cpu/stage3/ldselmux/n_14 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 9.300 | 7.400 | 126.700 | + | cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 | | | R | (net) | 5 | | | | + | cpu/stage3/ldselmux/g2426/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 10.600 | 12.600 | 139.300 | + | cpu/stage3/ldselmux/n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/FE_OCPC1515_n_30/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 2 | 8.400 | 11.600 | 150.900 | + | cpu/stage3/ldselmux/FE_OCPN1476_n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/g2399/Y | | A2->Y | F | AOI21x1_ASAP7_75t_SL | 7 | 7.800 | 15.700 | 166.600 | + | cpu/stage3/ldselmux/n_62 | | | F | (net) | 7 | | | | + | cpu/stage3/ldselmux/g2354/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 31.000 | 15.700 | 182.300 | + | cpu/stage3/ldselmux/n_92 | | | R | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | F | OAI221xp5_ASAP7_75t_SL | 1 | 25.100 | 15.700 | 198.000 | + | cpu/stage3/wb_dmem[0] | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | F | AO21x1_ASAP7_75t_SL | 3 | 28.200 | 22.300 | 220.300 | + | cpu/wb_data[0] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 4 | 15.500 | 23.200 | 243.500 | + | cpu/stage2/stage2_rs2_data[0] | | | F | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 18.500 | 10.300 | 253.800 | + | cpu/stage2/bselmux/n_6 | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 2 | 25.000 | 23.800 | 277.600 | + | cpu/stage2/stage2_alu_in2[0] | | | R | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 24 | 28.000 | 16.300 | 293.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | F | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 5 | 29.700 | 29.900 | 323.800 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | F | XNOR2xp5_ASAP7_75t_SL | 2 | 33.500 | 25.800 | 349.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | R | MAJIxp5_ASAP7_75t_SL | 2 | 33.200 | 23.900 | 373.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 44.100 | 19.200 | 392.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 15.700 | 408.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 3 | 13.100 | 16.700 | 425.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | F | OAI311xp33_ASAP7_75t_SL | 1 | 14.900 | 9.900 | 435.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 27.900 | 13.600 | 448.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 20.800 | 16.700 | 465.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 11.900 | 14.500 | 479.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 11.000 | 8.800 | 488.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 16.000 | 20.900 | 509.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | R | AOI31xp67_ASAP7_75t_SL | 3 | 15.700 | 15.200 | 524.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 30.500 | 10.200 | 534.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 32.200 | 26.200 | 561.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 20.400 | 17.700 | 578.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | R | NAND2x1_ASAP7_75t_SL | 2 | 13.200 | 10.700 | 589.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 20.400 | 9.300 | 598.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | R | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 36.500 | 16.100 | 614.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 27.700 | 12.200 | 627.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1519/Y | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 1 | 19.200 | 12.900 | 640.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_232 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1518/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 23.500 | 16.600 | 656.600 | + | cpu/stage2/alu/n_316 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5509/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 20.600 | 31.600 | 688.200 | + | dcache_addr[25] | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g430__2802/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 52.600 | 13.600 | 701.800 | + | cpu/s2_to_s3_alu/n_21 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC3580_n_21/Y | | A->Y | F | BUFx6f_ASAP7_75t_L | 1 | 66.300 | 24.800 | 726.600 | + | cpu/s2_to_s3_alu/FE_PHN3580_n_21 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2777_n_21/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 7.800 | 49.800 | 776.400 | + | cpu/s2_to_s3_alu/FE_PHN2777_n_21 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[25]/D | | D | F | DFFHQNx1_ASAP7_75t_L | 1 | 19.300 | 0.100 | 776.400 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 39.700 | 886.500 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[25]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 62.800 | 8.800 | 886.500 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 23: MET (17.815 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[25]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage3/csr/csr_reg[25]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.300 (P) 160.800 (P) + Arrival:= 900.300 21.800 + + Setup:- -4.515 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 804.815 + Launch Clock:= 21.800 + Data Path:+ 765.200 + Slack:= 17.815 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.800 | 21.800 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[3]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 50.100 | 71.900 | + | cpu/stage3_inst[3] | | | R | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OCPC1470_stage3_inst_3/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 2 | 10.500 | 4.600 | 76.500 | + | cpu/stage3/ldsel/FE_OCPN1434_stage3_inst_3 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_RC_26_0/Y | | B->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 6.000 | 5.300 | 81.800 | + | cpu/stage3/ldsel/FE_RN_10_0 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/FE_RC_27_0/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 16.200 | 6.500 | 88.300 | + | cpu/stage3/ldsel/n_10 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g208/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 1 | 9.800 | 7.100 | 95.400 | + | cpu/stage3/ldsel/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g205/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 4 | 16.800 | 17.600 | 113.000 | + | cpu/stage3/LdSelect[0] | | | R | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y | | A->Y | F | INVx3_ASAP7_75t_SL | 1 | 16.000 | 6.300 | 119.300 | + | cpu/stage3/ldselmux/n_14 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 9.300 | 7.400 | 126.700 | + | cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 | | | R | (net) | 5 | | | | + | cpu/stage3/ldselmux/g2426/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 10.600 | 12.600 | 139.300 | + | cpu/stage3/ldselmux/n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/FE_OCPC1515_n_30/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 2 | 8.400 | 11.600 | 150.900 | + | cpu/stage3/ldselmux/FE_OCPN1476_n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/g2399/Y | | A2->Y | F | AOI21x1_ASAP7_75t_SL | 7 | 7.800 | 15.700 | 166.600 | + | cpu/stage3/ldselmux/n_62 | | | F | (net) | 7 | | | | + | cpu/stage3/ldselmux/g2354/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 31.000 | 15.700 | 182.300 | + | cpu/stage3/ldselmux/n_92 | | | R | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | F | OAI221xp5_ASAP7_75t_SL | 1 | 25.100 | 15.700 | 198.000 | + | cpu/stage3/wb_dmem[0] | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | F | AO21x1_ASAP7_75t_SL | 3 | 28.200 | 22.300 | 220.300 | + | cpu/wb_data[0] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 4 | 15.500 | 23.200 | 243.500 | + | cpu/stage2/stage2_rs2_data[0] | | | F | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 18.500 | 10.300 | 253.800 | + | cpu/stage2/bselmux/n_6 | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 2 | 25.000 | 23.800 | 277.600 | + | cpu/stage2/stage2_alu_in2[0] | | | R | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 24 | 28.000 | 16.300 | 293.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | F | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 5 | 29.700 | 29.900 | 323.800 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | F | XNOR2xp5_ASAP7_75t_SL | 2 | 33.500 | 25.800 | 349.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | R | MAJIxp5_ASAP7_75t_SL | 2 | 33.200 | 23.900 | 373.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 44.100 | 19.200 | 392.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 15.700 | 408.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 3 | 13.100 | 16.700 | 425.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | F | OAI311xp33_ASAP7_75t_SL | 1 | 14.900 | 9.900 | 435.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 27.900 | 13.600 | 448.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 20.800 | 16.700 | 465.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 11.900 | 14.500 | 479.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 11.000 | 8.800 | 488.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 16.000 | 20.900 | 509.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | R | AOI31xp67_ASAP7_75t_SL | 3 | 15.700 | 15.200 | 524.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 30.500 | 10.200 | 534.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 32.200 | 26.200 | 561.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 20.400 | 17.700 | 578.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | R | NAND2x1_ASAP7_75t_SL | 2 | 13.200 | 10.700 | 589.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 20.400 | 9.300 | 598.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | R | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 36.500 | 16.100 | 614.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 27.700 | 12.200 | 627.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1519/Y | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 1 | 19.200 | 12.900 | 640.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_232 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1518/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 23.500 | 16.600 | 656.600 | + | cpu/stage2/alu/n_316 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5509/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 20.600 | 32.100 | 688.700 | + | dcache_addr[25] | | | R | (net) | 4 | | | | + | cpu/stage3/csr/g167/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 52.600 | 15.700 | 704.400 | + | cpu/stage3/csr/n_28 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2773_n_28/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 63.400 | 60.700 | 765.100 | + | cpu/stage3/csr/FE_PHN2773_n_28 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC3576_n_28/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 17.700 | 21.900 | 787.000 | + | cpu/stage3/csr/FE_PHN3576_n_28 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[25]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 11.300 | 0.000 | 787.000 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 30.900 | 900.300 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[25]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.100 | 1.600 | 900.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 24: MET (19.415 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[11]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[11]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 125.000 (P) 160.200 (P) + Arrival:= 886.000 21.200 + + Setup:- 6.185 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.815 + Launch Clock:= 21.200 + Data Path:+ 739.200 + Slack:= 19.415 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g393__9945/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 7 | 5.800 | 26.700 | 443.200 | + | cpu/stage1_inst[23] | | | F | (net) | 7 | | | | + | cpu/stage1/regfile/g80396/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 33.600 | 41.200 | 484.400 | + | cpu/stage1/regfile/n_247 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g79870/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 4 | 80.200 | 16.300 | 500.700 | + | cpu/stage1/regfile/n_246 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/g79865/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 30 | 34.300 | 93.600 | 594.300 | + | cpu/stage1/regfile/n_269 | | | F | (net) | 30 | | | | + | cpu/stage1/regfile/g78003/Y | | A2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 149.400 | 22.700 | 617.000 | + | cpu/stage1/regfile/n_1136 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77367/Y | | A->Y | R | AND4x1_ASAP7_75t_SL | 1 | 56.000 | 24.500 | 641.500 | + | cpu/stage1/regfile/n_1773 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77050/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 12.900 | 13.800 | 655.300 | + | cpu/stage1/regfile/n_2059 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76972__4733/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 39.800 | 15.700 | 671.000 | + | cpu/stage1/regfile/n_2137 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76948__2883/Y | | B->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 27.100 | 50.800 | 721.800 | + | cpu/stage1/rs2_mux_data[11] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g567__5115/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 111.800 | 29.100 | 750.900 | + | cpu/stage1_rs2[11] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g432__6783/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 15.900 | 9.500 | 760.400 | + | cpu/s1_to_s2_rs2/n_19 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[11]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 59.800 | 0.100 | 760.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.300 | 886.000 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[11]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 5.400 | 886.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 25: MET (19.487 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 148.900 (P) 160.200 (P) + Arrival:= 909.900 21.200 + + Setup:- 4.813 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 805.087 + Launch Clock:= 21.200 + Data Path:+ 764.400 + Slack:= 19.487 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.700 | 401.000 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 4 | 17.300 | 20.200 | 421.200 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1209_stage1_inst_15/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 6 | 37.700 | 11.200 | 432.400 | + | cpu/stage1/regfile/FE_OFN1007_stage1_inst_15 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/FE_RC_2_0/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 20.200 | 14.700 | 447.100 | + | cpu/stage1/regfile/FE_RN_0_0 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_RC_3_0/Y | | A->Y | F | INVx6_ASAP7_75t_SL | 5 | 22.500 | 12.500 | 459.600 | + | cpu/stage1/regfile/n_211 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC991_n_211/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 1 | 19.600 | 8.200 | 467.800 | + | cpu/stage1/regfile/FE_OFN1087_n_211 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1195_n_211/Y | | A->Y | F | INVx8_ASAP7_75t_SL | 13 | 12.200 | 10.500 | 478.300 | + | cpu/stage1/regfile/FE_OFN1090_n_211 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79826/Y | | B->Y | F | AND2x6_ASAP7_75t_SL | 7 | 13.200 | 22.500 | 500.800 | + | cpu/stage1/regfile/n_326 | | | F | (net) | 7 | | | | + | cpu/stage1/regfile/g78423/Y | | B->Y | R | NAND2x2_ASAP7_75t_SL | 4 | 19.600 | 15.400 | 516.200 | + | cpu/stage1/regfile/n_788 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77789/Y | | A2->Y | F | OAI22x1_ASAP7_75t_SL | 1 | 28.200 | 12.500 | 528.700 | + | cpu/stage1/regfile/n_1351 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77281/Y | | A->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 19.700 | 8.600 | 537.300 | + | cpu/stage1/regfile/n_1848 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76866__1666/Y | | B->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 15.800 | 19.300 | 556.600 | + | cpu/stage1/rs1_mux_data[13] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g563__7098/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 38.200 | 25.700 | 582.300 | + | cpu/stage1_rs1[13] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1258__4319/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 15.900 | 19.900 | 602.200 | + | cpu/stage1/pcadder/n_44 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 3 | 18.300 | 11.000 | 613.200 | + | 33_g1450__7098/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_77 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 2 | 18.700 | 8.200 | 621.400 | + | 33_g1353__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_158 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 14.200 | 17.500 | 638.900 | + | 33_g1318__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_186 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OA21x2_ASAP7_75t_SL | 2 | 33.100 | 19.900 | 658.800 | + | 33_g1305__9945/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_196 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0_dup/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 14.800 | 15.500 | 674.300 | + | cpu/stage1/pcadder/FE_RN_1 | | | F | (net) | 1 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 27.400 | 11.400 | 685.700 | + | 33_g1283__1617/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_19 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 20.300 | 9.000 | 694.700 | + | 33_g1275__4319/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_20 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 12.500 | 18.100 | 712.800 | + | 33_g1257__7482/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_231 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 12.000 | 11.100 | 723.900 | + | 33_g1244__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_243 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 24.600 | 6.600 | 730.500 | + | 33_g1236__5477/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_251 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 15.800 | 14.100 | 744.600 | + | 33_g1235__6417/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[31] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g988__5526/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 1 | 16.100 | 14.900 | 759.500 | + | cpu/stage1/pcselmux/n_16 | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g961__6783/Y | | B->Y | F | AO21x1_ASAP7_75t_SL | 2 | 14.200 | 17.300 | 776.800 | + | cpu/stage1/stage1_pc_mux_to_pc[31] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g362__7482/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 15.200 | 8.800 | 785.600 | + | cpu/stage1/pcreg/n_18 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[31]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 46.500 | 0.100 | 785.600 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 33.900 | 909.900 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.200 | 6.800 | 909.900 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 26: MET (20.493 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[22]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 120.300 (P) 160.200 (P) + Arrival:= 881.300 21.200 + + Setup:- 6.907 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 774.393 + Launch Clock:= 21.200 + Data Path:+ 732.700 + Slack:= 20.493 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 28.700 | 501.300 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79856/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 27 | 49.900 | 70.000 | 571.300 | + | cpu/stage1/regfile/n_284 | | | F | (net) | 27 | | | | + | cpu/stage1/regfile/g78499/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 111.700 | 45.300 | 616.600 | + | cpu/stage1/regfile/n_667 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g77806/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 42.100 | 19.600 | 636.200 | + | cpu/stage1/regfile/n_1334 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77085/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 53.900 | 24.300 | 660.500 | + | cpu/stage1/regfile/n_2024 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77004/Y | | B->Y | R | AOI211xp5_ASAP7_75t_SL | 1 | 48.700 | 25.500 | 686.000 | + | cpu/stage1/regfile/n_2105 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76906__1617/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 45.300 | 15.500 | 701.500 | + | cpu/stage1/rs2_mux_data[22] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_OCPC1477_rs2_mux_data_22 | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 33.400 | 23.500 | 725.000 | + | /Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_OCPN1438_rs2_mux_data_22 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g562__5122/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 17.700 | 17.300 | 742.300 | + | cpu/stage1_rs2[22] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g443__7482/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 12.400 | 11.600 | 753.900 | + | cpu/s1_to_s2_rs2/n_8 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[22]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 66.500 | 0.300 | 753.900 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 32.600 | 881.300 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[22]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 52.700 | 0.700 | 881.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 27: MET (20.999 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[24]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[24]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 121.300 (P) 160.200 (P) + Arrival:= 882.300 21.200 + + Setup:- 1.701 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.599 + Launch Clock:= 21.200 + Data Path:+ 738.400 + Slack:= 20.999 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.800 | 409.200 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_RC_13_0/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 13.000 | 6.300 | 415.500 | + | cpu/stage1/nopselmux/FE_RN_3_0 | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_RC_10_0/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 1 | 9.300 | 18.500 | 434.000 | + | cpu/stage1/nopselmux/FE_RN_5_0 | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_RC_11_0/Y | | A->Y | R | INVx6_ASAP7_75t_SL | 44 | 10.600 | 41.000 | 475.000 | + | cpu/stage1_inst[22] | | | R | (net) | 44 | | | | + | cpu/stage1/regfile/g80975/Y | | A->Y | F | INVx6_ASAP7_75t_SL | 19 | 59.400 | 17.000 | 492.000 | + | cpu/stage1/regfile/n_179 | | | F | (net) | 19 | | | | + | cpu/stage1/regfile/g79812/Y | | A->Y | R | NOR2xp33_ASAP7_75t_SL | 3 | 43.100 | 25.200 | 517.200 | + | cpu/stage1/regfile/n_342 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g79319/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 48.900 | 7.600 | 524.800 | + | cpu/stage1/regfile/n_341 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/g78502/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 7 | 18.200 | 87.600 | 612.400 | + | cpu/stage1/regfile/n_663 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g77792/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 198.700 | 19.900 | 632.300 | + | cpu/stage1/regfile/n_1348 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77156/Y | | C->Y | R | OAI211xp5_ASAP7_75t_SL | 1 | 70.600 | 22.500 | 654.800 | + | cpu/stage1/regfile/n_1953 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77066/Y | | C->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 41.200 | 16.500 | 671.300 | + | cpu/stage1/regfile/n_2043 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76942__5115/Y | | B->Y | R | OAI211xp5_ASAP7_75t_SL | 1 | 50.700 | 23.400 | 694.700 | + | cpu/stage1/rs2_mux_data[24] | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PSC4052_rs2_mux_data_24/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 1 | 48.400 | 27.000 | 721.700 | + | cpu/stage1/FE_PSN4052_rs2_mux_data_24 | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g552__5107/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 28.800 | 18.100 | 739.800 | + | cpu/stage1_rs2[24] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3587_stage1_rs2_24/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 13.700 | 11.400 | 751.200 | + | cpu/s1_to_s2_rs2/FE_PHN3587_stage1_rs2_24 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g445__6161/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.600 | 8.400 | 759.600 | + | cpu/s1_to_s2_rs2/n_6 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[24]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 66.700 | 0.300 | 759.600 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 33.600 | 882.300 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[24]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.100 | 1.700 | 882.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 28: MET (22.098 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 148.500 (P) 160.200 (P) + Arrival:= 909.500 21.200 + + Setup:- 4.802 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 804.698 + Launch Clock:= 21.200 + Data Path:+ 761.400 + Slack:= 22.098 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 18.400 | 398.500 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 4 | 17.400 | 18.100 | 416.600 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y | | A->Y | R | INVx4_ASAP7_75t_SL | 1 | 31.400 | 9.200 | 425.800 | + | cpu/stage1/regfile/FE_OFN1120_n | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 14.500 | 7.500 | 433.300 | + | cpu/stage1/regfile/FE_OFN1214_n | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/g80989/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 5 | 11.100 | 20.300 | 453.600 | + | cpu/stage1/regfile/n_171 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1093_n_171/Y | | A->Y | F | BUFx6f_ASAP7_75t_SL | 8 | 20.000 | 18.900 | 472.500 | + | cpu/stage1/regfile/FE_OFN1071_n_171 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/g79839/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 3 | 18.300 | 18.900 | 491.400 | + | cpu/stage1/regfile/n_311 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC797_n_311/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 3 | 11.900 | 9.500 | 500.900 | + | cpu/stage1/regfile/n_310 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g78360/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.000 | 11.000 | 511.900 | + | cpu/stage1/regfile/n_770 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77522/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 16.100 | 528.000 | + | cpu/stage1/regfile/n_1614 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77116/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 32.500 | 13.400 | 541.400 | + | cpu/stage1/regfile/n_1993 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76985__4319/Y | | A1->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 23.500 | 15.500 | 556.900 | + | cpu/stage1/regfile/n_2124 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76911__7098/Y | | A->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 26.200 | 12.400 | 569.300 | + | cpu/stage1/rs1_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g575__7410/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 25.100 | 20.800 | 590.100 | + | cpu/stage1_rs1[7] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1267__8246/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 16.800 | 606.900 | + | cpu/stage1/pcadder/n_38 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_L | 3 | 16.500 | 12.700 | 619.600 | + | 33_g1502__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_33 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 19.900 | 16.200 | 635.800 | + | 33_g1361__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_148 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 12.200 | 7.300 | 643.100 | + | 33_g1328__2802/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_176 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.700 | 13.400 | 656.500 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | R | BUFx2_ASAP7_75t_SL | 4 | 23.700 | 17.900 | 674.400 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | R | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0/Y | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 2 | 15.300 | 14.300 | 688.700 | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_18 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 25.000 | 14.000 | 702.700 | + | 33_g1295/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_203 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 21.800 | 9.400 | 712.100 | + | 33_g1288__1705/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_209 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 17.400 | 15.300 | 727.400 | + | 33_g1272__5107/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_218 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_18_0/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 30.600 | 12.500 | 739.900 | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_235 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 21.300 | 18.300 | 758.200 | + | 33_g1246__1617/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[19] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g947__9315/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.700 | 15.700 | 773.900 | + | cpu/stage1/stage1_pc_mux_to_pc[19] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g360__1881/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 15.000 | 8.700 | 782.600 | + | cpu/stage1/pcreg/n_20 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[19]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 46.400 | 0.100 | 782.600 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 33.500 | 909.500 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.200 | 6.400 | 909.500 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 29: MET (22.401 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[29]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 149.000 (P) 160.200 (P) + Arrival:= 910.000 21.200 + + Setup:- 4.699 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 805.301 + Launch Clock:= 21.200 + Data Path:+ 761.700 + Slack:= 22.401 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.700 | 401.000 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 4 | 17.300 | 20.200 | 421.200 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1209_stage1_inst_15/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 6 | 37.700 | 11.200 | 432.400 | + | cpu/stage1/regfile/FE_OFN1007_stage1_inst_15 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/FE_RC_2_0/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 20.200 | 14.700 | 447.100 | + | cpu/stage1/regfile/FE_RN_0_0 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_RC_3_0/Y | | A->Y | F | INVx6_ASAP7_75t_SL | 5 | 22.500 | 12.500 | 459.600 | + | cpu/stage1/regfile/n_211 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC991_n_211/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 1 | 19.600 | 8.200 | 467.800 | + | cpu/stage1/regfile/FE_OFN1087_n_211 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1195_n_211/Y | | A->Y | F | INVx8_ASAP7_75t_SL | 13 | 12.200 | 10.500 | 478.300 | + | cpu/stage1/regfile/FE_OFN1090_n_211 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79826/Y | | B->Y | F | AND2x6_ASAP7_75t_SL | 7 | 13.200 | 22.500 | 500.800 | + | cpu/stage1/regfile/n_326 | | | F | (net) | 7 | | | | + | cpu/stage1/regfile/g78423/Y | | B->Y | R | NAND2x2_ASAP7_75t_SL | 4 | 19.600 | 15.400 | 516.200 | + | cpu/stage1/regfile/n_788 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/g77789/Y | | A2->Y | F | OAI22x1_ASAP7_75t_SL | 1 | 28.200 | 12.500 | 528.700 | + | cpu/stage1/regfile/n_1351 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77281/Y | | A->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 19.700 | 8.600 | 537.300 | + | cpu/stage1/regfile/n_1848 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76866__1666/Y | | B->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 15.800 | 19.300 | 556.600 | + | cpu/stage1/rs1_mux_data[13] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g563__7098/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 38.200 | 25.700 | 582.300 | + | cpu/stage1_rs1[13] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1258__4319/Y | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 15.900 | 19.900 | 602.200 | + | cpu/stage1/pcadder/n_44 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 3 | 18.300 | 11.000 | 613.200 | + | 33_g1450__7098/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_77 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 2 | 18.700 | 8.200 | 621.400 | + | 33_g1353__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_158 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 14.200 | 17.500 | 638.900 | + | 33_g1318__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_186 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OA21x2_ASAP7_75t_SL | 2 | 33.100 | 19.900 | 658.800 | + | 33_g1305__9945/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_196 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0_dup/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 14.800 | 15.500 | 674.300 | + | cpu/stage1/pcadder/FE_RN_1 | | | F | (net) | 1 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 27.400 | 11.400 | 685.700 | + | 33_g1283__1617/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_19 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 20.300 | 9.000 | 694.700 | + | 33_g1275__4319/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_20 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | AO21x2_ASAP7_75t_SL | 2 | 12.500 | 18.100 | 712.800 | + | 33_g1257__7482/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_231 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 12.000 | 9.300 | 722.100 | + | 33_g1256/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_232 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 14.900 | 9.500 | 731.600 | + | 33_g1241__8428/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_246 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.800 | 14.000 | 745.600 | + | 33_g1238__5107/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[29] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g989__6783/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 1 | 18.400 | 14.100 | 759.700 | + | cpu/stage1/pcselmux/n_15 | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/FE_OCPC1474_n_15/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 12.600 | 7.900 | 767.600 | + | cpu/stage1/pcselmux/FE_RN_7_0 | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/FE_RC_15_0/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 11.900 | 6.700 | 774.300 | + | cpu/stage1/stage1_pc_mux_to_pc[29] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g350__5526/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 16.900 | 8.600 | 782.900 | + | cpu/stage1/pcreg/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[29]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 45.400 | 0.000 | 782.900 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 34.000 | 910.000 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[29]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.200 | 6.900 | 910.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 30: MET (22.659 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[23]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 148.300 (P) 160.200 (P) + Arrival:= 909.300 21.200 + + Setup:- 4.741 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 804.559 + Launch Clock:= 21.200 + Data Path:+ 760.700 + Slack:= 22.659 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 18.400 | 398.500 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 4 | 17.400 | 18.100 | 416.600 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y | | A->Y | R | INVx4_ASAP7_75t_SL | 1 | 31.400 | 9.200 | 425.800 | + | cpu/stage1/regfile/FE_OFN1120_n | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 14.500 | 7.500 | 433.300 | + | cpu/stage1/regfile/FE_OFN1214_n | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/g80989/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 5 | 11.100 | 20.300 | 453.600 | + | cpu/stage1/regfile/n_171 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1093_n_171/Y | | A->Y | F | BUFx6f_ASAP7_75t_SL | 8 | 20.000 | 18.900 | 472.500 | + | cpu/stage1/regfile/FE_OFN1071_n_171 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/g79839/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 3 | 18.300 | 18.900 | 491.400 | + | cpu/stage1/regfile/n_311 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC797_n_311/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 3 | 11.900 | 9.500 | 500.900 | + | cpu/stage1/regfile/n_310 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g78360/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.000 | 11.000 | 511.900 | + | cpu/stage1/regfile/n_770 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77522/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 16.100 | 528.000 | + | cpu/stage1/regfile/n_1614 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77116/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 32.500 | 13.400 | 541.400 | + | cpu/stage1/regfile/n_1993 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76985__4319/Y | | A1->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 23.500 | 15.500 | 556.900 | + | cpu/stage1/regfile/n_2124 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76911__7098/Y | | A->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 26.200 | 12.400 | 569.300 | + | cpu/stage1/rs1_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g575__7410/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 25.100 | 20.800 | 590.100 | + | cpu/stage1_rs1[7] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1267__8246/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 16.800 | 606.900 | + | cpu/stage1/pcadder/n_38 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_L | 3 | 16.500 | 12.700 | 619.600 | + | 33_g1502__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_33 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 19.900 | 16.200 | 635.800 | + | 33_g1361__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_148 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 12.200 | 7.300 | 643.100 | + | 33_g1328__2802/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_176 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.700 | 13.400 | 656.500 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | R | BUFx2_ASAP7_75t_SL | 4 | 23.700 | 17.900 | 674.400 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | R | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0/Y | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 2 | 15.300 | 14.300 | 688.700 | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_18 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 25.000 | 19.400 | 708.100 | + | 33_g1280__3680/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_213 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 36.000 | 13.000 | 721.100 | + | 33_g1270__5477/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_220 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 19.700 | 13.600 | 734.700 | + | 33_g1255__5115/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_233 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 28.000 | 7.200 | 741.900 | + | 33_g1242__5526/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_245 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 14.100 | 15.900 | 757.800 | + | 33_g1239__6260/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[23] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g933__6783/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 18.300 | 15.700 | 773.500 | + | cpu/stage1/stage1_pc_mux_to_pc[23] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g364__6161/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 14.900 | 8.400 | 781.900 | + | cpu/stage1/pcreg/n_16 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[23]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 45.900 | 0.000 | 781.900 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 33.300 | 909.300 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[23]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.100 | 6.200 | 909.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 31: MET (22.723 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 140.200 (P) 160.200 (P) + Arrival:= 901.200 21.200 + + Setup:- 3.776 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 797.424 + Launch Clock:= 21.200 + Data Path:+ 753.500 + Slack:= 22.723 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1549/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 1 | 33.200 | 20.100 | 550.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_206 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1547/Y | | B->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 11.000 | 12.600 | 562.700 | + | cpu/stage2/alu/n_306 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5665/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 12.600 | 8.100 | 570.800 | + | cpu/stage2/alu/n_56 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5522/Y | | A->Y | F | NAND3xp33_ASAP7_75t_SL | 2 | 33.300 | 42.000 | 612.800 | + | dcache_addr[15] | | | F | (net) | 2 | | | | + | cpu/FE_PHC2730_dcache_addr_15/Y | | A->Y | F | HB3xp67_ASAP7_75t_SL | 3 | 94.800 | 76.000 | 688.800 | + | cpu/FE_PHN2730_dcache_addr_15 | | | F | (net) | 3 | | | | + | cpu/stage3/csr/g180/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 63.400 | 17.200 | 706.000 | + | cpu/stage3/csr/FE_PHN2799_n_15 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2799_n_15/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 50.000 | 68.700 | 774.700 | + | cpu/stage3/csr/n_15 | | | R | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[15]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.200 | 0.400 | 774.700 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 31.800 | 901.200 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[15]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.300 | 2.500 | 901.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 32: MET (23.236 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 125.000 (P) 160.200 (P) + Arrival:= 886.000 21.200 + + Setup:- 6.164 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.836 + Launch Clock:= 21.200 + Data Path:+ 735.400 + Slack:= 23.236 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 28.700 | 501.300 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79863/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 28 | 49.900 | 90.200 | 591.500 | + | cpu/stage1/regfile/n_272 | | | F | (net) | 28 | | | | + | cpu/stage1/regfile/g77956/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 133.000 | 28.300 | 619.800 | + | cpu/stage1/regfile/n_1183 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77455/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 14.500 | 15.500 | 635.300 | + | cpu/stage1/regfile/n_1681 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77174/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 59.600 | 20.100 | 655.400 | + | cpu/stage1/regfile/n_1941 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77019/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 41.900 | 15.100 | 670.500 | + | cpu/stage1/regfile/n_2090 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76938__8246/Y | | C->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 26.000 | 18.800 | 689.300 | + | cpu/stage1/rs2_mux_data[15] | | | F | (net) | 1 | | | | + | cpu/stage1/FE_PHC4116_rs2_mux_data_15/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 41.700 | 28.300 | 717.600 | + | cpu/stage1/FE_PHN4116_rs2_mux_data_15 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g545__2883/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 13.600 | 17.600 | 735.200 | + | cpu/stage1_rs2[15] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3597_stage1_rs2_15/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 13.400 | 13.600 | 748.800 | + | cpu/s1_to_s2_rs2/FE_PHN3597_stage1_rs2_15 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g450__1666/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 8.600 | 7.800 | 756.600 | + | cpu/s1_to_s2_rs2/n_1 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[15]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 59.700 | 0.100 | 756.600 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.300 | 886.000 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[15]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 5.400 | 886.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 33: MET (24.331 ps) Setup Check with Pin mem/dcache/STATE_reg[1]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) mem/dcache/STATE_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 140.800 (P) 160.200 (P) + Arrival:= 901.800 21.200 + + Setup:- 8.169 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 793.631 + Launch Clock:= 21.200 + Data Path:+ 748.100 + Slack:= 24.331 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.300 | 179.500 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2349/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.500 | 192.000 | + | cpu/stage3/ldselmux/n_97 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2313/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 23.800 | 17.900 | 209.900 | + | cpu/stage3/wb_dmem[5] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1109/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 51.100 | 17.800 | 227.700 | + | cpu/wb_data[5] | | | R | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g550/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 5 | 19.800 | 23.100 | 250.800 | + | cpu/stage2/stage2_rs1_data[5] | | | R | (net) | 5 | | | | + | cpu/stage2/aselmux/g549/Y | | A1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 30.400 | 17.400 | 268.200 | + | cpu/stage2/stage2_alu_in1[5] | | | R | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC821_stage2_alu_in1_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 14.800 | 9.100 | 277.300 | + | cpu/stage2/alu/FE_DBTN72_stage2_alu_in1_5 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC823_stage2_alu_in1_5/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 9 | 13.500 | 34.700 | 312.000 | + | cpu/stage2/alu/FE_OFN957_stage2_alu_in1_5 | | | R | (net) | 9 | | | | + | cpu/stage2/alu/FE_OFC825_stage2_alu_in1_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 5 | 71.900 | 19.400 | 331.400 | + | cpu/stage2/alu/FE_OFN959_stage2_alu_in1_5 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/lt_30_22_g1493/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 4 | 35.800 | 20.700 | 352.100 | + | cpu/stage2/alu/lt_30_22_n_37 | | | F | (net) | 4 | | | | + | cpu/stage2/alu/lt_29_31_g1466/Y | | A1->Y | R | OAI32xp33_ASAP7_75t_SL | 1 | 12.400 | 14.200 | 366.300 | + | cpu/stage2/alu/lt_29_31_n_63 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1465/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 55.100 | 6.700 | 373.000 | + | cpu/stage2/alu/lt_29_31_n_64 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1451/Y | | C1->Y | R | OAI322xp33_ASAP7_75t_SL | 1 | 18.400 | 16.000 | 389.000 | + | cpu/stage2/alu/lt_29_31_n_78 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1444/Y | | B->Y | F | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 46.900 | 17.300 | 406.300 | + | cpu/stage2/alu/lt_29_31_n_85 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1443/Y | | A1->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 35.500 | 32.200 | 438.500 | + | cpu/stage2/alu/lt_29_31_n_86 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1442/Y | | A1->Y | F | AOI321xp33_ASAP7_75t_SL | 1 | 67.200 | 36.700 | 475.200 | + | cpu/stage2/alu/n_324 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5667/Y | | B1->Y | R | AOI33xp33_ASAP7_75t_SL | 1 | 68.000 | 30.300 | 505.500 | + | cpu/stage2/alu/n_54 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5520/Y | | A2->Y | F | OAI211xp5_ASAP7_75t_SL | 1 | 53.400 | 19.300 | 524.800 | + | cpu/stage2/alu/n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5502/Y | | C->Y | F | AO221x2_ASAP7_75t_SL | 9 | 43.500 | 52.300 | 577.100 | + | cpu/stage2_alu_out[0] | | | F | (net) | 9 | | | | + | cpu/stage3/memrw/g432/Y | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 56.900 | 16.900 | 594.000 | + | cpu/stage3/memrw/n_6 | | | R | (net) | 2 | | | | + | cpu/stage3/memrw/g425/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 3 | 31.900 | 19.800 | 613.800 | + | dcache_we[1] | | | F | (net) | 3 | | | | + | mem/g31/Y | | B->Y | F | OR5x1_ASAP7_75t_SL | 3 | 42.400 | 50.300 | 664.100 | + | mem/n_317 | | | F | (net) | 3 | | | | + | mem/dcache/g14019/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 5 | 46.900 | 29.700 | 693.800 | + | mem/dcache/n_316 | | | R | (net) | 5 | | | | + | mem/dcache/g14016/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 47.800 | 17.400 | 711.200 | + | mem/dcache/n_99 | | | F | (net) | 2 | | | | + | mem/dcache/g13751/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 4 | 29.800 | 28.400 | 739.600 | + | mem/dc_mem_req_rw | | | R | (net) | 4 | | | | + | mem/dcache/g13730/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 52.700 | 14.500 | 754.100 | + | mem/dcache/n_314 | | | F | (net) | 2 | | | | + | mem/dcache/g11166/Y | | B->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 28.700 | 15.200 | 769.300 | + | mem/dcache/n_81 | | | R | (net) | 1 | | | | + | mem/dcache/STATE_reg[1]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 41.900 | 0.100 | 769.300 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 42.100 | 867.800 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 39.600 | 34.000 | 901.800 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[1]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 3 | 24.000 | 0.200 | 901.800 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 34: MET (24.409 ps) Setup Check with Pin mem/dcache/STATE_reg[2]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) mem/dcache/STATE_reg[2]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 140.800 (P) 160.200 (P) + Arrival:= 901.800 21.200 + + Setup:- 4.391 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 797.409 + Launch Clock:= 21.200 + Data Path:+ 751.800 + Slack:= 24.409 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.300 | 179.500 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2349/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.500 | 192.000 | + | cpu/stage3/ldselmux/n_97 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2313/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 23.800 | 17.900 | 209.900 | + | cpu/stage3/wb_dmem[5] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1109/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 51.100 | 17.800 | 227.700 | + | cpu/wb_data[5] | | | R | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g550/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 5 | 19.800 | 23.100 | 250.800 | + | cpu/stage2/stage2_rs1_data[5] | | | R | (net) | 5 | | | | + | cpu/stage2/aselmux/g549/Y | | A1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 30.400 | 17.400 | 268.200 | + | cpu/stage2/stage2_alu_in1[5] | | | R | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC821_stage2_alu_in1_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 14.800 | 9.100 | 277.300 | + | cpu/stage2/alu/FE_DBTN72_stage2_alu_in1_5 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC823_stage2_alu_in1_5/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 9 | 13.500 | 34.700 | 312.000 | + | cpu/stage2/alu/FE_OFN957_stage2_alu_in1_5 | | | R | (net) | 9 | | | | + | cpu/stage2/alu/FE_OFC825_stage2_alu_in1_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 5 | 71.900 | 19.400 | 331.400 | + | cpu/stage2/alu/FE_OFN959_stage2_alu_in1_5 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/lt_30_22_g1493/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 4 | 35.800 | 20.700 | 352.100 | + | cpu/stage2/alu/lt_30_22_n_37 | | | F | (net) | 4 | | | | + | cpu/stage2/alu/lt_29_31_g1466/Y | | A1->Y | R | OAI32xp33_ASAP7_75t_SL | 1 | 12.400 | 14.200 | 366.300 | + | cpu/stage2/alu/lt_29_31_n_63 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1465/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 55.100 | 6.700 | 373.000 | + | cpu/stage2/alu/lt_29_31_n_64 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1451/Y | | C1->Y | R | OAI322xp33_ASAP7_75t_SL | 1 | 18.400 | 16.000 | 389.000 | + | cpu/stage2/alu/lt_29_31_n_78 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1444/Y | | B->Y | F | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 46.900 | 17.300 | 406.300 | + | cpu/stage2/alu/lt_29_31_n_85 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1443/Y | | A1->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 35.500 | 32.200 | 438.500 | + | cpu/stage2/alu/lt_29_31_n_86 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/lt_29_31_g1442/Y | | A1->Y | F | AOI321xp33_ASAP7_75t_SL | 1 | 67.200 | 36.700 | 475.200 | + | cpu/stage2/alu/n_324 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5667/Y | | B1->Y | R | AOI33xp33_ASAP7_75t_SL | 1 | 68.000 | 30.300 | 505.500 | + | cpu/stage2/alu/n_54 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5520/Y | | A2->Y | F | OAI211xp5_ASAP7_75t_SL | 1 | 53.400 | 19.300 | 524.800 | + | cpu/stage2/alu/n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5502/Y | | C->Y | F | AO221x2_ASAP7_75t_SL | 9 | 43.500 | 52.300 | 577.100 | + | cpu/stage2_alu_out[0] | | | F | (net) | 9 | | | | + | cpu/stage3/memrw/g432/Y | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 56.900 | 16.900 | 594.000 | + | cpu/stage3/memrw/n_6 | | | R | (net) | 2 | | | | + | cpu/stage3/memrw/g425/Y | | A1->Y | F | OAI31xp33_ASAP7_75t_SL | 3 | 31.900 | 19.800 | 613.800 | + | dcache_we[1] | | | F | (net) | 3 | | | | + | mem/g31/Y | | B->Y | F | OR5x1_ASAP7_75t_SL | 3 | 42.400 | 50.300 | 664.100 | + | mem/n_317 | | | F | (net) | 3 | | | | + | mem/dcache/g14019/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 5 | 46.900 | 29.700 | 693.800 | + | mem/dcache/n_316 | | | R | (net) | 5 | | | | + | mem/dcache/g14016/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 47.800 | 17.400 | 711.200 | + | mem/dcache/n_99 | | | F | (net) | 2 | | | | + | mem/dcache/g13751/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 4 | 29.800 | 28.800 | 740.000 | + | mem/dc_mem_req_rw | | | R | (net) | 4 | | | | + | mem/dcache/FE_OFC439_dc_mem_req_rw/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 52.700 | 6.400 | 746.400 | + | mem/dcache/n_2 | | | F | (net) | 1 | | | | + | mem/dcache/g11190/Y | | B->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 17.800 | 10.700 | 757.100 | + | mem/dcache/n_57 | | | R | (net) | 1 | | | | + | mem/dcache/FE_PHC3589_n_57/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 37.900 | 15.900 | 773.000 | + | mem/dcache/FE_PHN3589_n_57 | | | R | (net) | 1 | | | | + | mem/dcache/STATE_reg[2]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 11.700 | 0.000 | 773.000 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 42.100 | 867.800 | + | CTS_2 | | | R | (net) | 3 | | | | + | mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SRAM | 3 | 39.600 | 34.000 | 901.800 | + | GCLK | | | | | | | | | + | mem/dcache/CLKGATE_rc_gclk | | | R | (net) | 3 | | | | + | mem/dcache/STATE_reg[2]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 3 | 24.000 | 0.200 | 901.800 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 35: MET (24.464 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 146.700 (P) 160.200 (P) + Arrival:= 907.700 21.200 + + Setup:- 4.736 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 802.964 + Launch Clock:= 21.200 + Data Path:+ 757.300 + Slack:= 24.464 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 18.400 | 398.500 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 4 | 17.400 | 18.100 | 416.600 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y | | A->Y | R | INVx4_ASAP7_75t_SL | 1 | 31.400 | 9.200 | 425.800 | + | cpu/stage1/regfile/FE_OFN1120_n | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 14.500 | 7.500 | 433.300 | + | cpu/stage1/regfile/FE_OFN1214_n | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/g80989/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 5 | 11.100 | 20.300 | 453.600 | + | cpu/stage1/regfile/n_171 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1093_n_171/Y | | A->Y | F | BUFx6f_ASAP7_75t_SL | 8 | 20.000 | 18.900 | 472.500 | + | cpu/stage1/regfile/FE_OFN1071_n_171 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/g79839/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 3 | 18.300 | 18.900 | 491.400 | + | cpu/stage1/regfile/n_311 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC797_n_311/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 3 | 11.900 | 9.500 | 500.900 | + | cpu/stage1/regfile/n_310 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g78360/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.000 | 11.000 | 511.900 | + | cpu/stage1/regfile/n_770 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77522/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 16.100 | 528.000 | + | cpu/stage1/regfile/n_1614 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77116/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 32.500 | 13.400 | 541.400 | + | cpu/stage1/regfile/n_1993 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76985__4319/Y | | A1->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 23.500 | 15.500 | 556.900 | + | cpu/stage1/regfile/n_2124 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76911__7098/Y | | A->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 26.200 | 12.400 | 569.300 | + | cpu/stage1/rs1_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g575__7410/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 25.100 | 20.800 | 590.100 | + | cpu/stage1_rs1[7] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1267__8246/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 16.800 | 606.900 | + | cpu/stage1/pcadder/n_38 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_L | 3 | 16.500 | 12.700 | 619.600 | + | 33_g1502__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_33 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 19.900 | 16.200 | 635.800 | + | 33_g1361__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_148 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 12.200 | 7.300 | 643.100 | + | 33_g1328__2802/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_176 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.700 | 13.400 | 656.500 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | R | BUFx2_ASAP7_75t_SL | 4 | 23.700 | 18.000 | 674.500 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | R | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 15.300 | 8.100 | 682.600 | + | 33_g1310/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_193 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.800 | 12.200 | 694.800 | + | 33_g1299__5115/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_202 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 23.000 | 9.900 | 704.700 | + | 33_g1290__5122/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_207 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 14.300 | 17.600 | 722.300 | + | 33_g1273__6260/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_217 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 34.800 | 13.600 | 735.900 | + | 33_g1254__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_234 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 24.100 | 17.400 | 753.300 | + | 33_g1247__2802/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[15] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g934__3680/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 18.800 | 16.300 | 769.600 | + | cpu/stage1/stage1_pc_mux_to_pc[15] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g355__1705/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 15.500 | 8.900 | 778.500 | + | cpu/stage1/pcreg/n_25 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[15]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 45.800 | 0.100 | 778.500 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 31.700 | 907.700 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[15]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.600 | 4.600 | 907.700 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 36: MET (24.517 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[28]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage3/csr/csr_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.500 (P) 160.800 (P) + Arrival:= 900.500 21.800 + + Setup:- -3.916 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 804.416 + Launch Clock:= 21.800 + Data Path:+ 758.100 + Slack:= 24.517 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.800 | 21.800 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[3]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 50.100 | 71.900 | + | cpu/stage3_inst[3] | | | R | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OCPC1470_stage3_inst_3/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 2 | 10.500 | 4.600 | 76.500 | + | cpu/stage3/ldsel/FE_OCPN1434_stage3_inst_3 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_RC_26_0/Y | | B->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 6.000 | 5.300 | 81.800 | + | cpu/stage3/ldsel/FE_RN_10_0 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/FE_RC_27_0/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 16.200 | 6.500 | 88.300 | + | cpu/stage3/ldsel/n_10 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g208/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 1 | 9.800 | 7.100 | 95.400 | + | cpu/stage3/ldsel/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g205/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 4 | 16.800 | 17.600 | 113.000 | + | cpu/stage3/LdSelect[0] | | | R | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y | | A->Y | F | INVx3_ASAP7_75t_SL | 1 | 16.000 | 6.300 | 119.300 | + | cpu/stage3/ldselmux/n_14 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 9.300 | 7.400 | 126.700 | + | cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 | | | R | (net) | 5 | | | | + | cpu/stage3/ldselmux/g2426/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 10.600 | 12.600 | 139.300 | + | cpu/stage3/ldselmux/n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/FE_OCPC1515_n_30/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 2 | 8.400 | 11.600 | 150.900 | + | cpu/stage3/ldselmux/FE_OCPN1476_n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/g2399/Y | | A2->Y | F | AOI21x1_ASAP7_75t_SL | 7 | 7.800 | 15.700 | 166.600 | + | cpu/stage3/ldselmux/n_62 | | | F | (net) | 7 | | | | + | cpu/stage3/ldselmux/g2354/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 31.000 | 15.700 | 182.300 | + | cpu/stage3/ldselmux/n_92 | | | R | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | F | OAI221xp5_ASAP7_75t_SL | 1 | 25.100 | 15.700 | 198.000 | + | cpu/stage3/wb_dmem[0] | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | F | AO21x1_ASAP7_75t_SL | 3 | 28.200 | 22.300 | 220.300 | + | cpu/wb_data[0] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 4 | 15.500 | 23.200 | 243.500 | + | cpu/stage2/stage2_rs2_data[0] | | | F | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 18.500 | 10.300 | 253.800 | + | cpu/stage2/bselmux/n_6 | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 2 | 25.000 | 23.800 | 277.600 | + | cpu/stage2/stage2_alu_in2[0] | | | R | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 24 | 28.000 | 16.300 | 293.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | F | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 5 | 29.700 | 29.900 | 323.800 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | F | XNOR2xp5_ASAP7_75t_SL | 2 | 33.500 | 25.800 | 349.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | R | MAJIxp5_ASAP7_75t_SL | 2 | 33.200 | 23.900 | 373.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 44.100 | 19.200 | 392.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 15.700 | 408.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 3 | 13.100 | 16.700 | 425.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | F | OAI311xp33_ASAP7_75t_SL | 1 | 14.900 | 9.900 | 435.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 27.900 | 13.600 | 448.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 20.800 | 16.700 | 465.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 11.900 | 14.500 | 479.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 11.000 | 8.800 | 488.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 16.000 | 20.900 | 509.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | R | AOI31xp67_ASAP7_75t_SL | 3 | 15.700 | 15.200 | 524.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 30.500 | 10.200 | 534.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 32.200 | 26.200 | 561.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 20.400 | 17.700 | 578.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | R | NAND2x1_ASAP7_75t_SL | 2 | 13.200 | 10.700 | 589.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 20.400 | 9.300 | 598.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | R | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 36.500 | 16.100 | 614.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 27.700 | 12.200 | 627.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 19.200 | 19.500 | 646.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 16.700 | 10.700 | 657.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 19.400 | 16.500 | 673.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1511/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 12.600 | 16.900 | 690.700 | + | cpu/stage2/alu/n_319 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5508/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 22.700 | 30.200 | 720.900 | + | dcache_addr[28] | | | R | (net) | 4 | | | | + | cpu/stage3/csr/g190/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 47.900 | 17.700 | 738.600 | + | cpu/stage3/csr/n_5 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2779_n_5/Y | | A->Y | F | HB3xp67_ASAP7_75t_SL | 1 | 66.900 | 41.300 | 779.900 | + | cpu/stage3/csr/FE_PHN2779_n_5 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[28]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 16.200 | 0.000 | 779.900 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 31.100 | 900.500 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[28]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.100 | 1.800 | 900.500 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 37: MET (24.870 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage3/csr/csr_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.200 (P) 160.200 (P) + Arrival:= 900.200 21.200 + + Setup:- -2.370 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 802.570 + Launch Clock:= 21.200 + Data Path:+ 756.500 + Slack:= 24.870 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1545/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 2 | 23.000 | 15.000 | 580.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_210 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1540/Y | | A1->Y | F | AOI21xp5_ASAP7_75t_SL | 2 | 9.100 | 12.100 | 592.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_215 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1533/Y | | A2->Y | R | OAI21xp5_ASAP7_75t_SL | 1 | 22.800 | 14.500 | 607.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_222 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1528/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 31.300 | 17.000 | 624.200 | + | cpu/stage2/alu/n_310 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5523/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 19.300 | 31.600 | 655.800 | + | dcache_addr[19] | | | R | (net) | 4 | | | | + | cpu/stage3/csr/g183/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 51.300 | 9.800 | 665.600 | + | cpu/stage3/csr/FE_PHN2759_n_12 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC3573_n_12/Y | | A->Y | F | HB3xp67_ASAP7_75t_SL | 1 | 55.700 | 40.800 | 706.400 | + | cpu/stage3/csr/FE_PHN3573_n_12 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2759_n_12/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 17.600 | 71.300 | 777.700 | + | cpu/stage3/csr/n_12 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[19]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 26.700 | 0.300 | 777.700 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 30.800 | 900.200 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.200 | 1.500 | 900.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 38: MET (25.620 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[18]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[18]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 123.600 (P) 160.200 (P) + Arrival:= 884.600 21.200 + + Setup:- 6.080 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 778.520 + Launch Clock:= 21.200 + Data Path:+ 731.700 + Slack:= 25.620 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 30.100 | 502.700 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/FE_OFC643_n_237/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 50.100 | 9.500 | 512.200 | + | cpu/stage1/regfile/FE_OFN834_n_237 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g79821/Y | | B->Y | F | NOR2xp33_ASAP7_75t_L | 6 | 17.300 | 75.000 | 587.200 | + | cpu/stage1/regfile/n_332 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g77926/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 145.700 | 33.300 | 620.500 | + | cpu/stage1/regfile/n_1213 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77310/Y | | B->Y | F | NAND3xp33_ASAP7_75t_SL | 1 | 59.400 | 10.200 | 630.700 | + | cpu/stage1/regfile/n_1819 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77010/Y | | A2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 27.000 | 12.500 | 643.200 | + | cpu/stage1/regfile/n_2099 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC4041_n_2099/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 65.500 | 17.100 | 660.300 | + | cpu/stage1/regfile/FE_PHN4041_n_2099 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76915__7482/Y | | C->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 9.000 | 33.100 | 693.400 | + | cpu/stage1/rs2_mux_data[18] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3941_rs2_mux_data_18/ | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 73.100 | 22.200 | 715.600 | + | Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_PHN3941_rs2_mux_data_18 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g548__7410/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 9.200 | 17.700 | 733.300 | + | cpu/stage1_rs2[18] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3584_stage1_rs2_18/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 14.200 | 12.700 | 746.000 | + | cpu/s1_to_s2_rs2/FE_PHN3584_stage1_rs2_18 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g439__7098/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.400 | 6.900 | 752.900 | + | cpu/s1_to_s2_rs2/n_12 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[18]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 58.800 | 0.100 | 752.900 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 35.900 | 884.600 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[18]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.600 | 4.000 | 884.600 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 39: MET (25.828 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[21]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 148.200 (P) 160.200 (P) + Arrival:= 909.200 21.200 + + Setup:- 4.772 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 804.428 + Launch Clock:= 21.200 + Data Path:+ 757.400 + Slack:= 25.828 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 18.400 | 398.500 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 4 | 17.400 | 18.100 | 416.600 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y | | A->Y | R | INVx4_ASAP7_75t_SL | 1 | 31.400 | 9.200 | 425.800 | + | cpu/stage1/regfile/FE_OFN1120_n | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 14.500 | 7.500 | 433.300 | + | cpu/stage1/regfile/FE_OFN1214_n | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/g80989/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 5 | 11.100 | 20.300 | 453.600 | + | cpu/stage1/regfile/n_171 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1093_n_171/Y | | A->Y | F | BUFx6f_ASAP7_75t_SL | 8 | 20.000 | 18.900 | 472.500 | + | cpu/stage1/regfile/FE_OFN1071_n_171 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/g79839/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 3 | 18.300 | 18.900 | 491.400 | + | cpu/stage1/regfile/n_311 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC797_n_311/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 3 | 11.900 | 9.500 | 500.900 | + | cpu/stage1/regfile/n_310 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g78360/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.000 | 11.000 | 511.900 | + | cpu/stage1/regfile/n_770 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77522/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 16.100 | 528.000 | + | cpu/stage1/regfile/n_1614 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77116/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 32.500 | 13.400 | 541.400 | + | cpu/stage1/regfile/n_1993 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76985__4319/Y | | A1->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 23.500 | 15.500 | 556.900 | + | cpu/stage1/regfile/n_2124 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76911__7098/Y | | A->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 26.200 | 12.400 | 569.300 | + | cpu/stage1/rs1_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g575__7410/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 25.100 | 20.800 | 590.100 | + | cpu/stage1_rs1[7] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1267__8246/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 16.800 | 606.900 | + | cpu/stage1/pcadder/n_38 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_L | 3 | 16.500 | 12.700 | 619.600 | + | 33_g1502__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_33 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 19.900 | 16.200 | 635.800 | + | 33_g1361__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_148 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 12.200 | 7.300 | 643.100 | + | 33_g1328__2802/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_176 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.700 | 13.400 | 656.500 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | R | BUFx2_ASAP7_75t_SL | 4 | 23.700 | 17.900 | 674.400 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | R | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0/Y | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 2 | 15.300 | 14.300 | 688.700 | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_18 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 25.000 | 19.400 | 708.100 | + | 33_g1280__3680/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_213 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 36.000 | 13.000 | 721.100 | + | 33_g1270__5477/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_220 | | | | | | | | | + | cpu/stage1/pcadder/FE_OFC530_add_18_35_Y_add_17_34 | | A->Y | R | INVx1_ASAP7_75t_SL | 1 | 19.700 | 6.900 | 728.000 | + | _Y_add_16_33_n_220/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_221 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NAND2xp5_ASAP7_75t_L | 1 | 10.100 | 10.100 | 738.100 | + | 33_g1261__9945/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_227 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 19.200 | 16.800 | 754.900 | + | 33_g1250__8246/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[21] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g940__7098/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 15.600 | 15.200 | 770.100 | + | cpu/stage1/stage1_pc_mux_to_pc[21] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g347__6260/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 14.900 | 8.500 | 778.600 | + | cpu/stage1/pcreg/n_33 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[21]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 46.100 | 0.000 | 778.600 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 33.200 | 909.200 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[21]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.100 | 6.100 | 909.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 40: MET (26.565 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage3/csr/csr_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 139.300 (P) 160.800 (P) + Arrival:= 900.300 21.800 + + Setup:- -3.665 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 803.965 + Launch Clock:= 21.800 + Data Path:+ 755.600 + Slack:= 26.565 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.800 | 21.800 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[3]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 50.100 | 71.900 | + | cpu/stage3_inst[3] | | | R | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OCPC1470_stage3_inst_3/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 2 | 10.500 | 4.600 | 76.500 | + | cpu/stage3/ldsel/FE_OCPN1434_stage3_inst_3 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_RC_26_0/Y | | B->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 6.000 | 5.300 | 81.800 | + | cpu/stage3/ldsel/FE_RN_10_0 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/FE_RC_27_0/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 16.200 | 6.500 | 88.300 | + | cpu/stage3/ldsel/n_10 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g208/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 1 | 9.800 | 7.100 | 95.400 | + | cpu/stage3/ldsel/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g205/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 4 | 16.800 | 17.600 | 113.000 | + | cpu/stage3/LdSelect[0] | | | R | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y | | A->Y | F | INVx3_ASAP7_75t_SL | 1 | 16.000 | 6.300 | 119.300 | + | cpu/stage3/ldselmux/n_14 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 9.300 | 7.400 | 126.700 | + | cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 | | | R | (net) | 5 | | | | + | cpu/stage3/ldselmux/g2426/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 10.600 | 12.600 | 139.300 | + | cpu/stage3/ldselmux/n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/FE_OCPC1515_n_30/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 2 | 8.400 | 11.600 | 150.900 | + | cpu/stage3/ldselmux/FE_OCPN1476_n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/g2399/Y | | A2->Y | F | AOI21x1_ASAP7_75t_SL | 7 | 7.800 | 15.700 | 166.600 | + | cpu/stage3/ldselmux/n_62 | | | F | (net) | 7 | | | | + | cpu/stage3/ldselmux/g2354/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 31.000 | 15.700 | 182.300 | + | cpu/stage3/ldselmux/n_92 | | | R | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | F | OAI221xp5_ASAP7_75t_SL | 1 | 25.100 | 15.700 | 198.000 | + | cpu/stage3/wb_dmem[0] | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | F | AO21x1_ASAP7_75t_SL | 3 | 28.200 | 22.300 | 220.300 | + | cpu/wb_data[0] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 4 | 15.500 | 23.200 | 243.500 | + | cpu/stage2/stage2_rs2_data[0] | | | F | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 18.500 | 10.300 | 253.800 | + | cpu/stage2/bselmux/n_6 | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 2 | 25.000 | 23.800 | 277.600 | + | cpu/stage2/stage2_alu_in2[0] | | | R | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 24 | 28.000 | 16.300 | 293.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | F | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 5 | 29.700 | 29.900 | 323.800 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | F | XNOR2xp5_ASAP7_75t_SL | 2 | 33.500 | 25.800 | 349.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | R | MAJIxp5_ASAP7_75t_SL | 2 | 33.200 | 23.900 | 373.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 44.100 | 19.200 | 392.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 15.700 | 408.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 3 | 13.100 | 16.700 | 425.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | F | OAI311xp33_ASAP7_75t_SL | 1 | 14.900 | 9.900 | 435.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 27.900 | 13.600 | 448.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 20.800 | 16.700 | 465.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 11.900 | 14.500 | 479.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 11.000 | 8.800 | 488.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 16.000 | 20.900 | 509.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | R | AOI31xp67_ASAP7_75t_SL | 3 | 15.700 | 15.200 | 524.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 30.500 | 10.200 | 534.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 32.200 | 26.200 | 561.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 20.400 | 17.700 | 578.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | R | NAND2x1_ASAP7_75t_SL | 2 | 13.200 | 10.700 | 589.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 20.400 | 9.300 | 598.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | R | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 36.500 | 16.100 | 614.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 27.700 | 12.200 | 627.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 19.200 | 19.500 | 646.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 16.700 | 10.700 | 657.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1514/Y | | B->Y | R | XNOR2xp5_ASAP7_75t_SL | 1 | 19.400 | 13.200 | 670.500 | + | cpu/stage2/alu/n_318 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5512/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 24.700 | 28.600 | 699.100 | + | dcache_addr[27] | | | R | (net) | 4 | | | | + | cpu/stage3/csr/g168/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 43.500 | 16.500 | 715.600 | + | cpu/stage3/csr/n_27 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2781_n_27/Y | | A->Y | F | HB4xp67_ASAP7_75t_L | 1 | 65.900 | 61.800 | 777.400 | + | cpu/stage3/csr/FE_PHN2781_n_27 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[27]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 18.300 | 0.000 | 777.400 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 30.900 | 900.300 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[27]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.100 | 1.600 | 900.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 41: MET (26.995 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 151.200 (P) 160.200 (P) + Arrival:= 912.200 21.200 + + Setup:- -3.795 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 815.995 + Launch Clock:= 21.200 + Data Path:+ 767.800 + Slack:= 26.995 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 18.400 | 398.500 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 4 | 17.400 | 18.100 | 416.600 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y | | A->Y | R | INVx4_ASAP7_75t_SL | 1 | 31.400 | 9.200 | 425.800 | + | cpu/stage1/regfile/FE_OFN1120_n | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 14.500 | 7.500 | 433.300 | + | cpu/stage1/regfile/FE_OFN1214_n | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/g80989/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 5 | 11.100 | 20.300 | 453.600 | + | cpu/stage1/regfile/n_171 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1093_n_171/Y | | A->Y | F | BUFx6f_ASAP7_75t_SL | 8 | 20.000 | 18.900 | 472.500 | + | cpu/stage1/regfile/FE_OFN1071_n_171 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/g79839/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 3 | 18.300 | 18.900 | 491.400 | + | cpu/stage1/regfile/n_311 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC797_n_311/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 3 | 11.900 | 9.500 | 500.900 | + | cpu/stage1/regfile/n_310 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g78360/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.000 | 11.000 | 511.900 | + | cpu/stage1/regfile/n_770 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77522/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 16.100 | 528.000 | + | cpu/stage1/regfile/n_1614 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77116/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 32.500 | 13.400 | 541.400 | + | cpu/stage1/regfile/n_1993 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76985__4319/Y | | A1->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 23.500 | 15.500 | 556.900 | + | cpu/stage1/regfile/n_2124 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76911__7098/Y | | A->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 26.200 | 12.400 | 569.300 | + | cpu/stage1/rs1_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g575__7410/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 25.100 | 20.800 | 590.100 | + | cpu/stage1_rs1[7] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1267__8246/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 16.800 | 606.900 | + | cpu/stage1/pcadder/n_38 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_L | 3 | 16.500 | 12.700 | 619.600 | + | 33_g1502__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_33 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 19.900 | 16.200 | 635.800 | + | 33_g1361__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_148 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 12.200 | 7.300 | 643.100 | + | 33_g1328__2802/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_176 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.700 | 13.400 | 656.500 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | R | BUFx2_ASAP7_75t_SL | 4 | 23.700 | 18.000 | 674.500 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | R | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_PSC4087_FE_OCPN1494_add_18_3 | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 15.300 | 16.300 | 690.800 | + | 5_Y_add_17_34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_PSN4087_FE_OCPN1494_add_18_3 | | | R | (net) | 1 | | | | + | 5_Y_add_17_34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 16.400 | 14.800 | 705.600 | + | 33_g1300__7482/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[8] | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g952__7410/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 14.000 | 719.600 | + | cpu/stage1/stage1_pc_mux_to_pc[8] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g374__5107/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.100 | 14.400 | 734.000 | + | cpu/stage1/pcreg/n_6 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2856_n_6/Y | | A->Y | F | HB4xp67_ASAP7_75t_SL | 1 | 82.800 | 55.000 | 789.000 | + | cpu/stage1/pcreg/FE_PHN2856_n_6 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[8]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 19.500 | 0.000 | 789.000 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 36.200 | 912.200 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[8]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.000 | 9.100 | 912.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 42: MET (27.008 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[22]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 149.000 (P) 160.200 (P) + Arrival:= 910.000 21.200 + + Setup:- 4.792 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 805.208 + Launch Clock:= 21.200 + Data Path:+ 757.000 + Slack:= 27.008 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 9.000 | 409.400 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/g409__1617/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 3 | 13.000 | 17.200 | 426.600 | + | cpu/stage1/FE_OFN1186_stage1_inst_19 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC1169_stage1_inst_19/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 16.400 | 7.700 | 434.300 | + | cpu/stage1/regfile/n_192 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1171_stage1_inst_19/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 2 | 11.600 | 5.500 | 439.800 | + | cpu/stage1/regfile/FE_OFN1188_stage1_inst_19 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g80405/Y | | A->Y | R | AND2x6_ASAP7_75t_SL | 7 | 7.200 | 18.900 | 458.700 | + | cpu/stage1/regfile/n_231 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g79846/Y | | B->Y | R | AND2x6_ASAP7_75t_SL | 9 | 22.600 | 24.700 | 483.400 | + | cpu/stage1/regfile/n_300 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/FE_OFC1204_n_300/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 6 | 28.500 | 13.900 | 497.300 | + | cpu/stage1/regfile/n_299 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g77334/Y | | B->Y | R | AOI21xp5_ASAP7_75t_SL | 1 | 26.300 | 18.800 | 516.100 | + | cpu/stage1/regfile/n_1795 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77024/Y | | B->Y | F | NOR3x1_ASAP7_75t_SL | 1 | 32.100 | 16.200 | 532.300 | + | cpu/stage1/regfile/n_2085 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76910__8246/Y | | C->Y | R | NAND4xp75_ASAP7_75t_SL | 1 | 24.200 | 16.400 | 548.700 | + | cpu/stage1/rs1_mux_data[1] | | | R | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g556__6783/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 2 | 26.900 | 22.400 | 571.100 | + | cpu/stage1_rs1[1] | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/g1276__9945/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 2 | 20.900 | 18.300 | 589.400 | + | cpu/stage1/pcadder/n_32 | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1_ASAP7_75t_SL | 2 | 17.900 | 10.000 | 599.400 | + | 33_g1433__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_98 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | R | OAI21x1_ASAP7_75t_SL | 2 | 17.200 | 12.600 | 612.000 | + | 33_g1356__4319/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_153 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | F | NAND2x1p5_ASAP7_75t_SL | 1 | 21.700 | 5.400 | 617.400 | + | 33_g1335__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_169 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 3 | 11.000 | 10.000 | 627.400 | + | 33_g1332__8246/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_172 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AND2x2_ASAP7_75t_SL | 2 | 17.100 | 16.100 | 643.500 | + | 33_g1324__5526/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_180 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 11.900 | 10.400 | 653.900 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | F | BUFx2_ASAP7_75t_SL | 4 | 17.400 | 17.800 | 671.700 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | F | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_RC_19_0/Y | | A2->Y | R | OAI21x1_ASAP7_75t_SL | 2 | 12.700 | 19.000 | 690.700 | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_18 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | AOI21xp5_ASAP7_75t_SL | 2 | 36.900 | 17.600 | 708.300 | + | 33_g1280__3680/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_213 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_SL | 2 | 30.500 | 12.800 | 721.100 | + | 33_g1270__5477/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_220 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | F | AOI21x1_ASAP7_75t_SL | 2 | 22.800 | 12.500 | 733.600 | + | 33_g1255__5115/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_233 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 20.500 | 19.000 | 752.600 | + | 33_g1245__3680/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[22] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g936__2802/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 22.000 | 16.800 | 769.400 | + | cpu/stage1/stage1_pc_mux_to_pc[22] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g378__5526/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 15.500 | 8.800 | 778.200 | + | cpu/stage1/pcreg/n_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[22]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 46.400 | 0.100 | 778.200 | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 34.000 | 910.000 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[22]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 51.200 | 6.900 | 910.000 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 43: MET (27.746 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[11]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[11]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 149.100 (P) 160.200 (P) + Arrival:= 910.100 21.200 + + Setup:- 3.154 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 806.946 + Launch Clock:= 21.200 + Data Path:+ 758.000 + Slack:= 27.746 + Timing Path: + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 18.400 | 398.500 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/g392__9315/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 4 | 17.400 | 18.100 | 416.600 | + | cpu/stage1/FE_OFN1064_stage1_inst_15 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y | | A->Y | R | INVx4_ASAP7_75t_SL | 1 | 31.400 | 9.200 | 425.800 | + | cpu/stage1/regfile/FE_OFN1120_n | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 14.500 | 7.500 | 433.300 | + | cpu/stage1/regfile/FE_OFN1214_n | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/g80989/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 5 | 11.100 | 20.300 | 453.600 | + | cpu/stage1/regfile/n_171 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/FE_OFC1093_n_171/Y | | A->Y | F | BUFx6f_ASAP7_75t_SL | 8 | 20.000 | 18.900 | 472.500 | + | cpu/stage1/regfile/FE_OFN1071_n_171 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/g79839/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 3 | 18.300 | 18.900 | 491.400 | + | cpu/stage1/regfile/n_311 | | | F | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC797_n_311/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 3 | 11.900 | 9.500 | 500.900 | + | cpu/stage1/regfile/n_310 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/g78360/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 17.000 | 11.000 | 511.900 | + | cpu/stage1/regfile/n_770 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77522/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 16.100 | 528.000 | + | cpu/stage1/regfile/n_1614 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77116/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 32.500 | 13.400 | 541.400 | + | cpu/stage1/regfile/n_1993 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76985__4319/Y | | A1->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 23.500 | 15.500 | 556.900 | + | cpu/stage1/regfile/n_2124 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76911__7098/Y | | A->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 26.200 | 12.400 | 569.300 | + | cpu/stage1/rs1_mux_data[7] | | | F | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g575__7410/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 25.100 | 20.800 | 590.100 | + | cpu/stage1_rs1[7] | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/g1267__8246/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 17.100 | 16.800 | 606.900 | + | cpu/stage1/pcadder/n_38 | | | F | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | NOR2x1_ASAP7_75t_L | 3 | 16.500 | 12.700 | 619.600 | + | 33_g1502__1881/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_33 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 19.900 | 16.200 | 635.800 | + | 33_g1361__6783/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_148 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 12.200 | 7.300 | 643.100 | + | 33_g1328__2802/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_176 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 11.700 | 13.400 | 656.500 | + | 33_g1312__1666/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPC1533_add_18_35_Y_add_17_ | | A->Y | R | BUFx2_ASAP7_75t_SL | 4 | 23.700 | 17.600 | 674.100 | + | 34_Y_add_16_33_n_192/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_OCPN1494_add_18_35_Y_add_17_ | | | R | (net) | 4 | | | | + | 34_Y_add_16_33_n_192 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 2 | 15.300 | 16.000 | 690.100 | + | 33_g1302__4733/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_199 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 2 | 28.000 | 18.200 | 708.300 | + | 33_g1291__8246/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 2 | | | | + | 33_n_206 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 32.900 | 12.500 | 720.800 | + | 33_g1271__2398/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_219 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 21.700 | 17.300 | 738.100 | + | 33_g1260__9315/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[11] | | | F | (net) | 1 | | | | + | cpu/stage1/pcselmux/g941__6131/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 15.800 | 15.200 | 753.300 | + | cpu/stage1/stage1_pc_mux_to_pc[11] | | | F | (net) | 2 | | | | + | cpu/stage1/pcreg/g377__8428/Y | | B->Y | R | NOR2xp33_ASAP7_75t_L | 1 | 14.700 | 9.500 | 762.800 | + | cpu/stage1/pcreg/n_3 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2868_n_3/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 44.100 | 16.400 | 779.200 | + | cpu/stage1/pcreg/FE_PHN2868_n_3 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[11]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 12.100 | 0.000 | 779.200 | + +--------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 44.600 | 845.600 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 38.400 | 11.700 | 857.300 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 10.600 | 18.700 | 876.000 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 6.000 | 34.100 | 910.100 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[11]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 52.700 | 7.000 | 910.100 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 44: MET (28.315 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[23]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 125.100 (P) 160.200 (P) + Arrival:= 886.100 21.200 + + Setup:- 1.185 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 784.915 + Launch Clock:= 21.200 + Data Path:+ 735.400 + Slack:= 28.315 + Timing Path: + +-------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g629/Y | | B1->Y | F | AO22x2_ASAP7_75t_SL | 1 | 14.200 | 19.900 | 239.900 | + | cpu/stage2/stage2_rs2_data[30] | | | F | (net) | 1 | | | | + | cpu/stage2/FE_OFC502_stage2_rs2_data_30/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 5 | 13.200 | 12.600 | 252.500 | + | cpu/stage2/FE_OFN741_stage2_rs2_data_30 | | | R | (net) | 5 | | | | + | cpu/stage2/FE_OFC504_stage2_rs2_data_30/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 3 | 21.000 | 11.500 | 264.000 | + | cpu/stage2/FE_OFN743_stage2_rs2_data_30 | | | F | (net) | 3 | | | | + | cpu/stage2/branchcomp/g962/Y | | A->Y | F | XOR2xp5_ASAP7_75t_SL | 1 | 18.700 | 14.700 | 278.700 | + | cpu/stage2/branchcomp/n_7 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g903/Y | | B->Y | R | NOR2x1_ASAP7_75t_SL | 1 | 20.300 | 10.300 | 289.000 | + | cpu/stage2/branchcomp/n_36 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g893/Y | | C->Y | F | NAND4xp75_ASAP7_75t_SL | 1 | 17.700 | 13.000 | 302.000 | + | cpu/stage2/branchcomp/n_46 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/g892/Y | | B->Y | R | NOR2x1p5_ASAP7_75t_SL | 1 | 23.900 | 13.200 | 315.200 | + | cpu/stage2/branchcomp/n_47 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g891/Y | | B->Y | R | AND4x2_ASAP7_75t_SL | 2 | 22.000 | 20.500 | 335.700 | + | cpu/BrEq | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g881__4733/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.300 | 351.000 | + | cpu/stage1/pcsel/n_21 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g879__5115/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 11.100 | 8.300 | 359.300 | + | cpu/stage1/pcsel/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcsel/g873__5122/Y | | B->Y | R | NAND2x1p5_ASAP7_75t_SL | 1 | 17.200 | 9.700 | 369.000 | + | cpu/stage1/pcsel/n_30 | | | R | (net) | 1 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | A->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 16.100 | 9.300 | 378.300 | + | cpu/stage1/PCSelect[0] | | | F | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | F | OR2x6_ASAP7_75t_SL | 4 | 12.800 | 22.100 | 400.400 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 17.300 | 8.900 | 409.300 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | R | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | R | BUFx6f_ASAP7_75t_SL | 5 | 13.000 | 11.600 | 420.900 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | R | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 6 | 7.800 | 24.500 | 445.400 | + | cpu/stage1_inst[20] | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 4 | 31.800 | 30.600 | 476.000 | + | cpu/stage1/regfile/n_237 | | | F | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 13 | 56.400 | 35.900 | 511.900 | + | cpu/stage1/regfile/n_236 | | | R | (net) | 13 | | | | + | cpu/stage1/regfile/FE_OFC643_n_237/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 59.300 | 5.400 | 517.300 | + | cpu/stage1/regfile/FE_OFN834_n_237 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g79821/Y | | B->Y | R | NOR2xp33_ASAP7_75t_L | 6 | 18.100 | 93.000 | 610.300 | + | cpu/stage1/regfile/n_332 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g77539/Y | | B1->Y | F | AOI222xp33_ASAP7_75t_SL | 1 | 196.500 | 33.700 | 644.000 | + | cpu/stage1/regfile/n_1597 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77131/Y | | A1->Y | R | AOI21xp5_ASAP7_75t_SL | 1 | 80.700 | 16.500 | 660.500 | + | cpu/stage1/regfile/n_1978 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77084/Y | | C->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 37.400 | 12.200 | 672.700 | + | cpu/stage1/regfile/n_2025 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76998__5115/Y | | A->Y | F | AND5x1_ASAP7_75t_SL | 1 | 66.500 | 19.100 | 691.800 | + | cpu/stage1/regfile/n_2111 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76936__1705/Y | | C->Y | R | A2O1A1Ixp33_ASAP7_75t_SL | 1 | 12.400 | 14.900 | 706.700 | + | cpu/stage1/rs2_mux_data[23] | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3936_rs2_mux_data_23/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 48.600 | 25.200 | 731.900 | + | cpu/stage1/FE_PHN3936_rs2_mux_data_23 | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g559__1617/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 28.700 | 18.100 | 750.000 | + | cpu/stage1_rs2[23] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g444__4733/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 13.700 | 6.600 | 756.600 | + | cpu/s1_to_s2_rs2/n_7 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[23]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 61.200 | 0.000 | 756.600 | + +-------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.400 | 886.100 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[23]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 5.500 | 886.100 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 45: MET (28.343 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 126.400 (P) 160.200 (P) + Arrival:= 887.400 21.200 + + Setup:- -3.643 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.043 + Launch Clock:= 21.200 + Data Path:+ 741.500 + Slack:= 28.343 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1545/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 2 | 23.000 | 15.000 | 580.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_210 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1540/Y | | A1->Y | F | AOI21xp5_ASAP7_75t_SL | 2 | 9.100 | 12.100 | 592.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_215 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1533/Y | | A2->Y | R | OAI21xp5_ASAP7_75t_SL | 1 | 22.800 | 14.500 | 607.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_222 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1528/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 31.300 | 17.000 | 624.200 | + | cpu/stage2/alu/n_310 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5523/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 19.300 | 31.100 | 655.300 | + | dcache_addr[19] | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g440__6161/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 51.300 | 8.200 | 663.500 | + | cpu/s2_to_s3_alu/n_11 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC3575_n_11/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 60.000 | 32.100 | 695.600 | + | cpu/s2_to_s3_alu/FE_PHN3575_n_11 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2757_n_11/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 15.400 | 67.100 | 762.700 | + | cpu/s2_to_s3_alu/FE_PHN2757_n_11 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[19]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 22.600 | 0.100 | 762.700 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 40.600 | 887.400 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 62.800 | 9.700 | 887.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 46: MET (29.089 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 124.900 (P) 160.200 (P) + Arrival:= 885.900 21.200 + + Setup:- 6.111 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.789 + Launch Clock:= 21.200 + Data Path:+ 729.500 + Slack:= 29.089 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+----------------------------+--------+---------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 49.500 | 70.700 | + | cpu/stage3_inst[5] | | | R | (net) | 2 | | | | + | cpu/FE_OFC454_stage3_inst_5/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 9.100 | 7.300 | 78.000 | + | cpu/FE_OFN707_stage3_inst_5 | | | F | (net) | 1 | | | | + | cpu/FE_OFC456_stage3_inst_5/Y | | A->Y | R | INVx3_ASAP7_75t_SL | 9 | 11.200 | 10.400 | 88.400 | + | cpu/FE_OFN708_stage3_inst_5 | | | R | (net) | 9 | | | | + | cpu/stage3/wbsel/g108/Y | | A1->Y | R | OA21x2_ASAP7_75t_SL | 1 | 16.800 | 15.000 | 103.400 | + | cpu/stage3/wbsel/n_9 | | | R | (net) | 1 | | | | + | cpu/stage3/wbsel/g107/Y | | A->Y | R | OR2x2_ASAP7_75t_SL | 1 | 7.500 | 12.800 | 116.200 | + | cpu/stage3/WBSelect[1] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_OFC969_WBSelect_1/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 8.100 | 5.700 | 121.900 | + | cpu/stage3/wbselmux/n_1 | | | F | (net) | 2 | | | | + | cpu/stage3/wbselmux/g1156/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 10 | 8.200 | 20.200 | 142.100 | + | cpu/stage3/wbselmux/n_5 | | | F | (net) | 10 | | | | + | cpu/stage3/wbselmux/FE_OCPC1415_n_5/Y | | A->Y | F | BUFx12f_ASAP7_75t_SL | 17 | 19.300 | 20.400 | 162.500 | + | cpu/stage3/wbselmux/FE_OCPN1389_n_5 | | | F | (net) | 17 | | | | + | cpu/stage3/wbselmux/g1152/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 1 | 24.000 | 17.100 | 179.600 | + | cpu/stage3/wbselmux/n_9 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1119/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 1 | 8.300 | 19.300 | 198.900 | + | cpu/stage3/wbselmux/n_42 | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1118/Y | | B->Y | F | AO21x2_ASAP7_75t_SL | 3 | 13.000 | 21.100 | 220.000 | + | cpu/wb_data[30] | | | F | (net) | 3 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 6 | 14.200 | 25.400 | 245.400 | + | cpu/stage2/stage2_rs1_data[30] | | | F | (net) | 6 | | | | + | cpu/stage2/branchcomp/lt_12_36_g792/Y | | A->Y | F | AND2x4_ASAP7_75t_SL | 1 | 21.900 | 16.100 | 261.500 | + | cpu/stage2/branchcomp/lt_12_36_n_71 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g757/Y | | A2->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 6.700 | 10.200 | 271.700 | + | cpu/stage2/branchcomp/lt_12_36_n_109 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g731/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 17.300 | 8.700 | 280.400 | + | cpu/stage2/branchcomp/lt_12_36_n_133 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/FE_RC_21_0/Y | | B->Y | R | AOI21x1_ASAP7_75t_SL | 1 | 15.100 | 13.300 | 293.700 | + | cpu/stage2/branchcomp/lt_12_36_n_137 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g724/Y | | B->Y | F | OAI21x1_ASAP7_75t_SL | 1 | 22.700 | 12.900 | 306.600 | + | cpu/stage2/branchcomp/lt_12_36_n_139 | | | F | (net) | 1 | | | | + | cpu/stage2/branchcomp/lt_12_36_g723/Y | | D->Y | R | A2O1A1O1Ixp25_ASAP7_75t_SL | 1 | 20.100 | 19.600 | 326.200 | + | cpu/stage2/branchcomp/n_146 | | | R | (net) | 1 | | | | + | cpu/stage2/branchcomp/g922/Y | | A1->Y | R | AO22x2_ASAP7_75t_SL | 2 | 35.900 | 23.300 | 349.500 | + | cpu/BrLT | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g895__4319/Y | | B->Y | R | AND2x4_ASAP7_75t_SL | 2 | 19.800 | 14.600 | 364.100 | + | cpu/stage1/pcsel/n_9 | | | R | (net) | 2 | | | | + | cpu/stage1/pcsel/g878__1881/Y | | B->Y | F | NOR2x2_ASAP7_75t_SL | 2 | 10.000 | 7.700 | 371.800 | + | cpu/stage1/pcsel/n_25 | | | F | (net) | 2 | | | | + | cpu/stage1/pcsel/g871__2802/Y | | B->Y | R | NOR2x2_ASAP7_75t_SL | 2 | 13.600 | 8.300 | 380.100 | + | cpu/stage1/PCSelect[0] | | | R | (net) | 2 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | A->Y | R | OR2x6_ASAP7_75t_SL | 4 | 13.400 | 17.800 | 397.900 | + | cpu/stage1/NOPSignal | | | R | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1418_NOPSignal/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 5 | 17.300 | 7.200 | 405.100 | + | cpu/stage1/nopselmux/FE_DBTN75_NOPSignal | | | F | (net) | 5 | | | | + | cpu/stage1/nopselmux/FE_OCPC1489_FE_DBTN75_NOPSign | | A->Y | F | BUFx6f_ASAP7_75t_SL | 5 | 11.300 | 11.400 | 416.500 | + | al/Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OCPN1450_FE_DBTN75_NOPSign | | | F | (net) | 5 | | | | + | al | | | | | | | | | + | cpu/stage1/nopselmux/g406__5526/Y | | B->Y | F | AND2x2_ASAP7_75t_SL | 6 | 5.800 | 22.300 | 438.800 | + | cpu/stage1_inst[20] | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/g80402/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 4 | 24.600 | 33.800 | 472.600 | + | cpu/stage1/regfile/n_237 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/FE_OFC642_n_237/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 13 | 62.900 | 28.700 | 501.300 | + | cpu/stage1/regfile/n_236 | | | F | (net) | 13 | | | | + | cpu/stage1/regfile/g79863/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 28 | 49.900 | 84.300 | 585.600 | + | cpu/stage1/regfile/n_272 | | | F | (net) | 28 | | | | + | cpu/stage1/regfile/g78269/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 132.400 | 29.500 | 615.100 | + | cpu/stage1/regfile/n_874 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77490/Y | | C->Y | R | AOI221xp5_ASAP7_75t_SL | 1 | 15.800 | 15.400 | 630.500 | + | cpu/stage1/regfile/n_1646 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77181/Y | | A->Y | R | AND5x1_ASAP7_75t_SL | 1 | 59.300 | 25.400 | 655.900 | + | cpu/stage1/regfile/n_1937 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77009/Y | | A2->Y | R | OA211x2_ASAP7_75t_SL | 1 | 14.300 | 16.300 | 672.200 | + | cpu/stage1/regfile/n_2100 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76931__5526/Y | | A->Y | F | NAND5xp2_ASAP7_75t_SL | 1 | 11.300 | 24.900 | 697.100 | + | cpu/stage1/rs2_mux_data[27] | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g558__3680/Y | | A2->Y | F | AO22x1_ASAP7_75t_SL | 1 | 63.300 | 22.400 | 719.500 | + | cpu/stage1/data2sel_s1/FE_PHN3592_stage1_rs2_27 | | | F | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3592_stage1_rs2_27/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 12.100 | 12.700 | 732.200 | + | cpu/stage1_rs2[27] | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3938_stage1_rs2_27/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 6.300 | 11.400 | 743.600 | + | cpu/s1_to_s2_rs2/FE_PHN3938_stage1_rs2_27 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g425__5477/Y | | B->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 6.200 | 7.100 | 750.700 | + | cpu/s1_to_s2_rs2/n_26 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[27]/D | | D | R | DFFHQNx1_ASAP7_75t_SL | 1 | 59.100 | 0.100 | 750.700 | + +---------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 31.300 | 803.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 25.900 | 45.200 | 848.700 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 53.000 | 37.200 | 885.900 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[27]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 53.700 | 5.300 | 885.900 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 47: MET (29.840 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[24]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[24]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 126.300 (P) 160.200 (P) + Arrival:= 887.300 21.200 + + Setup:- -3.740 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.040 + Launch Clock:= 21.200 + Data Path:+ 740.000 + Slack:= 29.840 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | F | NAND2x1_ASAP7_75t_SL | 2 | 15.400 | 7.600 | 589.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 14.400 | 10.800 | 600.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | F | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 34.900 | 10.200 | 610.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 19.800 | 13.700 | 624.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1522/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 22.200 | 16.200 | 640.600 | + | cpu/stage2/alu/n_315 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5503/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 17.700 | 29.300 | 669.900 | + | dcache_addr[24] | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g445__1666/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 47.700 | 11.900 | 681.800 | + | cpu/s2_to_s3_alu/n_6 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2770_n_6/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 64.300 | 79.400 | 761.200 | + | cpu/s2_to_s3_alu/FE_PHN2770_n_6 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[24]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 22.000 | 0.000 | 761.200 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 40.500 | 887.300 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[24]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 62.800 | 9.600 | 887.300 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 48: MET (30.163 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[23]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 126.400 (P) 160.200 (P) + Arrival:= 887.400 21.200 + + Setup:- -3.463 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.863 + Launch Clock:= 21.200 + Data Path:+ 739.500 + Slack:= 30.163 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.200 | 21.200 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[5]/Q | | CLK->Q | F | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 48.400 | 69.600 | + | cpu/stage3_inst[5] | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y | | A->Y | R | INVx2_ASAP7_75t_SL | 1 | 7.800 | 3.900 | 73.500 | + | cpu/stage3/ldsel/n_4 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g215/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 1 | 4.700 | 17.700 | 91.200 | + | cpu/stage3/ldsel/n_11 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g213/Y | | B->Y | F | NAND2x2_ASAP7_75t_SL | 2 | 13.300 | 6.400 | 97.600 | + | cpu/stage3/ldsel/n_14 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g205/Y | | A->Y | F | OR2x2_ASAP7_75t_SL | 4 | 10.700 | 19.000 | 116.600 | + | cpu/stage3/LdSelect[0] | | | F | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC954_LdSelect_0/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 14.200 | 14.700 | 131.300 | + | cpu/stage3/ldselmux/FE_OFN758_LdSelect_0 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/g2417/Y | | A->Y | R | AND3x2_ASAP7_75t_SL | 3 | 25.700 | 23.100 | 154.400 | + | cpu/stage3/ldselmux/n_38 | | | R | (net) | 3 | | | | + | cpu/stage3/ldselmux/FE_OFC442_n_38/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 7.800 | 162.200 | + | cpu/stage3/ldselmux/FE_OFN698_n_38 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2374/Y | | A->Y | R | NAND2x1p5_ASAP7_75t_SL | 8 | 11.800 | 17.200 | 179.400 | + | cpu/stage3/ldselmux/n_78 | | | R | (net) | 8 | | | | + | cpu/stage3/ldselmux/g2354/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 30.500 | 12.900 | 192.300 | + | cpu/stage3/ldselmux/n_92 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 1 | 24.400 | 16.100 | 208.400 | + | cpu/stage3/wb_dmem[0] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | R | AO21x1_ASAP7_75t_SL | 3 | 43.300 | 17.900 | 226.300 | + | cpu/wb_data[0] | | | R | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | R | AO21x2_ASAP7_75t_SL | 4 | 19.500 | 20.000 | 246.300 | + | cpu/stage2/stage2_rs2_data[0] | | | R | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 21.500 | 6.800 | 253.100 | + | cpu/stage2/bselmux/n_6 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 2 | 25.500 | 26.300 | 279.400 | + | cpu/stage2/stage2_alu_in2[0] | | | F | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 24 | 22.700 | 18.500 | 297.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | R | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 33.400 | 31.400 | 329.300 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | R | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 2 | 45.500 | 18.200 | 347.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | F | MAJIxp5_ASAP7_75t_SL | 2 | 42.900 | 18.100 | 365.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 34.800 | 21.700 | 387.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 17.400 | 404.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 3 | 11.900 | 18.100 | 422.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | R | OAI311xp33_ASAP7_75t_SL | 1 | 13.100 | 16.200 | 439.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 37.200 | 11.400 | 450.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 19.700 | 18.500 | 468.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | F | OA21x2_ASAP7_75t_SL | 2 | 10.400 | 16.200 | 485.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 1 | 10.900 | 9.500 | 494.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 18.500 | 19.200 | 513.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | F | AOI31xp67_ASAP7_75t_SL | 3 | 18.300 | 16.200 | 530.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | R | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 33.200 | 12.200 | 542.200 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 3 | 32.000 | 23.400 | 565.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 23.000 | 16.500 | 582.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1542/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 2 | 15.400 | 7.900 | 590.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_213 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1536/Y | | A1->Y | R | OAI31xp33_ASAP7_75t_SL | 2 | 11.900 | 22.500 | 612.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_219 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1530/Y | | A1->Y | F | AOI21xp5_ASAP7_75t_SL | 1 | 59.100 | 14.300 | 626.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_225 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1527/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 30.000 | 11.400 | 638.200 | + | cpu/stage2/alu/n_314 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5526/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 19.600 | 29.300 | 667.500 | + | dcache_addr[23] | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g444__2346/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 48.300 | 11.800 | 679.300 | + | cpu/s2_to_s3_alu/n_7 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2762_n_7/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 64.600 | 81.400 | 760.700 | + | cpu/s2_to_s3_alu/FE_PHN2762_n_7 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[23]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 24.000 | 0.100 | 760.700 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 40.600 | 887.400 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[23]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 62.800 | 9.700 | 887.400 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 49: MET (30.203 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage3/csr/csr_reg[14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 140.200 (P) 160.800 (P) + Arrival:= 901.200 21.800 + + Setup:- -1.203 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 802.403 + Launch Clock:= 21.800 + Data Path:+ 750.400 + Slack:= 30.203 + Timing Path: + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.800 | 21.800 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[3]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 50.100 | 71.900 | + | cpu/stage3_inst[3] | | | R | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OCPC1470_stage3_inst_3/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 2 | 10.500 | 4.600 | 76.500 | + | cpu/stage3/ldsel/FE_OCPN1434_stage3_inst_3 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_RC_26_0/Y | | B->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 6.000 | 5.300 | 81.800 | + | cpu/stage3/ldsel/FE_RN_10_0 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/FE_RC_27_0/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 16.200 | 6.500 | 88.300 | + | cpu/stage3/ldsel/n_10 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g208/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 1 | 9.800 | 7.100 | 95.400 | + | cpu/stage3/ldsel/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g205/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 4 | 16.800 | 17.600 | 113.000 | + | cpu/stage3/LdSelect[0] | | | R | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y | | A->Y | F | INVx3_ASAP7_75t_SL | 1 | 16.000 | 6.300 | 119.300 | + | cpu/stage3/ldselmux/n_14 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 9.300 | 7.400 | 126.700 | + | cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 | | | R | (net) | 5 | | | | + | cpu/stage3/ldselmux/g2426/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 10.600 | 12.600 | 139.300 | + | cpu/stage3/ldselmux/n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/FE_OCPC1515_n_30/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 2 | 8.400 | 11.600 | 150.900 | + | cpu/stage3/ldselmux/FE_OCPN1476_n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/g2399/Y | | A2->Y | F | AOI21x1_ASAP7_75t_SL | 7 | 7.800 | 15.700 | 166.600 | + | cpu/stage3/ldselmux/n_62 | | | F | (net) | 7 | | | | + | cpu/stage3/ldselmux/g2354/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 31.000 | 15.700 | 182.300 | + | cpu/stage3/ldselmux/n_92 | | | R | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | F | OAI221xp5_ASAP7_75t_SL | 1 | 25.100 | 15.700 | 198.000 | + | cpu/stage3/wb_dmem[0] | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | F | AO21x1_ASAP7_75t_SL | 3 | 28.200 | 22.300 | 220.300 | + | cpu/wb_data[0] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 4 | 15.500 | 23.200 | 243.500 | + | cpu/stage2/stage2_rs2_data[0] | | | F | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 18.500 | 10.300 | 253.800 | + | cpu/stage2/bselmux/n_6 | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 2 | 25.000 | 23.800 | 277.600 | + | cpu/stage2/stage2_alu_in2[0] | | | R | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 24 | 28.000 | 17.600 | 295.200 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | F | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC696_n_30/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 14 | 29.900 | 38.500 | 333.700 | + | cpu/stage2/alu/FE_OFN871_n_30 | | | R | (net) | 14 | | | | + | cpu/stage2/alu/FE_OFC700_n_30/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 71.900 | 6.300 | 340.000 | + | cpu/stage2/alu/FE_OFN875_n_30 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC702_n_30/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 16 | 22.000 | 44.500 | 384.500 | + | cpu/stage2/alu/FE_OFN877_n_30 | | | R | (net) | 16 | | | | + | cpu/stage2/alu/FE_OFC704_n_30/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 16 | 86.900 | 36.600 | 421.100 | + | cpu/stage2/alu/FE_OFN879_n_30 | | | R | (net) | 16 | | | | + | cpu/stage2/alu/srl_33_21_g1794/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 46.600 | 9.400 | 430.500 | + | cpu/stage2/alu/srl_33_21_n_34 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/srl_33_21_g1788/Y | | B->Y | R | NOR2xp33_ASAP7_75t_SL | 3 | 41.800 | 30.600 | 461.100 | + | cpu/stage2/alu/srl_33_21_n_55 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/srl_33_21_g1769/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 73.700 | 11.900 | 473.000 | + | cpu/stage2/alu/srl_33_21_n_67 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/srl_33_21_g1765/Y | | C->Y | R | OAI221xp5_ASAP7_75t_SL | 2 | 43.800 | 23.500 | 496.500 | + | cpu/stage2/alu/srl_33_21_n_79 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/srl_33_21_g1731/Y | | A2->Y | F | AOI22xp5_ASAP7_75t_SL | 2 | 67.100 | 21.200 | 517.700 | + | cpu/stage2/alu/srl_33_21_n_112 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/srl_33_21_g1706/Y | | A2->Y | R | OAI22xp5_ASAP7_75t_SL | 1 | 40.400 | 19.100 | 536.800 | + | cpu/stage2/alu/n_210 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5562/Y | | A1->Y | F | AOI222xp33_ASAP7_75t_SL | 1 | 37.000 | 14.600 | 551.400 | + | cpu/stage2/alu/n_159 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5515/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 1 | 84.200 | 22.900 | 574.300 | + | cpu/stage2/alu/FE_PHN4114_dcache_addr_14 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/FE_PHC4114_dcache_addr_14/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 2 | 40.900 | 50.200 | 624.500 | + | dcache_addr[14] | | | R | (net) | 2 | | | | + | cpu/FE_PHC2732_dcache_addr_14/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 3 | 55.700 | 48.900 | 673.400 | + | cpu/FE_PHN2732_dcache_addr_14 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/g179/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 78.500 | 11.400 | 684.800 | + | cpu/stage3/csr/FE_PHN2800_n_16 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/FE_PHC2800_n_16/Y | | A->Y | F | HB4xp67_ASAP7_75t_R | 1 | 56.900 | 87.400 | 772.200 | + | cpu/stage3/csr/n_16 | | | F | (net) | 1 | | | | + | cpu/stage3/csr/csr_reg[14]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 33.800 | 0.600 | 772.200 | + +-----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 25.300 | 797.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 16.200 | 28.200 | 825.700 | + | CTS_1 | | | R | (net) | 6 | | | | + | CTS_ccl_a_buf_00106/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 3 | 27.300 | 43.700 | 869.400 | + | CTS_2 | | | R | (net) | 3 | | | | + | cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 39.800 | 31.800 | 901.200 | + | NST/GCLK | | | | | | | | | + | cpu/stage3/csr/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/stage3/csr/csr_reg[14]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 43.300 | 2.500 | 901.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 50: MET (30.862 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ -139.000 -139.000 + Net Latency:+ 126.200 (P) 160.800 (P) + Arrival:= 887.200 21.800 + + Setup:- -4.162 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.362 + Launch Clock:= 21.800 + Data Path:+ 738.700 + Slack:= 30.862 + Timing Path: + +------------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+--------------------------+--------+--------+--------+----------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 12.300 | -126.700 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 28.900 | 33.200 | -93.500 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 28.900 | 57.100 | -36.400 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 66.000 | 10.400 | -26.000 | + | _INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_inst/CTS_2 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_inst/CTS_cpc_drv_buf_00165/Y | | A->Y | R | BUFx2_ASAP7_75t_SRAM | 15 | 8.000 | 47.800 | 21.800 | + | cpu/s2_to_s3_inst/CTS_1 | | | R | (net) | 15 | | | | + | cpu/s2_to_s3_inst/register_reg[3]/Q | | CLK->Q | R | DFFHQx4_ASAP7_75t_SL | 2 | 64.400 | 50.100 | 71.900 | + | cpu/stage3_inst[3] | | | R | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_OCPC1470_stage3_inst_3/Y | | A->Y | F | INVx4_ASAP7_75t_SL | 2 | 10.500 | 4.600 | 76.500 | + | cpu/stage3/ldsel/FE_OCPN1434_stage3_inst_3 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/FE_RC_26_0/Y | | B->Y | R | OAI21x1_ASAP7_75t_SL | 1 | 6.000 | 5.300 | 81.800 | + | cpu/stage3/ldsel/FE_RN_10_0 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/FE_RC_27_0/Y | | A->Y | F | INVx2_ASAP7_75t_SL | 2 | 16.200 | 6.500 | 88.300 | + | cpu/stage3/ldsel/n_10 | | | F | (net) | 2 | | | | + | cpu/stage3/ldsel/g208/Y | | A->Y | R | NAND3x1_ASAP7_75t_SL | 1 | 9.800 | 7.100 | 95.400 | + | cpu/stage3/ldsel/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/ldsel/g205/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 4 | 16.800 | 17.600 | 113.000 | + | cpu/stage3/LdSelect[0] | | | R | (net) | 4 | | | | + | cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y | | A->Y | F | INVx3_ASAP7_75t_SL | 1 | 16.000 | 6.300 | 119.300 | + | cpu/stage3/ldselmux/n_14 | | | F | (net) | 1 | | | | + | cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y | | A->Y | R | INVx5_ASAP7_75t_SL | 5 | 9.300 | 7.400 | 126.700 | + | cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 | | | R | (net) | 5 | | | | + | cpu/stage3/ldselmux/g2426/Y | | B->Y | R | OR2x2_ASAP7_75t_SL | 2 | 10.600 | 12.600 | 139.300 | + | cpu/stage3/ldselmux/n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/FE_OCPC1515_n_30/Y | | A->Y | R | BUFx3_ASAP7_75t_SL | 2 | 8.400 | 11.600 | 150.900 | + | cpu/stage3/ldselmux/FE_OCPN1476_n_30 | | | R | (net) | 2 | | | | + | cpu/stage3/ldselmux/g2399/Y | | A2->Y | F | AOI21x1_ASAP7_75t_SL | 7 | 7.800 | 15.700 | 166.600 | + | cpu/stage3/ldselmux/n_62 | | | F | (net) | 7 | | | | + | cpu/stage3/ldselmux/g2354/Y | | B2->Y | R | AOI22xp5_ASAP7_75t_SL | 1 | 31.000 | 15.700 | 182.300 | + | cpu/stage3/ldselmux/n_92 | | | R | (net) | 1 | | | | + | cpu/stage3/ldselmux/g2318/Y | | C->Y | F | OAI221xp5_ASAP7_75t_SL | 1 | 25.100 | 15.700 | 198.000 | + | cpu/stage3/wb_dmem[0] | | | F | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1103/Y | | A1->Y | F | AO21x1_ASAP7_75t_SL | 3 | 28.200 | 22.300 | 220.300 | + | cpu/wb_data[0] | | | F | (net) | 3 | | | | + | cpu/stage2/rs2DataSel/g563/Y | | A1->Y | F | AO21x2_ASAP7_75t_SL | 4 | 15.500 | 23.200 | 243.500 | + | cpu/stage2/stage2_rs2_data[0] | | | F | (net) | 4 | | | | + | cpu/stage2/bselmux/g583/Y | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 18.500 | 10.300 | 253.800 | + | cpu/stage2/bselmux/n_6 | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g559/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 2 | 25.000 | 23.800 | 277.600 | + | cpu/stage2/stage2_alu_in2[0] | | | R | (net) | 2 | | | | + | cpu/stage2/alu/FE_OFC692_n_30/Y | | A->Y | F | INVx5_ASAP7_75t_SL | 24 | 28.000 | 16.300 | 293.900 | + | cpu/stage2/alu/FE_OFN867_n_30 | | | F | (net) | 24 | | | | + | cpu/stage2/alu/FE_OFC693_n_30/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 5 | 29.700 | 29.900 | 323.800 | + | cpu/stage2/alu/FE_OFN868_n_30 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1734/Y | | A->Y | F | XNOR2xp5_ASAP7_75t_SL | 2 | 33.500 | 25.800 | 349.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_24 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1628/Y | | C->Y | R | MAJIxp5_ASAP7_75t_SL | 2 | 33.200 | 23.900 | 373.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_146 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1585/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 44.100 | 19.200 | 392.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_173 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 12.500 | 15.700 | 408.400 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_177 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 3 | 13.100 | 16.700 | 425.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/FE_RC_30_0/Y | | A1->Y | F | OAI311xp33_ASAP7_75t_SL | 1 | 14.900 | 9.900 | 435.000 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 2 | 27.900 | 13.600 | 448.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 20.800 | 16.700 | 465.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y | | A2->Y | R | OA21x2_ASAP7_75t_SL | 2 | 11.900 | 14.500 | 479.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 11.000 | 8.800 | 488.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 16.000 | 20.900 | 509.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y | | A1->Y | R | AOI31xp67_ASAP7_75t_SL | 3 | 15.700 | 15.200 | 524.700 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 30.500 | 10.200 | 534.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 3 | 32.200 | 26.200 | 561.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 20.400 | 17.700 | 578.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y | | B->Y | R | NAND2x1_ASAP7_75t_SL | 2 | 13.200 | 10.700 | 589.500 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y | | A2->Y | F | O2A1O1Ixp5_ASAP7_75t_SL | 1 | 20.400 | 9.300 | 598.800 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y | | A2->Y | R | O2A1O1Ixp33_ASAP7_75t_SL | 1 | 36.500 | 16.100 | 614.900 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 3 | 27.700 | 12.200 | 627.100 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 | | | F | (net) | 3 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y | | A2->Y | F | AO21x1_ASAP7_75t_SL | 2 | 19.200 | 19.500 | 646.600 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y | | A1->Y | R | AOI21x1_ASAP7_75t_SL | 2 | 16.700 | 10.700 | 657.300 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1514/Y | | B->Y | R | XNOR2xp5_ASAP7_75t_SL | 1 | 19.400 | 13.200 | 670.500 | + | cpu/stage2/alu/n_318 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5512/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 4 | 24.700 | 27.800 | 698.300 | + | dcache_addr[27] | | | R | (net) | 4 | | | | + | cpu/s2_to_s3_alu/g425__8428/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 43.500 | 11.200 | 709.500 | + | cpu/s2_to_s3_alu/n_26 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/FE_PHC2780_n_26/Y | | A->Y | F | HB4xp67_ASAP7_75t_SL | 1 | 64.000 | 51.000 | 760.500 | + | cpu/s2_to_s3_alu/FE_PHN2780_n_26 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[27]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 18.700 | 0.100 | 760.500 | + +------------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 11.200 | 772.200 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 26.200 | 28.800 | 801.000 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 24.200 | 45.800 | 846.800 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 38.700 | 40.400 | 887.200 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[27]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 62.800 | 9.500 | 887.200 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + diff --git a/build/par-rundir/timingReports/riscv_top_postRoute_reg2reg_hold.tarpt b/build/par-rundir/timingReports/riscv_top_postRoute_reg2reg_hold.tarpt new file mode 100644 index 0000000..6c0d76f --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_postRoute_reg2reg_hold.tarpt @@ -0,0 +1,3683 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 22:07:14 2020 +# Design: riscv_top +# Command: opt_design -post_route -setup -hold +############################################################### +Path 1: VIOLATED (-0.176 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[20][17]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[17]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[20][17]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 111.400 (P) 76.500 (P) + Arrival:= 27.536 -7.364 + + Hold:+ 11.576 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 139.112 + Launch Clock:= -7.364 + Data Path:+ 146.300 + Slack:= -0.176 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 25.200 | -7.364 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[17]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 41.500 | 23.000 | 15.636 | + | cpu/stage3_alu[17] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1148/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 9.800 | 10.100 | 25.736 | + | cpu/stage3/wbselmux/n_13 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1112/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 8.000 | 8.900 | 34.636 | + | cpu/wb_data[17] | | | R | (net) | 3 | | | | + | cpu/stage1/FE_PHC2718_wb_data_17/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 7.100 | 27.200 | 61.836 | + | cpu/stage1/FE_PHN2718_wb_data_17 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3030_wb_data_17/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 11.700 | 26.600 | 88.436 | + | cpu/stage1/FE_PHN3030_wb_data_17 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OCPC1492_wb_data_17/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 3 | 9.400 | 14.000 | 102.436 | + | cpu/stage1/FE_OCPN1453_wb_data_17 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC899_wb_data_17/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 17.700 | 3.700 | 106.136 | + | cpu/stage1/regfile/FE_OFN1030_wb_data_17 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/FE_OFC900_wb_data_17/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 5 | 7.500 | 10.000 | 116.136 | + | cpu/stage1/regfile/FE_OFN1031_wb_data_17 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/g81398/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 8 | 17.900 | 22.800 | 138.936 | + | cpu/stage1/regfile/n_101 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/mem_reg[20][17]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 8 | 45.700 | 1.000 | 138.936 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 30.300 | -19.164 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.600 | 12.600 | -6.564 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_56 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00036/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 16.900 | 34.100 | 27.536 | + | cpu/stage1/regfile/CTS_57 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[20][17]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 48.500 | 19.800 | 27.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 2: VIOLATED (-0.060 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[13]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[26][13]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[13]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.800 (P) 84.300 (P) + Arrival:= -3.064 0.436 + + Hold:+ 7.560 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.496 + Launch Clock:= 0.436 + Data Path:+ 104.000 + Slack:= -0.060 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 23.800 | -28.464 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 23.200 | 7.300 | -21.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_5 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00018/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.800 | 21.600 | 0.436 | + | cpu/stage1/regfile/CTS_4 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[26][13]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_L | 1 | 15.800 | 22.400 | 22.836 | + | cpu/stage1/regfile/mem[26][13] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC1730_mem_26_13/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 2 | 7.200 | 28.700 | 51.536 | + | cpu/stage1/regfile/FE_PHN1730_mem_26_13 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77975/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 17.400 | 4.900 | 56.436 | + | cpu/stage1/regfile/n_1164 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77163/Y | | E->Y | F | AND5x1_ASAP7_75t_SL | 1 | 8.800 | 10.200 | 66.636 | + | cpu/stage1/regfile/n_1950 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76940__6131/Y | | A2->Y | R | OAI211xp5_ASAP7_75t_SL | 1 | 5.000 | 20.700 | 87.336 | + | cpu/stage1/rs2_mux_data[13] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g563__8246/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 24.400 | 11.800 | 99.136 | + | cpu/stage1_rs2[13] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g419__9945/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 6.400 | 5.300 | 104.436 | + | cpu/s1_to_s2_rs2/n_32 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[13]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.400 | 0.100 | 104.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.500 | -3.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[13]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.700 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 3: MET (0.155 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[16]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[30][16]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[16]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 77.800 (P) 86.100 (P) + Arrival:= -6.064 2.236 + + Hold:+ 7.545 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 101.481 + Launch Clock:= 2.236 + Data Path:+ 99.400 + Slack:= 0.155 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 22.300 | -51.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 19.400 | 25.300 | -26.564 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 20.300 | 7.600 | -18.964 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_48 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00006/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 7.300 | 21.200 | 2.236 | + | cpu/stage1/regfile/CTS_49 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[30][16]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 18.600 | 20.800 | 23.036 | + | cpu/stage1/regfile/mem[30][16] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2195_mem_30_16/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.900 | 33.000 | 56.036 | + | cpu/stage1/regfile/FE_PHN2195_mem_30_16 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77581/Y | | B1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 19.900 | 4.900 | 60.936 | + | cpu/stage1/regfile/n_1555 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77069/Y | | E->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 9.000 | 6.900 | 67.836 | + | cpu/stage1/regfile/n_2040 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77003/Y | | B->Y | F | AOI211xp5_ASAP7_75t_SL | 1 | 7.000 | 5.100 | 72.936 | + | cpu/stage1/regfile/n_2106 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76905__3680/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 7.500 | 12.900 | 85.836 | + | cpu/stage1/rs2_mux_data[16] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g555__8428/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 22.400 | 10.700 | 96.536 | + | cpu/stage1_rs2[16] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g436__1705/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.000 | 5.100 | 101.636 | + | cpu/s1_to_s2_rs2/n_15 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[16]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.100 | 0.100 | 101.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 21.500 | -6.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[16]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 36.700 | 2.700 | -6.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 4: MET (0.188 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[5]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[10][5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[5]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.800 (P) 82.700 (P) + Arrival:= -3.064 -1.164 + + Hold:+ 7.812 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.748 + Launch Clock:= -1.164 + Data Path:+ 106.100 + Slack:= 0.188 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 23.600 | -30.464 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.800 | 7.000 | -23.464 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_37 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00066/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.100 | 22.300 | -1.164 | + | cpu/stage1/regfile/CTS_36 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[10][5]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 20.000 | 21.200 | 20.036 | + | cpu/stage1/regfile/mem[10][5] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC1961_mem_10_5/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 9.300 | 30.700 | 50.736 | + | cpu/stage1/regfile/FE_PHN1961_mem_10_5 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC2891_mem_10_5/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 1 | 16.300 | 26.900 | 77.636 | + | cpu/stage1/regfile/FE_PHN2891_mem_10_5 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77660/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 10.200 | 4.900 | 82.536 | + | cpu/stage1/regfile/n_1480 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76954__2398/Y | | D->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 7.600 | 8.300 | 90.836 | + | cpu/stage1/rs2_mux_data[5] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g549__6417/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 10.000 | 9.900 | 100.736 | + | cpu/stage1_rs2[5] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g424__6417/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.500 | 4.200 | 104.936 | + | cpu/s1_to_s2_rs2/n_27 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[5]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 7.300 | 0.000 | 104.936 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.500 | -3.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[5]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.700 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 5: MET (0.296 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[9]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[11][9]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.900 (P) 83.200 (P) + Arrival:= -2.964 -0.664 + + Hold:+ 7.704 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.740 + Launch Clock:= -0.664 + Data Path:+ 105.700 + Slack:= 0.296 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 22.400 | -29.864 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 22.000 | 7.200 | -22.664 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_19 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00063/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.500 | 22.000 | -0.664 | + | cpu/stage1/regfile/CTS_20 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[11][9]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 17.700 | 19.200 | 18.536 | + | cpu/stage1/regfile/mem[11][9] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3888_mem_11_9/Y | | A->Y | R | HB1xp67_ASAP7_75t_SRAM | 1 | 6.500 | 11.900 | 30.436 | + | cpu/stage1/regfile/FE_PHN3888_mem_11_9 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC1843_mem_11_9/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.300 | 31.800 | 62.236 | + | cpu/stage1/regfile/FE_PHN1843_mem_11_9 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77635/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 18.400 | 4.500 | 66.736 | + | cpu/stage1/regfile/n_1505 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77092/Y | | A->Y | F | AND5x1_ASAP7_75t_SL | 1 | 6.000 | 7.600 | 74.336 | + | cpu/stage1/regfile/n_2017 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76891__9945/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 5.000 | 8.400 | 82.736 | + | cpu/stage1/rs2_mux_data[9] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g572__9945/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 13.400 | 10.800 | 93.536 | + | cpu/stage1_rs2[9] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3585_stage1_rs2_9/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 6.500 | 6.800 | 100.336 | + | cpu/s1_to_s2_rs2/FE_PHN3585_stage1_rs2_9 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g429__4319/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 4.700 | 105.036 | + | cpu/s1_to_s2_rs2/n_22 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[9]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 8.200 | 0.100 | 105.036 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.600 | -2.964 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[9]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.800 | -2.964 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 6: MET (0.304 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[17]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[25][17]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[17]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 81.200 (P) 81.500 (P) + Arrival:= -2.664 -2.364 + + Hold:+ 7.796 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 105.132 + Launch Clock:= -2.364 + Data Path:+ 107.800 + Slack:= 0.304 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 22.100 | -30.164 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 21.900 | 7.000 | -23.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00021/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.100 | 20.800 | -2.364 | + | cpu/stage1/regfile/CTS_8 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[25][17]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 15.800 | 20.800 | 18.436 | + | cpu/stage1/regfile/mem[25][17] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2335_mem_25_17/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 9.200 | 31.500 | 49.936 | + | cpu/stage1/regfile/FE_PHN2335_mem_25_17 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC2899_mem_25_17/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 1 | 17.600 | 18.200 | 68.136 | + | cpu/stage1/regfile/FE_PHN2899_mem_25_17 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77571/Y | | B1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 9.600 | 5.200 | 73.336 | + | cpu/stage1/regfile/n_1565 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77185/Y | | C->Y | F | AND4x1_ASAP7_75t_SL | 1 | 9.200 | 6.700 | 80.036 | + | cpu/stage1/regfile/n_1933 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76946__9315/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 4.000 | 10.500 | 90.536 | + | cpu/stage1/rs2_mux_data[17] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g553__6260/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 18.000 | 10.500 | 101.036 | + | cpu/stage1_rs2[17] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g438__8246/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.900 | 4.400 | 105.436 | + | cpu/s1_to_s2_rs2/n_13 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[17]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 7.500 | 0.100 | 105.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.900 | -2.664 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[17]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.600 | 6.100 | -2.664 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 7: MET (0.461 ps) Hold Check with Pin cpu/s2_to_s3_pc/register_reg[23]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_pc/register_reg[23]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 83.800 (P) 73.600 (P) + Arrival:= -0.064 -10.264 + + Hold:+ 8.039 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 107.975 + Launch Clock:= -10.264 + Data Path:+ 118.700 + Slack:= 0.461 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.100 | -32.164 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.200 | 21.900 | -10.264 | + | NST/GCLK | | | | | | | | | + | cpu/s1_to_s2_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_pc/register_reg[23]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.700 | 21.700 | 11.436 | + | cpu/stage2_pc[23] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2618_stage2_pc_23/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.700 | 32.200 | 43.636 | + | cpu/FE_PHN2618_stage2_pc_23 | | | R | (net) | 2 | | | | + | cpu/s2_to_s3_pc/FE_PHC3328_stage2_pc_23/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 18.900 | 31.900 | 75.536 | + | cpu/s2_to_s3_pc/FE_PHN3328_stage2_pc_23 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3599_stage2_pc_23/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 14.400 | 28.000 | 103.536 | + | cpu/s2_to_s3_pc/FE_PHN3599_stage2_pc_23 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/g444__5115/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 10.300 | 4.900 | 108.436 | + | cpu/s2_to_s3_pc/n_7 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_pc/register_reg[23]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 8.700 | 0.100 | 108.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.000 | -26.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 25.100 | 26.500 | -0.064 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[23]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 42.800 | 8.500 | -0.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 8: MET (0.476 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[10]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[27][10]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[10]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.900 (P) 85.700 (P) + Arrival:= -2.964 1.836 + + Hold:+ 7.824 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.860 + Launch Clock:= 1.836 + Data Path:+ 103.500 + Slack:= 0.476 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 24.400 | -27.864 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 23.300 | 8.000 | -19.864 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00015/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 7.800 | 21.700 | 1.836 | + | cpu/stage1/regfile/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[27][10]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 15.800 | 20.100 | 21.936 | + | cpu/stage1/regfile/mem[27][10] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2338_mem_27_10/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.300 | 30.200 | 52.136 | + | cpu/stage1/regfile/FE_PHN2338_mem_27_10 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC2970_mem_27_10/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 1 | 15.900 | 16.400 | 68.536 | + | cpu/stage1/regfile/FE_PHN2970_mem_27_10 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77418/Y | | C2->Y | F | AOI222xp33_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 76.436 | + | cpu/stage1/regfile/n_1722 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76933__3680/Y | | C->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 10.000 | 13.400 | 89.836 | + | cpu/stage1/rs2_mux_data[10] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g570__6161/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 20.100 | 11.400 | 101.236 | + | cpu/stage1_rs2[10] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g431__5526/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 6.300 | 4.100 | 105.336 | + | cpu/s1_to_s2_rs2/n_20 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[10]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 7.100 | 0.000 | 105.336 | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.600 | -2.964 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[10]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.800 | -2.964 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 9: MET (0.585 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[4][26]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[26]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[4][26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 102.300 (P) 76.600 (P) + Arrival:= 18.436 -7.264 + + Hold:+ 7.315 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 125.751 + Launch Clock:= -7.264 + Data Path:+ 133.600 + Slack:= 0.585 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 25.300 | -7.264 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[26]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 41.500 | 22.000 | 14.736 | + | cpu/stage3_alu[26] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1154/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 1 | 8.300 | 8.100 | 22.836 | + | cpu/stage3/wbselmux/n_7 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1138/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 1 | 4.600 | 6.900 | 29.736 | + | cpu/stage3/wbselmux/n_23 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1095/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 6.200 | 7.900 | 37.636 | + | cpu/wb_data[26] | | | R | (net) | 3 | | | | + | cpu/FE_PHC3919_wb_data_26/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 6.200 | 6.900 | 44.536 | + | cpu/FE_PHN3919_wb_data_26 | | | R | (net) | 1 | | | | + | cpu/FE_PHC3514_wb_data_26/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 1 | 4.000 | 29.500 | 74.036 | + | cpu/FE_PHN3514_wb_data_26 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC2715_wb_data_26/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 19.800 | 27.900 | 101.936 | + | cpu/stage1/FE_PHN2715_wb_data_26 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC908_wb_data_26/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 7 | 8.400 | 19.300 | 121.236 | + | cpu/stage1/FE_OFN1039_wb_data_26 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g51144/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 29.700 | 5.100 | 126.336 | + | cpu/stage1/regfile/n_18 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/mem_reg[4][26]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 12.800 | 0.000 | 126.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 29.100 | -20.364 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.600 | 10.500 | -9.864 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_62 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00084/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 12.300 | 28.300 | 18.436 | + | cpu/stage1/regfile/CTS_63 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[4][26]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 25.300 | 10.200 | 18.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 10: MET (0.588 ps) Hold Check with Pin cpu/s2_to_s3_pc/register_reg[22]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_pc/register_reg[22]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 83.700 (P) 73.600 (P) + Arrival:= -0.164 -10.264 + + Hold:+ 8.012 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 107.848 + Launch Clock:= -10.264 + Data Path:+ 118.700 + Slack:= 0.588 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.100 | -32.164 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.200 | 21.900 | -10.264 | + | NST/GCLK | | | | | | | | | + | cpu/s1_to_s2_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_pc/register_reg[22]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.700 | 21.800 | 11.536 | + | cpu/stage2_pc[22] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2615_stage2_pc_22/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.800 | 31.900 | 43.436 | + | cpu/FE_PHN2615_stage2_pc_22 | | | R | (net) | 2 | | | | + | cpu/s2_to_s3_pc/FE_PHC3329_stage2_pc_22/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 18.400 | 31.500 | 74.936 | + | cpu/s2_to_s3_pc/FE_PHN3329_stage2_pc_22 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3692_stage2_pc_22/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 14.000 | 28.500 | 103.436 | + | cpu/s2_to_s3_pc/FE_PHN3692_stage2_pc_22 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/g443__1881/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 11.100 | 5.000 | 108.436 | + | cpu/s2_to_s3_pc/n_8 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_pc/register_reg[22]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.000 | 0.000 | 108.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.000 | -26.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 25.100 | 26.400 | -0.164 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[22]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 42.800 | 8.400 | -0.164 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 11: MET (0.614 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[4]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[8][4]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[4]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 79.300 (P) 80.700 (P) + Arrival:= -4.564 -3.164 + + Hold:+ 8.786 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.222 + Launch Clock:= -3.164 + Data Path:+ 108.000 + Slack:= 0.614 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 21.100 | -31.164 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 21.700 | 7.000 | -24.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_23 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00072/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.100 | 21.000 | -3.164 | + | cpu/stage1/regfile/CTS_24 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[8][4]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 17.700 | 20.700 | 17.536 | + | cpu/stage1/regfile/mem[8][4] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2125_mem_8_4/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.900 | 30.800 | 48.336 | + | cpu/stage1/regfile/FE_PHN2125_mem_8_4 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC2892_mem_8_4/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 1 | 16.600 | 23.000 | 71.336 | + | cpu/stage1/regfile/FE_PHN2892_mem_8_4 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77668/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 10.000 | 5.100 | 76.436 | + | cpu/stage1/regfile/n_1472 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76955__5107/Y | | D->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 8.000 | 10.800 | 87.236 | + | cpu/stage1/rs2_mux_data[4] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g550__5477/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 14.400 | 9.700 | 96.936 | + | cpu/stage1_rs2[4] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g435__2802/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 4.500 | 7.900 | 104.836 | + | cpu/s1_to_s2_rs2/n_16 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[4]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 13.100 | 0.100 | 104.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 23.000 | -4.564 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[4]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.200 | 4.200 | -4.564 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 12: MET (0.736 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[31]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_rs1/register_reg[30]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 95.000 (P) 71.400 (P) + Arrival:= 11.136 -12.464 + + Hold:+ 7.764 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 118.901 + Launch Clock:= -12.464 + Data Path:+ 132.100 + Slack:= 0.736 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.300 | -31.964 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.300 | 19.500 | -12.464 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs1/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs1/register_reg[30]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_L | 1 | 30.900 | 25.000 | 12.536 | + | cpu/stage2_rs1[30] | | | R | (net) | 1 | | | | + | cpu/stage2/rs1DataSel/FE_PHC2632_stage2_rs1_30/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 1 | 8.700 | 15.100 | 27.636 | + | cpu/stage2/rs1DataSel/FE_PHN2632_stage2_rs1_30 | | | R | (net) | 1 | | | | + | cpu/stage2/rs1DataSel/g596/Y | | A->Y | R | AND2x2_ASAP7_75t_SL | 1 | 7.400 | 7.600 | 35.236 | + | cpu/stage2/rs1DataSel/n_17 | | | R | (net) | 1 | | | | + | cpu/stage2/rs1DataSel/g565/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 6 | 4.000 | 11.500 | 46.736 | + | cpu/stage2/stage2_rs1_data[30] | | | R | (net) | 6 | | | | + | cpu/stage2/aselmux/g564/Y | | A1->Y | R | AO22x1_ASAP7_75t_SL | 15 | 13.200 | 31.100 | 77.836 | + | cpu/stage2/stage2_alu_in1[30] | | | R | (net) | 15 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1661/Y | | A->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 51.500 | 5.500 | 83.336 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_106 | | | F | (net) | 2 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1504/Y | | B->Y | F | OA21x2_ASAP7_75t_SL | 1 | 11.100 | 7.800 | 91.136 | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_n_238 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/sub_25_21_Y_add_24_21_g1503/Y | | B->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 4.000 | 4.400 | 95.536 | + | cpu/stage2/alu/n_322 | | | R | (net) | 1 | | | | + | cpu/stage2/alu/g5521/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 4 | 6.500 | 11.900 | 107.436 | + | dcache_addr[31] | | | R | (net) | 4 | | | | + | cpu/stage1/pcselmux/g961__6783/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 9.800 | 8.300 | 115.736 | + | cpu/stage1/stage1_pc_mux_to_pc[31] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g362__7482/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.700 | 3.900 | 119.636 | + | cpu/stage1/pcreg/n_18 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[31]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.800 | 0.000 | 119.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 23.100 | 11.136 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 36.400 | 7.200 | 11.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 13: MET (0.839 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[2]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[15][2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[2]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 78.800 (P) 82.500 (P) + Arrival:= -5.064 -1.364 + + Hold:+ 7.461 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 102.397 + Launch Clock:= -1.364 + Data Path:+ 104.600 + Slack:= 0.839 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 22.300 | -51.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 19.400 | 25.800 | -26.064 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 20.300 | 8.800 | -17.264 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_58 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00051/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 9.700 | 15.900 | -1.364 | + | cpu/stage1/regfile/CTS_59 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[15][2]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 23.400 | 20.900 | 19.536 | + | cpu/stage1/regfile/mem[15][2] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3461_mem_15_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.400 | 31.000 | 50.536 | + | cpu/stage1/regfile/FE_PHN3461_mem_15_2 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g78093/Y | | B1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 17.000 | 4.500 | 55.036 | + | cpu/stage1/regfile/n_1047 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77373/Y | | D->Y | F | AND4x1_ASAP7_75t_SL | 1 | 9.500 | 7.000 | 62.036 | + | cpu/stage1/regfile/n_1767 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77054/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 4.000 | 4.200 | 66.236 | + | cpu/stage1/regfile/n_2055 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76977__2346/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.800 | 4.000 | 70.236 | + | cpu/stage1/regfile/n_2132 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76949__2346/Y | | B->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 6.900 | 5.900 | 76.136 | + | cpu/stage1/rs2_mux_data[2] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g554__4319/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.100 | 8.800 | 84.936 | + | cpu/stage1_rs2[2] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC2787_stage1_rs2_2/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 4.600 | 6.300 | 91.236 | + | cpu/s1_to_s2_rs2/FE_PHN2787_stage1_rs2_2 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3594_stage1_rs2_2/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 4.000 | 6.300 | 97.536 | + | cpu/s1_to_s2_rs2/FE_PHN3594_stage1_rs2_2 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g422__1666/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.200 | 5.700 | 103.236 | + | cpu/s1_to_s2_rs2/n_29 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[2]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.900 | 0.300 | 103.236 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 22.500 | -5.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[2]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.000 | 3.700 | -5.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 14: MET (0.846 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[9]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_imm/register_reg[9]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 97.700 (P) 73.300 (P) + Arrival:= 13.836 -10.564 + + Hold:+ 8.054 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 121.891 + Launch Clock:= -10.564 + Data Path:+ 133.300 + Slack:= 0.846 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.700 | -31.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.300 | 21.000 | -10.564 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_imm/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_imm/register_reg[9]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.700 | 21.600 | 11.036 | + | cpu/stage2_imm[9] | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g574/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 8.300 | 9.300 | 20.336 | + | cpu/stage2/stage2_alu_in2[9] | | | R | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC638_stage2_alu_in2_9/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 5 | 7.200 | 6.200 | 26.536 | + | cpu/stage2/alu/FE_DBTN48_stage2_alu_in2_9 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/FE_OFC639_stage2_alu_in2_9/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 9.700 | 8.300 | 34.836 | + | cpu/stage2/alu/FE_OFN831_stage2_alu_in2_9 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/g5552/Y | | B2->Y | F | AOI222xp33_ASAP7_75t_SL | 1 | 13.500 | 7.000 | 41.836 | + | cpu/stage2/alu/n_169 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5513/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 10.500 | 26.500 | 68.336 | + | dcache_addr[9] | | | R | (net) | 4 | | | | + | cpu/stage1/pcselmux/g975__9315/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 58.900 | 14.700 | 83.036 | + | cpu/stage1/pcselmux/n_29 | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/FE_PHC3546_n_29/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 1 | 6.100 | 16.000 | 99.036 | + | cpu/stage1/pcselmux/FE_PHN3546_n_29 | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g931__8428/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 2 | 9.300 | 6.300 | 105.336 | + | cpu/stage1/stage1_pc_mux_to_pc[9] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g375__6260/Y | | B->Y | F | NOR2xp33_ASAP7_75t_L | 1 | 4.600 | 5.400 | 110.736 | + | cpu/stage1/pcreg/n_5 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2860_n_5/Y | | A->Y | F | HB2xp67_ASAP7_75t_SL | 1 | 7.500 | 12.000 | 122.736 | + | cpu/stage1/pcreg/FE_PHN2860_n_5 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[9]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.000 | 122.736 | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 25.800 | 13.836 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[9]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 39.100 | 9.900 | 13.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 15: MET (0.851 ps) Hold Check with Pin cpu/s2_to_s3_pc/register_reg[29]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_pc/register_reg[29]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/register_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 83.500 (P) 73.200 (P) + Arrival:= -0.364 -10.664 + + Hold:+ 10.049 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.685 + Launch Clock:= -10.664 + Data Path:+ 121.200 + Slack:= 0.851 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.100 | -32.164 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.200 | 21.500 | -10.664 | + | NST/GCLK | | | | | | | | | + | cpu/s1_to_s2_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_pc/register_reg[29]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.700 | 21.500 | 10.836 | + | cpu/stage2_pc[29] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2620_stage2_pc_29/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.300 | 29.400 | 40.236 | + | cpu/FE_PHN2620_stage2_pc_29 | | | R | (net) | 2 | | | | + | cpu/s2_to_s3_pc/FE_PHC3355_stage2_pc_29/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 14.500 | 30.200 | 70.436 | + | cpu/s2_to_s3_pc/FE_PHN3355_stage2_pc_29 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3764_stage2_pc_29/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 13.400 | 28.700 | 99.136 | + | cpu/s2_to_s3_pc/FE_PHN3764_stage2_pc_29 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3988_stage2_pc_29/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 11.600 | 7.500 | 106.636 | + | cpu/s2_to_s3_pc/FE_PHN3988_stage2_pc_29 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/g421__9945/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.900 | 110.536 | + | cpu/s2_to_s3_pc/n_30 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_pc/register_reg[29]/D | | D | F | DFFHQNx1_ASAP7_75t_L | 1 | 6.700 | 0.000 | 110.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.000 | -26.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 25.100 | 26.200 | -0.364 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[29]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_L | 32 | 42.800 | 8.200 | -0.364 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 16: MET (0.990 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[22]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[15][22]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 75.900 (P) 84.700 (P) + Arrival:= -7.964 0.836 + + Hold:+ 7.410 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 99.446 + Launch Clock:= 0.836 + Data Path:+ 99.600 + Slack:= 0.990 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 22.300 | -51.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 19.400 | 25.800 | -26.064 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 20.300 | 8.800 | -17.264 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_58 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00051/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 9.700 | 18.100 | 0.836 | + | cpu/stage1/regfile/CTS_59 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[15][22]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 26.700 | 21.400 | 22.236 | + | cpu/stage1/regfile/mem[15][22] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC1739_mem_15_22/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.900 | 30.300 | 52.536 | + | cpu/stage1/regfile/FE_PHN1739_mem_15_22 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77807/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 15.800 | 5.100 | 57.636 | + | cpu/stage1/regfile/n_1333 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77085/Y | | B->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 6.400 | 6.200 | 63.836 | + | cpu/stage1/regfile/n_2024 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77004/Y | | B->Y | F | AOI211xp5_ASAP7_75t_SL | 1 | 8.300 | 6.200 | 70.036 | + | cpu/stage1/regfile/n_2105 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76906__1617/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 9.200 | 4.600 | 74.636 | + | cpu/stage1/rs2_mux_data[22] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_OCPC1477_rs2_mux_data_22 | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 6.000 | 11.100 | 85.736 | + | /Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_OCPN1438_rs2_mux_data_22 | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g562__5122/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 10.800 | 9.200 | 94.936 | + | cpu/stage1_rs2[22] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g443__7482/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.300 | 5.500 | 100.436 | + | cpu/s1_to_s2_rs2/n_8 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[22]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.700 | 0.200 | 100.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 19.600 | -7.964 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[22]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.500 | 0.800 | -7.964 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 17: MET (1.007 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[27]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[14][27]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.900 (P) 77.300 (P) + Arrival:= -2.964 -6.564 + + Hold:+ 7.893 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.929 + Launch Clock:= -6.564 + Data Path:+ 112.500 + Slack:= 1.007 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 25.500 | -33.064 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 33.400 | 10.400 | -22.664 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_42 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00054/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 12.100 | 16.100 | -6.564 | + | cpu/stage1/regfile/CTS_43 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[14][27]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 23.500 | 20.900 | 14.336 | + | cpu/stage1/regfile/mem[14][27] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2407_mem_14_27/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.500 | 31.300 | 45.636 | + | cpu/stage1/regfile/FE_PHN2407_mem_14_27 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g78270/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 17.500 | 5.300 | 50.936 | + | cpu/stage1/regfile/n_873 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77181/Y | | E->Y | F | AND5x1_ASAP7_75t_SL | 1 | 9.700 | 9.400 | 60.336 | + | cpu/stage1/regfile/n_1937 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77009/Y | | A2->Y | F | OA211x2_ASAP7_75t_SL | 1 | 4.000 | 11.000 | 71.336 | + | cpu/stage1/regfile/n_2100 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76931__5526/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 5.300 | 7.800 | 79.136 | + | cpu/stage1/rs2_mux_data[27] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g558__3680/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 12.700 | 9.700 | 88.836 | + | cpu/stage1/data2sel_s1/FE_PHN3592_stage1_rs2_27 | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3592_stage1_rs2_27/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 4.800 | 6.700 | 95.536 | + | cpu/stage1_rs2[27] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3938_stage1_rs2_27/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 4.000 | 6.500 | 102.036 | + | cpu/s1_to_s2_rs2/FE_PHN3938_stage1_rs2_27 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g425__5477/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.900 | 105.936 | + | cpu/s1_to_s2_rs2/n_26 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[27]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.600 | 0.000 | 105.936 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.600 | -2.964 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[27]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.600 | 5.800 | -2.964 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 18: MET (1.034 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[6][3]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[6][3]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 98.000 (P) 74.300 (P) + Arrival:= 14.136 -9.564 + + Hold:+ 8.766 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 122.902 + Launch Clock:= -9.564 + Data Path:+ 133.500 + Slack:= 1.034 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 23.000 | -9.564 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[3]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 38.500 | 21.100 | 11.536 | + | cpu/stage3_alu[3] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1145/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.300 | 8.500 | 20.036 | + | cpu/stage3/wbselmux/n_16 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1113/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 5.800 | 8.900 | 28.936 | + | cpu/wb_data[3] | | | R | (net) | 3 | | | | + | cpu/FE_PHC3916_wb_data_3/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 1 | 8.000 | 19.900 | 48.836 | + | cpu/FE_PHN3916_wb_data_3 | | | R | (net) | 1 | | | | + | cpu/FE_PHC3521_wb_data_3/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 8.700 | 19.600 | 68.436 | + | cpu/FE_PHN3521_wb_data_3 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC2716_wb_data_3/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 1 | 11.500 | 24.400 | 92.836 | + | cpu/stage1/FE_PHN2716_wb_data_3 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OCPC1516_wb_data_3/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 7 | 8.900 | 20.400 | 113.236 | + | cpu/stage1/FE_OCPN1477_wb_data_3 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g51163/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 32.300 | 10.700 | 123.936 | + | cpu/stage1/regfile/n_1 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/mem_reg[6][3]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 2 | 20.800 | 0.200 | 123.936 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 25.500 | -24.364 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 30.300 | 9.600 | -14.764 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_27 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00078/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 10.400 | 28.900 | 14.136 | + | cpu/stage1/regfile/CTS_28 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[6][3]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 25.500 | 11.000 | 14.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 19: MET (1.080 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[6]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[26][6]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[6]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.800 (P) 83.500 (P) + Arrival:= -3.064 -0.364 + + Hold:+ 7.620 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.556 + Launch Clock:= -0.364 + Data Path:+ 106.000 + Slack:= 1.080 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 23.800 | -28.464 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 23.200 | 7.300 | -21.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_5 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00018/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.800 | 20.800 | -0.364 | + | cpu/stage1/regfile/CTS_4 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[26][6]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 15.600 | 20.600 | 20.236 | + | cpu/stage1/regfile/mem[26][6] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2293_mem_26_6/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 9.000 | 30.100 | 50.336 | + | cpu/stage1/regfile/FE_PHN2293_mem_26_6 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g78050/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 15.400 | 5.400 | 55.736 | + | cpu/stage1/regfile/n_1089 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77165/Y | | E->Y | F | AND5x1_ASAP7_75t_SL | 1 | 9.900 | 10.100 | 65.836 | + | cpu/stage1/regfile/n_1948 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76941__1881/Y | | A2->Y | R | OAI211xp5_ASAP7_75t_SL | 1 | 4.600 | 16.500 | 82.336 | + | cpu/stage1/rs2_mux_data[6] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g561__1705/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 19.000 | 11.500 | 93.836 | + | cpu/stage1_rs2[6] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3588_stage1_rs2_6/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 6.600 | 6.800 | 100.636 | + | cpu/s1_to_s2_rs2/FE_PHN3588_stage1_rs2_6 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g426__2398/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 5.000 | 105.636 | + | cpu/s1_to_s2_rs2/n_25 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[6]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 8.900 | 0.100 | 105.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.500 | -3.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[6]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.700 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 20: MET (1.135 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[23][2]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[23][2]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 95.200 (P) 74.200 (P) + Arrival:= 11.336 -9.664 + + Hold:+ 11.365 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 122.701 + Launch Clock:= -9.664 + Data Path:+ 133.500 + Slack:= 1.135 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 22.900 | -9.664 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[2]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 38.500 | 21.100 | 11.436 | + | cpu/stage3_alu[2] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1147/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.400 | 8.000 | 19.436 | + | cpu/stage3/wbselmux/n_14 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1114/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 5.100 | 7.900 | 27.336 | + | cpu/wb_data[2] | | | R | (net) | 3 | | | | + | cpu/FE_PHC3923_wb_data_2/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 6.500 | 8.000 | 35.336 | + | cpu/FE_PHN3923_wb_data_2 | | | R | (net) | 1 | | | | + | cpu/FE_PHC3517_wb_data_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 6.900 | 28.800 | 64.136 | + | cpu/FE_PHN3517_wb_data_2 | | | R | (net) | 1 | | | | + | cpu/FE_PHC2707_wb_data_2/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 13.900 | 31.200 | 95.336 | + | cpu/FE_PHN2707_wb_data_2 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OCPC1438_wb_data_2/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 7 | 14.900 | 19.500 | 114.836 | + | cpu/stage1/FE_OCPN1403_wb_data_2 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g51162/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 29.100 | 9.000 | 123.836 | + | cpu/stage1/regfile/n_2 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/mem_reg[23][2]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 2 | 17.900 | 0.000 | 123.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 30.400 | -26.464 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 42.700 | 10.800 | -15.664 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_40 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00027/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 12.900 | 27.000 | 11.336 | + | cpu/stage1/regfile/CTS_41 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[23][2]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 40.800 | 13.200 | 11.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 21: MET (1.138 ps) Hold Check with Pin cpu/s1_to_s2_inst/register_reg[7]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/register_reg[7]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 85.100 (P) 77.900 (P) + Arrival:= 1.236 -5.964 + + Hold:+ 7.762 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 108.998 + Launch Clock:= -5.964 + Data Path:+ 116.100 + Slack:= 1.138 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 22.200 | -5.964 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.100 | 21.300 | 15.336 | + | cpu/stage2_inst[8] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2647_stage2_inst_8/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 3 | 8.100 | 29.900 | 45.236 | + | cpu/FE_PHN2647_stage2_inst_8 | | | R | (net) | 3 | | | | + | cpu/stage1/nopsel/g472__3680/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 25.600 | 3.900 | 49.136 | + | cpu/stage1/nopsel/n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g465__2398/Y | | C->Y | F | AND5x1_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 57.036 | + | cpu/stage1/nopsel/FE_PHN4110_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC4110_n_14/Y | | A->Y | F | HB1xp67_ASAP7_75t_L | 1 | 4.000 | 8.600 | 65.636 | + | cpu/stage1/nopsel/n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC2690_n_14/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 6.300 | 7.200 | 72.836 | + | cpu/stage1/nopsel/FE_PHN2690_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 4 | 3.800 | 11.200 | 84.036 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1417_NOPSignal/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 9.100 | 9.400 | 93.436 | + | cpu/stage1/nopselmux/FE_OFN971_FE_DBTN75_NOPSignal | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_OFC843_FE_DBTN75_NOPSignal | | A->Y | R | INVx3_ASAP7_75t_SL | 14 | 5.800 | 4.800 | 98.236 | + | /Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OFN974_FE_DBTN75_NOPSignal | | | R | (net) | 14 | | | | + | cpu/stage1/nopselmux/g408__3680/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 9.900 | 8.100 | 106.336 | + | cpu/stage1_inst[7] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_inst/g380__1881/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.800 | 110.136 | + | cpu/s1_to_s2_inst/n_23 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_inst/register_reg[7]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.000 | 110.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 29.700 | -22.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 33.200 | 23.600 | 1.236 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[7]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.900 | 5.900 | 1.236 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 22: MET (1.160 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[23][4]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[4]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[23][4]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 94.700 (P) 73.900 (P) + Arrival:= 10.836 -9.964 + + Hold:+ 11.640 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 122.476 + Launch Clock:= -9.964 + Data Path:+ 133.600 + Slack:= 1.160 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 22.600 | -9.964 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[4]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_L | 1 | 38.500 | 24.900 | 14.936 | + | cpu/stage3_alu[4] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1143/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.700 | 7.900 | 22.836 | + | cpu/stage3/wbselmux/n_18 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1110/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 5.000 | 8.500 | 31.336 | + | cpu/wb_data[4] | | | R | (net) | 3 | | | | + | cpu/FE_PHC2703_wb_data_4/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 7.100 | 33.000 | 64.336 | + | cpu/FE_PHN2703_wb_data_4 | | | R | (net) | 2 | | | | + | cpu/stage1/FE_PHC2869_wb_data_4/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 20.300 | 30.200 | 94.536 | + | cpu/stage1/FE_PHN2869_wb_data_4 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC1192_wb_data_4/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 6 | 11.300 | 19.900 | 114.436 | + | cpu/stage1/FE_OFN1208_wb_data_4 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g51164/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 30.200 | 9.200 | 123.636 | + | cpu/stage1/regfile/n_0 | | | F | (net) | 2 | | | | + | cpu/stage1/regfile/mem_reg[23][4]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 2 | 18.500 | 0.000 | 123.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 16.400 | -56.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 8.000 | 30.400 | -26.464 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 42.700 | 10.800 | -15.664 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_40 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00027/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 12.900 | 26.500 | 10.836 | + | cpu/stage1/regfile/CTS_41 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[23][4]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 40.800 | 12.700 | 10.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 23: MET (1.202 ps) Hold Check with Pin cpu/s2_to_s3_pc/register_reg[9]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_pc/register_reg[9]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.800 (P) 73.100 (P) + Arrival:= -3.064 -10.764 + + Hold:+ 7.998 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.934 + Launch Clock:= -10.764 + Data Path:+ 116.900 + Slack:= 1.202 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.100 | -32.164 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.200 | 21.400 | -10.764 | + | NST/GCLK | | | | | | | | | + | cpu/s1_to_s2_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_pc/register_reg[9]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.400 | 21.600 | 10.836 | + | cpu/stage2_pc[9] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2631_stage2_pc_9/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.500 | 31.400 | 42.236 | + | cpu/FE_PHN2631_stage2_pc_9 | | | R | (net) | 2 | | | | + | cpu/s2_to_s3_pc/FE_PHC3351_stage2_pc_9/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 17.600 | 31.400 | 73.636 | + | cpu/s2_to_s3_pc/FE_PHN3351_stage2_pc_9 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3598_stage2_pc_9/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 14.000 | 28.300 | 101.936 | + | cpu/s2_to_s3_pc/FE_PHN3598_stage2_pc_9 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/g429__5107/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 10.800 | 4.200 | 106.136 | + | cpu/s2_to_s3_pc/n_22 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_pc/register_reg[9]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 7.900 | 0.000 | 106.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.000 | -26.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 25.100 | 23.500 | -3.064 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[9]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 41.000 | 5.500 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 24: MET (1.222 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[14]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[28][14]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 93.300 (P) 78.300 (P) + Arrival:= 9.436 -5.564 + + Hold:+ 7.878 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 117.314 + Launch Clock:= -5.564 + Data Path:+ 124.100 + Slack:= 1.222 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 26.000 | -32.564 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 33.400 | 7.400 | -25.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_38 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00012/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.600 | 19.600 | -5.564 | + | cpu/stage1/regfile/CTS_39 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[28][14]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 13.600 | 20.100 | 14.536 | + | cpu/stage1/regfile/mem[28][14] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC1850_mem_28_14/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.500 | 33.100 | 47.636 | + | cpu/stage1/regfile/FE_PHN1850_mem_28_14 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g78277/Y | | B1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 20.200 | 6.000 | 53.636 | + | cpu/stage1/regfile/n_866 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76930__8428/Y | | A3->Y | F | AO31x2_ASAP7_75t_SL | 1 | 10.800 | 9.900 | 63.536 | + | cpu/stage1/regfile/n_2153 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76886__5115/Y | | C->Y | R | NAND4xp75_ASAP7_75t_SL | 1 | 4.700 | 5.900 | 69.436 | + | cpu/stage1/rs1_mux_data[14] | | | R | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g576__6417/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 2 | 6.000 | 10.600 | 80.036 | + | cpu/stage1_rs1[14] | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/g1256__5107/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 2 | 7.100 | 9.200 | 89.236 | + | cpu/stage1/pcadder/n_45 | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NOR2x1p5_ASAP7_75t_SL | 2 | 4.700 | 3.900 | 93.136 | + | 33_g1507__9315/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_24 | | | | | | | | | + | cpu/stage1/pcadder/FE_OFC1223_add_18_35_Y_add_17_3 | | A->Y | R | INVx2_ASAP7_75t_SL | 3 | 5.300 | 3.300 | 96.436 | + | 4_Y_add_16_33_n_24/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 3 | | | | + | 33_n_23 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.900 | 4.900 | 101.336 | + | 33_g1371__5115/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 1 | | | | + | 33_n_134 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | XOR2xp5_ASAP7_75t_SL | 1 | 9.000 | 5.600 | 106.936 | + | 33_g1259__6161/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[14] | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g935__1617/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 7.300 | 7.800 | 114.736 | + | cpu/stage1/stage1_pc_mux_to_pc[14] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g357__8246/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.300 | 3.800 | 118.536 | + | cpu/stage1/pcreg/n_23 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[14]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.000 | 118.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 21.400 | 9.436 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[14]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.300 | 5.500 | 9.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 25: MET (1.222 ps) Hold Check with Pin cpu/s2_to_s3_pc/register_reg[13]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_pc/register_reg[13]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/register_reg[13]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 79.100 (P) 72.200 (P) + Arrival:= -4.764 -11.664 + + Hold:+ 7.978 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 103.214 + Launch Clock:= -11.664 + Data Path:+ 116.100 + Slack:= 1.222 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.100 | -32.164 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.200 | 20.500 | -11.664 | + | NST/GCLK | | | | | | | | | + | cpu/s1_to_s2_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_pc/register_reg[13]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.300 | 21.600 | 9.936 | + | cpu/stage2_pc[13] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2600_stage2_pc_13/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.600 | 30.800 | 40.736 | + | cpu/FE_PHN2600_stage2_pc_13 | | | R | (net) | 2 | | | | + | cpu/s2_to_s3_pc/FE_PHC3338_stage2_pc_13/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 16.600 | 31.700 | 72.436 | + | cpu/s2_to_s3_pc/FE_PHN3338_stage2_pc_13 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3708_stage2_pc_13/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 14.900 | 27.800 | 100.236 | + | cpu/s2_to_s3_pc/FE_PHN3708_stage2_pc_13 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/g419__6161/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 10.000 | 4.200 | 104.436 | + | cpu/s2_to_s3_pc/n_32 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_pc/register_reg[13]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 7.800 | 0.000 | 104.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.000 | -26.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 25.100 | 21.800 | -4.764 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[13]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 40.400 | 3.800 | -4.764 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 26: MET (1.282 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[7]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[2][7]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[7]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 78.800 (P) 82.200 (P) + Arrival:= -5.064 -1.664 + + Hold:+ 7.518 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 102.454 + Launch Clock:= -1.664 + Data Path:+ 105.400 + Slack:= 1.282 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 24.400 | -27.864 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 23.300 | 7.900 | -19.964 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_31 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00090/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 7.600 | 18.300 | -1.664 | + | cpu/stage1/regfile/CTS_32 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[2][7]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 13.300 | 20.100 | 18.436 | + | cpu/stage1/regfile/mem[2][7] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2172_mem_2_7/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 8.500 | 26.900 | 45.336 | + | cpu/stage1/regfile/FE_PHN2172_mem_2_7 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3504_mem_2_7/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 2 | 10.900 | 23.500 | 68.836 | + | cpu/stage1/regfile/FE_PHN3504_mem_2_7 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77647/Y | | B1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 13.200 | 4.900 | 73.736 | + | cpu/stage1/regfile/n_1493 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76894__1666/Y | | E->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 9.100 | 8.900 | 82.636 | + | cpu/stage1/rs2_mux_data[7] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g575__1666/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 10.500 | 9.300 | 91.936 | + | cpu/stage1_rs2[7] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC2790_stage1_rs2_7/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 4.500 | 6.400 | 98.336 | + | cpu/s1_to_s2_rs2/FE_PHN2790_stage1_rs2_7 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g427__5107/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 5.400 | 103.736 | + | cpu/s1_to_s2_rs2/n_24 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[7]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.500 | 0.200 | 103.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 22.500 | -5.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[7]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.000 | 3.700 | -5.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 27: MET (1.288 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[3]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[17][3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[3]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.800 (P) 82.800 (P) + Arrival:= -3.064 -1.064 + + Hold:+ 7.812 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.748 + Launch Clock:= -1.064 + Data Path:+ 107.100 + Slack:= 1.288 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 21.200 | -31.064 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 22.100 | 7.100 | -23.964 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_15 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00045/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.400 | 22.900 | -1.064 | + | cpu/stage1/regfile/CTS_16 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[17][3]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 19.000 | 21.200 | 20.136 | + | cpu/stage1/regfile/mem[17][3] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC1925_mem_17_3/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 9.300 | 27.800 | 47.936 | + | cpu/stage1/regfile/FE_PHN1925_mem_17_3 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3491_mem_17_3/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 2 | 11.900 | 29.600 | 77.536 | + | cpu/stage1/regfile/FE_PHN3491_mem_17_3 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77099/Y | | A2->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 16.600 | 7.900 | 85.436 | + | cpu/stage1/regfile/n_2010 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76913__1881/Y | | C->Y | R | NAND4xp25_ASAP7_75t_SL | 1 | 6.800 | 6.600 | 92.036 | + | cpu/stage1/rs2_mux_data[3] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g551__2398/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 8.900 | 9.800 | 101.836 | + | cpu/stage1_rs2[3] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g423__7410/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.600 | 4.200 | 106.036 | + | cpu/s1_to_s2_rs2/n_28 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[3]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 7.300 | 0.000 | 106.036 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.500 | -3.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[3]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.700 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 28: MET (1.299 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[8]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_imm/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 97.200 (P) 73.000 (P) + Arrival:= 13.336 -10.864 + + Hold:+ 7.601 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 120.938 + Launch Clock:= -10.864 + Data Path:+ 133.100 + Slack:= 1.299 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.700 | -31.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.300 | 20.700 | -10.864 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_imm/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_imm/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_L | 1 | 33.700 | 25.700 | 14.836 | + | cpu/stage2_imm[8] | | | R | (net) | 1 | | | | + | cpu/stage2/bselmux/g575/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 9.300 | 8.300 | 23.136 | + | cpu/stage2/stage2_alu_in2[8] | | | R | (net) | 1 | | | | + | cpu/stage2/alu/FE_OFC661_stage2_alu_in2_8/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 5 | 5.500 | 7.000 | 30.136 | + | cpu/stage2/alu/FE_DBTN47_stage2_alu_in2_8 | | | F | (net) | 5 | | | | + | cpu/stage2/alu/FE_OFC662_stage2_alu_in2_8/Y | | A->Y | R | INVx1_ASAP7_75t_SL | 3 | 11.800 | 7.900 | 38.036 | + | cpu/stage2/alu/FE_OFN848_stage2_alu_in2_8 | | | R | (net) | 3 | | | | + | cpu/stage2/alu/g5553/Y | | B2->Y | F | AOI222xp33_ASAP7_75t_SL | 1 | 12.700 | 7.100 | 45.136 | + | cpu/stage2/alu/n_168 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5514/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 4 | 10.700 | 26.500 | 71.636 | + | dcache_addr[8] | | | R | (net) | 4 | | | | + | cpu/stage1/pcselmux/g977__2883/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 57.900 | 14.200 | 85.836 | + | cpu/stage1/pcselmux/n_27 | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g952__7410/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 2 | 5.100 | 6.100 | 91.936 | + | cpu/stage1/stage1_pc_mux_to_pc[8] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g374__5107/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 4.800 | 6.800 | 98.736 | + | cpu/stage1/pcreg/n_6 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_PHC2856_n_6/Y | | A->Y | F | HB4xp67_ASAP7_75t_SL | 1 | 11.000 | 23.500 | 122.236 | + | cpu/stage1/pcreg/FE_PHN2856_n_6 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[8]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.700 | 0.000 | 122.236 | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 25.300 | 13.336 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[8]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 39.100 | 9.400 | 13.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 29: MET (1.350 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[13]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[17][13]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[13]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 94.600 (P) 83.000 (P) + Arrival:= 10.736 -0.864 + + Hold:+ 7.950 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 118.687 + Launch Clock:= -0.864 + Data Path:+ 120.900 + Slack:= 1.350 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 21.200 | -31.064 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 22.100 | 7.100 | -23.964 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_15 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00045/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.400 | 23.100 | -0.864 | + | cpu/stage1/regfile/CTS_16 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[17][13]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 19.100 | 20.600 | 19.736 | + | cpu/stage1/regfile/mem[17][13] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2166_mem_17_13/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.600 | 30.400 | 50.136 | + | cpu/stage1/regfile/FE_PHN2166_mem_17_13 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g79288/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 16.000 | 3.800 | 53.936 | + | cpu/stage1/regfile/n_384 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77783/Y | | B1->Y | R | OAI22xp5_ASAP7_75t_SL | 1 | 7.400 | 6.000 | 59.936 | + | cpu/stage1/regfile/n_1357 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77433/Y | | B->Y | F | NOR2x1_ASAP7_75t_SL | 1 | 8.000 | 4.300 | 64.236 | + | cpu/stage1/regfile/n_1707 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76866__1666/Y | | A->Y | R | NAND4xp75_ASAP7_75t_SL | 1 | 6.000 | 7.300 | 71.536 | + | cpu/stage1/rs1_mux_data[13] | | | R | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g563__7098/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 2 | 11.000 | 11.800 | 83.336 | + | cpu/stage1_rs1[13] | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/g1258__4319/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 2 | 7.600 | 9.700 | 93.036 | + | cpu/stage1/pcadder/n_44 | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NAND2x1p5_ASAP7_75t_SL | 2 | 5.600 | 3.300 | 96.336 | + | 33_g1478__6161/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_67 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 5.600 | 5.800 | 102.136 | + | 33_g1372__7482/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_133 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 1 | 8.400 | 6.800 | 108.936 | + | 33_g1267__7410/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[13] | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g937__1705/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 5.000 | 7.300 | 116.236 | + | cpu/stage1/stage1_pc_mux_to_pc[13] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g354__2802/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.000 | 3.800 | 120.036 | + | cpu/stage1/pcreg/n_26 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[13]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.600 | 0.000 | 120.036 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 22.700 | 10.736 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[13]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 38.100 | 6.800 | 10.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 30: MET (1.354 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[20][15]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[15]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[20][15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 110.300 (P) 71.000 (P) + Arrival:= 26.436 -12.864 + + Hold:+ 11.646 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 138.082 + Launch Clock:= -12.864 + Data Path:+ 152.300 + Slack:= 1.354 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 19.700 | -12.864 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[15]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 37.800 | 21.400 | 8.536 | + | cpu/stage3_alu[15] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1121/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.800 | 8.000 | 16.536 | + | cpu/stage3/wbselmux/n_40 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1090/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 5.000 | 9.300 | 25.836 | + | cpu/wb_data[15] | | | R | (net) | 3 | | | | + | cpu/FE_PHC4040_wb_data_15/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 8.300 | 23.100 | 48.936 | + | cpu/FE_PHN4040_wb_data_15 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3529_wb_data_15/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 17.700 | 21.900 | 70.836 | + | cpu/stage1/FE_PHN3529_wb_data_15 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3904_wb_data_15/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 10.600 | 26.800 | 97.636 | + | cpu/stage1/FE_PHN3904_wb_data_15 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC858_wb_data_15/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 6 | 10.100 | 17.800 | 115.436 | + | cpu/stage1/FE_OFN989_wb_data_15 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g81275/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 8 | 26.000 | 24.000 | 139.436 | + | cpu/stage1/regfile/n_123 | | | F | (net) | 8 | | | | + | cpu/stage1/regfile/mem_reg[20][15]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 8 | 47.200 | 1.100 | 139.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 30.300 | -19.164 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.600 | 12.600 | -6.564 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_56 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00036/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 16.900 | 33.000 | 26.436 | + | cpu/stage1/regfile/CTS_57 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[20][15]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 48.500 | 18.700 | 26.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 31: MET (1.356 ps) Hold Check with Pin cpu/s2_to_s3_pc/register_reg[20]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_pc/register_reg[20]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/register_reg[20]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 83.600 (P) 73.600 (P) + Arrival:= -0.264 -10.264 + + Hold:+ 8.144 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 107.880 + Launch Clock:= -10.264 + Data Path:+ 119.500 + Slack:= 1.356 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.100 | -32.164 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.200 | 21.900 | -10.264 | + | NST/GCLK | | | | | | | | | + | cpu/s1_to_s2_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_pc/register_reg[20]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 33.700 | 21.800 | 11.536 | + | cpu/s1_to_s2_pc/FE_RN_4 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_pc/FE_PHC2616_stage2_pc_20/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.900 | 33.100 | 44.636 | + | cpu/stage2_pc[20] | | | R | (net) | 2 | | | | + | cpu/s2_to_s3_pc/FE_PHC3334_stage2_pc_20/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 20.100 | 32.400 | 77.036 | + | cpu/s2_to_s3_pc/FE_PHN3334_stage2_pc_20 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/FE_PHC3600_stage2_pc_20/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 14.600 | 27.800 | 104.836 | + | cpu/s2_to_s3_pc/FE_PHN3600_stage2_pc_20 | | | R | (net) | 1 | | | | + | cpu/s2_to_s3_pc/g441__7098/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 10.100 | 4.400 | 109.236 | + | cpu/s2_to_s3_pc/n_10 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_pc/register_reg[20]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 8.000 | 0.000 | 109.236 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 28.000 | -26.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 25.100 | 26.300 | -0.264 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[20]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 42.800 | 8.300 | -0.264 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 32: MET (1.403 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[19]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[14][19]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 94.500 (P) 77.700 (P) + Arrival:= 10.636 -6.164 + + Hold:+ 7.797 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 118.433 + Launch Clock:= -6.164 + Data Path:+ 126.000 + Slack:= 1.403 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 15.600 | -58.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | CTS_ccl_a_buf_00117/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 6 | 7.400 | 25.500 | -33.064 | + | CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 33.400 | 10.400 | -22.664 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_42 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00054/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 12.100 | 16.500 | -6.164 | + | cpu/stage1/regfile/CTS_43 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[14][19]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 23.600 | 21.100 | 14.936 | + | cpu/stage1/regfile/mem[14][19] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2364_mem_14_19/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.800 | 30.700 | 45.636 | + | cpu/stage1/regfile/FE_PHN2364_mem_14_19 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77903/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 16.400 | 8.100 | 53.736 | + | cpu/stage1/regfile/n_1236 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76986__8428/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 4.700 | 4.700 | 58.436 | + | cpu/stage1/regfile/n_2123 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76881__5122/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 1 | 7.600 | 5.900 | 64.336 | + | cpu/stage1/rs1_mux_data[19] | | | R | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g574__1666/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 6.000 | 9.000 | 73.336 | + | cpu/stage1_rs1[19] | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/g1265__1705/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 7.700 | 7.800 | 81.136 | + | cpu/stage1/pcadder/n_50 | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NAND2xp5_ASAP7_75t_L | 2 | 5.300 | 6.100 | 87.236 | + | 33_g1428__6161/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_104 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 10.300 | 5.300 | 92.536 | + | 33_g1376__9945/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_130 | | | | | | | | | + | cpu/stage1/pcadder/FE_PHC4112_add_18_35_Y_add_17_3 | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 5.100 | 8.700 | 101.236 | + | 4_Y_add_16_33_n_130/Y | | | | | | | | | + | cpu/stage1/pcadder/FE_PHN4112_add_18_35_Y_add_17_3 | | | R | (net) | 1 | | | | + | 4_Y_add_16_33_n_130 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 1 | 8.600 | 7.400 | 108.636 | + | 33_g1246__1617/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[19] | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g947__9315/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 6.000 | 7.400 | 116.036 | + | cpu/stage1/stage1_pc_mux_to_pc[19] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g360__1881/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.100 | 3.800 | 119.836 | + | cpu/stage1/pcreg/n_20 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[19]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.600 | 0.000 | 119.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 22.600 | 10.636 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 36.400 | 6.700 | 10.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 33: MET (1.407 ps) Hold Check with Pin cpu/s1_to_s2_inst/register_reg[11]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/register_reg[11]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 85.000 (P) 77.900 (P) + Arrival:= 1.136 -5.964 + + Hold:+ 7.793 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 108.929 + Launch Clock:= -5.964 + Data Path:+ 116.300 + Slack:= 1.407 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 22.200 | -5.964 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.100 | 21.300 | 15.336 | + | cpu/stage2_inst[8] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2647_stage2_inst_8/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 3 | 8.100 | 29.900 | 45.236 | + | cpu/FE_PHN2647_stage2_inst_8 | | | R | (net) | 3 | | | | + | cpu/stage1/nopsel/g472__3680/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 25.600 | 3.900 | 49.136 | + | cpu/stage1/nopsel/n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g465__2398/Y | | C->Y | F | AND5x1_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 57.036 | + | cpu/stage1/nopsel/FE_PHN4110_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC4110_n_14/Y | | A->Y | F | HB1xp67_ASAP7_75t_L | 1 | 4.000 | 8.600 | 65.636 | + | cpu/stage1/nopsel/n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC2690_n_14/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 6.300 | 7.200 | 72.836 | + | cpu/stage1/nopsel/FE_PHN2690_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 4 | 3.800 | 11.200 | 84.036 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1417_NOPSignal/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 9.100 | 9.400 | 93.436 | + | cpu/stage1/nopselmux/FE_OFN971_FE_DBTN75_NOPSignal | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_OFC843_FE_DBTN75_NOPSignal | | A->Y | R | INVx3_ASAP7_75t_SL | 14 | 5.800 | 5.300 | 98.736 | + | /Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OFN974_FE_DBTN75_NOPSignal | | | R | (net) | 14 | | | | + | cpu/stage1/nopselmux/g399__5477/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 10.200 | 8.000 | 106.736 | + | cpu/stage1_inst[11] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_inst/g385__9315/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.600 | 110.336 | + | cpu/s1_to_s2_inst/n_18 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_inst/register_reg[11]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.100 | 0.000 | 110.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 29.700 | -22.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 33.200 | 23.500 | 1.136 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[11]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.900 | 5.800 | 1.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 34: MET (1.428 ps) Hold Check with Pin cpu/s1_to_s2_inst/register_reg[31]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 86.000 (P) 77.900 (P) + Arrival:= 2.136 -5.964 + + Hold:+ 7.772 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.909 + Launch Clock:= -5.964 + Data Path:+ 117.300 + Slack:= 1.428 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 22.200 | -5.964 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.100 | 21.300 | 15.336 | + | cpu/stage2_inst[8] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2647_stage2_inst_8/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 3 | 8.100 | 29.900 | 45.236 | + | cpu/FE_PHN2647_stage2_inst_8 | | | R | (net) | 3 | | | | + | cpu/stage1/nopsel/g472__3680/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 25.600 | 3.900 | 49.136 | + | cpu/stage1/nopsel/n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g465__2398/Y | | C->Y | F | AND5x1_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 57.036 | + | cpu/stage1/nopsel/FE_PHN4110_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC4110_n_14/Y | | A->Y | F | HB1xp67_ASAP7_75t_L | 1 | 4.000 | 8.600 | 65.636 | + | cpu/stage1/nopsel/n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC2690_n_14/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 6.300 | 7.200 | 72.836 | + | cpu/stage1/nopsel/FE_PHN2690_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 4 | 3.800 | 11.200 | 84.036 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1417_NOPSignal/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 9.100 | 9.400 | 93.436 | + | cpu/stage1/nopselmux/FE_OFN971_FE_DBTN75_NOPSignal | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_OFC843_FE_DBTN75_NOPSignal | | A->Y | R | INVx3_ASAP7_75t_SL | 14 | 5.800 | 6.200 | 99.636 | + | /Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OFN974_FE_DBTN75_NOPSignal | | | R | (net) | 14 | | | | + | cpu/stage1/nopselmux/g401__5107/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 10.400 | 8.000 | 107.636 | + | cpu/stage1_inst[31] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_inst/g255__5526/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.700 | 111.336 | + | cpu/s1_to_s2_inst/n_33 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_inst/register_reg[31]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.400 | 0.000 | 111.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 29.700 | -22.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 33.200 | 24.500 | 2.136 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.900 | 6.800 | 2.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 35: MET (1.492 ps) Hold Check with Pin cpu/s2_to_s3_alu/register_reg[1]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_imm/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.900 (P) 73.400 (P) + Arrival:= -2.964 -10.464 + + Hold:+ 9.408 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 106.445 + Launch Clock:= -10.464 + Data Path:+ 118.400 + Slack:= 1.492 + Timing Path: + +----------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+-------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.700 | -31.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.300 | 21.100 | -10.464 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_imm/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_imm/register_reg[3]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 1 | 33.700 | 21.600 | 11.136 | + | cpu/stage2_imm[3] | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g588/Y | | A->Y | F | AND2x2_ASAP7_75t_SL | 1 | 9.700 | 9.500 | 20.636 | + | cpu/stage2/bselmux/n_1 | | | F | (net) | 1 | | | | + | cpu/stage2/bselmux/g553/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 6 | 4.800 | 11.700 | 32.336 | + | cpu/stage2/stage2_alu_in2[3] | | | F | (net) | 6 | | | | + | cpu/stage2/alu/FE_PHC4127_stage2_alu_in2_3/Y | | A->Y | F | BUFx4f_ASAP7_75t_SL | 9 | 11.800 | 10.700 | 43.036 | + | cpu/stage2/alu/FE_PHN4127_stage2_alu_in2_3 | | | F | (net) | 9 | | | | + | cpu/stage2/alu/srl_33_21_g1726/Y | | A2->Y | R | AOI222xp33_ASAP7_75t_SL | 2 | 9.500 | 8.700 | 51.736 | + | cpu/stage2/alu/srl_33_21_n_125 | | | R | (net) | 2 | | | | + | cpu/stage2/alu/srl_33_21_g1693/Y | | A2->Y | F | OAI21xp5_ASAP7_75t_SL | 1 | 16.000 | 5.200 | 56.936 | + | cpu/stage2/alu/n_197 | | | F | (net) | 1 | | | | + | cpu/stage2/alu/g5501/Y | | A1->Y | F | AO221x2_ASAP7_75t_SL | 6 | 7.300 | 16.000 | 72.936 | + | cpu/stage2_alu_out[1] | | | F | (net) | 6 | | | | + | cpu/FE_PHC2782_stage2_alu_out_1/Y | | A->Y | F | BUFx4_ASAP7_75t_SRAM | 3 | 13.800 | 24.600 | 97.536 | + | cpu/FE_PHN2782_stage2_alu_out_1 | | | F | (net) | 3 | | | | + | cpu/s2_to_s3_alu/g448__5477/Y | | B->Y | F | OR2x2_ASAP7_75t_SL | 1 | 16.200 | 10.400 | 107.936 | + | cpu/s2_to_s3_alu/n_3 | | | F | (net) | 1 | | | | + | cpu/s2_to_s3_alu/register_reg[1]/D | | D | F | DFFHQx4_ASAP7_75t_SL | 1 | 4.800 | 0.000 | 107.936 | + +----------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 26.700 | -27.864 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 24.800 | 24.900 | -2.964 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[1]/CLK | | CLK | R | DFFHQx4_ASAP7_75t_SL | 32 | 42.700 | 7.900 | -2.964 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 36: MET (1.492 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[20][28]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[28]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[20][28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 105.000 (P) 74.900 (P) + Arrival:= 21.136 -8.964 + + Hold:+ 11.808 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 132.944 + Launch Clock:= -8.964 + Data Path:+ 143.400 + Slack:= 1.492 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 23.600 | -8.964 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[28]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 41.300 | 23.100 | 14.136 | + | cpu/stage3_alu[28] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1126/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 10.000 | 10.900 | 25.036 | + | cpu/stage3/wbselmux/n_35 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1111/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 9.600 | 8.700 | 33.736 | + | cpu/wb_data[28] | | | R | (net) | 3 | | | | + | cpu/FE_PHC3921_wb_data_28/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 1 | 7.000 | 7.400 | 41.136 | + | cpu/FE_PHN3921_wb_data_28 | | | R | (net) | 1 | | | | + | cpu/FE_PHC3513_wb_data_28/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 1 | 5.500 | 27.600 | 68.736 | + | cpu/FE_PHN3513_wb_data_28 | | | R | (net) | 1 | | | | + | cpu/FE_PHC2710_wb_data_28/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 16.200 | 35.700 | 104.436 | + | cpu/FE_PHN2710_wb_data_28 | | | R | (net) | 3 | | | | + | cpu/stage1/regfile/FE_OFC890_wb_data_28/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 5 | 21.500 | 15.100 | 119.536 | + | cpu/stage1/regfile/FE_OFN1021_wb_data_28 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/g81631/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 5 | 18.300 | 14.900 | 134.436 | + | cpu/stage1/regfile/n_68 | | | F | (net) | 5 | | | | + | cpu/stage1/regfile/mem_reg[20][28]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 5 | 28.000 | 0.500 | 134.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 30.300 | -19.164 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.600 | 12.600 | -6.564 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_56 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00036/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 16.900 | 27.700 | 21.136 | + | cpu/stage1/regfile/CTS_57 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[20][28]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.200 | 13.400 | 21.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 37: MET (1.492 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[17]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[8][17]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[17]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 94.600 (P) 81.400 (P) + Arrival:= 10.736 -2.464 + + Hold:+ 7.808 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 118.544 + Launch Clock:= -2.464 + Data Path:+ 122.500 + Slack:= 1.492 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 21.100 | -31.164 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 21.700 | 7.000 | -24.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_23 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00072/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.100 | 21.700 | -2.464 | + | cpu/stage1/regfile/CTS_24 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[8][17]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_L | 1 | 16.900 | 23.200 | 20.736 | + | cpu/stage1/regfile/mem[8][17] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2194_mem_8_17/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.200 | 29.700 | 50.436 | + | cpu/stage1/regfile/FE_PHN2194_mem_8_17 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g79217/Y | | A->Y | F | INVx1_ASAP7_75t_SL | 1 | 15.000 | 3.100 | 53.536 | + | cpu/stage1/regfile/n_451 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77213/Y | | A1->Y | R | OAI21xp5_ASAP7_75t_SL | 1 | 6.400 | 4.900 | 58.436 | + | cpu/stage1/regfile/n_1911 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77080/Y | | B->Y | F | NOR2x1_ASAP7_75t_SL | 1 | 6.200 | 5.200 | 63.636 | + | cpu/stage1/regfile/n_2029 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76962__1617/Y | | C->Y | R | NAND4xp75_ASAP7_75t_SL | 1 | 7.300 | 7.100 | 70.736 | + | cpu/stage1/rs1_mux_data[17] | | | R | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g553__4319/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 8.700 | 8.600 | 79.336 | + | cpu/stage1_rs1[17] | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/g1252__7410/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 6.700 | 7.900 | 87.236 | + | cpu/stage1/pcadder/n_48 | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 2 | 5.700 | 6.500 | 93.736 | + | 33_g1484__7410/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 2 | | | | + | 33_n_58 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | NAND2xp5_ASAP7_75t_SL | 1 | 12.300 | 7.500 | 101.236 | + | 33_g1367__8246/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_138 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 1 | 9.900 | 7.000 | 108.236 | + | 33_g1266__1666/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[17] | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g954__5477/Y | | A2->Y | R | AO21x1_ASAP7_75t_L | 2 | 5.200 | 8.000 | 116.236 | + | cpu/stage1/stage1_pc_mux_to_pc[17] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g358__7098/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.100 | 3.800 | 120.036 | + | cpu/stage1/pcreg/n_22 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[17]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.000 | 120.036 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 22.700 | 10.736 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[17]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 36.400 | 6.800 | 10.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 38: MET (1.546 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[19]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[27][19]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 81.100 (P) 87.600 (P) + Arrival:= -2.764 3.736 + + Hold:+ 7.954 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 105.190 + Launch Clock:= 3.736 + Data Path:+ 103.000 + Slack:= 1.546 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 24.400 | -27.864 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 23.300 | 8.000 | -19.864 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00015/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 7.800 | 23.600 | 3.736 | + | cpu/stage1/regfile/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[27][19]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 20.100 | 20.600 | 24.336 | + | cpu/stage1/regfile/mem[27][19] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2392_mem_27_19/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.300 | 28.700 | 53.036 | + | cpu/stage1/regfile/FE_PHN2392_mem_27_19 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC3982_mem_27_19/Y | | A->Y | R | HB1xp67_ASAP7_75t_L | 1 | 13.400 | 9.200 | 62.236 | + | cpu/stage1/regfile/FE_PHN3982_mem_27_19 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77145/Y | | A2->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 5.600 | 7.800 | 70.036 | + | cpu/stage1/regfile/n_1964 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76922__1666/Y | | B->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 7.000 | 5.500 | 75.536 | + | cpu/stage1/regfile/n_2161 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76882__8246/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 1 | 6.700 | 6.100 | 81.636 | + | cpu/stage1/rs2_mux_data[19] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3934_rs2_mux_data_19/ | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 4.500 | 6.500 | 88.136 | + | Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_PHN3934_rs2_mux_data_19 | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g574__2346/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 4.000 | 8.500 | 96.636 | + | cpu/stage1_rs2[19] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3583_stage1_rs2_19/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 4.800 | 6.400 | 103.036 | + | cpu/s1_to_s2_rs2/FE_PHN3583_stage1_rs2_19 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g440__6131/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.700 | 106.736 | + | cpu/s1_to_s2_rs2/n_11 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[19]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.200 | 0.000 | 106.736 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.800 | -2.764 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[19]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.600 | 6.000 | -2.764 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 39: MET (1.652 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[0]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[11][0]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[0]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.800 (P) 83.800 (P) + Arrival:= -3.064 -0.064 + + Hold:+ 7.548 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.484 + Launch Clock:= -0.064 + Data Path:+ 106.200 + Slack:= 1.652 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 22.400 | -29.864 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 22.000 | 7.200 | -22.664 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_19 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00063/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.500 | 22.600 | -0.064 | + | cpu/stage1/regfile/CTS_20 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[11][0]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 17.700 | 20.800 | 20.736 | + | cpu/stage1/regfile/mem[11][0] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2046_mem_11_0/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 9.000 | 30.300 | 51.036 | + | cpu/stage1/regfile/FE_PHN2046_mem_11_0 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC2933_mem_11_0/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 15.800 | 20.900 | 71.936 | + | cpu/stage1/regfile/FE_PHN2933_mem_11_0 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77707/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 10.000 | 4.300 | 76.236 | + | cpu/stage1/regfile/n_1433 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77094/Y | | A->Y | F | AND5x1_ASAP7_75t_SL | 1 | 6.700 | 7.600 | 83.836 | + | cpu/stage1/regfile/n_2015 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76887__7482/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 4.800 | 5.900 | 89.736 | + | cpu/stage1/rs2_mux_data[0] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g557__6783/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 8.900 | 10.200 | 99.936 | + | cpu/stage1_rs2[0] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g449__2346/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 6.300 | 6.200 | 106.136 | + | cpu/s1_to_s2_rs2/n_2 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[0]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 9.400 | 0.000 | 106.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.500 | -3.064 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[0]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.500 | 5.700 | -3.064 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 40: MET (1.671 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[6][12]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[12]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[6][12]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 96.100 (P) 72.200 (P) + Arrival:= 12.236 -11.664 + + Hold:+ 7.529 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 119.765 + Launch Clock:= -11.664 + Data Path:+ 133.100 + Slack:= 1.671 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 20.900 | -11.664 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[12]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_L | 1 | 38.200 | 24.800 | 13.136 | + | cpu/stage3_alu[12] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1127/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.400 | 11.300 | 24.436 | + | cpu/stage3/wbselmux/n_34 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1094/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 10.500 | 9.100 | 33.536 | + | cpu/wb_data[12] | | | R | (net) | 3 | | | | + | cpu/FE_PHC2704_wb_data_12/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 2 | 6.800 | 32.000 | 65.536 | + | cpu/FE_PHN2704_wb_data_12 | | | R | (net) | 2 | | | | + | cpu/stage1/FE_PHC2870_wb_data_12/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 23.300 | 28.600 | 94.136 | + | cpu/stage1/FE_PHN2870_wb_data_12 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC868_wb_data_12/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 6 | 8.100 | 22.100 | 116.236 | + | cpu/stage1/FE_OFN999_wb_data_12 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g51152/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 35.700 | 5.200 | 121.436 | + | cpu/stage1/regfile/n_12 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/mem_reg[6][12]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 14.100 | 0.000 | 121.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 25.500 | -24.364 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 30.300 | 9.600 | -14.764 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_27 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00078/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 10.400 | 27.000 | 12.236 | + | cpu/stage1/regfile/CTS_28 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[6][12]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 25.100 | 9.100 | 12.236 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 41: MET (1.728 ps) Hold Check with Pin cpu/s1_to_s2_inst/register_reg[9]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 85.900 (P) 77.900 (P) + Arrival:= 2.036 -5.964 + + Hold:+ 7.772 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.809 + Launch Clock:= -5.964 + Data Path:+ 117.500 + Slack:= 1.728 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 22.200 | -5.964 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.100 | 21.300 | 15.336 | + | cpu/stage2_inst[8] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2647_stage2_inst_8/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 3 | 8.100 | 29.900 | 45.236 | + | cpu/FE_PHN2647_stage2_inst_8 | | | R | (net) | 3 | | | | + | cpu/stage1/nopsel/g472__3680/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 25.600 | 3.900 | 49.136 | + | cpu/stage1/nopsel/n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g465__2398/Y | | C->Y | F | AND5x1_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 57.036 | + | cpu/stage1/nopsel/FE_PHN4110_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC4110_n_14/Y | | A->Y | F | HB1xp67_ASAP7_75t_L | 1 | 4.000 | 8.600 | 65.636 | + | cpu/stage1/nopsel/n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC2690_n_14/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 6.300 | 7.200 | 72.836 | + | cpu/stage1/nopsel/FE_PHN2690_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 4 | 3.800 | 11.200 | 84.036 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1417_NOPSignal/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 9.100 | 9.400 | 93.436 | + | cpu/stage1/nopselmux/FE_OFN971_FE_DBTN75_NOPSignal | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_OFC843_FE_DBTN75_NOPSignal | | A->Y | R | INVx3_ASAP7_75t_SL | 14 | 5.800 | 6.300 | 99.736 | + | /Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OFN974_FE_DBTN75_NOPSignal | | | R | (net) | 14 | | | | + | cpu/stage1/nopselmux/g418__5115/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 10.400 | 8.100 | 107.836 | + | cpu/stage1_inst[9] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_inst/g382__7482/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.700 | 111.536 | + | cpu/s1_to_s2_inst/n_21 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_inst/register_reg[9]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.300 | 0.000 | 111.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 29.700 | -22.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 33.200 | 24.400 | 2.036 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[9]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.900 | 6.700 | 2.036 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 42: MET (1.786 ps) Hold Check with Pin cpu/s1_to_s2_inst/register_reg[8]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/register_reg[8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 85.700 (P) 77.900 (P) + Arrival:= 1.836 -5.964 + + Hold:+ 7.814 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.650 + Launch Clock:= -5.964 + Data Path:+ 117.400 + Slack:= 1.786 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 22.200 | -5.964 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.100 | 21.300 | 15.336 | + | cpu/stage2_inst[8] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2647_stage2_inst_8/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 3 | 8.100 | 29.900 | 45.236 | + | cpu/FE_PHN2647_stage2_inst_8 | | | R | (net) | 3 | | | | + | cpu/stage1/nopsel/g472__3680/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 25.600 | 3.900 | 49.136 | + | cpu/stage1/nopsel/n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g465__2398/Y | | C->Y | F | AND5x1_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 57.036 | + | cpu/stage1/nopsel/FE_PHN4110_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC4110_n_14/Y | | A->Y | F | HB1xp67_ASAP7_75t_L | 1 | 4.000 | 8.600 | 65.636 | + | cpu/stage1/nopsel/n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC2690_n_14/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 6.300 | 7.200 | 72.836 | + | cpu/stage1/nopsel/FE_PHN2690_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 4 | 3.800 | 11.200 | 84.036 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1417_NOPSignal/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 9.100 | 9.400 | 93.436 | + | cpu/stage1/nopselmux/FE_OFN971_FE_DBTN75_NOPSignal | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_OFC843_FE_DBTN75_NOPSignal | | A->Y | R | INVx3_ASAP7_75t_SL | 14 | 5.800 | 6.300 | 99.736 | + | /Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OFN974_FE_DBTN75_NOPSignal | | | R | (net) | 14 | | | | + | cpu/stage1/nopselmux/g407__6783/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 10.400 | 8.100 | 107.836 | + | cpu/stage1_inst[8] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_inst/g381__5115/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.600 | 111.436 | + | cpu/s1_to_s2_inst/n_22 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.000 | 0.000 | 111.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 29.700 | -22.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 33.200 | 24.200 | 1.836 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.900 | 6.500 | 1.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 43: MET (1.828 ps) Hold Check with Pin cpu/s1_to_s2_inst/register_reg[10]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/register_reg[10]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 85.800 (P) 77.900 (P) + Arrival:= 1.936 -5.964 + + Hold:+ 7.772 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 109.709 + Launch Clock:= -5.964 + Data Path:+ 117.500 + Slack:= 1.828 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 20.100 | -54.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 18.700 | 25.900 | -28.164 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 26.200 | 22.200 | -5.964 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[8]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 32.100 | 21.300 | 15.336 | + | cpu/stage2_inst[8] | | | R | (net) | 1 | | | | + | cpu/FE_PHC2647_stage2_inst_8/Y | | A->Y | R | HB3xp67_ASAP7_75t_R | 3 | 8.100 | 29.900 | 45.236 | + | cpu/FE_PHN2647_stage2_inst_8 | | | R | (net) | 3 | | | | + | cpu/stage1/nopsel/g472__3680/Y | | B->Y | F | XNOR2xp5_ASAP7_75t_SL | 1 | 25.600 | 3.900 | 49.136 | + | cpu/stage1/nopsel/n_7 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g465__2398/Y | | C->Y | F | AND5x1_ASAP7_75t_SL | 1 | 7.400 | 7.900 | 57.036 | + | cpu/stage1/nopsel/FE_PHN4110_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC4110_n_14/Y | | A->Y | F | HB1xp67_ASAP7_75t_L | 1 | 4.000 | 8.600 | 65.636 | + | cpu/stage1/nopsel/n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/FE_PHC2690_n_14/Y | | A->Y | F | BUFx3_ASAP7_75t_SL | 1 | 6.300 | 7.200 | 72.836 | + | cpu/stage1/nopsel/FE_PHN2690_n_14 | | | F | (net) | 1 | | | | + | cpu/stage1/nopsel/g464__5477/Y | | B->Y | F | OR2x6_ASAP7_75t_SL | 4 | 3.800 | 11.200 | 84.036 | + | cpu/stage1/NOPSignal | | | F | (net) | 4 | | | | + | cpu/stage1/nopselmux/FE_OCPC1417_NOPSignal/Y | | A->Y | F | BUFx2_ASAP7_75t_SL | 1 | 9.100 | 9.400 | 93.436 | + | cpu/stage1/nopselmux/FE_OFN971_FE_DBTN75_NOPSignal | | | F | (net) | 1 | | | | + | cpu/stage1/nopselmux/FE_OFC843_FE_DBTN75_NOPSignal | | A->Y | R | INVx3_ASAP7_75t_SL | 14 | 5.800 | 6.300 | 99.736 | + | /Y | | | | | | | | | + | cpu/stage1/nopselmux/FE_OFN974_FE_DBTN75_NOPSignal | | | R | (net) | 14 | | | | + | cpu/stage1/nopselmux/g386__6131/Y | | B->Y | R | AND2x2_ASAP7_75t_SL | 1 | 10.400 | 8.100 | 107.836 | + | cpu/stage1_inst[10] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_inst/g384__6161/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.700 | 111.536 | + | cpu/s1_to_s2_inst/n_19 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_inst/register_reg[10]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.400 | 0.000 | 111.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 29.700 | -22.364 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 33.200 | 24.300 | 1.936 | + | _INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_inst/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_inst/register_reg[10]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 35.900 | 6.600 | 1.936 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 44: MET (1.874 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[6][24]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[24]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[6][24]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 92.400 (P) 76.500 (P) + Arrival:= 8.536 -7.364 + + Hold:+ 7.226 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 115.762 + Launch Clock:= -7.364 + Data Path:+ 125.000 + Slack:= 1.874 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 25.200 | -7.364 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[24]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 41.500 | 23.300 | 15.936 | + | cpu/stage3_alu[24] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1122/Y | | B1->Y | R | AO22x2_ASAP7_75t_SL | 1 | 10.200 | 11.400 | 27.336 | + | cpu/stage3/wbselmux/n_39 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1115/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 9.200 | 9.100 | 36.436 | + | cpu/wb_data[24] | | | R | (net) | 3 | | | | + | cpu/FE_PHC2702_wb_data_24/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 2 | 7.000 | 32.100 | 68.536 | + | cpu/FE_PHN2702_wb_data_24 | | | R | (net) | 2 | | | | + | cpu/stage1/FE_PHC2873_wb_data_24/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 23.200 | 21.000 | 89.536 | + | cpu/stage1/FE_PHN2873_wb_data_24 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC872_wb_data_24/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 6 | 6.300 | 22.700 | 112.236 | + | cpu/stage1/FE_OFN1003_wb_data_24 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g51159/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 37.800 | 5.400 | 117.636 | + | cpu/stage1/regfile/n_5 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/mem_reg[6][24]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 14.700 | 0.000 | 117.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.400 | -49.864 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 21.800 | 25.500 | -24.364 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 30.300 | 9.600 | -14.764 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_27 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00078/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 10.400 | 23.300 | 8.536 | + | cpu/stage1/regfile/CTS_28 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[6][24]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 22.400 | 5.400 | 8.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 45: MET (1.894 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[1]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[24][1]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 80.500 (P) 82.600 (P) + Arrival:= -3.364 -1.264 + + Hold:+ 8.006 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 104.642 + Launch Clock:= -1.264 + Data Path:+ 107.800 + Slack:= 1.894 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 21.800 | -30.464 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 21.900 | 7.000 | -23.464 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_9 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00024/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.000 | 22.200 | -1.264 | + | cpu/stage1/regfile/CTS_10 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[24][1]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 18.600 | 20.700 | 19.436 | + | cpu/stage1/regfile/mem[24][1] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2099_mem_24_1/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.700 | 29.400 | 48.836 | + | cpu/stage1/regfile/FE_PHN2099_mem_24_1 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/FE_PHC3812_mem_24_1/Y | | A->Y | R | BUFx2_ASAP7_75t_L | 1 | 14.400 | 9.000 | 57.836 | + | cpu/stage1/regfile/FE_PHN3812_mem_24_1 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g78102/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 4.000 | 5.200 | 63.036 | + | cpu/stage1/regfile/n_1038 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77060/Y | | C->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 7.700 | 6.100 | 69.136 | + | cpu/stage1/regfile/n_2049 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76932__6783/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 1 | 6.400 | 13.700 | 82.836 | + | cpu/stage1/rs2_mux_data[1] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g556__5526/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 16.400 | 10.800 | 93.636 | + | cpu/stage1_rs2[1] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g448__2883/Y | | B->Y | F | NOR2xp33_ASAP7_75t_SL | 1 | 6.000 | 4.900 | 98.536 | + | cpu/s1_to_s2_rs2/n_3 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC3582_n_3/Y | | A->Y | F | HB1xp67_ASAP7_75t_SL | 1 | 7.100 | 8.000 | 106.536 | + | cpu/s1_to_s2_rs2/FE_PHN3582_n_3 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[1]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 5.600 | 0.000 | 106.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.200 | -3.364 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[1]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.400 | 5.400 | -3.364 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 46: MET (1.923 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[16]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/pcreg/register_reg[16]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[16]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 94.200 (P) 87.800 (P) + Arrival:= 10.336 3.936 + + Hold:+ 7.777 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 118.113 + Launch Clock:= 3.936 + Data Path:+ 116.100 + Slack:= 1.923 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 22.600 | -33.664 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 18.500 | 6.900 | -26.764 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 6.000 | 9.500 | -17.264 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 21.200 | 3.936 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[16]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 2 | 33.200 | 23.100 | 27.036 | + | cpu/stage1/FE_RN_14 | | | R | (net) | 2 | | | | + | cpu/stage1/FE_PHC3368_FE_RN_14/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 10.800 | 28.300 | 55.336 | + | cpu/stage1/FE_PHN3368_FE_RN_14 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC2555_stage1_pc_16/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 3 | 12.100 | 35.700 | 91.036 | + | cpu/stage1_pc[16] | | | R | (net) | 3 | | | | + | cpu/stage1/pcselmux/g963__1617/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 23.900 | 8.600 | 99.636 | + | cpu/stage1/pcselmux/n_41 | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g957__6260/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 2 | 5.400 | 6.500 | 106.136 | + | cpu/stage1/stage1_pc_mux_to_pc[16] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/FE_PHC2859_stage1_pc_mux_to_pc_16 | | A->Y | R | HB2xp67_ASAP7_75t_SL | 1 | 5.700 | 10.000 | 116.136 | + | /Y | | | | | | | | | + | cpu/stage1/pcreg/FE_PHN2859_stage1_pc_mux_to_pc_16 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/g356__5122/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.300 | 3.900 | 120.036 | + | cpu/stage1/pcreg/n_24 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[16]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.700 | 0.000 | 120.036 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 22.300 | 10.336 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[16]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 36.300 | 6.400 | 10.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 47: MET (1.968 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[5][15]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_alu/register_reg[15]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[5][15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 107.500 (P) 71.000 (P) + Arrival:= 23.636 -12.864 + + Hold:+ 11.232 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 134.868 + Launch Clock:= -12.864 + Data Path:+ 149.700 + Slack:= 1.968 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 23.700 | -32.564 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.100 | 19.700 | -12.864 | + | INST/GCLK | | | | | | | | | + | cpu/s2_to_s3_alu/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_alu/register_reg[15]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 37.800 | 21.400 | 8.536 | + | cpu/stage3_alu[15] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1121/Y | | B1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.800 | 8.000 | 16.536 | + | cpu/stage3/wbselmux/n_40 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1090/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 5.000 | 9.300 | 25.836 | + | cpu/wb_data[15] | | | R | (net) | 3 | | | | + | cpu/FE_PHC4040_wb_data_15/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 8.300 | 23.100 | 48.936 | + | cpu/FE_PHN4040_wb_data_15 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3529_wb_data_15/Y | | A->Y | R | HB2xp67_ASAP7_75t_SRAM | 1 | 17.700 | 21.900 | 70.836 | + | cpu/stage1/FE_PHN3529_wb_data_15 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3904_wb_data_15/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 1 | 10.600 | 26.800 | 97.636 | + | cpu/stage1/FE_PHN3904_wb_data_15 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OFC858_wb_data_15/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 6 | 10.100 | 17.800 | 115.436 | + | cpu/stage1/FE_OFN989_wb_data_15 | | | R | (net) | 6 | | | | + | cpu/stage1/regfile/g81088/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 7 | 26.000 | 21.400 | 136.836 | + | cpu/stage1/regfile/n_148 | | | F | (net) | 7 | | | | + | cpu/stage1/regfile/mem_reg[5][15]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 7 | 41.300 | 0.700 | 136.836 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 29.900 | -19.564 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 26.600 | 10.300 | -9.264 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_60 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00081/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 12.100 | 32.900 | 23.636 | + | cpu/stage1/regfile/CTS_61 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[5][15]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 46.200 | 18.700 | 23.636 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 48: MET (2.056 ps) Hold Check with Pin cpu/stage1/regfile/mem_reg[22][11]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_pc/register_reg[11]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/regfile/mem_reg[22][11]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 106.400 (P) 73.100 (P) + Arrival:= 22.536 -10.764 + + Hold:+ 11.544 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 134.080 + Launch Clock:= -10.764 + Data Path:+ 146.900 + Slack:= 2.056 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 17.900 | -56.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 16.800 | 24.600 | -31.664 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_I | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 19.300 | 20.900 | -10.764 | + | NST/GCLK | | | | | | | | | + | cpu/s2_to_s3_pc/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s2_to_s3_pc/register_reg[11]/QN | | CLK->QN | F | DFFHQNx1_ASAP7_75t_SL | 2 | 36.800 | 22.800 | 12.036 | + | cpu/stage3_pc[11] | | | F | (net) | 2 | | | | + | cpu/stage3/pcfour/add_9_31_g752/Y | | A->Y | R | XNOR2xp5_ASAP7_75t_SL | 1 | 11.400 | 7.000 | 19.036 | + | cpu/stage3/stage3_pc4[11] | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/FE_PHC2680_stage3_pc4_11/Y | | A->Y | R | HB3xp67_ASAP7_75t_SL | 1 | 5.800 | 14.700 | 33.736 | + | cpu/stage3/wbselmux/FE_PHN2680_stage3_pc4_11 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1129/Y | | A1->Y | R | AO22x1_ASAP7_75t_SL | 1 | 7.400 | 8.900 | 42.636 | + | cpu/stage3/wbselmux/n_32 | | | R | (net) | 1 | | | | + | cpu/stage3/wbselmux/g1097/Y | | B->Y | R | AO21x2_ASAP7_75t_SL | 3 | 4.900 | 9.400 | 52.036 | + | cpu/wb_data[11] | | | R | (net) | 3 | | | | + | cpu/stage1/FE_PHC3522_wb_data_11/Y | | A->Y | R | HB3xp67_ASAP7_75t_SRAM | 1 | 8.900 | 24.100 | 76.136 | + | cpu/stage1/FE_PHN3522_wb_data_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_PHC3910_wb_data_11/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 9.600 | 7.200 | 83.336 | + | cpu/stage1/FE_PHN3910_wb_data_11 | | | R | (net) | 1 | | | | + | cpu/stage1/FE_OCPC1453_wb_data_11/Y | | A->Y | R | HB1xp67_ASAP7_75t_SL | 7 | 4.000 | 30.400 | 113.736 | + | cpu/stage1/FE_OCPN1418_wb_data_11 | | | R | (net) | 7 | | | | + | cpu/stage1/regfile/g81797/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 6 | 56.400 | 22.400 | 136.136 | + | cpu/stage1/regfile/n_40 | | | F | (net) | 6 | | | | + | cpu/stage1/regfile/mem_reg[22][11]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 6 | 43.000 | 1.400 | 136.136 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 23.800 | -49.464 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00119/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 9 | 21.800 | 28.000 | -21.464 | + | cpu/stage1/regfile/CTS_65 | | | R | (net) | 9 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CG | | CLK->GCLK | R | ICGx2_ASAP7_75t_SL | 1 | 26.300 | 10.900 | -10.564 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_52 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00030/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 32 | 10.600 | 33.100 | 22.536 | + | cpu/stage1/regfile/CTS_53 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[22][11]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 49.800 | 19.500 | 22.536 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 49: MET (2.101 ps) Hold Check with Pin cpu/stage1/pcreg/register_reg[21]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[8][20]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 94.300 (P) 80.600 (P) + Arrival:= 10.436 -3.264 + + Hold:+ 7.799 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 118.235 + Launch Clock:= -3.264 + Data Path:+ 123.600 + Slack:= 2.101 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 21.100 | -31.164 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 21.700 | 7.000 | -24.164 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_23 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00072/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 6.100 | 20.900 | -3.264 | + | cpu/stage1/regfile/CTS_24 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[8][20]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 16.600 | 20.500 | 17.236 | + | cpu/stage1/regfile/mem[8][20] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC2282_mem_8_20/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.800 | 31.400 | 48.636 | + | cpu/stage1/regfile/FE_PHN2282_mem_8_20 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77613/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 17.500 | 8.500 | 57.136 | + | cpu/stage1/regfile/n_1523 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76865__2346/Y | | D->Y | R | NAND4xp75_ASAP7_75t_SL | 1 | 14.200 | 9.200 | 66.336 | + | cpu/stage1/rs1_mux_data[20] | | | R | (net) | 1 | | | | + | cpu/stage1/data1sel_s1/g571__9945/Y | | A2->Y | R | AO21x2_ASAP7_75t_SL | 2 | 8.300 | 10.400 | 76.736 | + | cpu/stage1_rs1[20] | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/g1280__7410/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 6.200 | 8.000 | 84.736 | + | cpu/stage1/pcadder/n_51 | | | R | (net) | 2 | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 3 | 6.000 | 8.900 | 93.636 | + | 33_g1439__6260/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | F | (net) | 3 | | | | + | 33_n_12 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | A->Y | R | NAND2xp5_ASAP7_75t_L | 1 | 17.000 | 8.500 | 102.136 | + | 33_g1261__9945/Y | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | | R | (net) | 1 | | | | + | 33_n_227 | | | | | | | | | + | cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_ | | B->Y | R | XNOR2xp5_ASAP7_75t_SL | 1 | 7.500 | 7.200 | 109.336 | + | 33_g1250__8246/Y | | | | | | | | | + | cpu/stage1/stage1_pc4[21] | | | R | (net) | 1 | | | | + | cpu/stage1/pcselmux/g940__7098/Y | | A2->Y | R | AO21x1_ASAP7_75t_SL | 2 | 5.300 | 7.200 | 116.536 | + | cpu/stage1/stage1_pc_mux_to_pc[21] | | | R | (net) | 2 | | | | + | cpu/stage1/pcreg/g347__6260/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 5.000 | 3.800 | 120.336 | + | cpu/stage1/pcreg/n_33 | | | F | (net) | 1 | | | | + | cpu/stage1/pcreg/register_reg[21]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.500 | 0.000 | 120.336 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 18.700 | -54.564 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00110/Y | | A->Y | R | BUFx5_ASAP7_75t_SRAM | 6 | 18.700 | 25.200 | -29.364 | + | cpu/CTS_1 | | | R | (net) | 6 | | | | + | cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_ | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 24.000 | 7.500 | -21.864 | + | INST/GCLK | | | | | | | | | + | cpu/stage1/pcreg/CTS_1 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/CTS_ccl_a_buf_00096/Y | | A->Y | R | BUFx6f_ASAP7_75t_SRAM | 1 | 7.000 | 9.900 | -11.964 | + | cpu/stage1/pcreg/FE_USKN4097_CTS_2 | | | R | (net) | 1 | | | | + | cpu/stage1/pcreg/FE_USKC4097_CTS_2/Y | | A->Y | R | BUFx4_ASAP7_75t_SL | 32 | 4.000 | 22.400 | 10.436 | + | cpu/stage1/pcreg/CTS_2 | | | R | (net) | 32 | | | | + | cpu/stage1/pcreg/register_reg[21]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 36.300 | 6.500 | 10.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ +Path 50: MET (2.158 ps) Hold Check with Pin cpu/s1_to_s2_rs2/register_reg[31]/CLK->D + View: PVT_0P77V_0C.hold_view + Group: reg2reg + Startpoint: (R) cpu/stage1/regfile/mem_reg[3][31]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 0.000 0.000 + Src Latency:+ -83.864 -83.864 + Net Latency:+ 81.200 (P) 85.900 (P) + Arrival:= -2.664 2.036 + + Hold:+ 7.942 + Uncertainty:+ 100.000 + Cppr Adjust:- 0.000 + Required Time:= 105.278 + Launch Clock:= 2.036 + Data Path:+ 105.400 + Slack:= 2.158 + Timing Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 9.700 | -74.164 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 22.700 | 21.900 | -52.264 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00108/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 16 | 19.400 | 23.900 | -28.364 | + | cpu/stage1/regfile/CTS_35 | | | R | (net) | 16 | | | | + | cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CG | | CLK->GCLK | R | ICGx1_ASAP7_75t_SL | 1 | 23.200 | 7.500 | -20.864 | + | IC_INST/GCLK | | | | | | | | | + | cpu/stage1/regfile/CTS_29 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/CTS_ccl_a_buf_00087/Y | | A->Y | R | BUFx10_ASAP7_75t_SRAM | 32 | 7.100 | 22.900 | 2.036 | + | cpu/stage1/regfile/CTS_30 | | | R | (net) | 32 | | | | + | cpu/stage1/regfile/mem_reg[3][31]/QN | | CLK->QN | R | DFFHQNx1_ASAP7_75t_SL | 1 | 18.600 | 20.400 | 22.436 | + | cpu/stage1/regfile/mem[3][31] | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/FE_PHC3107_mem_3_31/Y | | A->Y | R | HB4xp67_ASAP7_75t_R | 2 | 8.400 | 31.500 | 53.936 | + | cpu/stage1/regfile/FE_PHN3107_mem_3_31 | | | R | (net) | 2 | | | | + | cpu/stage1/regfile/g77734/Y | | A1->Y | F | AOI22xp5_ASAP7_75t_SL | 1 | 17.900 | 5.300 | 59.236 | + | cpu/stage1/regfile/n_1406 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g77155/Y | | C->Y | R | NAND3xp33_ASAP7_75t_SL | 1 | 9.700 | 6.000 | 65.236 | + | cpu/stage1/regfile/n_1954 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g77082/Y | | C->Y | F | AOI221xp5_ASAP7_75t_SL | 1 | 6.300 | 4.700 | 69.936 | + | cpu/stage1/regfile/n_2027 | | | F | (net) | 1 | | | | + | cpu/stage1/regfile/g76997__1881/Y | | A->Y | R | NAND5xp2_ASAP7_75t_SL | 1 | 7.100 | 5.700 | 75.636 | + | cpu/stage1/regfile/n_2112 | | | R | (net) | 1 | | | | + | cpu/stage1/regfile/g76939__7098/Y | | B->Y | R | AO21x1_ASAP7_75t_SL | 1 | 8.100 | 6.600 | 82.236 | + | cpu/stage1/rs2_mux_data[31] | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/FE_PHC3943_rs2_mux_data_31/ | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 5.100 | 6.400 | 88.636 | + | Y | | | | | | | | | + | cpu/stage1/data2sel_s1/FE_PHN3943_rs2_mux_data_31 | | | R | (net) | 1 | | | | + | cpu/stage1/data2sel_s1/g560__2802/Y | | A2->Y | R | AO22x1_ASAP7_75t_SL | 1 | 4.000 | 8.700 | 97.336 | + | cpu/stage1_rs2[31] | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/FE_PHC2793_stage1_rs2_31/Y | | A->Y | R | BUFx2_ASAP7_75t_SL | 1 | 5.200 | 6.400 | 103.736 | + | cpu/s1_to_s2_rs2/FE_PHN2793_stage1_rs2_31 | | | R | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/g420__2883/Y | | B->Y | F | NAND2xp5_ASAP7_75t_SL | 1 | 4.000 | 3.700 | 107.436 | + | cpu/s1_to_s2_rs2/n_31 | | | F | (net) | 1 | | | | + | cpu/s1_to_s2_rs2/register_reg[31]/D | | D | F | DFFHQNx1_ASAP7_75t_SL | 1 | 6.300 | 0.000 | 107.436 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + Other End Path: + +---------------------------------------------------------------------------------------------------------------------------------------------+ + | Timing Point | Flags | Arc | Edge | Cell | Fanout | Trans | Delay | Arrival | + | | | | | | | (ps) | (ps) | (ps) | + |----------------------------------------------------+-------+-----------+------+------------------------+--------+--------+--------+---------| + | clk | | clk | R | (arrival) | 2 | 4.100 | 10.600 | -73.264 | + | clk | | | R | (net) | 2 | | | | + | CTS_ccl_a_buf_00122/Y | | A->Y | R | BUFx12f_ASAP7_75t_SRAM | 5 | 25.000 | 21.200 | -52.064 | + | CTS_3 | | | R | (net) | 5 | | | | + | cpu/CTS_ccl_a_buf_00112/Y | | A->Y | R | BUFx3_ASAP7_75t_SRAM | 4 | 20.900 | 24.500 | -27.564 | + | cpu/CTS_2 | | | R | (net) | 4 | | | | + | cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_ | | CLK->GCLK | R | ICGx3_ASAP7_75t_SL | 32 | 30.500 | 24.900 | -2.664 | + | INST/GCLK | | | | | | | | | + | cpu/s1_to_s2_rs2/CLKGATE_rc_gclk | | | R | (net) | 32 | | | | + | cpu/s1_to_s2_rs2/register_reg[31]/CLK | | CLK | R | DFFHQNx1_ASAP7_75t_SL | 32 | 37.600 | 6.100 | -2.664 | + +---------------------------------------------------------------------------------------------------------------------------------------------+ + diff --git a/build/par-rundir/timingReports/riscv_top_preCTS.cap b/build/par-rundir/timingReports/riscv_top_preCTS.cap new file mode 100644 index 0000000..28d2aea --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_preCTS.cap @@ -0,0 +1,26 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 21:52:30 2020 +# Design: riscv_top +# Command: place_opt_design +############################################################### +# Net / InstPin MaxCap Cap CapSlack CellPort Remark +# +mem_req_addr[8] + mem/arbiter/g530/Y 0.092 1.001 -0.909 AO22x2_ASAP7_75t_SL/Y R +mem_req_addr[6] + mem/arbiter/g533/Y 0.092 1.001 -0.909 AO22x2_ASAP7_75t_SL/Y R +mem_req_data_bits[126] + mem/dcache/g13794/Y 0.092 1.000 -0.908 NOR2x2_ASAP7_75t_SL/Y R +mem_req_data_bits[92] + mem/dcache/g13874/Y 0.092 1.000 -0.908 NOR2x2_ASAP7_75t_SL/Y R +mem_req_data_bits[83] + mem/dcache/g13887/Y 0.092 1.000 -0.908 NOR2x2_ASAP7_75t_SL/Y R +mem_req_addr[27] + FE_OFC1457_mem_req_addr_27/Y 0.737 1.003 -0.266 BUFx12_ASAP7_75t_SL/Y R +mem_req_addr[2] + FE_OFC1683_mem_req_addr_2/Y 0.737 1.001 -0.263 BUFx12_ASAP7_75t_SL/Y R + +*info: there are 7 max_cap violations in the design. +*info: 7 violations are real (remark R). diff --git a/build/par-rundir/timingReports/riscv_top_preCTS.fanout b/build/par-rundir/timingReports/riscv_top_preCTS.fanout new file mode 100644 index 0000000..ab9c049 --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_preCTS.fanout @@ -0,0 +1,11 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 21:52:29 2020 +# Design: riscv_top +# Command: place_opt_design +############################################################### +# Net / InstPin MaxFanLoad FanLoad FanLoadSlk CellPort Remark +# + +*info: there is 0 max fanout load violation in the design. diff --git a/build/par-rundir/timingReports/riscv_top_preCTS.length b/build/par-rundir/timingReports/riscv_top_preCTS.length new file mode 100644 index 0000000..20208c5 --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_preCTS.length @@ -0,0 +1,7 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 21:52:30 2020 +# Design: riscv_top +# Command: place_opt_design +############################################################### diff --git a/build/par-rundir/timingReports/riscv_top_preCTS.summary b/build/par-rundir/timingReports/riscv_top_preCTS.summary new file mode 100644 index 0000000..2d17fdc --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_preCTS.summary @@ -0,0 +1,35 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 21:52:29 2020 +# Design: riscv_top +# Command: place_opt_design +############################################################### + +------------------------------------------------------------ + opt_design Final Summary +------------------------------------------------------------ + ++--------------------+---------+---------+---------+---------+ +| Setup mode | all | reg2reg |reg2cgate| default | ++--------------------+---------+---------+---------+---------+ +| WNS (ns):| -0.001 | -0.001 | 0.050 | 0.208 | +| TNS (ns):| -0.001 | -0.001 | 0.000 | 0.000 | +| Violating Paths:| 1 | 1 | 0 | 0 | +| All Paths:| 1344 | 1269 | 43 | 1344 | ++--------------------+---------+---------+---------+---------+ + ++----------------+-------------------------------+------------------+ +| | Real | Total | +| DRVs +------------------+------------+------------------| +| | Nr nets(terms) | Worst Vio | Nr nets(terms) | ++----------------+------------------+------------+------------------+ +| max_cap | 7 (7) | -0.909 | 7 (7) | +| max_tran | 8 (8) | -4.881 | 31 (31) | +| max_fanout | 0 (0) | 0 | 0 (0) | +| max_length | 0 (0) | 0 | 0 (0) | ++----------------+------------------+------------+------------------+ + +Density: 19.288% +Routing Overflow: 0.01% H and 0.24% V +------------------------------------------------------------ diff --git a/build/par-rundir/timingReports/riscv_top_preCTS.tran b/build/par-rundir/timingReports/riscv_top_preCTS.tran new file mode 100644 index 0000000..dba995e --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_preCTS.tran @@ -0,0 +1,76 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 21:52:29 2020 +# Design: riscv_top +# Command: place_opt_design +############################################################### +# Net / InstPin MaxTranTime TranTime TranSlack CellPort Remark +# +mem_req_addr[8] + mem/arbiter/g530/Y 1.000r/1.000f 5.881r/4.303f -4.881r/-3.303f AO22x2_ASAP7_75t_SL/Y R +mem_req_addr[6] + mem/arbiter/g533/Y 1.000r/1.000f 5.840r/4.269f -4.840r/-3.269f AO22x2_ASAP7_75t_SL/Y R +mem_req_data_bits[126] + mem/dcache/g13794/Y 1.000r/1.000f 4.970r/3.826f -3.970r/-2.826f NOR2x2_ASAP7_75t_SL/Y R +mem_req_data_bits[92] + mem/dcache/g13874/Y 1.000r/1.000f 4.967r/3.822f -3.967r/-2.822f NOR2x2_ASAP7_75t_SL/Y R +mem_req_data_bits[83] + mem/dcache/g13887/Y 1.000r/1.000f 4.846r/3.722f -3.847r/-2.722f NOR2x2_ASAP7_75t_SL/Y R +mem_req_addr[2] + FE_OFC1683_mem_req_addr_2/Y 1.000r/1.000f 1.105r/0.819f -0.105r/0.181f BUFx12_ASAP7_75t_SL/Y R +mem/icache/FE_OFN639_n + mem/icache/data_sram/A[4] 0.008r/0.008f 0.029r/0.028f -0.021r/-0.020f SRAM1RW64x128/A[4] R +mem/icache/FE_OFN636_n + mem/icache/data_sram/A[2] 0.008r/0.008f 0.029r/0.028f -0.021r/-0.020f SRAM1RW64x128/A[2] R +mem/icache/FE_OFN1270_FE_OFN340_n_370 + mem/icache/data_sram/I[122] 0.008r/0.008f 0.010r/0.010f -0.002r/-0.002f SRAM1RW64x128/I[122] B +mem/dcache/FE_OFN1287_FE_OFN202_n_627 + mem/dcache/data_sram/I[123] 0.008r/0.008f 0.010r/0.010f -0.002r/-0.002f SRAM1RW64x128/I[123] B +mem/dcache/FE_OFN1291_FE_OFN192_n_593 + mem/dcache/data_sram/I[89] 0.008r/0.008f 0.010r/0.010f -0.002r/-0.002f SRAM1RW64x128/I[89] B +mem/dcache/FE_OFN1283_FE_OFN363_n_622 + mem/dcache/data_sram/I[118] 0.008r/0.008f 0.010r/0.010f -0.002r/-0.002f SRAM1RW64x128/I[118] B +mem/icache/FE_OFN1285_FE_OFN337_n_367 + mem/icache/data_sram/I[119] 0.008r/0.008f 0.010r/0.009f -0.002r/-0.002f SRAM1RW64x128/I[119] B +mem/dcache/FE_OFN1289_FE_OFN199_n_624 + mem/dcache/data_sram/I[120] 0.008r/0.008f 0.010r/0.009f -0.002r/-0.002f SRAM1RW64x128/I[120] B +mem/dcache/FE_OFN1297_FE_OFN203_n_628 + mem/dcache/data_sram/I[124] 0.008r/0.008f 0.010r/0.009f -0.002r/-0.002f SRAM1RW64x128/I[124] B +mem/dcache/FE_OFN1306_FE_OFN197_n_598 + mem/dcache/data_sram/I[94] 0.008r/0.008f 0.010r/0.009f -0.002r/-0.002f SRAM1RW64x128/I[94] B +mem/dcache/FE_OFN1340_n + mem/dcache/data_sram/I[60] 0.008r/0.008f 0.010r/0.009f -0.002r/-0.002f SRAM1RW64x128/I[60] B +mem/dcache/FE_OFN1304_FE_OFN204_n_629 + mem/dcache/data_sram/I[125] 0.008r/0.008f 0.010r/0.009f -0.002r/-0.001f SRAM1RW64x128/I[125] B +mem/icache/FE_OFN1312_FE_OFN300_n_330 + mem/icache/data_sram/I[82] 0.008r/0.008f 0.010r/0.009f -0.002r/-0.001f SRAM1RW64x128/I[82] B +mem/icache/FE_OFN1314_FE_OFN293_n_323 + mem/icache/data_sram/I[75] 0.008r/0.008f 0.010r/0.009f -0.002r/-0.001f SRAM1RW64x128/I[75] B +mem/dcache/FE_OFN1327_FE_OFN179_n_580 + mem/dcache/data_sram/I[76] 0.008r/0.008f 0.010r/0.009f -0.002r/-0.001f SRAM1RW64x128/I[76] B +mem/dcache/FE_OFN1329_FE_OFN128_n_529 + mem/dcache/data_sram/I[25] 0.008r/0.008f 0.010r/0.009f -0.002r/-0.001f SRAM1RW64x128/I[25] B +mem/dcache/FE_OFN1331_FE_OFN127_n_528 + mem/dcache/data_sram/I[24] 0.008r/0.008f 0.010r/0.009f -0.002r/-0.001f SRAM1RW64x128/I[24] B +mem/icache/FE_OFN641_n + mem/icache/tag_valid_sram/A1[3] 0.008r/0.008f 0.009r/0.008f -0.001r/-0.000f SRAM2RW16x32/A1[3] B +mem/dcache/FE_OFN1249_FE_OFN39_original_addr_4 + mem/dcache/data_sram/A[2] 0.008r/0.008f 0.009r/0.008f -0.001r/0.000f SRAM1RW64x128/A[2] B +mem/dcache/FE_OFN30_original_addr_7 + mem/dcache/data_sram/A[5] 0.008r/0.008f 0.009r/0.008f -0.001r/0.000f SRAM1RW64x128/A[5] B +mem/dcache/FE_OFN1251_FE_OFN33_original_addr_6 + mem/dcache/data_sram/A[4] 0.008r/0.008f 0.008r/0.008f -0.000r/0.001f SRAM1RW64x128/A[4] B +mem/icache/FE_OFN1242_FE_OFN82_original_addr_5 + mem/icache/tag_valid_sram/A1[1] 0.008r/0.008f 0.008r/0.008f -0.000r/0.001f SRAM2RW16x32/A1[1] B +mem/icache/FE_OFN1335_n + mem/icache/data_sram/A[3] 0.008r/0.008f 0.008r/0.008f -0.000r/0.001f SRAM1RW64x128/A[3] B +mem/dcache/FE_OFN1337_n + mem/dcache/tag_valid_sram/A1[2] 0.008r/0.008f 0.008r/0.007f -0.000r/0.001f SRAM2RW16x32/A1[2] B +mem/dcache/FE_OFN1336_n + mem/dcache/tag_valid_sram/A1[0] 0.008r/0.008f 0.008r/0.007f -0.000r/0.001f SRAM2RW16x32/A1[0] B + +*info: there are 31 max_tran violations in the design. +*info: 8 violations are real (remark R). +*info: 23 violations may not be fixable: +*info: 23 violations on big pin capacitance net (remark B). diff --git a/build/par-rundir/timingReports/riscv_top_preCTS_all.tarpt b/build/par-rundir/timingReports/riscv_top_preCTS_all.tarpt new file mode 100644 index 0000000..6ea21bd --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_preCTS_all.tarpt @@ -0,0 +1,6376 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 21:52:30 2020 +# Design: riscv_top +# Command: place_opt_design +############################################################### +Path 1: VIOLATED (-0.710 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 5.910 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 794.090 + Launch Clock:= 0.000 + Data Path:+ 794.800 + Slack:= -0.710 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.400 394.400 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g390__4733/Y - B->Y R AND2x4_ASAP7_75t_SL 8 14.300 24.200 418.600 + cpu/stage1_inst[16] - - R (net) 8 - - - + cpu/stage1/regfile/FE_OFC1126_stage1_inst_16/Y - A->Y F INVx1_ASAP7_75t_SL 3 30.500 15.700 434.300 + cpu/stage1/regfile/FE_OFN902_stage1_inst_16 - - F (net) 3 - - - + cpu/stage1/regfile/g80403/Y - B->Y F AND2x4_ASAP7_75t_SL 11 24.400 24.800 459.100 + cpu/stage1/regfile/n_235 - - F (net) 11 - - - + cpu/stage1/regfile/g79836/Y - B->Y F AND2x2_ASAP7_75t_SL 6 24.900 26.600 485.700 + cpu/stage1/regfile/n_315 - - F (net) 6 - - - + cpu/stage1/regfile/g78500/Y - A->Y R NAND2xp5_ASAP7_75t_SL 1 29.200 12.100 497.800 + cpu/stage1/regfile/n_666 - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC608_n_666/Y - A->Y F INVx1_ASAP7_75t_SL 3 19.900 13.900 511.700 + cpu/stage1/regfile/n_665 - - F (net) 3 - - - + cpu/stage1/regfile/FE_OFC610_n_666/Y - A->Y R INVx1_ASAP7_75t_SL 4 21.100 17.100 528.800 + cpu/stage1/regfile/FE_OFN813_n_666 - - R (net) 4 - - - + cpu/stage1/regfile/g77382/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 28.600 9.800 538.600 + cpu/stage1/regfile/n_1758 - - F (net) 1 - - - + cpu/stage1/regfile/g77028/Y - A->Y R NOR3xp33_ASAP7_75t_SL 1 17.200 20.000 558.600 + cpu/stage1/regfile/n_2081 - - R (net) 1 - - - + cpu/stage1/regfile/g76863__9945/Y - B->Y F NAND4xp75_ASAP7_75t_SL 1 40.900 19.900 578.500 + cpu/stage1/rs1_mux_data[21] - - F (net) 1 - - - + cpu/stage1/data1sel_s1/g569__6161/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 36.400 25.200 603.700 + cpu/stage1_rs1[21] - - F (net) 2 - - - + cpu/stage1/pcadder/g1279__1666/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 21.300 17.900 621.600 + cpu/stage1/pcadder/n_52 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1425__5115/Y - B->Y R NAND2xp5_ASAP7_75t_SL 2 19.900 13.200 634.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_107 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1347__1666/Y - B->Y F OAI21xp5_ASAP7_75t_SL 2 21.200 11.600 646.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_160 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1319__5107/Y - A2->Y R A2O1A1O1Ixp25_ASAP7_75t_SL 1 21.600 15.800 662.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_185 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1304__9315/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 28.400 11.500 673.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_197 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - B->Y R AOI21x1_ASAP7_75t_SL 3 20.200 16.500 690.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 29.000 8.000 698.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_20 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1257__7482/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 12.800 17.900 716.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_231 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1244__6783/Y - A1->Y R AOI21x1_ASAP7_75t_SL 2 11.600 11.000 727.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_243 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1236__5477/Y - A1->Y F OAI21x1_ASAP7_75t_SL 1 25.100 8.100 735.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_251 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1235__6417/Y - B->Y F XOR2x1_ASAP7_75t_SL 1 20.700 17.700 752.900 + cpu/stage1/stage1_pc4[31] - - F (net) 1 - - - + cpu/stage1/pcselmux/g988__5526/Y - A2->Y F AO21x1_ASAP7_75t_SL 1 18.700 15.400 768.300 + cpu/stage1/pcselmux/n_16 - - F (net) 1 - - - + cpu/stage1/pcselmux/g961__6783/Y - B->Y F AO21x1_ASAP7_75t_SL 2 14.200 16.800 785.100 + cpu/stage1/stage1_pc_mux_to_pc[31] - - F (net) 2 - - - + cpu/stage1/pcreg/g362__7482/Y - B->Y R NAND2xp5_ASAP7_75t_L 1 14.700 9.700 794.800 + cpu/stage1/pcreg/n_18 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[31]/D - D R DFFHQNx1_ASAP7_75t_SL 1 43.900 0.000 794.800 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[31]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 2: MET (0.518 ps) Setup Check with Pin mem/dcache/STATE_reg[1]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) mem/dcache/STATE_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 5.282 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 794.718 + Launch Clock:= 0.000 + Data Path:+ 794.200 + Slack:= 0.518 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2318/Y - B1->Y F OAI221xp5_ASAP7_75t_SL 1 33.100 15.600 168.300 + cpu/stage3/wb_dmem[0] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1103/Y - A1->Y F AO21x1_ASAP7_75t_SL 3 28.600 22.400 190.700 + cpu/wb_data[0] - - F (net) 3 - - - + cpu/stage2/rs2DataSel/g563/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 17.700 29.600 220.300 + cpu/stage2/stage2_rs2_data[0] - - F (net) 8 - - - + cpu/stage2/bselmux/g583/Y - A->Y R NAND2xp5_ASAP7_75t_SL 1 31.200 12.400 232.700 + cpu/stage2/bselmux/n_6 - - R (net) 1 - - - + cpu/stage2/bselmux/g559/Y - A->Y R AND2x2_ASAP7_75t_SL 2 23.400 23.000 255.700 + cpu/stage2/stage2_alu_in2[0] - - R (net) 2 - - - + cpu/stage2/alu/FE_OFC692_n_30/Y - A->Y F INVx3_ASAP7_75t_SL 24 23.300 22.500 278.200 + cpu/stage2/alu/FE_OFN867_n_30 - - F (net) 24 - - - + cpu/stage2/alu/FE_OFC696_n_30/Y - A->Y R INVx1_ASAP7_75t_SL 14 39.300 38.900 317.100 + cpu/stage2/alu/FE_OFN871_n_30 - - R (net) 14 - - - + cpu/stage2/alu/lt_29_31_g1474/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 70.300 11.700 328.800 + cpu/stage2/alu/lt_29_31_n_55 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1456/Y - C->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 39.000 15.000 343.800 + cpu/stage2/alu/lt_29_31_n_73 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1448/Y - A->Y F MAJIxp5_ASAP7_75t_SL 1 39.100 11.600 355.400 + cpu/stage2/alu/lt_29_31_n_81 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1445/Y - A->Y R MAJIxp5_ASAP7_75t_SL 1 42.100 18.000 373.400 + cpu/stage2/alu/lt_29_31_n_84 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1444/Y - A1->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 44.600 17.000 390.400 + cpu/stage2/alu/lt_29_31_n_85 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1443/Y - A1->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 33.000 33.100 423.500 + cpu/stage2/alu/lt_29_31_n_86 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1442/Y - A1->Y F AOI321xp33_ASAP7_75t_SL 1 67.400 40.100 463.600 + cpu/stage2/alu/n_324 - - F (net) 1 - - - + cpu/stage2/alu/g5667/Y - B1->Y R AOI33xp33_ASAP7_75t_SL 1 70.300 29.800 493.400 + cpu/stage2/alu/n_54 - - R (net) 1 - - - + cpu/stage2/alu/g5520/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 52.900 15.400 508.800 + cpu/stage2/alu/n_192 - - F (net) 1 - - - + cpu/stage2/alu/g5502/Y - C->Y F AO221x1_ASAP7_75t_SL 9 37.700 66.100 574.900 + cpu/stage2_alu_out[0] - - F (net) 9 - - - + cpu/stage3/memrw/g432/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 91.900 19.700 594.600 + cpu/stage3/memrw/n_6 - - R (net) 2 - - - + cpu/stage3/memrw/g425/Y - A1->Y F OAI31xp33_ASAP7_75t_SL 3 42.000 20.400 615.000 + dcache_we[1] - - F (net) 3 - - - + mem/g31/Y - B->Y F OR5x1_ASAP7_75t_SL 3 60.200 57.900 672.900 + mem/n_317 - - F (net) 3 - - - + mem/dcache/g14019/Y - B->Y R NAND2x1_ASAP7_75t_SL 5 54.600 27.800 700.700 + mem/dcache/n_316 - - R (net) 5 - - - + mem/dcache/g14016/Y - A->Y F INVx2_ASAP7_75t_SL 37 41.300 22.400 723.100 + mem/dcache/n_99 - - F (net) 37 - - - + mem/dcache/g13751/Y - A->Y R NAND3x1_ASAP7_75t_SL 4 85.900 41.800 764.900 + mem/dc_mem_req_rw - - R (net) 4 - - - + mem/dcache/g13730/Y - B->Y F NAND2xp5_ASAP7_75t_SL 2 59.100 14.300 779.200 + mem/dcache/n_314 - - F (net) 2 - - - + mem/dcache/g11166/Y - B->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 29.900 15.000 794.200 + mem/dcache/n_81 - - R (net) 1 - - - + mem/dcache/STATE_reg[1]/D - D R DFFHQNx1_ASAP7_75t_SL 1 40.200 0.100 794.200 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#--------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 900.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[1]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 3 0.100 0.000 900.000 +#--------------------------------------------------------------------------------------------------------------------------------------- +Path 3: MET (1.623 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[29]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.477 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.523 + Launch Clock:= 0.000 + Data Path:+ 790.900 + Slack:= 1.623 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 30.100 9.500 704.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_20 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1257__7482/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 16.700 16.700 721.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_231 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1256/Y - A->Y F INVx1_ASAP7_75t_SL 2 12.000 7.700 728.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_232 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1241__8428/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 11.600 12.100 740.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_246 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1238__5107/Y - B->Y R XOR2xp5_ASAP7_75t_SL 1 25.900 15.700 756.600 + cpu/stage1/stage1_pc4[29] - - R (net) 1 - - - + cpu/stage1/pcselmux/g989__6783/Y - A2->Y R AO21x1_ASAP7_75t_SL 1 20.400 13.700 770.300 + cpu/stage1/pcselmux/n_15 - - R (net) 1 - - - + cpu/stage1/pcselmux/g960__5526/Y - B->Y R AO21x1_ASAP7_75t_SL 2 15.800 13.700 784.000 + cpu/stage1/stage1_pc_mux_to_pc[29] - - R (net) 2 - - - + cpu/stage1/pcreg/g350__5526/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.200 6.900 790.900 + cpu/stage1/pcreg/n_30 - - F (net) 1 - - - + cpu/stage1/pcreg/register_reg[29]/D - D F DFFHQNx1_ASAP7_75t_SL 1 55.600 0.000 790.900 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[29]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 4: MET (2.921 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.579 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.421 + Launch Clock:= 0.000 + Data Path:+ 789.500 + Slack:= 2.921 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 30.100 9.500 704.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_20 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1257__7482/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 16.700 16.700 721.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_231 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1244__6783/Y - A1->Y F AOI21x1_ASAP7_75t_SL 2 12.000 9.200 730.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_243 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1243/Y - A->Y R INVx1_ASAP7_75t_SL 1 20.600 8.800 739.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_244 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1237__2398/Y - B->Y R XOR2xp5_ASAP7_75t_SL 1 13.300 15.600 754.700 + cpu/stage1/stage1_pc4[30] - - R (net) 1 - - - + cpu/stage1/pcselmux/g987__8428/Y - A2->Y R AO21x1_ASAP7_75t_SL 1 23.300 14.500 769.200 + cpu/stage1/pcselmux/n_17 - - R (net) 1 - - - + cpu/stage1/pcselmux/g962__3680/Y - B->Y R AO21x1_ASAP7_75t_SL 2 16.600 13.200 782.400 + cpu/stage1/stage1_pc_mux_to_pc[30] - - R (net) 2 - - - + cpu/stage1/pcreg/g349__8428/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 17.300 7.100 789.500 + cpu/stage1/pcreg/n_31 - - F (net) 1 - - - + cpu/stage1/pcreg/register_reg[30]/D - D F DFFHQNx1_ASAP7_75t_SL 1 56.000 0.000 789.500 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[30]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 5: MET (5.498 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.402 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.598 + Launch Clock:= 0.000 + Data Path:+ 787.100 + Slack:= 5.498 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/g392__9315/Y - B->Y F NOR2x2_ASAP7_75t_SL 4 13.500 16.500 401.000 + cpu/stage1/FE_OFN1064_stage1_inst_15 - - F (net) 4 - - - + cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y - A->Y R INVx3_ASAP7_75t_SL 1 31.600 10.900 411.900 + cpu/stage1/regfile/FE_OFN1120_n - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y - A->Y F INVx6_ASAP7_75t_SL 11 17.000 10.800 422.700 + cpu/stage1/regfile/FE_OFN1214_n - - F (net) 11 - - - + cpu/stage1/regfile/g80989/Y - A->Y F AND2x4_ASAP7_75t_SL 5 14.500 21.800 444.500 + cpu/stage1/regfile/n_171 - - F (net) 5 - - - + cpu/stage1/regfile/FE_OFC1149_n_171/Y - A->Y R INVx3_ASAP7_75t_SL 2 20.300 15.600 460.100 + cpu/stage1/regfile/FE_OFN1075_n_171 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC1240_n_171/Y - A->Y F INVx3_ASAP7_75t_SL 9 25.600 13.900 474.000 + cpu/stage1/regfile/FE_OFN1073_n_171 - - F (net) 9 - - - + cpu/stage1/regfile/g78521/Y - A->Y F AND2x4_ASAP7_75t_SL 5 22.500 27.300 501.300 + cpu/stage1/regfile/n_637 - - F (net) 5 - - - + cpu/stage1/regfile/g77393/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 1 28.500 11.100 512.400 + cpu/stage1/regfile/n_1747 - - R (net) 1 - - - + cpu/stage1/regfile/g77240/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 18.700 10.000 522.400 + cpu/stage1/regfile/n_1884 - - F (net) 1 - - - + cpu/stage1/regfile/g77015/Y - B->Y R NOR2x1_ASAP7_75t_SL 1 32.500 9.100 531.500 + cpu/stage1/regfile/n_2094 - - R (net) 1 - - - + cpu/stage1/regfile/g76883__7098/Y - B->Y F NAND3xp33_ASAP7_75t_SL 1 17.400 13.500 545.000 + cpu/stage1/rs1_mux_data[0] - - F (net) 1 - - - + cpu/stage1/data1sel_s1/g557__3680/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 26.500 19.200 564.200 + cpu/stage1_rs1[0] - - F (net) 2 - - - + cpu/stage1/pcadder/g1277__2883/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 13.500 17.600 581.800 + cpu/stage1/pcadder/n_31 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1454__7482/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 3 21.800 13.200 595.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_7 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1356__4319/Y - A1->Y F OAI21x1_ASAP7_75t_SL 2 20.400 9.600 604.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_153 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1335__1881/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 1 18.200 11.100 615.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_169 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1332__8246/Y - B->Y F NAND2x2_ASAP7_75t_SL 3 16.000 7.100 622.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_172 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1324__5526/Y - B->Y F AND2x2_ASAP7_75t_SL 2 12.200 15.200 638.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_180 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - A1->Y R AOI21x1_ASAP7_75t_SL 3 9.900 13.300 651.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_192 - - R (net) 3 - - - + cpu/stage1/pcadder/FE_OCPC1369_add_18_35_Y_add_17_34_Y_add_16_33_n_192/Y - A->Y R HB1xp67_ASAP7_75t_SL 2 25.400 21.200 672.500 + cpu/stage1/pcadder/FE_OCPN1343_add_18_35_Y_add_17_34_Y_add_16_33_n_192 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1310/Y - A->Y F INVx1_ASAP7_75t_SL 1 24.400 6.100 678.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_193 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1299__5115/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 11.200 14.600 693.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_202 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1290__5122/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 30.300 19.100 712.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_207 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1273__6260/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 28.600 18.500 730.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_217 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1254__1881/Y - A1->Y F OAI21xp5_ASAP7_75t_L 1 33.000 16.000 746.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_234 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1247__2802/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 22.700 16.700 763.500 + cpu/stage1/stage1_pc4[15] - - F (net) 1 - - - + cpu/stage1/pcselmux/g934__3680/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 15.300 15.400 778.900 + cpu/stage1/stage1_pc_mux_to_pc[15] - - F (net) 2 - - - + cpu/stage1/pcreg/g355__1705/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 15.100 8.200 787.100 + cpu/stage1/pcreg/n_25 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[15]/D - D R DFFHQNx1_ASAP7_75t_SL 1 52.700 0.000 787.100 +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[15]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 6: MET (7.177 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[23]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.623 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.377 + Launch Clock:= 0.000 + Data Path:+ 785.200 + Slack:= 7.177 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/g392__9315/Y - B->Y F NOR2x2_ASAP7_75t_SL 4 13.500 16.500 401.000 + cpu/stage1/FE_OFN1064_stage1_inst_15 - - F (net) 4 - - - + cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y - A->Y R INVx3_ASAP7_75t_SL 1 31.600 10.900 411.900 + cpu/stage1/regfile/FE_OFN1120_n - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y - A->Y F INVx6_ASAP7_75t_SL 11 17.000 10.800 422.700 + cpu/stage1/regfile/FE_OFN1214_n - - F (net) 11 - - - + cpu/stage1/regfile/g80989/Y - A->Y F AND2x4_ASAP7_75t_SL 5 14.500 21.800 444.500 + cpu/stage1/regfile/n_171 - - F (net) 5 - - - + cpu/stage1/regfile/FE_OFC1149_n_171/Y - A->Y R INVx3_ASAP7_75t_SL 2 20.300 15.300 459.800 + cpu/stage1/regfile/FE_OFN1075_n_171 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC1150_n_171/Y - A->Y F INVx6_ASAP7_75t_SL 13 25.600 12.700 472.500 + cpu/stage1/regfile/FE_OFN1077_n_171 - - F (net) 13 - - - + cpu/stage1/regfile/FE_OFC1152_n_171/Y - A->Y F BUFx6f_ASAP7_75t_SL 10 21.500 18.900 491.400 + cpu/stage1/regfile/FE_OFN1079_n_171 - - F (net) 10 - - - + cpu/stage1/regfile/g78044/Y - B2->Y F AO22x2_ASAP7_75t_SL 1 12.300 16.600 508.000 + cpu/stage1/regfile/n_1095 - - F (net) 1 - - - + cpu/stage1/regfile/g77303/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 9.800 8.400 516.400 + cpu/stage1/regfile/n_1826 - - R (net) 1 - - - + cpu/stage1/regfile/g77043/Y - C->Y F NAND3xp33_ASAP7_75t_SL 1 15.900 13.700 530.100 + cpu/stage1/regfile/n_2066 - - F (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - B->Y R NOR2x1_ASAP7_75t_SL 1 27.400 9.900 540.000 + cpu/stage1/regfile/n_2178 - - R (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y F NAND3x1_ASAP7_75t_SL 1 17.900 13.500 553.500 + cpu/stage1/rs1_mux_data[8] - - F (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 31.400 24.500 578.000 + cpu/stage1_rs1[8] - - F (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 16.400 19.200 597.200 + cpu/stage1/pcadder/n_39 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 3 20.500 11.500 608.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - R (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y F OAI21x1_ASAP7_75t_SL 2 18.100 8.500 617.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 18.300 8.200 625.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 12.800 14.500 639.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y R OA21x2_ASAP7_75t_SL 1 9.700 14.100 654.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y F OAI21x1_ASAP7_75t_SL 3 10.500 19.000 673.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1280__3680/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 32.600 16.800 689.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_213 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1270__5477/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 29.300 18.000 707.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_220 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1255__5115/Y - A1->Y R AOI21xp5_ASAP7_75t_L 2 26.900 22.700 730.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_233 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1242__5526/Y - A1->Y F OAI21xp5_ASAP7_75t_SL 1 38.100 13.700 744.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_245 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1239__6260/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 24.900 17.500 761.700 + cpu/stage1/stage1_pc4[23] - - F (net) 1 - - - + cpu/stage1/pcselmux/g933__6783/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 15.300 15.100 776.800 + cpu/stage1/stage1_pc_mux_to_pc[23] - - F (net) 2 - - - + cpu/stage1/pcreg/g364__6161/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.800 8.400 785.200 + cpu/stage1/pcreg/n_16 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[23]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.000 0.000 785.200 +#-------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[23]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 7: MET (7.936 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.064 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.936 + Launch Clock:= 0.000 + Data Path:+ 784.000 + Slack:= 7.936 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 0.000 + cpu/s1_to_s2_inst/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_inst/register_reg[2]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_SL 1 0.100 30.000 30.000 + cpu/stage2_inst[2] - - R (net) 1 - - - + cpu/FE_OFC948_stage2_inst_2/Y - A->Y F INVx1_ASAP7_75t_SL 2 13.500 6.400 36.400 + cpu/FE_OFN851_stage2_inst_2 - - F (net) 2 - - - + cpu/FE_OFC952_stage2_inst_2/Y - A->Y R INVx1_ASAP7_75t_SL 13 9.500 29.600 66.000 + cpu/FE_OFN850_stage2_inst_2 - - R (net) 13 - - - + cpu/FE_OFC670_stage2_inst_2/Y - A->Y R BUFx2_ASAP7_75t_SL 9 59.500 25.900 91.900 + cpu/FE_OFN854_stage2_inst_2 - - R (net) 9 - - - + cpu/stage2/alusel/g764/Y - B->Y R OR2x2_ASAP7_75t_SL 3 25.000 15.600 107.500 + cpu/stage2/alusel/n_5 - - R (net) 3 - - - + cpu/stage2/alusel/g759/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 10.800 13.500 121.000 + cpu/stage2/alusel/n_9 - - F (net) 2 - - - + cpu/stage2/alusel/g755/Y - B->Y R NAND2xp5_ASAP7_75t_SL 3 26.600 18.400 139.400 + cpu/stage2/alusel/n_14 - - R (net) 3 - - - + cpu/stage2/alusel/FE_OFC746_n_14/Y - A->Y F INVx1_ASAP7_75t_SL 2 29.400 7.300 146.700 + cpu/stage2/alusel/n_13 - - F (net) 2 - - - + cpu/stage2/alusel/g751/Y - B->Y F AND2x2_ASAP7_75t_SL 3 13.600 15.200 161.900 + cpu/stage2/alusel/n_17 - - F (net) 3 - - - + cpu/stage2/alusel/g746/Y - B1->Y F AO221x1_ASAP7_75t_SL 1 12.100 18.700 180.600 + cpu/stage2/ALUop[1] - - F (net) 1 - - - + cpu/stage2/alu/FE_OFC626_ALUop_1/Y - A->Y R INVx1_ASAP7_75t_SL 5 13.400 21.500 202.100 + cpu/stage2/alu/n_0 - - R (net) 5 - - - + cpu/stage2/alu/FE_OFC627_ALUop_1/Y - A->Y F INVx1_ASAP7_75t_SL 4 37.200 15.600 217.700 + cpu/stage2/alu/FE_OFN823_ALUop_1 - - F (net) 4 - - - + cpu/stage2/alu/g3304/Y - B->Y R NOR2x1_ASAP7_75t_SL 3 25.000 13.200 230.900 + cpu/stage2/alu/n_194 - - R (net) 3 - - - + cpu/stage2/alu/g3302/Y - A->Y R AND3x4_ASAP7_75t_SL 9 23.600 26.700 257.600 + cpu/stage2/alu/n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC775_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 3 29.000 15.400 273.000 + cpu/stage2/alu/FE_OFN922_n_325 - - F (net) 3 - - - + cpu/stage2/alu/FE_OFC778_n_325/Y - A->Y R INVx3_ASAP7_75t_SL 9 24.200 24.000 297.000 + cpu/stage2/alu/FE_OFN925_n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC782_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 7 44.400 41.300 338.300 + cpu/stage2/alu/FE_OFN929_n_325 - - F (net) 7 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1722/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 2 72.200 24.100 362.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_36 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1655/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 45.200 24.300 386.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_116 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A1->Y F OA21x2_ASAP7_75t_SL 3 43.900 22.200 408.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y R OAI321xp33_ASAP7_75t_SL 1 13.300 17.300 426.200 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y F INVx1_ASAP7_75t_SL 2 42.800 11.500 437.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 21.200 19.000 456.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 10.600 16.200 472.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 10.800 9.200 482.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y R OR2x2_ASAP7_75t_SL 3 18.000 17.600 499.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y F AOI31xp67_ASAP7_75t_SL 3 15.800 16.400 516.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 34.100 15.700 531.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y R OR2x2_ASAP7_75t_SL 3 32.100 25.500 557.300 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 27.300 15.500 572.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y F NAND2xp5_ASAP7_75t_L 2 12.900 11.700 584.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 18.800 14.600 599.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 37.100 10.300 609.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y R INVx1_ASAP7_75t_SL 3 20.500 13.500 622.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.500 16.600 639.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 16.200 12.900 652.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 22.100 19.100 671.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 11.700 17.200 688.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 12.100 17.200 705.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1504/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 11.900 15.900 721.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_238 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1503/Y - B->Y F XOR2xp5_ASAP7_75t_SL 1 10.200 12.200 734.000 + cpu/stage2/alu/n_322 - - F (net) 1 - - - + cpu/stage2/alu/g5521/Y - A2->Y F AO21x1_ASAP7_75t_L 4 19.200 31.900 765.900 + dcache_addr[31] - - F (net) 4 - - - + cpu/stage3/csr/g178/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 33.800 18.100 784.000 + cpu/stage3/csr/n_17 - - R (net) 1 - - - + cpu/stage3/csr/csr_reg[31]/D - D R DFFHQNx1_ASAP7_75t_SL 1 56.600 0.700 784.000 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage3/csr/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage3/csr/csr_reg[31]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------------- +Path 8: MET (8.068 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 4.732 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 795.268 + Launch Clock:= 0.000 + Data Path:+ 787.200 + Slack:= 8.068 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 30.100 9.500 704.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_20 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1263__2883/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 16.700 19.200 723.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_226 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1249__5122/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 32.700 13.900 737.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_238 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1240__4319/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 1 27.500 12.900 750.400 + cpu/stage1/stage1_pc4[27] - - R (net) 1 - - - + cpu/stage1/pcselmux/g999__5115/Y - B->Y F NAND2xp5_ASAP7_75t_L 1 21.100 9.800 760.200 + cpu/stage1/pcselmux/n_5 - - F (net) 1 - - - + cpu/stage1/pcselmux/g932__5526/Y - A->Y R NAND2xp5_ASAP7_75t_SL 2 37.400 16.400 776.600 + cpu/stage1/stage1_pc_mux_to_pc[27] - - R (net) 2 - - - + cpu/stage1/pcreg/g352__3680/Y - B->Y F NAND2xp5_ASAP7_75t_L 1 25.200 10.600 787.200 + cpu/stage1/pcreg/n_28 - - F (net) 1 - - - + cpu/stage1/pcreg/register_reg[27]/D - D F DFFHQNx1_ASAP7_75t_SL 1 44.800 0.100 787.200 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 9: MET (8.384 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[22]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.116 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.884 + Launch Clock:= 0.000 + Data Path:+ 782.500 + Slack:= 8.384 + Timing Path: + +#--------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 7.800 392.300 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g397__7410/Y - B->Y F AND2x4_ASAP7_75t_SL 44 11.400 68.300 460.600 + cpu/stage1_inst[22] - - F (net) 44 - - - + cpu/stage1/regfile/g80975/Y - A->Y R INVx4_ASAP7_75t_SL 19 195.500 49.100 509.700 + cpu/stage1/regfile/n_179 - - R (net) 19 - - - + cpu/stage1/regfile/g79812/Y - A->Y F NOR2xp33_ASAP7_75t_SL 3 91.500 34.800 544.500 + cpu/stage1/regfile/n_342 - - F (net) 3 - - - + cpu/stage1/regfile/g79319/Y - A->Y R INVx1_ASAP7_75t_SL 2 55.600 12.400 556.900 + cpu/stage1/regfile/n_341 - - R (net) 2 - - - + cpu/stage1/regfile/g78503/Y - B->Y F NOR2xp33_ASAP7_75t_SL 7 21.600 74.000 630.900 + cpu/stage1/regfile/n_662 - - F (net) 7 - - - + cpu/stage1/regfile/g77810/Y - A2->Y R AOI22xp5_ASAP7_75t_SL 1 144.900 20.600 651.500 + cpu/stage1/regfile/n_1330 - - R (net) 1 - - - + cpu/stage1/regfile/g77085/Y - C->Y F NAND5xp2_ASAP7_75t_SL 1 52.400 22.300 673.800 + cpu/stage1/regfile/n_2024 - - F (net) 1 - - - + cpu/stage1/regfile/g77004/Y - B->Y R AOI211xp5_ASAP7_75t_SL 1 48.900 24.900 698.700 + cpu/stage1/regfile/n_2105 - - R (net) 1 - - - + cpu/stage1/regfile/g76906__1617/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 43.900 46.700 745.400 + cpu/stage1/rs2_mux_data[22] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g562__5122/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 97.800 25.700 771.100 + cpu/stage1_rs2[22] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g443__7482/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.700 11.400 782.500 + cpu/s1_to_s2_rs2/n_8 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[22]/D - D R DFFHQNx1_ASAP7_75t_SL 1 62.800 0.400 782.500 +#--------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[22]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 10: MET (11.245 ps) Setup Check with Pin mem/dcache/STATE_reg[2]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) mem/dcache/STATE_reg[2]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 5.354 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 794.646 + Launch Clock:= 0.000 + Data Path:+ 783.400 + Slack:= 11.245 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2318/Y - B1->Y F OAI221xp5_ASAP7_75t_SL 1 33.100 15.600 168.300 + cpu/stage3/wb_dmem[0] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1103/Y - A1->Y F AO21x1_ASAP7_75t_SL 3 28.600 22.400 190.700 + cpu/wb_data[0] - - F (net) 3 - - - + cpu/stage2/rs2DataSel/g563/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 17.700 29.600 220.300 + cpu/stage2/stage2_rs2_data[0] - - F (net) 8 - - - + cpu/stage2/bselmux/g583/Y - A->Y R NAND2xp5_ASAP7_75t_SL 1 31.200 12.400 232.700 + cpu/stage2/bselmux/n_6 - - R (net) 1 - - - + cpu/stage2/bselmux/g559/Y - A->Y R AND2x2_ASAP7_75t_SL 2 23.400 23.000 255.700 + cpu/stage2/stage2_alu_in2[0] - - R (net) 2 - - - + cpu/stage2/alu/FE_OFC692_n_30/Y - A->Y F INVx3_ASAP7_75t_SL 24 23.300 22.500 278.200 + cpu/stage2/alu/FE_OFN867_n_30 - - F (net) 24 - - - + cpu/stage2/alu/FE_OFC696_n_30/Y - A->Y R INVx1_ASAP7_75t_SL 14 39.300 38.900 317.100 + cpu/stage2/alu/FE_OFN871_n_30 - - R (net) 14 - - - + cpu/stage2/alu/lt_29_31_g1474/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 70.300 11.700 328.800 + cpu/stage2/alu/lt_29_31_n_55 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1456/Y - C->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 39.000 15.000 343.800 + cpu/stage2/alu/lt_29_31_n_73 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1448/Y - A->Y F MAJIxp5_ASAP7_75t_SL 1 39.100 11.600 355.400 + cpu/stage2/alu/lt_29_31_n_81 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1445/Y - A->Y R MAJIxp5_ASAP7_75t_SL 1 42.100 18.000 373.400 + cpu/stage2/alu/lt_29_31_n_84 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1444/Y - A1->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 44.600 17.000 390.400 + cpu/stage2/alu/lt_29_31_n_85 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1443/Y - A1->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 33.000 33.100 423.500 + cpu/stage2/alu/lt_29_31_n_86 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1442/Y - A1->Y F AOI321xp33_ASAP7_75t_SL 1 67.400 40.100 463.600 + cpu/stage2/alu/n_324 - - F (net) 1 - - - + cpu/stage2/alu/g5667/Y - B1->Y R AOI33xp33_ASAP7_75t_SL 1 70.300 29.800 493.400 + cpu/stage2/alu/n_54 - - R (net) 1 - - - + cpu/stage2/alu/g5520/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 52.900 15.400 508.800 + cpu/stage2/alu/n_192 - - F (net) 1 - - - + cpu/stage2/alu/g5502/Y - C->Y F AO221x1_ASAP7_75t_SL 9 37.700 66.100 574.900 + cpu/stage2_alu_out[0] - - F (net) 9 - - - + cpu/stage3/memrw/g432/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 91.900 19.700 594.600 + cpu/stage3/memrw/n_6 - - R (net) 2 - - - + cpu/stage3/memrw/g425/Y - A1->Y F OAI31xp33_ASAP7_75t_SL 3 42.000 20.400 615.000 + dcache_we[1] - - F (net) 3 - - - + mem/g31/Y - B->Y F OR5x1_ASAP7_75t_SL 3 60.200 57.900 672.900 + mem/n_317 - - F (net) 3 - - - + mem/dcache/g14019/Y - B->Y R NAND2x1_ASAP7_75t_SL 5 54.600 27.800 700.700 + mem/dcache/n_316 - - R (net) 5 - - - + mem/dcache/g14016/Y - A->Y F INVx2_ASAP7_75t_SL 37 41.300 22.400 723.100 + mem/dcache/n_99 - - F (net) 37 - - - + mem/dcache/g13751/Y - A->Y R NAND3x1_ASAP7_75t_SL 4 85.900 41.800 764.900 + mem/dc_mem_req_rw - - R (net) 4 - - - + mem/dcache/FE_OFC439_dc_mem_req_rw/Y - A->Y F INVx1_ASAP7_75t_SL 1 59.100 6.300 771.200 + mem/dcache/n_2 - - F (net) 1 - - - + mem/dcache/g11190/Y - B->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 19.100 12.200 783.400 + mem/dcache/n_57 - - R (net) 1 - - - + mem/dcache/STATE_reg[2]/D - D R DFFHQNx1_ASAP7_75t_SL 1 38.700 0.000 783.400 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#--------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 900.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[2]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 3 0.100 0.000 900.000 +#--------------------------------------------------------------------------------------------------------------------------------------- +Path 11: MET (11.743 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[22]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.657 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.343 + Launch Clock:= 0.000 + Data Path:+ 780.600 + Slack:= 11.743 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1280__3680/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_213 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1270__5477/Y - B->Y R NOR2xp33_ASAP7_75t_SL 2 30.200 19.500 714.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_220 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1255__5115/Y - A1->Y F AOI21xp5_ASAP7_75t_L 2 34.800 20.800 735.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_233 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1245__3680/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 29.700 20.300 755.500 + cpu/stage1/stage1_pc4[22] - - F (net) 1 - - - + cpu/stage1/pcselmux/g936__2802/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 22.200 16.600 772.100 + cpu/stage1/stage1_pc_mux_to_pc[22] - - F (net) 2 - - - + cpu/stage1/pcreg/g378__5526/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 15.100 8.500 780.600 + cpu/stage1/pcreg/n_2 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[22]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.200 0.000 780.600 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[22]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 12: MET (14.886 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[16]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[16]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.014 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.986 + Launch Clock:= 0.000 + Data Path:+ 776.100 + Slack:= 14.886 + Timing Path: + +#--------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 7.800 392.300 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g397__7410/Y - B->Y F AND2x4_ASAP7_75t_SL 44 11.400 68.300 460.600 + cpu/stage1_inst[22] - - F (net) 44 - - - + cpu/stage1/regfile/g80975/Y - A->Y R INVx4_ASAP7_75t_SL 19 195.500 49.100 509.700 + cpu/stage1/regfile/n_179 - - R (net) 19 - - - + cpu/stage1/regfile/g79812/Y - A->Y F NOR2xp33_ASAP7_75t_SL 3 91.500 34.800 544.500 + cpu/stage1/regfile/n_342 - - F (net) 3 - - - + cpu/stage1/regfile/g79319/Y - A->Y R INVx1_ASAP7_75t_SL 2 55.600 12.400 556.900 + cpu/stage1/regfile/n_341 - - R (net) 2 - - - + cpu/stage1/regfile/g78503/Y - B->Y F NOR2xp33_ASAP7_75t_SL 7 21.600 73.800 630.700 + cpu/stage1/regfile/n_662 - - F (net) 7 - - - + cpu/stage1/regfile/g77583/Y - A2->Y R AOI22xp5_ASAP7_75t_SL 1 144.800 20.500 651.200 + cpu/stage1/regfile/n_1553 - - R (net) 1 - - - + cpu/stage1/regfile/g77069/Y - C->Y F NAND5xp2_ASAP7_75t_SL 1 52.300 19.300 670.500 + cpu/stage1/regfile/n_2040 - - F (net) 1 - - - + cpu/stage1/regfile/g77003/Y - B->Y R AOI211xp5_ASAP7_75t_SL 1 42.500 20.500 691.000 + cpu/stage1/regfile/n_2106 - - R (net) 1 - - - + cpu/stage1/regfile/g76905__3680/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 35.700 47.700 738.700 + cpu/stage1/rs2_mux_data[16] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g555__8428/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 102.900 26.200 764.900 + cpu/stage1_rs2[16] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g436__1705/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 13.100 11.200 776.100 + cpu/s1_to_s2_rs2/n_15 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[16]/D - D R DFFHQNx1_ASAP7_75t_SL 1 62.200 0.300 776.100 +#--------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[16]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 13: MET (15.388 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.012 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.988 + Launch Clock:= 0.000 + Data Path:+ 777.600 + Slack:= 15.388 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 -0.000 + cpu/s1_to_s2_inst/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_inst/register_reg[2]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_SL 1 0.100 30.000 30.000 + cpu/stage2_inst[2] - - R (net) 1 - - - + cpu/FE_OFC948_stage2_inst_2/Y - A->Y F INVx1_ASAP7_75t_SL 2 13.500 6.400 36.400 + cpu/FE_OFN851_stage2_inst_2 - - F (net) 2 - - - + cpu/FE_OFC952_stage2_inst_2/Y - A->Y R INVx1_ASAP7_75t_SL 13 9.500 29.600 66.000 + cpu/FE_OFN850_stage2_inst_2 - - R (net) 13 - - - + cpu/FE_OFC670_stage2_inst_2/Y - A->Y R BUFx2_ASAP7_75t_SL 9 59.500 25.900 91.900 + cpu/FE_OFN854_stage2_inst_2 - - R (net) 9 - - - + cpu/stage2/alusel/g764/Y - B->Y R OR2x2_ASAP7_75t_SL 3 25.000 15.600 107.500 + cpu/stage2/alusel/n_5 - - R (net) 3 - - - + cpu/stage2/alusel/g759/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 10.800 13.500 121.000 + cpu/stage2/alusel/n_9 - - F (net) 2 - - - + cpu/stage2/alusel/g755/Y - B->Y R NAND2xp5_ASAP7_75t_SL 3 26.600 18.400 139.400 + cpu/stage2/alusel/n_14 - - R (net) 3 - - - + cpu/stage2/alusel/FE_OFC746_n_14/Y - A->Y F INVx1_ASAP7_75t_SL 2 29.400 7.300 146.700 + cpu/stage2/alusel/n_13 - - F (net) 2 - - - + cpu/stage2/alusel/g751/Y - B->Y F AND2x2_ASAP7_75t_SL 3 13.600 15.200 161.900 + cpu/stage2/alusel/n_17 - - F (net) 3 - - - + cpu/stage2/alusel/g746/Y - B1->Y F AO221x1_ASAP7_75t_SL 1 12.100 18.700 180.600 + cpu/stage2/ALUop[1] - - F (net) 1 - - - + cpu/stage2/alu/FE_OFC626_ALUop_1/Y - A->Y R INVx1_ASAP7_75t_SL 5 13.400 21.500 202.100 + cpu/stage2/alu/n_0 - - R (net) 5 - - - + cpu/stage2/alu/FE_OFC627_ALUop_1/Y - A->Y F INVx1_ASAP7_75t_SL 4 37.200 15.600 217.700 + cpu/stage2/alu/FE_OFN823_ALUop_1 - - F (net) 4 - - - + cpu/stage2/alu/g3304/Y - B->Y R NOR2x1_ASAP7_75t_SL 3 25.000 13.200 230.900 + cpu/stage2/alu/n_194 - - R (net) 3 - - - + cpu/stage2/alu/g3302/Y - A->Y R AND3x4_ASAP7_75t_SL 9 23.600 26.700 257.600 + cpu/stage2/alu/n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC775_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 3 29.000 15.400 273.000 + cpu/stage2/alu/FE_OFN922_n_325 - - F (net) 3 - - - + cpu/stage2/alu/FE_OFC778_n_325/Y - A->Y R INVx3_ASAP7_75t_SL 9 24.200 24.000 297.000 + cpu/stage2/alu/FE_OFN925_n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC782_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 7 44.400 41.300 338.300 + cpu/stage2/alu/FE_OFN929_n_325 - - F (net) 7 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1722/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 2 72.200 24.100 362.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_36 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1655/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 45.200 24.300 386.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_116 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A1->Y F OA21x2_ASAP7_75t_SL 3 43.900 22.200 408.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y R OAI321xp33_ASAP7_75t_SL 1 13.300 17.300 426.200 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y F INVx1_ASAP7_75t_SL 2 42.800 11.500 437.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 21.200 19.000 456.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 10.600 16.200 472.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 10.800 9.200 482.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y R OR2x2_ASAP7_75t_SL 3 18.000 17.600 499.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y F AOI31xp67_ASAP7_75t_SL 3 15.800 16.400 516.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 34.100 15.700 531.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y R OR2x2_ASAP7_75t_SL 3 32.100 25.500 557.300 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 27.300 15.500 572.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y F NAND2xp5_ASAP7_75t_L 2 12.900 11.700 584.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 18.800 14.600 599.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 37.100 10.300 609.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y R INVx1_ASAP7_75t_SL 3 20.500 13.500 622.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.500 16.600 639.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 16.200 12.900 652.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 22.100 19.100 671.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 11.700 17.200 688.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 12.100 17.200 705.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1504/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 11.900 15.900 721.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_238 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1503/Y - B->Y F XOR2xp5_ASAP7_75t_SL 1 10.200 12.200 734.000 + cpu/stage2/alu/n_322 - - F (net) 1 - - - + cpu/stage2/alu/g5521/Y - A2->Y F AO21x1_ASAP7_75t_L 4 19.200 31.400 765.400 + dcache_addr[31] - - F (net) 4 - - - + cpu/s2_to_s3_alu/g420__5477/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 33.700 12.200 777.600 + cpu/s2_to_s3_alu/n_31 - - R (net) 1 - - - + cpu/s2_to_s3_alu/register_reg[31]/D - D R DFFHQNx1_ASAP7_75t_SL 1 50.400 0.100 777.600 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s2_to_s3_alu/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s2_to_s3_alu/register_reg[31]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 14: MET (16.484 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[20]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[20]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.316 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.684 + Launch Clock:= 0.000 + Data Path:+ 775.200 + Slack:= 16.484 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.600 519.900 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y R AND2x2_ASAP7_75t_L 33 160.100 109.800 629.700 + cpu/stage1/regfile/n_266 - - R (net) 33 - - - + cpu/stage1/regfile/g77177/Y - B1->Y R AO222x2_ASAP7_75t_SL 1 191.800 49.800 679.500 + cpu/stage1/regfile/n_1938 - - R (net) 1 - - - + cpu/stage1/regfile/g77022/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 18.100 10.800 690.300 + cpu/stage1/regfile/n_2087 - - F (net) 1 - - - + cpu/stage1/regfile/g76958__8428/Y - A->Y R NAND5xp2_ASAP7_75t_SL 1 75.300 14.700 705.000 + cpu/stage1/regfile/n_2147 - - R (net) 1 - - - + cpu/stage1/regfile/g76903__5526/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 36.600 8.400 713.400 + cpu/stage1/regfile/n_2170 - - F (net) 1 - - - + cpu/stage1/regfile/g76895__7410/Y - B->Y R NAND5xp2_ASAP7_75t_SL 1 63.400 33.600 747.000 + cpu/stage1/rs2_mux_data[20] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g571__9315/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 52.000 21.400 768.400 + cpu/stage1_rs2[20] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g441__1881/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 14.100 6.800 775.200 + cpu/s1_to_s2_rs2/n_10 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[20]/D - D F DFFHQNx1_ASAP7_75t_SL 1 58.900 0.000 775.200 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[20]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 15: MET (16.826 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.674 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.326 + Launch Clock:= 0.000 + Data Path:+ 775.500 + Slack:= 16.826 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/g392__9315/Y - B->Y F NOR2x2_ASAP7_75t_SL 4 13.500 16.500 401.000 + cpu/stage1/FE_OFN1064_stage1_inst_15 - - F (net) 4 - - - + cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y - A->Y R INVx3_ASAP7_75t_SL 1 31.600 10.900 411.900 + cpu/stage1/regfile/FE_OFN1120_n - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y - A->Y F INVx6_ASAP7_75t_SL 11 17.000 10.800 422.700 + cpu/stage1/regfile/FE_OFN1214_n - - F (net) 11 - - - + cpu/stage1/regfile/g80989/Y - A->Y F AND2x4_ASAP7_75t_SL 5 14.500 21.800 444.500 + cpu/stage1/regfile/n_171 - - F (net) 5 - - - + cpu/stage1/regfile/FE_OFC1149_n_171/Y - A->Y R INVx3_ASAP7_75t_SL 2 20.300 15.300 459.800 + cpu/stage1/regfile/FE_OFN1075_n_171 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC1150_n_171/Y - A->Y F INVx6_ASAP7_75t_SL 13 25.600 12.700 472.500 + cpu/stage1/regfile/FE_OFN1077_n_171 - - F (net) 13 - - - + cpu/stage1/regfile/FE_OFC1152_n_171/Y - A->Y F BUFx6f_ASAP7_75t_SL 10 21.500 18.900 491.400 + cpu/stage1/regfile/FE_OFN1079_n_171 - - F (net) 10 - - - + cpu/stage1/regfile/g78044/Y - B2->Y F AO22x2_ASAP7_75t_SL 1 12.300 16.600 508.000 + cpu/stage1/regfile/n_1095 - - F (net) 1 - - - + cpu/stage1/regfile/g77303/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 9.800 8.400 516.400 + cpu/stage1/regfile/n_1826 - - R (net) 1 - - - + cpu/stage1/regfile/g77043/Y - C->Y F NAND3xp33_ASAP7_75t_SL 1 15.900 13.700 530.100 + cpu/stage1/regfile/n_2066 - - F (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - B->Y R NOR2x1_ASAP7_75t_SL 1 27.400 9.900 540.000 + cpu/stage1/regfile/n_2178 - - R (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y F NAND3x1_ASAP7_75t_SL 1 17.900 13.500 553.500 + cpu/stage1/rs1_mux_data[8] - - F (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 31.400 24.500 578.000 + cpu/stage1_rs1[8] - - F (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 16.400 19.200 597.200 + cpu/stage1/pcadder/n_39 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 3 20.500 11.500 608.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - R (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y F OAI21x1_ASAP7_75t_SL 2 18.100 8.500 617.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 18.300 8.200 625.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 12.800 14.500 639.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y R OA21x2_ASAP7_75t_SL 1 9.700 14.100 654.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y F OAI21x1_ASAP7_75t_SL 3 10.500 19.100 673.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1295/Y - A->Y R INVx1_ASAP7_75t_SL 2 32.600 13.000 686.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_203 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1288__1705/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 20.100 16.500 702.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_209 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1272__5107/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 33.300 17.700 720.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_218 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1253__6131/Y - A1->Y F OAI21xp5_ASAP7_75t_SL 1 31.400 12.900 733.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_235 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1246__1617/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 22.700 18.100 751.300 + cpu/stage1/stage1_pc4[19] - - F (net) 1 - - - + cpu/stage1/pcselmux/g947__9315/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 18.200 15.600 766.900 + cpu/stage1/stage1_pc_mux_to_pc[19] - - F (net) 2 - - - + cpu/stage1/pcreg/g360__1881/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.800 8.600 775.500 + cpu/stage1/pcreg/n_20 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[19]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.300 0.100 775.500 +#-------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[19]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 16: MET (18.101 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.799 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.201 + Launch Clock:= 0.000 + Data Path:+ 773.100 + Slack:= 18.101 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.700 520.000 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 160.100 34.400 554.400 + cpu/stage1/regfile/n_345 - - F (net) 4 - - - + cpu/stage1/regfile/g78531/Y - B->Y R NOR2xp67_ASAP7_75t_SL 12 76.500 102.200 656.600 + cpu/stage1/regfile/n_622 - - R (net) 12 - - - + cpu/stage1/regfile/g77643/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 195.400 23.500 680.100 + cpu/stage1/regfile/n_1497 - - F (net) 1 - - - + cpu/stage1/regfile/g77150/Y - C->Y R NAND3xp33_ASAP7_75t_SL 1 73.400 21.200 701.300 + cpu/stage1/regfile/n_1959 - - R (net) 1 - - - + cpu/stage1/regfile/g77073/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 36.300 11.400 712.700 + cpu/stage1/regfile/n_2036 - - F (net) 1 - - - + cpu/stage1/regfile/g76953__5477/Y - A->Y R NAND5xp2_ASAP7_75t_SL 1 57.500 28.500 741.200 + cpu/stage1/rs2_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g573__2883/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 53.900 23.500 764.700 + cpu/stage1_rs2[8] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g428__6260/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 17.300 8.400 773.100 + cpu/s1_to_s2_rs2/n_23 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[8]/D - D F DFFHQNx1_ASAP7_75t_SL 1 60.800 0.100 773.100 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[8]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 17: MET (19.622 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[7]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[7]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.878 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.122 + Launch Clock:= 0.000 + Data Path:+ 771.500 + Slack:= 19.622 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80394/Y - B->Y R NAND2xp5_ASAP7_75t_SL 3 27.100 16.000 462.300 + cpu/stage1/regfile/n_250 - - R (net) 3 - - - + cpu/stage1/regfile/g79869/Y - A->Y F INVx1_ASAP7_75t_SL 4 27.100 12.300 474.600 + cpu/stage1/regfile/n_249 - - F (net) 4 - - - + cpu/stage1/regfile/g79860/Y - A->Y F AND2x2_ASAP7_75t_SL 27 19.400 81.600 556.200 + cpu/stage1/regfile/n_277 - - F (net) 27 - - - + cpu/stage1/regfile/g79348/Y - A->Y R INVx1_ASAP7_75t_SL 2 156.600 30.400 586.600 + cpu/stage1/regfile/n_276 - - R (net) 2 - - - + cpu/stage1/regfile/g78488/Y - B->Y F NOR2xp33_ASAP7_75t_SL 5 54.900 75.800 662.400 + cpu/stage1/regfile/n_681 - - F (net) 5 - - - + cpu/stage1/regfile/g77645/Y - A2->Y R AOI22xp5_ASAP7_75t_SL 1 144.600 20.900 683.300 + cpu/stage1/regfile/n_1495 - - R (net) 1 - - - + cpu/stage1/regfile/g77151/Y - C->Y F NAND3xp33_ASAP7_75t_SL 1 52.800 8.500 691.800 + cpu/stage1/regfile/n_1958 - - F (net) 1 - - - + cpu/stage1/regfile/g76907__2802/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 24.600 15.600 707.400 + cpu/stage1/regfile/n_2169 - - R (net) 1 - - - + cpu/stage1/regfile/g76894__1666/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 78.100 31.100 738.500 + cpu/stage1/rs2_mux_data[7] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g575__1666/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 61.400 22.500 761.000 + cpu/stage1_rs2[7] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g427__5107/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 11.000 10.500 771.500 + cpu/s1_to_s2_rs2/n_24 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[7]/D - D R DFFHQNx1_ASAP7_75t_SL 1 61.400 0.300 771.500 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[7]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 18: MET (20.159 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.341 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.659 + Launch Clock:= 0.000 + Data Path:+ 771.500 + Slack:= 20.159 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.700 520.000 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 160.100 34.400 554.400 + cpu/stage1/regfile/n_345 - - F (net) 4 - - - + cpu/stage1/regfile/g78528/Y - B->Y R NOR2xp67_ASAP7_75t_SL 12 76.500 104.700 659.100 + cpu/stage1/regfile/n_625 - - R (net) 12 - - - + cpu/stage1/regfile/g77227/Y - B1->Y R AO222x2_ASAP7_75t_SL 1 203.100 51.600 710.700 + cpu/stage1/regfile/n_1897 - - R (net) 1 - - - + cpu/stage1/regfile/g77007/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 17.700 10.800 721.500 + cpu/stage1/regfile/n_2102 - - F (net) 1 - - - + cpu/stage1/regfile/g76922__1666/Y - A->Y R NAND5xp2_ASAP7_75t_SL 1 61.200 14.100 735.600 + cpu/stage1/regfile/n_2161 - - R (net) 1 - - - + cpu/stage1/regfile/g76882__8246/Y - B->Y R AO21x1_ASAP7_75t_SL 1 35.400 12.900 748.500 + cpu/stage1/rs2_mux_data[19] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g574__2346/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 16.100 16.000 764.500 + cpu/stage1_rs2[19] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g440__6131/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 13.800 7.000 771.500 + cpu/s1_to_s2_rs2/n_11 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[19]/D - D F DFFHQNx1_ASAP7_75t_SL 1 59.000 0.100 771.500 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[19]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 19: MET (21.328 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[13]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[13]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.572 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.428 + Launch Clock:= 0.000 + Data Path:+ 771.100 + Slack:= 21.328 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/g392__9315/Y - B->Y F NOR2x2_ASAP7_75t_SL 4 13.500 16.500 401.000 + cpu/stage1/FE_OFN1064_stage1_inst_15 - - F (net) 4 - - - + cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y - A->Y R INVx3_ASAP7_75t_SL 1 31.600 10.900 411.900 + cpu/stage1/regfile/FE_OFN1120_n - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y - A->Y F INVx6_ASAP7_75t_SL 11 17.000 10.800 422.700 + cpu/stage1/regfile/FE_OFN1214_n - - F (net) 11 - - - + cpu/stage1/regfile/g80989/Y - A->Y F AND2x4_ASAP7_75t_SL 5 14.500 21.800 444.500 + cpu/stage1/regfile/n_171 - - F (net) 5 - - - + cpu/stage1/regfile/FE_OFC1149_n_171/Y - A->Y R INVx3_ASAP7_75t_SL 2 20.300 15.600 460.100 + cpu/stage1/regfile/FE_OFN1075_n_171 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC1240_n_171/Y - A->Y F INVx3_ASAP7_75t_SL 9 25.600 13.900 474.000 + cpu/stage1/regfile/FE_OFN1073_n_171 - - F (net) 9 - - - + cpu/stage1/regfile/g78521/Y - A->Y F AND2x4_ASAP7_75t_SL 5 22.500 27.300 501.300 + cpu/stage1/regfile/n_637 - - F (net) 5 - - - + cpu/stage1/regfile/g77393/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 1 28.500 11.100 512.400 + cpu/stage1/regfile/n_1747 - - R (net) 1 - - - + cpu/stage1/regfile/g77240/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 18.700 10.000 522.400 + cpu/stage1/regfile/n_1884 - - F (net) 1 - - - + cpu/stage1/regfile/g77015/Y - B->Y R NOR2x1_ASAP7_75t_SL 1 32.500 9.100 531.500 + cpu/stage1/regfile/n_2094 - - R (net) 1 - - - + cpu/stage1/regfile/g76883__7098/Y - B->Y F NAND3xp33_ASAP7_75t_SL 1 17.400 13.500 545.000 + cpu/stage1/rs1_mux_data[0] - - F (net) 1 - - - + cpu/stage1/data1sel_s1/g557__3680/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 26.500 19.200 564.200 + cpu/stage1_rs1[0] - - F (net) 2 - - - + cpu/stage1/pcadder/g1277__2883/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 13.500 17.600 581.800 + cpu/stage1/pcadder/n_31 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1454__7482/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 3 21.800 13.200 595.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_7 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1356__4319/Y - A1->Y F OAI21x1_ASAP7_75t_SL 2 20.400 9.600 604.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_153 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1335__1881/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 1 18.200 11.100 615.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_169 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1332__8246/Y - B->Y F NAND2x2_ASAP7_75t_SL 3 16.000 7.100 622.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_172 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1324__5526/Y - B->Y F AND2x2_ASAP7_75t_SL 2 12.200 15.200 638.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_180 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - A1->Y R AOI21x1_ASAP7_75t_SL 3 9.900 13.300 651.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_192 - - R (net) 3 - - - + cpu/stage1/pcadder/FE_OCPC1369_add_18_35_Y_add_17_34_Y_add_16_33_n_192/Y - A->Y R HB1xp67_ASAP7_75t_SL 2 25.400 21.200 672.500 + cpu/stage1/pcadder/FE_OCPN1343_add_18_35_Y_add_17_34_Y_add_16_33_n_192 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1310/Y - A->Y F INVx1_ASAP7_75t_SL 1 24.400 6.100 678.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_193 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1299__5115/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 11.200 14.600 693.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_202 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1290__5122/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 30.300 19.100 712.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_207 - - F (net) 2 - - - + cpu/stage1/pcadder/FE_OFC708_add_18_35_Y_add_17_34_Y_add_16_33_n_207/Y - A->Y R INVx1_ASAP7_75t_SL 1 28.600 7.900 720.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_208 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1278__6783/Y - B->Y F NAND2xp5_ASAP7_75t_L 1 12.600 10.600 730.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_214 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1267__7410/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 17.500 16.200 747.000 + cpu/stage1/stage1_pc4[13] - - F (net) 1 - - - + cpu/stage1/pcselmux/g937__1705/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 15.700 15.400 762.400 + cpu/stage1/stage1_pc_mux_to_pc[13] - - F (net) 2 - - - + cpu/stage1/pcreg/g354__2802/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.900 8.700 771.100 + cpu/stage1/pcreg/n_26 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[13]/D - D R DFFHQNx1_ASAP7_75t_SL 1 53.700 0.100 771.100 +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[13]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 20: MET (21.384 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[12]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[12]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.316 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.684 + Launch Clock:= 0.000 + Data Path:+ 770.300 + Slack:= 21.384 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.600 519.900 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y R AND2x2_ASAP7_75t_L 33 160.100 85.800 605.700 + cpu/stage1/regfile/n_266 - - R (net) 33 - - - + cpu/stage1/regfile/g78480/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 180.100 49.000 654.700 + cpu/stage1/regfile/n_692 - - F (net) 4 - - - + cpu/stage1/regfile/FE_OFC555_n_692/Y - A->Y R INVx1_ASAP7_75t_SL 1 99.800 14.500 669.200 + cpu/stage1/regfile/n_691 - - R (net) 1 - - - + cpu/stage1/regfile/g77829/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 29.200 8.400 677.600 + cpu/stage1/regfile/n_1310 - - F (net) 1 - - - + cpu/stage1/regfile/g77064/Y - B->Y R NAND4xp25_ASAP7_75t_SL 1 16.300 9.800 687.400 + cpu/stage1/regfile/n_2045 - - R (net) 1 - - - + cpu/stage1/regfile/g77002/Y - B->Y F AOI211xp5_ASAP7_75t_SL 1 35.800 17.200 704.600 + cpu/stage1/regfile/n_2107 - - F (net) 1 - - - + cpu/stage1/regfile/g76890__9315/Y - B->Y R OAI211xp5_ASAP7_75t_SL 1 45.100 30.400 735.000 + cpu/stage1/rs2_mux_data[12] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g566__1881/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 108.400 27.800 762.800 + cpu/stage1_rs2[12] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g433__3680/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 16.500 7.500 770.300 + cpu/s1_to_s2_rs2/n_18 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[12]/D - D F DFFHQNx1_ASAP7_75t_SL 1 58.900 0.100 770.300 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[12]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 21: MET (21.521 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[5]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[5]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.979 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.021 + Launch Clock:= 0.000 + Data Path:+ 770.500 + Slack:= 21.521 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 35.500 430.300 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/g80399/Y - A->Y F NOR2x1_ASAP7_75t_SL 9 57.900 48.500 478.800 + cpu/stage1/regfile/n_242 - - F (net) 9 - - - + cpu/stage1/regfile/g79861/Y - A->Y R NAND2xp5_ASAP7_75t_SL 2 79.800 22.500 501.300 + cpu/stage1/regfile/n_275 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC508_n_275/Y - A->Y F INVx1_ASAP7_75t_SL 3 36.200 14.100 515.400 + cpu/stage1/regfile/n_274 - - F (net) 3 - - - + cpu/stage1/regfile/FE_OFC511_n_275/Y - A->Y R INVx1_ASAP7_75t_SL 2 22.900 14.200 529.600 + cpu/stage1/regfile/FE_OFN748_n_275 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC515_n_275/Y - A->Y F INVx1_ASAP7_75t_SL 21 22.000 95.700 625.300 + cpu/stage1/regfile/FE_OFN752_n_275 - - F (net) 21 - - - + cpu/stage1/regfile/g78064/Y - B2->Y R AOI22xp5_ASAP7_75t_SL 1 194.800 33.100 658.400 + cpu/stage1/regfile/n_1075 - - R (net) 1 - - - + cpu/stage1/regfile/g77370/Y - B->Y R AND4x1_ASAP7_75t_SL 1 65.900 24.600 683.000 + cpu/stage1/regfile/n_1770 - - R (net) 1 - - - + cpu/stage1/regfile/g77052/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 12.800 11.900 694.900 + cpu/stage1/regfile/n_2057 - - F (net) 1 - - - + cpu/stage1/regfile/g76974__9315/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 35.200 15.800 710.700 + cpu/stage1/regfile/n_2135 - - R (net) 1 - - - + cpu/stage1/regfile/g76954__2398/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 55.900 27.800 738.500 + cpu/stage1/rs2_mux_data[5] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g549__6417/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 56.100 23.300 761.800 + cpu/stage1_rs2[5] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g424__6417/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.700 8.700 770.500 + cpu/s1_to_s2_rs2/n_27 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[5]/D - D R DFFHQNx1_ASAP7_75t_SL 1 56.100 0.100 770.500 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[5]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 22: MET (21.818 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[13]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[13]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.282 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.718 + Launch Clock:= 0.000 + Data Path:+ 768.900 + Slack:= 21.818 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.600 519.900 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y R AND2x2_ASAP7_75t_L 33 160.100 85.800 605.700 + cpu/stage1/regfile/n_266 - - R (net) 33 - - - + cpu/stage1/regfile/g78480/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 180.100 49.200 654.900 + cpu/stage1/regfile/n_692 - - F (net) 4 - - - + cpu/stage1/regfile/g77148/Y - A2->Y R OAI211xp5_ASAP7_75t_SL 1 99.900 27.800 682.700 + cpu/stage1/regfile/n_1961 - - R (net) 1 - - - + cpu/stage1/regfile/g77063/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 45.000 11.900 694.600 + cpu/stage1/regfile/n_2046 - - F (net) 1 - - - + cpu/stage1/regfile/g76940__6131/Y - B->Y R OAI211xp5_ASAP7_75t_SL 1 41.600 35.600 730.200 + cpu/stage1/rs2_mux_data[13] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g563__8246/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 125.400 29.000 759.200 + cpu/stage1_rs2[13] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g419__9945/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 17.100 9.700 768.900 + cpu/s1_to_s2_rs2/n_32 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[13]/D - D F DFFHQNx1_ASAP7_75t_SL 1 62.700 0.200 768.900 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[13]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 23: MET (21.996 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.504 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.496 + Launch Clock:= 0.000 + Data Path:+ 770.500 + Slack:= 21.996 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.400 394.400 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g390__4733/Y - B->Y R AND2x4_ASAP7_75t_SL 8 14.300 25.400 419.800 + cpu/stage1_inst[16] - - R (net) 8 - - - + cpu/stage1/regfile/FE_OFC1125_stage1_inst_16/Y - A->Y F INVx4_ASAP7_75t_SL 7 30.600 16.200 436.000 + cpu/stage1/regfile/FE_OFN903_stage1_inst_16 - - F (net) 7 - - - + cpu/stage1/regfile/g79850/Y - B->Y F OR2x6_ASAP7_75t_SL 14 32.900 35.300 471.300 + cpu/stage1/regfile/n_292 - - F (net) 14 - - - + cpu/stage1/regfile/g79343/Y - A->Y R INVx4_ASAP7_75t_SL 8 33.300 22.100 493.400 + cpu/stage1/regfile/n_291 - - R (net) 8 - - - + cpu/stage1/regfile/g78473/Y - B->Y R AND2x2_ASAP7_75t_SL 1 39.900 16.900 510.300 + cpu/stage1/regfile/n_701 - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC733_n_701/Y - A->Y F INVx2_ASAP7_75t_SL 2 10.100 11.500 521.800 + cpu/stage1/regfile/n_700 - - F (net) 2 - - - + cpu/stage1/regfile/g77206/Y - B2->Y R OAI22x1_ASAP7_75t_SL 1 16.500 12.200 534.000 + cpu/stage1/regfile/n_1918 - - R (net) 1 - - - + cpu/stage1/regfile/g77078/Y - B->Y F NOR2x1_ASAP7_75t_SL 1 26.100 11.600 545.600 + cpu/stage1/regfile/n_2031 - - F (net) 1 - - - + cpu/stage1/regfile/g76912__6131/Y - B->Y R NAND3x1_ASAP7_75t_SL 1 19.400 21.000 566.600 + cpu/stage1/rs1_mux_data[6] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g561__5122/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 35.500 20.500 587.100 + cpu/stage1_rs1[6] - - R (net) 2 - - - + cpu/stage1/pcadder/g1268__7098/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.000 17.500 604.600 + cpu/stage1/pcadder/n_37 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1448__5122/Y - B->Y F NOR2x1_ASAP7_75t_SL 2 26.300 9.900 614.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_79 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1361__6783/Y - A->Y F OR2x2_ASAP7_75t_SL 2 14.800 16.800 631.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_148 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - A2->Y R OAI21x1_ASAP7_75t_SL 1 10.200 9.700 641.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_176 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y F AOI21x1_ASAP7_75t_SL 3 16.600 10.900 651.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_192 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_OCPC1369_add_18_35_Y_add_17_34_Y_add_16_33_n_192/Y - A->Y F HB1xp67_ASAP7_75t_SL 2 18.400 20.300 672.200 + cpu/stage1/pcadder/FE_OCPN1343_add_18_35_Y_add_17_34_Y_add_16_33_n_192 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1310/Y - A->Y R INVx1_ASAP7_75t_SL 1 18.600 7.400 679.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_193 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1299__5115/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 10.800 11.500 691.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_202 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1290__5122/Y - B->Y R NOR2xp33_ASAP7_75t_SL 2 32.800 21.000 712.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_207 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1273__6260/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 37.600 17.300 729.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_217 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1259__6161/Y - B->Y F XOR2xp5_ASAP7_75t_SL 1 30.000 16.100 745.500 + cpu/stage1/stage1_pc4[14] - - F (net) 1 - - - + cpu/stage1/pcselmux/g935__1617/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 20.000 16.500 762.000 + cpu/stage1/stage1_pc_mux_to_pc[14] - - F (net) 2 - - - + cpu/stage1/pcreg/g357__8246/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 15.300 8.500 770.500 + cpu/stage1/pcreg/n_23 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[14]/D - D R DFFHQNx1_ASAP7_75t_SL 1 53.300 0.000 770.500 +#---------------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 24: MET (22.721 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[3]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[3]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.979 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.021 + Launch Clock:= 0.000 + Data Path:+ 769.300 + Slack:= 22.721 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 35.500 430.300 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/g80399/Y - A->Y F NOR2x1_ASAP7_75t_SL 9 57.900 48.500 478.800 + cpu/stage1/regfile/n_242 - - F (net) 9 - - - + cpu/stage1/regfile/g79861/Y - A->Y R NAND2xp5_ASAP7_75t_SL 2 79.800 22.500 501.300 + cpu/stage1/regfile/n_275 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC508_n_275/Y - A->Y F INVx1_ASAP7_75t_SL 3 36.200 14.100 515.400 + cpu/stage1/regfile/n_274 - - F (net) 3 - - - + cpu/stage1/regfile/FE_OFC511_n_275/Y - A->Y R INVx1_ASAP7_75t_SL 2 22.900 14.200 529.600 + cpu/stage1/regfile/FE_OFN748_n_275 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC515_n_275/Y - A->Y F INVx1_ASAP7_75t_SL 21 22.000 95.800 625.400 + cpu/stage1/regfile/FE_OFN752_n_275 - - F (net) 21 - - - + cpu/stage1/regfile/FE_OFC517_n_275/Y - A->Y F HB1xp67_ASAP7_75t_SL 2 194.800 38.900 664.300 + cpu/stage1/regfile/FE_OFN754_n_275 - - F (net) 2 - - - + cpu/stage1/regfile/g77468/Y - B1->Y R AOI221xp5_ASAP7_75t_SL 1 22.300 15.000 679.300 + cpu/stage1/regfile/n_1668 - - R (net) 1 - - - + cpu/stage1/regfile/g77176/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 45.500 18.800 698.100 + cpu/stage1/regfile/n_1939 - - F (net) 1 - - - + cpu/stage1/regfile/g76976__2883/Y - B->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 38.800 20.900 719.000 + cpu/stage1/regfile/n_2133 - - R (net) 1 - - - + cpu/stage1/regfile/g76913__1881/Y - A->Y F NAND4xp25_ASAP7_75t_SL 1 58.500 20.000 739.000 + cpu/stage1/rs2_mux_data[3] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g551__2398/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 39.700 21.600 760.600 + cpu/stage1_rs2[3] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g423__7410/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.800 8.700 769.300 + cpu/s1_to_s2_rs2/n_28 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[3]/D - D R DFFHQNx1_ASAP7_75t_SL 1 56.100 0.100 769.300 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[3]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 25: MET (23.540 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[10]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[10]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.860 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.140 + Launch Clock:= 0.000 + Data Path:+ 768.600 + Slack:= 23.540 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 35.500 430.300 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/g80399/Y - A->Y F NOR2x1_ASAP7_75t_SL 9 57.900 48.500 478.800 + cpu/stage1/regfile/n_242 - - F (net) 9 - - - + cpu/stage1/regfile/g79861/Y - A->Y R NAND2xp5_ASAP7_75t_SL 2 79.800 22.500 501.300 + cpu/stage1/regfile/n_275 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC508_n_275/Y - A->Y F INVx1_ASAP7_75t_SL 3 36.200 14.100 515.400 + cpu/stage1/regfile/n_274 - - F (net) 3 - - - + cpu/stage1/regfile/FE_OFC511_n_275/Y - A->Y R INVx1_ASAP7_75t_SL 2 22.900 14.200 529.600 + cpu/stage1/regfile/FE_OFN748_n_275 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC515_n_275/Y - A->Y F INVx1_ASAP7_75t_SL 21 22.000 95.400 625.000 + cpu/stage1/regfile/FE_OFN752_n_275 - - F (net) 21 - - - + cpu/stage1/regfile/g78005/Y - A2->Y R AOI22xp5_ASAP7_75t_SL 1 194.800 25.300 650.300 + cpu/stage1/regfile/n_1134 - - R (net) 1 - - - + cpu/stage1/regfile/g77175/Y - B->Y R AND5x1_ASAP7_75t_SL 1 68.800 26.100 676.400 + cpu/stage1/regfile/n_1940 - - R (net) 1 - - - + cpu/stage1/regfile/g76989__3680/Y - A2->Y R OA211x2_ASAP7_75t_SL 1 14.200 17.700 694.100 + cpu/stage1/regfile/n_2120 - - R (net) 1 - - - + cpu/stage1/regfile/g76933__3680/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 15.000 38.700 732.800 + cpu/stage1/rs2_mux_data[10] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g570__6161/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 88.300 27.000 759.800 + cpu/stage1_rs2[10] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g431__5526/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.700 8.800 768.600 + cpu/s1_to_s2_rs2/n_20 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[10]/D - D R DFFHQNx1_ASAP7_75t_SL 1 55.400 0.100 768.600 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[10]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 26: MET (24.143 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[18]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[18]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.657 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.343 + Launch Clock:= 0.000 + Data Path:+ 768.200 + Slack:= 24.143 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1295/Y - A->Y F INVx1_ASAP7_75t_SL 2 47.100 11.000 689.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_203 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1288__1705/Y - B->Y R NOR2xp33_ASAP7_75t_SL 2 21.500 18.300 707.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_209 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1272__5107/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 35.900 15.900 723.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_218 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1258__4733/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 27.700 19.500 743.200 + cpu/stage1/stage1_pc4[18] - - F (net) 1 - - - + cpu/stage1/pcselmux/g950__2346/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 20.700 16.400 759.600 + cpu/stage1/stage1_pc_mux_to_pc[18] - - F (net) 2 - - - + cpu/stage1/pcreg/g359__6131/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 15.200 8.600 768.200 + cpu/stage1/pcreg/n_21 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[18]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.200 0.100 768.200 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[18]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 27: MET (24.886 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[24]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[24]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.714 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.286 + Launch Clock:= 0.000 + Data Path:+ 765.400 + Slack:= 24.886 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.600 519.900 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y R AND2x2_ASAP7_75t_L 33 160.100 85.800 605.700 + cpu/stage1/regfile/n_266 - - R (net) 33 - - - + cpu/stage1/regfile/g78480/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 180.100 47.300 653.000 + cpu/stage1/regfile/n_692 - - F (net) 4 - - - + cpu/stage1/regfile/g77156/Y - A2->Y R OAI211xp5_ASAP7_75t_SL 1 99.400 28.300 681.300 + cpu/stage1/regfile/n_1953 - - R (net) 1 - - - + cpu/stage1/regfile/g77066/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 45.800 14.500 695.800 + cpu/stage1/regfile/n_2043 - - F (net) 1 - - - + cpu/stage1/regfile/g76942__5115/Y - B->Y R OAI211xp5_ASAP7_75t_SL 1 45.600 32.800 728.600 + cpu/stage1/rs2_mux_data[24] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g552__5107/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 116.300 26.700 755.300 + cpu/stage1_rs2[24] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g445__6161/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 14.200 10.100 765.400 + cpu/s1_to_s2_rs2/n_6 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[24]/D - D F DFFHQNx1_ASAP7_75t_SL 1 64.400 0.400 765.400 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[24]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 28: MET (24.943 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[28]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.657 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.343 + Launch Clock:= 0.000 + Data Path:+ 767.400 + Slack:= 24.943 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 30.100 9.500 704.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_20 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1257__7482/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 16.700 16.700 721.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_231 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1256/Y - A->Y F INVx1_ASAP7_75t_SL 2 12.000 7.700 728.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_232 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1248__1705/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 11.600 14.400 743.200 + cpu/stage1/stage1_pc4[28] - - F (net) 1 - - - + cpu/stage1/pcselmux/g944__7482/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 17.900 15.700 758.900 + cpu/stage1/stage1_pc_mux_to_pc[28] - - F (net) 2 - - - + cpu/stage1/pcreg/g367__2883/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 15.100 8.500 767.400 + cpu/stage1/pcreg/n_13 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[28]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.200 0.000 767.400 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[28]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 29: MET (25.159 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.341 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.659 + Launch Clock:= 0.000 + Data Path:+ 766.500 + Slack:= 25.159 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.700 520.000 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 160.100 34.400 554.400 + cpu/stage1/regfile/n_345 - - F (net) 4 - - - + cpu/stage1/regfile/g78528/Y - B->Y R NOR2xp67_ASAP7_75t_SL 12 76.500 105.200 659.600 + cpu/stage1/regfile/n_625 - - R (net) 12 - - - + cpu/stage1/regfile/g77734/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 203.100 21.000 680.600 + cpu/stage1/regfile/n_1406 - - F (net) 1 - - - + cpu/stage1/regfile/g77155/Y - C->Y R NAND3xp33_ASAP7_75t_SL 1 72.700 19.200 699.800 + cpu/stage1/regfile/n_1954 - - R (net) 1 - - - + cpu/stage1/regfile/g77082/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 33.700 12.300 712.100 + cpu/stage1/regfile/n_2027 - - F (net) 1 - - - + cpu/stage1/regfile/g76997__1881/Y - A->Y R NAND5xp2_ASAP7_75t_SL 1 59.600 15.900 728.000 + cpu/stage1/regfile/n_2112 - - R (net) 1 - - - + cpu/stage1/regfile/g76939__7098/Y - B->Y R AO21x1_ASAP7_75t_SL 1 37.300 14.300 742.300 + cpu/stage1/rs2_mux_data[31] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g560__2802/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 19.000 17.200 759.500 + cpu/stage1_rs2[31] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g420__2883/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 14.700 7.000 766.500 + cpu/s1_to_s2_rs2/n_31 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[31]/D - D F DFFHQNx1_ASAP7_75t_SL 1 59.000 0.000 766.500 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[31]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 30: MET (26.496 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[21]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.604 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.396 + Launch Clock:= 0.000 + Data Path:+ 765.900 + Slack:= 26.496 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1280__3680/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_213 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1270__5477/Y - B->Y R NOR2xp33_ASAP7_75t_SL 2 30.200 19.500 714.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_220 - - R (net) 2 - - - + cpu/stage1/pcadder/FE_OFC530_add_18_35_Y_add_17_34_Y_add_16_33_n_220/Y - A->Y F INVx1_ASAP7_75t_SL 1 34.800 5.600 720.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_221 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1261__9945/Y - B->Y R NAND2xp5_ASAP7_75t_L 1 12.900 11.200 731.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_227 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1250__8246/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 1 20.200 13.100 744.300 + cpu/stage1/stage1_pc4[21] - - R (net) 1 - - - + cpu/stage1/pcselmux/g940__7098/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.000 14.400 758.700 + cpu/stage1/stage1_pc_mux_to_pc[21] - - R (net) 2 - - - + cpu/stage1/pcreg/g347__6260/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 17.200 7.200 765.900 + cpu/stage1/pcreg/n_33 - - F (net) 1 - - - + cpu/stage1/pcreg/register_reg[21]/D - D F DFFHQNx1_ASAP7_75t_SL 1 56.100 0.000 765.900 +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[21]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 31: MET (27.021 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[9]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.079 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.921 + Launch Clock:= 0.000 + Data Path:+ 763.900 + Slack:= 27.021 + Timing Path: + +#--------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80394/Y - B->Y F NAND2xp5_ASAP7_75t_SL 3 27.300 13.400 456.800 + cpu/stage1/regfile/n_250 - - F (net) 3 - - - + cpu/stage1/regfile/g79869/Y - A->Y R INVx1_ASAP7_75t_SL 4 24.700 14.600 471.400 + cpu/stage1/regfile/n_249 - - R (net) 4 - - - + cpu/stage1/regfile/g79860/Y - A->Y R AND2x2_ASAP7_75t_SL 27 23.200 91.300 562.700 + cpu/stage1/regfile/n_277 - - R (net) 27 - - - + cpu/stage1/regfile/g79348/Y - A->Y F INVx1_ASAP7_75t_SL 2 189.500 17.400 580.100 + cpu/stage1/regfile/n_276 - - F (net) 2 - - - + cpu/stage1/regfile/g78488/Y - B->Y R NOR2xp33_ASAP7_75t_SL 5 59.600 89.400 669.500 + cpu/stage1/regfile/n_681 - - R (net) 5 - - - + cpu/stage1/regfile/g77264/Y - A1->Y F AOI221xp5_ASAP7_75t_SL 1 182.800 33.200 702.700 + cpu/stage1/regfile/n_1865 - - F (net) 1 - - - + cpu/stage1/regfile/g76891__9945/Y - C->Y R NAND5xp2_ASAP7_75t_SL 1 78.400 30.500 733.200 + cpu/stage1/rs2_mux_data[9] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g572__9945/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 50.700 21.900 755.100 + cpu/stage1_rs2[9] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g429__4319/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 13.800 8.800 763.900 + cpu/s1_to_s2_rs2/n_22 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[9]/D - D F DFFHQNx1_ASAP7_75t_SL 1 61.900 0.200 763.900 +#--------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[9]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 32: MET (27.672 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[4]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[4]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.828 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.172 + Launch Clock:= 0.000 + Data Path:+ 762.500 + Slack:= 27.672 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.400 394.400 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g397__7410/Y - B->Y R AND2x4_ASAP7_75t_SL 44 14.300 75.100 469.500 + cpu/stage1_inst[22] - - R (net) 44 - - - + cpu/stage1/regfile/g80400/Y - B->Y F NOR2xp33_ASAP7_75t_L 10 215.500 131.800 601.300 + cpu/stage1/regfile/n_241 - - F (net) 10 - - - + cpu/stage1/regfile/g78429/Y - A->Y F AND2x2_ASAP7_75t_SL 10 182.900 62.300 663.600 + cpu/stage1/regfile/n_781 - - F (net) 10 - - - + cpu/stage1/regfile/g77671/Y - A2->Y R AOI22xp5_ASAP7_75t_SL 1 48.500 13.400 677.000 + cpu/stage1/regfile/n_1469 - - R (net) 1 - - - + cpu/stage1/regfile/g77107/Y - B->Y R OA211x2_ASAP7_75t_SL 1 24.400 19.100 696.100 + cpu/stage1/regfile/n_2002 - - R (net) 1 - - - + cpu/stage1/regfile/g76955__5107/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 13.400 28.400 724.500 + cpu/stage1/rs2_mux_data[4] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g550__5477/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 70.500 23.300 747.800 + cpu/stage1_rs2[4] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g435__2802/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 11.200 14.700 762.500 + cpu/s1_to_s2_rs2/n_16 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[4]/D - D R DFFHQNx1_ASAP7_75t_SL 1 67.000 0.200 762.500 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[4]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 33: MET (27.913 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[26]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.487 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.513 + Launch Clock:= 0.000 + Data Path:+ 764.600 + Slack:= 27.913 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 30.100 9.500 704.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_20 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1263__2883/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 16.700 19.200 723.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_226 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g2__9945/Y - B->Y F XOR2xp5_ASAP7_75t_SL 1 32.700 16.500 740.100 + cpu/stage1/stage1_pc4[26] - - F (net) 1 - - - + cpu/stage1/pcselmux/g939__8246/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 22.800 16.500 756.600 + cpu/stage1/stage1_pc_mux_to_pc[26] - - F (net) 2 - - - + cpu/stage1/pcreg/g366__9945/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.900 8.000 764.600 + cpu/stage1/pcreg/n_14 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[26]/D - D R DFFHQNx1_ASAP7_75t_SL 1 53.200 0.000 764.600 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[26]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 34: MET (28.026 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.674 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.326 + Launch Clock:= 0.000 + Data Path:+ 764.300 + Slack:= 28.026 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 -0.000 + cpu/s1_to_s2_inst/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_inst/register_reg[2]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_SL 1 0.100 30.000 30.000 + cpu/stage2_inst[2] - - R (net) 1 - - - + cpu/FE_OFC948_stage2_inst_2/Y - A->Y F INVx1_ASAP7_75t_SL 2 13.500 6.400 36.400 + cpu/FE_OFN851_stage2_inst_2 - - F (net) 2 - - - + cpu/FE_OFC952_stage2_inst_2/Y - A->Y R INVx1_ASAP7_75t_SL 13 9.500 29.600 66.000 + cpu/FE_OFN850_stage2_inst_2 - - R (net) 13 - - - + cpu/FE_OFC670_stage2_inst_2/Y - A->Y R BUFx2_ASAP7_75t_SL 9 59.500 25.900 91.900 + cpu/FE_OFN854_stage2_inst_2 - - R (net) 9 - - - + cpu/stage2/alusel/g764/Y - B->Y R OR2x2_ASAP7_75t_SL 3 25.000 15.600 107.500 + cpu/stage2/alusel/n_5 - - R (net) 3 - - - + cpu/stage2/alusel/g759/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 10.800 13.500 121.000 + cpu/stage2/alusel/n_9 - - F (net) 2 - - - + cpu/stage2/alusel/g755/Y - B->Y R NAND2xp5_ASAP7_75t_SL 3 26.600 18.400 139.400 + cpu/stage2/alusel/n_14 - - R (net) 3 - - - + cpu/stage2/alusel/FE_OFC746_n_14/Y - A->Y F INVx1_ASAP7_75t_SL 2 29.400 7.300 146.700 + cpu/stage2/alusel/n_13 - - F (net) 2 - - - + cpu/stage2/alusel/g751/Y - B->Y F AND2x2_ASAP7_75t_SL 3 13.600 15.200 161.900 + cpu/stage2/alusel/n_17 - - F (net) 3 - - - + cpu/stage2/alusel/g746/Y - B1->Y F AO221x1_ASAP7_75t_SL 1 12.100 18.700 180.600 + cpu/stage2/ALUop[1] - - F (net) 1 - - - + cpu/stage2/alu/FE_OFC626_ALUop_1/Y - A->Y R INVx1_ASAP7_75t_SL 5 13.400 21.500 202.100 + cpu/stage2/alu/n_0 - - R (net) 5 - - - + cpu/stage2/alu/FE_OFC627_ALUop_1/Y - A->Y F INVx1_ASAP7_75t_SL 4 37.200 15.600 217.700 + cpu/stage2/alu/FE_OFN823_ALUop_1 - - F (net) 4 - - - + cpu/stage2/alu/g3304/Y - B->Y R NOR2x1_ASAP7_75t_SL 3 25.000 13.200 230.900 + cpu/stage2/alu/n_194 - - R (net) 3 - - - + cpu/stage2/alu/g3302/Y - A->Y R AND3x4_ASAP7_75t_SL 9 23.600 26.700 257.600 + cpu/stage2/alu/n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC775_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 3 29.000 15.400 273.000 + cpu/stage2/alu/FE_OFN922_n_325 - - F (net) 3 - - - + cpu/stage2/alu/FE_OFC778_n_325/Y - A->Y R INVx3_ASAP7_75t_SL 9 24.200 24.000 297.000 + cpu/stage2/alu/FE_OFN925_n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC782_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 7 44.400 41.300 338.300 + cpu/stage2/alu/FE_OFN929_n_325 - - F (net) 7 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1722/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 2 72.200 24.100 362.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_36 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1655/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 45.200 24.300 386.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_116 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A1->Y F OA21x2_ASAP7_75t_SL 3 43.900 22.200 408.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y R OAI321xp33_ASAP7_75t_SL 1 13.300 17.300 426.200 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y F INVx1_ASAP7_75t_SL 2 42.800 11.500 437.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 21.200 19.000 456.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 10.600 16.200 472.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 10.800 9.200 482.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y R OR2x2_ASAP7_75t_SL 3 18.000 17.600 499.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y F AOI31xp67_ASAP7_75t_SL 3 15.800 16.400 516.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 34.100 15.700 531.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y R OR2x2_ASAP7_75t_SL 3 32.100 25.500 557.300 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 27.300 15.500 572.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y F NAND2xp5_ASAP7_75t_L 2 12.900 11.700 584.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 18.800 14.600 599.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 37.100 10.300 609.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y R INVx1_ASAP7_75t_SL 3 20.500 13.500 622.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.500 16.600 639.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 16.200 12.900 652.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 22.100 19.100 671.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 11.700 17.200 688.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 12.100 17.200 705.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1505/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 11.900 14.000 719.900 + cpu/stage2/alu/n_321 - - F (net) 1 - - - + cpu/stage2/alu/g5504/Y - A2->Y F AO21x1_ASAP7_75t_SL 4 18.300 27.900 747.800 + dcache_addr[30] - - F (net) 4 - - - + cpu/stage3/csr/g191/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 32.900 16.500 764.300 + cpu/stage3/csr/n_4 - - R (net) 1 - - - + cpu/stage3/csr/csr_reg[30]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.300 0.500 764.300 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage3/csr/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage3/csr/csr_reg[30]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------------- +Path 35: MET (28.867 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[6]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[6]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.333 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.667 + Launch Clock:= 0.000 + Data Path:+ 761.800 + Slack:= 28.867 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.600 519.900 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y R AND2x2_ASAP7_75t_L 33 160.100 85.800 605.700 + cpu/stage1/regfile/n_266 - - R (net) 33 - - - + cpu/stage1/regfile/g78480/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 180.100 49.100 654.800 + cpu/stage1/regfile/n_692 - - F (net) 4 - - - + cpu/stage1/regfile/g77153/Y - A2->Y R OAI211xp5_ASAP7_75t_SL 1 99.800 28.600 683.400 + cpu/stage1/regfile/n_1956 - - R (net) 1 - - - + cpu/stage1/regfile/g77065/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 46.200 12.600 696.000 + cpu/stage1/regfile/n_2044 - - F (net) 1 - - - + cpu/stage1/regfile/g76941__1881/Y - B->Y R OAI211xp5_ASAP7_75t_SL 1 42.600 29.200 725.200 + cpu/stage1/rs2_mux_data[6] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g561__1705/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 100.400 26.900 752.100 + cpu/stage1_rs2[6] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g426__2398/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 15.700 9.700 761.800 + cpu/s1_to_s2_rs2/n_25 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[6]/D - D F DFFHQNx1_ASAP7_75t_SL 1 62.900 0.300 761.800 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[6]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 36: MET (28.909 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[17]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[17]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.691 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.309 + Launch Clock:= 0.000 + Data Path:+ 763.400 + Slack:= 28.909 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/g392__9315/Y - B->Y F NOR2x2_ASAP7_75t_SL 4 13.500 16.500 401.000 + cpu/stage1/FE_OFN1064_stage1_inst_15 - - F (net) 4 - - - + cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y - A->Y R INVx3_ASAP7_75t_SL 1 31.600 10.900 411.900 + cpu/stage1/regfile/FE_OFN1120_n - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y - A->Y F INVx6_ASAP7_75t_SL 11 17.000 10.800 422.700 + cpu/stage1/regfile/FE_OFN1214_n - - F (net) 11 - - - + cpu/stage1/regfile/g80989/Y - A->Y F AND2x4_ASAP7_75t_SL 5 14.500 21.800 444.500 + cpu/stage1/regfile/n_171 - - F (net) 5 - - - + cpu/stage1/regfile/FE_OFC1149_n_171/Y - A->Y R INVx3_ASAP7_75t_SL 2 20.300 15.300 459.800 + cpu/stage1/regfile/FE_OFN1075_n_171 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC1150_n_171/Y - A->Y F INVx6_ASAP7_75t_SL 13 25.600 12.700 472.500 + cpu/stage1/regfile/FE_OFN1077_n_171 - - F (net) 13 - - - + cpu/stage1/regfile/FE_OFC1152_n_171/Y - A->Y F BUFx6f_ASAP7_75t_SL 10 21.500 18.900 491.400 + cpu/stage1/regfile/FE_OFN1079_n_171 - - F (net) 10 - - - + cpu/stage1/regfile/g78044/Y - B2->Y F AO22x2_ASAP7_75t_SL 1 12.300 16.600 508.000 + cpu/stage1/regfile/n_1095 - - F (net) 1 - - - + cpu/stage1/regfile/g77303/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 9.800 8.400 516.400 + cpu/stage1/regfile/n_1826 - - R (net) 1 - - - + cpu/stage1/regfile/g77043/Y - C->Y F NAND3xp33_ASAP7_75t_SL 1 15.900 13.700 530.100 + cpu/stage1/regfile/n_2066 - - F (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - B->Y R NOR2x1_ASAP7_75t_SL 1 27.400 9.900 540.000 + cpu/stage1/regfile/n_2178 - - R (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y F NAND3x1_ASAP7_75t_SL 1 17.900 13.500 553.500 + cpu/stage1/rs1_mux_data[8] - - F (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 31.400 24.500 578.000 + cpu/stage1_rs1[8] - - F (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 16.400 19.200 597.200 + cpu/stage1/pcadder/n_39 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 3 20.500 11.500 608.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - R (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y F OAI21x1_ASAP7_75t_SL 2 18.100 8.500 617.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 18.300 8.200 625.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 12.800 14.500 639.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y R OA21x2_ASAP7_75t_SL 1 9.700 14.100 654.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y F OAI21x1_ASAP7_75t_SL 3 10.500 19.100 673.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1295/Y - A->Y R INVx1_ASAP7_75t_SL 2 32.600 13.000 686.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_203 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1288__1705/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 20.100 16.500 702.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_209 - - F (net) 2 - - - + cpu/stage1/pcadder/FE_OFC657_add_18_35_Y_add_17_34_Y_add_16_33_n_209/Y - A->Y R INVx1_ASAP7_75t_SL 1 33.300 8.300 710.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_210 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1277__5526/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 13.700 9.000 719.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_215 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1266__1666/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 17.700 16.500 736.400 + cpu/stage1/stage1_pc4[17] - - F (net) 1 - - - + cpu/stage1/pcselmux/g954__5477/Y - A2->Y F AO21x1_ASAP7_75t_L 2 16.700 18.500 754.900 + cpu/stage1/stage1_pc_mux_to_pc[17] - - F (net) 2 - - - + cpu/stage1/pcreg/g358__7098/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.200 8.500 763.400 + cpu/stage1/pcreg/n_22 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[17]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.400 0.100 763.400 +#------------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[17]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 37: MET (29.486 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[0]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[0]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 11.214 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 788.786 + Launch Clock:= 0.000 + Data Path:+ 759.300 + Slack:= 29.486 + Timing Path: + +#--------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80394/Y - B->Y F NAND2xp5_ASAP7_75t_SL 3 27.300 13.400 456.800 + cpu/stage1/regfile/n_250 - - F (net) 3 - - - + cpu/stage1/regfile/g79869/Y - A->Y R INVx1_ASAP7_75t_SL 4 24.700 14.600 471.400 + cpu/stage1/regfile/n_249 - - R (net) 4 - - - + cpu/stage1/regfile/g79860/Y - A->Y R AND2x2_ASAP7_75t_SL 27 23.200 91.300 562.700 + cpu/stage1/regfile/n_277 - - R (net) 27 - - - + cpu/stage1/regfile/g79348/Y - A->Y F INVx1_ASAP7_75t_SL 2 189.500 17.400 580.100 + cpu/stage1/regfile/n_276 - - F (net) 2 - - - + cpu/stage1/regfile/g78488/Y - B->Y R NOR2xp33_ASAP7_75t_SL 5 59.600 89.000 669.100 + cpu/stage1/regfile/n_681 - - R (net) 5 - - - + cpu/stage1/regfile/g77269/Y - A1->Y F AOI221xp5_ASAP7_75t_SL 1 182.800 33.000 702.100 + cpu/stage1/regfile/n_1860 - - F (net) 1 - - - + cpu/stage1/regfile/g76887__7482/Y - C->Y R NAND5xp2_ASAP7_75t_SL 1 78.100 24.100 726.200 + cpu/stage1/rs2_mux_data[0] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g557__6783/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 43.500 22.100 748.300 + cpu/stage1_rs2[0] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g449__2346/Y - B->Y F NOR2xp33_ASAP7_75t_SL 1 15.300 11.000 759.300 + cpu/s1_to_s2_rs2/n_2 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[0]/D - D F DFFHQNx1_ASAP7_75t_SL 1 70.300 0.100 759.300 +#--------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[0]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 38: MET (30.002 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[11]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[11]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.098 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.902 + Launch Clock:= 0.000 + Data Path:+ 761.900 + Slack:= 30.002 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y F NOR2xp33_ASAP7_75t_SL 8 27.300 63.600 507.000 + cpu/stage1/regfile/n_243 - - F (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y F AND2x2_ASAP7_75t_L 33 123.700 108.000 615.000 + cpu/stage1/regfile/n_266 - - F (net) 33 - - - + cpu/stage1/regfile/g77998/Y - B2->Y R AOI22xp5_ASAP7_75t_SL 1 144.100 27.600 642.600 + cpu/stage1/regfile/n_1141 - - R (net) 1 - - - + cpu/stage1/regfile/g77050/Y - C->Y F NAND5xp2_ASAP7_75t_SL 1 64.600 19.200 661.800 + cpu/stage1/regfile/n_2059 - - F (net) 1 - - - + cpu/stage1/regfile/g76972__4733/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 42.900 16.200 678.000 + cpu/stage1/regfile/n_2137 - - R (net) 1 - - - + cpu/stage1/regfile/g76948__2883/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 71.600 47.400 725.400 + cpu/stage1/rs2_mux_data[11] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g567__5115/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 94.700 27.300 752.700 + cpu/stage1_rs2[11] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g432__6783/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.800 9.200 761.900 + cpu/s1_to_s2_rs2/n_19 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[11]/D - D R DFFHQNx1_ASAP7_75t_SL 1 56.800 0.100 761.900 +#---------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[11]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 39: MET (30.675 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.725 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.275 + Launch Clock:= 0.000 + Data Path:+ 761.600 + Slack:= 30.675 + Timing Path: + +#--------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y F NOR2xp33_ASAP7_75t_SL 8 27.300 63.700 507.100 + cpu/stage1/regfile/n_243 - - F (net) 8 - - - + cpu/stage1/regfile/g79809/Y - B->Y R NAND2xp5_ASAP7_75t_SL 4 123.700 44.300 551.400 + cpu/stage1/regfile/n_345 - - R (net) 4 - - - + cpu/stage1/regfile/g78528/Y - B->Y F NOR2xp67_ASAP7_75t_SL 12 70.400 91.300 642.700 + cpu/stage1/regfile/n_625 - - F (net) 12 - - - + cpu/stage1/regfile/g77768/Y - B2->Y R AOI22xp5_ASAP7_75t_SL 1 159.000 29.400 672.100 + cpu/stage1/regfile/n_1372 - - R (net) 1 - - - + cpu/stage1/regfile/g77280/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 56.600 10.100 682.200 + cpu/stage1/regfile/n_1849 - - F (net) 1 - - - + cpu/stage1/regfile/g77105/Y - C->Y R AOI221xp5_ASAP7_75t_SL 1 24.300 15.500 697.700 + cpu/stage1/regfile/n_2004 - - R (net) 1 - - - + cpu/stage1/regfile/g76931__5526/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 47.400 32.700 730.400 + cpu/stage1/rs2_mux_data[27] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g558__3680/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 66.500 23.400 753.800 + cpu/stage1_rs2[27] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g425__5477/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.800 7.800 761.600 + cpu/s1_to_s2_rs2/n_26 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[27]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.600 0.000 761.600 +#--------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 40: MET (31.090 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[25]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[25]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.810 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.190 + Launch Clock:= 0.000 + Data Path:+ 760.100 + Slack:= 31.090 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.400 394.400 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g397__7410/Y - B->Y R AND2x4_ASAP7_75t_SL 44 14.300 75.100 469.500 + cpu/stage1_inst[22] - - R (net) 44 - - - + cpu/stage1/regfile/g80400/Y - B->Y F NOR2xp33_ASAP7_75t_L 10 215.500 131.700 601.200 + cpu/stage1/regfile/n_241 - - F (net) 10 - - - + cpu/stage1/regfile/g78516/Y - A->Y F AND2x2_ASAP7_75t_SL 9 182.800 58.600 659.800 + cpu/stage1/regfile/n_645 - - F (net) 9 - - - + cpu/stage1/regfile/g77788/Y - B2->Y R AOI22xp5_ASAP7_75t_SL 1 42.600 15.400 675.200 + cpu/stage1/regfile/n_1352 - - R (net) 1 - - - + cpu/stage1/regfile/g77061/Y - C->Y R OA211x2_ASAP7_75t_SL 1 25.200 17.100 692.300 + cpu/stage1/regfile/n_2048 - - R (net) 1 - - - + cpu/stage1/regfile/g76935__2802/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 11.700 33.600 725.900 + cpu/stage1/rs2_mux_data[25] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g547__1666/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 75.200 23.700 749.600 + cpu/stage1_rs2[25] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g430__8428/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.200 10.500 760.100 + cpu/s1_to_s2_rs2/n_21 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[25]/D - D R DFFHQNx1_ASAP7_75t_SL 1 61.000 0.300 760.100 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[25]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 41: MET (31.702 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[17]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[17]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.098 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.902 + Launch Clock:= 0.000 + Data Path:+ 760.200 + Slack:= 31.702 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y F NOR2xp33_ASAP7_75t_SL 8 27.300 63.600 507.000 + cpu/stage1/regfile/n_243 - - F (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y F AND2x2_ASAP7_75t_L 33 123.700 109.900 616.900 + cpu/stage1/regfile/n_266 - - F (net) 33 - - - + cpu/stage1/regfile/g77932/Y - B2->Y R AOI22xp5_ASAP7_75t_SL 1 144.200 27.900 644.800 + cpu/stage1/regfile/n_1207 - - R (net) 1 - - - + cpu/stage1/regfile/g77048/Y - C->Y F NAND5xp2_ASAP7_75t_SL 1 64.900 18.500 663.300 + cpu/stage1/regfile/n_2061 - - F (net) 1 - - - + cpu/stage1/regfile/g76970__5115/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 41.700 16.300 679.600 + cpu/stage1/regfile/n_2139 - - R (net) 1 - - - + cpu/stage1/regfile/g76946__9315/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 72.200 46.100 725.700 + cpu/stage1/rs2_mux_data[17] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g553__6260/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 90.100 25.700 751.400 + cpu/stage1_rs2[17] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g438__8246/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 13.100 8.800 760.200 + cpu/s1_to_s2_rs2/n_13 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[17]/D - D R DFFHQNx1_ASAP7_75t_SL 1 56.800 0.100 760.200 +#---------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[17]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 42: MET (32.115 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[21]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.284 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.716 + Launch Clock:= 0.000 + Data Path:+ 759.600 + Slack:= 32.115 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y F NOR2xp33_ASAP7_75t_SL 8 27.300 63.600 507.000 + cpu/stage1/regfile/n_243 - - F (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y F AND2x2_ASAP7_75t_L 33 123.700 102.700 609.700 + cpu/stage1/regfile/n_266 - - F (net) 33 - - - + cpu/stage1/regfile/g77541/Y - A1->Y R AOI222xp33_ASAP7_75t_SL 1 143.100 34.900 644.600 + cpu/stage1/regfile/n_1595 - - R (net) 1 - - - + cpu/stage1/regfile/g77224/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 67.700 18.900 663.500 + cpu/stage1/regfile/n_1900 - - F (net) 1 - - - + cpu/stage1/regfile/g77018/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 40.900 14.400 677.900 + cpu/stage1/regfile/n_2091 - - R (net) 1 - - - + cpu/stage1/regfile/g76916__4733/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 64.900 46.900 724.800 + cpu/stage1/rs2_mux_data[21] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g569__4733/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 94.500 25.600 750.400 + cpu/stage1_rs2[21] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g442__5115/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.800 9.200 759.600 + cpu/s1_to_s2_rs2/n_9 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[21]/D - D R DFFHQNx1_ASAP7_75t_SL 1 57.900 0.100 759.600 +#---------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[21]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 43: MET (32.589 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[18]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[18]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.911 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.089 + Launch Clock:= 0.000 + Data Path:+ 759.500 + Slack:= 32.589 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y F NOR2xp33_ASAP7_75t_SL 8 27.300 63.600 507.000 + cpu/stage1/regfile/n_243 - - F (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y F AND2x2_ASAP7_75t_L 33 123.700 107.200 614.200 + cpu/stage1/regfile/n_266 - - F (net) 33 - - - + cpu/stage1/regfile/g77510/Y - A1->Y R AOI222xp33_ASAP7_75t_SL 1 143.600 35.100 649.300 + cpu/stage1/regfile/n_1626 - - R (net) 1 - - - + cpu/stage1/regfile/g77221/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 68.100 20.700 670.000 + cpu/stage1/regfile/n_1903 - - F (net) 1 - - - + cpu/stage1/regfile/g77017/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 43.800 15.600 685.600 + cpu/stage1/regfile/n_2092 - - R (net) 1 - - - + cpu/stage1/regfile/g76915__7482/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 70.000 41.400 727.000 + cpu/stage1/rs2_mux_data[18] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g548__7410/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 81.400 24.300 751.300 + cpu/stage1_rs2[18] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g439__7098/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.300 8.200 759.500 + cpu/s1_to_s2_rs2/n_12 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[18]/D - D R DFFHQNx1_ASAP7_75t_SL 1 55.700 0.100 759.500 +#---------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[18]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 44: MET (33.726 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[23]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.674 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.326 + Launch Clock:= 0.000 + Data Path:+ 758.600 + Slack:= 33.726 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.400 394.400 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g397__7410/Y - B->Y R AND2x4_ASAP7_75t_SL 44 14.300 75.100 469.500 + cpu/stage1_inst[22] - - R (net) 44 - - - + cpu/stage1/regfile/g80400/Y - B->Y F NOR2xp33_ASAP7_75t_L 10 215.500 131.300 600.800 + cpu/stage1/regfile/n_241 - - F (net) 10 - - - + cpu/stage1/regfile/g78430/Y - A->Y F AND2x2_ASAP7_75t_SL 10 182.800 61.200 662.000 + cpu/stage1/regfile/n_780 - - F (net) 10 - - - + cpu/stage1/regfile/g77803/Y - B2->Y R AOI22xp5_ASAP7_75t_SL 1 45.700 16.000 678.000 + cpu/stage1/regfile/n_1337 - - R (net) 1 - - - + cpu/stage1/regfile/g76998__5115/Y - B->Y R AND5x1_ASAP7_75t_SL 1 26.400 22.300 700.300 + cpu/stage1/regfile/n_2111 - - R (net) 1 - - - + cpu/stage1/regfile/g76936__1705/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 15.700 28.200 728.500 + cpu/stage1/rs2_mux_data[23] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g559__1617/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 61.500 22.500 751.000 + cpu/stage1_rs2[23] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g444__4733/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.300 7.600 758.600 + cpu/s1_to_s2_rs2/n_7 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[23]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.300 0.000 758.600 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[23]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 45: MET (34.408 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/register_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 6.792 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 793.208 + Launch Clock:= 0.000 + Data Path:+ 758.800 + Slack:= 34.408 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 0.000 + cpu/s1_to_s2_inst/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_inst/register_reg[2]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_SL 1 0.100 30.000 30.000 + cpu/stage2_inst[2] - - R (net) 1 - - - + cpu/FE_OFC948_stage2_inst_2/Y - A->Y F INVx1_ASAP7_75t_SL 2 13.500 6.400 36.400 + cpu/FE_OFN851_stage2_inst_2 - - F (net) 2 - - - + cpu/FE_OFC952_stage2_inst_2/Y - A->Y R INVx1_ASAP7_75t_SL 13 9.500 29.600 66.000 + cpu/FE_OFN850_stage2_inst_2 - - R (net) 13 - - - + cpu/FE_OFC670_stage2_inst_2/Y - A->Y R BUFx2_ASAP7_75t_SL 9 59.500 25.900 91.900 + cpu/FE_OFN854_stage2_inst_2 - - R (net) 9 - - - + cpu/stage2/alusel/g764/Y - B->Y R OR2x2_ASAP7_75t_SL 3 25.000 15.600 107.500 + cpu/stage2/alusel/n_5 - - R (net) 3 - - - + cpu/stage2/alusel/g759/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 10.800 13.500 121.000 + cpu/stage2/alusel/n_9 - - F (net) 2 - - - + cpu/stage2/alusel/g755/Y - B->Y R NAND2xp5_ASAP7_75t_SL 3 26.600 18.400 139.400 + cpu/stage2/alusel/n_14 - - R (net) 3 - - - + cpu/stage2/alusel/FE_OFC746_n_14/Y - A->Y F INVx1_ASAP7_75t_SL 2 29.400 7.300 146.700 + cpu/stage2/alusel/n_13 - - F (net) 2 - - - + cpu/stage2/alusel/g751/Y - B->Y F AND2x2_ASAP7_75t_SL 3 13.600 15.200 161.900 + cpu/stage2/alusel/n_17 - - F (net) 3 - - - + cpu/stage2/alusel/g746/Y - B1->Y F AO221x1_ASAP7_75t_SL 1 12.100 18.700 180.600 + cpu/stage2/ALUop[1] - - F (net) 1 - - - + cpu/stage2/alu/FE_OFC626_ALUop_1/Y - A->Y R INVx1_ASAP7_75t_SL 5 13.400 21.500 202.100 + cpu/stage2/alu/n_0 - - R (net) 5 - - - + cpu/stage2/alu/FE_OFC627_ALUop_1/Y - A->Y F INVx1_ASAP7_75t_SL 4 37.200 15.600 217.700 + cpu/stage2/alu/FE_OFN823_ALUop_1 - - F (net) 4 - - - + cpu/stage2/alu/g3304/Y - B->Y R NOR2x1_ASAP7_75t_SL 3 25.000 13.200 230.900 + cpu/stage2/alu/n_194 - - R (net) 3 - - - + cpu/stage2/alu/g3302/Y - A->Y R AND3x4_ASAP7_75t_SL 9 23.600 26.700 257.600 + cpu/stage2/alu/n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC775_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 3 29.000 15.400 273.000 + cpu/stage2/alu/FE_OFN922_n_325 - - F (net) 3 - - - + cpu/stage2/alu/FE_OFC778_n_325/Y - A->Y R INVx3_ASAP7_75t_SL 9 24.200 24.000 297.000 + cpu/stage2/alu/FE_OFN925_n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC782_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 7 44.400 41.300 338.300 + cpu/stage2/alu/FE_OFN929_n_325 - - F (net) 7 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1722/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 2 72.200 24.100 362.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_36 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1655/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 45.200 24.300 386.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_116 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A1->Y F OA21x2_ASAP7_75t_SL 3 43.900 22.200 408.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y R OAI321xp33_ASAP7_75t_SL 1 13.300 17.300 426.200 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y F INVx1_ASAP7_75t_SL 2 42.800 11.500 437.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 21.200 19.000 456.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 10.600 16.200 472.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 10.800 9.200 482.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y R OR2x2_ASAP7_75t_SL 3 18.000 17.600 499.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y F AOI31xp67_ASAP7_75t_SL 3 15.800 16.400 516.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 34.100 15.700 531.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y R OR2x2_ASAP7_75t_SL 3 32.100 25.500 557.300 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 27.300 15.500 572.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y F NAND2xp5_ASAP7_75t_L 2 12.900 11.700 584.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 18.800 14.600 599.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 37.100 10.300 609.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y R INVx1_ASAP7_75t_SL 3 20.500 13.500 622.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.500 16.600 639.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 16.200 12.900 652.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 22.100 19.100 671.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 11.700 17.200 688.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 12.100 17.200 705.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1505/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 11.900 14.000 719.900 + cpu/stage2/alu/n_321 - - F (net) 1 - - - + cpu/stage2/alu/g5504/Y - A2->Y F AO21x1_ASAP7_75t_SL 4 18.300 27.700 747.600 + dcache_addr[30] - - F (net) 4 - - - + cpu/s2_to_s3_alu/g434__7098/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 32.800 11.200 758.800 + cpu/s2_to_s3_alu/n_17 - - R (net) 1 - - - + cpu/s2_to_s3_alu/register_reg[30]/D - D R DFFHQNx1_ASAP7_75t_SL 1 49.100 0.000 758.800 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s2_to_s3_alu/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s2_to_s3_alu/register_reg[30]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 46: MET (37.519 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[29]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.081 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.919 + Launch Clock:= 0.000 + Data Path:+ 754.400 + Slack:= 37.519 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 0.000 + cpu/s1_to_s2_inst/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_inst/register_reg[2]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_SL 1 0.100 30.000 30.000 + cpu/stage2_inst[2] - - R (net) 1 - - - + cpu/FE_OFC948_stage2_inst_2/Y - A->Y F INVx1_ASAP7_75t_SL 2 13.500 6.400 36.400 + cpu/FE_OFN851_stage2_inst_2 - - F (net) 2 - - - + cpu/FE_OFC952_stage2_inst_2/Y - A->Y R INVx1_ASAP7_75t_SL 13 9.500 29.600 66.000 + cpu/FE_OFN850_stage2_inst_2 - - R (net) 13 - - - + cpu/FE_OFC670_stage2_inst_2/Y - A->Y R BUFx2_ASAP7_75t_SL 9 59.500 25.900 91.900 + cpu/FE_OFN854_stage2_inst_2 - - R (net) 9 - - - + cpu/stage2/alusel/g764/Y - B->Y R OR2x2_ASAP7_75t_SL 3 25.000 15.600 107.500 + cpu/stage2/alusel/n_5 - - R (net) 3 - - - + cpu/stage2/alusel/g759/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 10.800 13.500 121.000 + cpu/stage2/alusel/n_9 - - F (net) 2 - - - + cpu/stage2/alusel/g755/Y - B->Y R NAND2xp5_ASAP7_75t_SL 3 26.600 18.400 139.400 + cpu/stage2/alusel/n_14 - - R (net) 3 - - - + cpu/stage2/alusel/FE_OFC746_n_14/Y - A->Y F INVx1_ASAP7_75t_SL 2 29.400 7.300 146.700 + cpu/stage2/alusel/n_13 - - F (net) 2 - - - + cpu/stage2/alusel/g751/Y - B->Y F AND2x2_ASAP7_75t_SL 3 13.600 15.200 161.900 + cpu/stage2/alusel/n_17 - - F (net) 3 - - - + cpu/stage2/alusel/g746/Y - B1->Y F AO221x1_ASAP7_75t_SL 1 12.100 18.700 180.600 + cpu/stage2/ALUop[1] - - F (net) 1 - - - + cpu/stage2/alu/FE_OFC626_ALUop_1/Y - A->Y R INVx1_ASAP7_75t_SL 5 13.400 21.500 202.100 + cpu/stage2/alu/n_0 - - R (net) 5 - - - + cpu/stage2/alu/FE_OFC627_ALUop_1/Y - A->Y F INVx1_ASAP7_75t_SL 4 37.200 15.600 217.700 + cpu/stage2/alu/FE_OFN823_ALUop_1 - - F (net) 4 - - - + cpu/stage2/alu/g3304/Y - B->Y R NOR2x1_ASAP7_75t_SL 3 25.000 13.200 230.900 + cpu/stage2/alu/n_194 - - R (net) 3 - - - + cpu/stage2/alu/g3302/Y - A->Y R AND3x4_ASAP7_75t_SL 9 23.600 26.700 257.600 + cpu/stage2/alu/n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC775_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 3 29.000 15.400 273.000 + cpu/stage2/alu/FE_OFN922_n_325 - - F (net) 3 - - - + cpu/stage2/alu/FE_OFC778_n_325/Y - A->Y R INVx3_ASAP7_75t_SL 9 24.200 24.000 297.000 + cpu/stage2/alu/FE_OFN925_n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC782_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 7 44.400 41.300 338.300 + cpu/stage2/alu/FE_OFN929_n_325 - - F (net) 7 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1722/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 2 72.200 24.100 362.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_36 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1655/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 45.200 24.300 386.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_116 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A1->Y F OA21x2_ASAP7_75t_SL 3 43.900 22.200 408.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y R OAI321xp33_ASAP7_75t_SL 1 13.300 17.300 426.200 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y F INVx1_ASAP7_75t_SL 2 42.800 11.500 437.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 21.200 19.000 456.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 10.600 16.200 472.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 10.800 9.200 482.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y R OR2x2_ASAP7_75t_SL 3 18.000 17.600 499.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y F AOI31xp67_ASAP7_75t_SL 3 15.800 16.400 516.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 34.100 15.700 531.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y R OR2x2_ASAP7_75t_SL 3 32.100 25.500 557.300 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 27.300 15.500 572.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y F NAND2xp5_ASAP7_75t_L 2 12.900 11.700 584.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 18.800 14.600 599.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 37.100 10.300 609.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y R INVx1_ASAP7_75t_SL 3 20.500 13.500 622.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.500 16.600 639.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 16.200 12.900 652.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 22.100 19.100 671.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 11.700 17.200 688.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1508/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 12.100 14.100 702.800 + cpu/stage2/alu/n_320 - - F (net) 1 - - - + cpu/stage2/alu/g5506/Y - A2->Y F AO21x1_ASAP7_75t_L 4 18.300 32.900 735.700 + dcache_addr[29] - - F (net) 4 - - - + cpu/stage3/csr/g164/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 36.300 18.700 754.400 + cpu/stage3/csr/n_31 - - R (net) 1 - - - + cpu/stage3/csr/csr_reg[29]/D - D R DFFHQNx1_ASAP7_75t_SL 1 56.700 0.800 754.400 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage3/csr/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage3/csr/csr_reg[29]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------------- +Path 47: MET (38.330 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.570 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.430 + Launch Clock:= 0.000 + Data Path:+ 753.100 + Slack:= 38.330 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.700 520.000 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 160.100 34.400 554.400 + cpu/stage1/regfile/n_345 - - F (net) 4 - - - + cpu/stage1/regfile/g78531/Y - B->Y R NOR2xp67_ASAP7_75t_SL 12 76.500 102.200 656.600 + cpu/stage1/regfile/n_622 - - R (net) 12 - - - + cpu/stage1/regfile/g77587/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 195.400 19.800 676.400 + cpu/stage1/regfile/n_1549 - - F (net) 1 - - - + cpu/stage1/regfile/g77262/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 69.500 18.200 694.600 + cpu/stage1/regfile/n_1867 - - R (net) 1 - - - + cpu/stage1/regfile/g77096/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 30.200 10.500 705.100 + cpu/stage1/regfile/n_2013 - - F (net) 1 - - - + cpu/stage1/regfile/g76938__8246/Y - B->Y R NAND5xp2_ASAP7_75t_SL 1 49.700 19.000 724.100 + cpu/stage1/rs2_mux_data[15] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g545__2883/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 38.900 21.200 745.300 + cpu/stage1_rs2[15] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g450__1666/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 16.400 7.800 753.100 + cpu/s1_to_s2_rs2/n_1 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[15]/D - D F DFFHQNx1_ASAP7_75t_SL 1 59.900 0.100 753.100 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[15]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 48: MET (38.906 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[28]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.494 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.506 + Launch Clock:= 0.000 + Data Path:+ 752.600 + Slack:= 38.906 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.700 520.000 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 160.100 34.400 554.400 + cpu/stage1/regfile/n_345 - - F (net) 4 - - - + cpu/stage1/regfile/g78531/Y - B->Y R NOR2xp67_ASAP7_75t_SL 12 76.500 99.800 654.200 + cpu/stage1/regfile/n_622 - - R (net) 12 - - - + cpu/stage1/regfile/g77762/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 195.500 19.600 673.800 + cpu/stage1/regfile/n_1378 - - F (net) 1 - - - + cpu/stage1/regfile/g77279/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 69.400 21.100 694.900 + cpu/stage1/regfile/n_1850 - - R (net) 1 - - - + cpu/stage1/regfile/g77103/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 33.700 10.700 705.600 + cpu/stage1/regfile/n_2006 - - F (net) 1 - - - + cpu/stage1/regfile/g76888__4733/Y - B->Y R NAND5xp2_ASAP7_75t_SL 1 49.600 19.400 725.000 + cpu/stage1/rs2_mux_data[28] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g546__2346/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 44.300 20.300 745.300 + cpu/stage1_rs2[28] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g447__9945/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 14.000 7.300 752.600 + cpu/s1_to_s2_rs2/n_4 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[28]/D - D F DFFHQNx1_ASAP7_75t_SL 1 59.600 0.100 752.600 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[28]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 49: MET (43.699 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.301 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.699 + Launch Clock:= 0.000 + Data Path:+ 748.000 + Slack:= 43.699 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.400 394.400 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g397__7410/Y - B->Y R AND2x4_ASAP7_75t_SL 44 14.300 75.100 469.500 + cpu/stage1_inst[22] - - R (net) 44 - - - + cpu/stage1/regfile/g80400/Y - B->Y F NOR2xp33_ASAP7_75t_L 10 215.500 131.300 600.800 + cpu/stage1/regfile/n_241 - - F (net) 10 - - - + cpu/stage1/regfile/g78430/Y - A->Y F AND2x2_ASAP7_75t_SL 10 182.800 63.500 664.300 + cpu/stage1/regfile/n_780 - - F (net) 10 - - - + cpu/stage1/regfile/g77415/Y - C1->Y R AOI222xp33_ASAP7_75t_SL 1 46.000 18.500 682.800 + cpu/stage1/regfile/n_1725 - - R (net) 1 - - - + cpu/stage1/regfile/g76947__9945/Y - C->Y F NAND5xp2_ASAP7_75t_SL 1 34.500 30.000 712.800 + cpu/stage1/rs2_mux_data[14] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g576__7410/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 70.300 25.500 738.300 + cpu/stage1_rs2[14] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g437__5122/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 15.000 9.700 748.000 + cpu/s1_to_s2_rs2/n_14 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[14]/D - D R DFFHQNx1_ASAP7_75t_SL 1 58.000 0.100 748.000 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 50: MET (43.943 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[25]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[25]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.757 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.243 + Launch Clock:= 0.000 + Data Path:+ 748.300 + Slack:= 43.943 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1264__2346/Y - A1->Y R OAI21xp5_ASAP7_75t_L 1 30.100 16.100 711.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_225 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1252__7098/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 1 26.800 14.500 725.500 + cpu/stage1/stage1_pc4[25] - - R (net) 1 - - - + cpu/stage1/pcselmux/g946__6161/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 25.200 15.100 740.600 + cpu/stage1/stage1_pc_mux_to_pc[25] - - R (net) 2 - - - + cpu/stage1/pcreg/g353__1617/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 17.800 7.700 748.300 + cpu/stage1/pcreg/n_27 - - F (net) 1 - - - + cpu/stage1/pcreg/register_reg[25]/D - D F DFFHQNx1_ASAP7_75t_SL 1 56.700 0.100 748.300 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[25]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- + diff --git a/build/par-rundir/timingReports/riscv_top_preCTS_default.tarpt b/build/par-rundir/timingReports/riscv_top_preCTS_default.tarpt new file mode 100644 index 0000000..37952e6 --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_preCTS_default.tarpt @@ -0,0 +1,2681 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 21:52:30 2020 +# Design: riscv_top +# Command: place_opt_design +############################################################### +Path 1: MET (207.518 ps) Setup Check with Pin mem/dcache/STATE_reg[1]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) mem_resp_tag[1] + Clock: (R) clk + Endpoint: (R) mem/dcache/STATE_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 5.282 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 794.718 + Launch Clock:= 0.000 + Input Delay:+ 180.000 + Data Path:+ 407.200 + Slack:= 207.518 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------- + mem_resp_tag[1] - mem_resp_tag[1] F (arrival) 1 4.000 0.100 180.100 + mem_resp_tag[1] - - F (net) 1 - - - + mem/arbiter/g295/Y - D->Y R NOR4xp25_ASAP7_75t_SL 2 4.000 28.500 208.600 + mem/arbiter/n_2 - - R (net) 2 - - - + mem/arbiter/g293/Y - A->Y R AND3x1_ASAP7_75t_SL 8 56.600 45.100 253.700 + mem/ic_mem_resp_valid - - R (net) 8 - - - + mem/icache/g8840/Y - A1->Y R AO21x1_ASAP7_75t_SL 31 60.300 104.600 358.300 + mem/ic_mem_req_valid - - R (net) 31 - - - + mem/FE_DBTC0_ic_mem_req_valid/Y - A->Y F INVx1_ASAP7_75t_SL 12 227.500 55.200 413.500 + FE_OFN1444_mem_req_tag_0 - - F (net) 12 - - - + mem/arbiter/FE_OFC98_mem_req_tag_0/Y - A->Y F HB1xp67_ASAP7_75t_SL 19 107.500 79.600 493.100 + mem/arbiter/FE_OFN98_mem_req_tag_0 - - F (net) 19 - - - + mem/arbiter/g539/Y - A->Y F AND2x2_ASAP7_75t_SL 3 113.700 36.400 529.500 + mem/dc_mem_req_ready - - F (net) 3 - - - + mem/dcache/g13751/Y - C->Y R NAND3x1_ASAP7_75t_SL 4 17.300 28.400 557.900 + mem/dc_mem_req_rw - - R (net) 4 - - - + mem/dcache/g13730/Y - B->Y F NAND2xp5_ASAP7_75t_SL 2 59.100 14.300 572.200 + mem/dcache/n_314 - - F (net) 2 - - - + mem/dcache/g11166/Y - B->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 29.900 15.000 587.200 + mem/dcache/n_81 - - R (net) 1 - - - + mem/dcache/STATE_reg[1]/D - D R DFFHQNx1_ASAP7_75t_SL 1 40.200 0.100 587.200 +#---------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#--------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 900.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[1]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 3 0.100 0.000 900.000 +#--------------------------------------------------------------------------------------------------------------------------------------- +Path 2: MET (215.154 ps) Clock Gating Setup Check with Pin mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) mem_resp_tag[1] + Clock: (R) clk + Endpoint: (F) mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 36.646 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 763.354 + Launch Clock:= 0.000 + Input Delay:+ 180.000 + Data Path:+ 368.200 + Slack:= 215.154 + Timing Path: + +#--------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------------------- + mem_resp_tag[1] - mem_resp_tag[1] F (arrival) 1 4.000 0.100 180.100 + mem_resp_tag[1] - - F (net) 1 - - - + mem/arbiter/g295/Y - D->Y R NOR4xp25_ASAP7_75t_SL 2 4.000 28.500 208.600 + mem/arbiter/n_2 - - R (net) 2 - - - + mem/arbiter/g293/Y - A->Y R AND3x1_ASAP7_75t_SL 8 56.600 45.100 253.700 + mem/ic_mem_resp_valid - - R (net) 8 - - - + mem/icache/g8840/Y - A1->Y R AO21x1_ASAP7_75t_SL 31 60.300 104.600 358.300 + mem/ic_mem_req_valid - - R (net) 31 - - - + mem/FE_DBTC0_ic_mem_req_valid/Y - A->Y F INVx1_ASAP7_75t_SL 12 227.500 55.200 413.500 + FE_OFN1444_mem_req_tag_0 - - F (net) 12 - - - + mem/arbiter/FE_OFC98_mem_req_tag_0/Y - A->Y F HB1xp67_ASAP7_75t_SL 19 107.500 79.600 493.100 + mem/arbiter/FE_OFN98_mem_req_tag_0 - - F (net) 19 - - - + mem/arbiter/g539/Y - A->Y F AND2x2_ASAP7_75t_SL 3 113.700 36.400 529.500 + mem/dc_mem_req_ready - - F (net) 3 - - - + mem/dcache/g13992/Y - B->Y R OAI21xp5_ASAP7_75t_SL 1 17.300 8.800 538.300 + mem/dcache/n_101 - - R (net) 1 - - - + mem/dcache/g13600/Y - A2->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 28.100 9.900 548.200 + mem/dcache/n_323 - - F (net) 1 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ENA - ENA F ICGx1_ASAP7_75t_R 1 22.200 0.000 548.200 +#--------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#---------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#---------------------------------------------------------------------------------------------------------------------------- +Path 3: MET (218.245 ps) Setup Check with Pin mem/dcache/STATE_reg[2]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (F) mem_resp_tag[1] + Clock: (R) clk + Endpoint: (R) mem/dcache/STATE_reg[2]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 5.354 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 794.646 + Launch Clock:= 0.000 + Input Delay:+ 180.000 + Data Path:+ 396.400 + Slack:= 218.245 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------- + mem_resp_tag[1] - mem_resp_tag[1] F (arrival) 1 4.000 0.100 180.100 + mem_resp_tag[1] - - F (net) 1 - - - + mem/arbiter/g295/Y - D->Y R NOR4xp25_ASAP7_75t_SL 2 4.000 28.500 208.600 + mem/arbiter/n_2 - - R (net) 2 - - - + mem/arbiter/g293/Y - A->Y R AND3x1_ASAP7_75t_SL 8 56.600 45.100 253.700 + mem/ic_mem_resp_valid - - R (net) 8 - - - + mem/icache/g8840/Y - A1->Y R AO21x1_ASAP7_75t_SL 31 60.300 104.600 358.300 + mem/ic_mem_req_valid - - R (net) 31 - - - + mem/FE_DBTC0_ic_mem_req_valid/Y - A->Y F INVx1_ASAP7_75t_SL 12 227.500 55.200 413.500 + FE_OFN1444_mem_req_tag_0 - - F (net) 12 - - - + mem/arbiter/FE_OFC98_mem_req_tag_0/Y - A->Y F HB1xp67_ASAP7_75t_SL 19 107.500 79.600 493.100 + mem/arbiter/FE_OFN98_mem_req_tag_0 - - F (net) 19 - - - + mem/arbiter/g539/Y - A->Y F AND2x2_ASAP7_75t_SL 3 113.700 36.400 529.500 + mem/dc_mem_req_ready - - F (net) 3 - - - + mem/dcache/g13751/Y - C->Y R NAND3x1_ASAP7_75t_SL 4 17.300 28.400 557.900 + mem/dc_mem_req_rw - - R (net) 4 - - - + mem/dcache/FE_OFC439_dc_mem_req_rw/Y - A->Y F INVx1_ASAP7_75t_SL 1 59.100 6.300 564.200 + mem/dcache/n_2 - - F (net) 1 - - - + mem/dcache/g11190/Y - B->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 19.100 12.200 576.400 + mem/dcache/n_57 - - R (net) 1 - - - + mem/dcache/STATE_reg[2]/D - D R DFFHQNx1_ASAP7_75t_SL 1 38.700 0.000 576.400 +#---------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#--------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 900.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[2]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 3 0.100 0.000 900.000 +#--------------------------------------------------------------------------------------------------------------------------------------- +Path 4: MET (339.161 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[10][27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[10][27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.439 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.561 + Launch Clock:= 0.000 + Data Path:+ 441.400 + Slack:= 339.161 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.800 355.000 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81787/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.900 86.400 441.400 + cpu/stage1/regfile/n_42 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[10][27]/D - D R DFFHQNx1_ASAP7_75t_SL 10 131.500 2.300 441.400 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10123 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[10][27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 5: MET (339.261 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[19][27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[19][27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.439 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.561 + Launch Clock:= 0.000 + Data Path:+ 441.300 + Slack:= 339.261 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.800 355.000 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81787/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.900 86.300 441.300 + cpu/stage1/regfile/n_42 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[19][27]/D - D R DFFHQNx1_ASAP7_75t_SL 10 131.500 2.200 441.300 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10150 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[19][27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 6: MET (339.375 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[30][27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[30][27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.424 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.576 + Launch Clock:= 0.000 + Data Path:+ 441.200 + Slack:= 339.375 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.800 355.000 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81787/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.900 86.200 441.200 + cpu/stage1/regfile/n_42 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[30][27]/D - D R DFFHQNx1_ASAP7_75t_SL 10 131.400 2.100 441.200 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10183 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[30][27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 7: MET (339.375 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[11][27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[11][27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.424 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.576 + Launch Clock:= 0.000 + Data Path:+ 441.200 + Slack:= 339.375 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.800 355.000 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81787/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.900 86.200 441.200 + cpu/stage1/regfile/n_42 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[11][27]/D - D R DFFHQNx1_ASAP7_75t_SL 10 131.400 2.100 441.200 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10126 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[11][27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 8: MET (339.475 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[15][27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[15][27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.424 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.576 + Launch Clock:= 0.000 + Data Path:+ 441.100 + Slack:= 339.475 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.800 355.000 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81787/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.900 86.100 441.100 + cpu/stage1/regfile/n_42 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[15][27]/D - D R DFFHQNx1_ASAP7_75t_SL 10 131.400 2.000 441.100 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10138 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[15][27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 9: MET (339.790 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[25][27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[25][27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.410 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.590 + Launch Clock:= 0.000 + Data Path:+ 440.800 + Slack:= 339.790 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.800 355.000 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81787/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.900 85.800 440.800 + cpu/stage1/regfile/n_42 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[25][27]/D - D R DFFHQNx1_ASAP7_75t_SL 10 131.300 1.700 440.800 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10168 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[25][27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 10: MET (339.890 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[16][27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[16][27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.410 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.590 + Launch Clock:= 0.000 + Data Path:+ 440.700 + Slack:= 339.890 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.800 355.000 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81787/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.900 85.700 440.700 + cpu/stage1/regfile/n_42 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[16][27]/D - D R DFFHQNx1_ASAP7_75t_SL 10 131.300 1.600 440.700 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10141 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[16][27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 11: MET (340.519 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[30][8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[30][8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.281 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.719 + Launch Clock:= 0.000 + Data Path:+ 440.200 + Slack:= 340.519 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.500 354.700 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81668/Y - A->Y R NAND2xp5_ASAP7_75t_SL 9 201.900 85.500 440.200 + cpu/stage1/regfile/n_63 - - R (net) 9 - - - + cpu/stage1/regfile/mem_reg[30][8]/D - D R DFFHQNx1_ASAP7_75t_SL 9 130.400 2.000 440.200 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10183 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[30][8]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 12: MET (340.519 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[15][8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[15][8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.281 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.719 + Launch Clock:= 0.000 + Data Path:+ 440.200 + Slack:= 340.519 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.500 354.700 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81668/Y - A->Y R NAND2xp5_ASAP7_75t_SL 9 201.900 85.500 440.200 + cpu/stage1/regfile/n_63 - - R (net) 9 - - - + cpu/stage1/regfile/mem_reg[15][8]/D - D R DFFHQNx1_ASAP7_75t_SL 9 130.400 2.000 440.200 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10138 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[15][8]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 13: MET (340.619 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[31][8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[31][8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.281 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.719 + Launch Clock:= 0.000 + Data Path:+ 440.100 + Slack:= 340.619 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.500 354.700 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81668/Y - A->Y R NAND2xp5_ASAP7_75t_SL 9 201.900 85.400 440.100 + cpu/stage1/regfile/n_63 - - R (net) 9 - - - + cpu/stage1/regfile/mem_reg[31][8]/D - D R DFFHQNx1_ASAP7_75t_SL 9 130.400 1.900 440.100 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10186 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[31][8]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 14: MET (340.619 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[21][8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[21][8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.281 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.719 + Launch Clock:= 0.000 + Data Path:+ 440.100 + Slack:= 340.619 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.500 354.700 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81668/Y - A->Y R NAND2xp5_ASAP7_75t_SL 9 201.900 85.400 440.100 + cpu/stage1/regfile/n_63 - - R (net) 9 - - - + cpu/stage1/regfile/mem_reg[21][8]/D - D R DFFHQNx1_ASAP7_75t_SL 9 130.400 1.900 440.100 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10156 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[21][8]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 15: MET (340.819 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[13][27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[13][27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.381 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.619 + Launch Clock:= 0.000 + Data Path:+ 439.800 + Slack:= 340.819 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.800 355.000 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81787/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.900 84.800 439.800 + cpu/stage1/regfile/n_42 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[13][27]/D - D R DFFHQNx1_ASAP7_75t_SL 10 131.100 0.700 439.800 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10132 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[13][27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 16: MET (340.834 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[28][8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[28][8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.266 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.734 + Launch Clock:= 0.000 + Data Path:+ 439.900 + Slack:= 340.834 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.500 354.700 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81668/Y - A->Y R NAND2xp5_ASAP7_75t_SL 9 201.900 85.200 439.900 + cpu/stage1/regfile/n_63 - - R (net) 9 - - - + cpu/stage1/regfile/mem_reg[28][8]/D - D R DFFHQNx1_ASAP7_75t_SL 9 130.300 1.700 439.900 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10177 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[28][8]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 17: MET (341.043 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[27][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[27][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.957 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.043 + Launch Clock:= 0.000 + Data Path:+ 439.000 + Slack:= 341.043 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.300 351.500 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81268/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.500 87.500 439.000 + cpu/stage1/regfile/n_124 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[27][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 135.100 1.100 439.000 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10174 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[27][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 18: MET (341.058 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[22][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[22][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.942 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.058 + Launch Clock:= 0.000 + Data Path:+ 439.000 + Slack:= 341.058 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.300 351.500 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81268/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.500 87.500 439.000 + cpu/stage1/regfile/n_124 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[22][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 135.000 1.100 439.000 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10159 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[22][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 19: MET (341.058 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[2][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[2][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.942 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.058 + Launch Clock:= 0.000 + Data Path:+ 439.000 + Slack:= 341.058 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.300 351.500 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81268/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.500 87.500 439.000 + cpu/stage1/regfile/n_124 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[2][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 135.000 1.100 439.000 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10099 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[2][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 20: MET (341.058 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[10][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[10][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.942 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.058 + Launch Clock:= 0.000 + Data Path:+ 439.000 + Slack:= 341.058 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.300 351.500 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81268/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.500 87.500 439.000 + cpu/stage1/regfile/n_124 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[10][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 135.000 1.100 439.000 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10123 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[10][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 21: MET (341.158 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[15][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[15][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.942 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.058 + Launch Clock:= 0.000 + Data Path:+ 438.900 + Slack:= 341.158 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.300 351.500 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81268/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.500 87.400 438.900 + cpu/stage1/regfile/n_124 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[15][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 135.000 1.000 438.900 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10138 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[15][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 22: MET (341.158 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[23][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[23][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.942 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.058 + Launch Clock:= 0.000 + Data Path:+ 438.900 + Slack:= 341.158 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.300 351.500 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81268/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.500 87.400 438.900 + cpu/stage1/regfile/n_124 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[23][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 135.000 1.000 438.900 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10162 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[23][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 23: MET (341.158 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[11][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[11][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.942 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.058 + Launch Clock:= 0.000 + Data Path:+ 438.900 + Slack:= 341.158 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.300 351.500 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81268/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.500 87.400 438.900 + cpu/stage1/regfile/n_124 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[11][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 135.000 1.000 438.900 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10126 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[11][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 24: MET (341.233 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[14][27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[14][27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.367 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.633 + Launch Clock:= 0.000 + Data Path:+ 439.400 + Slack:= 341.233 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.800 355.000 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81787/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.900 84.400 439.400 + cpu/stage1/regfile/n_42 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[14][27]/D - D R DFFHQNx1_ASAP7_75t_SL 10 131.000 0.300 439.400 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10135 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[14][27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 25: MET (341.358 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[9][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[9][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.942 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.058 + Launch Clock:= 0.000 + Data Path:+ 438.700 + Slack:= 341.358 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.300 351.500 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81268/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.500 87.200 438.700 + cpu/stage1/regfile/n_124 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[9][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 135.000 0.800 438.700 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10120 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[9][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 26: MET (341.358 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[25][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[25][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.942 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.058 + Launch Clock:= 0.000 + Data Path:+ 438.700 + Slack:= 341.358 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.300 351.500 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81268/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.500 87.200 438.700 + cpu/stage1/regfile/n_124 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[25][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 135.000 0.800 438.700 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10168 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[25][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 27: MET (341.447 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[21][27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[21][27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.353 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.647 + Launch Clock:= 0.000 + Data Path:+ 439.200 + Slack:= 341.447 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.800 355.000 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81787/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.900 84.200 439.200 + cpu/stage1/regfile/n_42 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[21][27]/D - D R DFFHQNx1_ASAP7_75t_SL 10 130.900 0.100 439.200 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10156 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[21][27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 28: MET (341.588 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[14][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[14][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.712 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.288 + Launch Clock:= 0.000 + Data Path:+ 438.700 + Slack:= 341.588 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.700 351.900 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81512/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.600 86.800 438.700 + cpu/stage1/regfile/n_85 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[14][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 133.400 1.400 438.700 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10135 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[14][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 29: MET (341.588 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[21][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[21][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.712 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.288 + Launch Clock:= 0.000 + Data Path:+ 438.700 + Slack:= 341.588 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.700 351.900 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81512/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.600 86.800 438.700 + cpu/stage1/regfile/n_85 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[21][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 133.400 1.400 438.700 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10156 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[21][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 30: MET (341.662 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[7][8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[7][8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.238 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.762 + Launch Clock:= 0.000 + Data Path:+ 439.100 + Slack:= 341.662 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.500 354.700 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81668/Y - A->Y R NAND2xp5_ASAP7_75t_SL 9 201.900 84.400 439.100 + cpu/stage1/regfile/n_63 - - R (net) 9 - - - + cpu/stage1/regfile/mem_reg[7][8]/D - D R DFFHQNx1_ASAP7_75t_SL 9 130.100 0.900 439.100 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10114 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[7][8]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 31: MET (341.662 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[20][8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[20][8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.238 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.762 + Launch Clock:= 0.000 + Data Path:+ 439.100 + Slack:= 341.662 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.500 354.700 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81668/Y - A->Y R NAND2xp5_ASAP7_75t_SL 9 201.900 84.400 439.100 + cpu/stage1/regfile/n_63 - - R (net) 9 - - - + cpu/stage1/regfile/mem_reg[20][8]/D - D R DFFHQNx1_ASAP7_75t_SL 9 130.100 0.900 439.100 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10153 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[20][8]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 32: MET (341.688 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[29][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[29][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.712 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.288 + Launch Clock:= 0.000 + Data Path:+ 438.600 + Slack:= 341.688 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.700 351.900 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81512/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.600 86.700 438.600 + cpu/stage1/regfile/n_85 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[29][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 133.400 1.300 438.600 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10180 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[29][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 33: MET (341.772 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[7][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[7][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.928 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.072 + Launch Clock:= 0.000 + Data Path:+ 438.300 + Slack:= 341.772 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.300 351.500 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81268/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.500 86.800 438.300 + cpu/stage1/regfile/n_124 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[7][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 134.900 0.400 438.300 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10114 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[7][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 34: MET (341.802 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[13][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[13][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.698 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.302 + Launch Clock:= 0.000 + Data Path:+ 438.500 + Slack:= 341.802 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.700 351.900 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81512/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.600 86.600 438.500 + cpu/stage1/regfile/n_85 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[13][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 133.300 1.200 438.500 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10132 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[13][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 35: MET (342.002 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[18][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[18][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.698 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.302 + Launch Clock:= 0.000 + Data Path:+ 438.300 + Slack:= 342.002 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.700 351.900 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81512/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.600 86.400 438.300 + cpu/stage1/regfile/n_85 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[18][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 133.300 1.000 438.300 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10147 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[18][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 36: MET (342.002 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[4][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[4][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.698 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.302 + Launch Clock:= 0.000 + Data Path:+ 438.300 + Slack:= 342.002 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.700 351.900 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81512/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.600 86.400 438.300 + cpu/stage1/regfile/n_85 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[4][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 133.300 1.000 438.300 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10105 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[4][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 37: MET (342.002 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[19][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[19][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.698 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.302 + Launch Clock:= 0.000 + Data Path:+ 438.300 + Slack:= 342.002 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.700 351.900 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81512/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.600 86.400 438.300 + cpu/stage1/regfile/n_85 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[19][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 133.300 1.000 438.300 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10150 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[19][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 38: MET (342.102 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[17][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[17][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.698 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.302 + Launch Clock:= 0.000 + Data Path:+ 438.200 + Slack:= 342.102 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.700 351.900 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81512/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.600 86.300 438.200 + cpu/stage1/regfile/n_85 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[17][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 133.300 0.900 438.200 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10144 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[17][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 39: MET (342.217 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[20][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[20][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.683 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.317 + Launch Clock:= 0.000 + Data Path:+ 438.100 + Slack:= 342.217 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.700 351.900 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81512/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.600 86.200 438.100 + cpu/stage1/regfile/n_85 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[20][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 133.200 0.800 438.100 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10153 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[20][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 40: MET (342.277 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[19][8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[19][8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.223 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.777 + Launch Clock:= 0.000 + Data Path:+ 438.500 + Slack:= 342.277 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.500 354.700 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81668/Y - A->Y R NAND2xp5_ASAP7_75t_SL 9 201.900 83.800 438.500 + cpu/stage1/regfile/n_63 - - R (net) 9 - - - + cpu/stage1/regfile/mem_reg[19][8]/D - D R DFFHQNx1_ASAP7_75t_SL 9 130.000 0.300 438.500 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10150 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[19][8]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 41: MET (342.291 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[11][8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[11][8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.209 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.791 + Launch Clock:= 0.000 + Data Path:+ 438.500 + Slack:= 342.291 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 117.500 354.700 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81668/Y - A->Y R NAND2xp5_ASAP7_75t_SL 9 201.900 83.800 438.500 + cpu/stage1/regfile/n_63 - - R (net) 9 - - - + cpu/stage1/regfile/mem_reg[11][8]/D - D R DFFHQNx1_ASAP7_75t_SL 9 129.900 0.300 438.500 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10126 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[11][8]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 42: MET (342.417 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[8][14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[8][14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 19.683 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 780.317 + Launch Clock:= 0.000 + Data Path:+ 437.900 + Slack:= 342.417 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 114.700 351.900 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81512/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 201.600 86.000 437.900 + cpu/stage1/regfile/n_85 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[8][14]/D - D R DFFHQNx1_ASAP7_75t_SL 10 133.200 0.600 437.900 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10117 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[8][14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 43: MET (343.957 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[12][26]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[12][26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 20.143 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.857 + Launch Clock:= 0.000 + Data Path:+ 435.900 + Slack:= 343.957 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 110.400 347.600 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81625/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 200.900 88.300 435.900 + cpu/stage1/regfile/n_70 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[12][26]/D - D R DFFHQNx1_ASAP7_75t_SL 10 136.400 1.100 435.900 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10129 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[12][26]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 44: MET (343.957 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[31][26]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[31][26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 20.143 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.857 + Launch Clock:= 0.000 + Data Path:+ 435.900 + Slack:= 343.957 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 110.400 347.600 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81625/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 200.900 88.300 435.900 + cpu/stage1/regfile/n_70 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[31][26]/D - D R DFFHQNx1_ASAP7_75t_SL 10 136.400 1.100 435.900 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10186 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[31][26]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 45: MET (344.057 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[25][26]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[25][26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 20.143 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.857 + Launch Clock:= 0.000 + Data Path:+ 435.800 + Slack:= 344.057 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 110.400 347.600 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81625/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 200.900 88.200 435.800 + cpu/stage1/regfile/n_70 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[25][26]/D - D R DFFHQNx1_ASAP7_75t_SL 10 136.400 1.000 435.800 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10168 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[25][26]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 46: MET (344.057 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[6][26]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[6][26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 20.143 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.857 + Launch Clock:= 0.000 + Data Path:+ 435.800 + Slack:= 344.057 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 110.400 347.600 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81625/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 200.900 88.200 435.800 + cpu/stage1/regfile/n_70 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[6][26]/D - D R DFFHQNx1_ASAP7_75t_SL 10 136.400 1.000 435.800 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10111 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[6][26]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 47: MET (344.057 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[5][26]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[5][26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 20.143 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.857 + Launch Clock:= 0.000 + Data Path:+ 435.800 + Slack:= 344.057 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 110.400 347.600 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81625/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 200.900 88.200 435.800 + cpu/stage1/regfile/n_70 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[5][26]/D - D R DFFHQNx1_ASAP7_75t_SL 10 136.400 1.000 435.800 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10108 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[5][26]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 48: MET (344.171 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[26][26]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[26][26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 20.129 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.871 + Launch Clock:= 0.000 + Data Path:+ 435.700 + Slack:= 344.171 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 110.400 347.600 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81625/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 200.900 88.100 435.700 + cpu/stage1/regfile/n_70 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[26][26]/D - D R DFFHQNx1_ASAP7_75t_SL 10 136.300 0.900 435.700 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10171 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[26][26]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 49: MET (344.271 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[17][26]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[17][26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 20.129 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.871 + Launch Clock:= 0.000 + Data Path:+ 435.600 + Slack:= 344.271 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 110.400 347.600 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81625/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 200.900 88.000 435.600 + cpu/stage1/regfile/n_70 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[17][26]/D - D R DFFHQNx1_ASAP7_75t_SL 10 136.300 0.800 435.600 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10144 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[17][26]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- +Path 50: MET (344.271 ps) Setup Check with Pin cpu/stage1/regfile/mem_reg[11][26]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: default + Startpoint: (R) reset + Clock: + Endpoint: (R) cpu/stage1/regfile/mem_reg[11][26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 20.129 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 779.871 + Launch Clock:= 0.000 + Data Path:+ 435.600 + Slack:= 344.271 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------ + reset - reset R (arrival) 6 4.100 12.900 12.900 + reset - - R (net) 6 - - - + FE_OFC0_reset/Y - A->Y R BUFx2_ASAP7_75t_SL 48 34.000 91.000 103.900 + FE_OFN0_reset - - R (net) 48 - - - + cpu/stage1/FE_DBTC77_reset/Y - A->Y F INVx2_ASAP7_75t_L 46 198.500 76.800 180.700 + cpu/stage1/FE_DBTN77_reset - - F (net) 46 - - - + cpu/stage1/regfile/FE_OFC91_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 48 143.700 56.500 237.200 + cpu/stage1/regfile/FE_OFN91_FE_DBTN77_reset - - F (net) 48 - - - + cpu/stage1/regfile/FE_OFC92_FE_DBTN77_reset/Y - A->Y F BUFx2_ASAP7_75t_SL 58 129.500 110.400 347.600 + cpu/stage1/regfile/FE_OFN92_FE_DBTN77_reset - - F (net) 58 - - - + cpu/stage1/regfile/g81625/Y - A->Y R NAND2xp5_ASAP7_75t_SL 10 200.900 88.000 435.600 + cpu/stage1/regfile/n_70 - - R (net) 10 - - - + cpu/stage1/regfile/mem_reg[11][26]/D - D R DFFHQNx1_ASAP7_75t_SL 10 136.300 0.800 435.600 +#------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/regfile/CLKGATE_rc_gclk_10126 - - R (net) 32 - - - + cpu/stage1/regfile/mem_reg[11][26]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------------------- + diff --git a/build/par-rundir/timingReports/riscv_top_preCTS_reg2cgate.tarpt b/build/par-rundir/timingReports/riscv_top_preCTS_reg2cgate.tarpt new file mode 100644 index 0000000..ca0f28f --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_preCTS_reg2cgate.tarpt @@ -0,0 +1,2457 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 21:52:30 2020 +# Design: riscv_top +# Command: place_opt_design +############################################################### +Path 1: MET (49.954 ps) Clock Gating Setup Check with Pin mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 36.646 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 763.354 + Launch Clock:= 0.000 + Data Path:+ 713.400 + Slack:= 49.954 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2318/Y - B1->Y F OAI221xp5_ASAP7_75t_SL 1 33.100 15.600 168.300 + cpu/stage3/wb_dmem[0] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1103/Y - A1->Y F AO21x1_ASAP7_75t_SL 3 28.600 22.400 190.700 + cpu/wb_data[0] - - F (net) 3 - - - + cpu/stage2/rs2DataSel/g563/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 17.700 29.600 220.300 + cpu/stage2/stage2_rs2_data[0] - - F (net) 8 - - - + cpu/stage2/bselmux/g583/Y - A->Y R NAND2xp5_ASAP7_75t_SL 1 31.200 12.400 232.700 + cpu/stage2/bselmux/n_6 - - R (net) 1 - - - + cpu/stage2/bselmux/g559/Y - A->Y R AND2x2_ASAP7_75t_SL 2 23.400 23.000 255.700 + cpu/stage2/stage2_alu_in2[0] - - R (net) 2 - - - + cpu/stage2/alu/FE_OFC692_n_30/Y - A->Y F INVx3_ASAP7_75t_SL 24 23.300 22.500 278.200 + cpu/stage2/alu/FE_OFN867_n_30 - - F (net) 24 - - - + cpu/stage2/alu/FE_OFC696_n_30/Y - A->Y R INVx1_ASAP7_75t_SL 14 39.300 38.900 317.100 + cpu/stage2/alu/FE_OFN871_n_30 - - R (net) 14 - - - + cpu/stage2/alu/lt_29_31_g1474/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 70.300 11.700 328.800 + cpu/stage2/alu/lt_29_31_n_55 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1456/Y - C->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 39.000 15.000 343.800 + cpu/stage2/alu/lt_29_31_n_73 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1448/Y - A->Y F MAJIxp5_ASAP7_75t_SL 1 39.100 11.600 355.400 + cpu/stage2/alu/lt_29_31_n_81 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1445/Y - A->Y R MAJIxp5_ASAP7_75t_SL 1 42.100 18.000 373.400 + cpu/stage2/alu/lt_29_31_n_84 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1444/Y - A1->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 44.600 17.000 390.400 + cpu/stage2/alu/lt_29_31_n_85 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1443/Y - A1->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 33.000 33.100 423.500 + cpu/stage2/alu/lt_29_31_n_86 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1442/Y - A1->Y F AOI321xp33_ASAP7_75t_SL 1 67.400 40.100 463.600 + cpu/stage2/alu/n_324 - - F (net) 1 - - - + cpu/stage2/alu/g5667/Y - B1->Y R AOI33xp33_ASAP7_75t_SL 1 70.300 29.800 493.400 + cpu/stage2/alu/n_54 - - R (net) 1 - - - + cpu/stage2/alu/g5520/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 52.900 15.400 508.800 + cpu/stage2/alu/n_192 - - F (net) 1 - - - + cpu/stage2/alu/g5502/Y - C->Y F AO221x1_ASAP7_75t_SL 9 37.700 65.900 574.700 + cpu/stage2_alu_out[0] - - F (net) 9 - - - + cpu/stage3/memrw/g428/Y - A->Y F OR3x1_ASAP7_75t_SL 2 91.900 34.800 609.500 + cpu/stage3/memrw/n_10 - - F (net) 2 - - - + cpu/stage3/memrw/g424/Y - A2->Y R OAI211xp5_ASAP7_75t_SL 3 14.500 24.700 634.200 + dcache_we[2] - - R (net) 3 - - - + mem/dcache/g13997/Y - C->Y F NOR4xp25_ASAP7_75t_SL 1 50.100 12.200 646.400 + mem/dcache/n_119 - - F (net) 1 - - - + mem/dcache/FE_OFC480_n_119/Y - A->Y R INVx1_ASAP7_75t_SL 3 27.600 36.400 682.800 + mem/dcache/n_321 - - R (net) 3 - - - + mem/dcache/FE_OFC481_n_119/Y - A->Y F INVx1_ASAP7_75t_SL 1 67.300 6.500 689.300 + mem/dcache/FE_OFN727_n_119 - - F (net) 1 - - - + mem/dcache/g13731/Y - A1->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 21.100 12.700 702.000 + mem/dcache/n_195 - - R (net) 1 - - - + mem/dcache/g13600/Y - A1->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 32.700 11.400 713.400 + mem/dcache/n_323 - - F (net) 1 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/ENA - ENA F ICGx1_ASAP7_75t_R 1 22.200 0.000 713.400 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#---------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#---------------------------------------------------------------------------------------------------------------------------- +Path 2: MET (473.564 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 45.636 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 754.364 + Launch Clock:= 0.000 + Data Path:+ 280.800 + Slack:= 473.564 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77625/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 31.000 263.300 + cpu/stage1/regfile/n_1704 - - F (net) 4 - - - + cpu/stage1/regfile/g77202/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 57.100 17.500 280.800 + cpu/stage1/regfile/n_2195 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 34.400 0.100 280.800 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST30/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 3: MET (474.939 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 45.261 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 754.739 + Launch Clock:= 0.000 + Data Path:+ 279.800 + Slack:= 474.939 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77625/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 31.000 263.300 + cpu/stage1/regfile/n_1704 - - F (net) 4 - - - + cpu/stage1/regfile/g77162/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 57.100 16.500 279.800 + cpu/stage1/regfile/n_2189 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 33.500 0.100 279.800 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST36/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 4: MET (476.457 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 44.843 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 755.157 + Launch Clock:= 0.000 + Data Path:+ 278.700 + Slack:= 476.457 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77627/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 31.000 263.300 + cpu/stage1/regfile/n_1702 - - F (net) 4 - - - + cpu/stage1/regfile/g77178/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 57.200 15.400 278.700 + cpu/stage1/regfile/n_2194 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 32.500 0.100 278.700 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST31/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 5: MET (476.490 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 45.010 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 754.990 + Launch Clock:= 0.000 + Data Path:+ 278.500 + Slack:= 476.490 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77626/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 30.600 262.900 + cpu/stage1/regfile/n_1703 - - F (net) 4 - - - + cpu/stage1/regfile/g77179/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 56.600 15.600 278.500 + cpu/stage1/regfile/n_2200 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 32.900 0.100 278.500 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST25/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 6: MET (476.515 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 44.885 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 755.115 + Launch Clock:= 0.000 + Data Path:+ 278.600 + Slack:= 476.515 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77627/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 31.000 263.300 + cpu/stage1/regfile/n_1702 - - F (net) 4 - - - + cpu/stage1/regfile/g77172/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 57.200 15.300 278.600 + cpu/stage1/regfile/n_2186 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 32.600 0.000 278.600 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST39/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 7: MET (476.557 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 44.843 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 755.157 + Launch Clock:= 0.000 + Data Path:+ 278.600 + Slack:= 476.557 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77625/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 31.000 263.300 + cpu/stage1/regfile/n_1704 - - F (net) 4 - - - + cpu/stage1/regfile/g77203/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 57.100 15.300 278.600 + cpu/stage1/regfile/n_2197 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 32.500 0.100 278.600 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST28/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 8: MET (476.606 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 45.094 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 754.906 + Launch Clock:= 0.000 + Data Path:+ 278.300 + Slack:= 476.606 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77628/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 30.100 262.400 + cpu/stage1/regfile/n_1701 - - F (net) 4 - - - + cpu/stage1/regfile/g77201/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 55.700 15.900 278.300 + cpu/stage1/regfile/n_2201 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 33.100 0.100 278.300 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST24/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 9: MET (476.657 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 44.843 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 755.157 + Launch Clock:= 0.000 + Data Path:+ 278.500 + Slack:= 476.657 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77627/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 31.000 263.300 + cpu/stage1/regfile/n_1702 - - F (net) 4 - - - + cpu/stage1/regfile/g77199/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 57.200 15.200 278.500 + cpu/stage1/regfile/n_2188 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 32.500 0.000 278.500 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST37/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 10: MET (476.706 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 45.094 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 754.906 + Launch Clock:= 0.000 + Data Path:+ 278.200 + Slack:= 476.706 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77628/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 30.100 262.400 + cpu/stage1/regfile/n_1701 - - F (net) 4 - - - + cpu/stage1/regfile/g77200/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 55.700 15.800 278.200 + cpu/stage1/regfile/n_2199 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 33.100 0.100 278.200 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST26/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 11: MET (476.799 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 44.801 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 755.199 + Launch Clock:= 0.000 + Data Path:+ 278.400 + Slack:= 476.799 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77625/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 31.000 263.300 + cpu/stage1/regfile/n_1704 - - F (net) 4 - - - + cpu/stage1/regfile/g77158/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 57.100 15.100 278.400 + cpu/stage1/regfile/n_2187 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 32.400 0.000 278.400 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST38/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 12: MET (477.057 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 44.843 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 755.157 + Launch Clock:= 0.000 + Data Path:+ 278.100 + Slack:= 477.057 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77626/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 30.600 262.900 + cpu/stage1/regfile/n_1703 - - F (net) 4 - - - + cpu/stage1/regfile/g77246/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 56.600 15.200 278.100 + cpu/stage1/regfile/n_2198 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 32.500 0.000 278.100 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST27/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 13: MET (477.540 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 44.760 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 755.240 + Launch Clock:= 0.000 + Data Path:+ 277.700 + Slack:= 477.540 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77626/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 30.600 262.900 + cpu/stage1/regfile/n_1703 - - F (net) 4 - - - + cpu/stage1/regfile/g77198/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 56.600 14.800 277.700 + cpu/stage1/regfile/n_2192 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 32.300 0.000 277.700 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST33/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 14: MET (477.891 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 44.509 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 755.491 + Launch Clock:= 0.000 + Data Path:+ 277.600 + Slack:= 477.891 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77627/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 31.000 263.300 + cpu/stage1/regfile/n_1702 - - F (net) 4 - - - + cpu/stage1/regfile/g77180/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 57.200 14.300 277.600 + cpu/stage1/regfile/n_2196 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 31.700 0.000 277.600 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST29/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 15: MET (478.249 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 44.551 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 755.449 + Launch Clock:= 0.000 + Data Path:+ 277.200 + Slack:= 478.249 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77626/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 30.600 262.900 + cpu/stage1/regfile/n_1703 - - F (net) 4 - - - + cpu/stage1/regfile/g77171/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 56.600 14.300 277.200 + cpu/stage1/regfile/n_2190 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 31.800 0.000 277.200 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST35/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 16: MET (478.466 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 44.634 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 755.366 + Launch Clock:= 0.000 + Data Path:+ 276.900 + Slack:= 478.466 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77628/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 30.100 262.400 + cpu/stage1/regfile/n_1701 - - F (net) 4 - - - + cpu/stage1/regfile/g77161/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 55.700 14.500 276.900 + cpu/stage1/regfile/n_2193 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 32.000 0.000 276.900 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST32/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 17: MET (478.707 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 44.593 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 755.407 + Launch Clock:= 0.000 + Data Path:+ 276.700 + Slack:= 478.707 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.800 202.100 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77822/Y - A->Y R INVx1_ASAP7_75t_SL 4 146.300 30.200 232.300 + cpu/stage1/regfile/n_1317 - - R (net) 4 - - - + cpu/stage1/regfile/g77628/Y - A->Y F NAND3xp33_ASAP7_75t_SL 4 54.000 30.100 262.400 + cpu/stage1/regfile/n_1701 - - F (net) 4 - - - + cpu/stage1/regfile/g77157/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 55.700 14.300 276.700 + cpu/stage1/regfile/n_2191 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 31.900 0.000 276.700 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST34/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 18: MET (505.576 ps) Clock Gating Setup Check with Pin cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 46.324 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 753.676 + Launch Clock:= 0.000 + Data Path:+ 248.100 + Slack:= 505.576 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 0.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[2]/QN - CLK->QN F DFFHQNx1_ASAP7_75t_SL 3 0.100 34.100 34.100 + mem/dcache/STATE[2] - - F (net) 3 - - - + mem/dcache/g11633/Y - A->Y R INVx1_ASAP7_75t_SL 2 21.100 9.400 43.500 + mem/dcache/n_204 - - R (net) 2 - - - + mem/dcache/g11616/Y - B->Y F NAND2xp5_ASAP7_75t_SL 6 14.100 18.700 62.200 + mem/dcache/n_325 - - F (net) 6 - - - + mem/dcache/g14031/Y - A->Y R NAND2xp5_ASAP7_75t_SL 3 36.000 20.300 82.500 + mem/dcache/n_92 - - R (net) 3 - - - + mem/dcache/g14018/Y - B->Y F NOR2xp33_ASAP7_75t_SL 1 31.100 29.900 112.400 + mem/d_stall_n - - F (net) 1 - - - + mem/g20/Y - A->Y R NAND2x1_ASAP7_75t_SL 41 46.400 127.300 239.700 + stall - - R (net) 41 - - - + cpu/s2_to_s3_inst/g128__6260/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 250.300 8.400 248.100 + cpu/s2_to_s3_inst/n_19 - - F (net) 1 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/ENA - ENA F ICGx1_ASAP7_75t_R 1 70.500 0.100 248.100 +#------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#---------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#---------------------------------------------------------------------------------------------------------------------------------- +Path 19: MET (510.431 ps) Clock Gating Setup Check with Pin cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 45.769 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 754.231 + Launch Clock:= 0.000 + Data Path:+ 243.800 + Slack:= 510.431 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 0.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[2]/QN - CLK->QN F DFFHQNx1_ASAP7_75t_SL 3 0.100 34.100 34.100 + mem/dcache/STATE[2] - - F (net) 3 - - - + mem/dcache/g11633/Y - A->Y R INVx1_ASAP7_75t_SL 2 21.100 9.400 43.500 + mem/dcache/n_204 - - R (net) 2 - - - + mem/dcache/g11616/Y - B->Y F NAND2xp5_ASAP7_75t_SL 6 14.100 18.700 62.200 + mem/dcache/n_325 - - F (net) 6 - - - + mem/dcache/g14031/Y - A->Y R NAND2xp5_ASAP7_75t_SL 3 36.000 20.300 82.500 + mem/dcache/n_92 - - R (net) 3 - - - + mem/dcache/g14018/Y - B->Y F NOR2xp33_ASAP7_75t_SL 1 31.100 29.900 112.400 + mem/d_stall_n - - F (net) 1 - - - + mem/g20/Y - A->Y R NAND2x1_ASAP7_75t_SL 41 46.400 127.300 239.700 + stall - - R (net) 41 - - - + cpu/s1_to_s2_inst/g261__5122/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 250.300 4.100 243.800 + cpu/s1_to_s2_inst/n_34 - - F (net) 1 - - - + cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/ENA - ENA F ICGx1_ASAP7_75t_R 1 66.400 0.000 243.800 +#------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#---------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#---------------------------------------------------------------------------------------------------------------------------------- +Path 20: MET (513.275 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 50.425 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 749.575 + Launch Clock:= 0.000 + Data Path:+ 236.300 + Slack:= 513.275 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 68.300 202.600 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77358/Y - A1->Y R OAI31xp33_ASAP7_75t_SL 1 146.300 33.700 236.300 + cpu/stage1/regfile/n_2213 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 65.500 0.100 236.300 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST12/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 21: MET (513.601 ps) Clock Gating Setup Check with Pin cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 45.999 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 754.001 + Launch Clock:= 0.000 + Data Path:+ 240.400 + Slack:= 513.601 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 0.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[2]/QN - CLK->QN F DFFHQNx1_ASAP7_75t_SL 3 0.100 34.100 34.100 + mem/dcache/STATE[2] - - F (net) 3 - - - + mem/dcache/g11633/Y - A->Y R INVx1_ASAP7_75t_SL 2 21.100 9.400 43.500 + mem/dcache/n_204 - - R (net) 2 - - - + mem/dcache/g11616/Y - B->Y F NAND2xp5_ASAP7_75t_SL 6 14.100 18.700 62.200 + mem/dcache/n_325 - - F (net) 6 - - - + mem/dcache/g14031/Y - A->Y R NAND2xp5_ASAP7_75t_SL 3 36.000 20.300 82.500 + mem/dcache/n_92 - - R (net) 3 - - - + mem/dcache/g14018/Y - B->Y F NOR2xp33_ASAP7_75t_SL 1 31.100 29.900 112.400 + mem/d_stall_n - - F (net) 1 - - - + mem/g20/Y - A->Y R NAND2x1_ASAP7_75t_SL 41 46.400 122.000 234.400 + stall - - R (net) 41 - - - + cpu/s2_to_s3_pc/g213__4733/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 249.800 6.000 240.400 + cpu/s2_to_s3_pc/n_34 - - F (net) 1 - - - + cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_INST/ENA - ENA F ICGx1_ASAP7_75t_R 1 68.100 0.100 240.400 +#---------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_pc/CLKGATE_RC_CG_HIER_INST7/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------- +Path 22: MET (514.195 ps) Clock Gating Setup Check with Pin cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 45.905 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 754.095 + Launch Clock:= 0.000 + Data Path:+ 239.900 + Slack:= 514.195 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 0.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[2]/QN - CLK->QN F DFFHQNx1_ASAP7_75t_SL 3 0.100 34.100 34.100 + mem/dcache/STATE[2] - - F (net) 3 - - - + mem/dcache/g11633/Y - A->Y R INVx1_ASAP7_75t_SL 2 21.100 9.400 43.500 + mem/dcache/n_204 - - R (net) 2 - - - + mem/dcache/g11616/Y - B->Y F NAND2xp5_ASAP7_75t_SL 6 14.100 18.700 62.200 + mem/dcache/n_325 - - F (net) 6 - - - + mem/dcache/g14031/Y - A->Y R NAND2xp5_ASAP7_75t_SL 3 36.000 20.300 82.500 + mem/dcache/n_92 - - R (net) 3 - - - + mem/dcache/g14018/Y - B->Y F NOR2xp33_ASAP7_75t_SL 1 31.100 29.900 112.400 + mem/d_stall_n - - F (net) 1 - - - + mem/g20/Y - A->Y R NAND2x1_ASAP7_75t_SL 41 46.400 122.300 234.700 + stall - - R (net) 41 - - - + cpu/s1_to_s2_rs2/g213__9315/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 249.900 5.200 239.900 + cpu/s1_to_s2_rs2/n_34 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/ENA - ENA F ICGx1_ASAP7_75t_R 1 67.400 0.000 239.900 +#----------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#--------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#--------------------------------------------------------------------------------------------------------------------------------- +Path 23: MET (514.209 ps) Clock Gating Setup Check with Pin cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 45.891 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 754.109 + Launch Clock:= 0.000 + Data Path:+ 239.900 + Slack:= 514.209 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 0.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[2]/QN - CLK->QN F DFFHQNx1_ASAP7_75t_SL 3 0.100 34.100 34.100 + mem/dcache/STATE[2] - - F (net) 3 - - - + mem/dcache/g11633/Y - A->Y R INVx1_ASAP7_75t_SL 2 21.100 9.400 43.500 + mem/dcache/n_204 - - R (net) 2 - - - + mem/dcache/g11616/Y - B->Y F NAND2xp5_ASAP7_75t_SL 6 14.100 18.700 62.200 + mem/dcache/n_325 - - F (net) 6 - - - + mem/dcache/g14031/Y - A->Y R NAND2xp5_ASAP7_75t_SL 3 36.000 20.300 82.500 + mem/dcache/n_92 - - R (net) 3 - - - + mem/dcache/g14018/Y - B->Y F NOR2xp33_ASAP7_75t_SL 1 31.100 29.900 112.400 + mem/d_stall_n - - F (net) 1 - - - + mem/g20/Y - A->Y R NAND2x1_ASAP7_75t_SL 41 46.400 122.300 234.700 + stall - - R (net) 41 - - - + cpu/s2_to_s3_alu/g213__7410/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 249.800 5.200 239.900 + cpu/s2_to_s3_alu/n_34 - - F (net) 1 - - - + cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_INST/ENA - ENA F ICGx1_ASAP7_75t_R 1 67.300 0.100 239.900 +#----------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#--------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#--------------------------------------------------------------------------------------------------------------------------------- +Path 24: MET (515.067 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 50.233 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 749.767 + Launch Clock:= 0.000 + Data Path:+ 234.700 + Slack:= 515.067 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 68.100 202.400 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77348/Y - A1->Y R OAI31xp33_ASAP7_75t_SL 1 146.300 32.300 234.700 + cpu/stage1/regfile/n_2203 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 63.500 0.100 234.700 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST22/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 25: MET (515.376 ps) Clock Gating Setup Check with Pin cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 45.824 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 754.176 + Launch Clock:= 0.000 + Data Path:+ 238.800 + Slack:= 515.376 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 0.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[2]/QN - CLK->QN F DFFHQNx1_ASAP7_75t_SL 3 0.100 34.100 34.100 + mem/dcache/STATE[2] - - F (net) 3 - - - + mem/dcache/g11633/Y - A->Y R INVx1_ASAP7_75t_SL 2 21.100 9.400 43.500 + mem/dcache/n_204 - - R (net) 2 - - - + mem/dcache/g11616/Y - B->Y F NAND2xp5_ASAP7_75t_SL 6 14.100 18.700 62.200 + mem/dcache/n_325 - - F (net) 6 - - - + mem/dcache/g14031/Y - A->Y R NAND2xp5_ASAP7_75t_SL 3 36.000 20.300 82.500 + mem/dcache/n_92 - - R (net) 3 - - - + mem/dcache/g14018/Y - B->Y F NOR2xp33_ASAP7_75t_SL 1 31.100 29.900 112.400 + mem/d_stall_n - - F (net) 1 - - - + mem/g20/Y - A->Y R NAND2x1_ASAP7_75t_SL 41 46.400 121.800 234.200 + stall - - R (net) 41 - - - + cpu/s1_to_s2_pc/g213__1705/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 249.800 4.600 238.800 + cpu/s1_to_s2_pc/n_34 - - F (net) 1 - - - + cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_INST/ENA - ENA F ICGx1_ASAP7_75t_R 1 66.800 0.000 238.800 +#---------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_pc/CLKGATE_RC_CG_HIER_INST2/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------- +Path 26: MET (515.390 ps) Clock Gating Setup Check with Pin cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 45.810 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 754.190 + Launch Clock:= 0.000 + Data Path:+ 238.800 + Slack:= 515.390 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 0.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[2]/QN - CLK->QN F DFFHQNx1_ASAP7_75t_SL 3 0.100 34.100 34.100 + mem/dcache/STATE[2] - - F (net) 3 - - - + mem/dcache/g11633/Y - A->Y R INVx1_ASAP7_75t_SL 2 21.100 9.400 43.500 + mem/dcache/n_204 - - R (net) 2 - - - + mem/dcache/g11616/Y - B->Y F NAND2xp5_ASAP7_75t_SL 6 14.100 18.700 62.200 + mem/dcache/n_325 - - F (net) 6 - - - + mem/dcache/g14031/Y - A->Y R NAND2xp5_ASAP7_75t_SL 3 36.000 20.300 82.500 + mem/dcache/n_92 - - R (net) 3 - - - + mem/dcache/g14018/Y - B->Y F NOR2xp33_ASAP7_75t_SL 1 31.100 29.900 112.400 + mem/d_stall_n - - F (net) 1 - - - + mem/g20/Y - A->Y R NAND2x1_ASAP7_75t_SL 41 46.400 121.900 234.300 + stall - - R (net) 41 - - - + cpu/s1_to_s2_imm/g213__2398/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 249.800 4.500 238.800 + cpu/s1_to_s2_imm/n_34 - - F (net) 1 - - - + cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_INST/ENA - ENA F ICGx1_ASAP7_75t_R 1 66.700 0.000 238.800 +#----------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#--------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_imm/CLKGATE_RC_CG_HIER_INST0/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#--------------------------------------------------------------------------------------------------------------------------------- +Path 27: MET (515.992 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 50.108 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 749.892 + Launch Clock:= 0.000 + Data Path:+ 233.900 + Slack:= 515.992 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 68.200 202.500 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77356/Y - A1->Y R OAI31xp33_ASAP7_75t_SL 1 146.300 31.400 233.900 + cpu/stage1/regfile/n_2204 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 62.200 0.100 233.900 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST21/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 28: MET (516.121 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 50.079 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 749.921 + Launch Clock:= 0.000 + Data Path:+ 233.800 + Slack:= 516.121 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 68.300 202.600 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77355/Y - A1->Y R OAI31xp33_ASAP7_75t_SL 1 146.300 31.200 233.800 + cpu/stage1/regfile/n_2205 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 61.900 0.100 233.800 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST20/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 29: MET (516.144 ps) Clock Gating Setup Check with Pin cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 45.756 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 754.244 + Launch Clock:= 0.000 + Data Path:+ 238.100 + Slack:= 516.144 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 0.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[2]/QN - CLK->QN F DFFHQNx1_ASAP7_75t_SL 3 0.100 34.100 34.100 + mem/dcache/STATE[2] - - F (net) 3 - - - + mem/dcache/g11633/Y - A->Y R INVx1_ASAP7_75t_SL 2 21.100 9.400 43.500 + mem/dcache/n_204 - - R (net) 2 - - - + mem/dcache/g11616/Y - B->Y F NAND2xp5_ASAP7_75t_SL 6 14.100 18.700 62.200 + mem/dcache/n_325 - - F (net) 6 - - - + mem/dcache/g14031/Y - A->Y R NAND2xp5_ASAP7_75t_SL 3 36.000 20.300 82.500 + mem/dcache/n_92 - - R (net) 3 - - - + mem/dcache/g14018/Y - B->Y F NOR2xp33_ASAP7_75t_SL 1 31.100 29.900 112.400 + mem/d_stall_n - - F (net) 1 - - - + mem/g20/Y - A->Y R NAND2x1_ASAP7_75t_SL 41 46.400 121.700 234.100 + stall - - R (net) 41 - - - + cpu/s1_to_s2_rs1/g213__1881/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 249.800 4.000 238.100 + cpu/s1_to_s2_rs1/n_34 - - F (net) 1 - - - + cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_INST/ENA - ENA F ICGx1_ASAP7_75t_R 1 66.300 0.000 238.100 +#----------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#--------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs1/CLKGATE_RC_CG_HIER_INST3/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#--------------------------------------------------------------------------------------------------------------------------------- +Path 30: MET (516.769 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 50.031 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 749.969 + Launch Clock:= 0.000 + Data Path:+ 233.200 + Slack:= 516.769 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 68.000 202.300 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77354/Y - A1->Y R OAI31xp33_ASAP7_75t_SL 1 146.300 30.900 233.200 + cpu/stage1/regfile/n_2212 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 61.400 0.100 233.200 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST13/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 31: MET (517.064 ps) Clock Gating Setup Check with Pin mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 35.336 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 764.664 + Launch Clock:= 0.000 + Data Path:+ 247.600 + Slack:= 517.064 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 0.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[2]/QN - CLK->QN F DFFHQNx1_ASAP7_75t_SL 3 0.100 34.100 34.100 + mem/dcache/STATE[2] - - F (net) 3 - - - + mem/dcache/g11633/Y - A->Y R INVx1_ASAP7_75t_SL 2 21.100 9.400 43.500 + mem/dcache/n_204 - - R (net) 2 - - - + mem/dcache/g11616/Y - B->Y F NAND2xp5_ASAP7_75t_SL 6 14.100 18.700 62.200 + mem/dcache/n_325 - - F (net) 6 - - - + mem/dcache/g14031/Y - A->Y R NAND2xp5_ASAP7_75t_SL 3 36.000 20.300 82.500 + mem/dcache/n_92 - - R (net) 3 - - - + mem/dcache/g14018/Y - B->Y F NOR2xp33_ASAP7_75t_SL 1 31.100 29.900 112.400 + mem/d_stall_n - - F (net) 1 - - - + mem/g20/Y - A->Y R NAND2x1_ASAP7_75t_SL 41 46.400 96.500 208.900 + stall - - R (net) 41 - - - + mem/g22/Y - A->Y F INVx1_ASAP7_75t_SL 2 241.100 8.900 217.800 + mem/n_1 - - F (net) 2 - - - + mem/icache/g6622/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 2 63.000 21.900 239.700 + mem/icache/n_216 - - R (net) 2 - - - + mem/icache/g6621/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 36.500 7.900 247.600 + mem/icache/n_214 - - F (net) 1 - - - + mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/ENA - ENA F ICGx1_ASAP7_75t_R 1 17.100 0.100 247.600 +#------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#---------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + mem/icache/CLKGATE_RC_CG_HIER_INST42/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#---------------------------------------------------------------------------------------------------------------------------- +Path 32: MET (517.674 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 49.926 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 750.074 + Launch Clock:= 0.000 + Data Path:+ 232.400 + Slack:= 517.674 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 68.100 202.400 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77259/Y - A1->Y R OAI31xp33_ASAP7_75t_SL 1 146.300 30.000 232.400 + cpu/stage1/regfile/n_2209 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 60.300 0.100 232.400 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST16/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 33: MET (517.874 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 49.926 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 750.074 + Launch Clock:= 0.000 + Data Path:+ 232.200 + Slack:= 517.874 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.900 202.200 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77361/Y - A1->Y R OAI31xp33_ASAP7_75t_SL 1 146.300 30.000 232.200 + cpu/stage1/regfile/n_2202 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 60.300 0.000 232.200 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST23/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 34: MET (517.894 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 49.906 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 750.094 + Launch Clock:= 0.000 + Data Path:+ 232.200 + Slack:= 517.894 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 68.100 202.400 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77353/Y - A1->Y R OAI31xp33_ASAP7_75t_SL 1 146.300 29.800 232.200 + cpu/stage1/regfile/n_2211 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 60.100 0.000 232.200 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST14/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 35: MET (518.332 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 49.868 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 750.132 + Launch Clock:= 0.000 + Data Path:+ 231.800 + Slack:= 518.332 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.900 202.200 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77359/Y - A1->Y R OAI31xp33_ASAP7_75t_SL 1 146.300 29.600 231.800 + cpu/stage1/regfile/n_2214 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 59.700 0.000 231.800 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST11/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 36: MET (518.523 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 49.877 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 750.123 + Launch Clock:= 0.000 + Data Path:+ 231.600 + Slack:= 518.523 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.700 202.000 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77360/Y - A1->Y R OAI31xp33_ASAP7_75t_SL 1 146.300 29.600 231.600 + cpu/stage1/regfile/n_2210 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 59.800 0.000 231.600 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST15/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 37: MET (518.680 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 49.820 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 750.180 + Launch Clock:= 0.000 + Data Path:+ 231.500 + Slack:= 518.680 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.900 202.200 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77362/Y - A1->Y R OAI31xp33_ASAP7_75t_SL 1 146.300 29.300 231.500 + cpu/stage1/regfile/n_2206 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 59.200 0.100 231.500 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST19/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 38: MET (518.842 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 49.858 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 750.142 + Launch Clock:= 0.000 + Data Path:+ 231.300 + Slack:= 518.842 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.600 201.900 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77254/Y - A1->Y R OAI31xp33_ASAP7_75t_SL 1 146.300 29.400 231.300 + cpu/stage1/regfile/n_2207 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 59.600 0.000 231.300 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST18/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 39: MET (519.190 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 49.810 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 750.190 + Launch Clock:= 0.000 + Data Path:+ 231.000 + Slack:= 519.190 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.600 201.900 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77357/Y - A1->Y R OAI31xp33_ASAP7_75t_SL 1 146.300 29.100 231.000 + cpu/stage1/regfile/n_2215 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 59.100 0.000 231.000 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST10/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 40: MET (521.605 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 49.195 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 750.805 + Launch Clock:= 0.000 + Data Path:+ 229.200 + Slack:= 521.605 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 68.100 202.400 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77249/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 146.300 26.800 229.200 + cpu/stage1/regfile/n_2208 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 52.700 0.100 229.200 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST17/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------ +Path 41: MET (522.157 ps) Clock Gating Setup Check with Pin cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) mem/dcache/STATE_reg[2]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 45.742 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 754.258 + Launch Clock:= 0.000 + Data Path:+ 232.100 + Slack:= 522.157 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 0.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[2]/QN - CLK->QN F DFFHQNx1_ASAP7_75t_SL 3 0.100 34.100 34.100 + mem/dcache/STATE[2] - - F (net) 3 - - - + mem/dcache/g11633/Y - A->Y R INVx1_ASAP7_75t_SL 2 21.100 9.400 43.500 + mem/dcache/n_204 - - R (net) 2 - - - + mem/dcache/g11616/Y - B->Y F NAND2xp5_ASAP7_75t_SL 6 14.100 18.700 62.200 + mem/dcache/n_325 - - F (net) 6 - - - + mem/dcache/g14031/Y - A->Y R NAND2xp5_ASAP7_75t_SL 3 36.000 20.300 82.500 + mem/dcache/n_92 - - R (net) 3 - - - + mem/dcache/g14018/Y - B->Y F NOR2xp33_ASAP7_75t_SL 1 31.100 29.900 112.400 + mem/d_stall_n - - F (net) 1 - - - + mem/g20/Y - A->Y R NAND2x1_ASAP7_75t_SL 41 46.400 115.600 228.000 + stall - - R (net) 41 - - - + cpu/stage1/pcreg/g189__5107/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 249.000 4.100 232.100 + cpu/stage1/pcreg/n_35 - - F (net) 1 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/ENA - ENA F ICGx1_ASAP7_75t_R 1 66.200 0.000 232.100 +#----------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#--------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#--------------------------------------------------------------------------------------------------------------------------------- +Path 42: MET (524.255 ps) Clock Gating Setup Check with Pin cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[8]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 48.945 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 751.055 + Launch Clock:= 0.000 + Data Path:+ 226.800 + Slack:= 524.255 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[8]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 9 0.100 48.700 48.700 + cpu/stage3_inst[8] - - R (net) 9 - - - + cpu/stage1/regfile/FE_OFC921_stage3_inst_8/Y - A->Y R HB1xp67_ASAP7_75t_SL 8 19.300 55.500 104.200 + cpu/stage1/regfile/FE_OFN1052_stage3_inst_8 - - R (net) 8 - - - + cpu/stage1/regfile/g80392/Y - A->Y R OR2x2_ASAP7_75t_SL 5 104.800 30.100 134.300 + cpu/stage1/regfile/n_253 - - R (net) 5 - - - + cpu/stage1/regfile/g78085/Y - A2->Y F OAI31xp33_ASAP7_75t_SL 16 23.000 67.900 202.200 + cpu/stage1/regfile/n_1318 - - F (net) 16 - - - + cpu/stage1/regfile/g77250/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 146.300 24.600 226.800 + cpu/stage1/regfile/n_2216 - - R (net) 1 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 50.100 0.100 226.800 +#------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#----------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/regfile/CLKGATE_RC_CG_HIER_INST9/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#----------------------------------------------------------------------------------------------------------------------------------- +Path 43: MET (589.660 ps) Clock Gating Setup Check with Pin cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/CLK->ENA + View: PVT_0P63V_100C.setup_view + Group: reg2cgate + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[3]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/ENA + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Clock Gating Setup:- 38.140 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 761.860 + Launch Clock:= 0.000 + Data Path:+ 172.200 + Slack:= 589.660 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 0.000 + cpu/s1_to_s2_inst/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_inst/register_reg[3]/QN - CLK->QN F DFFHQNx1_ASAP7_75t_SL 9 0.100 48.500 48.500 + cpu/stage2_inst[3] - - F (net) 9 - - - + cpu/FE_OFC628_stage2_inst_3/Y - A->Y R INVx1_ASAP7_75t_SL 2 42.200 12.700 61.200 + cpu/FE_OFN824_stage2_inst_3 - - R (net) 2 - - - + cpu/FE_OFC631_stage2_inst_3/Y - A->Y F INVx1_ASAP7_75t_SL 4 20.500 11.700 72.900 + cpu/FE_OFN826_stage2_inst_3 - - F (net) 4 - - - + cpu/stage3/csrsel/g212/Y - D->Y R NOR5xp2_ASAP7_75t_SL 1 18.000 27.500 100.400 + cpu/stage3/csrsel/n_7 - - R (net) 1 - - - + cpu/stage3/csrsel/g211/Y - A->Y R AND5x1_ASAP7_75t_SL 1 56.600 50.700 151.100 + cpu/stage3/CSRSelect - - R (net) 1 - - - + cpu/stage3/csr/g195/Y - B->Y R OR2x2_ASAP7_75t_SL 1 59.300 21.100 172.200 + cpu/stage3/csr/n_33 - - R (net) 1 - - - + cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/ENA - ENA R ICGx1_ASAP7_75t_R 1 13.600 1.300 172.200 +#----------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/CLK - CLK R ICGx1_ASAP7_75t_R 47 4.000 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------- + diff --git a/build/par-rundir/timingReports/riscv_top_preCTS_reg2reg.tarpt b/build/par-rundir/timingReports/riscv_top_preCTS_reg2reg.tarpt new file mode 100644 index 0000000..6ea21bd --- /dev/null +++ b/build/par-rundir/timingReports/riscv_top_preCTS_reg2reg.tarpt @@ -0,0 +1,6376 @@ +############################################################### +# Generated by: Cadence Innovus 18.10-p002_1 +# OS: Linux x86_64(Host ID c125m-16.EECS.Berkeley.EDU) +# Generated on: Mon Dec 14 21:52:30 2020 +# Design: riscv_top +# Command: place_opt_design +############################################################### +Path 1: VIOLATED (-0.710 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 5.910 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 794.090 + Launch Clock:= 0.000 + Data Path:+ 794.800 + Slack:= -0.710 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.400 394.400 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g390__4733/Y - B->Y R AND2x4_ASAP7_75t_SL 8 14.300 24.200 418.600 + cpu/stage1_inst[16] - - R (net) 8 - - - + cpu/stage1/regfile/FE_OFC1126_stage1_inst_16/Y - A->Y F INVx1_ASAP7_75t_SL 3 30.500 15.700 434.300 + cpu/stage1/regfile/FE_OFN902_stage1_inst_16 - - F (net) 3 - - - + cpu/stage1/regfile/g80403/Y - B->Y F AND2x4_ASAP7_75t_SL 11 24.400 24.800 459.100 + cpu/stage1/regfile/n_235 - - F (net) 11 - - - + cpu/stage1/regfile/g79836/Y - B->Y F AND2x2_ASAP7_75t_SL 6 24.900 26.600 485.700 + cpu/stage1/regfile/n_315 - - F (net) 6 - - - + cpu/stage1/regfile/g78500/Y - A->Y R NAND2xp5_ASAP7_75t_SL 1 29.200 12.100 497.800 + cpu/stage1/regfile/n_666 - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC608_n_666/Y - A->Y F INVx1_ASAP7_75t_SL 3 19.900 13.900 511.700 + cpu/stage1/regfile/n_665 - - F (net) 3 - - - + cpu/stage1/regfile/FE_OFC610_n_666/Y - A->Y R INVx1_ASAP7_75t_SL 4 21.100 17.100 528.800 + cpu/stage1/regfile/FE_OFN813_n_666 - - R (net) 4 - - - + cpu/stage1/regfile/g77382/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 28.600 9.800 538.600 + cpu/stage1/regfile/n_1758 - - F (net) 1 - - - + cpu/stage1/regfile/g77028/Y - A->Y R NOR3xp33_ASAP7_75t_SL 1 17.200 20.000 558.600 + cpu/stage1/regfile/n_2081 - - R (net) 1 - - - + cpu/stage1/regfile/g76863__9945/Y - B->Y F NAND4xp75_ASAP7_75t_SL 1 40.900 19.900 578.500 + cpu/stage1/rs1_mux_data[21] - - F (net) 1 - - - + cpu/stage1/data1sel_s1/g569__6161/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 36.400 25.200 603.700 + cpu/stage1_rs1[21] - - F (net) 2 - - - + cpu/stage1/pcadder/g1279__1666/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 21.300 17.900 621.600 + cpu/stage1/pcadder/n_52 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1425__5115/Y - B->Y R NAND2xp5_ASAP7_75t_SL 2 19.900 13.200 634.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_107 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1347__1666/Y - B->Y F OAI21xp5_ASAP7_75t_SL 2 21.200 11.600 646.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_160 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1319__5107/Y - A2->Y R A2O1A1O1Ixp25_ASAP7_75t_SL 1 21.600 15.800 662.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_185 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1304__9315/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 28.400 11.500 673.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_197 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - B->Y R AOI21x1_ASAP7_75t_SL 3 20.200 16.500 690.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 29.000 8.000 698.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_20 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1257__7482/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 12.800 17.900 716.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_231 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1244__6783/Y - A1->Y R AOI21x1_ASAP7_75t_SL 2 11.600 11.000 727.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_243 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1236__5477/Y - A1->Y F OAI21x1_ASAP7_75t_SL 1 25.100 8.100 735.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_251 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1235__6417/Y - B->Y F XOR2x1_ASAP7_75t_SL 1 20.700 17.700 752.900 + cpu/stage1/stage1_pc4[31] - - F (net) 1 - - - + cpu/stage1/pcselmux/g988__5526/Y - A2->Y F AO21x1_ASAP7_75t_SL 1 18.700 15.400 768.300 + cpu/stage1/pcselmux/n_16 - - F (net) 1 - - - + cpu/stage1/pcselmux/g961__6783/Y - B->Y F AO21x1_ASAP7_75t_SL 2 14.200 16.800 785.100 + cpu/stage1/stage1_pc_mux_to_pc[31] - - F (net) 2 - - - + cpu/stage1/pcreg/g362__7482/Y - B->Y R NAND2xp5_ASAP7_75t_L 1 14.700 9.700 794.800 + cpu/stage1/pcreg/n_18 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[31]/D - D R DFFHQNx1_ASAP7_75t_SL 1 43.900 0.000 794.800 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[31]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 2: MET (0.518 ps) Setup Check with Pin mem/dcache/STATE_reg[1]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) mem/dcache/STATE_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 5.282 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 794.718 + Launch Clock:= 0.000 + Data Path:+ 794.200 + Slack:= 0.518 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2318/Y - B1->Y F OAI221xp5_ASAP7_75t_SL 1 33.100 15.600 168.300 + cpu/stage3/wb_dmem[0] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1103/Y - A1->Y F AO21x1_ASAP7_75t_SL 3 28.600 22.400 190.700 + cpu/wb_data[0] - - F (net) 3 - - - + cpu/stage2/rs2DataSel/g563/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 17.700 29.600 220.300 + cpu/stage2/stage2_rs2_data[0] - - F (net) 8 - - - + cpu/stage2/bselmux/g583/Y - A->Y R NAND2xp5_ASAP7_75t_SL 1 31.200 12.400 232.700 + cpu/stage2/bselmux/n_6 - - R (net) 1 - - - + cpu/stage2/bselmux/g559/Y - A->Y R AND2x2_ASAP7_75t_SL 2 23.400 23.000 255.700 + cpu/stage2/stage2_alu_in2[0] - - R (net) 2 - - - + cpu/stage2/alu/FE_OFC692_n_30/Y - A->Y F INVx3_ASAP7_75t_SL 24 23.300 22.500 278.200 + cpu/stage2/alu/FE_OFN867_n_30 - - F (net) 24 - - - + cpu/stage2/alu/FE_OFC696_n_30/Y - A->Y R INVx1_ASAP7_75t_SL 14 39.300 38.900 317.100 + cpu/stage2/alu/FE_OFN871_n_30 - - R (net) 14 - - - + cpu/stage2/alu/lt_29_31_g1474/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 70.300 11.700 328.800 + cpu/stage2/alu/lt_29_31_n_55 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1456/Y - C->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 39.000 15.000 343.800 + cpu/stage2/alu/lt_29_31_n_73 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1448/Y - A->Y F MAJIxp5_ASAP7_75t_SL 1 39.100 11.600 355.400 + cpu/stage2/alu/lt_29_31_n_81 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1445/Y - A->Y R MAJIxp5_ASAP7_75t_SL 1 42.100 18.000 373.400 + cpu/stage2/alu/lt_29_31_n_84 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1444/Y - A1->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 44.600 17.000 390.400 + cpu/stage2/alu/lt_29_31_n_85 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1443/Y - A1->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 33.000 33.100 423.500 + cpu/stage2/alu/lt_29_31_n_86 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1442/Y - A1->Y F AOI321xp33_ASAP7_75t_SL 1 67.400 40.100 463.600 + cpu/stage2/alu/n_324 - - F (net) 1 - - - + cpu/stage2/alu/g5667/Y - B1->Y R AOI33xp33_ASAP7_75t_SL 1 70.300 29.800 493.400 + cpu/stage2/alu/n_54 - - R (net) 1 - - - + cpu/stage2/alu/g5520/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 52.900 15.400 508.800 + cpu/stage2/alu/n_192 - - F (net) 1 - - - + cpu/stage2/alu/g5502/Y - C->Y F AO221x1_ASAP7_75t_SL 9 37.700 66.100 574.900 + cpu/stage2_alu_out[0] - - F (net) 9 - - - + cpu/stage3/memrw/g432/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 91.900 19.700 594.600 + cpu/stage3/memrw/n_6 - - R (net) 2 - - - + cpu/stage3/memrw/g425/Y - A1->Y F OAI31xp33_ASAP7_75t_SL 3 42.000 20.400 615.000 + dcache_we[1] - - F (net) 3 - - - + mem/g31/Y - B->Y F OR5x1_ASAP7_75t_SL 3 60.200 57.900 672.900 + mem/n_317 - - F (net) 3 - - - + mem/dcache/g14019/Y - B->Y R NAND2x1_ASAP7_75t_SL 5 54.600 27.800 700.700 + mem/dcache/n_316 - - R (net) 5 - - - + mem/dcache/g14016/Y - A->Y F INVx2_ASAP7_75t_SL 37 41.300 22.400 723.100 + mem/dcache/n_99 - - F (net) 37 - - - + mem/dcache/g13751/Y - A->Y R NAND3x1_ASAP7_75t_SL 4 85.900 41.800 764.900 + mem/dc_mem_req_rw - - R (net) 4 - - - + mem/dcache/g13730/Y - B->Y F NAND2xp5_ASAP7_75t_SL 2 59.100 14.300 779.200 + mem/dcache/n_314 - - F (net) 2 - - - + mem/dcache/g11166/Y - B->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 29.900 15.000 794.200 + mem/dcache/n_81 - - R (net) 1 - - - + mem/dcache/STATE_reg[1]/D - D R DFFHQNx1_ASAP7_75t_SL 1 40.200 0.100 794.200 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#--------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 900.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[1]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 3 0.100 0.000 900.000 +#--------------------------------------------------------------------------------------------------------------------------------------- +Path 3: MET (1.623 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[29]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.477 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.523 + Launch Clock:= 0.000 + Data Path:+ 790.900 + Slack:= 1.623 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 30.100 9.500 704.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_20 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1257__7482/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 16.700 16.700 721.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_231 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1256/Y - A->Y F INVx1_ASAP7_75t_SL 2 12.000 7.700 728.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_232 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1241__8428/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 11.600 12.100 740.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_246 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1238__5107/Y - B->Y R XOR2xp5_ASAP7_75t_SL 1 25.900 15.700 756.600 + cpu/stage1/stage1_pc4[29] - - R (net) 1 - - - + cpu/stage1/pcselmux/g989__6783/Y - A2->Y R AO21x1_ASAP7_75t_SL 1 20.400 13.700 770.300 + cpu/stage1/pcselmux/n_15 - - R (net) 1 - - - + cpu/stage1/pcselmux/g960__5526/Y - B->Y R AO21x1_ASAP7_75t_SL 2 15.800 13.700 784.000 + cpu/stage1/stage1_pc_mux_to_pc[29] - - R (net) 2 - - - + cpu/stage1/pcreg/g350__5526/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.200 6.900 790.900 + cpu/stage1/pcreg/n_30 - - F (net) 1 - - - + cpu/stage1/pcreg/register_reg[29]/D - D F DFFHQNx1_ASAP7_75t_SL 1 55.600 0.000 790.900 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[29]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 4: MET (2.921 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.579 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.421 + Launch Clock:= 0.000 + Data Path:+ 789.500 + Slack:= 2.921 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 30.100 9.500 704.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_20 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1257__7482/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 16.700 16.700 721.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_231 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1244__6783/Y - A1->Y F AOI21x1_ASAP7_75t_SL 2 12.000 9.200 730.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_243 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1243/Y - A->Y R INVx1_ASAP7_75t_SL 1 20.600 8.800 739.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_244 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1237__2398/Y - B->Y R XOR2xp5_ASAP7_75t_SL 1 13.300 15.600 754.700 + cpu/stage1/stage1_pc4[30] - - R (net) 1 - - - + cpu/stage1/pcselmux/g987__8428/Y - A2->Y R AO21x1_ASAP7_75t_SL 1 23.300 14.500 769.200 + cpu/stage1/pcselmux/n_17 - - R (net) 1 - - - + cpu/stage1/pcselmux/g962__3680/Y - B->Y R AO21x1_ASAP7_75t_SL 2 16.600 13.200 782.400 + cpu/stage1/stage1_pc_mux_to_pc[30] - - R (net) 2 - - - + cpu/stage1/pcreg/g349__8428/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 17.300 7.100 789.500 + cpu/stage1/pcreg/n_31 - - F (net) 1 - - - + cpu/stage1/pcreg/register_reg[30]/D - D F DFFHQNx1_ASAP7_75t_SL 1 56.000 0.000 789.500 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[30]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 5: MET (5.498 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.402 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.598 + Launch Clock:= 0.000 + Data Path:+ 787.100 + Slack:= 5.498 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/g392__9315/Y - B->Y F NOR2x2_ASAP7_75t_SL 4 13.500 16.500 401.000 + cpu/stage1/FE_OFN1064_stage1_inst_15 - - F (net) 4 - - - + cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y - A->Y R INVx3_ASAP7_75t_SL 1 31.600 10.900 411.900 + cpu/stage1/regfile/FE_OFN1120_n - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y - A->Y F INVx6_ASAP7_75t_SL 11 17.000 10.800 422.700 + cpu/stage1/regfile/FE_OFN1214_n - - F (net) 11 - - - + cpu/stage1/regfile/g80989/Y - A->Y F AND2x4_ASAP7_75t_SL 5 14.500 21.800 444.500 + cpu/stage1/regfile/n_171 - - F (net) 5 - - - + cpu/stage1/regfile/FE_OFC1149_n_171/Y - A->Y R INVx3_ASAP7_75t_SL 2 20.300 15.600 460.100 + cpu/stage1/regfile/FE_OFN1075_n_171 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC1240_n_171/Y - A->Y F INVx3_ASAP7_75t_SL 9 25.600 13.900 474.000 + cpu/stage1/regfile/FE_OFN1073_n_171 - - F (net) 9 - - - + cpu/stage1/regfile/g78521/Y - A->Y F AND2x4_ASAP7_75t_SL 5 22.500 27.300 501.300 + cpu/stage1/regfile/n_637 - - F (net) 5 - - - + cpu/stage1/regfile/g77393/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 1 28.500 11.100 512.400 + cpu/stage1/regfile/n_1747 - - R (net) 1 - - - + cpu/stage1/regfile/g77240/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 18.700 10.000 522.400 + cpu/stage1/regfile/n_1884 - - F (net) 1 - - - + cpu/stage1/regfile/g77015/Y - B->Y R NOR2x1_ASAP7_75t_SL 1 32.500 9.100 531.500 + cpu/stage1/regfile/n_2094 - - R (net) 1 - - - + cpu/stage1/regfile/g76883__7098/Y - B->Y F NAND3xp33_ASAP7_75t_SL 1 17.400 13.500 545.000 + cpu/stage1/rs1_mux_data[0] - - F (net) 1 - - - + cpu/stage1/data1sel_s1/g557__3680/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 26.500 19.200 564.200 + cpu/stage1_rs1[0] - - F (net) 2 - - - + cpu/stage1/pcadder/g1277__2883/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 13.500 17.600 581.800 + cpu/stage1/pcadder/n_31 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1454__7482/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 3 21.800 13.200 595.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_7 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1356__4319/Y - A1->Y F OAI21x1_ASAP7_75t_SL 2 20.400 9.600 604.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_153 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1335__1881/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 1 18.200 11.100 615.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_169 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1332__8246/Y - B->Y F NAND2x2_ASAP7_75t_SL 3 16.000 7.100 622.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_172 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1324__5526/Y - B->Y F AND2x2_ASAP7_75t_SL 2 12.200 15.200 638.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_180 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - A1->Y R AOI21x1_ASAP7_75t_SL 3 9.900 13.300 651.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_192 - - R (net) 3 - - - + cpu/stage1/pcadder/FE_OCPC1369_add_18_35_Y_add_17_34_Y_add_16_33_n_192/Y - A->Y R HB1xp67_ASAP7_75t_SL 2 25.400 21.200 672.500 + cpu/stage1/pcadder/FE_OCPN1343_add_18_35_Y_add_17_34_Y_add_16_33_n_192 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1310/Y - A->Y F INVx1_ASAP7_75t_SL 1 24.400 6.100 678.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_193 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1299__5115/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 11.200 14.600 693.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_202 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1290__5122/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 30.300 19.100 712.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_207 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1273__6260/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 28.600 18.500 730.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_217 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1254__1881/Y - A1->Y F OAI21xp5_ASAP7_75t_L 1 33.000 16.000 746.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_234 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1247__2802/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 22.700 16.700 763.500 + cpu/stage1/stage1_pc4[15] - - F (net) 1 - - - + cpu/stage1/pcselmux/g934__3680/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 15.300 15.400 778.900 + cpu/stage1/stage1_pc_mux_to_pc[15] - - F (net) 2 - - - + cpu/stage1/pcreg/g355__1705/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 15.100 8.200 787.100 + cpu/stage1/pcreg/n_25 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[15]/D - D R DFFHQNx1_ASAP7_75t_SL 1 52.700 0.000 787.100 +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[15]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 6: MET (7.177 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[23]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.623 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.377 + Launch Clock:= 0.000 + Data Path:+ 785.200 + Slack:= 7.177 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/g392__9315/Y - B->Y F NOR2x2_ASAP7_75t_SL 4 13.500 16.500 401.000 + cpu/stage1/FE_OFN1064_stage1_inst_15 - - F (net) 4 - - - + cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y - A->Y R INVx3_ASAP7_75t_SL 1 31.600 10.900 411.900 + cpu/stage1/regfile/FE_OFN1120_n - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y - A->Y F INVx6_ASAP7_75t_SL 11 17.000 10.800 422.700 + cpu/stage1/regfile/FE_OFN1214_n - - F (net) 11 - - - + cpu/stage1/regfile/g80989/Y - A->Y F AND2x4_ASAP7_75t_SL 5 14.500 21.800 444.500 + cpu/stage1/regfile/n_171 - - F (net) 5 - - - + cpu/stage1/regfile/FE_OFC1149_n_171/Y - A->Y R INVx3_ASAP7_75t_SL 2 20.300 15.300 459.800 + cpu/stage1/regfile/FE_OFN1075_n_171 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC1150_n_171/Y - A->Y F INVx6_ASAP7_75t_SL 13 25.600 12.700 472.500 + cpu/stage1/regfile/FE_OFN1077_n_171 - - F (net) 13 - - - + cpu/stage1/regfile/FE_OFC1152_n_171/Y - A->Y F BUFx6f_ASAP7_75t_SL 10 21.500 18.900 491.400 + cpu/stage1/regfile/FE_OFN1079_n_171 - - F (net) 10 - - - + cpu/stage1/regfile/g78044/Y - B2->Y F AO22x2_ASAP7_75t_SL 1 12.300 16.600 508.000 + cpu/stage1/regfile/n_1095 - - F (net) 1 - - - + cpu/stage1/regfile/g77303/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 9.800 8.400 516.400 + cpu/stage1/regfile/n_1826 - - R (net) 1 - - - + cpu/stage1/regfile/g77043/Y - C->Y F NAND3xp33_ASAP7_75t_SL 1 15.900 13.700 530.100 + cpu/stage1/regfile/n_2066 - - F (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - B->Y R NOR2x1_ASAP7_75t_SL 1 27.400 9.900 540.000 + cpu/stage1/regfile/n_2178 - - R (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y F NAND3x1_ASAP7_75t_SL 1 17.900 13.500 553.500 + cpu/stage1/rs1_mux_data[8] - - F (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 31.400 24.500 578.000 + cpu/stage1_rs1[8] - - F (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 16.400 19.200 597.200 + cpu/stage1/pcadder/n_39 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 3 20.500 11.500 608.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - R (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y F OAI21x1_ASAP7_75t_SL 2 18.100 8.500 617.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 18.300 8.200 625.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 12.800 14.500 639.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y R OA21x2_ASAP7_75t_SL 1 9.700 14.100 654.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y F OAI21x1_ASAP7_75t_SL 3 10.500 19.000 673.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1280__3680/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 32.600 16.800 689.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_213 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1270__5477/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 29.300 18.000 707.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_220 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1255__5115/Y - A1->Y R AOI21xp5_ASAP7_75t_L 2 26.900 22.700 730.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_233 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1242__5526/Y - A1->Y F OAI21xp5_ASAP7_75t_SL 1 38.100 13.700 744.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_245 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1239__6260/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 24.900 17.500 761.700 + cpu/stage1/stage1_pc4[23] - - F (net) 1 - - - + cpu/stage1/pcselmux/g933__6783/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 15.300 15.100 776.800 + cpu/stage1/stage1_pc_mux_to_pc[23] - - F (net) 2 - - - + cpu/stage1/pcreg/g364__6161/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.800 8.400 785.200 + cpu/stage1/pcreg/n_16 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[23]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.000 0.000 785.200 +#-------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[23]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 7: MET (7.936 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.064 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.936 + Launch Clock:= 0.000 + Data Path:+ 784.000 + Slack:= 7.936 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 0.000 + cpu/s1_to_s2_inst/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_inst/register_reg[2]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_SL 1 0.100 30.000 30.000 + cpu/stage2_inst[2] - - R (net) 1 - - - + cpu/FE_OFC948_stage2_inst_2/Y - A->Y F INVx1_ASAP7_75t_SL 2 13.500 6.400 36.400 + cpu/FE_OFN851_stage2_inst_2 - - F (net) 2 - - - + cpu/FE_OFC952_stage2_inst_2/Y - A->Y R INVx1_ASAP7_75t_SL 13 9.500 29.600 66.000 + cpu/FE_OFN850_stage2_inst_2 - - R (net) 13 - - - + cpu/FE_OFC670_stage2_inst_2/Y - A->Y R BUFx2_ASAP7_75t_SL 9 59.500 25.900 91.900 + cpu/FE_OFN854_stage2_inst_2 - - R (net) 9 - - - + cpu/stage2/alusel/g764/Y - B->Y R OR2x2_ASAP7_75t_SL 3 25.000 15.600 107.500 + cpu/stage2/alusel/n_5 - - R (net) 3 - - - + cpu/stage2/alusel/g759/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 10.800 13.500 121.000 + cpu/stage2/alusel/n_9 - - F (net) 2 - - - + cpu/stage2/alusel/g755/Y - B->Y R NAND2xp5_ASAP7_75t_SL 3 26.600 18.400 139.400 + cpu/stage2/alusel/n_14 - - R (net) 3 - - - + cpu/stage2/alusel/FE_OFC746_n_14/Y - A->Y F INVx1_ASAP7_75t_SL 2 29.400 7.300 146.700 + cpu/stage2/alusel/n_13 - - F (net) 2 - - - + cpu/stage2/alusel/g751/Y - B->Y F AND2x2_ASAP7_75t_SL 3 13.600 15.200 161.900 + cpu/stage2/alusel/n_17 - - F (net) 3 - - - + cpu/stage2/alusel/g746/Y - B1->Y F AO221x1_ASAP7_75t_SL 1 12.100 18.700 180.600 + cpu/stage2/ALUop[1] - - F (net) 1 - - - + cpu/stage2/alu/FE_OFC626_ALUop_1/Y - A->Y R INVx1_ASAP7_75t_SL 5 13.400 21.500 202.100 + cpu/stage2/alu/n_0 - - R (net) 5 - - - + cpu/stage2/alu/FE_OFC627_ALUop_1/Y - A->Y F INVx1_ASAP7_75t_SL 4 37.200 15.600 217.700 + cpu/stage2/alu/FE_OFN823_ALUop_1 - - F (net) 4 - - - + cpu/stage2/alu/g3304/Y - B->Y R NOR2x1_ASAP7_75t_SL 3 25.000 13.200 230.900 + cpu/stage2/alu/n_194 - - R (net) 3 - - - + cpu/stage2/alu/g3302/Y - A->Y R AND3x4_ASAP7_75t_SL 9 23.600 26.700 257.600 + cpu/stage2/alu/n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC775_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 3 29.000 15.400 273.000 + cpu/stage2/alu/FE_OFN922_n_325 - - F (net) 3 - - - + cpu/stage2/alu/FE_OFC778_n_325/Y - A->Y R INVx3_ASAP7_75t_SL 9 24.200 24.000 297.000 + cpu/stage2/alu/FE_OFN925_n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC782_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 7 44.400 41.300 338.300 + cpu/stage2/alu/FE_OFN929_n_325 - - F (net) 7 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1722/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 2 72.200 24.100 362.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_36 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1655/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 45.200 24.300 386.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_116 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A1->Y F OA21x2_ASAP7_75t_SL 3 43.900 22.200 408.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y R OAI321xp33_ASAP7_75t_SL 1 13.300 17.300 426.200 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y F INVx1_ASAP7_75t_SL 2 42.800 11.500 437.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 21.200 19.000 456.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 10.600 16.200 472.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 10.800 9.200 482.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y R OR2x2_ASAP7_75t_SL 3 18.000 17.600 499.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y F AOI31xp67_ASAP7_75t_SL 3 15.800 16.400 516.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 34.100 15.700 531.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y R OR2x2_ASAP7_75t_SL 3 32.100 25.500 557.300 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 27.300 15.500 572.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y F NAND2xp5_ASAP7_75t_L 2 12.900 11.700 584.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 18.800 14.600 599.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 37.100 10.300 609.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y R INVx1_ASAP7_75t_SL 3 20.500 13.500 622.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.500 16.600 639.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 16.200 12.900 652.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 22.100 19.100 671.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 11.700 17.200 688.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 12.100 17.200 705.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1504/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 11.900 15.900 721.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_238 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1503/Y - B->Y F XOR2xp5_ASAP7_75t_SL 1 10.200 12.200 734.000 + cpu/stage2/alu/n_322 - - F (net) 1 - - - + cpu/stage2/alu/g5521/Y - A2->Y F AO21x1_ASAP7_75t_L 4 19.200 31.900 765.900 + dcache_addr[31] - - F (net) 4 - - - + cpu/stage3/csr/g178/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 33.800 18.100 784.000 + cpu/stage3/csr/n_17 - - R (net) 1 - - - + cpu/stage3/csr/csr_reg[31]/D - D R DFFHQNx1_ASAP7_75t_SL 1 56.600 0.700 784.000 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage3/csr/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage3/csr/csr_reg[31]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------------- +Path 8: MET (8.068 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 4.732 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 795.268 + Launch Clock:= 0.000 + Data Path:+ 787.200 + Slack:= 8.068 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 30.100 9.500 704.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_20 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1263__2883/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 16.700 19.200 723.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_226 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1249__5122/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 32.700 13.900 737.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_238 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1240__4319/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 1 27.500 12.900 750.400 + cpu/stage1/stage1_pc4[27] - - R (net) 1 - - - + cpu/stage1/pcselmux/g999__5115/Y - B->Y F NAND2xp5_ASAP7_75t_L 1 21.100 9.800 760.200 + cpu/stage1/pcselmux/n_5 - - F (net) 1 - - - + cpu/stage1/pcselmux/g932__5526/Y - A->Y R NAND2xp5_ASAP7_75t_SL 2 37.400 16.400 776.600 + cpu/stage1/stage1_pc_mux_to_pc[27] - - R (net) 2 - - - + cpu/stage1/pcreg/g352__3680/Y - B->Y F NAND2xp5_ASAP7_75t_L 1 25.200 10.600 787.200 + cpu/stage1/pcreg/n_28 - - F (net) 1 - - - + cpu/stage1/pcreg/register_reg[27]/D - D F DFFHQNx1_ASAP7_75t_SL 1 44.800 0.100 787.200 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 9: MET (8.384 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[22]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.116 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.884 + Launch Clock:= 0.000 + Data Path:+ 782.500 + Slack:= 8.384 + Timing Path: + +#--------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 7.800 392.300 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g397__7410/Y - B->Y F AND2x4_ASAP7_75t_SL 44 11.400 68.300 460.600 + cpu/stage1_inst[22] - - F (net) 44 - - - + cpu/stage1/regfile/g80975/Y - A->Y R INVx4_ASAP7_75t_SL 19 195.500 49.100 509.700 + cpu/stage1/regfile/n_179 - - R (net) 19 - - - + cpu/stage1/regfile/g79812/Y - A->Y F NOR2xp33_ASAP7_75t_SL 3 91.500 34.800 544.500 + cpu/stage1/regfile/n_342 - - F (net) 3 - - - + cpu/stage1/regfile/g79319/Y - A->Y R INVx1_ASAP7_75t_SL 2 55.600 12.400 556.900 + cpu/stage1/regfile/n_341 - - R (net) 2 - - - + cpu/stage1/regfile/g78503/Y - B->Y F NOR2xp33_ASAP7_75t_SL 7 21.600 74.000 630.900 + cpu/stage1/regfile/n_662 - - F (net) 7 - - - + cpu/stage1/regfile/g77810/Y - A2->Y R AOI22xp5_ASAP7_75t_SL 1 144.900 20.600 651.500 + cpu/stage1/regfile/n_1330 - - R (net) 1 - - - + cpu/stage1/regfile/g77085/Y - C->Y F NAND5xp2_ASAP7_75t_SL 1 52.400 22.300 673.800 + cpu/stage1/regfile/n_2024 - - F (net) 1 - - - + cpu/stage1/regfile/g77004/Y - B->Y R AOI211xp5_ASAP7_75t_SL 1 48.900 24.900 698.700 + cpu/stage1/regfile/n_2105 - - R (net) 1 - - - + cpu/stage1/regfile/g76906__1617/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 43.900 46.700 745.400 + cpu/stage1/rs2_mux_data[22] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g562__5122/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 97.800 25.700 771.100 + cpu/stage1_rs2[22] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g443__7482/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.700 11.400 782.500 + cpu/s1_to_s2_rs2/n_8 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[22]/D - D R DFFHQNx1_ASAP7_75t_SL 1 62.800 0.400 782.500 +#--------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[22]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 10: MET (11.245 ps) Setup Check with Pin mem/dcache/STATE_reg[2]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) mem/dcache/STATE_reg[2]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 5.354 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 794.646 + Launch Clock:= 0.000 + Data Path:+ 783.400 + Slack:= 11.245 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2318/Y - B1->Y F OAI221xp5_ASAP7_75t_SL 1 33.100 15.600 168.300 + cpu/stage3/wb_dmem[0] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1103/Y - A1->Y F AO21x1_ASAP7_75t_SL 3 28.600 22.400 190.700 + cpu/wb_data[0] - - F (net) 3 - - - + cpu/stage2/rs2DataSel/g563/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 17.700 29.600 220.300 + cpu/stage2/stage2_rs2_data[0] - - F (net) 8 - - - + cpu/stage2/bselmux/g583/Y - A->Y R NAND2xp5_ASAP7_75t_SL 1 31.200 12.400 232.700 + cpu/stage2/bselmux/n_6 - - R (net) 1 - - - + cpu/stage2/bselmux/g559/Y - A->Y R AND2x2_ASAP7_75t_SL 2 23.400 23.000 255.700 + cpu/stage2/stage2_alu_in2[0] - - R (net) 2 - - - + cpu/stage2/alu/FE_OFC692_n_30/Y - A->Y F INVx3_ASAP7_75t_SL 24 23.300 22.500 278.200 + cpu/stage2/alu/FE_OFN867_n_30 - - F (net) 24 - - - + cpu/stage2/alu/FE_OFC696_n_30/Y - A->Y R INVx1_ASAP7_75t_SL 14 39.300 38.900 317.100 + cpu/stage2/alu/FE_OFN871_n_30 - - R (net) 14 - - - + cpu/stage2/alu/lt_29_31_g1474/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 70.300 11.700 328.800 + cpu/stage2/alu/lt_29_31_n_55 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1456/Y - C->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 39.000 15.000 343.800 + cpu/stage2/alu/lt_29_31_n_73 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1448/Y - A->Y F MAJIxp5_ASAP7_75t_SL 1 39.100 11.600 355.400 + cpu/stage2/alu/lt_29_31_n_81 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1445/Y - A->Y R MAJIxp5_ASAP7_75t_SL 1 42.100 18.000 373.400 + cpu/stage2/alu/lt_29_31_n_84 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1444/Y - A1->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 44.600 17.000 390.400 + cpu/stage2/alu/lt_29_31_n_85 - - F (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1443/Y - A1->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 33.000 33.100 423.500 + cpu/stage2/alu/lt_29_31_n_86 - - R (net) 1 - - - + cpu/stage2/alu/lt_29_31_g1442/Y - A1->Y F AOI321xp33_ASAP7_75t_SL 1 67.400 40.100 463.600 + cpu/stage2/alu/n_324 - - F (net) 1 - - - + cpu/stage2/alu/g5667/Y - B1->Y R AOI33xp33_ASAP7_75t_SL 1 70.300 29.800 493.400 + cpu/stage2/alu/n_54 - - R (net) 1 - - - + cpu/stage2/alu/g5520/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 52.900 15.400 508.800 + cpu/stage2/alu/n_192 - - F (net) 1 - - - + cpu/stage2/alu/g5502/Y - C->Y F AO221x1_ASAP7_75t_SL 9 37.700 66.100 574.900 + cpu/stage2_alu_out[0] - - F (net) 9 - - - + cpu/stage3/memrw/g432/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 91.900 19.700 594.600 + cpu/stage3/memrw/n_6 - - R (net) 2 - - - + cpu/stage3/memrw/g425/Y - A1->Y F OAI31xp33_ASAP7_75t_SL 3 42.000 20.400 615.000 + dcache_we[1] - - F (net) 3 - - - + mem/g31/Y - B->Y F OR5x1_ASAP7_75t_SL 3 60.200 57.900 672.900 + mem/n_317 - - F (net) 3 - - - + mem/dcache/g14019/Y - B->Y R NAND2x1_ASAP7_75t_SL 5 54.600 27.800 700.700 + mem/dcache/n_316 - - R (net) 5 - - - + mem/dcache/g14016/Y - A->Y F INVx2_ASAP7_75t_SL 37 41.300 22.400 723.100 + mem/dcache/n_99 - - F (net) 37 - - - + mem/dcache/g13751/Y - A->Y R NAND3x1_ASAP7_75t_SL 4 85.900 41.800 764.900 + mem/dc_mem_req_rw - - R (net) 4 - - - + mem/dcache/FE_OFC439_dc_mem_req_rw/Y - A->Y F INVx1_ASAP7_75t_SL 1 59.100 6.300 771.200 + mem/dcache/n_2 - - F (net) 1 - - - + mem/dcache/g11190/Y - B->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 19.100 12.200 783.400 + mem/dcache/n_57 - - R (net) 1 - - - + mem/dcache/STATE_reg[2]/D - D R DFFHQNx1_ASAP7_75t_SL 1 38.700 0.000 783.400 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#--------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + mem/dcache/CLKGATE_RC_CG_HIER_INST41/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 3 4.000 0.000 900.000 + mem/dcache/CLKGATE_rc_gclk - - R (net) 3 - - - + mem/dcache/STATE_reg[2]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 3 0.100 0.000 900.000 +#--------------------------------------------------------------------------------------------------------------------------------------- +Path 11: MET (11.743 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[22]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.657 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.343 + Launch Clock:= 0.000 + Data Path:+ 780.600 + Slack:= 11.743 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1280__3680/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_213 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1270__5477/Y - B->Y R NOR2xp33_ASAP7_75t_SL 2 30.200 19.500 714.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_220 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1255__5115/Y - A1->Y F AOI21xp5_ASAP7_75t_L 2 34.800 20.800 735.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_233 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1245__3680/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 29.700 20.300 755.500 + cpu/stage1/stage1_pc4[22] - - F (net) 1 - - - + cpu/stage1/pcselmux/g936__2802/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 22.200 16.600 772.100 + cpu/stage1/stage1_pc_mux_to_pc[22] - - F (net) 2 - - - + cpu/stage1/pcreg/g378__5526/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 15.100 8.500 780.600 + cpu/stage1/pcreg/n_2 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[22]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.200 0.000 780.600 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[22]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 12: MET (14.886 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[16]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[16]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.014 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.986 + Launch Clock:= 0.000 + Data Path:+ 776.100 + Slack:= 14.886 + Timing Path: + +#--------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 7.800 392.300 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g397__7410/Y - B->Y F AND2x4_ASAP7_75t_SL 44 11.400 68.300 460.600 + cpu/stage1_inst[22] - - F (net) 44 - - - + cpu/stage1/regfile/g80975/Y - A->Y R INVx4_ASAP7_75t_SL 19 195.500 49.100 509.700 + cpu/stage1/regfile/n_179 - - R (net) 19 - - - + cpu/stage1/regfile/g79812/Y - A->Y F NOR2xp33_ASAP7_75t_SL 3 91.500 34.800 544.500 + cpu/stage1/regfile/n_342 - - F (net) 3 - - - + cpu/stage1/regfile/g79319/Y - A->Y R INVx1_ASAP7_75t_SL 2 55.600 12.400 556.900 + cpu/stage1/regfile/n_341 - - R (net) 2 - - - + cpu/stage1/regfile/g78503/Y - B->Y F NOR2xp33_ASAP7_75t_SL 7 21.600 73.800 630.700 + cpu/stage1/regfile/n_662 - - F (net) 7 - - - + cpu/stage1/regfile/g77583/Y - A2->Y R AOI22xp5_ASAP7_75t_SL 1 144.800 20.500 651.200 + cpu/stage1/regfile/n_1553 - - R (net) 1 - - - + cpu/stage1/regfile/g77069/Y - C->Y F NAND5xp2_ASAP7_75t_SL 1 52.300 19.300 670.500 + cpu/stage1/regfile/n_2040 - - F (net) 1 - - - + cpu/stage1/regfile/g77003/Y - B->Y R AOI211xp5_ASAP7_75t_SL 1 42.500 20.500 691.000 + cpu/stage1/regfile/n_2106 - - R (net) 1 - - - + cpu/stage1/regfile/g76905__3680/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 35.700 47.700 738.700 + cpu/stage1/rs2_mux_data[16] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g555__8428/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 102.900 26.200 764.900 + cpu/stage1_rs2[16] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g436__1705/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 13.100 11.200 776.100 + cpu/s1_to_s2_rs2/n_15 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[16]/D - D R DFFHQNx1_ASAP7_75t_SL 1 62.200 0.300 776.100 +#--------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[16]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 13: MET (15.388 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.012 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.988 + Launch Clock:= 0.000 + Data Path:+ 777.600 + Slack:= 15.388 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 -0.000 + cpu/s1_to_s2_inst/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_inst/register_reg[2]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_SL 1 0.100 30.000 30.000 + cpu/stage2_inst[2] - - R (net) 1 - - - + cpu/FE_OFC948_stage2_inst_2/Y - A->Y F INVx1_ASAP7_75t_SL 2 13.500 6.400 36.400 + cpu/FE_OFN851_stage2_inst_2 - - F (net) 2 - - - + cpu/FE_OFC952_stage2_inst_2/Y - A->Y R INVx1_ASAP7_75t_SL 13 9.500 29.600 66.000 + cpu/FE_OFN850_stage2_inst_2 - - R (net) 13 - - - + cpu/FE_OFC670_stage2_inst_2/Y - A->Y R BUFx2_ASAP7_75t_SL 9 59.500 25.900 91.900 + cpu/FE_OFN854_stage2_inst_2 - - R (net) 9 - - - + cpu/stage2/alusel/g764/Y - B->Y R OR2x2_ASAP7_75t_SL 3 25.000 15.600 107.500 + cpu/stage2/alusel/n_5 - - R (net) 3 - - - + cpu/stage2/alusel/g759/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 10.800 13.500 121.000 + cpu/stage2/alusel/n_9 - - F (net) 2 - - - + cpu/stage2/alusel/g755/Y - B->Y R NAND2xp5_ASAP7_75t_SL 3 26.600 18.400 139.400 + cpu/stage2/alusel/n_14 - - R (net) 3 - - - + cpu/stage2/alusel/FE_OFC746_n_14/Y - A->Y F INVx1_ASAP7_75t_SL 2 29.400 7.300 146.700 + cpu/stage2/alusel/n_13 - - F (net) 2 - - - + cpu/stage2/alusel/g751/Y - B->Y F AND2x2_ASAP7_75t_SL 3 13.600 15.200 161.900 + cpu/stage2/alusel/n_17 - - F (net) 3 - - - + cpu/stage2/alusel/g746/Y - B1->Y F AO221x1_ASAP7_75t_SL 1 12.100 18.700 180.600 + cpu/stage2/ALUop[1] - - F (net) 1 - - - + cpu/stage2/alu/FE_OFC626_ALUop_1/Y - A->Y R INVx1_ASAP7_75t_SL 5 13.400 21.500 202.100 + cpu/stage2/alu/n_0 - - R (net) 5 - - - + cpu/stage2/alu/FE_OFC627_ALUop_1/Y - A->Y F INVx1_ASAP7_75t_SL 4 37.200 15.600 217.700 + cpu/stage2/alu/FE_OFN823_ALUop_1 - - F (net) 4 - - - + cpu/stage2/alu/g3304/Y - B->Y R NOR2x1_ASAP7_75t_SL 3 25.000 13.200 230.900 + cpu/stage2/alu/n_194 - - R (net) 3 - - - + cpu/stage2/alu/g3302/Y - A->Y R AND3x4_ASAP7_75t_SL 9 23.600 26.700 257.600 + cpu/stage2/alu/n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC775_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 3 29.000 15.400 273.000 + cpu/stage2/alu/FE_OFN922_n_325 - - F (net) 3 - - - + cpu/stage2/alu/FE_OFC778_n_325/Y - A->Y R INVx3_ASAP7_75t_SL 9 24.200 24.000 297.000 + cpu/stage2/alu/FE_OFN925_n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC782_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 7 44.400 41.300 338.300 + cpu/stage2/alu/FE_OFN929_n_325 - - F (net) 7 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1722/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 2 72.200 24.100 362.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_36 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1655/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 45.200 24.300 386.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_116 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A1->Y F OA21x2_ASAP7_75t_SL 3 43.900 22.200 408.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y R OAI321xp33_ASAP7_75t_SL 1 13.300 17.300 426.200 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y F INVx1_ASAP7_75t_SL 2 42.800 11.500 437.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 21.200 19.000 456.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 10.600 16.200 472.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 10.800 9.200 482.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y R OR2x2_ASAP7_75t_SL 3 18.000 17.600 499.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y F AOI31xp67_ASAP7_75t_SL 3 15.800 16.400 516.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 34.100 15.700 531.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y R OR2x2_ASAP7_75t_SL 3 32.100 25.500 557.300 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 27.300 15.500 572.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y F NAND2xp5_ASAP7_75t_L 2 12.900 11.700 584.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 18.800 14.600 599.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 37.100 10.300 609.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y R INVx1_ASAP7_75t_SL 3 20.500 13.500 622.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.500 16.600 639.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 16.200 12.900 652.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 22.100 19.100 671.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 11.700 17.200 688.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 12.100 17.200 705.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1504/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 11.900 15.900 721.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_238 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1503/Y - B->Y F XOR2xp5_ASAP7_75t_SL 1 10.200 12.200 734.000 + cpu/stage2/alu/n_322 - - F (net) 1 - - - + cpu/stage2/alu/g5521/Y - A2->Y F AO21x1_ASAP7_75t_L 4 19.200 31.400 765.400 + dcache_addr[31] - - F (net) 4 - - - + cpu/s2_to_s3_alu/g420__5477/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 33.700 12.200 777.600 + cpu/s2_to_s3_alu/n_31 - - R (net) 1 - - - + cpu/s2_to_s3_alu/register_reg[31]/D - D R DFFHQNx1_ASAP7_75t_SL 1 50.400 0.100 777.600 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s2_to_s3_alu/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s2_to_s3_alu/register_reg[31]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 14: MET (16.484 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[20]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[20]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.316 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.684 + Launch Clock:= 0.000 + Data Path:+ 775.200 + Slack:= 16.484 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.600 519.900 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y R AND2x2_ASAP7_75t_L 33 160.100 109.800 629.700 + cpu/stage1/regfile/n_266 - - R (net) 33 - - - + cpu/stage1/regfile/g77177/Y - B1->Y R AO222x2_ASAP7_75t_SL 1 191.800 49.800 679.500 + cpu/stage1/regfile/n_1938 - - R (net) 1 - - - + cpu/stage1/regfile/g77022/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 18.100 10.800 690.300 + cpu/stage1/regfile/n_2087 - - F (net) 1 - - - + cpu/stage1/regfile/g76958__8428/Y - A->Y R NAND5xp2_ASAP7_75t_SL 1 75.300 14.700 705.000 + cpu/stage1/regfile/n_2147 - - R (net) 1 - - - + cpu/stage1/regfile/g76903__5526/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 36.600 8.400 713.400 + cpu/stage1/regfile/n_2170 - - F (net) 1 - - - + cpu/stage1/regfile/g76895__7410/Y - B->Y R NAND5xp2_ASAP7_75t_SL 1 63.400 33.600 747.000 + cpu/stage1/rs2_mux_data[20] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g571__9315/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 52.000 21.400 768.400 + cpu/stage1_rs2[20] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g441__1881/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 14.100 6.800 775.200 + cpu/s1_to_s2_rs2/n_10 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[20]/D - D F DFFHQNx1_ASAP7_75t_SL 1 58.900 0.000 775.200 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[20]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 15: MET (16.826 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.674 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.326 + Launch Clock:= 0.000 + Data Path:+ 775.500 + Slack:= 16.826 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/g392__9315/Y - B->Y F NOR2x2_ASAP7_75t_SL 4 13.500 16.500 401.000 + cpu/stage1/FE_OFN1064_stage1_inst_15 - - F (net) 4 - - - + cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y - A->Y R INVx3_ASAP7_75t_SL 1 31.600 10.900 411.900 + cpu/stage1/regfile/FE_OFN1120_n - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y - A->Y F INVx6_ASAP7_75t_SL 11 17.000 10.800 422.700 + cpu/stage1/regfile/FE_OFN1214_n - - F (net) 11 - - - + cpu/stage1/regfile/g80989/Y - A->Y F AND2x4_ASAP7_75t_SL 5 14.500 21.800 444.500 + cpu/stage1/regfile/n_171 - - F (net) 5 - - - + cpu/stage1/regfile/FE_OFC1149_n_171/Y - A->Y R INVx3_ASAP7_75t_SL 2 20.300 15.300 459.800 + cpu/stage1/regfile/FE_OFN1075_n_171 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC1150_n_171/Y - A->Y F INVx6_ASAP7_75t_SL 13 25.600 12.700 472.500 + cpu/stage1/regfile/FE_OFN1077_n_171 - - F (net) 13 - - - + cpu/stage1/regfile/FE_OFC1152_n_171/Y - A->Y F BUFx6f_ASAP7_75t_SL 10 21.500 18.900 491.400 + cpu/stage1/regfile/FE_OFN1079_n_171 - - F (net) 10 - - - + cpu/stage1/regfile/g78044/Y - B2->Y F AO22x2_ASAP7_75t_SL 1 12.300 16.600 508.000 + cpu/stage1/regfile/n_1095 - - F (net) 1 - - - + cpu/stage1/regfile/g77303/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 9.800 8.400 516.400 + cpu/stage1/regfile/n_1826 - - R (net) 1 - - - + cpu/stage1/regfile/g77043/Y - C->Y F NAND3xp33_ASAP7_75t_SL 1 15.900 13.700 530.100 + cpu/stage1/regfile/n_2066 - - F (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - B->Y R NOR2x1_ASAP7_75t_SL 1 27.400 9.900 540.000 + cpu/stage1/regfile/n_2178 - - R (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y F NAND3x1_ASAP7_75t_SL 1 17.900 13.500 553.500 + cpu/stage1/rs1_mux_data[8] - - F (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 31.400 24.500 578.000 + cpu/stage1_rs1[8] - - F (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 16.400 19.200 597.200 + cpu/stage1/pcadder/n_39 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 3 20.500 11.500 608.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - R (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y F OAI21x1_ASAP7_75t_SL 2 18.100 8.500 617.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 18.300 8.200 625.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 12.800 14.500 639.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y R OA21x2_ASAP7_75t_SL 1 9.700 14.100 654.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y F OAI21x1_ASAP7_75t_SL 3 10.500 19.100 673.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1295/Y - A->Y R INVx1_ASAP7_75t_SL 2 32.600 13.000 686.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_203 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1288__1705/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 20.100 16.500 702.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_209 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1272__5107/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 33.300 17.700 720.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_218 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1253__6131/Y - A1->Y F OAI21xp5_ASAP7_75t_SL 1 31.400 12.900 733.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_235 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1246__1617/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 22.700 18.100 751.300 + cpu/stage1/stage1_pc4[19] - - F (net) 1 - - - + cpu/stage1/pcselmux/g947__9315/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 18.200 15.600 766.900 + cpu/stage1/stage1_pc_mux_to_pc[19] - - F (net) 2 - - - + cpu/stage1/pcreg/g360__1881/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.800 8.600 775.500 + cpu/stage1/pcreg/n_20 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[19]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.300 0.100 775.500 +#-------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[19]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 16: MET (18.101 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.799 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.201 + Launch Clock:= 0.000 + Data Path:+ 773.100 + Slack:= 18.101 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.700 520.000 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 160.100 34.400 554.400 + cpu/stage1/regfile/n_345 - - F (net) 4 - - - + cpu/stage1/regfile/g78531/Y - B->Y R NOR2xp67_ASAP7_75t_SL 12 76.500 102.200 656.600 + cpu/stage1/regfile/n_622 - - R (net) 12 - - - + cpu/stage1/regfile/g77643/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 195.400 23.500 680.100 + cpu/stage1/regfile/n_1497 - - F (net) 1 - - - + cpu/stage1/regfile/g77150/Y - C->Y R NAND3xp33_ASAP7_75t_SL 1 73.400 21.200 701.300 + cpu/stage1/regfile/n_1959 - - R (net) 1 - - - + cpu/stage1/regfile/g77073/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 36.300 11.400 712.700 + cpu/stage1/regfile/n_2036 - - F (net) 1 - - - + cpu/stage1/regfile/g76953__5477/Y - A->Y R NAND5xp2_ASAP7_75t_SL 1 57.500 28.500 741.200 + cpu/stage1/rs2_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g573__2883/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 53.900 23.500 764.700 + cpu/stage1_rs2[8] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g428__6260/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 17.300 8.400 773.100 + cpu/s1_to_s2_rs2/n_23 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[8]/D - D F DFFHQNx1_ASAP7_75t_SL 1 60.800 0.100 773.100 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[8]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 17: MET (19.622 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[7]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[7]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.878 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.122 + Launch Clock:= 0.000 + Data Path:+ 771.500 + Slack:= 19.622 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80394/Y - B->Y R NAND2xp5_ASAP7_75t_SL 3 27.100 16.000 462.300 + cpu/stage1/regfile/n_250 - - R (net) 3 - - - + cpu/stage1/regfile/g79869/Y - A->Y F INVx1_ASAP7_75t_SL 4 27.100 12.300 474.600 + cpu/stage1/regfile/n_249 - - F (net) 4 - - - + cpu/stage1/regfile/g79860/Y - A->Y F AND2x2_ASAP7_75t_SL 27 19.400 81.600 556.200 + cpu/stage1/regfile/n_277 - - F (net) 27 - - - + cpu/stage1/regfile/g79348/Y - A->Y R INVx1_ASAP7_75t_SL 2 156.600 30.400 586.600 + cpu/stage1/regfile/n_276 - - R (net) 2 - - - + cpu/stage1/regfile/g78488/Y - B->Y F NOR2xp33_ASAP7_75t_SL 5 54.900 75.800 662.400 + cpu/stage1/regfile/n_681 - - F (net) 5 - - - + cpu/stage1/regfile/g77645/Y - A2->Y R AOI22xp5_ASAP7_75t_SL 1 144.600 20.900 683.300 + cpu/stage1/regfile/n_1495 - - R (net) 1 - - - + cpu/stage1/regfile/g77151/Y - C->Y F NAND3xp33_ASAP7_75t_SL 1 52.800 8.500 691.800 + cpu/stage1/regfile/n_1958 - - F (net) 1 - - - + cpu/stage1/regfile/g76907__2802/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 24.600 15.600 707.400 + cpu/stage1/regfile/n_2169 - - R (net) 1 - - - + cpu/stage1/regfile/g76894__1666/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 78.100 31.100 738.500 + cpu/stage1/rs2_mux_data[7] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g575__1666/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 61.400 22.500 761.000 + cpu/stage1_rs2[7] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g427__5107/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 11.000 10.500 771.500 + cpu/s1_to_s2_rs2/n_24 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[7]/D - D R DFFHQNx1_ASAP7_75t_SL 1 61.400 0.300 771.500 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[7]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 18: MET (20.159 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.341 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.659 + Launch Clock:= 0.000 + Data Path:+ 771.500 + Slack:= 20.159 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.700 520.000 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 160.100 34.400 554.400 + cpu/stage1/regfile/n_345 - - F (net) 4 - - - + cpu/stage1/regfile/g78528/Y - B->Y R NOR2xp67_ASAP7_75t_SL 12 76.500 104.700 659.100 + cpu/stage1/regfile/n_625 - - R (net) 12 - - - + cpu/stage1/regfile/g77227/Y - B1->Y R AO222x2_ASAP7_75t_SL 1 203.100 51.600 710.700 + cpu/stage1/regfile/n_1897 - - R (net) 1 - - - + cpu/stage1/regfile/g77007/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 17.700 10.800 721.500 + cpu/stage1/regfile/n_2102 - - F (net) 1 - - - + cpu/stage1/regfile/g76922__1666/Y - A->Y R NAND5xp2_ASAP7_75t_SL 1 61.200 14.100 735.600 + cpu/stage1/regfile/n_2161 - - R (net) 1 - - - + cpu/stage1/regfile/g76882__8246/Y - B->Y R AO21x1_ASAP7_75t_SL 1 35.400 12.900 748.500 + cpu/stage1/rs2_mux_data[19] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g574__2346/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 16.100 16.000 764.500 + cpu/stage1_rs2[19] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g440__6131/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 13.800 7.000 771.500 + cpu/s1_to_s2_rs2/n_11 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[19]/D - D F DFFHQNx1_ASAP7_75t_SL 1 59.000 0.100 771.500 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[19]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 19: MET (21.328 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[13]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[13]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.572 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.428 + Launch Clock:= 0.000 + Data Path:+ 771.100 + Slack:= 21.328 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/g392__9315/Y - B->Y F NOR2x2_ASAP7_75t_SL 4 13.500 16.500 401.000 + cpu/stage1/FE_OFN1064_stage1_inst_15 - - F (net) 4 - - - + cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y - A->Y R INVx3_ASAP7_75t_SL 1 31.600 10.900 411.900 + cpu/stage1/regfile/FE_OFN1120_n - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y - A->Y F INVx6_ASAP7_75t_SL 11 17.000 10.800 422.700 + cpu/stage1/regfile/FE_OFN1214_n - - F (net) 11 - - - + cpu/stage1/regfile/g80989/Y - A->Y F AND2x4_ASAP7_75t_SL 5 14.500 21.800 444.500 + cpu/stage1/regfile/n_171 - - F (net) 5 - - - + cpu/stage1/regfile/FE_OFC1149_n_171/Y - A->Y R INVx3_ASAP7_75t_SL 2 20.300 15.600 460.100 + cpu/stage1/regfile/FE_OFN1075_n_171 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC1240_n_171/Y - A->Y F INVx3_ASAP7_75t_SL 9 25.600 13.900 474.000 + cpu/stage1/regfile/FE_OFN1073_n_171 - - F (net) 9 - - - + cpu/stage1/regfile/g78521/Y - A->Y F AND2x4_ASAP7_75t_SL 5 22.500 27.300 501.300 + cpu/stage1/regfile/n_637 - - F (net) 5 - - - + cpu/stage1/regfile/g77393/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 1 28.500 11.100 512.400 + cpu/stage1/regfile/n_1747 - - R (net) 1 - - - + cpu/stage1/regfile/g77240/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 18.700 10.000 522.400 + cpu/stage1/regfile/n_1884 - - F (net) 1 - - - + cpu/stage1/regfile/g77015/Y - B->Y R NOR2x1_ASAP7_75t_SL 1 32.500 9.100 531.500 + cpu/stage1/regfile/n_2094 - - R (net) 1 - - - + cpu/stage1/regfile/g76883__7098/Y - B->Y F NAND3xp33_ASAP7_75t_SL 1 17.400 13.500 545.000 + cpu/stage1/rs1_mux_data[0] - - F (net) 1 - - - + cpu/stage1/data1sel_s1/g557__3680/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 26.500 19.200 564.200 + cpu/stage1_rs1[0] - - F (net) 2 - - - + cpu/stage1/pcadder/g1277__2883/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 13.500 17.600 581.800 + cpu/stage1/pcadder/n_31 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1454__7482/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 3 21.800 13.200 595.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_7 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1356__4319/Y - A1->Y F OAI21x1_ASAP7_75t_SL 2 20.400 9.600 604.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_153 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1335__1881/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 1 18.200 11.100 615.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_169 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1332__8246/Y - B->Y F NAND2x2_ASAP7_75t_SL 3 16.000 7.100 622.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_172 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1324__5526/Y - B->Y F AND2x2_ASAP7_75t_SL 2 12.200 15.200 638.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_180 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - A1->Y R AOI21x1_ASAP7_75t_SL 3 9.900 13.300 651.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_192 - - R (net) 3 - - - + cpu/stage1/pcadder/FE_OCPC1369_add_18_35_Y_add_17_34_Y_add_16_33_n_192/Y - A->Y R HB1xp67_ASAP7_75t_SL 2 25.400 21.200 672.500 + cpu/stage1/pcadder/FE_OCPN1343_add_18_35_Y_add_17_34_Y_add_16_33_n_192 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1310/Y - A->Y F INVx1_ASAP7_75t_SL 1 24.400 6.100 678.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_193 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1299__5115/Y - A1->Y R AOI21xp5_ASAP7_75t_SL 2 11.200 14.600 693.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_202 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1290__5122/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 30.300 19.100 712.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_207 - - F (net) 2 - - - + cpu/stage1/pcadder/FE_OFC708_add_18_35_Y_add_17_34_Y_add_16_33_n_207/Y - A->Y R INVx1_ASAP7_75t_SL 1 28.600 7.900 720.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_208 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1278__6783/Y - B->Y F NAND2xp5_ASAP7_75t_L 1 12.600 10.600 730.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_214 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1267__7410/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 17.500 16.200 747.000 + cpu/stage1/stage1_pc4[13] - - F (net) 1 - - - + cpu/stage1/pcselmux/g937__1705/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 15.700 15.400 762.400 + cpu/stage1/stage1_pc_mux_to_pc[13] - - F (net) 2 - - - + cpu/stage1/pcreg/g354__2802/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.900 8.700 771.100 + cpu/stage1/pcreg/n_26 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[13]/D - D R DFFHQNx1_ASAP7_75t_SL 1 53.700 0.100 771.100 +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[13]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 20: MET (21.384 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[12]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[12]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.316 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.684 + Launch Clock:= 0.000 + Data Path:+ 770.300 + Slack:= 21.384 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.600 519.900 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y R AND2x2_ASAP7_75t_L 33 160.100 85.800 605.700 + cpu/stage1/regfile/n_266 - - R (net) 33 - - - + cpu/stage1/regfile/g78480/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 180.100 49.000 654.700 + cpu/stage1/regfile/n_692 - - F (net) 4 - - - + cpu/stage1/regfile/FE_OFC555_n_692/Y - A->Y R INVx1_ASAP7_75t_SL 1 99.800 14.500 669.200 + cpu/stage1/regfile/n_691 - - R (net) 1 - - - + cpu/stage1/regfile/g77829/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 29.200 8.400 677.600 + cpu/stage1/regfile/n_1310 - - F (net) 1 - - - + cpu/stage1/regfile/g77064/Y - B->Y R NAND4xp25_ASAP7_75t_SL 1 16.300 9.800 687.400 + cpu/stage1/regfile/n_2045 - - R (net) 1 - - - + cpu/stage1/regfile/g77002/Y - B->Y F AOI211xp5_ASAP7_75t_SL 1 35.800 17.200 704.600 + cpu/stage1/regfile/n_2107 - - F (net) 1 - - - + cpu/stage1/regfile/g76890__9315/Y - B->Y R OAI211xp5_ASAP7_75t_SL 1 45.100 30.400 735.000 + cpu/stage1/rs2_mux_data[12] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g566__1881/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 108.400 27.800 762.800 + cpu/stage1_rs2[12] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g433__3680/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 16.500 7.500 770.300 + cpu/s1_to_s2_rs2/n_18 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[12]/D - D F DFFHQNx1_ASAP7_75t_SL 1 58.900 0.100 770.300 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[12]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 21: MET (21.521 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[5]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[5]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.979 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.021 + Launch Clock:= 0.000 + Data Path:+ 770.500 + Slack:= 21.521 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 35.500 430.300 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/g80399/Y - A->Y F NOR2x1_ASAP7_75t_SL 9 57.900 48.500 478.800 + cpu/stage1/regfile/n_242 - - F (net) 9 - - - + cpu/stage1/regfile/g79861/Y - A->Y R NAND2xp5_ASAP7_75t_SL 2 79.800 22.500 501.300 + cpu/stage1/regfile/n_275 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC508_n_275/Y - A->Y F INVx1_ASAP7_75t_SL 3 36.200 14.100 515.400 + cpu/stage1/regfile/n_274 - - F (net) 3 - - - + cpu/stage1/regfile/FE_OFC511_n_275/Y - A->Y R INVx1_ASAP7_75t_SL 2 22.900 14.200 529.600 + cpu/stage1/regfile/FE_OFN748_n_275 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC515_n_275/Y - A->Y F INVx1_ASAP7_75t_SL 21 22.000 95.700 625.300 + cpu/stage1/regfile/FE_OFN752_n_275 - - F (net) 21 - - - + cpu/stage1/regfile/g78064/Y - B2->Y R AOI22xp5_ASAP7_75t_SL 1 194.800 33.100 658.400 + cpu/stage1/regfile/n_1075 - - R (net) 1 - - - + cpu/stage1/regfile/g77370/Y - B->Y R AND4x1_ASAP7_75t_SL 1 65.900 24.600 683.000 + cpu/stage1/regfile/n_1770 - - R (net) 1 - - - + cpu/stage1/regfile/g77052/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 12.800 11.900 694.900 + cpu/stage1/regfile/n_2057 - - F (net) 1 - - - + cpu/stage1/regfile/g76974__9315/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 35.200 15.800 710.700 + cpu/stage1/regfile/n_2135 - - R (net) 1 - - - + cpu/stage1/regfile/g76954__2398/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 55.900 27.800 738.500 + cpu/stage1/rs2_mux_data[5] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g549__6417/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 56.100 23.300 761.800 + cpu/stage1_rs2[5] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g424__6417/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.700 8.700 770.500 + cpu/s1_to_s2_rs2/n_27 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[5]/D - D R DFFHQNx1_ASAP7_75t_SL 1 56.100 0.100 770.500 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[5]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 22: MET (21.818 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[13]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[13]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.282 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.718 + Launch Clock:= 0.000 + Data Path:+ 768.900 + Slack:= 21.818 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.600 519.900 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y R AND2x2_ASAP7_75t_L 33 160.100 85.800 605.700 + cpu/stage1/regfile/n_266 - - R (net) 33 - - - + cpu/stage1/regfile/g78480/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 180.100 49.200 654.900 + cpu/stage1/regfile/n_692 - - F (net) 4 - - - + cpu/stage1/regfile/g77148/Y - A2->Y R OAI211xp5_ASAP7_75t_SL 1 99.900 27.800 682.700 + cpu/stage1/regfile/n_1961 - - R (net) 1 - - - + cpu/stage1/regfile/g77063/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 45.000 11.900 694.600 + cpu/stage1/regfile/n_2046 - - F (net) 1 - - - + cpu/stage1/regfile/g76940__6131/Y - B->Y R OAI211xp5_ASAP7_75t_SL 1 41.600 35.600 730.200 + cpu/stage1/rs2_mux_data[13] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g563__8246/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 125.400 29.000 759.200 + cpu/stage1_rs2[13] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g419__9945/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 17.100 9.700 768.900 + cpu/s1_to_s2_rs2/n_32 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[13]/D - D F DFFHQNx1_ASAP7_75t_SL 1 62.700 0.200 768.900 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[13]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 23: MET (21.996 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.504 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.496 + Launch Clock:= 0.000 + Data Path:+ 770.500 + Slack:= 21.996 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.400 394.400 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g390__4733/Y - B->Y R AND2x4_ASAP7_75t_SL 8 14.300 25.400 419.800 + cpu/stage1_inst[16] - - R (net) 8 - - - + cpu/stage1/regfile/FE_OFC1125_stage1_inst_16/Y - A->Y F INVx4_ASAP7_75t_SL 7 30.600 16.200 436.000 + cpu/stage1/regfile/FE_OFN903_stage1_inst_16 - - F (net) 7 - - - + cpu/stage1/regfile/g79850/Y - B->Y F OR2x6_ASAP7_75t_SL 14 32.900 35.300 471.300 + cpu/stage1/regfile/n_292 - - F (net) 14 - - - + cpu/stage1/regfile/g79343/Y - A->Y R INVx4_ASAP7_75t_SL 8 33.300 22.100 493.400 + cpu/stage1/regfile/n_291 - - R (net) 8 - - - + cpu/stage1/regfile/g78473/Y - B->Y R AND2x2_ASAP7_75t_SL 1 39.900 16.900 510.300 + cpu/stage1/regfile/n_701 - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC733_n_701/Y - A->Y F INVx2_ASAP7_75t_SL 2 10.100 11.500 521.800 + cpu/stage1/regfile/n_700 - - F (net) 2 - - - + cpu/stage1/regfile/g77206/Y - B2->Y R OAI22x1_ASAP7_75t_SL 1 16.500 12.200 534.000 + cpu/stage1/regfile/n_1918 - - R (net) 1 - - - + cpu/stage1/regfile/g77078/Y - B->Y F NOR2x1_ASAP7_75t_SL 1 26.100 11.600 545.600 + cpu/stage1/regfile/n_2031 - - F (net) 1 - - - + cpu/stage1/regfile/g76912__6131/Y - B->Y R NAND3x1_ASAP7_75t_SL 1 19.400 21.000 566.600 + cpu/stage1/rs1_mux_data[6] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g561__5122/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 35.500 20.500 587.100 + cpu/stage1_rs1[6] - - R (net) 2 - - - + cpu/stage1/pcadder/g1268__7098/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.000 17.500 604.600 + cpu/stage1/pcadder/n_37 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1448__5122/Y - B->Y F NOR2x1_ASAP7_75t_SL 2 26.300 9.900 614.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_79 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1361__6783/Y - A->Y F OR2x2_ASAP7_75t_SL 2 14.800 16.800 631.300 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_148 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - A2->Y R OAI21x1_ASAP7_75t_SL 1 10.200 9.700 641.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_176 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y F AOI21x1_ASAP7_75t_SL 3 16.600 10.900 651.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_192 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_OCPC1369_add_18_35_Y_add_17_34_Y_add_16_33_n_192/Y - A->Y F HB1xp67_ASAP7_75t_SL 2 18.400 20.300 672.200 + cpu/stage1/pcadder/FE_OCPN1343_add_18_35_Y_add_17_34_Y_add_16_33_n_192 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1310/Y - A->Y R INVx1_ASAP7_75t_SL 1 18.600 7.400 679.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_193 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1299__5115/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 10.800 11.500 691.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_202 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1290__5122/Y - B->Y R NOR2xp33_ASAP7_75t_SL 2 32.800 21.000 712.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_207 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1273__6260/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 37.600 17.300 729.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_217 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1259__6161/Y - B->Y F XOR2xp5_ASAP7_75t_SL 1 30.000 16.100 745.500 + cpu/stage1/stage1_pc4[14] - - F (net) 1 - - - + cpu/stage1/pcselmux/g935__1617/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 20.000 16.500 762.000 + cpu/stage1/stage1_pc_mux_to_pc[14] - - F (net) 2 - - - + cpu/stage1/pcreg/g357__8246/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 15.300 8.500 770.500 + cpu/stage1/pcreg/n_23 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[14]/D - D R DFFHQNx1_ASAP7_75t_SL 1 53.300 0.000 770.500 +#---------------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 24: MET (22.721 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[3]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[3]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.979 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.021 + Launch Clock:= 0.000 + Data Path:+ 769.300 + Slack:= 22.721 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 35.500 430.300 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/g80399/Y - A->Y F NOR2x1_ASAP7_75t_SL 9 57.900 48.500 478.800 + cpu/stage1/regfile/n_242 - - F (net) 9 - - - + cpu/stage1/regfile/g79861/Y - A->Y R NAND2xp5_ASAP7_75t_SL 2 79.800 22.500 501.300 + cpu/stage1/regfile/n_275 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC508_n_275/Y - A->Y F INVx1_ASAP7_75t_SL 3 36.200 14.100 515.400 + cpu/stage1/regfile/n_274 - - F (net) 3 - - - + cpu/stage1/regfile/FE_OFC511_n_275/Y - A->Y R INVx1_ASAP7_75t_SL 2 22.900 14.200 529.600 + cpu/stage1/regfile/FE_OFN748_n_275 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC515_n_275/Y - A->Y F INVx1_ASAP7_75t_SL 21 22.000 95.800 625.400 + cpu/stage1/regfile/FE_OFN752_n_275 - - F (net) 21 - - - + cpu/stage1/regfile/FE_OFC517_n_275/Y - A->Y F HB1xp67_ASAP7_75t_SL 2 194.800 38.900 664.300 + cpu/stage1/regfile/FE_OFN754_n_275 - - F (net) 2 - - - + cpu/stage1/regfile/g77468/Y - B1->Y R AOI221xp5_ASAP7_75t_SL 1 22.300 15.000 679.300 + cpu/stage1/regfile/n_1668 - - R (net) 1 - - - + cpu/stage1/regfile/g77176/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 45.500 18.800 698.100 + cpu/stage1/regfile/n_1939 - - F (net) 1 - - - + cpu/stage1/regfile/g76976__2883/Y - B->Y R A2O1A1Ixp33_ASAP7_75t_SL 1 38.800 20.900 719.000 + cpu/stage1/regfile/n_2133 - - R (net) 1 - - - + cpu/stage1/regfile/g76913__1881/Y - A->Y F NAND4xp25_ASAP7_75t_SL 1 58.500 20.000 739.000 + cpu/stage1/rs2_mux_data[3] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g551__2398/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 39.700 21.600 760.600 + cpu/stage1_rs2[3] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g423__7410/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.800 8.700 769.300 + cpu/s1_to_s2_rs2/n_28 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[3]/D - D R DFFHQNx1_ASAP7_75t_SL 1 56.100 0.100 769.300 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[3]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 25: MET (23.540 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[10]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[10]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.860 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.140 + Launch Clock:= 0.000 + Data Path:+ 768.600 + Slack:= 23.540 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 35.500 430.300 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/g80399/Y - A->Y F NOR2x1_ASAP7_75t_SL 9 57.900 48.500 478.800 + cpu/stage1/regfile/n_242 - - F (net) 9 - - - + cpu/stage1/regfile/g79861/Y - A->Y R NAND2xp5_ASAP7_75t_SL 2 79.800 22.500 501.300 + cpu/stage1/regfile/n_275 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC508_n_275/Y - A->Y F INVx1_ASAP7_75t_SL 3 36.200 14.100 515.400 + cpu/stage1/regfile/n_274 - - F (net) 3 - - - + cpu/stage1/regfile/FE_OFC511_n_275/Y - A->Y R INVx1_ASAP7_75t_SL 2 22.900 14.200 529.600 + cpu/stage1/regfile/FE_OFN748_n_275 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC515_n_275/Y - A->Y F INVx1_ASAP7_75t_SL 21 22.000 95.400 625.000 + cpu/stage1/regfile/FE_OFN752_n_275 - - F (net) 21 - - - + cpu/stage1/regfile/g78005/Y - A2->Y R AOI22xp5_ASAP7_75t_SL 1 194.800 25.300 650.300 + cpu/stage1/regfile/n_1134 - - R (net) 1 - - - + cpu/stage1/regfile/g77175/Y - B->Y R AND5x1_ASAP7_75t_SL 1 68.800 26.100 676.400 + cpu/stage1/regfile/n_1940 - - R (net) 1 - - - + cpu/stage1/regfile/g76989__3680/Y - A2->Y R OA211x2_ASAP7_75t_SL 1 14.200 17.700 694.100 + cpu/stage1/regfile/n_2120 - - R (net) 1 - - - + cpu/stage1/regfile/g76933__3680/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 15.000 38.700 732.800 + cpu/stage1/rs2_mux_data[10] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g570__6161/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 88.300 27.000 759.800 + cpu/stage1_rs2[10] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g431__5526/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.700 8.800 768.600 + cpu/s1_to_s2_rs2/n_20 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[10]/D - D R DFFHQNx1_ASAP7_75t_SL 1 55.400 0.100 768.600 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[10]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 26: MET (24.143 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[18]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[18]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.657 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.343 + Launch Clock:= 0.000 + Data Path:+ 768.200 + Slack:= 24.143 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1295/Y - A->Y F INVx1_ASAP7_75t_SL 2 47.100 11.000 689.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_203 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1288__1705/Y - B->Y R NOR2xp33_ASAP7_75t_SL 2 21.500 18.300 707.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_209 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1272__5107/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 35.900 15.900 723.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_218 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1258__4733/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 27.700 19.500 743.200 + cpu/stage1/stage1_pc4[18] - - F (net) 1 - - - + cpu/stage1/pcselmux/g950__2346/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 20.700 16.400 759.600 + cpu/stage1/stage1_pc_mux_to_pc[18] - - F (net) 2 - - - + cpu/stage1/pcreg/g359__6131/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 15.200 8.600 768.200 + cpu/stage1/pcreg/n_21 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[18]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.200 0.100 768.200 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[18]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 27: MET (24.886 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[24]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[24]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.714 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.286 + Launch Clock:= 0.000 + Data Path:+ 765.400 + Slack:= 24.886 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.600 519.900 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y R AND2x2_ASAP7_75t_L 33 160.100 85.800 605.700 + cpu/stage1/regfile/n_266 - - R (net) 33 - - - + cpu/stage1/regfile/g78480/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 180.100 47.300 653.000 + cpu/stage1/regfile/n_692 - - F (net) 4 - - - + cpu/stage1/regfile/g77156/Y - A2->Y R OAI211xp5_ASAP7_75t_SL 1 99.400 28.300 681.300 + cpu/stage1/regfile/n_1953 - - R (net) 1 - - - + cpu/stage1/regfile/g77066/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 45.800 14.500 695.800 + cpu/stage1/regfile/n_2043 - - F (net) 1 - - - + cpu/stage1/regfile/g76942__5115/Y - B->Y R OAI211xp5_ASAP7_75t_SL 1 45.600 32.800 728.600 + cpu/stage1/rs2_mux_data[24] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g552__5107/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 116.300 26.700 755.300 + cpu/stage1_rs2[24] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g445__6161/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 14.200 10.100 765.400 + cpu/s1_to_s2_rs2/n_6 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[24]/D - D F DFFHQNx1_ASAP7_75t_SL 1 64.400 0.400 765.400 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[24]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 28: MET (24.943 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[28]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.657 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.343 + Launch Clock:= 0.000 + Data Path:+ 767.400 + Slack:= 24.943 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 30.100 9.500 704.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_20 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1257__7482/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 16.700 16.700 721.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_231 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1256/Y - A->Y F INVx1_ASAP7_75t_SL 2 12.000 7.700 728.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_232 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1248__1705/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 11.600 14.400 743.200 + cpu/stage1/stage1_pc4[28] - - F (net) 1 - - - + cpu/stage1/pcselmux/g944__7482/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 17.900 15.700 758.900 + cpu/stage1/stage1_pc_mux_to_pc[28] - - F (net) 2 - - - + cpu/stage1/pcreg/g367__2883/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 15.100 8.500 767.400 + cpu/stage1/pcreg/n_13 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[28]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.200 0.000 767.400 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[28]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 29: MET (25.159 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.341 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.659 + Launch Clock:= 0.000 + Data Path:+ 766.500 + Slack:= 25.159 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.700 520.000 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 160.100 34.400 554.400 + cpu/stage1/regfile/n_345 - - F (net) 4 - - - + cpu/stage1/regfile/g78528/Y - B->Y R NOR2xp67_ASAP7_75t_SL 12 76.500 105.200 659.600 + cpu/stage1/regfile/n_625 - - R (net) 12 - - - + cpu/stage1/regfile/g77734/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 203.100 21.000 680.600 + cpu/stage1/regfile/n_1406 - - F (net) 1 - - - + cpu/stage1/regfile/g77155/Y - C->Y R NAND3xp33_ASAP7_75t_SL 1 72.700 19.200 699.800 + cpu/stage1/regfile/n_1954 - - R (net) 1 - - - + cpu/stage1/regfile/g77082/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 33.700 12.300 712.100 + cpu/stage1/regfile/n_2027 - - F (net) 1 - - - + cpu/stage1/regfile/g76997__1881/Y - A->Y R NAND5xp2_ASAP7_75t_SL 1 59.600 15.900 728.000 + cpu/stage1/regfile/n_2112 - - R (net) 1 - - - + cpu/stage1/regfile/g76939__7098/Y - B->Y R AO21x1_ASAP7_75t_SL 1 37.300 14.300 742.300 + cpu/stage1/rs2_mux_data[31] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g560__2802/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 19.000 17.200 759.500 + cpu/stage1_rs2[31] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g420__2883/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 14.700 7.000 766.500 + cpu/s1_to_s2_rs2/n_31 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[31]/D - D F DFFHQNx1_ASAP7_75t_SL 1 59.000 0.000 766.500 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[31]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 30: MET (26.496 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[21]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.604 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.396 + Launch Clock:= 0.000 + Data Path:+ 765.900 + Slack:= 26.496 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1280__3680/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_213 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1270__5477/Y - B->Y R NOR2xp33_ASAP7_75t_SL 2 30.200 19.500 714.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_220 - - R (net) 2 - - - + cpu/stage1/pcadder/FE_OFC530_add_18_35_Y_add_17_34_Y_add_16_33_n_220/Y - A->Y F INVx1_ASAP7_75t_SL 1 34.800 5.600 720.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_221 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1261__9945/Y - B->Y R NAND2xp5_ASAP7_75t_L 1 12.900 11.200 731.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_227 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1250__8246/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 1 20.200 13.100 744.300 + cpu/stage1/stage1_pc4[21] - - R (net) 1 - - - + cpu/stage1/pcselmux/g940__7098/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.000 14.400 758.700 + cpu/stage1/stage1_pc_mux_to_pc[21] - - R (net) 2 - - - + cpu/stage1/pcreg/g347__6260/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 17.200 7.200 765.900 + cpu/stage1/pcreg/n_33 - - F (net) 1 - - - + cpu/stage1/pcreg/register_reg[21]/D - D F DFFHQNx1_ASAP7_75t_SL 1 56.100 0.000 765.900 +#-------------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[21]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 31: MET (27.021 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[9]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.079 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.921 + Launch Clock:= 0.000 + Data Path:+ 763.900 + Slack:= 27.021 + Timing Path: + +#--------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80394/Y - B->Y F NAND2xp5_ASAP7_75t_SL 3 27.300 13.400 456.800 + cpu/stage1/regfile/n_250 - - F (net) 3 - - - + cpu/stage1/regfile/g79869/Y - A->Y R INVx1_ASAP7_75t_SL 4 24.700 14.600 471.400 + cpu/stage1/regfile/n_249 - - R (net) 4 - - - + cpu/stage1/regfile/g79860/Y - A->Y R AND2x2_ASAP7_75t_SL 27 23.200 91.300 562.700 + cpu/stage1/regfile/n_277 - - R (net) 27 - - - + cpu/stage1/regfile/g79348/Y - A->Y F INVx1_ASAP7_75t_SL 2 189.500 17.400 580.100 + cpu/stage1/regfile/n_276 - - F (net) 2 - - - + cpu/stage1/regfile/g78488/Y - B->Y R NOR2xp33_ASAP7_75t_SL 5 59.600 89.400 669.500 + cpu/stage1/regfile/n_681 - - R (net) 5 - - - + cpu/stage1/regfile/g77264/Y - A1->Y F AOI221xp5_ASAP7_75t_SL 1 182.800 33.200 702.700 + cpu/stage1/regfile/n_1865 - - F (net) 1 - - - + cpu/stage1/regfile/g76891__9945/Y - C->Y R NAND5xp2_ASAP7_75t_SL 1 78.400 30.500 733.200 + cpu/stage1/rs2_mux_data[9] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g572__9945/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 50.700 21.900 755.100 + cpu/stage1_rs2[9] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g429__4319/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 13.800 8.800 763.900 + cpu/s1_to_s2_rs2/n_22 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[9]/D - D F DFFHQNx1_ASAP7_75t_SL 1 61.900 0.200 763.900 +#--------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[9]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 32: MET (27.672 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[4]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[4]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.828 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.172 + Launch Clock:= 0.000 + Data Path:+ 762.500 + Slack:= 27.672 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.400 394.400 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g397__7410/Y - B->Y R AND2x4_ASAP7_75t_SL 44 14.300 75.100 469.500 + cpu/stage1_inst[22] - - R (net) 44 - - - + cpu/stage1/regfile/g80400/Y - B->Y F NOR2xp33_ASAP7_75t_L 10 215.500 131.800 601.300 + cpu/stage1/regfile/n_241 - - F (net) 10 - - - + cpu/stage1/regfile/g78429/Y - A->Y F AND2x2_ASAP7_75t_SL 10 182.900 62.300 663.600 + cpu/stage1/regfile/n_781 - - F (net) 10 - - - + cpu/stage1/regfile/g77671/Y - A2->Y R AOI22xp5_ASAP7_75t_SL 1 48.500 13.400 677.000 + cpu/stage1/regfile/n_1469 - - R (net) 1 - - - + cpu/stage1/regfile/g77107/Y - B->Y R OA211x2_ASAP7_75t_SL 1 24.400 19.100 696.100 + cpu/stage1/regfile/n_2002 - - R (net) 1 - - - + cpu/stage1/regfile/g76955__5107/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 13.400 28.400 724.500 + cpu/stage1/rs2_mux_data[4] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g550__5477/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 70.500 23.300 747.800 + cpu/stage1_rs2[4] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g435__2802/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 11.200 14.700 762.500 + cpu/s1_to_s2_rs2/n_16 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[4]/D - D R DFFHQNx1_ASAP7_75t_SL 1 67.000 0.200 762.500 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[4]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 33: MET (27.913 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[26]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.487 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.513 + Launch Clock:= 0.000 + Data Path:+ 764.600 + Slack:= 27.913 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 30.100 9.500 704.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_20 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1263__2883/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 16.700 19.200 723.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_226 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g2__9945/Y - B->Y F XOR2xp5_ASAP7_75t_SL 1 32.700 16.500 740.100 + cpu/stage1/stage1_pc4[26] - - F (net) 1 - - - + cpu/stage1/pcselmux/g939__8246/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 22.800 16.500 756.600 + cpu/stage1/stage1_pc_mux_to_pc[26] - - F (net) 2 - - - + cpu/stage1/pcreg/g366__9945/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.900 8.000 764.600 + cpu/stage1/pcreg/n_14 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[26]/D - D R DFFHQNx1_ASAP7_75t_SL 1 53.200 0.000 764.600 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[26]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 34: MET (28.026 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.674 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.326 + Launch Clock:= 0.000 + Data Path:+ 764.300 + Slack:= 28.026 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 -0.000 + cpu/s1_to_s2_inst/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_inst/register_reg[2]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_SL 1 0.100 30.000 30.000 + cpu/stage2_inst[2] - - R (net) 1 - - - + cpu/FE_OFC948_stage2_inst_2/Y - A->Y F INVx1_ASAP7_75t_SL 2 13.500 6.400 36.400 + cpu/FE_OFN851_stage2_inst_2 - - F (net) 2 - - - + cpu/FE_OFC952_stage2_inst_2/Y - A->Y R INVx1_ASAP7_75t_SL 13 9.500 29.600 66.000 + cpu/FE_OFN850_stage2_inst_2 - - R (net) 13 - - - + cpu/FE_OFC670_stage2_inst_2/Y - A->Y R BUFx2_ASAP7_75t_SL 9 59.500 25.900 91.900 + cpu/FE_OFN854_stage2_inst_2 - - R (net) 9 - - - + cpu/stage2/alusel/g764/Y - B->Y R OR2x2_ASAP7_75t_SL 3 25.000 15.600 107.500 + cpu/stage2/alusel/n_5 - - R (net) 3 - - - + cpu/stage2/alusel/g759/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 10.800 13.500 121.000 + cpu/stage2/alusel/n_9 - - F (net) 2 - - - + cpu/stage2/alusel/g755/Y - B->Y R NAND2xp5_ASAP7_75t_SL 3 26.600 18.400 139.400 + cpu/stage2/alusel/n_14 - - R (net) 3 - - - + cpu/stage2/alusel/FE_OFC746_n_14/Y - A->Y F INVx1_ASAP7_75t_SL 2 29.400 7.300 146.700 + cpu/stage2/alusel/n_13 - - F (net) 2 - - - + cpu/stage2/alusel/g751/Y - B->Y F AND2x2_ASAP7_75t_SL 3 13.600 15.200 161.900 + cpu/stage2/alusel/n_17 - - F (net) 3 - - - + cpu/stage2/alusel/g746/Y - B1->Y F AO221x1_ASAP7_75t_SL 1 12.100 18.700 180.600 + cpu/stage2/ALUop[1] - - F (net) 1 - - - + cpu/stage2/alu/FE_OFC626_ALUop_1/Y - A->Y R INVx1_ASAP7_75t_SL 5 13.400 21.500 202.100 + cpu/stage2/alu/n_0 - - R (net) 5 - - - + cpu/stage2/alu/FE_OFC627_ALUop_1/Y - A->Y F INVx1_ASAP7_75t_SL 4 37.200 15.600 217.700 + cpu/stage2/alu/FE_OFN823_ALUop_1 - - F (net) 4 - - - + cpu/stage2/alu/g3304/Y - B->Y R NOR2x1_ASAP7_75t_SL 3 25.000 13.200 230.900 + cpu/stage2/alu/n_194 - - R (net) 3 - - - + cpu/stage2/alu/g3302/Y - A->Y R AND3x4_ASAP7_75t_SL 9 23.600 26.700 257.600 + cpu/stage2/alu/n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC775_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 3 29.000 15.400 273.000 + cpu/stage2/alu/FE_OFN922_n_325 - - F (net) 3 - - - + cpu/stage2/alu/FE_OFC778_n_325/Y - A->Y R INVx3_ASAP7_75t_SL 9 24.200 24.000 297.000 + cpu/stage2/alu/FE_OFN925_n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC782_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 7 44.400 41.300 338.300 + cpu/stage2/alu/FE_OFN929_n_325 - - F (net) 7 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1722/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 2 72.200 24.100 362.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_36 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1655/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 45.200 24.300 386.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_116 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A1->Y F OA21x2_ASAP7_75t_SL 3 43.900 22.200 408.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y R OAI321xp33_ASAP7_75t_SL 1 13.300 17.300 426.200 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y F INVx1_ASAP7_75t_SL 2 42.800 11.500 437.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 21.200 19.000 456.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 10.600 16.200 472.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 10.800 9.200 482.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y R OR2x2_ASAP7_75t_SL 3 18.000 17.600 499.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y F AOI31xp67_ASAP7_75t_SL 3 15.800 16.400 516.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 34.100 15.700 531.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y R OR2x2_ASAP7_75t_SL 3 32.100 25.500 557.300 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 27.300 15.500 572.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y F NAND2xp5_ASAP7_75t_L 2 12.900 11.700 584.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 18.800 14.600 599.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 37.100 10.300 609.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y R INVx1_ASAP7_75t_SL 3 20.500 13.500 622.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.500 16.600 639.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 16.200 12.900 652.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 22.100 19.100 671.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 11.700 17.200 688.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 12.100 17.200 705.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1505/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 11.900 14.000 719.900 + cpu/stage2/alu/n_321 - - F (net) 1 - - - + cpu/stage2/alu/g5504/Y - A2->Y F AO21x1_ASAP7_75t_SL 4 18.300 27.900 747.800 + dcache_addr[30] - - F (net) 4 - - - + cpu/stage3/csr/g191/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 32.900 16.500 764.300 + cpu/stage3/csr/n_4 - - R (net) 1 - - - + cpu/stage3/csr/csr_reg[30]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.300 0.500 764.300 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage3/csr/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage3/csr/csr_reg[30]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------------- +Path 35: MET (28.867 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[6]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[6]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 9.333 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 790.667 + Launch Clock:= 0.000 + Data Path:+ 761.800 + Slack:= 28.867 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.600 519.900 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y R AND2x2_ASAP7_75t_L 33 160.100 85.800 605.700 + cpu/stage1/regfile/n_266 - - R (net) 33 - - - + cpu/stage1/regfile/g78480/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 180.100 49.100 654.800 + cpu/stage1/regfile/n_692 - - F (net) 4 - - - + cpu/stage1/regfile/g77153/Y - A2->Y R OAI211xp5_ASAP7_75t_SL 1 99.800 28.600 683.400 + cpu/stage1/regfile/n_1956 - - R (net) 1 - - - + cpu/stage1/regfile/g77065/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 46.200 12.600 696.000 + cpu/stage1/regfile/n_2044 - - F (net) 1 - - - + cpu/stage1/regfile/g76941__1881/Y - B->Y R OAI211xp5_ASAP7_75t_SL 1 42.600 29.200 725.200 + cpu/stage1/rs2_mux_data[6] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g561__1705/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 100.400 26.900 752.100 + cpu/stage1_rs2[6] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g426__2398/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 15.700 9.700 761.800 + cpu/s1_to_s2_rs2/n_25 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[6]/D - D F DFFHQNx1_ASAP7_75t_SL 1 62.900 0.300 761.800 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[6]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 36: MET (28.909 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[17]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[17]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.691 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.309 + Launch Clock:= 0.000 + Data Path:+ 763.400 + Slack:= 28.909 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/g392__9315/Y - B->Y F NOR2x2_ASAP7_75t_SL 4 13.500 16.500 401.000 + cpu/stage1/FE_OFN1064_stage1_inst_15 - - F (net) 4 - - - + cpu/stage1/regfile/FE_OFC1208_stage1_inst_15/Y - A->Y R INVx3_ASAP7_75t_SL 1 31.600 10.900 411.900 + cpu/stage1/regfile/FE_OFN1120_n - - R (net) 1 - - - + cpu/stage1/regfile/FE_OFC1212_stage1_inst_15/Y - A->Y F INVx6_ASAP7_75t_SL 11 17.000 10.800 422.700 + cpu/stage1/regfile/FE_OFN1214_n - - F (net) 11 - - - + cpu/stage1/regfile/g80989/Y - A->Y F AND2x4_ASAP7_75t_SL 5 14.500 21.800 444.500 + cpu/stage1/regfile/n_171 - - F (net) 5 - - - + cpu/stage1/regfile/FE_OFC1149_n_171/Y - A->Y R INVx3_ASAP7_75t_SL 2 20.300 15.300 459.800 + cpu/stage1/regfile/FE_OFN1075_n_171 - - R (net) 2 - - - + cpu/stage1/regfile/FE_OFC1150_n_171/Y - A->Y F INVx6_ASAP7_75t_SL 13 25.600 12.700 472.500 + cpu/stage1/regfile/FE_OFN1077_n_171 - - F (net) 13 - - - + cpu/stage1/regfile/FE_OFC1152_n_171/Y - A->Y F BUFx6f_ASAP7_75t_SL 10 21.500 18.900 491.400 + cpu/stage1/regfile/FE_OFN1079_n_171 - - F (net) 10 - - - + cpu/stage1/regfile/g78044/Y - B2->Y F AO22x2_ASAP7_75t_SL 1 12.300 16.600 508.000 + cpu/stage1/regfile/n_1095 - - F (net) 1 - - - + cpu/stage1/regfile/g77303/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 9.800 8.400 516.400 + cpu/stage1/regfile/n_1826 - - R (net) 1 - - - + cpu/stage1/regfile/g77043/Y - C->Y F NAND3xp33_ASAP7_75t_SL 1 15.900 13.700 530.100 + cpu/stage1/regfile/n_2066 - - F (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - B->Y R NOR2x1_ASAP7_75t_SL 1 27.400 9.900 540.000 + cpu/stage1/regfile/n_2178 - - R (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y F NAND3x1_ASAP7_75t_SL 1 17.900 13.500 553.500 + cpu/stage1/rs1_mux_data[8] - - F (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 31.400 24.500 578.000 + cpu/stage1_rs1[8] - - F (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 16.400 19.200 597.200 + cpu/stage1/pcadder/n_39 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 3 20.500 11.500 608.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - R (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y F OAI21x1_ASAP7_75t_SL 2 18.100 8.500 617.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 18.300 8.200 625.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 12.800 14.500 639.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y R OA21x2_ASAP7_75t_SL 1 9.700 14.100 654.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y F OAI21x1_ASAP7_75t_SL 3 10.500 19.100 673.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1295/Y - A->Y R INVx1_ASAP7_75t_SL 2 32.600 13.000 686.100 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_203 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1288__1705/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 20.100 16.500 702.600 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_209 - - F (net) 2 - - - + cpu/stage1/pcadder/FE_OFC657_add_18_35_Y_add_17_34_Y_add_16_33_n_209/Y - A->Y R INVx1_ASAP7_75t_SL 1 33.300 8.300 710.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_210 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1277__5526/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 13.700 9.000 719.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_215 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1266__1666/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 17.700 16.500 736.400 + cpu/stage1/stage1_pc4[17] - - F (net) 1 - - - + cpu/stage1/pcselmux/g954__5477/Y - A2->Y F AO21x1_ASAP7_75t_L 2 16.700 18.500 754.900 + cpu/stage1/stage1_pc_mux_to_pc[17] - - F (net) 2 - - - + cpu/stage1/pcreg/g358__7098/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.200 8.500 763.400 + cpu/stage1/pcreg/n_22 - - R (net) 1 - - - + cpu/stage1/pcreg/register_reg[17]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.400 0.100 763.400 +#------------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[17]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 37: MET (29.486 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[0]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[0]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 11.214 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 788.786 + Launch Clock:= 0.000 + Data Path:+ 759.300 + Slack:= 29.486 + Timing Path: + +#--------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80394/Y - B->Y F NAND2xp5_ASAP7_75t_SL 3 27.300 13.400 456.800 + cpu/stage1/regfile/n_250 - - F (net) 3 - - - + cpu/stage1/regfile/g79869/Y - A->Y R INVx1_ASAP7_75t_SL 4 24.700 14.600 471.400 + cpu/stage1/regfile/n_249 - - R (net) 4 - - - + cpu/stage1/regfile/g79860/Y - A->Y R AND2x2_ASAP7_75t_SL 27 23.200 91.300 562.700 + cpu/stage1/regfile/n_277 - - R (net) 27 - - - + cpu/stage1/regfile/g79348/Y - A->Y F INVx1_ASAP7_75t_SL 2 189.500 17.400 580.100 + cpu/stage1/regfile/n_276 - - F (net) 2 - - - + cpu/stage1/regfile/g78488/Y - B->Y R NOR2xp33_ASAP7_75t_SL 5 59.600 89.000 669.100 + cpu/stage1/regfile/n_681 - - R (net) 5 - - - + cpu/stage1/regfile/g77269/Y - A1->Y F AOI221xp5_ASAP7_75t_SL 1 182.800 33.000 702.100 + cpu/stage1/regfile/n_1860 - - F (net) 1 - - - + cpu/stage1/regfile/g76887__7482/Y - C->Y R NAND5xp2_ASAP7_75t_SL 1 78.100 24.100 726.200 + cpu/stage1/rs2_mux_data[0] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g557__6783/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 43.500 22.100 748.300 + cpu/stage1_rs2[0] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g449__2346/Y - B->Y F NOR2xp33_ASAP7_75t_SL 1 15.300 11.000 759.300 + cpu/s1_to_s2_rs2/n_2 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[0]/D - D F DFFHQNx1_ASAP7_75t_SL 1 70.300 0.100 759.300 +#--------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[0]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 38: MET (30.002 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[11]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[11]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.098 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.902 + Launch Clock:= 0.000 + Data Path:+ 761.900 + Slack:= 30.002 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y F NOR2xp33_ASAP7_75t_SL 8 27.300 63.600 507.000 + cpu/stage1/regfile/n_243 - - F (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y F AND2x2_ASAP7_75t_L 33 123.700 108.000 615.000 + cpu/stage1/regfile/n_266 - - F (net) 33 - - - + cpu/stage1/regfile/g77998/Y - B2->Y R AOI22xp5_ASAP7_75t_SL 1 144.100 27.600 642.600 + cpu/stage1/regfile/n_1141 - - R (net) 1 - - - + cpu/stage1/regfile/g77050/Y - C->Y F NAND5xp2_ASAP7_75t_SL 1 64.600 19.200 661.800 + cpu/stage1/regfile/n_2059 - - F (net) 1 - - - + cpu/stage1/regfile/g76972__4733/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 42.900 16.200 678.000 + cpu/stage1/regfile/n_2137 - - R (net) 1 - - - + cpu/stage1/regfile/g76948__2883/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 71.600 47.400 725.400 + cpu/stage1/rs2_mux_data[11] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g567__5115/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 94.700 27.300 752.700 + cpu/stage1_rs2[11] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g432__6783/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 14.800 9.200 761.900 + cpu/s1_to_s2_rs2/n_19 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[11]/D - D R DFFHQNx1_ASAP7_75t_SL 1 56.800 0.100 761.900 +#---------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[11]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 39: MET (30.675 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.725 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.275 + Launch Clock:= 0.000 + Data Path:+ 761.600 + Slack:= 30.675 + Timing Path: + +#--------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#--------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y F NOR2xp33_ASAP7_75t_SL 8 27.300 63.700 507.100 + cpu/stage1/regfile/n_243 - - F (net) 8 - - - + cpu/stage1/regfile/g79809/Y - B->Y R NAND2xp5_ASAP7_75t_SL 4 123.700 44.300 551.400 + cpu/stage1/regfile/n_345 - - R (net) 4 - - - + cpu/stage1/regfile/g78528/Y - B->Y F NOR2xp67_ASAP7_75t_SL 12 70.400 91.300 642.700 + cpu/stage1/regfile/n_625 - - F (net) 12 - - - + cpu/stage1/regfile/g77768/Y - B2->Y R AOI22xp5_ASAP7_75t_SL 1 159.000 29.400 672.100 + cpu/stage1/regfile/n_1372 - - R (net) 1 - - - + cpu/stage1/regfile/g77280/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 56.600 10.100 682.200 + cpu/stage1/regfile/n_1849 - - F (net) 1 - - - + cpu/stage1/regfile/g77105/Y - C->Y R AOI221xp5_ASAP7_75t_SL 1 24.300 15.500 697.700 + cpu/stage1/regfile/n_2004 - - R (net) 1 - - - + cpu/stage1/regfile/g76931__5526/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 47.400 32.700 730.400 + cpu/stage1/rs2_mux_data[27] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g558__3680/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 66.500 23.400 753.800 + cpu/stage1_rs2[27] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g425__5477/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.800 7.800 761.600 + cpu/s1_to_s2_rs2/n_26 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[27]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.600 0.000 761.600 +#--------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[27]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 40: MET (31.090 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[25]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[25]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.810 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.190 + Launch Clock:= 0.000 + Data Path:+ 760.100 + Slack:= 31.090 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.400 394.400 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g397__7410/Y - B->Y R AND2x4_ASAP7_75t_SL 44 14.300 75.100 469.500 + cpu/stage1_inst[22] - - R (net) 44 - - - + cpu/stage1/regfile/g80400/Y - B->Y F NOR2xp33_ASAP7_75t_L 10 215.500 131.700 601.200 + cpu/stage1/regfile/n_241 - - F (net) 10 - - - + cpu/stage1/regfile/g78516/Y - A->Y F AND2x2_ASAP7_75t_SL 9 182.800 58.600 659.800 + cpu/stage1/regfile/n_645 - - F (net) 9 - - - + cpu/stage1/regfile/g77788/Y - B2->Y R AOI22xp5_ASAP7_75t_SL 1 42.600 15.400 675.200 + cpu/stage1/regfile/n_1352 - - R (net) 1 - - - + cpu/stage1/regfile/g77061/Y - C->Y R OA211x2_ASAP7_75t_SL 1 25.200 17.100 692.300 + cpu/stage1/regfile/n_2048 - - R (net) 1 - - - + cpu/stage1/regfile/g76935__2802/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 11.700 33.600 725.900 + cpu/stage1/rs2_mux_data[25] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g547__1666/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 75.200 23.700 749.600 + cpu/stage1_rs2[25] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g430__8428/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.200 10.500 760.100 + cpu/s1_to_s2_rs2/n_21 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[25]/D - D R DFFHQNx1_ASAP7_75t_SL 1 61.000 0.300 760.100 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[25]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 41: MET (31.702 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[17]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[17]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.098 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.902 + Launch Clock:= 0.000 + Data Path:+ 760.200 + Slack:= 31.702 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y F NOR2xp33_ASAP7_75t_SL 8 27.300 63.600 507.000 + cpu/stage1/regfile/n_243 - - F (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y F AND2x2_ASAP7_75t_L 33 123.700 109.900 616.900 + cpu/stage1/regfile/n_266 - - F (net) 33 - - - + cpu/stage1/regfile/g77932/Y - B2->Y R AOI22xp5_ASAP7_75t_SL 1 144.200 27.900 644.800 + cpu/stage1/regfile/n_1207 - - R (net) 1 - - - + cpu/stage1/regfile/g77048/Y - C->Y F NAND5xp2_ASAP7_75t_SL 1 64.900 18.500 663.300 + cpu/stage1/regfile/n_2061 - - F (net) 1 - - - + cpu/stage1/regfile/g76970__5115/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 41.700 16.300 679.600 + cpu/stage1/regfile/n_2139 - - R (net) 1 - - - + cpu/stage1/regfile/g76946__9315/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 72.200 46.100 725.700 + cpu/stage1/rs2_mux_data[17] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g553__6260/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 90.100 25.700 751.400 + cpu/stage1_rs2[17] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g438__8246/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 13.100 8.800 760.200 + cpu/s1_to_s2_rs2/n_13 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[17]/D - D R DFFHQNx1_ASAP7_75t_SL 1 56.800 0.100 760.200 +#---------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[17]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 42: MET (32.115 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[21]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.284 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.716 + Launch Clock:= 0.000 + Data Path:+ 759.600 + Slack:= 32.115 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y F NOR2xp33_ASAP7_75t_SL 8 27.300 63.600 507.000 + cpu/stage1/regfile/n_243 - - F (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y F AND2x2_ASAP7_75t_L 33 123.700 102.700 609.700 + cpu/stage1/regfile/n_266 - - F (net) 33 - - - + cpu/stage1/regfile/g77541/Y - A1->Y R AOI222xp33_ASAP7_75t_SL 1 143.100 34.900 644.600 + cpu/stage1/regfile/n_1595 - - R (net) 1 - - - + cpu/stage1/regfile/g77224/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 67.700 18.900 663.500 + cpu/stage1/regfile/n_1900 - - F (net) 1 - - - + cpu/stage1/regfile/g77018/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 40.900 14.400 677.900 + cpu/stage1/regfile/n_2091 - - R (net) 1 - - - + cpu/stage1/regfile/g76916__4733/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 64.900 46.900 724.800 + cpu/stage1/rs2_mux_data[21] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g569__4733/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 94.500 25.600 750.400 + cpu/stage1_rs2[21] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g442__5115/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.800 9.200 759.600 + cpu/s1_to_s2_rs2/n_9 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[21]/D - D R DFFHQNx1_ASAP7_75t_SL 1 57.900 0.100 759.600 +#---------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[21]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 43: MET (32.589 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[18]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[0]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[18]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.911 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.089 + Launch Clock:= 0.000 + Data Path:+ 759.500 + Slack:= 32.589 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[0]/Q - CLK->Q R DFFHQx4_ASAP7_75t_SL 3 0.100 42.500 42.500 + cpu/stage3_inst[0] - - R (net) 3 - - - + cpu/FE_OFC655_stage3_inst_0/Y - A->Y R HB1xp67_ASAP7_75t_SL 6 9.100 25.600 68.100 + cpu/FE_OFN844_stage3_inst_0 - - R (net) 6 - - - + cpu/stage2/data1sel/g747/Y - A->Y R OR4x1_ASAP7_75t_SL 1 39.200 10.500 78.600 + cpu/stage2/data1sel/n_17 - - R (net) 1 - - - + cpu/stage2/data1sel/g739/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 8.400 8.200 86.800 + cpu/stage2/data1sel/n_25 - - F (net) 1 - - - + cpu/stage2/data1sel/g736/Y - C->Y R NOR3xp33_ASAP7_75t_SL 1 15.000 13.100 99.900 + cpu/stage2/data1sel/n_28 - - R (net) 1 - - - + cpu/stage2/data1sel/g735/Y - B->Y R AND4x1_ASAP7_75t_SL 1 24.800 18.700 118.600 + cpu/stage2/data1sel/n_29 - - R (net) 1 - - - + cpu/stage2/data1sel/g734/Y - B->Y R AND2x2_ASAP7_75t_SL 14 10.700 38.100 156.700 + cpu/stage2/Data1SelSignal - - R (net) 14 - - - + cpu/stage2/rs1DataSel/FE_OFC591_Data1SelSignal/Y - A->Y F INVx2_ASAP7_75t_SL 10 62.000 19.300 176.000 + cpu/stage2/rs1DataSel/FE_OFN801_Data1SelSignal - - F (net) 10 - - - + cpu/stage2/rs1DataSel/g592/Y - B->Y F AND2x2_ASAP7_75t_SL 1 33.700 18.100 194.100 + cpu/stage2/rs1DataSel/n_21 - - F (net) 1 - - - + cpu/stage2/rs1DataSel/g546/Y - B->Y F AO21x2_ASAP7_75t_SL 5 8.200 25.400 219.500 + cpu/stage2/stage2_rs1_data[15] - - F (net) 5 - - - + cpu/stage2/branchcomp/lt_12_69_g831/Y - A->Y R NOR2x1_ASAP7_75t_SL 4 20.800 16.200 235.700 + cpu/stage2/branchcomp/lt_12_69_n_62 - - R (net) 4 - - - + cpu/stage2/branchcomp/lt_12_69_g807/Y - A->Y F INVx1_ASAP7_75t_SL 1 30.000 5.900 241.600 + cpu/stage2/branchcomp/lt_12_69_n_63 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g760/Y - A3->Y R AOI31xp33_ASAP7_75t_SL 1 12.000 16.700 258.300 + cpu/stage2/branchcomp/lt_12_69_n_117 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g737/Y - B->Y F OAI21xp5_ASAP7_75t_SL 1 29.500 10.500 268.800 + cpu/stage2/branchcomp/lt_12_69_n_140 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g728/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 18.400 10.800 279.600 + cpu/stage2/branchcomp/lt_12_69_n_149 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g725/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 17.500 19.200 298.800 + cpu/stage2/branchcomp/lt_12_69_n_152 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_69_g723/Y - A1->Y R AOI21x1_ASAP7_75t_SL 1 36.000 15.200 314.000 + cpu/stage2/branchcomp/n_145 - - R (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - B2->Y R AO22x2_ASAP7_75t_SL 2 25.000 19.500 333.500 + cpu/BrLT - - R (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y R AND2x4_ASAP7_75t_SL 2 15.600 14.000 347.500 + cpu/stage1/pcsel/n_9 - - R (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y F NOR2x2_ASAP7_75t_SL 2 11.800 7.200 354.700 + cpu/stage1/pcsel/n_25 - - F (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 13.700 10.700 365.400 + cpu/stage1/PCSelect[0] - - R (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 3 18.000 19.100 384.500 + cpu/stage1/NOPSignal - - R (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y F INVx5_ASAP7_75t_SL 10 13.500 8.200 392.700 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - F (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y F AND2x2_ASAP7_75t_SL 11 11.600 33.200 425.900 + cpu/stage1_inst[21] - - F (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y R INVx1_ASAP7_75t_SL 3 46.700 17.500 443.400 + cpu/stage1/regfile/n_194 - - R (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y F NOR2xp33_ASAP7_75t_SL 8 27.300 63.600 507.000 + cpu/stage1/regfile/n_243 - - F (net) 8 - - - + cpu/stage1/regfile/g79867/Y - A->Y F AND2x2_ASAP7_75t_L 33 123.700 107.200 614.200 + cpu/stage1/regfile/n_266 - - F (net) 33 - - - + cpu/stage1/regfile/g77510/Y - A1->Y R AOI222xp33_ASAP7_75t_SL 1 143.600 35.100 649.300 + cpu/stage1/regfile/n_1626 - - R (net) 1 - - - + cpu/stage1/regfile/g77221/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 68.100 20.700 670.000 + cpu/stage1/regfile/n_1903 - - F (net) 1 - - - + cpu/stage1/regfile/g77017/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 43.800 15.600 685.600 + cpu/stage1/regfile/n_2092 - - R (net) 1 - - - + cpu/stage1/regfile/g76915__7482/Y - B->Y F NAND5xp2_ASAP7_75t_SL 1 70.000 41.400 727.000 + cpu/stage1/rs2_mux_data[18] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g548__7410/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 81.400 24.300 751.300 + cpu/stage1_rs2[18] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g439__7098/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.300 8.200 759.500 + cpu/s1_to_s2_rs2/n_12 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[18]/D - D R DFFHQNx1_ASAP7_75t_SL 1 55.700 0.100 759.500 +#---------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[18]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 44: MET (33.726 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[23]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.674 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.326 + Launch Clock:= 0.000 + Data Path:+ 758.600 + Slack:= 33.726 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.400 394.400 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g397__7410/Y - B->Y R AND2x4_ASAP7_75t_SL 44 14.300 75.100 469.500 + cpu/stage1_inst[22] - - R (net) 44 - - - + cpu/stage1/regfile/g80400/Y - B->Y F NOR2xp33_ASAP7_75t_L 10 215.500 131.300 600.800 + cpu/stage1/regfile/n_241 - - F (net) 10 - - - + cpu/stage1/regfile/g78430/Y - A->Y F AND2x2_ASAP7_75t_SL 10 182.800 61.200 662.000 + cpu/stage1/regfile/n_780 - - F (net) 10 - - - + cpu/stage1/regfile/g77803/Y - B2->Y R AOI22xp5_ASAP7_75t_SL 1 45.700 16.000 678.000 + cpu/stage1/regfile/n_1337 - - R (net) 1 - - - + cpu/stage1/regfile/g76998__5115/Y - B->Y R AND5x1_ASAP7_75t_SL 1 26.400 22.300 700.300 + cpu/stage1/regfile/n_2111 - - R (net) 1 - - - + cpu/stage1/regfile/g76936__1705/Y - C->Y F A2O1A1Ixp33_ASAP7_75t_SL 1 15.700 28.200 728.500 + cpu/stage1/rs2_mux_data[23] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g559__1617/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 61.500 22.500 751.000 + cpu/stage1_rs2[23] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g444__4733/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 12.300 7.600 758.600 + cpu/s1_to_s2_rs2/n_7 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[23]/D - D R DFFHQNx1_ASAP7_75t_SL 1 54.300 0.000 758.600 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[23]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 45: MET (34.408 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/register_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 6.792 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 793.208 + Launch Clock:= 0.000 + Data Path:+ 758.800 + Slack:= 34.408 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 0.000 + cpu/s1_to_s2_inst/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_inst/register_reg[2]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_SL 1 0.100 30.000 30.000 + cpu/stage2_inst[2] - - R (net) 1 - - - + cpu/FE_OFC948_stage2_inst_2/Y - A->Y F INVx1_ASAP7_75t_SL 2 13.500 6.400 36.400 + cpu/FE_OFN851_stage2_inst_2 - - F (net) 2 - - - + cpu/FE_OFC952_stage2_inst_2/Y - A->Y R INVx1_ASAP7_75t_SL 13 9.500 29.600 66.000 + cpu/FE_OFN850_stage2_inst_2 - - R (net) 13 - - - + cpu/FE_OFC670_stage2_inst_2/Y - A->Y R BUFx2_ASAP7_75t_SL 9 59.500 25.900 91.900 + cpu/FE_OFN854_stage2_inst_2 - - R (net) 9 - - - + cpu/stage2/alusel/g764/Y - B->Y R OR2x2_ASAP7_75t_SL 3 25.000 15.600 107.500 + cpu/stage2/alusel/n_5 - - R (net) 3 - - - + cpu/stage2/alusel/g759/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 10.800 13.500 121.000 + cpu/stage2/alusel/n_9 - - F (net) 2 - - - + cpu/stage2/alusel/g755/Y - B->Y R NAND2xp5_ASAP7_75t_SL 3 26.600 18.400 139.400 + cpu/stage2/alusel/n_14 - - R (net) 3 - - - + cpu/stage2/alusel/FE_OFC746_n_14/Y - A->Y F INVx1_ASAP7_75t_SL 2 29.400 7.300 146.700 + cpu/stage2/alusel/n_13 - - F (net) 2 - - - + cpu/stage2/alusel/g751/Y - B->Y F AND2x2_ASAP7_75t_SL 3 13.600 15.200 161.900 + cpu/stage2/alusel/n_17 - - F (net) 3 - - - + cpu/stage2/alusel/g746/Y - B1->Y F AO221x1_ASAP7_75t_SL 1 12.100 18.700 180.600 + cpu/stage2/ALUop[1] - - F (net) 1 - - - + cpu/stage2/alu/FE_OFC626_ALUop_1/Y - A->Y R INVx1_ASAP7_75t_SL 5 13.400 21.500 202.100 + cpu/stage2/alu/n_0 - - R (net) 5 - - - + cpu/stage2/alu/FE_OFC627_ALUop_1/Y - A->Y F INVx1_ASAP7_75t_SL 4 37.200 15.600 217.700 + cpu/stage2/alu/FE_OFN823_ALUop_1 - - F (net) 4 - - - + cpu/stage2/alu/g3304/Y - B->Y R NOR2x1_ASAP7_75t_SL 3 25.000 13.200 230.900 + cpu/stage2/alu/n_194 - - R (net) 3 - - - + cpu/stage2/alu/g3302/Y - A->Y R AND3x4_ASAP7_75t_SL 9 23.600 26.700 257.600 + cpu/stage2/alu/n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC775_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 3 29.000 15.400 273.000 + cpu/stage2/alu/FE_OFN922_n_325 - - F (net) 3 - - - + cpu/stage2/alu/FE_OFC778_n_325/Y - A->Y R INVx3_ASAP7_75t_SL 9 24.200 24.000 297.000 + cpu/stage2/alu/FE_OFN925_n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC782_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 7 44.400 41.300 338.300 + cpu/stage2/alu/FE_OFN929_n_325 - - F (net) 7 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1722/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 2 72.200 24.100 362.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_36 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1655/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 45.200 24.300 386.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_116 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A1->Y F OA21x2_ASAP7_75t_SL 3 43.900 22.200 408.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y R OAI321xp33_ASAP7_75t_SL 1 13.300 17.300 426.200 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y F INVx1_ASAP7_75t_SL 2 42.800 11.500 437.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 21.200 19.000 456.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 10.600 16.200 472.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 10.800 9.200 482.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y R OR2x2_ASAP7_75t_SL 3 18.000 17.600 499.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y F AOI31xp67_ASAP7_75t_SL 3 15.800 16.400 516.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 34.100 15.700 531.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y R OR2x2_ASAP7_75t_SL 3 32.100 25.500 557.300 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 27.300 15.500 572.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y F NAND2xp5_ASAP7_75t_L 2 12.900 11.700 584.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 18.800 14.600 599.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 37.100 10.300 609.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y R INVx1_ASAP7_75t_SL 3 20.500 13.500 622.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.500 16.600 639.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 16.200 12.900 652.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 22.100 19.100 671.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 11.700 17.200 688.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 12.100 17.200 705.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_6 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1505/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 11.900 14.000 719.900 + cpu/stage2/alu/n_321 - - F (net) 1 - - - + cpu/stage2/alu/g5504/Y - A2->Y F AO21x1_ASAP7_75t_SL 4 18.300 27.700 747.600 + dcache_addr[30] - - F (net) 4 - - - + cpu/s2_to_s3_alu/g434__7098/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 32.800 11.200 758.800 + cpu/s2_to_s3_alu/n_17 - - R (net) 1 - - - + cpu/s2_to_s3_alu/register_reg[30]/D - D R DFFHQNx1_ASAP7_75t_SL 1 49.100 0.000 758.800 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_alu/CLKGATE_RC_CG_HIER_INST5/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s2_to_s3_alu/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s2_to_s3_alu/register_reg[30]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 46: MET (37.519 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[29]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s1_to_s2_inst/register_reg[2]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.081 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.919 + Launch Clock:= 0.000 + Data Path:+ 754.400 + Slack:= 37.519 + Timing Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_inst/CLKGATE_RC_CG_HIER_INST1/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 0.000 + cpu/s1_to_s2_inst/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_inst/register_reg[2]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_SL 1 0.100 30.000 30.000 + cpu/stage2_inst[2] - - R (net) 1 - - - + cpu/FE_OFC948_stage2_inst_2/Y - A->Y F INVx1_ASAP7_75t_SL 2 13.500 6.400 36.400 + cpu/FE_OFN851_stage2_inst_2 - - F (net) 2 - - - + cpu/FE_OFC952_stage2_inst_2/Y - A->Y R INVx1_ASAP7_75t_SL 13 9.500 29.600 66.000 + cpu/FE_OFN850_stage2_inst_2 - - R (net) 13 - - - + cpu/FE_OFC670_stage2_inst_2/Y - A->Y R BUFx2_ASAP7_75t_SL 9 59.500 25.900 91.900 + cpu/FE_OFN854_stage2_inst_2 - - R (net) 9 - - - + cpu/stage2/alusel/g764/Y - B->Y R OR2x2_ASAP7_75t_SL 3 25.000 15.600 107.500 + cpu/stage2/alusel/n_5 - - R (net) 3 - - - + cpu/stage2/alusel/g759/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 10.800 13.500 121.000 + cpu/stage2/alusel/n_9 - - F (net) 2 - - - + cpu/stage2/alusel/g755/Y - B->Y R NAND2xp5_ASAP7_75t_SL 3 26.600 18.400 139.400 + cpu/stage2/alusel/n_14 - - R (net) 3 - - - + cpu/stage2/alusel/FE_OFC746_n_14/Y - A->Y F INVx1_ASAP7_75t_SL 2 29.400 7.300 146.700 + cpu/stage2/alusel/n_13 - - F (net) 2 - - - + cpu/stage2/alusel/g751/Y - B->Y F AND2x2_ASAP7_75t_SL 3 13.600 15.200 161.900 + cpu/stage2/alusel/n_17 - - F (net) 3 - - - + cpu/stage2/alusel/g746/Y - B1->Y F AO221x1_ASAP7_75t_SL 1 12.100 18.700 180.600 + cpu/stage2/ALUop[1] - - F (net) 1 - - - + cpu/stage2/alu/FE_OFC626_ALUop_1/Y - A->Y R INVx1_ASAP7_75t_SL 5 13.400 21.500 202.100 + cpu/stage2/alu/n_0 - - R (net) 5 - - - + cpu/stage2/alu/FE_OFC627_ALUop_1/Y - A->Y F INVx1_ASAP7_75t_SL 4 37.200 15.600 217.700 + cpu/stage2/alu/FE_OFN823_ALUop_1 - - F (net) 4 - - - + cpu/stage2/alu/g3304/Y - B->Y R NOR2x1_ASAP7_75t_SL 3 25.000 13.200 230.900 + cpu/stage2/alu/n_194 - - R (net) 3 - - - + cpu/stage2/alu/g3302/Y - A->Y R AND3x4_ASAP7_75t_SL 9 23.600 26.700 257.600 + cpu/stage2/alu/n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC775_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 3 29.000 15.400 273.000 + cpu/stage2/alu/FE_OFN922_n_325 - - F (net) 3 - - - + cpu/stage2/alu/FE_OFC778_n_325/Y - A->Y R INVx3_ASAP7_75t_SL 9 24.200 24.000 297.000 + cpu/stage2/alu/FE_OFN925_n_325 - - R (net) 9 - - - + cpu/stage2/alu/FE_OFC782_n_325/Y - A->Y F INVx1_ASAP7_75t_SL 7 44.400 41.300 338.300 + cpu/stage2/alu/FE_OFN929_n_325 - - F (net) 7 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1722/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 2 72.200 24.100 362.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_36 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1655/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 45.200 24.300 386.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_116 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A1->Y F OA21x2_ASAP7_75t_SL 3 43.900 22.200 408.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_181 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y R OAI321xp33_ASAP7_75t_SL 1 13.300 17.300 426.200 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_183 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y F INVx1_ASAP7_75t_SL 2 42.800 11.500 437.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_184 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 21.200 19.000 456.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_188 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 10.600 16.200 472.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_190 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 10.800 9.200 482.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_192 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y R OR2x2_ASAP7_75t_SL 3 18.000 17.600 499.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_195 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y F AOI31xp67_ASAP7_75t_SL 3 15.800 16.400 516.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_1 - - F (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 34.100 15.700 531.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_207 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y R OR2x2_ASAP7_75t_SL 3 32.100 25.500 557.300 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_209 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 27.300 15.500 572.800 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_212 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y F NAND2xp5_ASAP7_75t_L 2 12.900 11.700 584.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_216 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 18.800 14.600 599.100 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_226 - - R (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 37.100 10.300 609.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_229 - - F (net) 1 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y R INVx1_ASAP7_75t_SL 3 20.500 13.500 622.900 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_2 - - R (net) 3 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 21.500 16.600 639.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_231 - - R (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 2 16.200 12.900 652.400 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_3 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 22.100 19.100 671.500 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_4 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 11.700 17.200 688.700 + cpu/stage2/alu/sub_25_21_Y_add_24_21_n_5 - - F (net) 2 - - - + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1508/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 12.100 14.100 702.800 + cpu/stage2/alu/n_320 - - F (net) 1 - - - + cpu/stage2/alu/g5506/Y - A2->Y F AO21x1_ASAP7_75t_L 4 18.300 32.900 735.700 + dcache_addr[29] - - F (net) 4 - - - + cpu/stage3/csr/g164/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 36.300 18.700 754.400 + cpu/stage3/csr/n_31 - - R (net) 1 - - - + cpu/stage3/csr/csr_reg[29]/D - D R DFFHQNx1_ASAP7_75t_SL 1 56.700 0.800 754.400 +#-------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage3/csr/CLKGATE_RC_CG_HIER_INST40/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage3/csr/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage3/csr/csr_reg[29]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#------------------------------------------------------------------------------------------------------------------------------------------- +Path 47: MET (38.330 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.570 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.430 + Launch Clock:= 0.000 + Data Path:+ 753.100 + Slack:= 38.330 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.700 520.000 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 160.100 34.400 554.400 + cpu/stage1/regfile/n_345 - - F (net) 4 - - - + cpu/stage1/regfile/g78531/Y - B->Y R NOR2xp67_ASAP7_75t_SL 12 76.500 102.200 656.600 + cpu/stage1/regfile/n_622 - - R (net) 12 - - - + cpu/stage1/regfile/g77587/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 195.400 19.800 676.400 + cpu/stage1/regfile/n_1549 - - F (net) 1 - - - + cpu/stage1/regfile/g77262/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 69.500 18.200 694.600 + cpu/stage1/regfile/n_1867 - - R (net) 1 - - - + cpu/stage1/regfile/g77096/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 30.200 10.500 705.100 + cpu/stage1/regfile/n_2013 - - F (net) 1 - - - + cpu/stage1/regfile/g76938__8246/Y - B->Y R NAND5xp2_ASAP7_75t_SL 1 49.700 19.000 724.100 + cpu/stage1/rs2_mux_data[15] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g545__2883/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 38.900 21.200 745.300 + cpu/stage1_rs2[15] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g450__1666/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 16.400 7.800 753.100 + cpu/s1_to_s2_rs2/n_1 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[15]/D - D F DFFHQNx1_ASAP7_75t_SL 1 59.900 0.100 753.100 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[15]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 48: MET (38.906 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[28]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.494 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.506 + Launch Clock:= 0.000 + Data Path:+ 752.600 + Slack:= 38.906 + Timing Path: + +#----------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#----------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.800 394.800 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 14.500 37.300 432.100 + cpu/stage1_inst[21] - - R (net) 11 - - - + cpu/stage1/regfile/FE_OFC458_stage1_inst_21/Y - A->Y F INVx1_ASAP7_75t_SL 3 58.300 14.200 446.300 + cpu/stage1/regfile/n_194 - - F (net) 3 - - - + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 27.100 73.700 520.000 + cpu/stage1/regfile/n_243 - - R (net) 8 - - - + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 160.100 34.400 554.400 + cpu/stage1/regfile/n_345 - - F (net) 4 - - - + cpu/stage1/regfile/g78531/Y - B->Y R NOR2xp67_ASAP7_75t_SL 12 76.500 99.800 654.200 + cpu/stage1/regfile/n_622 - - R (net) 12 - - - + cpu/stage1/regfile/g77762/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 195.500 19.600 673.800 + cpu/stage1/regfile/n_1378 - - F (net) 1 - - - + cpu/stage1/regfile/g77279/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 69.400 21.100 694.900 + cpu/stage1/regfile/n_1850 - - R (net) 1 - - - + cpu/stage1/regfile/g77103/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 33.700 10.700 705.600 + cpu/stage1/regfile/n_2006 - - F (net) 1 - - - + cpu/stage1/regfile/g76888__4733/Y - B->Y R NAND5xp2_ASAP7_75t_SL 1 49.600 19.400 725.000 + cpu/stage1/rs2_mux_data[28] - - R (net) 1 - - - + cpu/stage1/data2sel_s1/g546__2346/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 44.300 20.300 745.300 + cpu/stage1_rs2[28] - - R (net) 1 - - - + cpu/s1_to_s2_rs2/g447__9945/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 14.000 7.300 752.600 + cpu/s1_to_s2_rs2/n_4 - - F (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[28]/D - D F DFFHQNx1_ASAP7_75t_SL 1 59.600 0.100 752.600 +#----------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[28]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 49: MET (43.699 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 8.301 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 791.699 + Launch Clock:= 0.000 + Data Path:+ 748.000 + Slack:= 43.699 + Timing Path: + +#------------------------------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#------------------------------------------------------------------------------------------------------------------------------------------------------ + clk - clk R (arrival) 47 0.000 0.000 -0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 -0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/FE_DBTC75_NOPSignal/Y - A->Y R INVx5_ASAP7_75t_SL 10 13.600 9.400 394.400 + cpu/stage1/nopselmux/FE_DBTN75_NOPSignal - - R (net) 10 - - - + cpu/stage1/nopselmux/g397__7410/Y - B->Y R AND2x4_ASAP7_75t_SL 44 14.300 75.100 469.500 + cpu/stage1_inst[22] - - R (net) 44 - - - + cpu/stage1/regfile/g80400/Y - B->Y F NOR2xp33_ASAP7_75t_L 10 215.500 131.300 600.800 + cpu/stage1/regfile/n_241 - - F (net) 10 - - - + cpu/stage1/regfile/g78430/Y - A->Y F AND2x2_ASAP7_75t_SL 10 182.800 63.500 664.300 + cpu/stage1/regfile/n_780 - - F (net) 10 - - - + cpu/stage1/regfile/g77415/Y - C1->Y R AOI222xp33_ASAP7_75t_SL 1 46.000 18.500 682.800 + cpu/stage1/regfile/n_1725 - - R (net) 1 - - - + cpu/stage1/regfile/g76947__9945/Y - C->Y F NAND5xp2_ASAP7_75t_SL 1 34.500 30.000 712.800 + cpu/stage1/rs2_mux_data[14] - - F (net) 1 - - - + cpu/stage1/data2sel_s1/g576__7410/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 70.300 25.500 738.300 + cpu/stage1_rs2[14] - - F (net) 1 - - - + cpu/s1_to_s2_rs2/g437__5122/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 15.000 9.700 748.000 + cpu/s1_to_s2_rs2/n_14 - - R (net) 1 - - - + cpu/s1_to_s2_rs2/register_reg[14]/D - D R DFFHQNx1_ASAP7_75t_SL 1 58.000 0.100 748.000 +#------------------------------------------------------------------------------------------------------------------------------------------------------ + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/s1_to_s2_rs2/CLKGATE_RC_CG_HIER_INST4/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/s1_to_s2_rs2/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/s1_to_s2_rs2/register_reg[14]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- +Path 50: MET (43.943 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[25]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: reg2reg + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[5]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[25]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900.000 0.000 + Src Latency:+ 0.000 0.000 + Net Latency:+ 0.000 (I) 0.000 (I) + Arrival:= 900.000 0.000 + + Setup:- 7.757 + Uncertainty:- 100.000 + Cppr Adjust:+ 0.000 + Required Time:= 792.243 + Launch Clock:= 0.000 + Data Path:+ 748.300 + Slack:= 43.943 + Timing Path: + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 0.000 + clk - - R (net) 47 - - - + cpu/s2_to_s3_inst/CLKGATE_RC_CG_HIER_INST6/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 15 4.000 0.000 0.000 + cpu/s2_to_s3_inst/CLKGATE_rc_gclk - - R (net) 15 - - - + cpu/s2_to_s3_inst/register_reg[5]/Q - CLK->Q F DFFHQx4_ASAP7_75t_SL 2 0.100 41.200 41.200 + cpu/stage3_inst[5] - - F (net) 2 - - - + cpu/stage3/ldsel/FE_OFC455_stage3_inst_5/Y - A->Y R INVx2_ASAP7_75t_SL 1 7.700 3.900 45.100 + cpu/stage3/ldsel/n_4 - - R (net) 1 - - - + cpu/stage3/ldsel/g215/Y - A->Y R AND3x2_ASAP7_75t_SL 1 4.800 17.700 62.800 + cpu/stage3/ldsel/n_11 - - R (net) 1 - - - + cpu/stage3/ldsel/g213/Y - B->Y F NAND2x2_ASAP7_75t_SL 2 13.300 6.800 69.600 + cpu/stage3/ldsel/n_14 - - F (net) 2 - - - + cpu/stage3/ldsel/g205/Y - A->Y F OR2x2_ASAP7_75t_SL 4 11.200 18.900 88.500 + cpu/stage3/LdSelect[0] - - F (net) 4 - - - + cpu/stage3/ldselmux/FE_OFC955_LdSelect_0/Y - A->Y R INVx3_ASAP7_75t_SL 1 14.000 6.700 95.200 + cpu/stage3/ldselmux/n_14 - - R (net) 1 - - - + cpu/stage3/ldselmux/FE_OFC956_LdSelect_0/Y - A->Y F INVx4_ASAP7_75t_SL 5 9.400 6.600 101.800 + cpu/stage3/ldselmux/FE_OFN759_LdSelect_0 - - F (net) 5 - - - + cpu/stage3/ldselmux/g2421/Y - A->Y R NAND2x1p5_ASAP7_75t_SL 4 9.300 11.100 112.900 + cpu/stage3/ldselmux/n_34 - - R (net) 4 - - - + cpu/stage3/ldselmux/g2401/Y - B->Y R OR2x2_ASAP7_75t_SL 1 18.600 14.600 127.500 + cpu/stage3/ldselmux/n_46 - - R (net) 1 - - - + cpu/stage3/ldselmux/g2367/Y - A2->Y F AOI21x1_ASAP7_75t_SL 2 9.100 7.300 134.800 + cpu/stage3/ldselmux/n_83 - - F (net) 2 - - - + cpu/stage3/ldselmux/FE_OFC1221_n_83/Y - A->Y R INVx1_ASAP7_75t_SL 7 14.000 17.900 152.700 + cpu/stage3/ldselmux/FE_OFN1221_n_83 - - R (net) 7 - - - + cpu/stage3/ldselmux/g2299/Y - A2->Y F OAI211xp5_ASAP7_75t_SL 1 33.100 24.600 177.300 + cpu/stage3/wb_dmem[7] - - F (net) 1 - - - + cpu/stage3/wbselmux/g1106/Y - A1->Y F AO21x2_ASAP7_75t_SL 5 44.100 30.000 207.300 + cpu/wb_data[7] - - F (net) 5 - - - + cpu/stage2/rs2DataSel/g592/Y - A1->Y F AO21x2_ASAP7_75t_SL 8 20.700 30.000 237.300 + cpu/stage2/stage2_rs2_data[7] - - F (net) 8 - - - + cpu/stage2/branchcomp/FE_DBTC17_stage2_rs2_data_7/Y - A->Y R INVx2_ASAP7_75t_SL 3 28.900 11.000 248.300 + cpu/stage2/branchcomp/FE_DBTN17_stage2_rs2_data_7 - - R (net) 3 - - - + cpu/stage2/branchcomp/lt_12_36_g814/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 17.100 7.800 256.100 + cpu/stage2/branchcomp/lt_12_36_n_68 - - F (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g768/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 14.800 10.300 266.400 + cpu/stage2/branchcomp/lt_12_36_n_102 - - R (net) 2 - - - + cpu/stage2/branchcomp/lt_12_36_g748/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 18.000 7.700 274.100 + cpu/stage2/branchcomp/lt_12_36_n_115 - - F (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g725/Y - A1->Y R OAI21xp5_ASAP7_75t_SL 1 13.100 12.900 287.000 + cpu/stage2/branchcomp/lt_12_36_n_138 - - R (net) 1 - - - + cpu/stage2/branchcomp/lt_12_36_g723/Y - A2->Y F A2O1A1O1Ixp25_ASAP7_75t_SL 1 22.800 20.500 307.500 + cpu/stage2/branchcomp/n_146 - - F (net) 1 - - - + cpu/stage2/branchcomp/g922/Y - A1->Y F AO22x2_ASAP7_75t_SL 2 38.600 25.000 332.500 + cpu/BrLT - - F (net) 2 - - - + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 13.700 14.200 346.700 + cpu/stage1/pcsel/n_9 - - F (net) 2 - - - + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 10.900 7.400 354.100 + cpu/stage1/pcsel/n_25 - - R (net) 2 - - - + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 13.100 9.200 363.300 + cpu/stage1/PCSelect[0] - - F (net) 2 - - - + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 3 14.000 21.700 385.000 + cpu/stage1/NOPSignal - - F (net) 3 - - - + cpu/stage1/nopselmux/g413__5122/Y - B->Y R NOR2x2_ASAP7_75t_SL 3 13.600 17.800 402.800 + cpu/stage1/FE_OFN1105_stage1_inst_18 - - R (net) 3 - - - + cpu/stage1/regfile/FE_OFC1252_stage1_inst_18/Y - A->Y F INVx4_ASAP7_75t_SL 1 34.500 8.400 411.200 + cpu/stage1/regfile/FE_OFN967_stage1_inst_18 - - F (net) 1 - - - + cpu/stage1/regfile/FE_OFC1255_stage1_inst_18/Y - A->Y R INVx8_ASAP7_75t_SL 13 15.700 11.700 422.900 + cpu/stage1/regfile/FE_OFN1156_n - - R (net) 13 - - - + cpu/stage1/regfile/FE_RC_2_0/Y - B->Y F NAND2x2_ASAP7_75t_SL 1 20.900 9.700 432.600 + cpu/stage1/regfile/FE_RN_0_0 - - F (net) 1 - - - + cpu/stage1/regfile/FE_RC_3_0/Y - A->Y R INVx8_ASAP7_75t_SL 22 16.900 17.600 450.200 + cpu/stage1/regfile/n_211 - - R (net) 22 - - - + cpu/stage1/regfile/FE_OFC990_n_211/Y - A->Y F INVx4_ASAP7_75t_SL 2 23.300 7.600 457.800 + cpu/stage1/regfile/FE_OFN101_n_211 - - F (net) 2 - - - + cpu/stage1/regfile/FE_OFC1241_n_211/Y - A->Y R INVx5_ASAP7_75t_SL 9 12.600 12.000 469.800 + cpu/stage1/regfile/FE_OFN1089_n_211 - - R (net) 9 - - - + cpu/stage1/regfile/g79842/Y - A->Y R AND2x4_ASAP7_75t_SL 10 19.800 28.400 498.200 + cpu/stage1/regfile/n_306 - - R (net) 10 - - - + cpu/stage1/regfile/g77098/Y - B2->Y F AOI22xp5_ASAP7_75t_SL 1 38.700 13.700 511.900 + cpu/stage1/regfile/n_2011 - - F (net) 1 - - - + cpu/stage1/regfile/g76917__6161/Y - A3->Y R AOI31xp67_ASAP7_75t_SL 1 25.200 14.000 525.900 + cpu/stage1/regfile/n_2165 - - R (net) 1 - - - + cpu/stage1/regfile/g76880__1705/Y - A->Y F NOR2x1_ASAP7_75t_SL 1 26.600 10.800 536.700 + cpu/stage1/regfile/n_2178 - - F (net) 1 - - - + cpu/stage1/regfile/g76874__8428/Y - C->Y R NAND3x1_ASAP7_75t_SL 1 16.200 24.300 561.000 + cpu/stage1/rs1_mux_data[8] - - R (net) 1 - - - + cpu/stage1/data1sel_s1/g573__2346/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 41.600 22.800 583.800 + cpu/stage1_rs1[8] - - R (net) 2 - - - + cpu/stage1/pcadder/g1249__2883/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 18.100 17.600 601.400 + cpu/stage1/pcadder/n_39 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1498__5122/Y - B->Y F NAND2x1p5_ASAP7_75t_SL 3 22.700 8.300 609.700 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_4 - - F (net) 3 - - - + cpu/stage1/pcadder/FE_RC_8_0/Y - A1->Y R OAI21x1_ASAP7_75t_SL 2 15.300 12.700 622.400 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_162 - - R (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1327__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 1 22.200 7.800 630.200 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_177 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1315__6417/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 13.900 16.700 646.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_189 - - F (net) 2 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1305__9945/Y - A2->Y F OA21x2_ASAP7_75t_SL 1 9.000 15.900 662.800 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_196 - - F (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - B->Y R OAI21x1_ASAP7_75t_SL 3 9.200 15.700 678.500 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_18 - - R (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 47.100 16.400 694.900 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_19 - - F (net) 3 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1264__2346/Y - A1->Y R OAI21xp5_ASAP7_75t_L 1 30.100 16.100 711.000 + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_n_225 - - R (net) 1 - - - + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1252__7098/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 1 26.800 14.500 725.500 + cpu/stage1/stage1_pc4[25] - - R (net) 1 - - - + cpu/stage1/pcselmux/g946__6161/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 25.200 15.100 740.600 + cpu/stage1/stage1_pc_mux_to_pc[25] - - R (net) 2 - - - + cpu/stage1/pcreg/g353__1617/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 17.800 7.700 748.300 + cpu/stage1/pcreg/n_27 - - F (net) 1 - - - + cpu/stage1/pcreg/register_reg[25]/D - D F DFFHQNx1_ASAP7_75t_SL 1 56.700 0.100 748.300 +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + Other End Path: + +#-------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Trans Delay Arrival +# (ps) (ps) (ps) +#-------------------------------------------------------------------------------------------------------------------------------------------- + clk - clk R (arrival) 47 0.000 0.000 900.000 + clk - - R (net) 47 - - - + cpu/stage1/pcreg/CLKGATE_RC_CG_HIER_INST8/RC_CGIC_INST/GCLK - CLK->GCLK R ICGx1_ASAP7_75t_R 32 4.000 0.000 900.000 + cpu/stage1/pcreg/CLKGATE_rc_gclk - - R (net) 32 - - - + cpu/stage1/pcreg/register_reg[25]/CLK - CLK R DFFHQNx1_ASAP7_75t_SL 32 0.100 0.000 900.000 +#-------------------------------------------------------------------------------------------------------------------------------------------- + diff --git a/build/syn-rundir/reports/final.rpt b/build/syn-rundir/reports/final.rpt new file mode 100644 index 0000000..879a88e --- /dev/null +++ b/build/syn-rundir/reports/final.rpt @@ -0,0 +1,51 @@ + + +Working Directory = /home/cc/eecs151/fa20/class/eecs151-abr/project/build/syn-rundir +QoS Summary for riscv_top +================================================================================ +Metric final +================================================================================ +Slack (ps): 27 + R2R (ps): 27 + I2R (ps): 274 + R2O (ps): no_value + I2O (ps): no_value + CG (ps): 81 +TNS (ps): 0 + R2R (ps): 0 + I2R (ps): 0 + R2O (ps): no_value + I2O (ps): no_value + CG (ps): 0 +Failing Paths: 0 +Cell Area: 56,137 +Total Cell Area: 56,137 +Leaf Instances: 9,616 +Total Instances: 9,616 +Utilization (%): 0.00 +Tot. Net Length (um): no_value +Avg. Net Length (um): no_value +Route Overflow H (%): no_value +Route Overflow V (%): no_value +MBCI(%) (bits/gate) : 0.00 +Norm Cong Hotspot Area: + Max Cong: no_value + Tot Cong: no_value +================================================================================ +CPU Runtime (h:m:s): 00:05:51 +Real Runtime (h:m:s): 00:04:24 +CPU Elapsed (h:m:s): 00:05:58 +Real Elapsed (h:m:s): 00:04:26 +Memory (MB): 1091.00 +================================================================================ +================================================================================ +Flow Settings: +================================================================================ +Total Runtime (h:m:s): 00:04:27 +Total Memory (MB): 1091.00 +Executable Version: 19.11-s087_1 +================================================================================ +Total Cell Area = Cell Area + Physical Cell Area +Total Instances = Leaf Instances + Physical Instances + + diff --git a/build/syn-rundir/reports/final_area.rpt b/build/syn-rundir/reports/final_area.rpt new file mode 100644 index 0000000..b69dd82 --- /dev/null +++ b/build/syn-rundir/reports/final_area.rpt @@ -0,0 +1,122 @@ +============================================================ + Generated by: Genus(TM) Synthesis Solution 19.11-s087_1 + Generated on: Dec 14 2020 09:46:20 pm + Module: riscv_top + Library domain: PVT_0P63V_100C.setup_cond + Domain index: 0 + Technology libraries: asap7sc7p5t_22b_SIMPLE_RVT_SS_170906 1.0 + asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 1.0 + asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_SIMPLE_SRAM_SS_170906 1.0 + asap7sc7p5t_22b_AO_RVT_SS_170906 1.0 + asap7sc7p5t_22b_AO_LVT_SS_170906 1.0 + asap7sc7p5t_22b_AO_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_AO_SRAM_SS_170906 1.0 + asap7sc7p5t_22b_OA_RVT_SS_170906 1.0 + asap7sc7p5t_22b_OA_LVT_SS_170906 1.0 + asap7sc7p5t_22b_OA_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_OA_SRAM_SS_170906 1.0 + asap7sc7p5t_22b_SEQ_RVT_SS_170906 1.0 + asap7sc7p5t_22b_SEQ_LVT_SS_170906 1.0 + asap7sc7p5t_22b_SEQ_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_SEQ_SRAM_SS_170906 1.0 + asap7sc7p5t_22b_INVBUF_RVT_SS_170906 1.0 + asap7sc7p5t_22b_INVBUF_LVT_SS_170906 1.0 + asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_INVBUF_SRAM_SS_170906 1.0 + SRAM1RW1024x8_PVT_0P63V_100C 0 + SRAM1RW128x46_PVT_0P63V_100C 0 + SRAM1RW128x48_PVT_0P63V_100C 0 + SRAM1RW128x8_PVT_0P63V_100C 0 + SRAM1RW256x128_PVT_0P63V_100C 0 + SRAM1RW256x32_PVT_0P63V_100C 0 + SRAM1RW256x46_PVT_0P63V_100C 0 + SRAM1RW256x48_PVT_0P63V_100C 0 + SRAM1RW256x8_PVT_0P63V_100C 0 + SRAM1RW32x50_PVT_0P63V_100C 0 + SRAM1RW512x128_PVT_0P63V_100C 0 + SRAM1RW512x32_PVT_0P63V_100C 0 + SRAM1RW512x8_PVT_0P63V_100C 0 + SRAM1RW64x128_PVT_0P63V_100C 0 + SRAM1RW64x32_PVT_0P63V_100C 0 + SRAM1RW64x34_PVT_0P63V_100C 0 + SRAM1RW64x8_PVT_0P63V_100C 0 + SRAM2RW128x16_PVT_0P63V_100C 0 + SRAM2RW128x32_PVT_0P63V_100C 0 + SRAM2RW128x4_PVT_0P63V_100C 0 + SRAM2RW128x8_PVT_0P63V_100C 0 + SRAM2RW16x16_PVT_0P63V_100C 0 + SRAM2RW16x32_PVT_0P63V_100C 0 + SRAM2RW16x4_PVT_0P63V_100C 0 + SRAM2RW16x8_PVT_0P63V_100C 0 + SRAM2RW32x16_PVT_0P63V_100C 0 + SRAM2RW32x22_PVT_0P63V_100C 0 + SRAM2RW32x32_PVT_0P63V_100C 0 + SRAM2RW32x39_PVT_0P63V_100C 0 + SRAM2RW32x4_PVT_0P63V_100C 0 + SRAM2RW32x8_PVT_0P63V_100C 0 + SRAM2RW64x16_PVT_0P63V_100C 0 + SRAM2RW64x32_PVT_0P63V_100C 0 + SRAM2RW64x4_PVT_0P63V_100C 0 + SRAM2RW64x8_PVT_0P63V_100C 0 + Operating conditions: PVT_0P63V_100C + Interconnect mode: global + Area mode: physical library +============================================================ + + Instance Module Cell Count Cell Area Net Area Total Area +--------------------------------------------------------------------------------- +riscv_top 9616 56136.692 7450.433 63587.125 + mem Memory151 1539 41473.644 1188.962 42662.607 + dcache cache_1 795 20852.412 670.024 21522.436 + icache cache 653 20512.757 464.101 20976.857 + arbiter riscv_arbiter 43 73.017 9.042 82.058 + cpu Riscv151 8067 14656.049 5891.930 20547.979 + stage1 Stage1Module 4436 9303.906 3225.532 12529.438 + regfile RegFile 3334 7835.642 2679.264 10514.906 + pcadder Adder 348 452.796 233.662 686.458 + pcreg FlipFlop 73 191.989 22.815 214.804 + pcselmux PCSelMux 74 119.906 44.517 164.423 + data1sel_s1 DataSelMux 78 91.679 35.821 127.500 + immgen ImmGen 48 71.150 24.260 95.410 + data2sel_s1 DataSelMux_181 33 67.884 8.031 75.916 + nopselmux NOPSelMux 40 61.586 10.551 72.137 + pcsel PCSel 37 47.123 19.145 66.267 + rs1DataSel_s1 Data1Sel 25 36.158 11.970 48.129 + rs2DataSel_s1 Data2Sel 25 34.759 12.699 47.458 + nopsel NOPSel 16 26.127 7.724 33.852 + immsel ImmSel 16 17.963 8.671 26.633 + pcaddsignal PCAddSignal 6 6.299 2.238 8.537 + regwen RegWEn 3 3.499 0.998 4.497 + stage2 Stage2Module 2181 2829.686 1691.838 4521.524 + alu ALU 1139 1529.384 885.986 2415.370 + branchcomp BranchComp 377 481.956 214.249 696.205 + rs2DataSel DataSelMux_179 68 104.509 25.731 130.240 + rs1DataSel DataSelMux_180 67 99.377 25.475 124.852 + storeselmux StoreSelMux 59 91.446 32.905 124.351 + bselmux BSelMux 45 87.480 14.016 101.496 + aselmux ASelMux 33 68.118 8.031 76.149 + data2sel Data2Sel_178 37 52.721 19.413 72.134 + data1sel Data1Sel_177 31 46.656 15.935 62.591 + alusel ALUdec 26 32.659 15.346 48.006 + asel ASel 7 10.264 3.479 13.743 + bsel BSel 7 10.264 2.993 13.257 + storesel StoreSel 8 9.331 2.993 12.324 + brun BrUn 4 4.899 1.496 6.395 + stage3 Stage3Module 628 852.172 290.162 1142.334 + ldselmux LdSelMux 150 187.091 91.170 278.261 + pcfour PCFour 115 154.665 57.677 212.342 + csr CSR 68 186.157 24.989 211.146 + wbselmux WBSelMux 74 128.771 43.545 172.316 + ldsel LdSel 22 34.292 11.177 45.469 + memrw MemRW 16 17.729 9.144 26.873 + wbsel WBSel 12 15.630 5.717 21.346 + csrsel CSRSel 9 10.964 3.990 14.954 + s2_to_s3_pc FlipFlop_8_188 69 199.454 24.759 224.213 + s2_to_s3_alu FlipFlop_8 69 189.657 24.759 214.415 + s1_to_s2_rs2 FlipFlop_8_186 69 186.391 24.759 211.150 + s1_to_s2_rs1 FlipFlop_8_185 69 186.391 24.759 211.150 + s1_to_s2_pc FlipFlop_8_183 69 186.391 24.759 211.150 + s1_to_s2_inst FlipFlop_8_182 69 186.391 24.759 211.150 + s1_to_s2_imm FlipFlop_8_184 69 186.391 24.759 211.150 + s2_to_s3_inst FlipFlop_8_187 53 123.405 12.405 135.810 diff --git a/build/syn-rundir/reports/final_gates.rpt b/build/syn-rundir/reports/final_gates.rpt new file mode 100644 index 0000000..d35901e --- /dev/null +++ b/build/syn-rundir/reports/final_gates.rpt @@ -0,0 +1,269 @@ +============================================================ + Generated by: Genus(TM) Synthesis Solution 19.11-s087_1 + Generated on: Dec 14 2020 09:46:25 pm + Module: riscv_top + Library domain: PVT_0P63V_100C.setup_cond + Domain index: 0 + Technology libraries: asap7sc7p5t_22b_SIMPLE_RVT_SS_170906 1.0 + asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 1.0 + asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_SIMPLE_SRAM_SS_170906 1.0 + asap7sc7p5t_22b_AO_RVT_SS_170906 1.0 + asap7sc7p5t_22b_AO_LVT_SS_170906 1.0 + asap7sc7p5t_22b_AO_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_AO_SRAM_SS_170906 1.0 + asap7sc7p5t_22b_OA_RVT_SS_170906 1.0 + asap7sc7p5t_22b_OA_LVT_SS_170906 1.0 + asap7sc7p5t_22b_OA_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_OA_SRAM_SS_170906 1.0 + asap7sc7p5t_22b_SEQ_RVT_SS_170906 1.0 + asap7sc7p5t_22b_SEQ_LVT_SS_170906 1.0 + asap7sc7p5t_22b_SEQ_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_SEQ_SRAM_SS_170906 1.0 + asap7sc7p5t_22b_INVBUF_RVT_SS_170906 1.0 + asap7sc7p5t_22b_INVBUF_LVT_SS_170906 1.0 + asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_INVBUF_SRAM_SS_170906 1.0 + SRAM1RW1024x8_PVT_0P63V_100C 0 + SRAM1RW128x46_PVT_0P63V_100C 0 + SRAM1RW128x48_PVT_0P63V_100C 0 + SRAM1RW128x8_PVT_0P63V_100C 0 + SRAM1RW256x128_PVT_0P63V_100C 0 + SRAM1RW256x32_PVT_0P63V_100C 0 + SRAM1RW256x46_PVT_0P63V_100C 0 + SRAM1RW256x48_PVT_0P63V_100C 0 + SRAM1RW256x8_PVT_0P63V_100C 0 + SRAM1RW32x50_PVT_0P63V_100C 0 + SRAM1RW512x128_PVT_0P63V_100C 0 + SRAM1RW512x32_PVT_0P63V_100C 0 + SRAM1RW512x8_PVT_0P63V_100C 0 + SRAM1RW64x128_PVT_0P63V_100C 0 + SRAM1RW64x32_PVT_0P63V_100C 0 + SRAM1RW64x34_PVT_0P63V_100C 0 + SRAM1RW64x8_PVT_0P63V_100C 0 + SRAM2RW128x16_PVT_0P63V_100C 0 + SRAM2RW128x32_PVT_0P63V_100C 0 + SRAM2RW128x4_PVT_0P63V_100C 0 + SRAM2RW128x8_PVT_0P63V_100C 0 + SRAM2RW16x16_PVT_0P63V_100C 0 + SRAM2RW16x32_PVT_0P63V_100C 0 + SRAM2RW16x4_PVT_0P63V_100C 0 + SRAM2RW16x8_PVT_0P63V_100C 0 + SRAM2RW32x16_PVT_0P63V_100C 0 + SRAM2RW32x22_PVT_0P63V_100C 0 + SRAM2RW32x32_PVT_0P63V_100C 0 + SRAM2RW32x39_PVT_0P63V_100C 0 + SRAM2RW32x4_PVT_0P63V_100C 0 + SRAM2RW32x8_PVT_0P63V_100C 0 + SRAM2RW64x16_PVT_0P63V_100C 0 + SRAM2RW64x32_PVT_0P63V_100C 0 + SRAM2RW64x4_PVT_0P63V_100C 0 + SRAM2RW64x8_PVT_0P63V_100C 0 + Operating conditions: PVT_0P63V_100C + Interconnect mode: global + Area mode: physical library +============================================================ + + Leakage Library + Gate Instances Area Power (nW) Library Domain +-------------------------------------------------------------------------------------------------------------- +A2O1A1Ixp33_ASAP7_75t_SL 19 26.594 755.125 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +A2O1A1O1Ixp25_ASAP7_75t_SL 4 8.398 206.304 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AND2x2_ASAP7_75t_L 17 23.795 253.405 asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 0 +AND2x2_ASAP7_75t_R 63 88.180 136.194 asap7sc7p5t_22b_SIMPLE_RVT_SS_170906 0 +AND2x2_ASAP7_75t_SL 299 418.504 28469.363 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +AND2x4_ASAP7_75t_SL 41 95.645 7694.049 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +AND2x6_ASAP7_75t_SL 7 19.596 1821.078 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +AND3x1_ASAP7_75t_L 3 4.199 24.343 asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 0 +AND3x1_ASAP7_75t_SL 19 26.594 1327.498 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +AND3x2_ASAP7_75t_SL 3 4.899 329.181 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +AND3x4_ASAP7_75t_SL 3 9.798 578.741 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +AND4x1_ASAP7_75t_L 5 8.165 121.032 asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 0 +AND4x1_ASAP7_75t_SL 31 50.622 4994.644 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +AND4x2_ASAP7_75t_SL 5 9.331 706.870 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +AND5x1_ASAP7_75t_SL 17 31.726 2251.841 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +AO21x1_ASAP7_75t_L 30 41.990 380.590 asap7sc7p5t_22b_AO_LVT_SS_170906 0 +AO21x1_ASAP7_75t_SL 154 215.551 11385.089 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AO21x1_ASAP7_75t_SRAM 22 30.793 7.407 asap7sc7p5t_22b_AO_SRAM_SS_170906 0 +AO21x2_ASAP7_75t_SL 79 129.004 8527.452 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AO221x1_ASAP7_75t_SL 23 53.654 1581.332 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AO222x2_ASAP7_75t_L 141 394.710 3457.885 asap7sc7p5t_22b_AO_LVT_SS_170906 0 +AO222x2_ASAP7_75t_SL 33 92.379 3904.835 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AO22x1_ASAP7_75t_L 23 48.289 199.922 asap7sc7p5t_22b_AO_LVT_SS_170906 0 +AO22x1_ASAP7_75t_SL 430 902.794 26966.389 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AO22x2_ASAP7_75t_SL 7 16.330 774.276 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AO31x2_ASAP7_75t_SL 6 22.395 1028.976 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AO32x1_ASAP7_75t_SL 9 16.796 665.351 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AO332x1_ASAP7_75t_SRAM 1 2.566 0.335 asap7sc7p5t_22b_AO_SRAM_SS_170906 0 +AOI211x1_ASAP7_75t_SL 2 5.599 112.271 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI211xp5_ASAP7_75t_L 2 2.799 7.606 asap7sc7p5t_22b_AO_LVT_SS_170906 0 +AOI211xp5_ASAP7_75t_SL 15 20.995 562.343 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI21x1_ASAP7_75t_SL 35 65.318 2368.667 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI21xp33_ASAP7_75t_SL 29 33.826 1154.101 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI21xp5_ASAP7_75t_L 11 12.830 47.398 asap7sc7p5t_22b_AO_LVT_SS_170906 0 +AOI21xp5_ASAP7_75t_SL 72 83.981 2379.110 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI221x1_ASAP7_75t_SL 1 3.266 36.992 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI221xp5_ASAP7_75t_SL 73 119.206 2223.196 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI222xp33_ASAP7_75t_SL 59 137.635 1311.997 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI22x1_ASAP7_75t_L 1 2.333 7.712 asap7sc7p5t_22b_AO_LVT_SS_170906 0 +AOI22x1_ASAP7_75t_SL 2 4.666 82.217 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI22xp33_ASAP7_75t_SL 145 202.954 3884.672 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI22xp5_ASAP7_75t_L 41 57.387 141.927 asap7sc7p5t_22b_AO_LVT_SS_170906 0 +AOI22xp5_ASAP7_75t_SL 714 999.372 17619.219 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI311xp33_ASAP7_75t_SL 1 1.633 34.110 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI31xp33_ASAP7_75t_SL 9 12.597 369.182 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI31xp67_ASAP7_75t_SL 11 33.359 904.513 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI321xp33_ASAP7_75t_SL 2 3.732 140.922 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI322xp5_ASAP7_75t_SL 10 20.995 473.486 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI32xp33_ASAP7_75t_SL 11 17.963 373.158 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +AOI33xp33_ASAP7_75t_SL 2 3.732 54.629 asap7sc7p5t_22b_AO_SLVT_SS_170906 0 +ASYNC_DFFHx1_ASAP7_75t_L 2 12.131 52.570 asap7sc7p5t_22b_SEQ_LVT_SS_170906 0 +BUFx10_ASAP7_75t_SL 1 3.266 380.774 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +BUFx12f_ASAP7_75t_SL 8 33.592 4155.484 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +BUFx2_ASAP7_75t_SL 39 45.490 3421.642 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +BUFx3_ASAP7_75t_L 1 1.400 16.689 asap7sc7p5t_22b_INVBUF_LVT_SS_170906 0 +BUFx3_ASAP7_75t_SL 2 2.799 248.669 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +BUFx4f_ASAP7_75t_L 1 1.866 28.906 asap7sc7p5t_22b_INVBUF_LVT_SS_170906 0 +BUFx4f_ASAP7_75t_SL 2 3.732 310.468 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +BUFx6f_ASAP7_75t_SL 7 16.330 1782.060 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +BUFx8_ASAP7_75t_SL 1 2.799 251.831 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +DFFHQNx1_ASAP7_75t_L 35 163.296 776.021 asap7sc7p5t_22b_SEQ_LVT_SS_170906 0 +DFFHQNx1_ASAP7_75t_R 2 9.331 5.671 asap7sc7p5t_22b_SEQ_RVT_SS_170906 0 +DFFHQNx1_ASAP7_75t_SL 1239 5780.678 180284.025 asap7sc7p5t_22b_SEQ_SLVT_SS_170906 0 +DFFHQx4_ASAP7_75t_SL 23 134.136 6721.009 asap7sc7p5t_22b_SEQ_SLVT_SS_170906 0 +DHLx1_ASAP7_75t_SL 72 251.942 8116.891 asap7sc7p5t_22b_SEQ_SLVT_SS_170906 0 +DLLx1_ASAP7_75t_SL 88 307.930 10088.788 asap7sc7p5t_22b_SEQ_SLVT_SS_170906 0 +HB1xp67_ASAP7_75t_L 23 21.462 117.457 asap7sc7p5t_22b_INVBUF_LVT_SS_170906 0 +HB1xp67_ASAP7_75t_SL 120 111.974 3891.633 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +ICGx1_ASAP7_75t_R 43 180.559 188.157 asap7sc7p5t_22b_SEQ_RVT_SS_170906 0 +INVx11_ASAP7_75t_SL 6 18.196 1856.399 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +INVx13_ASAP7_75t_SL 3 10.498 1165.380 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +INVx1_ASAP7_75t_L 119 83.281 500.271 asap7sc7p5t_22b_INVBUF_LVT_SS_170906 0 +INVx1_ASAP7_75t_SL 671 469.593 17564.236 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +INVx2_ASAP7_75t_L 13 12.131 122.343 asap7sc7p5t_22b_INVBUF_LVT_SS_170906 0 +INVx2_ASAP7_75t_SL 50 46.656 2595.013 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +INVx3_ASAP7_75t_L 4 4.666 43.266 asap7sc7p5t_22b_INVBUF_LVT_SS_170906 0 +INVx3_ASAP7_75t_SL 13 15.163 1288.286 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +INVx4_ASAP7_75t_L 2 2.799 48.456 asap7sc7p5t_22b_INVBUF_LVT_SS_170906 0 +INVx4_ASAP7_75t_SL 6 8.398 789.085 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +INVx5_ASAP7_75t_SL 7 11.431 1029.218 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +INVx6_ASAP7_75t_SL 2 3.732 334.975 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +INVxp33_ASAP7_75t_SL 3 2.100 28.784 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +INVxp67_ASAP7_75t_SL 102 71.384 2063.777 asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 0 +MAJIxp5_ASAP7_75t_SL 7 11.431 400.557 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NAND2x1_ASAP7_75t_SL 45 62.986 2031.368 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NAND2x1p5_ASAP7_75t_L 4 7.465 37.621 asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 0 +NAND2x1p5_ASAP7_75t_SL 20 37.325 1410.591 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NAND2x2_ASAP7_75t_SL 2 4.666 234.013 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NAND2xp33_ASAP7_75t_L 1 0.933 2.415 asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 0 +NAND2xp33_ASAP7_75t_SL 3 2.799 38.745 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NAND2xp5_ASAP7_75t_L 70 65.318 299.831 asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 0 +NAND2xp5_ASAP7_75t_R 159 148.366 102.061 asap7sc7p5t_22b_SIMPLE_RVT_SS_170906 0 +NAND2xp5_ASAP7_75t_SL 747 697.041 15333.184 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NAND2xp67_ASAP7_75t_SL 8 11.197 375.915 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NAND3x1_ASAP7_75t_SL 5 12.830 554.240 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NAND3x2_ASAP7_75t_SL 1 4.666 123.565 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NAND3xp33_ASAP7_75t_R 7 8.165 3.143 asap7sc7p5t_22b_SIMPLE_RVT_SS_170906 0 +NAND3xp33_ASAP7_75t_SL 64 74.650 3129.618 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NAND4xp25_ASAP7_75t_SL 36 50.388 2914.913 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NAND4xp75_ASAP7_75t_SL 12 39.191 3077.461 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NAND5xp2_ASAP7_75t_L 4 6.532 3.522 asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 0 +NAND5xp2_ASAP7_75t_SL 51 83.281 6262.325 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NOR2x1_ASAP7_75t_L 54 75.583 483.382 asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 0 +NOR2x1_ASAP7_75t_SL 54 75.583 3072.705 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NOR2x1p5_ASAP7_75t_L 3 5.599 36.326 asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 0 +NOR2x1p5_ASAP7_75t_SL 10 18.662 775.759 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NOR2x2_ASAP7_75t_SL 1 2.333 107.040 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NOR2xp33_ASAP7_75t_L 94 87.713 228.645 asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 0 +NOR2xp33_ASAP7_75t_R 210 195.955 74.189 asap7sc7p5t_22b_SIMPLE_RVT_SS_170906 0 +NOR2xp33_ASAP7_75t_SL 157 146.500 2807.288 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NOR2xp67_ASAP7_75t_SL 2 2.799 69.134 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NOR3x1_ASAP7_75t_SL 10 25.661 714.106 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NOR3xp33_ASAP7_75t_L 2 2.333 14.011 asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 0 +NOR3xp33_ASAP7_75t_R 4 4.666 2.711 asap7sc7p5t_22b_SIMPLE_RVT_SS_170906 0 +NOR3xp33_ASAP7_75t_SL 19 22.162 599.358 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NOR4xp25_ASAP7_75t_R 5 6.998 2.469 asap7sc7p5t_22b_SIMPLE_RVT_SS_170906 0 +NOR4xp25_ASAP7_75t_SL 12 16.796 445.079 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NOR4xp75_ASAP7_75t_SL 3 9.798 301.836 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +NOR5xp2_ASAP7_75t_L 5 8.165 11.096 asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 0 +NOR5xp2_ASAP7_75t_SL 5 8.165 105.785 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +O2A1O1Ixp33_ASAP7_75t_L 3 4.199 17.642 asap7sc7p5t_22b_OA_LVT_SS_170906 0 +O2A1O1Ixp33_ASAP7_75t_SL 7 9.798 236.360 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +O2A1O1Ixp5_ASAP7_75t_SL 1 1.866 26.833 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OA211x2_ASAP7_75t_SL 7 13.064 636.047 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OA211x2_ASAP7_75t_SRAM 1 1.866 0.484 asap7sc7p5t_22b_OA_SRAM_SS_170906 0 +OA21x2_ASAP7_75t_SL 41 66.951 4495.519 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OA21x2_ASAP7_75t_SRAM 27 44.090 16.019 asap7sc7p5t_22b_OA_SRAM_SS_170906 0 +OA222x2_ASAP7_75t_SL 3 8.398 317.360 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OAI211xp5_ASAP7_75t_SL 28 39.191 1773.097 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OAI21x1_ASAP7_75t_SL 23 42.924 2605.976 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OAI21xp33_ASAP7_75t_SL 5 5.832 159.526 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OAI21xp5_ASAP7_75t_L 27 31.493 175.205 asap7sc7p5t_22b_OA_LVT_SS_170906 0 +OAI21xp5_ASAP7_75t_SL 171 199.454 8952.919 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OAI221xp5_ASAP7_75t_L 3 4.899 10.301 asap7sc7p5t_22b_OA_LVT_SS_170906 0 +OAI221xp5_ASAP7_75t_SL 71 115.940 4014.241 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OAI222xp33_ASAP7_75t_SL 8 18.662 521.785 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OAI22x1_ASAP7_75t_SL 6 13.997 649.223 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OAI22xp5_ASAP7_75t_L 10 13.997 69.855 asap7sc7p5t_22b_OA_LVT_SS_170906 0 +OAI22xp5_ASAP7_75t_SL 232 324.726 10907.549 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OAI31xp33_ASAP7_75t_L 1 1.400 2.335 asap7sc7p5t_22b_OA_LVT_SS_170906 0 +OAI31xp33_ASAP7_75t_SL 22 30.793 794.563 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OAI31xp67_ASAP7_75t_SL 1 3.033 99.045 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OAI321xp33_ASAP7_75t_SL 1 1.866 55.568 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OAI322xp33_ASAP7_75t_SL 2 4.199 147.960 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OAI32xp33_ASAP7_75t_SL 3 4.899 148.817 asap7sc7p5t_22b_OA_SLVT_SS_170906 0 +OR2x2_ASAP7_75t_SL 75 104.976 6533.478 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +OR2x2_ASAP7_75t_SRAM 8 11.197 2.991 asap7sc7p5t_22b_SIMPLE_SRAM_SS_170906 0 +OR2x6_ASAP7_75t_SL 6 16.796 1434.304 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +OR3x1_ASAP7_75t_SL 6 8.398 341.524 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +OR3x1_ASAP7_75t_SRAM 1 1.400 0.194 asap7sc7p5t_22b_SIMPLE_SRAM_SS_170906 0 +OR3x4_ASAP7_75t_SL 1 2.100 132.639 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +OR4x1_ASAP7_75t_SL 2 3.266 113.791 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +OR5x1_ASAP7_75t_SL 3 5.599 237.648 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +SRAM1RW64x128 2 33552.261 0.000 SRAM1RW64x128_PVT_0P63V_100C 0 +SRAM2RW16x32 2 5544.960 0.000 SRAM2RW16x32_PVT_0P63V_100C 0 +TIEHIx1_ASAP7_75t_SL 3 2.100 0.006 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +TIELOx1_ASAP7_75t_SL 1220 853.805 3.593 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +XNOR2xp5_ASAP7_75t_L 2 4.199 21.193 asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 0 +XNOR2xp5_ASAP7_75t_SL 85 178.459 6974.848 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +XNOR2xp5_ASAP7_75t_SRAM 27 56.687 11.264 asap7sc7p5t_22b_SIMPLE_SRAM_SS_170906 0 +XOR2xp5_ASAP7_75t_SL 100 209.952 7575.836 asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 0 +XOR2xp5_ASAP7_75t_SRAM 21 44.090 7.575 asap7sc7p5t_22b_SIMPLE_SRAM_SS_170906 0 +-------------------------------------------------------------------------------------------------------------- +total 9616 56136.692 499518.295 + + + Leakage Leakage + Library Instances Instances % Area Power (nW) Power % +----------------------------------------------------------------------------------------- +SRAM1RW64x128_PVT_0P63V_100C 2 0.0 33552.261 0.000 0.0 +SRAM2RW16x32_PVT_0P63V_100C 2 0.0 5544.960 0.000 0.0 +asap7sc7p5t_22b_AO_LVT_SS_170906 249 2.6 560.339 4243.041 0.8 +asap7sc7p5t_22b_AO_SLVT_SS_170906 1957 20.4 3254.723 89879.913 18.0 +asap7sc7p5t_22b_AO_SRAM_SS_170906 23 0.2 33.359 7.742 0.0 +asap7sc7p5t_22b_INVBUF_LVT_SS_170906 163 1.7 127.604 877.389 0.2 +asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 1043 10.8 877.133 43157.714 8.6 +asap7sc7p5t_22b_OA_LVT_SS_170906 44 0.5 55.987 275.338 0.1 +asap7sc7p5t_22b_OA_SLVT_SS_170906 632 6.6 905.593 36542.388 7.3 +asap7sc7p5t_22b_OA_SRAM_SS_170906 28 0.3 45.956 16.503 0.0 +asap7sc7p5t_22b_SEQ_LVT_SS_170906 37 0.4 175.427 828.591 0.2 +asap7sc7p5t_22b_SEQ_RVT_SS_170906 45 0.5 189.890 193.828 0.0 +asap7sc7p5t_22b_SEQ_SLVT_SS_170906 1422 14.8 6474.686 205210.713 41.1 +asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 264 2.7 299.998 1536.823 0.3 +asap7sc7p5t_22b_SIMPLE_RVT_SS_170906 448 4.7 452.330 320.767 0.1 +asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 3200 33.3 3473.073 116405.519 23.3 +asap7sc7p5t_22b_SIMPLE_SRAM_SS_170906 57 0.6 113.374 22.024 0.0 + + Leakage Leakage + Type Instances Area Area % Power (nW) Power % +--------------------------------------------------------------------------- +timing_model 4 39097.221 69.6 0.000 0.0 +sequential 1461 6659.444 11.9 206044.975 41.2 +inverter 1001 760.026 1.4 29429.490 5.9 +buffer 205 244.711 0.4 14605.613 2.9 +clock_gating_integrated_cell 43 180.559 0.3 188.157 0.0 +logic 6902 9194.731 16.4 249250.059 49.9 +physical_cells 0 0.000 0.0 0.000 0.0 +--------------------------------------------------------------------------- +total 9616 56136.692 100.0 499518.295 100.0 + diff --git a/build/syn-rundir/reports/final_qor.rpt b/build/syn-rundir/reports/final_qor.rpt new file mode 100644 index 0000000..1d4d01a --- /dev/null +++ b/build/syn-rundir/reports/final_qor.rpt @@ -0,0 +1,105 @@ +============================================================ + Generated by: Genus(TM) Synthesis Solution 19.11-s087_1 + Generated on: Dec 14 2020 09:46:20 pm + Module: riscv_top + Library domain: PVT_0P63V_100C.setup_cond + Domain index: 0 + Technology libraries: asap7sc7p5t_22b_SIMPLE_RVT_SS_170906 1.0 + asap7sc7p5t_22b_SIMPLE_LVT_SS_170906 1.0 + asap7sc7p5t_22b_SIMPLE_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_SIMPLE_SRAM_SS_170906 1.0 + asap7sc7p5t_22b_AO_RVT_SS_170906 1.0 + asap7sc7p5t_22b_AO_LVT_SS_170906 1.0 + asap7sc7p5t_22b_AO_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_AO_SRAM_SS_170906 1.0 + asap7sc7p5t_22b_OA_RVT_SS_170906 1.0 + asap7sc7p5t_22b_OA_LVT_SS_170906 1.0 + asap7sc7p5t_22b_OA_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_OA_SRAM_SS_170906 1.0 + asap7sc7p5t_22b_SEQ_RVT_SS_170906 1.0 + asap7sc7p5t_22b_SEQ_LVT_SS_170906 1.0 + asap7sc7p5t_22b_SEQ_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_SEQ_SRAM_SS_170906 1.0 + asap7sc7p5t_22b_INVBUF_RVT_SS_170906 1.0 + asap7sc7p5t_22b_INVBUF_LVT_SS_170906 1.0 + asap7sc7p5t_22b_INVBUF_SLVT_SS_170906 1.0 + asap7sc7p5t_22b_INVBUF_SRAM_SS_170906 1.0 + SRAM1RW1024x8_PVT_0P63V_100C 0 + SRAM1RW128x46_PVT_0P63V_100C 0 + SRAM1RW128x48_PVT_0P63V_100C 0 + SRAM1RW128x8_PVT_0P63V_100C 0 + SRAM1RW256x128_PVT_0P63V_100C 0 + SRAM1RW256x32_PVT_0P63V_100C 0 + SRAM1RW256x46_PVT_0P63V_100C 0 + SRAM1RW256x48_PVT_0P63V_100C 0 + SRAM1RW256x8_PVT_0P63V_100C 0 + SRAM1RW32x50_PVT_0P63V_100C 0 + SRAM1RW512x128_PVT_0P63V_100C 0 + SRAM1RW512x32_PVT_0P63V_100C 0 + SRAM1RW512x8_PVT_0P63V_100C 0 + SRAM1RW64x128_PVT_0P63V_100C 0 + SRAM1RW64x32_PVT_0P63V_100C 0 + SRAM1RW64x34_PVT_0P63V_100C 0 + SRAM1RW64x8_PVT_0P63V_100C 0 + SRAM2RW128x16_PVT_0P63V_100C 0 + SRAM2RW128x32_PVT_0P63V_100C 0 + SRAM2RW128x4_PVT_0P63V_100C 0 + SRAM2RW128x8_PVT_0P63V_100C 0 + SRAM2RW16x16_PVT_0P63V_100C 0 + SRAM2RW16x32_PVT_0P63V_100C 0 + SRAM2RW16x4_PVT_0P63V_100C 0 + SRAM2RW16x8_PVT_0P63V_100C 0 + SRAM2RW32x16_PVT_0P63V_100C 0 + SRAM2RW32x22_PVT_0P63V_100C 0 + SRAM2RW32x32_PVT_0P63V_100C 0 + SRAM2RW32x39_PVT_0P63V_100C 0 + SRAM2RW32x4_PVT_0P63V_100C 0 + SRAM2RW32x8_PVT_0P63V_100C 0 + SRAM2RW64x16_PVT_0P63V_100C 0 + SRAM2RW64x32_PVT_0P63V_100C 0 + SRAM2RW64x4_PVT_0P63V_100C 0 + SRAM2RW64x8_PVT_0P63V_100C 0 + Operating conditions: PVT_0P63V_100C + Interconnect mode: global + Area mode: physical library +============================================================ + +Timing +-------- + + Analysis view Clock Period +--------------------------------------- +PVT_0P63V_100C.setup_view clk 900.0 + + + Analysis Cost Critical Violating + View Group Path Slack TNS Paths +------------------------------------------------------------------------- +PVT_0P63V_100C.setup_view cg_enable_group_clk 81.3 0.0 0 + clk 27.2 0.0 0 + default No paths 0.0 0 +------------------------------------------------------------------------- +Total -0.0 0 + + +Instance Count +-------------- +Leaf Instance Count 9616 +Physical Instance count 0 +Sequential Instance Count 1504 +Combinational Instance Count 8112 +Hierarchical Instance Count 96 + +Area +---- +Cell Area 56136.692 +Physical Cell Area 0.000 +Total Cell Area (Cell+Physical) 56136.692 +Net Area 7450.433 +Total Area (Cell+Physical+Net) 63587.125 + +Runtime 2.0 seconds +Elapsed Runtime 273 seconds +Genus peak memory usage 1091.00 +Innovus peak memory usage no_value +Hostname c125m-16.EECS.Berkeley.EDU diff --git a/build/syn-rundir/reports/final_time_PVT_0P63V_100C.setup_view.rpt b/build/syn-rundir/reports/final_time_PVT_0P63V_100C.setup_view.rpt new file mode 100644 index 0000000..c1c3aa3 --- /dev/null +++ b/build/syn-rundir/reports/final_time_PVT_0P63V_100C.setup_view.rpt @@ -0,0 +1,3683 @@ +============================================================ + Generated by: Genus(TM) Synthesis Solution 19.11-s087_1 + Generated on: Dec 14 2020 09:46:21 pm + Module: riscv_top + Operating conditions: PVT_0P63V_100C + Interconnect mode: global + Area mode: physical library +============================================================ + + +Path 1: MET (27 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 5 + Uncertainty:- 100 + Required Time:= 795 + Launch Clock:- 0 + Data Path:- 768 + Slack:= 27 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y R AND2x2_ASAP7_75t_SL 5 4.5 26 22 400 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y F INVx2_ASAP7_75t_L 3 2.9 17 13 413 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y F AND2x6_ASAP7_75t_SL 11 8.8 16 22 435 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y F AND2x4_ASAP7_75t_SL 12 7.6 18 20 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y F AND2x2_ASAP7_75t_L 7 3.7 19 24 479 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y R INVx1_ASAP7_75t_SL 3 1.8 22 13 492 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 0.7 16 10 502 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 1.4 34 18 520 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y F NAND4xp75_ASAP7_75t_SL 1 0.7 22 9 529 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.3 14 18 547 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.6 20 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1482__2346/Y - B->Y R NAND2xp5_ASAP7_75t_L 2 1.3 28 18 586 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1342__6161/Y - B->Y R OA21x2_ASAP7_75t_SL 1 1.2 12 17 603 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.1 13 8 611 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 1.7 23 13 624 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1311/Y - A->Y R BUFx2_ASAP7_75t_SL 3 2.5 16 18 642 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1310/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.2 9 6 648 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1299__5115/Y - A1->Y R AOI21x1_ASAP7_75t_SL 2 2.0 27 13 660 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1290__5122/Y - B->Y F NOR2x1_ASAP7_75t_L 2 1.3 18 14 674 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1273__6260/Y - A1->Y R AOI21xp5_ASAP7_75t_L 2 1.7 45 24 698 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1254__1881/Y - A1->Y F OAI21xp5_ASAP7_75t_L 1 1.1 29 20 718 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1247__2802/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 0.7 18 18 737 (-,-) + cpu/stage1/pcselmux/g934__3680/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.2 18 20 757 (-,-) + cpu/stage1/pcreg/g355__1705/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 39 10 768 (-,-) + cpu/stage1/pcreg/register_reg[15]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 768 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 2: MET (27 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 5 + Uncertainty:- 100 + Required Time:= 795 + Launch Clock:- 0 + Data Path:- 767 + Slack:= 27 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g217/Y - A1->Y F OA21x2_ASAP7_75t_SL 2 1.8 12 18 67 (-,-) + cpu/stage3/ldsel/g208/Y - A->Y R NAND3x1_ASAP7_75t_SL 1 1.0 22 10 77 (-,-) + cpu/stage3/ldsel/g205/Y - B->Y R OR2x6_ASAP7_75t_SL 8 6.8 16 21 98 (-,-) + cpu/stage3/ldselmux/g2442/Y - A->Y F INVx4_ASAP7_75t_SL 3 2.7 9 6 104 (-,-) + cpu/stage3/ldselmux/g2414/Y - B2->Y R OAI22x1_ASAP7_75t_SL 1 1.0 23 12 116 (-,-) + cpu/stage3/ldselmux/g2387/Y - B->Y R AND2x4_ASAP7_75t_SL 5 3.0 12 16 132 (-,-) + cpu/stage3/ldselmux/g2362/Y - A2->Y R AO21x2_ASAP7_75t_SL 7 4.0 24 21 153 (-,-) + cpu/stage3/ldselmux/g2338/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 1.0 24 14 167 (-,-) + cpu/stage3/ldselmux/g2323/Y - A->Y R NAND2x1_ASAP7_75t_SL 1 0.7 16 12 179 (-,-) + cpu/stage3/wbselmux/g1093/Y - A1->Y R AO21x2_ASAP7_75t_SL 3 1.6 18 16 194 (-,-) + cpu/stage2/rs2DataSel/g628/Y - A2->Y R AO21x2_ASAP7_75t_SL 9 5.4 30 25 220 (-,-) + cpu/stage2/branchcomp/g516/Y - A->Y R HB1xp67_ASAP7_75t_SL 1 1.1 19 19 239 (-,-) + cpu/stage2/branchcomp/g936/Y - A->Y R XNOR2xp5_ASAP7_75t_SL 1 0.7 22 13 252 (-,-) + cpu/stage2/branchcomp/g900/Y - A->Y F NAND4xp25_ASAP7_75t_SL 1 0.6 26 13 265 (-,-) + cpu/stage2/branchcomp/g895/Y - A->Y R NOR2xp33_ASAP7_75t_SL 1 1.0 35 18 283 (-,-) + cpu/stage2/branchcomp/g891/Y - A->Y R AND4x2_ASAP7_75t_SL 2 1.3 12 18 301 (-,-) + cpu/stage1/pcsel/g894__6260/Y - B->Y F NAND2xp5_ASAP7_75t_SL 2 1.6 28 13 314 (-,-) + cpu/stage1/pcsel/g883__9315/Y - B->Y R NAND2x1_ASAP7_75t_SL 1 1.7 26 16 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - A->Y F NOR2x2_ASAP7_75t_SL 2 1.9 16 11 341 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 1.7 17 10 351 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 5 5.3 13 18 369 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y F INVx3_ASAP7_75t_SL 6 3.8 12 8 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y F AND2x2_ASAP7_75t_SL 5 4.4 20 21 398 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y R INVx2_ASAP7_75t_L 3 2.9 20 14 412 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y R AND2x6_ASAP7_75t_SL 11 8.8 20 22 434 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y R AND2x4_ASAP7_75t_SL 12 7.6 24 21 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y R AND2x2_ASAP7_75t_L 7 3.7 25 26 482 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y F INVx1_ASAP7_75t_SL 3 1.8 19 12 493 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 505 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y F AOI21xp5_ASAP7_75t_SL 1 1.4 27 13 519 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y R NAND4xp75_ASAP7_75t_SL 1 0.7 19 11 530 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 1.3 16 16 546 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y R AO21x1_ASAP7_75t_L 2 1.6 26 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1502__1881/Y - B->Y F NOR2x1_ASAP7_75t_L 3 1.7 20 15 583 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1361__6783/Y - B->Y F OR2x2_ASAP7_75t_SL 2 1.7 11 19 601 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - A2->Y R OAI21x1_ASAP7_75t_SL 1 1.1 18 11 612 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y F AOI21x1_ASAP7_75t_SL 2 1.7 17 10 622 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - A1->Y R OAI21x1_ASAP7_75t_SL 3 2.8 35 19 641 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 2.4 27 16 656 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 1.6 19 11 667 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1257__7482/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 1.8 13 18 685 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1244__6783/Y - A1->Y F AOI21x1_ASAP7_75t_SL 2 1.8 25 10 695 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1236__5477/Y - A1->Y R OAI21x1_ASAP7_75t_SL 1 1.1 27 13 709 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1235__6417/Y - B->Y F XOR2xp5_ASAP7_75t_SL 1 0.7 20 11 720 (-,-) + cpu/stage1/pcselmux/g988__5526/Y - A2->Y F AO21x1_ASAP7_75t_SL 1 0.7 15 15 735 (-,-) + cpu/stage1/pcselmux/g961__6783/Y - B->Y F AO21x1_ASAP7_75t_L 2 1.2 15 22 757 (-,-) + cpu/stage1/pcreg/g362__7482/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 39 10 767 (-,-) + cpu/stage1/pcreg/register_reg[31]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 767 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 3: MET (28 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[29]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 5 + Uncertainty:- 100 + Required Time:= 795 + Launch Clock:- 0 + Data Path:- 767 + Slack:= 28 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y R AND2x2_ASAP7_75t_SL 5 4.5 26 22 400 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y F INVx2_ASAP7_75t_L 3 2.9 17 13 413 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y F AND2x6_ASAP7_75t_SL 11 8.8 16 22 435 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y F AND2x4_ASAP7_75t_SL 12 7.6 18 20 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y F AND2x2_ASAP7_75t_L 7 3.7 19 24 479 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y R INVx1_ASAP7_75t_SL 3 1.8 22 13 492 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 0.7 16 10 502 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 1.4 34 18 520 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y F NAND4xp75_ASAP7_75t_SL 1 0.7 22 9 529 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.3 14 18 547 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.6 20 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1482__2346/Y - B->Y R NAND2xp5_ASAP7_75t_L 2 1.3 28 18 586 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1342__6161/Y - B->Y R OA21x2_ASAP7_75t_SL 1 1.2 12 17 603 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.1 13 8 611 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 1.7 23 13 624 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - A1->Y F OAI21x1_ASAP7_75t_SL 3 2.8 25 13 637 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y R AOI21x1_ASAP7_75t_SL 3 2.4 32 16 654 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.6 16 10 664 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1257__7482/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 1.8 13 19 683 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1256/Y - A->Y R INVx1_ASAP7_75t_L 2 1.6 20 13 695 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1241__8428/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 1.0 22 12 707 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1238__5107/Y - B->Y F XOR2xp5_ASAP7_75t_SL 1 0.7 23 16 723 (-,-) + cpu/stage1/pcselmux/g989__6783/Y - A2->Y F AO21x1_ASAP7_75t_SL 1 0.7 15 16 739 (-,-) + cpu/stage1/pcselmux/g960__5526/Y - B->Y F AO21x1_ASAP7_75t_SL 2 1.2 15 18 757 (-,-) + cpu/stage1/pcreg/g350__5526/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 39 10 766 (-,-) + cpu/stage1/pcreg/register_reg[29]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 767 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 4: MET (29 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[23]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 5 + Uncertainty:- 100 + Required Time:= 795 + Launch Clock:- 0 + Data Path:- 766 + Slack:= 29 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y R AND2x2_ASAP7_75t_SL 5 4.5 26 22 400 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y F INVx2_ASAP7_75t_L 3 2.9 17 13 413 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y F AND2x6_ASAP7_75t_SL 11 8.8 16 22 435 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y F AND2x4_ASAP7_75t_SL 12 7.6 18 20 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y F AND2x2_ASAP7_75t_L 7 3.7 19 24 479 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y R INVx1_ASAP7_75t_SL 3 1.8 22 13 492 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 0.7 16 10 502 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 1.4 34 18 520 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y F NAND4xp75_ASAP7_75t_SL 1 0.7 22 9 529 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.3 14 18 547 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.6 20 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1482__2346/Y - B->Y R NAND2xp5_ASAP7_75t_L 2 1.3 28 18 586 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1342__6161/Y - B->Y R OA21x2_ASAP7_75t_SL 1 1.2 12 17 603 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.1 13 8 611 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 1.7 23 13 624 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - A1->Y F OAI21x1_ASAP7_75t_SL 3 2.8 25 13 637 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1280__3680/Y - A1->Y R AOI21x1_ASAP7_75t_SL 2 1.6 23 13 651 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1270__5477/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.3 34 20 671 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1255__5115/Y - A1->Y R AOI21xp5_ASAP7_75t_L 2 1.6 44 26 696 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1242__5526/Y - A1->Y F OAI21xp5_ASAP7_75t_L 1 1.1 29 20 716 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1239__6260/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 0.7 18 18 735 (-,-) + cpu/stage1/pcselmux/g933__6783/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.2 18 20 755 (-,-) + cpu/stage1/pcreg/g364__6161/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 39 10 766 (-,-) + cpu/stage1/pcreg/register_reg[23]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 766 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 5: MET (30 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 5 + Uncertainty:- 100 + Required Time:= 795 + Launch Clock:- 0 + Data Path:- 764 + Slack:= 30 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y R AND2x2_ASAP7_75t_SL 5 4.5 26 22 400 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y F INVx2_ASAP7_75t_L 3 2.9 17 13 413 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y F AND2x6_ASAP7_75t_SL 11 8.8 16 22 435 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y F AND2x4_ASAP7_75t_SL 12 7.6 18 20 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y F AND2x2_ASAP7_75t_L 7 3.7 19 24 479 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y R INVx1_ASAP7_75t_SL 3 1.8 22 13 492 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 0.7 16 10 502 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 1.4 34 18 520 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y F NAND4xp75_ASAP7_75t_SL 1 0.7 22 9 529 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.3 14 18 547 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.6 20 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1482__2346/Y - B->Y R NAND2xp5_ASAP7_75t_L 2 1.3 28 18 586 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1342__6161/Y - B->Y R OA21x2_ASAP7_75t_SL 1 1.2 12 17 603 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.1 13 8 611 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 1.7 23 13 624 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - A1->Y F OAI21x1_ASAP7_75t_SL 3 2.8 25 13 637 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1295/Y - A->Y R INVx1_ASAP7_75t_SL 2 1.6 21 13 651 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1288__1705/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 34 19 670 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1272__5107/Y - A1->Y R AOI21xp5_ASAP7_75t_L 2 1.6 44 26 695 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1253__6131/Y - A1->Y F OAI21xp5_ASAP7_75t_L 1 1.1 29 20 715 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1246__1617/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 0.7 18 18 734 (-,-) + cpu/stage1/pcselmux/g947__9315/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.2 18 20 754 (-,-) + cpu/stage1/pcreg/g360__1881/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 39 10 764 (-,-) + cpu/stage1/pcreg/register_reg[19]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 764 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 6: MET (32 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage3/csr/csr_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 9 + Uncertainty:- 100 + Required Time:= 791 + Launch Clock:- 0 + Data Path:- 759 + Slack:= 32 + +#-------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#-------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2423/Y - A->Y R INVx2_ASAP7_75t_SL 2 1.3 9 6 123 (-,-) + cpu/stage3/ldselmux/g2397/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 0.7 17 8 132 (-,-) + cpu/stage3/ldselmux/g2360/Y - A1->Y F OA21x2_ASAP7_75t_SL 2 2.1 13 20 151 (-,-) + cpu/stage3/ldselmux/g2359/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.5 14 9 160 (-,-) + cpu/stage3/ldselmux/g2312/Y - A1->Y F OAI221xp5_ASAP7_75t_SL 1 0.7 25 12 172 (-,-) + cpu/stage3/wbselmux/g1114/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 2.0 16 23 194 (-,-) + cpu/stage2/rs2DataSel/g560/Y - A2->Y R AOI21x1_ASAP7_75t_SL 1 1.5 22 13 207 (-,-) + cpu/stage2/rs2DataSel/g549/Y - A->Y F INVx3_ASAP7_75t_SL 10 6.9 21 13 220 (-,-) + cpu/stage2/bselmux/g579/Y - A->Y F AND2x2_ASAP7_75t_SL 1 1.0 9 17 238 (-,-) + cpu/stage2/bselmux/g556/Y - B->Y F OR2x6_ASAP7_75t_SL 89 48.7 64 47 285 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1724/Y - A->Y F XNOR2xp5_ASAP7_75t_SL 2 1.2 40 28 313 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1658/Y - B->Y R NOR2xp33_ASAP7_75t_L 2 1.2 51 29 342 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y - A1->Y R OA21x2_ASAP7_75t_SL 2 1.7 15 22 365 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A2->Y R OA21x2_ASAP7_75t_SL 3 2.2 17 18 382 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y F OAI321xp33_ASAP7_75t_SL 1 0.7 37 13 395 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y R INVx1_ASAP7_75t_SL 2 1.7 25 16 411 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 1.7 14 18 429 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 1.4 13 16 445 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y F NOR2xp67_ASAP7_75t_SL 1 0.7 17 8 453 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y F OR2x2_ASAP7_75t_SL 3 2.5 14 20 473 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y R AOI31xp67_ASAP7_75t_SL 3 2.4 33 16 489 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y F O2A1O1Ixp5_ASAP7_75t_SL 1 0.7 36 11 501 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y F OR2x2_ASAP7_75t_SL 3 2.2 14 23 523 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 1.3 11 17 541 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y R NAND2xp5_ASAP7_75t_L 2 1.3 29 15 556 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 0.7 38 11 567 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 0.7 33 19 586 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y F INVx1_ASAP7_75t_SL 3 2.1 23 14 600 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 2.2 14 21 621 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y R AOI21x1_ASAP7_75t_SL 2 1.6 23 12 633 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 1.7 15 18 651 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 1.6 14 16 668 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 1.6 14 16 684 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1504/Y - A2->Y R OA21x2_ASAP7_75t_SL 1 1.1 12 15 699 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1503/Y - B->Y R XOR2xp5_ASAP7_75t_SL 1 0.7 28 16 715 (-,-) + cpu/stage2/alu/g5521/Y - A2->Y R AO21x1_ASAP7_75t_L 2 1.2 19 21 736 (-,-) + cpu/g8/Y - A->Y R BUFx2_ASAP7_75t_SL 3 1.8 12 15 751 (-,-) + cpu/stage3/csr/g178/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 0.7 60 8 759 (-,-) + cpu/stage3/csr/csr_reg[31]/D - - F DFFHQNx1_ASAP7_75t_SL 1 - - 0 759 (-,-) +#-------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 7: MET (33 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 5 + Uncertainty:- 100 + Required Time:= 795 + Launch Clock:- 0 + Data Path:- 762 + Slack:= 33 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y R AND2x2_ASAP7_75t_SL 5 4.5 26 22 400 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y F INVx2_ASAP7_75t_L 3 2.9 17 13 413 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y F AND2x6_ASAP7_75t_SL 11 8.8 16 22 435 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y F AND2x4_ASAP7_75t_SL 12 7.6 18 20 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y F AND2x2_ASAP7_75t_L 7 3.7 19 24 479 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y R INVx1_ASAP7_75t_SL 3 1.8 22 13 492 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 0.7 16 10 502 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 1.4 34 18 520 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y F NAND4xp75_ASAP7_75t_SL 1 0.7 22 9 529 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.3 14 18 547 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.6 20 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1482__2346/Y - B->Y R NAND2xp5_ASAP7_75t_L 2 1.3 28 18 586 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1342__6161/Y - B->Y R OA21x2_ASAP7_75t_SL 1 1.2 12 17 603 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.1 13 8 611 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 1.7 23 13 624 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - A1->Y F OAI21x1_ASAP7_75t_SL 3 2.8 25 13 637 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y R AOI21x1_ASAP7_75t_SL 3 2.4 32 16 654 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.6 16 10 664 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1257__7482/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 1.8 13 19 683 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1244__6783/Y - A1->Y R AOI21x1_ASAP7_75t_SL 2 1.8 30 13 695 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1243/Y - A->Y F INVx1_ASAP7_75t_SL 1 1.0 15 8 704 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1237__2398/Y - B->Y F XOR2xp5_ASAP7_75t_SL 1 0.7 24 14 718 (-,-) + cpu/stage1/pcselmux/g987__8428/Y - A2->Y F AO21x1_ASAP7_75t_SL 1 0.7 15 16 734 (-,-) + cpu/stage1/pcselmux/g962__3680/Y - B->Y F AO21x1_ASAP7_75t_SL 2 1.2 15 18 752 (-,-) + cpu/stage1/pcreg/g349__8428/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 39 10 762 (-,-) + cpu/stage1/pcreg/register_reg[30]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 762 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 8: MET (34 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s2_to_s3_alu/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 759 + Slack:= 34 + +#-------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#-------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2423/Y - A->Y R INVx2_ASAP7_75t_SL 2 1.3 9 6 123 (-,-) + cpu/stage3/ldselmux/g2397/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 0.7 17 8 132 (-,-) + cpu/stage3/ldselmux/g2360/Y - A1->Y F OA21x2_ASAP7_75t_SL 2 2.1 13 20 151 (-,-) + cpu/stage3/ldselmux/g2359/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.5 14 9 160 (-,-) + cpu/stage3/ldselmux/g2312/Y - A1->Y F OAI221xp5_ASAP7_75t_SL 1 0.7 25 12 172 (-,-) + cpu/stage3/wbselmux/g1114/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 2.0 16 23 194 (-,-) + cpu/stage2/rs2DataSel/g560/Y - A2->Y R AOI21x1_ASAP7_75t_SL 1 1.5 22 13 207 (-,-) + cpu/stage2/rs2DataSel/g549/Y - A->Y F INVx3_ASAP7_75t_SL 10 6.9 21 13 220 (-,-) + cpu/stage2/bselmux/g579/Y - A->Y F AND2x2_ASAP7_75t_SL 1 1.0 9 17 238 (-,-) + cpu/stage2/bselmux/g556/Y - B->Y F OR2x6_ASAP7_75t_SL 89 48.7 64 47 285 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1724/Y - A->Y F XNOR2xp5_ASAP7_75t_SL 2 1.2 40 28 313 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1658/Y - B->Y R NOR2xp33_ASAP7_75t_L 2 1.2 51 29 342 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y - A1->Y R OA21x2_ASAP7_75t_SL 2 1.7 15 22 365 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A2->Y R OA21x2_ASAP7_75t_SL 3 2.2 17 18 382 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y F OAI321xp33_ASAP7_75t_SL 1 0.7 37 13 395 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y R INVx1_ASAP7_75t_SL 2 1.7 25 16 411 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 1.7 14 18 429 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 1.4 13 16 445 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y F NOR2xp67_ASAP7_75t_SL 1 0.7 17 8 453 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y F OR2x2_ASAP7_75t_SL 3 2.5 14 20 473 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y R AOI31xp67_ASAP7_75t_SL 3 2.4 33 16 489 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y F O2A1O1Ixp5_ASAP7_75t_SL 1 0.7 36 11 501 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y F OR2x2_ASAP7_75t_SL 3 2.2 14 23 523 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 1.3 11 17 541 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y R NAND2xp5_ASAP7_75t_L 2 1.3 29 15 556 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 0.7 38 11 567 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 0.7 33 19 586 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y F INVx1_ASAP7_75t_SL 3 2.1 23 14 600 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y F AO21x2_ASAP7_75t_SL 2 2.2 14 21 621 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y R AOI21x1_ASAP7_75t_SL 2 1.6 23 12 633 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 1.7 15 18 651 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 1.6 14 16 668 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y - A2->Y R OA21x2_ASAP7_75t_SL 2 1.6 14 16 684 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1504/Y - A2->Y R OA21x2_ASAP7_75t_SL 1 1.1 12 15 699 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1503/Y - B->Y R XOR2xp5_ASAP7_75t_SL 1 0.7 28 16 715 (-,-) + cpu/stage2/alu/g5521/Y - A2->Y R AO21x1_ASAP7_75t_L 2 1.2 19 21 736 (-,-) + cpu/g8/Y - A->Y R BUFx2_ASAP7_75t_SL 3 1.8 12 15 751 (-,-) + cpu/s2_to_s3_alu/g420__5477/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 0.7 55 8 759 (-,-) + cpu/s2_to_s3_alu/register_reg[31]/D - - F DFFHQNx1_ASAP7_75t_SL 1 - - 0 759 (-,-) +#-------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 9: MET (34 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[11]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[11]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 6 + Uncertainty:- 100 + Required Time:= 794 + Launch Clock:- 0 + Data Path:- 759 + Slack:= 34 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y R AND2x2_ASAP7_75t_SL 5 4.5 26 22 400 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y F INVx2_ASAP7_75t_L 3 2.9 17 13 413 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y F AND2x6_ASAP7_75t_SL 11 8.8 16 22 435 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y F AND2x4_ASAP7_75t_SL 12 7.6 18 20 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y F AND2x2_ASAP7_75t_L 7 3.7 19 24 479 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y R INVx1_ASAP7_75t_SL 3 1.8 22 13 492 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 0.7 16 10 502 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 1.4 34 18 520 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y F NAND4xp75_ASAP7_75t_SL 1 0.7 22 9 529 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.3 14 18 547 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.6 20 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1482__2346/Y - B->Y R NAND2xp5_ASAP7_75t_L 2 1.3 28 18 586 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1342__6161/Y - B->Y R OA21x2_ASAP7_75t_SL 1 1.2 12 17 603 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.1 13 8 611 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 1.7 23 13 624 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1311/Y - A->Y R BUFx2_ASAP7_75t_SL 3 2.5 16 18 642 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1302__4733/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 1.2 36 20 662 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1291__8246/Y - A1->Y R AOI21xp5_ASAP7_75t_L 2 1.7 45 27 689 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1271__2398/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 1.1 28 15 704 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1260__9315/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 0.7 18 18 722 (-,-) + cpu/stage1/pcselmux/g941__6131/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.1 17 20 742 (-,-) + cpu/stage1/pcreg/g377__8428/Y - B->Y R NOR2xp33_ASAP7_75t_L 1 0.7 28 17 759 (-,-) + cpu/stage1/pcreg/register_reg[11]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 759 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 10: MET (36 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 4 + Uncertainty:- 100 + Required Time:= 796 + Launch Clock:- 0 + Data Path:- 760 + Slack:= 36 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g217/Y - A1->Y F OA21x2_ASAP7_75t_SL 2 1.8 12 18 67 (-,-) + cpu/stage3/ldsel/g208/Y - A->Y R NAND3x1_ASAP7_75t_SL 1 1.0 22 10 77 (-,-) + cpu/stage3/ldsel/g205/Y - B->Y R OR2x6_ASAP7_75t_SL 8 6.8 16 21 98 (-,-) + cpu/stage3/ldselmux/g2442/Y - A->Y F INVx4_ASAP7_75t_SL 3 2.7 9 6 104 (-,-) + cpu/stage3/ldselmux/g2414/Y - B2->Y R OAI22x1_ASAP7_75t_SL 1 1.0 23 12 116 (-,-) + cpu/stage3/ldselmux/g2387/Y - B->Y R AND2x4_ASAP7_75t_SL 5 3.0 12 16 132 (-,-) + cpu/stage3/ldselmux/g2362/Y - A2->Y R AO21x2_ASAP7_75t_SL 7 4.0 24 21 153 (-,-) + cpu/stage3/ldselmux/g2338/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 1.0 24 14 167 (-,-) + cpu/stage3/ldselmux/g2323/Y - A->Y R NAND2x1_ASAP7_75t_SL 1 0.7 16 12 179 (-,-) + cpu/stage3/wbselmux/g1093/Y - A1->Y R AO21x2_ASAP7_75t_SL 3 1.6 18 16 194 (-,-) + cpu/stage2/rs2DataSel/g628/Y - A2->Y R AO21x2_ASAP7_75t_SL 9 5.4 30 25 220 (-,-) + cpu/stage2/branchcomp/g516/Y - A->Y R HB1xp67_ASAP7_75t_SL 1 1.1 19 19 239 (-,-) + cpu/stage2/branchcomp/g936/Y - A->Y R XNOR2xp5_ASAP7_75t_SL 1 0.7 22 13 252 (-,-) + cpu/stage2/branchcomp/g900/Y - A->Y F NAND4xp25_ASAP7_75t_SL 1 0.6 26 13 265 (-,-) + cpu/stage2/branchcomp/g895/Y - A->Y R NOR2xp33_ASAP7_75t_SL 1 1.0 35 18 283 (-,-) + cpu/stage2/branchcomp/g891/Y - A->Y R AND4x2_ASAP7_75t_SL 2 1.3 12 18 301 (-,-) + cpu/stage1/pcsel/g894__6260/Y - B->Y F NAND2xp5_ASAP7_75t_SL 2 1.6 28 13 314 (-,-) + cpu/stage1/pcsel/g883__9315/Y - B->Y R NAND2x1_ASAP7_75t_SL 1 1.7 26 16 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - A->Y F NOR2x2_ASAP7_75t_SL 2 1.9 16 11 341 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 1.7 17 10 351 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 5 5.3 13 18 369 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y F INVx3_ASAP7_75t_SL 6 3.8 12 8 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y F AND2x2_ASAP7_75t_SL 5 4.4 20 21 398 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y R INVx2_ASAP7_75t_L 3 2.9 20 14 412 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y R AND2x6_ASAP7_75t_SL 11 8.8 20 22 434 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y R AND2x4_ASAP7_75t_SL 12 7.6 24 21 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y R AND2x2_ASAP7_75t_L 7 3.7 25 26 482 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y F INVx1_ASAP7_75t_SL 3 1.8 19 12 493 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 505 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y F AOI21xp5_ASAP7_75t_SL 1 1.4 27 13 519 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y R NAND4xp75_ASAP7_75t_SL 1 0.7 19 11 530 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 1.3 16 16 546 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y R AO21x1_ASAP7_75t_L 2 1.6 26 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1502__1881/Y - B->Y F NOR2x1_ASAP7_75t_L 3 1.7 20 15 583 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1361__6783/Y - B->Y F OR2x2_ASAP7_75t_SL 2 1.7 11 19 601 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - A2->Y R OAI21x1_ASAP7_75t_SL 1 1.1 18 11 612 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y F AOI21x1_ASAP7_75t_SL 2 1.7 17 10 622 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - A1->Y R OAI21x1_ASAP7_75t_SL 3 2.8 35 19 641 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 2.4 27 16 656 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 1.6 19 11 667 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1263__2883/Y - B->Y F NOR2x1_ASAP7_75t_L 2 1.6 18 13 681 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1249__5122/Y - A1->Y R OAI21xp5_ASAP7_75t_L 1 1.0 35 17 698 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1240__4319/Y - B->Y R XNOR2xp5_ASAP7_75t_SL 1 0.7 26 15 713 (-,-) + cpu/stage1/pcselmux/g999__5115/Y - B->Y F NAND2xp5_ASAP7_75t_L 1 0.7 51 12 725 (-,-) + cpu/stage1/pcselmux/g932__5526/Y - A->Y R NAND2xp5_ASAP7_75t_L 2 1.2 34 25 750 (-,-) + cpu/stage1/pcreg/g352__3680/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 0.7 43 10 760 (-,-) + cpu/stage1/pcreg/register_reg[27]/D - - F DFFHQNx1_ASAP7_75t_SL 1 - - 0 760 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 11: MET (44 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[19]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[19]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 749 + Slack:= 44 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 6.2 34 26 403 (-,-) + cpu/stage1/regfile/g80960/Y - A->Y F INVx1_ASAP7_75t_L 3 1.6 20 15 418 (-,-) + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 4.9 141 64 483 (-,-) + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 2.0 63 26 509 (-,-) + cpu/stage1/regfile/g78528/Y - B->Y R NOR2xp33_ASAP7_75t_L 12 7.1 240 120 629 (-,-) + cpu/stage1/regfile/g77227/Y - B1->Y R AO222x2_ASAP7_75t_SL 1 0.7 20 56 685 (-,-) + cpu/stage1/regfile/g77007/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 0.7 38 11 696 (-,-) + cpu/stage1/regfile/g76922__1666/Y - A->Y R NAND5xp2_ASAP7_75t_SL 1 0.7 27 14 710 (-,-) + cpu/stage1/regfile/g76882__8246/Y - B->Y R AO21x1_ASAP7_75t_SL 1 0.6 12 13 723 (-,-) + cpu/stage1/data2sel_s1/g574__2346/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 0.7 19 17 740 (-,-) + cpu/s1_to_s2_rs2/g440__6131/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 0.7 56 9 749 (-,-) + cpu/s1_to_s2_rs2/register_reg[19]/D - - F DFFHQNx1_ASAP7_75t_SL 1 - - 0 749 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 12: MET (44 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[22]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 5 + Uncertainty:- 100 + Required Time:= 795 + Launch Clock:- 0 + Data Path:- 750 + Slack:= 44 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g217/Y - A1->Y F OA21x2_ASAP7_75t_SL 2 1.8 12 18 67 (-,-) + cpu/stage3/ldsel/g208/Y - A->Y R NAND3x1_ASAP7_75t_SL 1 1.0 22 10 77 (-,-) + cpu/stage3/ldsel/g205/Y - B->Y R OR2x6_ASAP7_75t_SL 8 6.8 16 21 98 (-,-) + cpu/stage3/ldselmux/g2442/Y - A->Y F INVx4_ASAP7_75t_SL 3 2.7 9 6 104 (-,-) + cpu/stage3/ldselmux/g2414/Y - B2->Y R OAI22x1_ASAP7_75t_SL 1 1.0 23 12 116 (-,-) + cpu/stage3/ldselmux/g2387/Y - B->Y R AND2x4_ASAP7_75t_SL 5 3.0 12 16 132 (-,-) + cpu/stage3/ldselmux/g2362/Y - A2->Y R AO21x2_ASAP7_75t_SL 7 4.0 24 21 153 (-,-) + cpu/stage3/ldselmux/g2338/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 1.0 24 14 167 (-,-) + cpu/stage3/ldselmux/g2323/Y - A->Y R NAND2x1_ASAP7_75t_SL 1 0.7 16 12 179 (-,-) + cpu/stage3/wbselmux/g1093/Y - A1->Y R AO21x2_ASAP7_75t_SL 3 1.6 18 16 194 (-,-) + cpu/stage2/rs2DataSel/g628/Y - A2->Y R AO21x2_ASAP7_75t_SL 9 5.4 30 25 220 (-,-) + cpu/stage2/branchcomp/g516/Y - A->Y R HB1xp67_ASAP7_75t_SL 1 1.1 19 19 239 (-,-) + cpu/stage2/branchcomp/g936/Y - A->Y R XNOR2xp5_ASAP7_75t_SL 1 0.7 22 13 252 (-,-) + cpu/stage2/branchcomp/g900/Y - A->Y F NAND4xp25_ASAP7_75t_SL 1 0.6 26 13 265 (-,-) + cpu/stage2/branchcomp/g895/Y - A->Y R NOR2xp33_ASAP7_75t_SL 1 1.0 35 18 283 (-,-) + cpu/stage2/branchcomp/g891/Y - A->Y R AND4x2_ASAP7_75t_SL 2 1.3 12 18 301 (-,-) + cpu/stage1/pcsel/g894__6260/Y - B->Y F NAND2xp5_ASAP7_75t_SL 2 1.6 28 13 314 (-,-) + cpu/stage1/pcsel/g883__9315/Y - B->Y R NAND2x1_ASAP7_75t_SL 1 1.7 26 16 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - A->Y F NOR2x2_ASAP7_75t_SL 2 1.9 16 11 341 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 1.7 17 10 351 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 5 5.3 13 18 369 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y F INVx3_ASAP7_75t_SL 6 3.8 12 8 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y F AND2x2_ASAP7_75t_SL 5 4.4 20 21 398 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y R INVx2_ASAP7_75t_L 3 2.9 20 14 412 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y R AND2x6_ASAP7_75t_SL 11 8.8 20 22 434 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y R AND2x4_ASAP7_75t_SL 12 7.6 24 21 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y R AND2x2_ASAP7_75t_L 7 3.7 25 26 482 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y F INVx1_ASAP7_75t_SL 3 1.8 19 12 493 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 505 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y F AOI21xp5_ASAP7_75t_SL 1 1.4 27 13 519 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y R NAND4xp75_ASAP7_75t_SL 1 0.7 19 11 530 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 1.3 16 16 546 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y R AO21x1_ASAP7_75t_L 2 1.6 26 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1502__1881/Y - B->Y F NOR2x1_ASAP7_75t_L 3 1.7 20 15 583 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1361__6783/Y - B->Y F OR2x2_ASAP7_75t_SL 2 1.7 11 19 601 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - A2->Y R OAI21x1_ASAP7_75t_SL 1 1.1 18 11 612 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y F AOI21x1_ASAP7_75t_SL 2 1.7 17 10 622 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - A1->Y R OAI21x1_ASAP7_75t_SL 3 2.8 35 19 641 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1280__3680/Y - A1->Y F AOI21x1_ASAP7_75t_SL 2 1.5 23 12 653 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1270__5477/Y - B->Y R NOR2xp33_ASAP7_75t_SL 2 1.3 42 22 675 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1255__5115/Y - A1->Y F AOI21xp5_ASAP7_75t_L 2 1.7 36 24 699 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1245__3680/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 0.7 21 20 719 (-,-) + cpu/stage1/pcselmux/g936__2802/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.2 18 21 740 (-,-) + cpu/stage1/pcreg/g378__5526/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 39 10 750 (-,-) + cpu/stage1/pcreg/register_reg[22]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 750 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 13: MET (45 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[9]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 12 + Uncertainty:- 100 + Required Time:= 788 + Launch Clock:- 0 + Data Path:- 743 + Slack:= 45 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y R AND2x2_ASAP7_75t_SL 5 4.5 26 22 400 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y F INVx2_ASAP7_75t_L 3 2.9 17 13 413 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y F AND2x6_ASAP7_75t_SL 11 8.8 16 22 435 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y F AND2x4_ASAP7_75t_SL 12 7.6 18 20 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y F AND2x2_ASAP7_75t_L 7 3.7 19 24 479 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y R INVx1_ASAP7_75t_SL 3 1.8 22 13 492 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 0.7 16 10 502 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 1.4 34 18 520 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y F NAND4xp75_ASAP7_75t_SL 1 0.7 22 9 529 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.3 14 18 547 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.6 20 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1482__2346/Y - B->Y R NAND2xp5_ASAP7_75t_L 2 1.3 28 18 586 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1342__6161/Y - B->Y R OA21x2_ASAP7_75t_SL 1 1.2 12 17 603 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.1 13 8 611 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 1.7 23 13 624 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1311/Y - A->Y R BUFx2_ASAP7_75t_SL 3 2.5 16 18 642 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1302__4733/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 1.2 36 20 662 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1301/Y - A->Y R INVxp67_ASAP7_75t_SL 1 0.7 20 13 675 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1293__6131/Y - B->Y F NAND2xp5_ASAP7_75t_L 1 1.1 23 14 689 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1286__2802/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 0.7 18 17 706 (-,-) + cpu/stage1/pcselmux/g931__8428/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.1 17 20 726 (-,-) + cpu/stage1/pcreg/g375__6260/Y - B->Y R NOR2xp33_ASAP7_75t_L 1 0.7 28 17 743 (-,-) + cpu/stage1/pcreg/register_reg[9]/D - - R DFFHQNx1_ASAP7_75t_L 1 - - 0 743 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 14: MET (46 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[10]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[10]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 12 + Uncertainty:- 100 + Required Time:= 788 + Launch Clock:- 0 + Data Path:- 743 + Slack:= 46 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g217/Y - A1->Y F OA21x2_ASAP7_75t_SL 2 1.8 12 18 67 (-,-) + cpu/stage3/ldsel/g208/Y - A->Y R NAND3x1_ASAP7_75t_SL 1 1.0 22 10 77 (-,-) + cpu/stage3/ldsel/g205/Y - B->Y R OR2x6_ASAP7_75t_SL 8 6.8 16 21 98 (-,-) + cpu/stage3/ldselmux/g2442/Y - A->Y F INVx4_ASAP7_75t_SL 3 2.7 9 6 104 (-,-) + cpu/stage3/ldselmux/g2414/Y - B2->Y R OAI22x1_ASAP7_75t_SL 1 1.0 23 12 116 (-,-) + cpu/stage3/ldselmux/g2387/Y - B->Y R AND2x4_ASAP7_75t_SL 5 3.0 12 16 132 (-,-) + cpu/stage3/ldselmux/g2362/Y - A2->Y R AO21x2_ASAP7_75t_SL 7 4.0 24 21 153 (-,-) + cpu/stage3/ldselmux/g2338/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 1.0 24 14 167 (-,-) + cpu/stage3/ldselmux/g2323/Y - A->Y R NAND2x1_ASAP7_75t_SL 1 0.7 16 12 179 (-,-) + cpu/stage3/wbselmux/g1093/Y - A1->Y R AO21x2_ASAP7_75t_SL 3 1.6 18 16 194 (-,-) + cpu/stage2/rs2DataSel/g628/Y - A2->Y R AO21x2_ASAP7_75t_SL 9 5.4 30 25 220 (-,-) + cpu/stage2/branchcomp/g516/Y - A->Y R HB1xp67_ASAP7_75t_SL 1 1.1 19 19 239 (-,-) + cpu/stage2/branchcomp/g936/Y - A->Y R XNOR2xp5_ASAP7_75t_SL 1 0.7 22 13 252 (-,-) + cpu/stage2/branchcomp/g900/Y - A->Y F NAND4xp25_ASAP7_75t_SL 1 0.6 26 13 265 (-,-) + cpu/stage2/branchcomp/g895/Y - A->Y R NOR2xp33_ASAP7_75t_SL 1 1.0 35 18 283 (-,-) + cpu/stage2/branchcomp/g891/Y - A->Y R AND4x2_ASAP7_75t_SL 2 1.3 12 18 301 (-,-) + cpu/stage1/pcsel/g894__6260/Y - B->Y F NAND2xp5_ASAP7_75t_SL 2 1.6 28 13 314 (-,-) + cpu/stage1/pcsel/g883__9315/Y - B->Y R NAND2x1_ASAP7_75t_SL 1 1.7 26 16 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - A->Y F NOR2x2_ASAP7_75t_SL 2 1.9 16 11 341 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 1.7 17 10 351 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 5 5.3 13 18 369 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y F INVx3_ASAP7_75t_SL 6 3.8 12 8 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y F AND2x2_ASAP7_75t_SL 5 4.4 20 21 398 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y R INVx2_ASAP7_75t_L 3 2.9 20 14 412 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y R AND2x6_ASAP7_75t_SL 11 8.8 20 22 434 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y R AND2x4_ASAP7_75t_SL 12 7.6 24 21 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y R AND2x2_ASAP7_75t_L 7 3.7 25 26 482 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y F INVx1_ASAP7_75t_SL 3 1.8 19 12 493 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 505 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y F AOI21xp5_ASAP7_75t_SL 1 1.4 27 13 519 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y R NAND4xp75_ASAP7_75t_SL 1 0.7 19 11 530 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 1.3 16 16 546 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y R AO21x1_ASAP7_75t_L 2 1.6 26 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1502__1881/Y - B->Y F NOR2x1_ASAP7_75t_L 3 1.7 20 15 583 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1361__6783/Y - B->Y F OR2x2_ASAP7_75t_SL 2 1.7 11 19 601 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - A2->Y R OAI21x1_ASAP7_75t_SL 1 1.1 18 11 612 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y F AOI21x1_ASAP7_75t_SL 2 1.7 17 10 622 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1311/Y - A->Y F BUFx2_ASAP7_75t_SL 3 2.4 12 17 640 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1302__4733/Y - B->Y R NOR2xp33_ASAP7_75t_L 2 1.2 45 23 663 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1291__8246/Y - A1->Y F AOI21xp5_ASAP7_75t_L 2 1.6 35 24 687 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1276__8428/Y - B->Y F XOR2xp5_ASAP7_75t_SL 1 0.7 26 18 704 (-,-) + cpu/stage1/pcselmux/g942__1881/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.1 17 22 726 (-,-) + cpu/stage1/pcreg/g376__4319/Y - B->Y R NOR2xp33_ASAP7_75t_L 1 0.7 28 17 742 (-,-) + cpu/stage1/pcreg/register_reg[10]/D - - R DFFHQNx1_ASAP7_75t_L 1 - - 0 743 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 15: MET (47 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[18]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[18]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 5 + Uncertainty:- 100 + Required Time:= 795 + Launch Clock:- 0 + Data Path:- 748 + Slack:= 47 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g217/Y - A1->Y F OA21x2_ASAP7_75t_SL 2 1.8 12 18 67 (-,-) + cpu/stage3/ldsel/g208/Y - A->Y R NAND3x1_ASAP7_75t_SL 1 1.0 22 10 77 (-,-) + cpu/stage3/ldsel/g205/Y - B->Y R OR2x6_ASAP7_75t_SL 8 6.8 16 21 98 (-,-) + cpu/stage3/ldselmux/g2442/Y - A->Y F INVx4_ASAP7_75t_SL 3 2.7 9 6 104 (-,-) + cpu/stage3/ldselmux/g2414/Y - B2->Y R OAI22x1_ASAP7_75t_SL 1 1.0 23 12 116 (-,-) + cpu/stage3/ldselmux/g2387/Y - B->Y R AND2x4_ASAP7_75t_SL 5 3.0 12 16 132 (-,-) + cpu/stage3/ldselmux/g2362/Y - A2->Y R AO21x2_ASAP7_75t_SL 7 4.0 24 21 153 (-,-) + cpu/stage3/ldselmux/g2338/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 1.0 24 14 167 (-,-) + cpu/stage3/ldselmux/g2323/Y - A->Y R NAND2x1_ASAP7_75t_SL 1 0.7 16 12 179 (-,-) + cpu/stage3/wbselmux/g1093/Y - A1->Y R AO21x2_ASAP7_75t_SL 3 1.6 18 16 194 (-,-) + cpu/stage2/rs2DataSel/g628/Y - A2->Y R AO21x2_ASAP7_75t_SL 9 5.4 30 25 220 (-,-) + cpu/stage2/branchcomp/g516/Y - A->Y R HB1xp67_ASAP7_75t_SL 1 1.1 19 19 239 (-,-) + cpu/stage2/branchcomp/g936/Y - A->Y R XNOR2xp5_ASAP7_75t_SL 1 0.7 22 13 252 (-,-) + cpu/stage2/branchcomp/g900/Y - A->Y F NAND4xp25_ASAP7_75t_SL 1 0.6 26 13 265 (-,-) + cpu/stage2/branchcomp/g895/Y - A->Y R NOR2xp33_ASAP7_75t_SL 1 1.0 35 18 283 (-,-) + cpu/stage2/branchcomp/g891/Y - A->Y R AND4x2_ASAP7_75t_SL 2 1.3 12 18 301 (-,-) + cpu/stage1/pcsel/g894__6260/Y - B->Y F NAND2xp5_ASAP7_75t_SL 2 1.6 28 13 314 (-,-) + cpu/stage1/pcsel/g883__9315/Y - B->Y R NAND2x1_ASAP7_75t_SL 1 1.7 26 16 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - A->Y F NOR2x2_ASAP7_75t_SL 2 1.9 16 11 341 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 1.7 17 10 351 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 5 5.3 13 18 369 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y F INVx3_ASAP7_75t_SL 6 3.8 12 8 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y F AND2x2_ASAP7_75t_SL 5 4.4 20 21 398 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y R INVx2_ASAP7_75t_L 3 2.9 20 14 412 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y R AND2x6_ASAP7_75t_SL 11 8.8 20 22 434 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y R AND2x4_ASAP7_75t_SL 12 7.6 24 21 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y R AND2x2_ASAP7_75t_L 7 3.7 25 26 482 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y F INVx1_ASAP7_75t_SL 3 1.8 19 12 493 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 505 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y F AOI21xp5_ASAP7_75t_SL 1 1.4 27 13 519 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y R NAND4xp75_ASAP7_75t_SL 1 0.7 19 11 530 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 1.3 16 16 546 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y R AO21x1_ASAP7_75t_L 2 1.6 26 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1502__1881/Y - B->Y F NOR2x1_ASAP7_75t_L 3 1.7 20 15 583 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1361__6783/Y - B->Y F OR2x2_ASAP7_75t_SL 2 1.7 11 19 601 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - A2->Y R OAI21x1_ASAP7_75t_SL 1 1.1 18 11 612 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y F AOI21x1_ASAP7_75t_SL 2 1.7 17 10 622 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - A1->Y R OAI21x1_ASAP7_75t_SL 3 2.8 35 19 641 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1295/Y - A->Y F INVx1_ASAP7_75t_SL 2 1.6 20 12 653 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1288__1705/Y - B->Y R NOR2xp33_ASAP7_75t_SL 2 1.2 40 20 673 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1272__5107/Y - A1->Y F AOI21xp5_ASAP7_75t_L 2 1.7 35 24 697 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1258__4733/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 0.7 21 19 716 (-,-) + cpu/stage1/pcselmux/g950__2346/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.2 18 21 737 (-,-) + cpu/stage1/pcreg/g359__6131/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 39 10 748 (-,-) + cpu/stage1/pcreg/register_reg[18]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 748 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 16: MET (49 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (F) cpu/stage1/pcreg/register_reg[14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 4 + Uncertainty:- 100 + Required Time:= 796 + Launch Clock:- 0 + Data Path:- 746 + Slack:= 49 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y R AND2x2_ASAP7_75t_SL 5 4.5 26 22 400 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y F INVx2_ASAP7_75t_L 3 2.9 17 13 413 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y F AND2x6_ASAP7_75t_SL 11 8.8 16 22 435 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y F AND2x4_ASAP7_75t_SL 12 7.6 18 20 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y F AND2x2_ASAP7_75t_L 7 3.7 19 24 479 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y R INVx1_ASAP7_75t_SL 3 1.8 22 13 492 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 0.7 16 10 502 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 1.4 34 18 520 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y F NAND4xp75_ASAP7_75t_SL 1 0.7 22 9 529 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.3 14 18 547 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.6 20 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1482__2346/Y - B->Y R NAND2xp5_ASAP7_75t_L 2 1.3 28 18 586 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1342__6161/Y - B->Y R OA21x2_ASAP7_75t_SL 1 1.2 12 17 603 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.1 13 8 611 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 1.7 23 13 624 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1311/Y - A->Y R BUFx2_ASAP7_75t_SL 3 2.5 16 18 642 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1310/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.2 9 6 648 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1299__5115/Y - A1->Y R AOI21x1_ASAP7_75t_SL 2 2.0 27 13 660 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1290__5122/Y - B->Y F NOR2x1_ASAP7_75t_L 2 1.3 18 14 674 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1273__6260/Y - A1->Y R AOI21xp5_ASAP7_75t_L 2 1.7 45 24 698 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1259__6161/Y - B->Y R XOR2xp5_ASAP7_75t_SL 1 0.7 23 19 717 (-,-) + cpu/stage1/pcselmux/g935__1617/Y - A2->Y R AO21x1_ASAP7_75t_L 2 1.2 22 20 737 (-,-) + cpu/stage1/pcreg/g357__8246/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 0.7 43 9 746 (-,-) + cpu/stage1/pcreg/register_reg[14]/D - - F DFFHQNx1_ASAP7_75t_SL 1 - - 0 746 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 17: MET (50 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[31]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[31]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 744 + Slack:= 50 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/fopt427/Y - A->Y R BUFx3_ASAP7_75t_L 18 10.4 42 32 412 (-,-) + cpu/stage1/nopselmux/g397__7410/Y - B->Y R AND2x4_ASAP7_75t_SL 44 24.7 64 42 453 (-,-) + cpu/stage1/regfile/g80975/Y - A->Y F INVx2_ASAP7_75t_L 19 9.8 50 36 489 (-,-) + cpu/stage1/regfile/g79809/Y - A->Y R NAND2xp5_ASAP7_75t_SL 4 2.0 58 27 516 (-,-) + cpu/stage1/regfile/g78530/Y - B->Y F NOR2xp33_ASAP7_75t_L 12 6.7 167 95 611 (-,-) + cpu/stage1/regfile/g77735/Y - B2->Y R AOI22xp5_ASAP7_75t_SL 1 0.7 66 33 644 (-,-) + cpu/stage1/regfile/g77155/Y - B->Y F NAND3xp33_ASAP7_75t_SL 1 0.7 33 13 657 (-,-) + cpu/stage1/regfile/g77082/Y - C->Y R AOI221xp5_ASAP7_75t_SL 1 0.7 36 21 678 (-,-) + cpu/stage1/regfile/g76997__1881/Y - A->Y F NAND5xp2_ASAP7_75t_SL 1 0.7 39 19 697 (-,-) + cpu/stage1/regfile/g76939__7098/Y - B->Y F AO21x1_ASAP7_75t_SL 1 0.6 10 19 716 (-,-) + cpu/stage1/data2sel_s1/g560__2802/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 18 734 (-,-) + cpu/s1_to_s2_rs2/g420__2883/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 744 (-,-) + cpu/s1_to_s2_rs2/register_reg[31]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 744 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 18: MET (51 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[17]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[17]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 5 + Uncertainty:- 100 + Required Time:= 795 + Launch Clock:- 0 + Data Path:- 744 + Slack:= 51 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y R AND2x2_ASAP7_75t_SL 5 4.5 26 22 400 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y F INVx2_ASAP7_75t_L 3 2.9 17 13 413 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y F AND2x6_ASAP7_75t_SL 11 8.8 16 22 435 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y F AND2x4_ASAP7_75t_SL 12 7.6 18 20 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y F AND2x2_ASAP7_75t_L 7 3.7 19 24 479 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y R INVx1_ASAP7_75t_SL 3 1.8 22 13 492 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 0.7 16 10 502 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 1.4 34 18 520 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y F NAND4xp75_ASAP7_75t_SL 1 0.7 22 9 529 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.3 14 18 547 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.6 20 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1482__2346/Y - B->Y R NAND2xp5_ASAP7_75t_L 2 1.3 28 18 586 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1342__6161/Y - B->Y R OA21x2_ASAP7_75t_SL 1 1.2 12 17 603 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.1 13 8 611 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 1.7 23 13 624 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - A1->Y F OAI21x1_ASAP7_75t_SL 3 2.8 25 13 637 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1295/Y - A->Y R INVx1_ASAP7_75t_SL 2 1.6 21 13 651 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1288__1705/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 34 19 670 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1287/Y - A->Y R INVxp67_ASAP7_75t_SL 1 0.7 20 12 682 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1277__5526/Y - B->Y F NAND2xp5_ASAP7_75t_L 1 1.1 21 14 696 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1266__1666/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 0.7 18 17 713 (-,-) + cpu/stage1/pcselmux/g954__5477/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.2 18 20 733 (-,-) + cpu/stage1/pcreg/g358__7098/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 39 10 744 (-,-) + cpu/stage1/pcreg/register_reg[17]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 744 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 19: MET (52 ps) Setup Check with Pin cpu/stage3/csr/csr_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage3/csr/csr_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 741 + Slack:= 52 + +#-------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#-------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2423/Y - A->Y R INVx2_ASAP7_75t_SL 2 1.3 9 6 123 (-,-) + cpu/stage3/ldselmux/g2397/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 0.7 17 8 132 (-,-) + cpu/stage3/ldselmux/g2360/Y - A1->Y F OA21x2_ASAP7_75t_SL 2 2.1 13 20 151 (-,-) + cpu/stage3/ldselmux/g2359/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.5 14 9 160 (-,-) + cpu/stage3/ldselmux/g2312/Y - A1->Y F OAI221xp5_ASAP7_75t_SL 1 0.7 25 12 172 (-,-) + cpu/stage3/wbselmux/g1114/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 2.0 16 23 194 (-,-) + cpu/stage2/rs2DataSel/g560/Y - A2->Y R AOI21x1_ASAP7_75t_SL 1 1.5 22 13 207 (-,-) + cpu/stage2/rs2DataSel/g549/Y - A->Y F INVx3_ASAP7_75t_SL 10 6.9 21 13 220 (-,-) + cpu/stage2/bselmux/g579/Y - A->Y F AND2x2_ASAP7_75t_SL 1 1.0 9 17 238 (-,-) + cpu/stage2/bselmux/g556/Y - B->Y F OR2x6_ASAP7_75t_SL 89 48.7 64 47 285 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1724/Y - A->Y R XNOR2xp5_ASAP7_75t_SL 2 1.2 43 23 308 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1658/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 1.2 48 27 335 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y - A1->Y F OA21x2_ASAP7_75t_SL 2 1.6 13 22 357 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A2->Y F OA21x2_ASAP7_75t_SL 3 2.1 14 19 376 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y R OAI321xp33_ASAP7_75t_SL 1 0.7 50 20 396 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y F INVx1_ASAP7_75t_SL 2 1.6 25 13 410 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 1.6 13 20 430 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 1.4 12 18 447 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y R NOR2xp67_ASAP7_75t_SL 1 0.7 19 9 456 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y R OR2x2_ASAP7_75t_SL 3 2.6 17 18 474 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y F AOI31xp67_ASAP7_75t_SL 3 2.3 36 17 491 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y R O2A1O1Ixp5_ASAP7_75t_SL 1 0.7 35 14 505 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y R OR2x2_ASAP7_75t_SL 3 2.1 14 19 524 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 1.3 11 16 539 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y F NAND2xp5_ASAP7_75t_L 2 1.3 24 13 552 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 0.7 42 17 570 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 0.7 24 13 582 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y R INVx1_ASAP7_75t_SL 3 2.2 27 16 598 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 2.1 15 19 617 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y F AOI21x1_ASAP7_75t_SL 2 1.7 18 10 628 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 1.6 13 19 647 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 1.7 13 18 665 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 1.7 13 18 683 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1505/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 0.7 23 16 699 (-,-) + cpu/stage2/alu/g5504/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.2 15 18 717 (-,-) + cpu/g9/Y - A->Y F BUFx2_ASAP7_75t_SL 3 1.8 10 16 732 (-,-) + cpu/stage3/csr/g191/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 52 9 741 (-,-) + cpu/stage3/csr/csr_reg[30]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 741 (-,-) +#-------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 20: MET (52 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[13]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[13]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 5 + Uncertainty:- 100 + Required Time:= 795 + Launch Clock:- 0 + Data Path:- 743 + Slack:= 52 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y R AND2x2_ASAP7_75t_SL 5 4.5 26 22 400 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y F INVx2_ASAP7_75t_L 3 2.9 17 13 413 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y F AND2x6_ASAP7_75t_SL 11 8.8 16 22 435 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y F AND2x4_ASAP7_75t_SL 12 7.6 18 20 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y F AND2x2_ASAP7_75t_L 7 3.7 19 24 479 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y R INVx1_ASAP7_75t_SL 3 1.8 22 13 492 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 0.7 16 10 502 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 1.4 34 18 520 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y F NAND4xp75_ASAP7_75t_SL 1 0.7 22 9 529 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.3 14 18 547 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.6 20 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1482__2346/Y - B->Y R NAND2xp5_ASAP7_75t_L 2 1.3 28 18 586 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1342__6161/Y - B->Y R OA21x2_ASAP7_75t_SL 1 1.2 12 17 603 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.1 13 8 611 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 1.7 23 13 624 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1311/Y - A->Y R BUFx2_ASAP7_75t_SL 3 2.5 16 18 642 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1310/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.2 9 6 648 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1299__5115/Y - A1->Y R AOI21x1_ASAP7_75t_SL 2 2.0 27 13 660 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1290__5122/Y - B->Y F NOR2x1_ASAP7_75t_L 2 1.3 18 14 674 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1289/Y - A->Y R INVx1_ASAP7_75t_SL 1 0.7 12 8 682 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1278__6783/Y - B->Y F NAND2xp5_ASAP7_75t_L 1 1.1 24 12 694 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1267__7410/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 0.7 18 18 712 (-,-) + cpu/stage1/pcselmux/g937__1705/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.2 18 20 732 (-,-) + cpu/stage1/pcreg/g354__2802/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 39 10 742 (-,-) + cpu/stage1/pcreg/register_reg[13]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 743 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 21: MET (52 ps) Setup Check with Pin cpu/s2_to_s3_alu/register_reg[30]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s2_to_s3_alu/register_reg[30]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 6 + Uncertainty:- 100 + Required Time:= 794 + Launch Clock:- 0 + Data Path:- 741 + Slack:= 52 + +#-------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#-------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2423/Y - A->Y R INVx2_ASAP7_75t_SL 2 1.3 9 6 123 (-,-) + cpu/stage3/ldselmux/g2397/Y - A1->Y F AOI21xp5_ASAP7_75t_SL 1 0.7 17 8 132 (-,-) + cpu/stage3/ldselmux/g2360/Y - A1->Y F OA21x2_ASAP7_75t_SL 2 2.1 13 20 151 (-,-) + cpu/stage3/ldselmux/g2359/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.5 14 9 160 (-,-) + cpu/stage3/ldselmux/g2312/Y - A1->Y F OAI221xp5_ASAP7_75t_SL 1 0.7 25 12 172 (-,-) + cpu/stage3/wbselmux/g1114/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 2.0 16 23 194 (-,-) + cpu/stage2/rs2DataSel/g560/Y - A2->Y R AOI21x1_ASAP7_75t_SL 1 1.5 22 13 207 (-,-) + cpu/stage2/rs2DataSel/g549/Y - A->Y F INVx3_ASAP7_75t_SL 10 6.9 21 13 220 (-,-) + cpu/stage2/bselmux/g579/Y - A->Y F AND2x2_ASAP7_75t_SL 1 1.0 9 17 238 (-,-) + cpu/stage2/bselmux/g556/Y - B->Y F OR2x6_ASAP7_75t_SL 89 48.7 64 47 285 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1724/Y - A->Y R XNOR2xp5_ASAP7_75t_SL 2 1.2 43 23 308 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1658/Y - B->Y F NOR2xp33_ASAP7_75t_L 2 1.2 48 27 335 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1581/Y - A1->Y F OA21x2_ASAP7_75t_SL 2 1.6 13 22 357 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1577/Y - A2->Y F OA21x2_ASAP7_75t_SL 3 2.1 14 19 376 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1575/Y - A1->Y R OAI321xp33_ASAP7_75t_SL 1 0.7 50 20 396 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1574/Y - A->Y F INVx1_ASAP7_75t_SL 2 1.6 25 13 410 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1570/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 1.6 13 20 430 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1568/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 1.4 12 18 447 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1566/Y - B->Y R NOR2xp67_ASAP7_75t_SL 1 0.7 19 9 456 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1563/Y - B->Y R OR2x2_ASAP7_75t_SL 3 2.6 17 18 474 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1556/Y - A1->Y F AOI31xp67_ASAP7_75t_SL 3 2.3 36 17 491 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1548/Y - A2->Y R O2A1O1Ixp5_ASAP7_75t_SL 1 0.7 35 14 505 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1546/Y - B->Y R OR2x2_ASAP7_75t_SL 3 2.1 14 19 524 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1543/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 1.3 11 16 539 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1539/Y - B->Y F NAND2xp5_ASAP7_75t_L 2 1.3 24 13 552 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1529/Y - A2->Y R O2A1O1Ixp33_ASAP7_75t_SL 1 0.7 42 17 570 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1526/Y - A2->Y F O2A1O1Ixp33_ASAP7_75t_SL 1 0.7 24 13 582 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1525/Y - A->Y R INVx1_ASAP7_75t_SL 3 2.2 27 16 598 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1521/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 2.1 15 19 617 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1516/Y - A1->Y F AOI21x1_ASAP7_75t_SL 2 1.7 18 10 628 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1513/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 1.6 13 19 647 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1510/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 1.7 13 18 665 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1507/Y - A2->Y F OA21x2_ASAP7_75t_SL 2 1.7 13 18 683 (-,-) + cpu/stage2/alu/sub_25_21_Y_add_24_21_g1505/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 0.7 23 16 699 (-,-) + cpu/stage2/alu/g5504/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.2 15 18 717 (-,-) + cpu/g9/Y - A->Y F BUFx2_ASAP7_75t_SL 3 1.8 10 16 732 (-,-) + cpu/s2_to_s3_alu/g434__7098/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 48 9 741 (-,-) + cpu/s2_to_s3_alu/register_reg[30]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 741 (-,-) +#-------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 22: MET (53 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[21]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 5 + Uncertainty:- 100 + Required Time:= 795 + Launch Clock:- 0 + Data Path:- 742 + Slack:= 53 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y R AND2x2_ASAP7_75t_SL 5 4.5 26 22 400 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y F INVx2_ASAP7_75t_L 3 2.9 17 13 413 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y F AND2x6_ASAP7_75t_SL 11 8.8 16 22 435 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y F AND2x4_ASAP7_75t_SL 12 7.6 18 20 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y F AND2x2_ASAP7_75t_L 7 3.7 19 24 479 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y R INVx1_ASAP7_75t_SL 3 1.8 22 13 492 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y F OAI21xp5_ASAP7_75t_SL 1 0.7 16 10 502 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y R AOI21xp5_ASAP7_75t_SL 1 1.4 34 18 520 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y F NAND4xp75_ASAP7_75t_SL 1 0.7 22 9 529 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.3 14 18 547 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.6 20 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1482__2346/Y - B->Y R NAND2xp5_ASAP7_75t_L 2 1.3 28 18 586 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1342__6161/Y - B->Y R OA21x2_ASAP7_75t_SL 1 1.2 12 17 603 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.1 13 8 611 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y R AOI21x1_ASAP7_75t_SL 2 1.7 23 13 624 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - A1->Y F OAI21x1_ASAP7_75t_SL 3 2.8 25 13 637 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1280__3680/Y - A1->Y R AOI21x1_ASAP7_75t_SL 2 1.6 23 13 651 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1270__5477/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.3 34 20 671 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1269/Y - A->Y R INVx1_ASAP7_75t_SL 1 0.7 16 10 681 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1261__9945/Y - B->Y F NAND2xp5_ASAP7_75t_L 1 1.1 22 13 694 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1250__8246/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 0.7 18 17 711 (-,-) + cpu/stage1/pcselmux/g940__7098/Y - A2->Y F AO21x1_ASAP7_75t_L 2 1.2 18 20 732 (-,-) + cpu/stage1/pcreg/g347__6260/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 39 10 742 (-,-) + cpu/stage1/pcreg/register_reg[21]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 742 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 23: MET (54 ps) Setup Check with Pin cpu/stage1/pcreg/register_reg[28]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/stage1/pcreg/register_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 5 + Uncertainty:- 100 + Required Time:= 795 + Launch Clock:- 0 + Data Path:- 740 + Slack:= 54 + +#---------------------------------------------------------------------------------------------------------------------------------------------------------- +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g217/Y - A1->Y F OA21x2_ASAP7_75t_SL 2 1.8 12 18 67 (-,-) + cpu/stage3/ldsel/g208/Y - A->Y R NAND3x1_ASAP7_75t_SL 1 1.0 22 10 77 (-,-) + cpu/stage3/ldsel/g205/Y - B->Y R OR2x6_ASAP7_75t_SL 8 6.8 16 21 98 (-,-) + cpu/stage3/ldselmux/g2442/Y - A->Y F INVx4_ASAP7_75t_SL 3 2.7 9 6 104 (-,-) + cpu/stage3/ldselmux/g2414/Y - B2->Y R OAI22x1_ASAP7_75t_SL 1 1.0 23 12 116 (-,-) + cpu/stage3/ldselmux/g2387/Y - B->Y R AND2x4_ASAP7_75t_SL 5 3.0 12 16 132 (-,-) + cpu/stage3/ldselmux/g2362/Y - A2->Y R AO21x2_ASAP7_75t_SL 7 4.0 24 21 153 (-,-) + cpu/stage3/ldselmux/g2338/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 1.0 24 14 167 (-,-) + cpu/stage3/ldselmux/g2323/Y - A->Y R NAND2x1_ASAP7_75t_SL 1 0.7 16 12 179 (-,-) + cpu/stage3/wbselmux/g1093/Y - A1->Y R AO21x2_ASAP7_75t_SL 3 1.6 18 16 194 (-,-) + cpu/stage2/rs2DataSel/g628/Y - A2->Y R AO21x2_ASAP7_75t_SL 9 5.4 30 25 220 (-,-) + cpu/stage2/branchcomp/g516/Y - A->Y R HB1xp67_ASAP7_75t_SL 1 1.1 19 19 239 (-,-) + cpu/stage2/branchcomp/g936/Y - A->Y R XNOR2xp5_ASAP7_75t_SL 1 0.7 22 13 252 (-,-) + cpu/stage2/branchcomp/g900/Y - A->Y F NAND4xp25_ASAP7_75t_SL 1 0.6 26 13 265 (-,-) + cpu/stage2/branchcomp/g895/Y - A->Y R NOR2xp33_ASAP7_75t_SL 1 1.0 35 18 283 (-,-) + cpu/stage2/branchcomp/g891/Y - A->Y R AND4x2_ASAP7_75t_SL 2 1.3 12 18 301 (-,-) + cpu/stage1/pcsel/g894__6260/Y - B->Y F NAND2xp5_ASAP7_75t_SL 2 1.6 28 13 314 (-,-) + cpu/stage1/pcsel/g883__9315/Y - B->Y R NAND2x1_ASAP7_75t_SL 1 1.7 26 16 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - A->Y F NOR2x2_ASAP7_75t_SL 2 1.9 16 11 341 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 1.7 17 10 351 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y R OR2x6_ASAP7_75t_SL 5 5.3 13 18 369 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y F INVx3_ASAP7_75t_SL 6 3.8 12 8 377 (-,-) + cpu/stage1/nopselmux/g416__6131/Y - B->Y F AND2x2_ASAP7_75t_SL 5 4.4 20 21 398 (-,-) + cpu/stage1/regfile/g80973/Y - A->Y R INVx2_ASAP7_75t_L 3 2.9 20 14 412 (-,-) + cpu/stage1/regfile/g80405/Y - B->Y R AND2x6_ASAP7_75t_SL 11 8.8 20 22 434 (-,-) + cpu/stage1/regfile/g79846/Y - B->Y R AND2x4_ASAP7_75t_SL 12 7.6 24 21 455 (-,-) + cpu/stage1/regfile/g78522/Y - B->Y R AND2x2_ASAP7_75t_L 7 3.7 25 26 482 (-,-) + cpu/stage1/regfile/g78457/Y - A->Y F INVx1_ASAP7_75t_SL 3 1.8 19 12 493 (-,-) + cpu/stage1/regfile/g77385/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 505 (-,-) + cpu/stage1/regfile/g77234/Y - B->Y F AOI21xp5_ASAP7_75t_SL 1 1.4 27 13 519 (-,-) + cpu/stage1/regfile/g76911__7098/Y - D->Y R NAND4xp75_ASAP7_75t_SL 1 0.7 19 11 530 (-,-) + cpu/stage1/data1sel_s1/g575__7410/Y - A2->Y R AO21x1_ASAP7_75t_SL 2 1.3 16 16 546 (-,-) + cpu/stage1/pcadder/g1267__8246/Y - A2->Y R AO21x1_ASAP7_75t_L 2 1.6 26 21 568 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1502__1881/Y - B->Y F NOR2x1_ASAP7_75t_L 3 1.7 20 15 583 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1361__6783/Y - B->Y F OR2x2_ASAP7_75t_SL 2 1.7 11 19 601 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1328__2802/Y - A2->Y R OAI21x1_ASAP7_75t_SL 1 1.1 18 11 612 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1312__1666/Y - B->Y F AOI21x1_ASAP7_75t_SL 2 1.7 17 10 622 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1297__1881/Y - A1->Y R OAI21x1_ASAP7_75t_SL 3 2.8 35 19 641 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1283__1617/Y - A1->Y F AOI21x1_ASAP7_75t_SL 3 2.4 27 16 656 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1275__4319/Y - B->Y R NOR2x1p5_ASAP7_75t_SL 2 1.6 19 11 667 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1257__7482/Y - A2->Y R AO21x2_ASAP7_75t_SL 2 1.8 13 18 685 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1256/Y - A->Y F INVx1_ASAP7_75t_L 2 1.7 16 11 696 (-,-) + cpu/stage1/pcadder/add_18_35_Y_add_17_34_Y_add_16_33_g1248__1705/Y - B->Y F XNOR2xp5_ASAP7_75t_SL 1 0.7 21 16 712 (-,-) + cpu/stage1/pcselmux/g944__7482/Y - A2->Y F AO21x1_ASAP7_75t_SL 2 1.2 18 18 730 (-,-) + cpu/stage1/pcreg/g367__2883/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 39 10 740 (-,-) + cpu/stage1/pcreg/register_reg[28]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 740 (-,-) +#---------------------------------------------------------------------------------------------------------------------------------------------------------- + + + +Path 24: MET (57 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[0]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[0]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 736 + Slack:= 57 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 6.2 34 26 403 (-,-) + cpu/stage1/regfile/g80960/Y - A->Y F INVx1_ASAP7_75t_L 3 1.6 20 15 418 (-,-) + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 4.9 141 64 483 (-,-) + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 2.0 63 26 509 (-,-) + cpu/stage1/regfile/g78529/Y - B->Y R NOR2xp33_ASAP7_75t_L 12 7.1 240 120 629 (-,-) + cpu/stage1/regfile/g77706/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 0.7 85 24 653 (-,-) + cpu/stage1/regfile/g77270/Y - A->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 37 23 676 (-,-) + cpu/stage1/regfile/g77100/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 0.7 36 13 689 (-,-) + cpu/stage1/regfile/g76887__7482/Y - B->Y R NAND5xp2_ASAP7_75t_SL 1 0.6 29 14 703 (-,-) + cpu/stage1/data2sel_s1/g557__6783/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 0.6 18 19 722 (-,-) + cpu/s1_to_s2_rs2/g449__2346/Y - B->Y F NOR2xp33_ASAP7_75t_SL 1 0.7 19 13 735 (-,-) + cpu/s1_to_s2_rs2/register_reg[0]/D - - F DFFHQNx1_ASAP7_75t_SL 1 - - 0 736 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 25: MET (60 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[3]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[3]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 733 + Slack:= 60 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 6.2 34 26 403 (-,-) + cpu/stage1/regfile/g80960/Y - A->Y F INVx1_ASAP7_75t_L 3 1.6 20 15 418 (-,-) + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 4.9 141 64 483 (-,-) + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 2.0 63 26 509 (-,-) + cpu/stage1/regfile/g78529/Y - B->Y R NOR2xp33_ASAP7_75t_L 12 7.1 240 120 629 (-,-) + cpu/stage1/regfile/g77677/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 0.7 85 24 653 (-,-) + cpu/stage1/regfile/g77267/Y - A->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 37 23 676 (-,-) + cpu/stage1/regfile/g77099/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 0.7 36 13 689 (-,-) + cpu/stage1/regfile/g76913__1881/Y - C->Y R NAND4xp25_ASAP7_75t_SL 1 0.6 31 15 704 (-,-) + cpu/stage1/data2sel_s1/g551__2398/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 0.7 19 20 724 (-,-) + cpu/s1_to_s2_rs2/g423__7410/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 0.7 56 9 733 (-,-) + cpu/s1_to_s2_rs2/register_reg[3]/D - - F DFFHQNx1_ASAP7_75t_SL 1 - - 0 733 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 26: MET (60 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[4]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[4]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 6 + Uncertainty:- 100 + Required Time:= 794 + Launch Clock:- 0 + Data Path:- 733 + Slack:= 60 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g550__5477/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.6 16 34 719 (-,-) + cpu/s1_to_s2_rs2/g435__2802/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 0.7 25 14 733 (-,-) + cpu/s1_to_s2_rs2/register_reg[4]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 733 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 27: MET (60 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[1]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[1]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 6 + Uncertainty:- 100 + Required Time:= 794 + Launch Clock:- 0 + Data Path:- 733 + Slack:= 60 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g556__5526/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.6 16 34 719 (-,-) + cpu/s1_to_s2_rs2/g448__2883/Y - B->Y R NOR2xp33_ASAP7_75t_SL 1 0.7 25 14 733 (-,-) + cpu/s1_to_s2_rs2/register_reg[1]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 733 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 28: MET (61 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[28]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[28]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 732 + Slack:= 61 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 6.2 34 26 403 (-,-) + cpu/stage1/regfile/g80960/Y - A->Y F INVx1_ASAP7_75t_L 3 1.6 20 15 418 (-,-) + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 4.9 141 64 483 (-,-) + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 2.0 63 26 509 (-,-) + cpu/stage1/regfile/g78529/Y - B->Y R NOR2xp33_ASAP7_75t_L 12 7.1 240 120 629 (-,-) + cpu/stage1/regfile/g77763/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 0.7 85 24 653 (-,-) + cpu/stage1/regfile/g77279/Y - A->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 37 23 676 (-,-) + cpu/stage1/regfile/g77103/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 0.7 36 13 689 (-,-) + cpu/stage1/regfile/g76888__4733/Y - B->Y R NAND5xp2_ASAP7_75t_SL 1 0.6 29 14 703 (-,-) + cpu/stage1/data2sel_s1/g546__2346/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 0.7 19 20 723 (-,-) + cpu/s1_to_s2_rs2/g447__9945/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 0.7 56 9 732 (-,-) + cpu/s1_to_s2_rs2/register_reg[28]/D - - F DFFHQNx1_ASAP7_75t_SL 1 - - 0 732 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 29: MET (61 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[27]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[27]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 732 + Slack:= 61 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 6.2 34 26 403 (-,-) + cpu/stage1/regfile/g80960/Y - A->Y F INVx1_ASAP7_75t_L 3 1.6 20 15 418 (-,-) + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 4.9 141 64 483 (-,-) + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 2.0 63 26 509 (-,-) + cpu/stage1/regfile/g78529/Y - B->Y R NOR2xp33_ASAP7_75t_L 12 7.1 240 120 629 (-,-) + cpu/stage1/regfile/g77769/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 0.7 85 24 653 (-,-) + cpu/stage1/regfile/g77280/Y - A->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 37 23 676 (-,-) + cpu/stage1/regfile/g77105/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 0.7 36 13 689 (-,-) + cpu/stage1/regfile/g76931__5526/Y - B->Y R NAND5xp2_ASAP7_75t_SL 1 0.6 28 14 703 (-,-) + cpu/stage1/data2sel_s1/g558__3680/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 0.7 19 19 722 (-,-) + cpu/s1_to_s2_rs2/g425__5477/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 0.7 56 9 732 (-,-) + cpu/s1_to_s2_rs2/register_reg[27]/D - - F DFFHQNx1_ASAP7_75t_SL 1 - - 0 732 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 30: MET (62 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[15]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (F) cpu/s1_to_s2_rs2/register_reg[15]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 731 + Slack:= 62 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt431/Y - A->Y R INVx3_ASAP7_75t_SL 6 3.8 16 10 377 (-,-) + cpu/stage1/nopselmux/g400__2398/Y - B->Y R AND2x2_ASAP7_75t_SL 11 6.2 34 26 403 (-,-) + cpu/stage1/regfile/g80960/Y - A->Y F INVx1_ASAP7_75t_L 3 1.6 20 15 418 (-,-) + cpu/stage1/regfile/g80398/Y - B->Y R NOR2xp33_ASAP7_75t_SL 8 4.9 141 64 483 (-,-) + cpu/stage1/regfile/g79809/Y - B->Y F NAND2xp5_ASAP7_75t_SL 4 2.0 63 26 509 (-,-) + cpu/stage1/regfile/g78529/Y - B->Y R NOR2xp33_ASAP7_75t_L 12 7.1 240 120 629 (-,-) + cpu/stage1/regfile/g77588/Y - A2->Y F AOI22xp5_ASAP7_75t_SL 1 0.7 85 24 653 (-,-) + cpu/stage1/regfile/g77262/Y - A->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 37 23 676 (-,-) + cpu/stage1/regfile/g77096/Y - C->Y F AOI221xp5_ASAP7_75t_SL 1 0.7 36 13 689 (-,-) + cpu/stage1/regfile/g76938__8246/Y - B->Y R NAND5xp2_ASAP7_75t_SL 1 0.6 24 14 703 (-,-) + cpu/stage1/data2sel_s1/g545__2883/Y - A2->Y R AO22x1_ASAP7_75t_SL 1 0.7 19 19 722 (-,-) + cpu/s1_to_s2_rs2/g450__1666/Y - B->Y F NAND2xp5_ASAP7_75t_SL 1 0.7 56 9 731 (-,-) + cpu/s1_to_s2_rs2/register_reg[15]/D - - F DFFHQNx1_ASAP7_75t_SL 1 - - 0 731 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 31: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[14]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[14]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g576__7410/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g437__5122/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[14]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 32: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[26]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[26]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g568__7482/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g446__9315/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[26]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 33: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[25]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[25]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g547__1666/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g430__8428/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[25]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 34: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[24]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[24]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g552__5107/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g445__6161/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[24]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 35: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[23]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[23]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g559__1617/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g444__4733/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[23]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 36: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[22]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[22]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g562__5122/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g443__7482/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[22]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 37: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[21]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[21]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g569__4733/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g442__5115/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[21]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 38: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[20]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[20]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g571__9315/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g441__1881/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[20]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 39: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[18]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[18]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g548__7410/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g439__7098/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[18]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 40: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[17]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[17]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g553__6260/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g438__8246/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[17]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 41: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[16]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[16]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g555__8428/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g436__1705/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[16]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 42: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[29]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[29]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g565__6131/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g421__2346/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[29]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 43: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[12]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[12]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g566__1881/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g433__3680/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[12]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 44: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[11]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[11]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g567__5115/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g432__6783/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[11]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 45: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[10]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[10]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g570__6161/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g431__5526/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[10]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 46: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[9]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[9]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g572__9945/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g429__4319/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[9]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 47: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[8]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[8]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g573__2883/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g428__6260/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[8]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 48: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[7]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[7]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g575__1666/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g427__5107/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[7]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 49: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[6]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[6]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g561__1705/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g426__2398/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[6]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + + + +Path 50: MET (63 ps) Setup Check with Pin cpu/s1_to_s2_rs2/register_reg[5]/CLK->D + View: PVT_0P63V_100C.setup_view + Group: clk + Startpoint: (R) cpu/s2_to_s3_inst/register_reg[14]/CLK + Clock: (R) clk + Endpoint: (R) cpu/s1_to_s2_rs2/register_reg[5]/D + Clock: (R) clk + + Capture Launch + Clock Edge:+ 900 0 + Src Latency:+ 0 0 + Net Latency:+ 0 (I) 0 (I) + Arrival:= 900 0 + + Setup:- 7 + Uncertainty:- 100 + Required Time:= 793 + Launch Clock:- 0 + Data Path:- 730 + Slack:= 63 + +#------------------------------------------------------------------------------------------------------------------------------ +# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance +# (fF) (ps) (ps) (ps) Location +#------------------------------------------------------------------------------------------------------------------------------ + cpu/s2_to_s3_inst/register_reg[14]/CLK - - R (arrival) 15 - 0 - 0 (-,-) + cpu/s2_to_s3_inst/register_reg[14]/QN - CLK->QN R DFFHQNx1_ASAP7_75t_L 1 1.1 22 40 40 (-,-) + cpu/stage3/ldsel/g226/Y - A->Y F INVx2_ASAP7_75t_SL 3 2.3 14 9 48 (-,-) + cpu/stage3/ldsel/g225/Y - A->Y R INVx2_ASAP7_75t_SL 1 1.2 10 7 55 (-,-) + cpu/stage3/ldsel/g214/Y - B->Y F OAI21x1_ASAP7_75t_SL 1 1.3 19 8 64 (-,-) + cpu/stage3/ldsel/g210/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.3 13 10 73 (-,-) + cpu/stage3/ldsel/g207/Y - A->Y F NOR2x1p5_ASAP7_75t_SL 1 1.7 13 9 82 (-,-) + cpu/stage3/ldsel/g206/Y - B->Y R NAND2x2_ASAP7_75t_SL 4 4.0 26 14 96 (-,-) + cpu/stage3/ldselmux/g2441/Y - A->Y F INVx2_ASAP7_75t_SL 1 1.0 11 6 101 (-,-) + cpu/stage3/ldselmux/g2427/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.6 11 15 117 (-,-) + cpu/stage3/ldselmux/g2416/Y - B->Y F AND2x4_ASAP7_75t_SL 4 3.3 10 15 132 (-,-) + cpu/stage3/ldselmux/g2365/Y - B->Y R NAND2x1p5_ASAP7_75t_SL 1 1.1 13 7 139 (-,-) + cpu/stage3/ldselmux/g2327/Y - A->Y R AND2x6_ASAP7_75t_SL 15 9.3 21 21 160 (-,-) + cpu/stage3/ldselmux/g2301/Y - A->Y F NAND2xp67_ASAP7_75t_SL 1 0.7 13 7 166 (-,-) + cpu/stage3/wbselmux/g1105/Y - A1->Y F AO21x2_ASAP7_75t_SL 3 1.6 15 19 185 (-,-) + cpu/stage2/rs2DataSel/g635/Y - A2->Y F AO21x2_ASAP7_75t_SL 8 5.7 26 26 212 (-,-) + cpu/stage2/branchcomp/lt_12_69_g877/Y - A->Y F HB1xp67_ASAP7_75t_L 1 0.7 12 21 233 (-,-) + cpu/stage2/branchcomp/lt_12_69_g756/Y - B2->Y R OAI22xp5_ASAP7_75t_L 1 1.1 36 20 252 (-,-) + cpu/stage2/branchcomp/lt_12_69_g734/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 16 8 261 (-,-) + cpu/stage2/branchcomp/lt_12_69_g727/Y - A2->Y R OAI21xp5_ASAP7_75t_SL 1 0.7 20 12 273 (-,-) + cpu/stage2/branchcomp/lt_12_69_g724/Y - A1->Y R AO21x1_ASAP7_75t_SL 1 1.1 14 15 288 (-,-) + cpu/stage2/branchcomp/lt_12_69_g723/Y - B->Y F AOI21x1_ASAP7_75t_SL 1 0.7 18 6 294 (-,-) + cpu/stage2/branchcomp/g922/Y - B2->Y F AO22x2_ASAP7_75t_SL 2 2.1 14 22 316 (-,-) + cpu/stage1/pcsel/g895__4319/Y - B->Y F AND2x4_ASAP7_75t_SL 2 2.2 11 14 330 (-,-) + cpu/stage1/pcsel/g878__1881/Y - B->Y R NOR2x2_ASAP7_75t_SL 2 1.9 15 8 338 (-,-) + cpu/stage1/pcsel/g871__2802/Y - B->Y F NOR2x1p5_ASAP7_75t_SL 2 1.7 14 8 346 (-,-) + cpu/stage1/nopsel/g464__5477/Y - A->Y F OR2x6_ASAP7_75t_SL 5 5.3 13 21 368 (-,-) + cpu/stage1/nopselmux/fopt430/Y - A->Y R INVx2_ASAP7_75t_SL 6 3.5 20 12 380 (-,-) + cpu/stage1/nopselmux/g410__2802/Y - B->Y R AND2x2_ASAP7_75t_L 4 2.2 17 22 401 (-,-) + cpu/stage1/g306/Y - A->Y R BUFx2_ASAP7_75t_SL 5 2.6 16 17 418 (-,-) + cpu/stage1/rs2DataSel_s1/g873/Y - B->Y F NOR2xp33_ASAP7_75t_SL 2 1.2 30 18 436 (-,-) + cpu/stage1/rs2DataSel_s1/g861/Y - B->Y R AOI31xp33_ASAP7_75t_SL 1 0.7 34 21 457 (-,-) + cpu/stage1/rs2DataSel_s1/g860/Y - A->Y F INVx1_ASAP7_75t_SL 1 0.6 14 7 463 (-,-) + cpu/stage1/rs2DataSel_s1/g857/Y - A2->Y F AO22x1_ASAP7_75t_SL 1 0.7 11 18 482 (-,-) + cpu/stage1/rs2DataSel_s1/g855/Y - A3->Y R AOI33xp33_ASAP7_75t_SL 1 0.7 43 20 501 (-,-) + cpu/stage1/rs2DataSel_s1/g854/Y - A->Y R AND4x1_ASAP7_75t_SL 33 15.1 153 87 589 (-,-) + cpu/stage1/data2sel_s1/g577/Y - A->Y F INVx1_ASAP7_75t_L 32 14.6 139 97 685 (-,-) + cpu/stage1/data2sel_s1/g549__6417/Y - A1->Y F AO22x1_ASAP7_75t_SL 1 0.7 17 34 720 (-,-) + cpu/s1_to_s2_rs2/g424__6417/Y - B->Y R NAND2xp5_ASAP7_75t_SL 1 0.7 49 10 730 (-,-) + cpu/s1_to_s2_rs2/register_reg[5]/D - - R DFFHQNx1_ASAP7_75t_SL 1 - - 0 730 (-,-) +#------------------------------------------------------------------------------------------------------------------------------ + +