RISC-V-Processor/par.yml at master · kkhus5/RISC-V-Processor · GitHub

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# Placement Constraints (standard cells, SRAMs)

# Source: hammer/src/hammer-vlsi/defaults.yml
# - Valid options:
#   - "r0"   (standard orientation)
#   - "r90"  (rotated 90 degrees clockwise) # NOT VALID
#   - "r180" (rotated 180 degrees)
#   - "r270" (rotated 270 degrees clockwise; equivalent to -90 degrees counterclockwise) # NOT VALID
#   - "mx"   (mirrored about the x-axis)
#   - "mx90" (mirrored about the x-axis, then rotated 90 degrees clockwise)
#   - "my"   (mirrored about the y-axis)
#   - "my90" (mirrored about the y-axis, then rotated 90 degrees clockwise)
# x (float) - x coordinate in um
# - Required for all types
# y (float) - y coordinate in um
# - Required for all types
# width (float) - width in um
# - Required for all types, but can be auto-filled for hierarchical and hardmacro if left blank
# height (float) - height in um
# - Required for all types, but can be auto-filled for hierarchical and hardmacro if left blank

  #   #SRAM1RW64x32
  # - path: "riscv_top/mem/icache/Cache_Tag"
  #   type: hardmacro
  #   x: 95
  #   y: 30
  #   orientation: "my"
  #   master: "SRAM1RW64x32"

  #   #SRAM1RW64x32
  # - path: "riscv_top/mem/dcache/Cache_Tag"
  #   type: hardmacro
  #   x: 250
  #   y: 30
  #   orientation: "r0"
  #   master: "SRAM1RW64x32"

  #   #SRAM1RW256x128
  # - path: "riscv_top/mem/icache/Cache_Data"
  #   type: hardmacro
  #   x: 50
  #   y: 120
  #   orientation: "my"
  #   master: "SRAM1RW256x128"

  #   #SRAM1RW256x128
  # - path: "riscv_top/mem/dcache/Cache_Data"
  #   type: hardmacro
  #   x: 250
  #   y: 120
  #   orientation: "r0"
  #   master: "SRAM1RW256x128"

vlsi.inputs.placement_constraints:
  - path: "riscv_top"
    type: toplevel

    # Set the floorplan margin
    margins:
      left:   0
      right:  0
      top:    0
      bottom: 0

    # Lower left corner coordinate of the top module
    x: 0
    y: 0

    # Floorplan dimensions
    width: &FP_WIDTH 350
    height: 400

    # Modify the path of the SRAMs according to your design
    # Add more hardmacro placement constraints if your design
    # uses more SRAMs
    # You can play around with different options of
    # orientations and locations to achieve good QoR

    #SRAM2RW16x32 - ICACHE TAG - A
  - path: "riscv_top/mem/icache/tag_valid_sram"
    type: hardmacro
    x: 95.04
    y: 14.04 #30.24
    orientation: "my"
    master: "SRAM2RW16x32"

    #SRAM2RW16x32 - DCACHE TAG - B
  - path: "riscv_top/mem/dcache/tag_valid_sram"
    type: hardmacro
    x: 264.6
    y: 9.72
    orientation: "r0"
    master: "SRAM2RW16x32"

    #SRAM1RW64x128 - ICACHE DATA - C
  - path: "riscv_top/mem/icache/data_sram"
    type: hardmacro
    x: 19.44
    y: 139.32 #119.88
    orientation: "my"
    master: "SRAM1RW64x128"

    #SRAM1RW64x128 - DCACHE DATA - D
  - path: "riscv_top/mem/dcache/data_sram"
    type: hardmacro
    x: 284.04
    y: 140.4 #129.6
    orientation: "r0"
    master: "SRAM1RW64x128"

  - path: "riscv_top/place_obs_bottom"
    type: obstruction
    obs_types: ["place"]
    x: 0
    y: 0
    width: *FP_WIDTH # must span across the whole floorplan
    height: 1.08 # 1 core site tall, necessary to avoid shorts

# Pin placement constraints
# Pins are placed at the bottom of the layout
vlsi.inputs.pin_mode: generated
vlsi.inputs.pin.generate_mode: semi_auto
vlsi.inputs.pin.assignments: [
  {pins: "*", layers: ["M5", "M7"], side: "bottom"}
]

# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
vlsi.inputs.power_spec_mode: "auto"
vlsi.inputs.power_spec_type: "cpf"

par.power_straps_mode: generate
par.generate_power_straps_method: by_tracks
par.blockage_spacing: 2.0
par.generate_power_straps_options:
  by_tracks:
    strap_layers:
      - M3
      - M4
      - M5
      - M6
      - M7
      - M8
      - M9
    pin_layers:
      - M9
    track_width: 7 # minimum allowed for M2 & M3
    track_spacing: 0
    track_spacing_M3: 1 # to avoid M2 shorts at higher density
    track_start: 10
    power_utilization: 0.25
    power_utilization_M8: 1.0
    power_utilization_M9: 1.0

# Clock Concurrent Optimization for CTS
par.innovus.use_cco: true

# Enable this option will let Innovus perform auto floorplan exploration.
# All the placement constraints specified above will be ignored.
# This might lead to poor QoR and more DRVs.

#par.innovus.floorplan_mode: auto