README.md

CaballoLoco Processor

The fastest processor whenever Will Smith is in the backstage.

This repository contains the System Verilog code for the CaballoLoco processor. The project is organized into several modules, each with its corresponding testbench. The objective of this project is to optimize the processor more and more to understand every optimization step.

Main Implementations

each of these has a dedicated folder

Single Cycle Processor: CaBalloSano - CBS

Name	Module	Testbench
Main Logic	mod	tb
Arithmetic Logic Unit	mod	tb
Comparator	mod	tb
Opcode Decoder	mod	tb
Register Bank	mod	tb
Register Mono	mod	tb
Register Bank Mono	mod	tb

Pipelined Processor: CaBalloLoco - CBL

Name	Module	Testbench
Main Logic	mod	tb
Arithmetic Logic Unit	mod	tb
Comparator	mod	tb
Forwarding Unit	mod	tb
Hazard Unit	mod	tb
Opcode Decoder	mod	tb
Pipes	mod	tb
Register Bank	mod	tb
Register Mono	mod	tb
Register Bank Mono	mod	tb

Pipelined Processor with memory: CaBalloDesquiciado - CBD

Name	Module	Testbench
Main Logic	mod	/
Arbiter	mod	tb
Data Cache	mod	tb
Data Memory	mod	/
Instruction Cache	mod	tb
Instruction Memory	mod	/
Store Buffer	mod	tb
Translation Lookaside Buffer	mod	tb

TODO

• Cache: Implement a cache memory.
• TLB: Implement a Translation Lookaside Buffer.
• Memory: Implement a memory module.
• Memory Arbiter: Implement a memory arbiter.
• Speculation: Implement branch and memory speculation.
• Multiple Issue: Implement multiple issue.

Folder Structure

Each implementation has its own folder with the following structure:

• mod/: Contains the source files for all the individual modules of the processor combined with the testbenches.
• pkg/: Contains the source files for all the packages used in the project.
• tc/: Contains the source files for all the testbenches.
• doc/: Contains documentation related to the project, such as design specifications, architectural diagrams, or any other relevant information. Here you will find schemas of the various implementations.
• Makefile: Icarus verilog Makefile.

TODO

• Shift Left (shl): Implement the shift left operation.
• Shift Right (shr): Implement the shift right operation.
• Memory: Implement the main memory.

Future Work

• Branch Speculation: Implement branch speculation to improve performance.
• Memory Speculation: Implement memory speculation.
• Multi-level Cache: Implement a multi-level cache hierarchy.
• Multiple Issue: Implement a multiple issue pipeline.