Fix bug where one-bit struct output ports improperly slice (#629)

Author: mkorbel1

lib/src/synthesizers/systemverilog/systemverilog_synthesis_result.dart

@@ -153,7 +153,7 @@ class SystemVerilogSynthesisResult extends SynthesisResult {
           ' bidirectional net connections.');
 
       var sliceString = '';
-      if (assignment is PartialSynthAssignment) {
+      if (assignment is PartialSynthAssignment && assignment.width > 1) {
         sliceString = assignment.dstUpperIndex == assignment.dstLowerIndex
             ? '[${assignment.dstUpperIndex}]'
             : '[${assignment.dstUpperIndex}:${assignment.dstLowerIndex}]';

lib/src/synthesizers/utilities/synth_assignment.dart

@@ -47,6 +47,9 @@ class SynthAssignment {
     assert(_checkWidths(), 'Signal width mismatch');
   }
 
+  /// The width of the assignment (of both the [src] and [dst]).
+  int get width => dst.width;
+
   @override
   String toString() => '$dst <= $src';
 }

test/bus_test.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2025 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // bus_test.dart
@@ -211,11 +211,35 @@ class ConstBusModule extends Module {
   }
 }
 
+class SingleBitBusSubsetMod extends Module {
+  SingleBitBusSubsetMod(Logic oneBit) {
+    oneBit = addInput('oneBit', oneBit);
+
+    addOutput('result') <= BusSubset(oneBit, 0, 0).subset;
+  }
+}
+
 void main() {
   tearDown(() async {
     await Simulator.reset();
   });
 
+  test('single-bit bus subset', () async {
+    final mod = SingleBitBusSubsetMod(Logic());
+    await mod.build();
+
+    final sv = mod.generateSynth();
+    expect(sv, contains('assign result = oneBit'));
+
+    final vectors = [
+      Vector({'oneBit': 0}, {'result': 0}),
+      Vector({'oneBit': 1}, {'result': 1}),
+    ];
+
+    await SimCompare.checkFunctionalVector(mod, vectors);
+    SimCompare.checkIverilogVector(mod, vectors);
+  });
+
   group('functional', () {
     test('NotGate bus', () async {
       final a = Logic(width: 8);

test/typed_port_test.dart

@@ -55,6 +55,22 @@ class SimpleStructModule extends Module {
   }
 }
 
+class OneBitStruct extends LogicStructure {
+  OneBitStruct({super.name = 'obs'}) : super([Logic(name: 'oneBit')]);
+
+  @override
+  OneBitStruct clone({String? name}) => OneBitStruct(name: name ?? this.name);
+}
+
+class ModuleWithOneBitStructPort extends Module {
+  ModuleWithOneBitStructPort(OneBitStruct inStruct) {
+    inStruct = addTypedInput('inStruct', inStruct);
+    final outStruct = addTypedOutput('outStruct', inStruct.clone);
+
+    outStruct.elements.first.gets(inStruct.elements.first);
+  }
+}
+
 class SimpleStructModuleContainer extends Module {
   SimpleStructModuleContainer(Logic a1, Logic a2,
       {super.name = 'simple_struct_mod_container', bool asNet = false}) {
@@ -408,4 +424,22 @@ void main() {
       });
     }
   });
+
+  test('single bit struct port partial assignment', () async {
+    final mod = ModuleWithOneBitStructPort(OneBitStruct());
+    await mod.build();
+
+    final sv = mod.generateSynth();
+
+    // no slicing on single-bit signals
+    expect(sv, contains('assign outStruct = outStruct_oneBit'));
+
+    final vectors = [
+      Vector({'inStruct': 0}, {'outStruct': 0}),
+      Vector({'inStruct': 1}, {'outStruct': 1}),
+    ];
+
+    await SimCompare.checkFunctionalVector(mod, vectors);
+    SimCompare.checkIverilogVector(mod, vectors);
+  });
 }