|
1 | 1 | { |
2 | 2 | "Header": { |
3 | 3 | "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", |
4 | | - "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.02", |
5 | | - "DatePublished": "10/16/2025", |
6 | | - "Version": "1.02", |
| 4 | + "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.03", |
| 5 | + "DatePublished": "11/14/2025", |
| 6 | + "Version": "1.03", |
7 | 7 | "Legend": "" |
8 | 8 | }, |
9 | 9 | "Events": [ |
|
3247 | 3247 | "PDISTCounter": "NA", |
3248 | 3248 | "Speculative": "1" |
3249 | 3249 | }, |
| 3250 | + { |
| 3251 | + "EventCode": "0x83", |
| 3252 | + "UMask": "0x08", |
| 3253 | + "UMaskExt": "0x00", |
| 3254 | + "EventName": "ICACHE_TAG.STALLS_ISB", |
| 3255 | + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache ISB-full", |
| 3256 | + "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache ISB-full", |
| 3257 | + "Counter": "0,1,2,3,4,5,6,7,8,9", |
| 3258 | + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", |
| 3259 | + "SampleAfterValue": "200003", |
| 3260 | + "MSRIndex": "0x00", |
| 3261 | + "MSRValue": "0x00", |
| 3262 | + "Precise": "0", |
| 3263 | + "CollectPEBSRecord": "2", |
| 3264 | + "TakenAlone": "0", |
| 3265 | + "CounterMask": "0", |
| 3266 | + "Invert": "0", |
| 3267 | + "EdgeDetect": "0", |
| 3268 | + "Data_LA": "0", |
| 3269 | + "L1_Hit_Indication": "0", |
| 3270 | + "Errata": "null", |
| 3271 | + "Offcore": "0", |
| 3272 | + "Deprecated": "0", |
| 3273 | + "Equal": "0", |
| 3274 | + "PDISTCounter": "NA", |
| 3275 | + "Speculative": "1" |
| 3276 | + }, |
| 3277 | + { |
| 3278 | + "EventCode": "0x83", |
| 3279 | + "UMask": "0x10", |
| 3280 | + "UMaskExt": "0x00", |
| 3281 | + "EventName": "ICACHE_TAG.STALLS_INUSE", |
| 3282 | + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache In use-full", |
| 3283 | + "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache In use-full", |
| 3284 | + "Counter": "0,1,2,3,4,5,6,7,8,9", |
| 3285 | + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", |
| 3286 | + "SampleAfterValue": "200003", |
| 3287 | + "MSRIndex": "0x00", |
| 3288 | + "MSRValue": "0x00", |
| 3289 | + "Precise": "0", |
| 3290 | + "CollectPEBSRecord": "2", |
| 3291 | + "TakenAlone": "0", |
| 3292 | + "CounterMask": "0", |
| 3293 | + "Invert": "0", |
| 3294 | + "EdgeDetect": "0", |
| 3295 | + "Data_LA": "0", |
| 3296 | + "L1_Hit_Indication": "0", |
| 3297 | + "Errata": "null", |
| 3298 | + "Offcore": "0", |
| 3299 | + "Deprecated": "0", |
| 3300 | + "Equal": "0", |
| 3301 | + "PDISTCounter": "NA", |
| 3302 | + "Speculative": "1" |
| 3303 | + }, |
3250 | 3304 | { |
3251 | 3305 | "EventCode": "0x87", |
3252 | 3306 | "UMask": "0x01", |
|
5871 | 5925 | "UMask": "0xfb", |
5872 | 5926 | "UMaskExt": "0x00", |
5873 | 5927 | "EventName": "BR_INST_RETIRED.NEAR_TAKEN", |
5874 | | - "BriefDescription": "Taken branch instructions retired.", |
| 5928 | + "BriefDescription": "Near Taken branch instructions retired.", |
5875 | 5929 | "PublicDescription": "Counts taken branch instructions retired.", |
5876 | 5930 | "Counter": "0,1,2,3,4,5,6,7,8,9", |
5877 | 5931 | "PEBScounters": "0,1,2,3,4,5,6,7,8,9", |
|
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