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[NFC][MC] Use [MC]Register in MachineVerifier
Differential Revision: https://reviews.llvm.org/D89815
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‎llvm/lib/CodeGen/MachineVerifier.cpp‎

Lines changed: 62 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -102,10 +102,10 @@ namespace {
102102
bool isFunctionRegBankSelected;
103103
bool isFunctionSelected;
104104

105-
using RegVector = SmallVector<unsigned, 16>;
105+
using RegVector = SmallVector<Register, 16>;
106106
using RegMaskVector = SmallVector<const uint32_t *, 4>;
107-
using RegSet = DenseSet<unsigned>;
108-
using RegMap = DenseMap<unsigned, const MachineInstr *>;
107+
using RegSet = DenseSet<Register>;
108+
using RegMap = DenseMap<Register, const MachineInstr *>;
109109
using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
110110

111111
const MachineInstr *FirstNonPHI;
@@ -120,10 +120,10 @@ namespace {
120120
SlotIndex lastIndex;
121121

122122
// Add Reg and any sub-registers to RV
123-
void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
123+
void addRegWithSubRegs(RegVector &RV, Register Reg) {
124124
RV.push_back(Reg);
125-
if (Register::isPhysicalRegister(Reg))
126-
for (const MCPhysReg &SubReg : TRI->subregs(Reg))
125+
if (Reg.isPhysical())
126+
for (const MCPhysReg &SubReg : TRI->subregs(Reg.asMCReg()))
127127
RV.push_back(SubReg);
128128
}
129129

@@ -159,8 +159,8 @@ namespace {
159159

160160
// Add register to vregsRequired if it belongs there. Return true if
161161
// anything changed.
162-
bool addRequired(unsigned Reg) {
163-
if (!Register::isVirtualRegister(Reg))
162+
bool addRequired(Register Reg) {
163+
if (!Reg.isVirtual())
164164
return false;
165165
if (regsLiveOut.count(Reg))
166166
return false;
@@ -170,7 +170,7 @@ namespace {
170170
// Same for a full set.
171171
bool addRequired(const RegSet &RS) {
172172
bool Changed = false;
173-
for (unsigned Reg : RS)
173+
for (Register Reg : RS)
174174
Changed |= addRequired(Reg);
175175
return Changed;
176176
}
@@ -184,21 +184,21 @@ namespace {
184184
}
185185

186186
// Live-out registers are either in regsLiveOut or vregsPassed.
187-
bool isLiveOut(unsigned Reg) const {
187+
bool isLiveOut(Register Reg) const {
188188
return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
189189
}
190190
};
191191

192192
// Extra register info per MBB.
193193
DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
194194

195-
bool isReserved(unsigned Reg) {
196-
return Reg < regsReserved.size() && regsReserved.test(Reg);
195+
bool isReserved(Register Reg) {
196+
return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id());
197197
}
198198

199-
bool isAllocatable(unsigned Reg) const {
200-
return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
201-
!regsReserved.test(Reg);
199+
bool isAllocatable(Register Reg) const {
200+
return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
201+
!regsReserved.test(Reg.id());
202202
}
203203

204204
// Analysis information if available
@@ -226,26 +226,27 @@ namespace {
226226
LLT MOVRegType = LLT{});
227227

228228
void report_context(const LiveInterval &LI) const;
229-
void report_context(const LiveRange &LR, unsigned VRegUnit,
229+
void report_context(const LiveRange &LR, Register VRegUnit,
230230
LaneBitmask LaneMask) const;
231231
void report_context(const LiveRange::Segment &S) const;
232232
void report_context(const VNInfo &VNI) const;
233233
void report_context(SlotIndex Pos) const;
234234
void report_context(MCPhysReg PhysReg) const;
235235
void report_context_liverange(const LiveRange &LR) const;
236236
void report_context_lanemask(LaneBitmask LaneMask) const;
237-
void report_context_vreg(unsigned VReg) const;
238-
void report_context_vreg_regunit(unsigned VRegOrUnit) const;
237+
void report_context_vreg(Register VReg) const;
238+
void report_context_vreg_regunit(Register VRegOrUnit) const;
239239

240240
void verifyInlineAsm(const MachineInstr *MI);
241241

242242
void checkLiveness(const MachineOperand *MO, unsigned MONum);
243243
void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
244-
SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
244+
SlotIndex UseIdx, const LiveRange &LR,
245+
Register VRegOrUnit,
245246
LaneBitmask LaneMask = LaneBitmask::getNone());
246247
void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
247-
SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
248-
bool SubRangeCheck = false,
248+
SlotIndex DefIdx, const LiveRange &LR,
249+
Register VRegOrUnit, bool SubRangeCheck = false,
249250
LaneBitmask LaneMask = LaneBitmask::getNone());
250251

251252
void markReachable(const MachineBasicBlock *MBB);
@@ -256,12 +257,12 @@ namespace {
256257
void verifyLiveVariables();
257258
void verifyLiveIntervals();
258259
void verifyLiveInterval(const LiveInterval&);
259-
void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
260+
void verifyLiveRangeValue(const LiveRange &, const VNInfo *, Register,
260261
LaneBitmask);
261-
void verifyLiveRangeSegment(const LiveRange&,
262-
const LiveRange::const_iterator I, unsigned,
262+
void verifyLiveRangeSegment(const LiveRange &,
263+
const LiveRange::const_iterator I, Register,
263264
LaneBitmask);
264-
void verifyLiveRange(const LiveRange&, unsigned,
265+
void verifyLiveRange(const LiveRange &, Register,
265266
LaneBitmask LaneMask = LaneBitmask::getNone());
266267

267268
void verifyStackFrame();
@@ -508,7 +509,7 @@ void MachineVerifier::report_context(const LiveInterval &LI) const {
508509
errs() << "- interval: " << LI << '\n';
509510
}
510511

511-
void MachineVerifier::report_context(const LiveRange &LR, unsigned VRegUnit,
512+
void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
512513
LaneBitmask LaneMask) const {
513514
report_context_liverange(LR);
514515
report_context_vreg_regunit(VRegUnit);
@@ -532,11 +533,11 @@ void MachineVerifier::report_context(MCPhysReg PReg) const {
532533
errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
533534
}
534535

535-
void MachineVerifier::report_context_vreg(unsigned VReg) const {
536+
void MachineVerifier::report_context_vreg(Register VReg) const {
536537
errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
537538
}
538539

539-
void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
540+
void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
540541
if (Register::isVirtualRegister(VRegOrUnit)) {
541542
report_context_vreg(VRegOrUnit);
542543
} else {
@@ -1958,8 +1959,10 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
19581959
}
19591960

19601961
void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
1961-
unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
1962-
LaneBitmask LaneMask) {
1962+
unsigned MONum, SlotIndex UseIdx,
1963+
const LiveRange &LR,
1964+
Register VRegOrUnit,
1965+
LaneBitmask LaneMask) {
19631966
LiveQueryResult LRQ = LR.Query(UseIdx);
19641967
// Check if we have a segment at the use, note however that we only need one
19651968
// live subregister range, the others may be dead.
@@ -1980,8 +1983,11 @@ void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
19801983
}
19811984

19821985
void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
1983-
unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
1984-
bool SubRangeCheck, LaneBitmask LaneMask) {
1986+
unsigned MONum, SlotIndex DefIdx,
1987+
const LiveRange &LR,
1988+
Register VRegOrUnit,
1989+
bool SubRangeCheck,
1990+
LaneBitmask LaneMask) {
19851991
if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
19861992
assert(VNI && "NULL valno is not allowed");
19871993
if (VNI->def != DefIdx) {
@@ -2025,7 +2031,7 @@ void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
20252031

20262032
void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
20272033
const MachineInstr *MI = MO->getParent();
2028-
const unsigned Reg = MO->getReg();
2034+
const Register Reg = MO->getReg();
20292035

20302036
// Both use and def operands can read a register.
20312037
if (MO->readsReg()) {
@@ -2043,8 +2049,9 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
20432049
if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
20442050
SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
20452051
// Check the cached regunit intervals.
2046-
if (Register::isPhysicalRegister(Reg) && !isReserved(Reg)) {
2047-
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
2052+
if (Reg.isPhysical() && !isReserved(Reg)) {
2053+
for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
2054+
++Units) {
20482055
if (MRI->isReservedRegUnit(*Units))
20492056
continue;
20502057
if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
@@ -2190,9 +2197,9 @@ void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
21902197
// Kill any masked registers.
21912198
while (!regMasks.empty()) {
21922199
const uint32_t *Mask = regMasks.pop_back_val();
2193-
for (unsigned Reg : regsLive)
2194-
if (Register::isPhysicalRegister(Reg) &&
2195-
MachineOperand::clobbersPhysReg(Mask, Reg))
2200+
for (Register Reg : regsLive)
2201+
if (Reg.isPhysical() &&
2202+
MachineOperand::clobbersPhysReg(Mask, Reg.asMCReg()))
21962203
regsDead.push_back(Reg);
21972204
}
21982205
set_subtract(regsLive, regsDead); regsDead.clear();
@@ -2225,21 +2232,21 @@ struct VRegFilter {
22252232
// Add elements to the filter itself. \pre Input set \p FromRegSet must have
22262233
// no duplicates. Both virtual and physical registers are fine.
22272234
template <typename RegSetT> void add(const RegSetT &FromRegSet) {
2228-
SmallVector<unsigned, 0> VRegsBuffer;
2235+
SmallVector<Register, 0> VRegsBuffer;
22292236
filterAndAdd(FromRegSet, VRegsBuffer);
22302237
}
22312238
// Filter \p FromRegSet through the filter and append passed elements into \p
22322239
// ToVRegs. All elements appended are then added to the filter itself.
22332240
// \returns true if anything changed.
22342241
template <typename RegSetT>
22352242
bool filterAndAdd(const RegSetT &FromRegSet,
2236-
SmallVectorImpl<unsigned> &ToVRegs) {
2243+
SmallVectorImpl<Register> &ToVRegs) {
22372244
unsigned SparseUniverse = Sparse.size();
22382245
unsigned NewSparseUniverse = SparseUniverse;
22392246
unsigned NewDenseSize = Dense.size();
22402247
size_t Begin = ToVRegs.size();
2241-
for (unsigned Reg : FromRegSet) {
2242-
if (!Register::isVirtualRegister(Reg))
2248+
for (Register Reg : FromRegSet) {
2249+
if (!Reg.isVirtual())
22432250
continue;
22442251
unsigned Index = Register::virtReg2Index(Reg);
22452252
if (Index < SparseUniverseMax) {
@@ -2263,7 +2270,7 @@ struct VRegFilter {
22632270
Sparse.resize(NewSparseUniverse);
22642271
Dense.reserve(NewDenseSize);
22652272
for (unsigned I = Begin; I < End; ++I) {
2266-
unsigned Reg = ToVRegs[I];
2273+
Register Reg = ToVRegs[I];
22672274
unsigned Index = Register::virtReg2Index(Reg);
22682275
if (Index < SparseUniverseMax)
22692276
Sparse.set(Index);
@@ -2296,7 +2303,7 @@ struct VRegFilter {
22962303
// universe). filter_b implicitly contains all physical registers at all times.
22972304
class FilteringVRegSet {
22982305
VRegFilter Filter;
2299-
SmallVector<unsigned, 0> VRegs;
2306+
SmallVector<Register, 0> VRegs;
23002307

23012308
public:
23022309
// Set-up the filter_b. \pre Input register set \p RS must have no duplicates.
@@ -2474,7 +2481,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
24742481
// Check for killed virtual registers that should be live out.
24752482
for (const auto &MBB : *MF) {
24762483
BBInfo &MInfo = MBBInfoMap[&MBB];
2477-
for (unsigned VReg : MInfo.vregsRequired)
2484+
for (Register VReg : MInfo.vregsRequired)
24782485
if (MInfo.regsKilled.count(VReg)) {
24792486
report("Virtual register killed in block, but needed live out.", &MBB);
24802487
errs() << "Virtual register " << printReg(VReg)
@@ -2484,7 +2491,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
24842491

24852492
if (!MF->empty()) {
24862493
BBInfo &MInfo = MBBInfoMap[&MF->front()];
2487-
for (unsigned VReg : MInfo.vregsRequired) {
2494+
for (Register VReg : MInfo.vregsRequired) {
24882495
report("Virtual register defs don't dominate all uses.", MF);
24892496
report_context_vreg(VReg);
24902497
}
@@ -2543,8 +2550,8 @@ void MachineVerifier::visitMachineFunctionAfter() {
25432550

25442551
void MachineVerifier::verifyLiveVariables() {
25452552
assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
2546-
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
2547-
unsigned Reg = Register::index2VirtReg(i);
2553+
for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2554+
Register Reg = Register::index2VirtReg(I);
25482555
LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
25492556
for (const auto &MBB : *MF) {
25502557
BBInfo &MInfo = MBBInfoMap[&MBB];
@@ -2569,8 +2576,8 @@ void MachineVerifier::verifyLiveVariables() {
25692576

25702577
void MachineVerifier::verifyLiveIntervals() {
25712578
assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
2572-
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
2573-
unsigned Reg = Register::index2VirtReg(i);
2579+
for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2580+
Register Reg = Register::index2VirtReg(I);
25742581

25752582
// Spilling and splitting may leave unused registers around. Skip them.
25762583
if (MRI->reg_nodbg_empty(Reg))
@@ -2594,7 +2601,7 @@ void MachineVerifier::verifyLiveIntervals() {
25942601
}
25952602

25962603
void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
2597-
const VNInfo *VNI, unsigned Reg,
2604+
const VNInfo *VNI, Register Reg,
25982605
LaneBitmask LaneMask) {
25992606
if (VNI->isUnused())
26002607
return;
@@ -2687,8 +2694,8 @@ void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
26872694

26882695
void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
26892696
const LiveRange::const_iterator I,
2690-
unsigned Reg, LaneBitmask LaneMask)
2691-
{
2697+
Register Reg,
2698+
LaneBitmask LaneMask) {
26922699
const LiveRange::Segment &S = *I;
26932700
const VNInfo *VNI = S.valno;
26942701
assert(VNI && "Live segment has no valno");
@@ -2899,7 +2906,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
28992906
}
29002907
}
29012908

2902-
void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
2909+
void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg,
29032910
LaneBitmask LaneMask) {
29042911
for (const VNInfo *VNI : LR.valnos)
29052912
verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
@@ -2909,7 +2916,7 @@ void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
29092916
}
29102917

29112918
void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
2912-
unsigned Reg = LI.reg();
2919+
Register Reg = LI.reg();
29132920
assert(Register::isVirtualRegister(Reg));
29142921
verifyLiveRange(LI, Reg);
29152922

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